SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/radeon_device.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/console.h>
  29 #include <drm/drmP.h>
  30 #include <drm/drm_crtc_helper.h>
  31 #include <drm/radeon_drm.h>
  32 #include <linux/vgaarb.h>
  33 #include "radeon_reg.h"
  34 #include "radeon.h"
  35 #include "radeon_asic.h"
  36 #include "atom.h"
  37
  38 /*
  39  * Clear GPU surface registers.
  40  */
  41 void radeon_surface_init(struct radeon_device *rdev)
  42 {
  43         /* FIXME: check this out */
  44         if (rdev->family < CHIP_R600) {
  45                 int i;
  46
  47                 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
  48                         if (rdev->surface_regs[i].bo)
  49                                 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
  50                         else
  51                                 radeon_clear_surface_reg(rdev, i);
  52                 }
  53                 /* enable surfaces */
  54                 WREG32(RADEON_SURFACE_CNTL, 0);
  55         }
  56 }
  57
  58 /*
  59  * GPU scratch registers helpers function.
  60  */
  61 void radeon_scratch_init(struct radeon_device *rdev)
  62 {
  63         int i;
  64
  65         /* FIXME: check this out */
  66         if (rdev->family < CHIP_R300) {
  67                 rdev->scratch.num_reg = 5;
  68         } else {
  69                 rdev->scratch.num_reg = 7;
  70         }
  71         for (i = 0; i < rdev->scratch.num_reg; i++) {
  72                 rdev->scratch.free[i] = true;
  73                 rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4);
  74         }
  75 }
  76
  77 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
  78 {
  79         int i;
  80
  81         for (i = 0; i < rdev->scratch.num_reg; i++) {
  82                 if (rdev->scratch.free[i]) {
  83                         rdev->scratch.free[i] = false;
  84                         *reg = rdev->scratch.reg[i];
  85                         return 0;
  86                 }
  87         }
  88         return -EINVAL;
  89 }
  90
  91 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
  92 {
  93         int i;
  94
  95         for (i = 0; i < rdev->scratch.num_reg; i++) {
  96                 if (rdev->scratch.reg[i] == reg) {
  97                         rdev->scratch.free[i] = true;
  98                         return;
  99                 }
 100         }
 101 }
 102
 103 /*
 104  * MC common functions
 105  */
 106 int radeon_mc_setup(struct radeon_device *rdev)
 107 {
 108         uint32_t tmp;
 109
 110         /* Some chips have an "issue" with the memory controller, the
 111          * location must be aligned to the size. We just align it down,
 112          * too bad if we walk over the top of system memory, we don't
 113          * use DMA without a remapped anyway.
 114          * Affected chips are rv280, all r3xx, and all r4xx, but not IGP
 115          */
 116         /* FGLRX seems to setup like this, VRAM a 0, then GART.
 117          */
 118         /*
 119          * Note: from R6xx the address space is 40bits but here we only
 120          * use 32bits (still have to see a card which would exhaust 4G
 121          * address space).
 122          */
 123         if (rdev->mc.vram_location != 0xFFFFFFFFUL) {
 124                 /* vram location was already setup try to put gtt after
 125                  * if it fits */
 126                 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
 127                 tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
 128                 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
 129                         rdev->mc.gtt_location = tmp;
 130                 } else {
 131                         if (rdev->mc.gtt_size >= rdev->mc.vram_location) {
 132                                 printk(KERN_ERR "[drm] GTT too big to fit "
 133                                        "before or after vram location.\n");
 134                                 return -EINVAL;
 135                         }
 136                         rdev->mc.gtt_location = 0;
 137                 }
 138         } else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) {
 139                 /* gtt location was already setup try to put vram before
 140                  * if it fits */
 141                 if (rdev->mc.mc_vram_size < rdev->mc.gtt_location) {
 142                         rdev->mc.vram_location = 0;
 143                 } else {
 144                         tmp = rdev->mc.gtt_location + rdev->mc.gtt_size;
 145                         tmp += (rdev->mc.mc_vram_size - 1);
 146                         tmp &= ~(rdev->mc.mc_vram_size - 1);
 147                         if ((0xFFFFFFFFUL - tmp) >= rdev->mc.mc_vram_size) {
 148                                 rdev->mc.vram_location = tmp;
 149                         } else {
 150                                 printk(KERN_ERR "[drm] vram too big to fit "
 151                                        "before or after GTT location.\n");
 152                                 return -EINVAL;
 153                         }
 154                 }
 155         } else {
 156                 rdev->mc.vram_location = 0;
 157                 tmp = rdev->mc.mc_vram_size;
 158                 tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
 159                 rdev->mc.gtt_location = tmp;
 160         }
 161         rdev->mc.vram_start = rdev->mc.vram_location;
 162         rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
 163         rdev->mc.gtt_start = rdev->mc.gtt_location;
 164         rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
 165         DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev->mc.mc_vram_size >> 20));
 166         DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
 167                  (unsigned)rdev->mc.vram_location,
 168                  (unsigned)(rdev->mc.vram_location + rdev->mc.mc_vram_size - 1));
 169         DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev->mc.gtt_size >> 20));
 170         DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",
 171                  (unsigned)rdev->mc.gtt_location,
 172                  (unsigned)(rdev->mc.gtt_location + rdev->mc.gtt_size - 1));
 173         return 0;
 174 }
 175
 176
 177 /*
 178  * GPU helpers function.
 179  */
 180 bool radeon_card_posted(struct radeon_device *rdev)
 181 {
 182         uint32_t reg;
 183
 184         /* first check CRTCs */
 185         if (ASIC_IS_AVIVO(rdev)) {
 186                 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
 187                       RREG32(AVIVO_D2CRTC_CONTROL);
 188                 if (reg & AVIVO_CRTC_EN) {
 189                         return true;
 190                 }
 191         } else {
 192                 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
 193                       RREG32(RADEON_CRTC2_GEN_CNTL);
 194                 if (reg & RADEON_CRTC_EN) {
 195                         return true;
 196                 }
 197         }
 198
 199         /* then check MEM_SIZE, in case the crtcs are off */
 200         if (rdev->family >= CHIP_R600)
 201                 reg = RREG32(R600_CONFIG_MEMSIZE);
 202         else
 203                 reg = RREG32(RADEON_CONFIG_MEMSIZE);
 204
 205         if (reg)
 206                 return true;
 207
 208         return false;
 209
 210 }
 211
 212 bool radeon_boot_test_post_card(struct radeon_device *rdev)
 213 {
 214         if (radeon_card_posted(rdev))
 215                 return true;
 216
 217         if (rdev->bios) {
 218                 DRM_INFO("GPU not posted. posting now...\n");
 219                 if (rdev->is_atom_bios)
 220                         atom_asic_init(rdev->mode_info.atom_context);
 221                 else
 222                         radeon_combios_asic_init(rdev->ddev);
 223                 return true;
 224         } else {
 225                 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
 226                 return false;
 227         }
 228 }
 229
 230 int radeon_dummy_page_init(struct radeon_device *rdev)
 231 {
 232         rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
 233         if (rdev->dummy_page.page == NULL)
 234                 return -ENOMEM;
 235         rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
 236                                         0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 237         if (!rdev->dummy_page.addr) {
 238                 __free_page(rdev->dummy_page.page);
 239                 rdev->dummy_page.page = NULL;
 240                 return -ENOMEM;
 241         }
 242         return 0;
 243 }
 244
 245 void radeon_dummy_page_fini(struct radeon_device *rdev)
 246 {
 247         if (rdev->dummy_page.page == NULL)
 248                 return;
 249         pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
 250                         PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 251         __free_page(rdev->dummy_page.page);
 252         rdev->dummy_page.page = NULL;
 253 }
 254
 255
 256 /*
 257  * Registers accessors functions.
 258  */
 259 uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
 260 {
 261         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
 262         BUG_ON(1);
 263         return 0;
 264 }
 265
 266 void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 267 {
 268         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
 269                   reg, v);
 270         BUG_ON(1);
 271 }
 272
 273 void radeon_register_accessor_init(struct radeon_device *rdev)
 274 {
 275         rdev->mc_rreg = &radeon_invalid_rreg;
 276         rdev->mc_wreg = &radeon_invalid_wreg;
 277         rdev->pll_rreg = &radeon_invalid_rreg;
 278         rdev->pll_wreg = &radeon_invalid_wreg;
 279         rdev->pciep_rreg = &radeon_invalid_rreg;
 280         rdev->pciep_wreg = &radeon_invalid_wreg;
 281
 282         /* Don't change order as we are overridding accessor. */
 283         if (rdev->family < CHIP_RV515) {
 284                 rdev->pcie_reg_mask = 0xff;
 285         } else {
 286                 rdev->pcie_reg_mask = 0x7ff;
 287         }
 288         /* FIXME: not sure here */
 289         if (rdev->family <= CHIP_R580) {
 290                 rdev->pll_rreg = &r100_pll_rreg;
 291                 rdev->pll_wreg = &r100_pll_wreg;
 292         }
 293         if (rdev->family >= CHIP_R420) {
 294                 rdev->mc_rreg = &r420_mc_rreg;
 295                 rdev->mc_wreg = &r420_mc_wreg;
 296         }
 297         if (rdev->family >= CHIP_RV515) {
 298                 rdev->mc_rreg = &rv515_mc_rreg;
 299                 rdev->mc_wreg = &rv515_mc_wreg;
 300         }
 301         if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
 302                 rdev->mc_rreg = &rs400_mc_rreg;
 303                 rdev->mc_wreg = &rs400_mc_wreg;
 304         }
 305         if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
 306                 rdev->mc_rreg = &rs690_mc_rreg;
 307                 rdev->mc_wreg = &rs690_mc_wreg;
 308         }
 309         if (rdev->family == CHIP_RS600) {
 310                 rdev->mc_rreg = &rs600_mc_rreg;
 311                 rdev->mc_wreg = &rs600_mc_wreg;
 312         }
 313         if (rdev->family >= CHIP_R600) {
 314                 rdev->pciep_rreg = &r600_pciep_rreg;
 315                 rdev->pciep_wreg = &r600_pciep_wreg;
 316         }
 317 }
 318
 319
 320 /*
 321  * ASIC
 322  */
 323 int radeon_asic_init(struct radeon_device *rdev)
 324 {
 325         radeon_register_accessor_init(rdev);
 326         switch (rdev->family) {
 327         case CHIP_R100:
 328         case CHIP_RV100:
 329         case CHIP_RS100:
 330         case CHIP_RV200:
 331         case CHIP_RS200:
 332         case CHIP_R200:
 333         case CHIP_RV250:
 334         case CHIP_RS300:
 335         case CHIP_RV280:
 336                 rdev->asic = &r100_asic;
 337                 break;
 338         case CHIP_R300:
 339         case CHIP_R350:
 340         case CHIP_RV350:
 341         case CHIP_RV380:
 342                 rdev->asic = &r300_asic;
 343                 if (rdev->flags & RADEON_IS_PCIE) {
 344                         rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
 345                         rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
 346                 }
 347                 break;
 348         case CHIP_R420:
 349         case CHIP_R423:
 350         case CHIP_RV410:
 351                 rdev->asic = &r420_asic;
 352                 break;
 353         case CHIP_RS400:
 354         case CHIP_RS480:
 355                 rdev->asic = &rs400_asic;
 356                 break;
 357         case CHIP_RS600:
 358                 rdev->asic = &rs600_asic;
 359                 break;
 360         case CHIP_RS690:
 361         case CHIP_RS740:
 362                 rdev->asic = &rs690_asic;
 363                 break;
 364         case CHIP_RV515:
 365                 rdev->asic = &rv515_asic;
 366                 break;
 367         case CHIP_R520:
 368         case CHIP_RV530:
 369         case CHIP_RV560:
 370         case CHIP_RV570:
 371         case CHIP_R580:
 372                 rdev->asic = &r520_asic;
 373                 break;
 374         case CHIP_R600:
 375         case CHIP_RV610:
 376         case CHIP_RV630:
 377         case CHIP_RV620:
 378         case CHIP_RV635:
 379         case CHIP_RV670:
 380         case CHIP_RS780:
 381         case CHIP_RS880:
 382                 rdev->asic = &r600_asic;
 383                 break;
 384         case CHIP_RV770:
 385         case CHIP_RV730:
 386         case CHIP_RV710:
 387         case CHIP_RV740:
 388                 rdev->asic = &rv770_asic;
 389                 break;
 390         default:
 391                 /* FIXME: not supported yet */
 392                 return -EINVAL;
 393         }
 394         return 0;
 395 }
 396
 397
 398 /*
 399  * Wrapper around modesetting bits.
 400  */
 401 int radeon_clocks_init(struct radeon_device *rdev)
 402 {
 403         int r;
 404
 405         r = radeon_static_clocks_init(rdev->ddev);
 406         if (r) {
 407                 return r;
 408         }
 409         DRM_INFO("Clocks initialized !\n");
 410         return 0;
 411 }
 412
 413 void radeon_clocks_fini(struct radeon_device *rdev)
 414 {
 415 }
 416
 417 /* ATOM accessor methods */
 418 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
 419 {
 420         struct radeon_device *rdev = info->dev->dev_private;
 421         uint32_t r;
 422
 423         r = rdev->pll_rreg(rdev, reg);
 424         return r;
 425 }
 426
 427 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
 428 {
 429         struct radeon_device *rdev = info->dev->dev_private;
 430
 431         rdev->pll_wreg(rdev, reg, val);
 432 }
 433
 434 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
 435 {
 436         struct radeon_device *rdev = info->dev->dev_private;
 437         uint32_t r;
 438
 439         r = rdev->mc_rreg(rdev, reg);
 440         return r;
 441 }
 442
 443 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
 444 {
 445         struct radeon_device *rdev = info->dev->dev_private;
 446
 447         rdev->mc_wreg(rdev, reg, val);
 448 }
 449
 450 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
 451 {
 452         struct radeon_device *rdev = info->dev->dev_private;
 453
 454         WREG32(reg*4, val);
 455 }
 456
 457 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
 458 {
 459         struct radeon_device *rdev = info->dev->dev_private;
 460         uint32_t r;
 461
 462         r = RREG32(reg*4);
 463         return r;
 464 }
 465
 466 int radeon_atombios_init(struct radeon_device *rdev)
 467 {
 468         struct card_info *atom_card_info =
 469             kzalloc(sizeof(struct card_info), GFP_KERNEL);
 470
 471         if (!atom_card_info)
 472                 return -ENOMEM;
 473
 474         rdev->mode_info.atom_card_info = atom_card_info;
 475         atom_card_info->dev = rdev->ddev;
 476         atom_card_info->reg_read = cail_reg_read;
 477         atom_card_info->reg_write = cail_reg_write;
 478         atom_card_info->mc_read = cail_mc_read;
 479         atom_card_info->mc_write = cail_mc_write;
 480         atom_card_info->pll_read = cail_pll_read;
 481         atom_card_info->pll_write = cail_pll_write;
 482
 483         rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
 484         mutex_init(&rdev->mode_info.atom_context->mutex);
 485         radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
 486         atom_allocate_fb_scratch(rdev->mode_info.atom_context);
 487         return 0;
 488 }
 489
 490 void radeon_atombios_fini(struct radeon_device *rdev)
 491 {
 492         if (rdev->mode_info.atom_context) {
 493                 kfree(rdev->mode_info.atom_context->scratch);
 494                 kfree(rdev->mode_info.atom_context);
 495         }
 496         kfree(rdev->mode_info.atom_card_info);
 497 }
 498
 499 int radeon_combios_init(struct radeon_device *rdev)
 500 {
 501         radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
 502         return 0;
 503 }
 504
 505 void radeon_combios_fini(struct radeon_device *rdev)
 506 {
 507 }
 508
 509 /* if we get transitioned to only one device, tak VGA back */
 510 static unsigned int radeon_vga_set_decode(void *cookie, bool state)
 511 {
 512         struct radeon_device *rdev = cookie;
 513         radeon_vga_set_state(rdev, state);
 514         if (state)
 515                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 516                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 517         else
 518                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 519 }
 520
 521 void radeon_agp_disable(struct radeon_device *rdev)
 522 {
 523         rdev->flags &= ~RADEON_IS_AGP;
 524         if (rdev->family >= CHIP_R600) {
 525                 DRM_INFO("Forcing AGP to PCIE mode\n");
 526                 rdev->flags |= RADEON_IS_PCIE;
 527         } else if (rdev->family >= CHIP_RV515 ||
 528                         rdev->family == CHIP_RV380 ||
 529                         rdev->family == CHIP_RV410 ||
 530                         rdev->family == CHIP_R423) {
 531                 DRM_INFO("Forcing AGP to PCIE mode\n");
 532                 rdev->flags |= RADEON_IS_PCIE;
 533                 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
 534                 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
 535         } else {
 536                 DRM_INFO("Forcing AGP to PCI mode\n");
 537                 rdev->flags |= RADEON_IS_PCI;
 538                 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
 539                 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
 540         }
 541 }
 542
 543 /*
 544  * Radeon device.
 545  */
 546 int radeon_device_init(struct radeon_device *rdev,
 547                        struct drm_device *ddev,
 548                        struct pci_dev *pdev,
 549                        uint32_t flags)
 550 {
 551         int r;
 552         int dma_bits;
 553
 554         DRM_INFO("radeon: Initializing kernel modesetting.\n");
 555         rdev->shutdown = false;
 556         rdev->dev = &pdev->dev;
 557         rdev->ddev = ddev;
 558         rdev->pdev = pdev;
 559         rdev->flags = flags;
 560         rdev->family = flags & RADEON_FAMILY_MASK;
 561         rdev->is_atom_bios = false;
 562         rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
 563         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 564         rdev->gpu_lockup = false;
 565         rdev->accel_working = false;
 566         /* mutex initialization are all done here so we
 567          * can recall function without having locking issues */
 568         mutex_init(&rdev->cs_mutex);
 569         mutex_init(&rdev->ib_pool.mutex);
 570         mutex_init(&rdev->cp.mutex);
 571         if (rdev->family >= CHIP_R600)
 572                 spin_lock_init(&rdev->ih.lock);
 573         mutex_init(&rdev->gem.mutex);
 574         rwlock_init(&rdev->fence_drv.lock);
 575         INIT_LIST_HEAD(&rdev->gem.objects);
 576
 577         /* setup workqueue */
 578         rdev->wq = create_workqueue("radeon");
 579         if (rdev->wq == NULL)
 580                 return -ENOMEM;
 581
 582         /* Set asic functions */
 583         r = radeon_asic_init(rdev);
 584         if (r) {
 585                 return r;
 586         }
 587
 588         if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
 589                 radeon_agp_disable(rdev);
 590         }
 591
 592         /* set DMA mask + need_dma32 flags.
 593          * PCIE - can handle 40-bits.
 594          * IGP - can handle 40-bits (in theory)
 595          * AGP - generally dma32 is safest
 596          * PCI - only dma32
 597          */
 598         rdev->need_dma32 = false;
 599         if (rdev->flags & RADEON_IS_AGP)
 600                 rdev->need_dma32 = true;
 601         if (rdev->flags & RADEON_IS_PCI)
 602                 rdev->need_dma32 = true;
 603
 604         dma_bits = rdev->need_dma32 ? 32 : 40;
 605         r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
 606         if (r) {
 607                 printk(KERN_WARNING "radeon: No suitable DMA available.\n");
 608         }
 609
 610         /* Registers mapping */
 611         /* TODO: block userspace mapping of io register */
 612         rdev->rmmio_base = drm_get_resource_start(rdev->ddev, 2);
 613         rdev->rmmio_size = drm_get_resource_len(rdev->ddev, 2);
 614         rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
 615         if (rdev->rmmio == NULL) {
 616                 return -ENOMEM;
 617         }
 618         DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
 619         DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
 620
 621         /* if we have > 1 VGA cards, then disable the radeon VGA resources */
 622         /* this will fail for cards that aren't VGA class devices, just
 623          * ignore it */
 624         vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
 625
 626         r = radeon_init(rdev);
 627         if (r)
 628                 return r;
 629
 630         if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
 631                 /* Acceleration not working on AGP card try again
 632                  * with fallback to PCI or PCIE GART
 633                  */
 634                 radeon_gpu_reset(rdev);
 635                 radeon_fini(rdev);
 636                 radeon_agp_disable(rdev);
 637                 r = radeon_init(rdev);
 638                 if (r)
 639                         return r;
 640         }
 641         if (radeon_testing) {
 642                 radeon_test_moves(rdev);
 643         }
 644         if (radeon_benchmarking) {
 645                 radeon_benchmark(rdev);
 646         }
 647         return 0;
 648 }
 649
 650 void radeon_device_fini(struct radeon_device *rdev)
 651 {
 652         DRM_INFO("radeon: finishing device.\n");
 653         rdev->shutdown = true;
 654         radeon_fini(rdev);
 655         destroy_workqueue(rdev->wq);
 656         vga_client_register(rdev->pdev, NULL, NULL, NULL);
 657         iounmap(rdev->rmmio);
 658         rdev->rmmio = NULL;
 659 }
 660
 661
 662 /*
 663  * Suspend & resume.
 664  */
 665 int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
 666 {
 667         struct radeon_device *rdev = dev->dev_private;
 668         struct drm_crtc *crtc;
 669         int r;
 670
 671         if (dev == NULL || rdev == NULL) {
 672                 return -ENODEV;
 673         }
 674         if (state.event == PM_EVENT_PRETHAW) {
 675                 return 0;
 676         }
 677         /* unpin the front buffers */
 678         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 679                 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb);
 680                 struct radeon_bo *robj;
 681
 682                 if (rfb == NULL || rfb->obj == NULL) {
 683                         continue;
 684                 }
 685                 robj = rfb->obj->driver_private;
 686                 if (robj != rdev->fbdev_rbo) {
 687                         r = radeon_bo_reserve(robj, false);
 688                         if (unlikely(r == 0)) {
 689                                 radeon_bo_unpin(robj);
 690                                 radeon_bo_unreserve(robj);
 691                         }
 692                 }
 693         }
 694         /* evict vram memory */
 695         radeon_bo_evict_vram(rdev);
 696         /* wait for gpu to finish processing current batch */
 697         radeon_fence_wait_last(rdev);
 698
 699         radeon_save_bios_scratch_regs(rdev);
 700
 701         radeon_suspend(rdev);
 702         radeon_hpd_fini(rdev);
 703         /* evict remaining vram memory */
 704         radeon_bo_evict_vram(rdev);
 705
 706         pci_save_state(dev->pdev);
 707         if (state.event == PM_EVENT_SUSPEND) {
 708                 /* Shut down the device */
 709                 pci_disable_device(dev->pdev);
 710                 pci_set_power_state(dev->pdev, PCI_D3hot);
 711         }
 712         acquire_console_sem();
 713         fb_set_suspend(rdev->fbdev_info, 1);
 714         release_console_sem();
 715         return 0;
 716 }
 717
 718 int radeon_resume_kms(struct drm_device *dev)
 719 {
 720         struct radeon_device *rdev = dev->dev_private;
 721
 722         acquire_console_sem();
 723         pci_set_power_state(dev->pdev, PCI_D0);
 724         pci_restore_state(dev->pdev);
 725         if (pci_enable_device(dev->pdev)) {
 726                 release_console_sem();
 727                 return -1;
 728         }
 729         pci_set_master(dev->pdev);
 730         /* resume AGP if in use */
 731         radeon_agp_resume(rdev);
 732         radeon_resume(rdev);
 733         radeon_restore_bios_scratch_regs(rdev);
 734         fb_set_suspend(rdev->fbdev_info, 0);
 735         release_console_sem();
 736
 737         /* reset hpd state */
 738         radeon_hpd_init(rdev);
 739         /* blat the mode back in */
 740         drm_helper_resume_force_mode(dev);
 741         return 0;
 742 }
 743
 744
 745 /*
 746  * Debugfs
 747  */
 748 struct radeon_debugfs {
 749         struct drm_info_list    *files;
 750         unsigned                num_files;
 751 };
 752 static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_NUM_FILES];
 753 static unsigned _radeon_debugfs_count = 0;
 754
 755 int radeon_debugfs_add_files(struct radeon_device *rdev,
 756                              struct drm_info_list *files,
 757                              unsigned nfiles)
 758 {
 759         unsigned i;
 760
 761         for (i = 0; i < _radeon_debugfs_count; i++) {
 762                 if (_radeon_debugfs[i].files == files) {
 763                         /* Already registered */
 764                         return 0;
 765                 }
 766         }
 767         if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) {
 768                 DRM_ERROR("Reached maximum number of debugfs files.\n");
 769                 DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n");
 770                 return -EINVAL;
 771         }
 772         _radeon_debugfs[_radeon_debugfs_count].files = files;
 773         _radeon_debugfs[_radeon_debugfs_count].num_files = nfiles;
 774         _radeon_debugfs_count++;
 775 #if defined(CONFIG_DEBUG_FS)
 776         drm_debugfs_create_files(files, nfiles,
 777                                  rdev->ddev->control->debugfs_root,
 778                                  rdev->ddev->control);
 779         drm_debugfs_create_files(files, nfiles,
 780                                  rdev->ddev->primary->debugfs_root,
 781                                  rdev->ddev->primary);
 782 #endif
 783         return 0;
 784 }
 785
 786 #if defined(CONFIG_DEBUG_FS)
 787 int radeon_debugfs_init(struct drm_minor *minor)
 788 {
 789         return 0;
 790 }
 791
 792 void radeon_debugfs_cleanup(struct drm_minor *minor)
 793 {
 794         unsigned i;
 795
 796         for (i = 0; i < _radeon_debugfs_count; i++) {
 797                 drm_debugfs_remove_files(_radeon_debugfs[i].files,
 798                                          _radeon_debugfs[i].num_files, minor);
 799         }
 800 }
 801 #endif