SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/radeon_device.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/console.h>
  29 #include <drm/drmP.h>
  30 #include <drm/drm_crtc_helper.h>
  31 #include <drm/radeon_drm.h>
  32 #include "radeon_reg.h"
  33 #include "radeon.h"
  34 #include "radeon_asic.h"
  35 #include "atom.h"
  36
  37 /*
  38  * Clear GPU surface registers.
  39  */
  40 void radeon_surface_init(struct radeon_device *rdev)
  41 {
  42         /* FIXME: check this out */
  43         if (rdev->family < CHIP_R600) {
  44                 int i;
  45
  46                 for (i = 0; i < 8; i++) {
  47                         WREG32(RADEON_SURFACE0_INFO +
  48                                i * (RADEON_SURFACE1_INFO - RADEON_SURFACE0_INFO),
  49                                0);
  50                 }
  51                 /* enable surfaces */
  52                 WREG32(RADEON_SURFACE_CNTL, 0);
  53         }
  54 }
  55
  56 /*
  57  * GPU scratch registers helpers function.
  58  */
  59 void radeon_scratch_init(struct radeon_device *rdev)
  60 {
  61         int i;
  62
  63         /* FIXME: check this out */
  64         if (rdev->family < CHIP_R300) {
  65                 rdev->scratch.num_reg = 5;
  66         } else {
  67                 rdev->scratch.num_reg = 7;
  68         }
  69         for (i = 0; i < rdev->scratch.num_reg; i++) {
  70                 rdev->scratch.free[i] = true;
  71                 rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4);
  72         }
  73 }
  74
  75 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
  76 {
  77         int i;
  78
  79         for (i = 0; i < rdev->scratch.num_reg; i++) {
  80                 if (rdev->scratch.free[i]) {
  81                         rdev->scratch.free[i] = false;
  82                         *reg = rdev->scratch.reg[i];
  83                         return 0;
  84                 }
  85         }
  86         return -EINVAL;
  87 }
  88
  89 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
  90 {
  91         int i;
  92
  93         for (i = 0; i < rdev->scratch.num_reg; i++) {
  94                 if (rdev->scratch.reg[i] == reg) {
  95                         rdev->scratch.free[i] = true;
  96                         return;
  97                 }
  98         }
  99 }
 100
 101 /*
 102  * MC common functions
 103  */
 104 int radeon_mc_setup(struct radeon_device *rdev)
 105 {
 106         uint32_t tmp;
 107
 108         /* Some chips have an "issue" with the memory controller, the
 109          * location must be aligned to the size. We just align it down,
 110          * too bad if we walk over the top of system memory, we don't
 111          * use DMA without a remapped anyway.
 112          * Affected chips are rv280, all r3xx, and all r4xx, but not IGP
 113          */
 114         /* FGLRX seems to setup like this, VRAM a 0, then GART.
 115          */
 116         /*
 117          * Note: from R6xx the address space is 40bits but here we only
 118          * use 32bits (still have to see a card which would exhaust 4G
 119          * address space).
 120          */
 121         if (rdev->mc.vram_location != 0xFFFFFFFFUL) {
 122                 /* vram location was already setup try to put gtt after
 123                  * if it fits */
 124                 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
 125                 tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
 126                 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
 127                         rdev->mc.gtt_location = tmp;
 128                 } else {
 129                         if (rdev->mc.gtt_size >= rdev->mc.vram_location) {
 130                                 printk(KERN_ERR "[drm] GTT too big to fit "
 131                                        "before or after vram location.\n");
 132                                 return -EINVAL;
 133                         }
 134                         rdev->mc.gtt_location = 0;
 135                 }
 136         } else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) {
 137                 /* gtt location was already setup try to put vram before
 138                  * if it fits */
 139                 if (rdev->mc.mc_vram_size < rdev->mc.gtt_location) {
 140                         rdev->mc.vram_location = 0;
 141                 } else {
 142                         tmp = rdev->mc.gtt_location + rdev->mc.gtt_size;
 143                         tmp += (rdev->mc.mc_vram_size - 1);
 144                         tmp &= ~(rdev->mc.mc_vram_size - 1);
 145                         if ((0xFFFFFFFFUL - tmp) >= rdev->mc.mc_vram_size) {
 146                                 rdev->mc.vram_location = tmp;
 147                         } else {
 148                                 printk(KERN_ERR "[drm] vram too big to fit "
 149                                        "before or after GTT location.\n");
 150                                 return -EINVAL;
 151                         }
 152                 }
 153         } else {
 154                 rdev->mc.vram_location = 0;
 155                 tmp = rdev->mc.mc_vram_size;
 156                 tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
 157                 rdev->mc.gtt_location = tmp;
 158         }
 159         DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev->mc.mc_vram_size >> 20));
 160         DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
 161                  (unsigned)rdev->mc.vram_location,
 162                  (unsigned)(rdev->mc.vram_location + rdev->mc.mc_vram_size - 1));
 163         DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev->mc.gtt_size >> 20));
 164         DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",
 165                  (unsigned)rdev->mc.gtt_location,
 166                  (unsigned)(rdev->mc.gtt_location + rdev->mc.gtt_size - 1));
 167         return 0;
 168 }
 169
 170
 171 /*
 172  * GPU helpers function.
 173  */
 174 static bool radeon_card_posted(struct radeon_device *rdev)
 175 {
 176         uint32_t reg;
 177
 178         /* first check CRTCs */
 179         if (ASIC_IS_AVIVO(rdev)) {
 180                 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
 181                       RREG32(AVIVO_D2CRTC_CONTROL);
 182                 if (reg & AVIVO_CRTC_EN) {
 183                         return true;
 184                 }
 185         } else {
 186                 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
 187                       RREG32(RADEON_CRTC2_GEN_CNTL);
 188                 if (reg & RADEON_CRTC_EN) {
 189                         return true;
 190                 }
 191         }
 192
 193         /* then check MEM_SIZE, in case the crtcs are off */
 194         if (rdev->family >= CHIP_R600)
 195                 reg = RREG32(R600_CONFIG_MEMSIZE);
 196         else
 197                 reg = RREG32(RADEON_CONFIG_MEMSIZE);
 198
 199         if (reg)
 200                 return true;
 201
 202         return false;
 203
 204 }
 205
 206 int radeon_dummy_page_init(struct radeon_device *rdev)
 207 {
 208         rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
 209         if (rdev->dummy_page.page == NULL)
 210                 return -ENOMEM;
 211         rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
 212                                         0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 213         if (!rdev->dummy_page.addr) {
 214                 __free_page(rdev->dummy_page.page);
 215                 rdev->dummy_page.page = NULL;
 216                 return -ENOMEM;
 217         }
 218         return 0;
 219 }
 220
 221 void radeon_dummy_page_fini(struct radeon_device *rdev)
 222 {
 223         if (rdev->dummy_page.page == NULL)
 224                 return;
 225         pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
 226                         PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 227         __free_page(rdev->dummy_page.page);
 228         rdev->dummy_page.page = NULL;
 229 }
 230
 231
 232 /*
 233  * Registers accessors functions.
 234  */
 235 uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
 236 {
 237         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
 238         BUG_ON(1);
 239         return 0;
 240 }
 241
 242 void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 243 {
 244         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
 245                   reg, v);
 246         BUG_ON(1);
 247 }
 248
 249 void radeon_register_accessor_init(struct radeon_device *rdev)
 250 {
 251         rdev->mc_rreg = &radeon_invalid_rreg;
 252         rdev->mc_wreg = &radeon_invalid_wreg;
 253         rdev->pll_rreg = &radeon_invalid_rreg;
 254         rdev->pll_wreg = &radeon_invalid_wreg;
 255         rdev->pciep_rreg = &radeon_invalid_rreg;
 256         rdev->pciep_wreg = &radeon_invalid_wreg;
 257
 258         /* Don't change order as we are overridding accessor. */
 259         if (rdev->family < CHIP_RV515) {
 260                 rdev->pcie_reg_mask = 0xff;
 261         } else {
 262                 rdev->pcie_reg_mask = 0x7ff;
 263         }
 264         /* FIXME: not sure here */
 265         if (rdev->family <= CHIP_R580) {
 266                 rdev->pll_rreg = &r100_pll_rreg;
 267                 rdev->pll_wreg = &r100_pll_wreg;
 268         }
 269         if (rdev->family >= CHIP_R420) {
 270                 rdev->mc_rreg = &r420_mc_rreg;
 271                 rdev->mc_wreg = &r420_mc_wreg;
 272         }
 273         if (rdev->family >= CHIP_RV515) {
 274                 rdev->mc_rreg = &rv515_mc_rreg;
 275                 rdev->mc_wreg = &rv515_mc_wreg;
 276         }
 277         if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
 278                 rdev->mc_rreg = &rs400_mc_rreg;
 279                 rdev->mc_wreg = &rs400_mc_wreg;
 280         }
 281         if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
 282                 rdev->mc_rreg = &rs690_mc_rreg;
 283                 rdev->mc_wreg = &rs690_mc_wreg;
 284         }
 285         if (rdev->family == CHIP_RS600) {
 286                 rdev->mc_rreg = &rs600_mc_rreg;
 287                 rdev->mc_wreg = &rs600_mc_wreg;
 288         }
 289         if (rdev->family >= CHIP_R600) {
 290                 rdev->pciep_rreg = &r600_pciep_rreg;
 291                 rdev->pciep_wreg = &r600_pciep_wreg;
 292         }
 293 }
 294
 295
 296 /*
 297  * ASIC
 298  */
 299 int radeon_asic_init(struct radeon_device *rdev)
 300 {
 301         radeon_register_accessor_init(rdev);
 302         switch (rdev->family) {
 303         case CHIP_R100:
 304         case CHIP_RV100:
 305         case CHIP_RS100:
 306         case CHIP_RV200:
 307         case CHIP_RS200:
 308         case CHIP_R200:
 309         case CHIP_RV250:
 310         case CHIP_RS300:
 311         case CHIP_RV280:
 312                 rdev->asic = &r100_asic;
 313                 break;
 314         case CHIP_R300:
 315         case CHIP_R350:
 316         case CHIP_RV350:
 317         case CHIP_RV380:
 318                 rdev->asic = &r300_asic;
 319                 break;
 320         case CHIP_R420:
 321         case CHIP_R423:
 322         case CHIP_RV410:
 323                 rdev->asic = &r420_asic;
 324                 break;
 325         case CHIP_RS400:
 326         case CHIP_RS480:
 327                 rdev->asic = &rs400_asic;
 328                 break;
 329         case CHIP_RS600:
 330                 rdev->asic = &rs600_asic;
 331                 break;
 332         case CHIP_RS690:
 333         case CHIP_RS740:
 334                 rdev->asic = &rs690_asic;
 335                 break;
 336         case CHIP_RV515:
 337                 rdev->asic = &rv515_asic;
 338                 break;
 339         case CHIP_R520:
 340         case CHIP_RV530:
 341         case CHIP_RV560:
 342         case CHIP_RV570:
 343         case CHIP_R580:
 344                 rdev->asic = &r520_asic;
 345                 break;
 346         case CHIP_R600:
 347         case CHIP_RV610:
 348         case CHIP_RV630:
 349         case CHIP_RV620:
 350         case CHIP_RV635:
 351         case CHIP_RV670:
 352         case CHIP_RS780:
 353         case CHIP_RS880:
 354                 rdev->asic = &r600_asic;
 355                 break;
 356         case CHIP_RV770:
 357         case CHIP_RV730:
 358         case CHIP_RV710:
 359         case CHIP_RV740:
 360                 rdev->asic = &rv770_asic;
 361                 break;
 362         default:
 363                 /* FIXME: not supported yet */
 364                 return -EINVAL;
 365         }
 366         return 0;
 367 }
 368
 369
 370 /*
 371  * Wrapper around modesetting bits.
 372  */
 373 int radeon_clocks_init(struct radeon_device *rdev)
 374 {
 375         int r;
 376
 377         radeon_get_clock_info(rdev->ddev);
 378         r = radeon_static_clocks_init(rdev->ddev);
 379         if (r) {
 380                 return r;
 381         }
 382         DRM_INFO("Clocks initialized !\n");
 383         return 0;
 384 }
 385
 386 void radeon_clocks_fini(struct radeon_device *rdev)
 387 {
 388 }
 389
 390 /* ATOM accessor methods */
 391 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
 392 {
 393         struct radeon_device *rdev = info->dev->dev_private;
 394         uint32_t r;
 395
 396         r = rdev->pll_rreg(rdev, reg);
 397         return r;
 398 }
 399
 400 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
 401 {
 402         struct radeon_device *rdev = info->dev->dev_private;
 403
 404         rdev->pll_wreg(rdev, reg, val);
 405 }
 406
 407 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
 408 {
 409         struct radeon_device *rdev = info->dev->dev_private;
 410         uint32_t r;
 411
 412         r = rdev->mc_rreg(rdev, reg);
 413         return r;
 414 }
 415
 416 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
 417 {
 418         struct radeon_device *rdev = info->dev->dev_private;
 419
 420         rdev->mc_wreg(rdev, reg, val);
 421 }
 422
 423 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
 424 {
 425         struct radeon_device *rdev = info->dev->dev_private;
 426
 427         WREG32(reg*4, val);
 428 }
 429
 430 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
 431 {
 432         struct radeon_device *rdev = info->dev->dev_private;
 433         uint32_t r;
 434
 435         r = RREG32(reg*4);
 436         return r;
 437 }
 438
 439 static struct card_info atom_card_info = {
 440         .dev = NULL,
 441         .reg_read = cail_reg_read,
 442         .reg_write = cail_reg_write,
 443         .mc_read = cail_mc_read,
 444         .mc_write = cail_mc_write,
 445         .pll_read = cail_pll_read,
 446         .pll_write = cail_pll_write,
 447 };
 448
 449 int radeon_atombios_init(struct radeon_device *rdev)
 450 {
 451         atom_card_info.dev = rdev->ddev;
 452         rdev->mode_info.atom_context = atom_parse(&atom_card_info, rdev->bios);
 453         radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
 454         return 0;
 455 }
 456
 457 void radeon_atombios_fini(struct radeon_device *rdev)
 458 {
 459         kfree(rdev->mode_info.atom_context);
 460 }
 461
 462 int radeon_combios_init(struct radeon_device *rdev)
 463 {
 464         radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
 465         return 0;
 466 }
 467
 468 void radeon_combios_fini(struct radeon_device *rdev)
 469 {
 470 }
 471
 472 int radeon_modeset_init(struct radeon_device *rdev);
 473 void radeon_modeset_fini(struct radeon_device *rdev);
 474
 475
 476 /*
 477  * Radeon device.
 478  */
 479 int radeon_device_init(struct radeon_device *rdev,
 480                        struct drm_device *ddev,
 481                        struct pci_dev *pdev,
 482                        uint32_t flags)
 483 {
 484         int r, ret = 0;
 485         int dma_bits;
 486
 487         DRM_INFO("radeon: Initializing kernel modesetting.\n");
 488         rdev->shutdown = false;
 489         rdev->ddev = ddev;
 490         rdev->pdev = pdev;
 491         rdev->flags = flags;
 492         rdev->family = flags & RADEON_FAMILY_MASK;
 493         rdev->is_atom_bios = false;
 494         rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
 495         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 496         rdev->gpu_lockup = false;
 497         /* mutex initialization are all done here so we
 498          * can recall function without having locking issues */
 499         mutex_init(&rdev->cs_mutex);
 500         mutex_init(&rdev->ib_pool.mutex);
 501         mutex_init(&rdev->cp.mutex);
 502         rwlock_init(&rdev->fence_drv.lock);
 503
 504         if (radeon_agpmode == -1) {
 505                 rdev->flags &= ~RADEON_IS_AGP;
 506                 if (rdev->family > CHIP_RV515 ||
 507                     rdev->family == CHIP_RV380 ||
 508                     rdev->family == CHIP_RV410 ||
 509                     rdev->family == CHIP_R423) {
 510                         DRM_INFO("Forcing AGP to PCIE mode\n");
 511                         rdev->flags |= RADEON_IS_PCIE;
 512                 } else {
 513                         DRM_INFO("Forcing AGP to PCI mode\n");
 514                         rdev->flags |= RADEON_IS_PCI;
 515                 }
 516         }
 517
 518         /* Set asic functions */
 519         r = radeon_asic_init(rdev);
 520         if (r) {
 521                 return r;
 522         }
 523
 524         /* set DMA mask + need_dma32 flags.
 525          * PCIE - can handle 40-bits.
 526          * IGP - can handle 40-bits (in theory)
 527          * AGP - generally dma32 is safest
 528          * PCI - only dma32
 529          */
 530         rdev->need_dma32 = false;
 531         if (rdev->flags & RADEON_IS_AGP)
 532                 rdev->need_dma32 = true;
 533         if (rdev->flags & RADEON_IS_PCI)
 534                 rdev->need_dma32 = true;
 535
 536         dma_bits = rdev->need_dma32 ? 32 : 40;
 537         r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
 538         if (r) {
 539                 printk(KERN_WARNING "radeon: No suitable DMA available.\n");
 540         }
 541
 542         /* Registers mapping */
 543         /* TODO: block userspace mapping of io register */
 544         rdev->rmmio_base = drm_get_resource_start(rdev->ddev, 2);
 545         rdev->rmmio_size = drm_get_resource_len(rdev->ddev, 2);
 546         rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
 547         if (rdev->rmmio == NULL) {
 548                 return -ENOMEM;
 549         }
 550         DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
 551         DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
 552
 553         rdev->new_init_path = false;
 554         r = radeon_init(rdev);
 555         if (r) {
 556                 return r;
 557         }
 558         if (!rdev->new_init_path) {
 559                 /* Setup errata flags */
 560                 radeon_errata(rdev);
 561                 /* Initialize scratch registers */
 562                 radeon_scratch_init(rdev);
 563                 /* Initialize surface registers */
 564                 radeon_surface_init(rdev);
 565
 566                 /* TODO: disable VGA need to use VGA request */
 567                 /* BIOS*/
 568                 if (!radeon_get_bios(rdev)) {
 569                         if (ASIC_IS_AVIVO(rdev))
 570                                 return -EINVAL;
 571                 }
 572                 if (rdev->is_atom_bios) {
 573                         r = radeon_atombios_init(rdev);
 574                         if (r) {
 575                                 return r;
 576                         }
 577                 } else {
 578                         r = radeon_combios_init(rdev);
 579                         if (r) {
 580                                 return r;
 581                         }
 582                 }
 583                 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 584                 if (radeon_gpu_reset(rdev)) {
 585                         /* FIXME: what do we want to do here ? */
 586                 }
 587                 /* check if cards are posted or not */
 588                 if (!radeon_card_posted(rdev) && rdev->bios) {
 589                         DRM_INFO("GPU not posted. posting now...\n");
 590                         if (rdev->is_atom_bios) {
 591                                 atom_asic_init(rdev->mode_info.atom_context);
 592                         } else {
 593                                 radeon_combios_asic_init(rdev->ddev);
 594                         }
 595                 }
 596                 /* Initialize clocks */
 597                 r = radeon_clocks_init(rdev);
 598                 if (r) {
 599                         return r;
 600                 }
 601                 /* Get vram informations */
 602                 radeon_vram_info(rdev);
 603
 604                 /* Add an MTRR for the VRAM */
 605                 rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
 606                                 MTRR_TYPE_WRCOMB, 1);
 607                 DRM_INFO("Detected VRAM RAM=%uM, BAR=%uM\n",
 608                                 (unsigned)(rdev->mc.mc_vram_size >> 20),
 609                                 (unsigned)(rdev->mc.aper_size >> 20));
 610                 DRM_INFO("RAM width %dbits %cDR\n",
 611                                 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
 612                 /* Initialize memory controller (also test AGP) */
 613                 r = radeon_mc_init(rdev);
 614                 if (r) {
 615                         return r;
 616                 }
 617                 /* Fence driver */
 618                 r = radeon_fence_driver_init(rdev);
 619                 if (r) {
 620                         return r;
 621                 }
 622                 r = radeon_irq_kms_init(rdev);
 623                 if (r) {
 624                         return r;
 625                 }
 626                 /* Memory manager */
 627                 r = radeon_object_init(rdev);
 628                 if (r) {
 629                         return r;
 630                 }
 631                 /* Initialize GART (initialize after TTM so we can allocate
 632                  * memory through TTM but finalize after TTM) */
 633                 r = radeon_gart_enable(rdev);
 634                 if (!r) {
 635                         r = radeon_gem_init(rdev);
 636                 }
 637
 638                 /* 1M ring buffer */
 639                 if (!r) {
 640                         r = radeon_cp_init(rdev, 1024 * 1024);
 641                 }
 642                 if (!r) {
 643                         r = radeon_wb_init(rdev);
 644                         if (r) {
 645                                 DRM_ERROR("radeon: failled initializing WB (%d).\n", r);
 646                                 return r;
 647                         }
 648                 }
 649                 if (!r) {
 650                         r = radeon_ib_pool_init(rdev);
 651                         if (r) {
 652                                 DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
 653                                 return r;
 654                         }
 655                 }
 656                 if (!r) {
 657                         r = radeon_ib_test(rdev);
 658                         if (r) {
 659                                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
 660                                 return r;
 661                         }
 662                 }
 663                 ret = r;
 664         }
 665         r = radeon_modeset_init(rdev);
 666         if (r) {
 667                 return r;
 668         }
 669         if (!ret) {
 670                 DRM_INFO("radeon: kernel modesetting successfully initialized.\n");
 671         }
 672         if (radeon_testing) {
 673                 radeon_test_moves(rdev);
 674         }
 675         if (radeon_benchmarking) {
 676                 radeon_benchmark(rdev);
 677         }
 678         return ret;
 679 }
 680
 681 void radeon_device_fini(struct radeon_device *rdev)
 682 {
 683         if (rdev == NULL || rdev->rmmio == NULL) {
 684                 return;
 685         }
 686         DRM_INFO("radeon: finishing device.\n");
 687         rdev->shutdown = true;
 688         /* Order matter so becarefull if you rearrange anythings */
 689         radeon_modeset_fini(rdev);
 690         if (!rdev->new_init_path) {
 691                 radeon_ib_pool_fini(rdev);
 692                 radeon_cp_fini(rdev);
 693                 radeon_wb_fini(rdev);
 694                 radeon_gem_fini(rdev);
 695                 radeon_mc_fini(rdev);
 696 #if __OS_HAS_AGP
 697                 radeon_agp_fini(rdev);
 698 #endif
 699                 radeon_irq_kms_fini(rdev);
 700                 radeon_fence_driver_fini(rdev);
 701                 radeon_clocks_fini(rdev);
 702                 radeon_object_fini(rdev);
 703                 if (rdev->is_atom_bios) {
 704                         radeon_atombios_fini(rdev);
 705                 } else {
 706                         radeon_combios_fini(rdev);
 707                 }
 708                 kfree(rdev->bios);
 709                 rdev->bios = NULL;
 710         } else {
 711                 radeon_fini(rdev);
 712         }
 713         iounmap(rdev->rmmio);
 714         rdev->rmmio = NULL;
 715 }
 716
 717
 718 /*
 719  * Suspend & resume.
 720  */
 721 int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
 722 {
 723         struct radeon_device *rdev = dev->dev_private;
 724         struct drm_crtc *crtc;
 725
 726         if (dev == NULL || rdev == NULL) {
 727                 return -ENODEV;
 728         }
 729         if (state.event == PM_EVENT_PRETHAW) {
 730                 return 0;
 731         }
 732         /* unpin the front buffers */
 733         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 734                 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb);
 735                 struct radeon_object *robj;
 736
 737                 if (rfb == NULL || rfb->obj == NULL) {
 738                         continue;
 739                 }
 740                 robj = rfb->obj->driver_private;
 741                 if (robj != rdev->fbdev_robj) {
 742                         radeon_object_unpin(robj);
 743                 }
 744         }
 745         /* evict vram memory */
 746         radeon_object_evict_vram(rdev);
 747         /* wait for gpu to finish processing current batch */
 748         radeon_fence_wait_last(rdev);
 749
 750         if (!rdev->new_init_path) {
 751                 radeon_cp_disable(rdev);
 752                 radeon_gart_disable(rdev);
 753         } else {
 754                 radeon_suspend(rdev);
 755         }
 756         /* evict remaining vram memory */
 757         radeon_object_evict_vram(rdev);
 758
 759         rdev->irq.sw_int = false;
 760         radeon_irq_set(rdev);
 761
 762         pci_save_state(dev->pdev);
 763         if (state.event == PM_EVENT_SUSPEND) {
 764                 /* Shut down the device */
 765                 pci_disable_device(dev->pdev);
 766                 pci_set_power_state(dev->pdev, PCI_D3hot);
 767         }
 768         acquire_console_sem();
 769         fb_set_suspend(rdev->fbdev_info, 1);
 770         release_console_sem();
 771         return 0;
 772 }
 773
 774 int radeon_resume_kms(struct drm_device *dev)
 775 {
 776         struct radeon_device *rdev = dev->dev_private;
 777         int r;
 778
 779         acquire_console_sem();
 780         pci_set_power_state(dev->pdev, PCI_D0);
 781         pci_restore_state(dev->pdev);
 782         if (pci_enable_device(dev->pdev)) {
 783                 release_console_sem();
 784                 return -1;
 785         }
 786         pci_set_master(dev->pdev);
 787         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 788         if (radeon_gpu_reset(rdev)) {
 789                 /* FIXME: what do we want to do here ? */
 790         }
 791         if (!rdev->new_init_path) {
 792                 /* post card */
 793                 if (rdev->is_atom_bios) {
 794                         atom_asic_init(rdev->mode_info.atom_context);
 795                 } else {
 796                         radeon_combios_asic_init(rdev->ddev);
 797                 }
 798                 /* Initialize clocks */
 799                 r = radeon_clocks_init(rdev);
 800                 if (r) {
 801                         release_console_sem();
 802                         return r;
 803                 }
 804                 /* Enable IRQ */
 805                 rdev->irq.sw_int = true;
 806                 radeon_irq_set(rdev);
 807                 /* Initialize GPU Memory Controller */
 808                 r = radeon_mc_init(rdev);
 809                 if (r) {
 810                         goto out;
 811                 }
 812                 r = radeon_gart_enable(rdev);
 813                 if (r) {
 814                         goto out;
 815                 }
 816                 r = radeon_cp_init(rdev, rdev->cp.ring_size);
 817                 if (r) {
 818                         goto out;
 819                 }
 820         } else {
 821                 radeon_resume(rdev);
 822         }
 823 out:
 824         fb_set_suspend(rdev->fbdev_info, 0);
 825         release_console_sem();
 826
 827         /* blat the mode back in */
 828         drm_helper_resume_force_mode(dev);
 829         return 0;
 830 }
 831
 832
 833 /*
 834  * Debugfs
 835  */
 836 struct radeon_debugfs {
 837         struct drm_info_list    *files;
 838         unsigned                num_files;
 839 };
 840 static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_NUM_FILES];
 841 static unsigned _radeon_debugfs_count = 0;
 842
 843 int radeon_debugfs_add_files(struct radeon_device *rdev,
 844                              struct drm_info_list *files,
 845                              unsigned nfiles)
 846 {
 847         unsigned i;
 848
 849         for (i = 0; i < _radeon_debugfs_count; i++) {
 850                 if (_radeon_debugfs[i].files == files) {
 851                         /* Already registered */
 852                         return 0;
 853                 }
 854         }
 855         if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) {
 856                 DRM_ERROR("Reached maximum number of debugfs files.\n");
 857                 DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n");
 858                 return -EINVAL;
 859         }
 860         _radeon_debugfs[_radeon_debugfs_count].files = files;
 861         _radeon_debugfs[_radeon_debugfs_count].num_files = nfiles;
 862         _radeon_debugfs_count++;
 863 #if defined(CONFIG_DEBUG_FS)
 864         drm_debugfs_create_files(files, nfiles,
 865                                  rdev->ddev->control->debugfs_root,
 866                                  rdev->ddev->control);
 867         drm_debugfs_create_files(files, nfiles,
 868                                  rdev->ddev->primary->debugfs_root,
 869                                  rdev->ddev->primary);
 870 #endif
 871         return 0;
 872 }
 873
 874 #if defined(CONFIG_DEBUG_FS)
 875 int radeon_debugfs_init(struct drm_minor *minor)
 876 {
 877         return 0;
 878 }
 879
 880 void radeon_debugfs_cleanup(struct drm_minor *minor)
 881 {
 882         unsigned i;
 883
 884         for (i = 0; i < _radeon_debugfs_count; i++) {
 885                 drm_debugfs_remove_files(_radeon_debugfs[i].files,
 886                                          _radeon_debugfs[i].num_files, minor);
 887         }
 888 }
 889 #endif