SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/radeon_device.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/console.h>
  29 #include <drm/drmP.h>
  30 #include <drm/drm_crtc_helper.h>
  31 #include <drm/radeon_drm.h>
  32 #include "radeon_reg.h"
  33 #include "radeon.h"
  34 #include "radeon_asic.h"
  35 #include "atom.h"
  36
  37 /*
  38  * Clear GPU surface registers.
  39  */
  40 void radeon_surface_init(struct radeon_device *rdev)
  41 {
  42         /* FIXME: check this out */
  43         if (rdev->family < CHIP_R600) {
  44                 int i;
  45
  46                 for (i = 0; i < 8; i++) {
  47                         WREG32(RADEON_SURFACE0_INFO +
  48                                i * (RADEON_SURFACE1_INFO - RADEON_SURFACE0_INFO),
  49                                0);
  50                 }
  51                 /* enable surfaces */
  52                 WREG32(RADEON_SURFACE_CNTL, 0);
  53         }
  54 }
  55
  56 /*
  57  * GPU scratch registers helpers function.
  58  */
  59 void radeon_scratch_init(struct radeon_device *rdev)
  60 {
  61         int i;
  62
  63         /* FIXME: check this out */
  64         if (rdev->family < CHIP_R300) {
  65                 rdev->scratch.num_reg = 5;
  66         } else {
  67                 rdev->scratch.num_reg = 7;
  68         }
  69         for (i = 0; i < rdev->scratch.num_reg; i++) {
  70                 rdev->scratch.free[i] = true;
  71                 rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4);
  72         }
  73 }
  74
  75 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
  76 {
  77         int i;
  78
  79         for (i = 0; i < rdev->scratch.num_reg; i++) {
  80                 if (rdev->scratch.free[i]) {
  81                         rdev->scratch.free[i] = false;
  82                         *reg = rdev->scratch.reg[i];
  83                         return 0;
  84                 }
  85         }
  86         return -EINVAL;
  87 }
  88
  89 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
  90 {
  91         int i;
  92
  93         for (i = 0; i < rdev->scratch.num_reg; i++) {
  94                 if (rdev->scratch.reg[i] == reg) {
  95                         rdev->scratch.free[i] = true;
  96                         return;
  97                 }
  98         }
  99 }
 100
 101 /*
 102  * MC common functions
 103  */
 104 int radeon_mc_setup(struct radeon_device *rdev)
 105 {
 106         uint32_t tmp;
 107
 108         /* Some chips have an "issue" with the memory controller, the
 109          * location must be aligned to the size. We just align it down,
 110          * too bad if we walk over the top of system memory, we don't
 111          * use DMA without a remapped anyway.
 112          * Affected chips are rv280, all r3xx, and all r4xx, but not IGP
 113          */
 114         /* FGLRX seems to setup like this, VRAM a 0, then GART.
 115          */
 116         /*
 117          * Note: from R6xx the address space is 40bits but here we only
 118          * use 32bits (still have to see a card which would exhaust 4G
 119          * address space).
 120          */
 121         if (rdev->mc.vram_location != 0xFFFFFFFFUL) {
 122                 /* vram location was already setup try to put gtt after
 123                  * if it fits */
 124                 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
 125                 tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
 126                 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
 127                         rdev->mc.gtt_location = tmp;
 128                 } else {
 129                         if (rdev->mc.gtt_size >= rdev->mc.vram_location) {
 130                                 printk(KERN_ERR "[drm] GTT too big to fit "
 131                                        "before or after vram location.\n");
 132                                 return -EINVAL;
 133                         }
 134                         rdev->mc.gtt_location = 0;
 135                 }
 136         } else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) {
 137                 /* gtt location was already setup try to put vram before
 138                  * if it fits */
 139                 if (rdev->mc.mc_vram_size < rdev->mc.gtt_location) {
 140                         rdev->mc.vram_location = 0;
 141                 } else {
 142                         tmp = rdev->mc.gtt_location + rdev->mc.gtt_size;
 143                         tmp += (rdev->mc.mc_vram_size - 1);
 144                         tmp &= ~(rdev->mc.mc_vram_size - 1);
 145                         if ((0xFFFFFFFFUL - tmp) >= rdev->mc.mc_vram_size) {
 146                                 rdev->mc.vram_location = tmp;
 147                         } else {
 148                                 printk(KERN_ERR "[drm] vram too big to fit "
 149                                        "before or after GTT location.\n");
 150                                 return -EINVAL;
 151                         }
 152                 }
 153         } else {
 154                 rdev->mc.vram_location = 0;
 155                 tmp = rdev->mc.mc_vram_size;
 156                 tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
 157                 rdev->mc.gtt_location = tmp;
 158         }
 159         rdev->mc.vram_start = rdev->mc.vram_location;
 160         rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
 161         rdev->mc.gtt_start = rdev->mc.gtt_location;
 162         rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
 163         DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev->mc.mc_vram_size >> 20));
 164         DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
 165                  (unsigned)rdev->mc.vram_location,
 166                  (unsigned)(rdev->mc.vram_location + rdev->mc.mc_vram_size - 1));
 167         DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev->mc.gtt_size >> 20));
 168         DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",
 169                  (unsigned)rdev->mc.gtt_location,
 170                  (unsigned)(rdev->mc.gtt_location + rdev->mc.gtt_size - 1));
 171         return 0;
 172 }
 173
 174
 175 /*
 176  * GPU helpers function.
 177  */
 178 bool radeon_card_posted(struct radeon_device *rdev)
 179 {
 180         uint32_t reg;
 181
 182         /* first check CRTCs */
 183         if (ASIC_IS_AVIVO(rdev)) {
 184                 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
 185                       RREG32(AVIVO_D2CRTC_CONTROL);
 186                 if (reg & AVIVO_CRTC_EN) {
 187                         return true;
 188                 }
 189         } else {
 190                 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
 191                       RREG32(RADEON_CRTC2_GEN_CNTL);
 192                 if (reg & RADEON_CRTC_EN) {
 193                         return true;
 194                 }
 195         }
 196
 197         /* then check MEM_SIZE, in case the crtcs are off */
 198         if (rdev->family >= CHIP_R600)
 199                 reg = RREG32(R600_CONFIG_MEMSIZE);
 200         else
 201                 reg = RREG32(RADEON_CONFIG_MEMSIZE);
 202
 203         if (reg)
 204                 return true;
 205
 206         return false;
 207
 208 }
 209
 210 int radeon_dummy_page_init(struct radeon_device *rdev)
 211 {
 212         rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
 213         if (rdev->dummy_page.page == NULL)
 214                 return -ENOMEM;
 215         rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
 216                                         0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 217         if (!rdev->dummy_page.addr) {
 218                 __free_page(rdev->dummy_page.page);
 219                 rdev->dummy_page.page = NULL;
 220                 return -ENOMEM;
 221         }
 222         return 0;
 223 }
 224
 225 void radeon_dummy_page_fini(struct radeon_device *rdev)
 226 {
 227         if (rdev->dummy_page.page == NULL)
 228                 return;
 229         pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
 230                         PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 231         __free_page(rdev->dummy_page.page);
 232         rdev->dummy_page.page = NULL;
 233 }
 234
 235
 236 /*
 237  * Registers accessors functions.
 238  */
 239 uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
 240 {
 241         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
 242         BUG_ON(1);
 243         return 0;
 244 }
 245
 246 void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 247 {
 248         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
 249                   reg, v);
 250         BUG_ON(1);
 251 }
 252
 253 void radeon_register_accessor_init(struct radeon_device *rdev)
 254 {
 255         rdev->mc_rreg = &radeon_invalid_rreg;
 256         rdev->mc_wreg = &radeon_invalid_wreg;
 257         rdev->pll_rreg = &radeon_invalid_rreg;
 258         rdev->pll_wreg = &radeon_invalid_wreg;
 259         rdev->pciep_rreg = &radeon_invalid_rreg;
 260         rdev->pciep_wreg = &radeon_invalid_wreg;
 261
 262         /* Don't change order as we are overridding accessor. */
 263         if (rdev->family < CHIP_RV515) {
 264                 rdev->pcie_reg_mask = 0xff;
 265         } else {
 266                 rdev->pcie_reg_mask = 0x7ff;
 267         }
 268         /* FIXME: not sure here */
 269         if (rdev->family <= CHIP_R580) {
 270                 rdev->pll_rreg = &r100_pll_rreg;
 271                 rdev->pll_wreg = &r100_pll_wreg;
 272         }
 273         if (rdev->family >= CHIP_R420) {
 274                 rdev->mc_rreg = &r420_mc_rreg;
 275                 rdev->mc_wreg = &r420_mc_wreg;
 276         }
 277         if (rdev->family >= CHIP_RV515) {
 278                 rdev->mc_rreg = &rv515_mc_rreg;
 279                 rdev->mc_wreg = &rv515_mc_wreg;
 280         }
 281         if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
 282                 rdev->mc_rreg = &rs400_mc_rreg;
 283                 rdev->mc_wreg = &rs400_mc_wreg;
 284         }
 285         if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
 286                 rdev->mc_rreg = &rs690_mc_rreg;
 287                 rdev->mc_wreg = &rs690_mc_wreg;
 288         }
 289         if (rdev->family == CHIP_RS600) {
 290                 rdev->mc_rreg = &rs600_mc_rreg;
 291                 rdev->mc_wreg = &rs600_mc_wreg;
 292         }
 293         if (rdev->family >= CHIP_R600) {
 294                 rdev->pciep_rreg = &r600_pciep_rreg;
 295                 rdev->pciep_wreg = &r600_pciep_wreg;
 296         }
 297 }
 298
 299
 300 /*
 301  * ASIC
 302  */
 303 int radeon_asic_init(struct radeon_device *rdev)
 304 {
 305         radeon_register_accessor_init(rdev);
 306         switch (rdev->family) {
 307         case CHIP_R100:
 308         case CHIP_RV100:
 309         case CHIP_RS100:
 310         case CHIP_RV200:
 311         case CHIP_RS200:
 312         case CHIP_R200:
 313         case CHIP_RV250:
 314         case CHIP_RS300:
 315         case CHIP_RV280:
 316                 rdev->asic = &r100_asic;
 317                 break;
 318         case CHIP_R300:
 319         case CHIP_R350:
 320         case CHIP_RV350:
 321         case CHIP_RV380:
 322                 rdev->asic = &r300_asic;
 323                 if (rdev->flags & RADEON_IS_PCIE) {
 324                         rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
 325                         rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
 326                 }
 327                 break;
 328         case CHIP_R420:
 329         case CHIP_R423:
 330         case CHIP_RV410:
 331                 rdev->asic = &r420_asic;
 332                 break;
 333         case CHIP_RS400:
 334         case CHIP_RS480:
 335                 rdev->asic = &rs400_asic;
 336                 break;
 337         case CHIP_RS600:
 338                 rdev->asic = &rs600_asic;
 339                 break;
 340         case CHIP_RS690:
 341         case CHIP_RS740:
 342                 rdev->asic = &rs690_asic;
 343                 break;
 344         case CHIP_RV515:
 345                 rdev->asic = &rv515_asic;
 346                 break;
 347         case CHIP_R520:
 348         case CHIP_RV530:
 349         case CHIP_RV560:
 350         case CHIP_RV570:
 351         case CHIP_R580:
 352                 rdev->asic = &r520_asic;
 353                 break;
 354         case CHIP_R600:
 355         case CHIP_RV610:
 356         case CHIP_RV630:
 357         case CHIP_RV620:
 358         case CHIP_RV635:
 359         case CHIP_RV670:
 360         case CHIP_RS780:
 361         case CHIP_RS880:
 362                 rdev->asic = &r600_asic;
 363                 break;
 364         case CHIP_RV770:
 365         case CHIP_RV730:
 366         case CHIP_RV710:
 367         case CHIP_RV740:
 368                 rdev->asic = &rv770_asic;
 369                 break;
 370         default:
 371                 /* FIXME: not supported yet */
 372                 return -EINVAL;
 373         }
 374         return 0;
 375 }
 376
 377
 378 /*
 379  * Wrapper around modesetting bits.
 380  */
 381 int radeon_clocks_init(struct radeon_device *rdev)
 382 {
 383         int r;
 384
 385         r = radeon_static_clocks_init(rdev->ddev);
 386         if (r) {
 387                 return r;
 388         }
 389         DRM_INFO("Clocks initialized !\n");
 390         return 0;
 391 }
 392
 393 void radeon_clocks_fini(struct radeon_device *rdev)
 394 {
 395 }
 396
 397 /* ATOM accessor methods */
 398 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
 399 {
 400         struct radeon_device *rdev = info->dev->dev_private;
 401         uint32_t r;
 402
 403         r = rdev->pll_rreg(rdev, reg);
 404         return r;
 405 }
 406
 407 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
 408 {
 409         struct radeon_device *rdev = info->dev->dev_private;
 410
 411         rdev->pll_wreg(rdev, reg, val);
 412 }
 413
 414 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
 415 {
 416         struct radeon_device *rdev = info->dev->dev_private;
 417         uint32_t r;
 418
 419         r = rdev->mc_rreg(rdev, reg);
 420         return r;
 421 }
 422
 423 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
 424 {
 425         struct radeon_device *rdev = info->dev->dev_private;
 426
 427         rdev->mc_wreg(rdev, reg, val);
 428 }
 429
 430 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
 431 {
 432         struct radeon_device *rdev = info->dev->dev_private;
 433
 434         WREG32(reg*4, val);
 435 }
 436
 437 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
 438 {
 439         struct radeon_device *rdev = info->dev->dev_private;
 440         uint32_t r;
 441
 442         r = RREG32(reg*4);
 443         return r;
 444 }
 445
 446 int radeon_atombios_init(struct radeon_device *rdev)
 447 {
 448         struct card_info *atom_card_info =
 449             kzalloc(sizeof(struct card_info), GFP_KERNEL);
 450
 451         if (!atom_card_info)
 452                 return -ENOMEM;
 453
 454         rdev->mode_info.atom_card_info = atom_card_info;
 455         atom_card_info->dev = rdev->ddev;
 456         atom_card_info->reg_read = cail_reg_read;
 457         atom_card_info->reg_write = cail_reg_write;
 458         atom_card_info->mc_read = cail_mc_read;
 459         atom_card_info->mc_write = cail_mc_write;
 460         atom_card_info->pll_read = cail_pll_read;
 461         atom_card_info->pll_write = cail_pll_write;
 462
 463         rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
 464         radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
 465         return 0;
 466 }
 467
 468 void radeon_atombios_fini(struct radeon_device *rdev)
 469 {
 470         kfree(rdev->mode_info.atom_context);
 471         kfree(rdev->mode_info.atom_card_info);
 472 }
 473
 474 int radeon_combios_init(struct radeon_device *rdev)
 475 {
 476         radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
 477         return 0;
 478 }
 479
 480 void radeon_combios_fini(struct radeon_device *rdev)
 481 {
 482 }
 483
 484 void radeon_agp_disable(struct radeon_device *rdev)
 485 {
 486         rdev->flags &= ~RADEON_IS_AGP;
 487         if (rdev->family >= CHIP_R600) {
 488                 DRM_INFO("Forcing AGP to PCIE mode\n");
 489                 rdev->flags |= RADEON_IS_PCIE;
 490         } else if (rdev->family >= CHIP_RV515 ||
 491                         rdev->family == CHIP_RV380 ||
 492                         rdev->family == CHIP_RV410 ||
 493                         rdev->family == CHIP_R423) {
 494                 DRM_INFO("Forcing AGP to PCIE mode\n");
 495                 rdev->flags |= RADEON_IS_PCIE;
 496                 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
 497                 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
 498         } else {
 499                 DRM_INFO("Forcing AGP to PCI mode\n");
 500                 rdev->flags |= RADEON_IS_PCI;
 501                 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
 502                 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
 503         }
 504 }
 505
 506 /*
 507  * Radeon device.
 508  */
 509 int radeon_device_init(struct radeon_device *rdev,
 510                        struct drm_device *ddev,
 511                        struct pci_dev *pdev,
 512                        uint32_t flags)
 513 {
 514         int r;
 515         int dma_bits;
 516
 517         DRM_INFO("radeon: Initializing kernel modesetting.\n");
 518         rdev->shutdown = false;
 519         rdev->dev = &pdev->dev;
 520         rdev->ddev = ddev;
 521         rdev->pdev = pdev;
 522         rdev->flags = flags;
 523         rdev->family = flags & RADEON_FAMILY_MASK;
 524         rdev->is_atom_bios = false;
 525         rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
 526         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 527         rdev->gpu_lockup = false;
 528         rdev->accel_working = false;
 529         /* mutex initialization are all done here so we
 530          * can recall function without having locking issues */
 531         mutex_init(&rdev->cs_mutex);
 532         mutex_init(&rdev->ib_pool.mutex);
 533         mutex_init(&rdev->cp.mutex);
 534         rwlock_init(&rdev->fence_drv.lock);
 535         INIT_LIST_HEAD(&rdev->gem.objects);
 536
 537         /* Set asic functions */
 538         r = radeon_asic_init(rdev);
 539         if (r) {
 540                 return r;
 541         }
 542
 543         if (radeon_agpmode == -1) {
 544                 radeon_agp_disable(rdev);
 545         }
 546
 547         /* set DMA mask + need_dma32 flags.
 548          * PCIE - can handle 40-bits.
 549          * IGP - can handle 40-bits (in theory)
 550          * AGP - generally dma32 is safest
 551          * PCI - only dma32
 552          */
 553         rdev->need_dma32 = false;
 554         if (rdev->flags & RADEON_IS_AGP)
 555                 rdev->need_dma32 = true;
 556         if (rdev->flags & RADEON_IS_PCI)
 557                 rdev->need_dma32 = true;
 558
 559         dma_bits = rdev->need_dma32 ? 32 : 40;
 560         r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
 561         if (r) {
 562                 printk(KERN_WARNING "radeon: No suitable DMA available.\n");
 563         }
 564
 565         /* Registers mapping */
 566         /* TODO: block userspace mapping of io register */
 567         rdev->rmmio_base = drm_get_resource_start(rdev->ddev, 2);
 568         rdev->rmmio_size = drm_get_resource_len(rdev->ddev, 2);
 569         rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
 570         if (rdev->rmmio == NULL) {
 571                 return -ENOMEM;
 572         }
 573         DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
 574         DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
 575
 576         r = radeon_init(rdev);
 577         if (r)
 578                 return r;
 579         if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
 580                 /* Acceleration not working on AGP card try again
 581                  * with fallback to PCI or PCIE GART
 582                  */
 583                 radeon_gpu_reset(rdev);
 584                 radeon_fini(rdev);
 585                 radeon_agp_disable(rdev);
 586                 r = radeon_init(rdev);
 587                 if (r)
 588                         return r;
 589         }
 590         if (radeon_testing) {
 591                 radeon_test_moves(rdev);
 592         }
 593         if (radeon_benchmarking) {
 594                 radeon_benchmark(rdev);
 595         }
 596         return 0;
 597 }
 598
 599 void radeon_device_fini(struct radeon_device *rdev)
 600 {
 601         DRM_INFO("radeon: finishing device.\n");
 602         rdev->shutdown = true;
 603         /* Order matter so becarefull if you rearrange anythings */
 604         radeon_fini(rdev);
 605         iounmap(rdev->rmmio);
 606         rdev->rmmio = NULL;
 607 }
 608
 609
 610 /*
 611  * Suspend & resume.
 612  */
 613 int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
 614 {
 615         struct radeon_device *rdev = dev->dev_private;
 616         struct drm_crtc *crtc;
 617
 618         if (dev == NULL || rdev == NULL) {
 619                 return -ENODEV;
 620         }
 621         if (state.event == PM_EVENT_PRETHAW) {
 622                 return 0;
 623         }
 624         /* unpin the front buffers */
 625         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 626                 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb);
 627                 struct radeon_object *robj;
 628
 629                 if (rfb == NULL || rfb->obj == NULL) {
 630                         continue;
 631                 }
 632                 robj = rfb->obj->driver_private;
 633                 if (robj != rdev->fbdev_robj) {
 634                         radeon_object_unpin(robj);
 635                 }
 636         }
 637         /* evict vram memory */
 638         radeon_object_evict_vram(rdev);
 639         /* wait for gpu to finish processing current batch */
 640         radeon_fence_wait_last(rdev);
 641
 642         radeon_save_bios_scratch_regs(rdev);
 643
 644         radeon_suspend(rdev);
 645         /* evict remaining vram memory */
 646         radeon_object_evict_vram(rdev);
 647
 648         pci_save_state(dev->pdev);
 649         if (state.event == PM_EVENT_SUSPEND) {
 650                 /* Shut down the device */
 651                 pci_disable_device(dev->pdev);
 652                 pci_set_power_state(dev->pdev, PCI_D3hot);
 653         }
 654         acquire_console_sem();
 655         fb_set_suspend(rdev->fbdev_info, 1);
 656         release_console_sem();
 657         return 0;
 658 }
 659
 660 int radeon_resume_kms(struct drm_device *dev)
 661 {
 662         struct radeon_device *rdev = dev->dev_private;
 663
 664         acquire_console_sem();
 665         pci_set_power_state(dev->pdev, PCI_D0);
 666         pci_restore_state(dev->pdev);
 667         if (pci_enable_device(dev->pdev)) {
 668                 release_console_sem();
 669                 return -1;
 670         }
 671         pci_set_master(dev->pdev);
 672         radeon_resume(rdev);
 673         radeon_restore_bios_scratch_regs(rdev);
 674         fb_set_suspend(rdev->fbdev_info, 0);
 675         release_console_sem();
 676
 677         /* blat the mode back in */
 678         drm_helper_resume_force_mode(dev);
 679         return 0;
 680 }
 681
 682
 683 /*
 684  * Debugfs
 685  */
 686 struct radeon_debugfs {
 687         struct drm_info_list    *files;
 688         unsigned                num_files;
 689 };
 690 static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_NUM_FILES];
 691 static unsigned _radeon_debugfs_count = 0;
 692
 693 int radeon_debugfs_add_files(struct radeon_device *rdev,
 694                              struct drm_info_list *files,
 695                              unsigned nfiles)
 696 {
 697         unsigned i;
 698
 699         for (i = 0; i < _radeon_debugfs_count; i++) {
 700                 if (_radeon_debugfs[i].files == files) {
 701                         /* Already registered */
 702                         return 0;
 703                 }
 704         }
 705         if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) {
 706                 DRM_ERROR("Reached maximum number of debugfs files.\n");
 707                 DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n");
 708                 return -EINVAL;
 709         }
 710         _radeon_debugfs[_radeon_debugfs_count].files = files;
 711         _radeon_debugfs[_radeon_debugfs_count].num_files = nfiles;
 712         _radeon_debugfs_count++;
 713 #if defined(CONFIG_DEBUG_FS)
 714         drm_debugfs_create_files(files, nfiles,
 715                                  rdev->ddev->control->debugfs_root,
 716                                  rdev->ddev->control);
 717         drm_debugfs_create_files(files, nfiles,
 718                                  rdev->ddev->primary->debugfs_root,
 719                                  rdev->ddev->primary);
 720 #endif
 721         return 0;
 722 }
 723
 724 #if defined(CONFIG_DEBUG_FS)
 725 int radeon_debugfs_init(struct drm_minor *minor)
 726 {
 727         return 0;
 728 }
 729
 730 void radeon_debugfs_cleanup(struct drm_minor *minor)
 731 {
 732         unsigned i;
 733
 734         for (i = 0; i < _radeon_debugfs_count; i++) {
 735                 drm_debugfs_remove_files(_radeon_debugfs[i].files,
 736                                          _radeon_debugfs[i].num_files, minor);
 737         }
 738 }
 739 #endif