SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/radeon_device.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/console.h>
  29 #include <drm/drmP.h>
  30 #include <drm/drm_crtc_helper.h>
  31 #include <drm/radeon_drm.h>
  32 #include <linux/vgaarb.h>
  33 #include "radeon_reg.h"
  34 #include "radeon.h"
  35 #include "radeon_asic.h"
  36 #include "atom.h"
  37
  38 /*
  39  * Clear GPU surface registers.
  40  */
  41 void radeon_surface_init(struct radeon_device *rdev)
  42 {
  43         /* FIXME: check this out */
  44         if (rdev->family < CHIP_R600) {
  45                 int i;
  46
  47                 for (i = 0; i < 8; i++) {
  48                         WREG32(RADEON_SURFACE0_INFO +
  49                                i * (RADEON_SURFACE1_INFO - RADEON_SURFACE0_INFO),
  50                                0);
  51                 }
  52                 /* enable surfaces */
  53                 WREG32(RADEON_SURFACE_CNTL, 0);
  54         }
  55 }
  56
  57 /*
  58  * GPU scratch registers helpers function.
  59  */
  60 void radeon_scratch_init(struct radeon_device *rdev)
  61 {
  62         int i;
  63
  64         /* FIXME: check this out */
  65         if (rdev->family < CHIP_R300) {
  66                 rdev->scratch.num_reg = 5;
  67         } else {
  68                 rdev->scratch.num_reg = 7;
  69         }
  70         for (i = 0; i < rdev->scratch.num_reg; i++) {
  71                 rdev->scratch.free[i] = true;
  72                 rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4);
  73         }
  74 }
  75
  76 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
  77 {
  78         int i;
  79
  80         for (i = 0; i < rdev->scratch.num_reg; i++) {
  81                 if (rdev->scratch.free[i]) {
  82                         rdev->scratch.free[i] = false;
  83                         *reg = rdev->scratch.reg[i];
  84                         return 0;
  85                 }
  86         }
  87         return -EINVAL;
  88 }
  89
  90 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
  91 {
  92         int i;
  93
  94         for (i = 0; i < rdev->scratch.num_reg; i++) {
  95                 if (rdev->scratch.reg[i] == reg) {
  96                         rdev->scratch.free[i] = true;
  97                         return;
  98                 }
  99         }
 100 }
 101
 102 /*
 103  * MC common functions
 104  */
 105 int radeon_mc_setup(struct radeon_device *rdev)
 106 {
 107         uint32_t tmp;
 108
 109         /* Some chips have an "issue" with the memory controller, the
 110          * location must be aligned to the size. We just align it down,
 111          * too bad if we walk over the top of system memory, we don't
 112          * use DMA without a remapped anyway.
 113          * Affected chips are rv280, all r3xx, and all r4xx, but not IGP
 114          */
 115         /* FGLRX seems to setup like this, VRAM a 0, then GART.
 116          */
 117         /*
 118          * Note: from R6xx the address space is 40bits but here we only
 119          * use 32bits (still have to see a card which would exhaust 4G
 120          * address space).
 121          */
 122         if (rdev->mc.vram_location != 0xFFFFFFFFUL) {
 123                 /* vram location was already setup try to put gtt after
 124                  * if it fits */
 125                 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
 126                 tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
 127                 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
 128                         rdev->mc.gtt_location = tmp;
 129                 } else {
 130                         if (rdev->mc.gtt_size >= rdev->mc.vram_location) {
 131                                 printk(KERN_ERR "[drm] GTT too big to fit "
 132                                        "before or after vram location.\n");
 133                                 return -EINVAL;
 134                         }
 135                         rdev->mc.gtt_location = 0;
 136                 }
 137         } else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) {
 138                 /* gtt location was already setup try to put vram before
 139                  * if it fits */
 140                 if (rdev->mc.mc_vram_size < rdev->mc.gtt_location) {
 141                         rdev->mc.vram_location = 0;
 142                 } else {
 143                         tmp = rdev->mc.gtt_location + rdev->mc.gtt_size;
 144                         tmp += (rdev->mc.mc_vram_size - 1);
 145                         tmp &= ~(rdev->mc.mc_vram_size - 1);
 146                         if ((0xFFFFFFFFUL - tmp) >= rdev->mc.mc_vram_size) {
 147                                 rdev->mc.vram_location = tmp;
 148                         } else {
 149                                 printk(KERN_ERR "[drm] vram too big to fit "
 150                                        "before or after GTT location.\n");
 151                                 return -EINVAL;
 152                         }
 153                 }
 154         } else {
 155                 rdev->mc.vram_location = 0;
 156                 tmp = rdev->mc.mc_vram_size;
 157                 tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
 158                 rdev->mc.gtt_location = tmp;
 159         }
 160         rdev->mc.vram_start = rdev->mc.vram_location;
 161         rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
 162         rdev->mc.gtt_start = rdev->mc.gtt_location;
 163         rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
 164         DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev->mc.mc_vram_size >> 20));
 165         DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
 166                  (unsigned)rdev->mc.vram_location,
 167                  (unsigned)(rdev->mc.vram_location + rdev->mc.mc_vram_size - 1));
 168         DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev->mc.gtt_size >> 20));
 169         DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",
 170                  (unsigned)rdev->mc.gtt_location,
 171                  (unsigned)(rdev->mc.gtt_location + rdev->mc.gtt_size - 1));
 172         return 0;
 173 }
 174
 175
 176 /*
 177  * GPU helpers function.
 178  */
 179 bool radeon_card_posted(struct radeon_device *rdev)
 180 {
 181         uint32_t reg;
 182
 183         /* first check CRTCs */
 184         if (ASIC_IS_AVIVO(rdev)) {
 185                 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
 186                       RREG32(AVIVO_D2CRTC_CONTROL);
 187                 if (reg & AVIVO_CRTC_EN) {
 188                         return true;
 189                 }
 190         } else {
 191                 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
 192                       RREG32(RADEON_CRTC2_GEN_CNTL);
 193                 if (reg & RADEON_CRTC_EN) {
 194                         return true;
 195                 }
 196         }
 197
 198         /* then check MEM_SIZE, in case the crtcs are off */
 199         if (rdev->family >= CHIP_R600)
 200                 reg = RREG32(R600_CONFIG_MEMSIZE);
 201         else
 202                 reg = RREG32(RADEON_CONFIG_MEMSIZE);
 203
 204         if (reg)
 205                 return true;
 206
 207         return false;
 208
 209 }
 210
 211 bool radeon_boot_test_post_card(struct radeon_device *rdev)
 212 {
 213         if (radeon_card_posted(rdev))
 214                 return true;
 215
 216         if (rdev->bios) {
 217                 DRM_INFO("GPU not posted. posting now...\n");
 218                 if (rdev->is_atom_bios)
 219                         atom_asic_init(rdev->mode_info.atom_context);
 220                 else
 221                         radeon_combios_asic_init(rdev->ddev);
 222                 return true;
 223         } else {
 224                 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
 225                 return false;
 226         }
 227 }
 228
 229 int radeon_dummy_page_init(struct radeon_device *rdev)
 230 {
 231         rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
 232         if (rdev->dummy_page.page == NULL)
 233                 return -ENOMEM;
 234         rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
 235                                         0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 236         if (!rdev->dummy_page.addr) {
 237                 __free_page(rdev->dummy_page.page);
 238                 rdev->dummy_page.page = NULL;
 239                 return -ENOMEM;
 240         }
 241         return 0;
 242 }
 243
 244 void radeon_dummy_page_fini(struct radeon_device *rdev)
 245 {
 246         if (rdev->dummy_page.page == NULL)
 247                 return;
 248         pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
 249                         PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 250         __free_page(rdev->dummy_page.page);
 251         rdev->dummy_page.page = NULL;
 252 }
 253
 254
 255 /*
 256  * Registers accessors functions.
 257  */
 258 uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
 259 {
 260         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
 261         BUG_ON(1);
 262         return 0;
 263 }
 264
 265 void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 266 {
 267         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
 268                   reg, v);
 269         BUG_ON(1);
 270 }
 271
 272 void radeon_register_accessor_init(struct radeon_device *rdev)
 273 {
 274         rdev->mc_rreg = &radeon_invalid_rreg;
 275         rdev->mc_wreg = &radeon_invalid_wreg;
 276         rdev->pll_rreg = &radeon_invalid_rreg;
 277         rdev->pll_wreg = &radeon_invalid_wreg;
 278         rdev->pciep_rreg = &radeon_invalid_rreg;
 279         rdev->pciep_wreg = &radeon_invalid_wreg;
 280
 281         /* Don't change order as we are overridding accessor. */
 282         if (rdev->family < CHIP_RV515) {
 283                 rdev->pcie_reg_mask = 0xff;
 284         } else {
 285                 rdev->pcie_reg_mask = 0x7ff;
 286         }
 287         /* FIXME: not sure here */
 288         if (rdev->family <= CHIP_R580) {
 289                 rdev->pll_rreg = &r100_pll_rreg;
 290                 rdev->pll_wreg = &r100_pll_wreg;
 291         }
 292         if (rdev->family >= CHIP_R420) {
 293                 rdev->mc_rreg = &r420_mc_rreg;
 294                 rdev->mc_wreg = &r420_mc_wreg;
 295         }
 296         if (rdev->family >= CHIP_RV515) {
 297                 rdev->mc_rreg = &rv515_mc_rreg;
 298                 rdev->mc_wreg = &rv515_mc_wreg;
 299         }
 300         if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
 301                 rdev->mc_rreg = &rs400_mc_rreg;
 302                 rdev->mc_wreg = &rs400_mc_wreg;
 303         }
 304         if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
 305                 rdev->mc_rreg = &rs690_mc_rreg;
 306                 rdev->mc_wreg = &rs690_mc_wreg;
 307         }
 308         if (rdev->family == CHIP_RS600) {
 309                 rdev->mc_rreg = &rs600_mc_rreg;
 310                 rdev->mc_wreg = &rs600_mc_wreg;
 311         }
 312         if (rdev->family >= CHIP_R600) {
 313                 rdev->pciep_rreg = &r600_pciep_rreg;
 314                 rdev->pciep_wreg = &r600_pciep_wreg;
 315         }
 316 }
 317
 318
 319 /*
 320  * ASIC
 321  */
 322 int radeon_asic_init(struct radeon_device *rdev)
 323 {
 324         radeon_register_accessor_init(rdev);
 325         switch (rdev->family) {
 326         case CHIP_R100:
 327         case CHIP_RV100:
 328         case CHIP_RS100:
 329         case CHIP_RV200:
 330         case CHIP_RS200:
 331         case CHIP_R200:
 332         case CHIP_RV250:
 333         case CHIP_RS300:
 334         case CHIP_RV280:
 335                 rdev->asic = &r100_asic;
 336                 break;
 337         case CHIP_R300:
 338         case CHIP_R350:
 339         case CHIP_RV350:
 340         case CHIP_RV380:
 341                 rdev->asic = &r300_asic;
 342                 if (rdev->flags & RADEON_IS_PCIE) {
 343                         rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
 344                         rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
 345                 }
 346                 break;
 347         case CHIP_R420:
 348         case CHIP_R423:
 349         case CHIP_RV410:
 350                 rdev->asic = &r420_asic;
 351                 break;
 352         case CHIP_RS400:
 353         case CHIP_RS480:
 354                 rdev->asic = &rs400_asic;
 355                 break;
 356         case CHIP_RS600:
 357                 rdev->asic = &rs600_asic;
 358                 break;
 359         case CHIP_RS690:
 360         case CHIP_RS740:
 361                 rdev->asic = &rs690_asic;
 362                 break;
 363         case CHIP_RV515:
 364                 rdev->asic = &rv515_asic;
 365                 break;
 366         case CHIP_R520:
 367         case CHIP_RV530:
 368         case CHIP_RV560:
 369         case CHIP_RV570:
 370         case CHIP_R580:
 371                 rdev->asic = &r520_asic;
 372                 break;
 373         case CHIP_R600:
 374         case CHIP_RV610:
 375         case CHIP_RV630:
 376         case CHIP_RV620:
 377         case CHIP_RV635:
 378         case CHIP_RV670:
 379         case CHIP_RS780:
 380         case CHIP_RS880:
 381                 rdev->asic = &r600_asic;
 382                 break;
 383         case CHIP_RV770:
 384         case CHIP_RV730:
 385         case CHIP_RV710:
 386         case CHIP_RV740:
 387                 rdev->asic = &rv770_asic;
 388                 break;
 389         default:
 390                 /* FIXME: not supported yet */
 391                 return -EINVAL;
 392         }
 393         return 0;
 394 }
 395
 396
 397 /*
 398  * Wrapper around modesetting bits.
 399  */
 400 int radeon_clocks_init(struct radeon_device *rdev)
 401 {
 402         int r;
 403
 404         r = radeon_static_clocks_init(rdev->ddev);
 405         if (r) {
 406                 return r;
 407         }
 408         DRM_INFO("Clocks initialized !\n");
 409         return 0;
 410 }
 411
 412 void radeon_clocks_fini(struct radeon_device *rdev)
 413 {
 414 }
 415
 416 /* ATOM accessor methods */
 417 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
 418 {
 419         struct radeon_device *rdev = info->dev->dev_private;
 420         uint32_t r;
 421
 422         r = rdev->pll_rreg(rdev, reg);
 423         return r;
 424 }
 425
 426 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
 427 {
 428         struct radeon_device *rdev = info->dev->dev_private;
 429
 430         rdev->pll_wreg(rdev, reg, val);
 431 }
 432
 433 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
 434 {
 435         struct radeon_device *rdev = info->dev->dev_private;
 436         uint32_t r;
 437
 438         r = rdev->mc_rreg(rdev, reg);
 439         return r;
 440 }
 441
 442 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
 443 {
 444         struct radeon_device *rdev = info->dev->dev_private;
 445
 446         rdev->mc_wreg(rdev, reg, val);
 447 }
 448
 449 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
 450 {
 451         struct radeon_device *rdev = info->dev->dev_private;
 452
 453         WREG32(reg*4, val);
 454 }
 455
 456 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
 457 {
 458         struct radeon_device *rdev = info->dev->dev_private;
 459         uint32_t r;
 460
 461         r = RREG32(reg*4);
 462         return r;
 463 }
 464
 465 int radeon_atombios_init(struct radeon_device *rdev)
 466 {
 467         struct card_info *atom_card_info =
 468             kzalloc(sizeof(struct card_info), GFP_KERNEL);
 469
 470         if (!atom_card_info)
 471                 return -ENOMEM;
 472
 473         rdev->mode_info.atom_card_info = atom_card_info;
 474         atom_card_info->dev = rdev->ddev;
 475         atom_card_info->reg_read = cail_reg_read;
 476         atom_card_info->reg_write = cail_reg_write;
 477         atom_card_info->mc_read = cail_mc_read;
 478         atom_card_info->mc_write = cail_mc_write;
 479         atom_card_info->pll_read = cail_pll_read;
 480         atom_card_info->pll_write = cail_pll_write;
 481
 482         rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
 483         radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
 484         return 0;
 485 }
 486
 487 void radeon_atombios_fini(struct radeon_device *rdev)
 488 {
 489         kfree(rdev->mode_info.atom_context);
 490         kfree(rdev->mode_info.atom_card_info);
 491 }
 492
 493 int radeon_combios_init(struct radeon_device *rdev)
 494 {
 495         radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
 496         return 0;
 497 }
 498
 499 void radeon_combios_fini(struct radeon_device *rdev)
 500 {
 501 }
 502
 503 /* if we get transitioned to only one device, tak VGA back */
 504 static unsigned int radeon_vga_set_decode(void *cookie, bool state)
 505 {
 506         struct radeon_device *rdev = cookie;
 507         radeon_vga_set_state(rdev, state);
 508         if (state)
 509                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 510                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 511         else
 512                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 513 }
 514
 515 void radeon_agp_disable(struct radeon_device *rdev)
 516 {
 517         rdev->flags &= ~RADEON_IS_AGP;
 518         if (rdev->family >= CHIP_R600) {
 519                 DRM_INFO("Forcing AGP to PCIE mode\n");
 520                 rdev->flags |= RADEON_IS_PCIE;
 521         } else if (rdev->family >= CHIP_RV515 ||
 522                         rdev->family == CHIP_RV380 ||
 523                         rdev->family == CHIP_RV410 ||
 524                         rdev->family == CHIP_R423) {
 525                 DRM_INFO("Forcing AGP to PCIE mode\n");
 526                 rdev->flags |= RADEON_IS_PCIE;
 527                 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
 528                 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
 529         } else {
 530                 DRM_INFO("Forcing AGP to PCI mode\n");
 531                 rdev->flags |= RADEON_IS_PCI;
 532                 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
 533                 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
 534         }
 535 }
 536
 537 /*
 538  * Radeon device.
 539  */
 540 int radeon_device_init(struct radeon_device *rdev,
 541                        struct drm_device *ddev,
 542                        struct pci_dev *pdev,
 543                        uint32_t flags)
 544 {
 545         int r;
 546         int dma_bits;
 547
 548         DRM_INFO("radeon: Initializing kernel modesetting.\n");
 549         rdev->shutdown = false;
 550         rdev->dev = &pdev->dev;
 551         rdev->ddev = ddev;
 552         rdev->pdev = pdev;
 553         rdev->flags = flags;
 554         rdev->family = flags & RADEON_FAMILY_MASK;
 555         rdev->is_atom_bios = false;
 556         rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
 557         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 558         rdev->gpu_lockup = false;
 559         rdev->accel_working = false;
 560         /* mutex initialization are all done here so we
 561          * can recall function without having locking issues */
 562         mutex_init(&rdev->cs_mutex);
 563         mutex_init(&rdev->ib_pool.mutex);
 564         mutex_init(&rdev->cp.mutex);
 565         if (rdev->family >= CHIP_R600)
 566                 spin_lock_init(&rdev->ih.lock);
 567         rwlock_init(&rdev->fence_drv.lock);
 568         INIT_LIST_HEAD(&rdev->gem.objects);
 569
 570         /* Set asic functions */
 571         r = radeon_asic_init(rdev);
 572         if (r) {
 573                 return r;
 574         }
 575
 576         if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
 577                 radeon_agp_disable(rdev);
 578         }
 579
 580         /* set DMA mask + need_dma32 flags.
 581          * PCIE - can handle 40-bits.
 582          * IGP - can handle 40-bits (in theory)
 583          * AGP - generally dma32 is safest
 584          * PCI - only dma32
 585          */
 586         rdev->need_dma32 = false;
 587         if (rdev->flags & RADEON_IS_AGP)
 588                 rdev->need_dma32 = true;
 589         if (rdev->flags & RADEON_IS_PCI)
 590                 rdev->need_dma32 = true;
 591
 592         dma_bits = rdev->need_dma32 ? 32 : 40;
 593         r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
 594         if (r) {
 595                 printk(KERN_WARNING "radeon: No suitable DMA available.\n");
 596         }
 597
 598         /* Registers mapping */
 599         /* TODO: block userspace mapping of io register */
 600         rdev->rmmio_base = drm_get_resource_start(rdev->ddev, 2);
 601         rdev->rmmio_size = drm_get_resource_len(rdev->ddev, 2);
 602         rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
 603         if (rdev->rmmio == NULL) {
 604                 return -ENOMEM;
 605         }
 606         DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
 607         DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
 608
 609         /* if we have > 1 VGA cards, then disable the radeon VGA resources */
 610         /* this will fail for cards that aren't VGA class devices, just
 611          * ignore it */
 612         vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
 613
 614         r = radeon_init(rdev);
 615         if (r)
 616                 return r;
 617
 618         if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
 619                 /* Acceleration not working on AGP card try again
 620                  * with fallback to PCI or PCIE GART
 621                  */
 622                 radeon_gpu_reset(rdev);
 623                 radeon_fini(rdev);
 624                 radeon_agp_disable(rdev);
 625                 r = radeon_init(rdev);
 626                 if (r)
 627                         return r;
 628         }
 629         if (radeon_testing) {
 630                 radeon_test_moves(rdev);
 631         }
 632         if (radeon_benchmarking) {
 633                 radeon_benchmark(rdev);
 634         }
 635         return 0;
 636 }
 637
 638 void radeon_device_fini(struct radeon_device *rdev)
 639 {
 640         DRM_INFO("radeon: finishing device.\n");
 641         rdev->shutdown = true;
 642         radeon_fini(rdev);
 643         vga_client_register(rdev->pdev, NULL, NULL, NULL);
 644         iounmap(rdev->rmmio);
 645         rdev->rmmio = NULL;
 646 }
 647
 648
 649 /*
 650  * Suspend & resume.
 651  */
 652 int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
 653 {
 654         struct radeon_device *rdev = dev->dev_private;
 655         struct drm_crtc *crtc;
 656
 657         if (dev == NULL || rdev == NULL) {
 658                 return -ENODEV;
 659         }
 660         if (state.event == PM_EVENT_PRETHAW) {
 661                 return 0;
 662         }
 663         /* unpin the front buffers */
 664         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 665                 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb);
 666                 struct radeon_object *robj;
 667
 668                 if (rfb == NULL || rfb->obj == NULL) {
 669                         continue;
 670                 }
 671                 robj = rfb->obj->driver_private;
 672                 if (robj != rdev->fbdev_robj) {
 673                         radeon_object_unpin(robj);
 674                 }
 675         }
 676         /* evict vram memory */
 677         radeon_object_evict_vram(rdev);
 678         /* wait for gpu to finish processing current batch */
 679         radeon_fence_wait_last(rdev);
 680
 681         radeon_save_bios_scratch_regs(rdev);
 682
 683         radeon_suspend(rdev);
 684         /* evict remaining vram memory */
 685         radeon_object_evict_vram(rdev);
 686
 687         pci_save_state(dev->pdev);
 688         if (state.event == PM_EVENT_SUSPEND) {
 689                 /* Shut down the device */
 690                 pci_disable_device(dev->pdev);
 691                 pci_set_power_state(dev->pdev, PCI_D3hot);
 692         }
 693         acquire_console_sem();
 694         fb_set_suspend(rdev->fbdev_info, 1);
 695         release_console_sem();
 696         return 0;
 697 }
 698
 699 int radeon_resume_kms(struct drm_device *dev)
 700 {
 701         struct radeon_device *rdev = dev->dev_private;
 702
 703         acquire_console_sem();
 704         pci_set_power_state(dev->pdev, PCI_D0);
 705         pci_restore_state(dev->pdev);
 706         if (pci_enable_device(dev->pdev)) {
 707                 release_console_sem();
 708                 return -1;
 709         }
 710         pci_set_master(dev->pdev);
 711         /* resume AGP if in use */
 712         radeon_agp_resume(rdev);
 713         radeon_resume(rdev);
 714         radeon_restore_bios_scratch_regs(rdev);
 715         fb_set_suspend(rdev->fbdev_info, 0);
 716         release_console_sem();
 717
 718         /* blat the mode back in */
 719         drm_helper_resume_force_mode(dev);
 720         return 0;
 721 }
 722
 723
 724 /*
 725  * Debugfs
 726  */
 727 struct radeon_debugfs {
 728         struct drm_info_list    *files;
 729         unsigned                num_files;
 730 };
 731 static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_NUM_FILES];
 732 static unsigned _radeon_debugfs_count = 0;
 733
 734 int radeon_debugfs_add_files(struct radeon_device *rdev,
 735                              struct drm_info_list *files,
 736                              unsigned nfiles)
 737 {
 738         unsigned i;
 739
 740         for (i = 0; i < _radeon_debugfs_count; i++) {
 741                 if (_radeon_debugfs[i].files == files) {
 742                         /* Already registered */
 743                         return 0;
 744                 }
 745         }
 746         if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) {
 747                 DRM_ERROR("Reached maximum number of debugfs files.\n");
 748                 DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n");
 749                 return -EINVAL;
 750         }
 751         _radeon_debugfs[_radeon_debugfs_count].files = files;
 752         _radeon_debugfs[_radeon_debugfs_count].num_files = nfiles;
 753         _radeon_debugfs_count++;
 754 #if defined(CONFIG_DEBUG_FS)
 755         drm_debugfs_create_files(files, nfiles,
 756                                  rdev->ddev->control->debugfs_root,
 757                                  rdev->ddev->control);
 758         drm_debugfs_create_files(files, nfiles,
 759                                  rdev->ddev->primary->debugfs_root,
 760                                  rdev->ddev->primary);
 761 #endif
 762         return 0;
 763 }
 764
 765 #if defined(CONFIG_DEBUG_FS)
 766 int radeon_debugfs_init(struct drm_minor *minor)
 767 {
 768         return 0;
 769 }
 770
 771 void radeon_debugfs_cleanup(struct drm_minor *minor)
 772 {
 773         unsigned i;
 774
 775         for (i = 0; i < _radeon_debugfs_count; i++) {
 776                 drm_debugfs_remove_files(_radeon_debugfs[i].files,
 777                                          _radeon_debugfs[i].num_files, minor);
 778         }
 779 }
 780 #endif