SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/radeon_atombios.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "radeon_drm.h"
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include "atom-bits.h"
  32
  33 /* from radeon_encoder.c */
  34 extern uint32_t
  35 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
  36                       uint8_t dac);
  37 extern void radeon_link_encoder_connector(struct drm_device *dev);
  38 extern void
  39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id,
  40                         uint32_t supported_device);
  41
  42 /* from radeon_connector.c */
  43 extern void
  44 radeon_add_atom_connector(struct drm_device *dev,
  45                           uint32_t connector_id,
  46                           uint32_t supported_device,
  47                           int connector_type,
  48                           struct radeon_i2c_bus_rec *i2c_bus,
  49                           bool linkb, uint32_t igp_lane_info,
  50                           uint16_t connector_object_id,
  51                           struct radeon_hpd *hpd);
  52
  53 /* from radeon_legacy_encoder.c */
  54 extern void
  55 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
  56                           uint32_t supported_device);
  57
  58 union atom_supported_devices {
  59         struct _ATOM_SUPPORTED_DEVICES_INFO info;
  60         struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
  61         struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
  62 };
  63
  64 static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
  65                                                                uint8_t id)
  66 {
  67         struct atom_context *ctx = rdev->mode_info.atom_context;
  68         ATOM_GPIO_I2C_ASSIGMENT *gpio;
  69         struct radeon_i2c_bus_rec i2c;
  70         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
  71         struct _ATOM_GPIO_I2C_INFO *i2c_info;
  72         uint16_t data_offset;
  73         int i;
  74
  75         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
  76         i2c.valid = false;
  77
  78         atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset);
  79
  80         i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
  81
  82
  83         for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
  84                 gpio = &i2c_info->asGPIO_Info[i];
  85
  86                 if (gpio->sucI2cId.ucAccess == id) {
  87                         i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
  88                         i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
  89                         i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
  90                         i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
  91                         i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
  92                         i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
  93                         i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
  94                         i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
  95                         i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
  96                         i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
  97                         i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
  98                         i2c.en_data_mask = (1 << gpio->ucDataEnShift);
  99                         i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
 100                         i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
 101                         i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
 102                         i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
 103
 104                         if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
 105                                 i2c.hw_capable = true;
 106                         else
 107                                 i2c.hw_capable = false;
 108
 109                         if (gpio->sucI2cId.ucAccess == 0xa0)
 110                                 i2c.mm_i2c = true;
 111                         else
 112                                 i2c.mm_i2c = false;
 113
 114                         i2c.i2c_id = gpio->sucI2cId.ucAccess;
 115
 116                         i2c.valid = true;
 117                         break;
 118                 }
 119         }
 120
 121         return i2c;
 122 }
 123
 124 static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
 125                                                         u8 id)
 126 {
 127         struct atom_context *ctx = rdev->mode_info.atom_context;
 128         struct radeon_gpio_rec gpio;
 129         int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
 130         struct _ATOM_GPIO_PIN_LUT *gpio_info;
 131         ATOM_GPIO_PIN_ASSIGNMENT *pin;
 132         u16 data_offset, size;
 133         int i, num_indices;
 134
 135         memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
 136         gpio.valid = false;
 137
 138         atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset);
 139
 140         gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
 141
 142         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
 143
 144         for (i = 0; i < num_indices; i++) {
 145                 pin = &gpio_info->asGPIO_Pin[i];
 146                 if (id == pin->ucGPIO_ID) {
 147                         gpio.id = pin->ucGPIO_ID;
 148                         gpio.reg = pin->usGpioPin_AIndex * 4;
 149                         gpio.mask = (1 << pin->ucGpioPinBitShift);
 150                         gpio.valid = true;
 151                         break;
 152                 }
 153         }
 154
 155         return gpio;
 156 }
 157
 158 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
 159                                                             struct radeon_gpio_rec *gpio)
 160 {
 161         struct radeon_hpd hpd;
 162         hpd.gpio = *gpio;
 163         if (gpio->reg == AVIVO_DC_GPIO_HPD_A) {
 164                 switch(gpio->mask) {
 165                 case (1 << 0):
 166                         hpd.hpd = RADEON_HPD_1;
 167                         break;
 168                 case (1 << 8):
 169                         hpd.hpd = RADEON_HPD_2;
 170                         break;
 171                 case (1 << 16):
 172                         hpd.hpd = RADEON_HPD_3;
 173                         break;
 174                 case (1 << 24):
 175                         hpd.hpd = RADEON_HPD_4;
 176                         break;
 177                 case (1 << 26):
 178                         hpd.hpd = RADEON_HPD_5;
 179                         break;
 180                 case (1 << 28):
 181                         hpd.hpd = RADEON_HPD_6;
 182                         break;
 183                 default:
 184                         hpd.hpd = RADEON_HPD_NONE;
 185                         break;
 186                 }
 187         } else
 188                 hpd.hpd = RADEON_HPD_NONE;
 189         return hpd;
 190 }
 191
 192 static bool radeon_atom_apply_quirks(struct drm_device *dev,
 193                                      uint32_t supported_device,
 194                                      int *connector_type,
 195                                      struct radeon_i2c_bus_rec *i2c_bus,
 196                                      uint16_t *line_mux,
 197                                      struct radeon_hpd *hpd)
 198 {
 199
 200         /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
 201         if ((dev->pdev->device == 0x791e) &&
 202             (dev->pdev->subsystem_vendor == 0x1043) &&
 203             (dev->pdev->subsystem_device == 0x826d)) {
 204                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 205                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 206                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 207         }
 208
 209         /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
 210         if ((dev->pdev->device == 0x7941) &&
 211             (dev->pdev->subsystem_vendor == 0x147b) &&
 212             (dev->pdev->subsystem_device == 0x2412)) {
 213                 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
 214                         return false;
 215         }
 216
 217         /* Falcon NW laptop lists vga ddc line for LVDS */
 218         if ((dev->pdev->device == 0x5653) &&
 219             (dev->pdev->subsystem_vendor == 0x1462) &&
 220             (dev->pdev->subsystem_device == 0x0291)) {
 221                 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
 222                         i2c_bus->valid = false;
 223                         *line_mux = 53;
 224                 }
 225         }
 226
 227         /* HIS X1300 is DVI+VGA, not DVI+DVI */
 228         if ((dev->pdev->device == 0x7146) &&
 229             (dev->pdev->subsystem_vendor == 0x17af) &&
 230             (dev->pdev->subsystem_device == 0x2058)) {
 231                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 232                         return false;
 233         }
 234
 235         /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
 236         if ((dev->pdev->device == 0x7142) &&
 237             (dev->pdev->subsystem_vendor == 0x1458) &&
 238             (dev->pdev->subsystem_device == 0x2134)) {
 239                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 240                         return false;
 241         }
 242
 243
 244         /* Funky macbooks */
 245         if ((dev->pdev->device == 0x71C5) &&
 246             (dev->pdev->subsystem_vendor == 0x106b) &&
 247             (dev->pdev->subsystem_device == 0x0080)) {
 248                 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
 249                     (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
 250                         return false;
 251         }
 252
 253         /* ASUS HD 3600 XT board lists the DVI port as HDMI */
 254         if ((dev->pdev->device == 0x9598) &&
 255             (dev->pdev->subsystem_vendor == 0x1043) &&
 256             (dev->pdev->subsystem_device == 0x01da)) {
 257                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 258                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 259                 }
 260         }
 261
 262         /* ASUS HD 3450 board lists the DVI port as HDMI */
 263         if ((dev->pdev->device == 0x95C5) &&
 264             (dev->pdev->subsystem_vendor == 0x1043) &&
 265             (dev->pdev->subsystem_device == 0x01e2)) {
 266                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 267                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 268                 }
 269         }
 270
 271         /* some BIOSes seem to report DAC on HDMI - usually this is a board with
 272          * HDMI + VGA reporting as HDMI
 273          */
 274         if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 275                 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
 276                         *connector_type = DRM_MODE_CONNECTOR_VGA;
 277                         *line_mux = 0;
 278                 }
 279         }
 280
 281         /* Acer laptop reports DVI-D as DVI-I */
 282         if ((dev->pdev->device == 0x95c4) &&
 283             (dev->pdev->subsystem_vendor == 0x1025) &&
 284             (dev->pdev->subsystem_device == 0x013c)) {
 285                 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
 286                     (supported_device == ATOM_DEVICE_DFP1_SUPPORT))
 287                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 288         }
 289
 290         return true;
 291 }
 292
 293 const int supported_devices_connector_convert[] = {
 294         DRM_MODE_CONNECTOR_Unknown,
 295         DRM_MODE_CONNECTOR_VGA,
 296         DRM_MODE_CONNECTOR_DVII,
 297         DRM_MODE_CONNECTOR_DVID,
 298         DRM_MODE_CONNECTOR_DVIA,
 299         DRM_MODE_CONNECTOR_SVIDEO,
 300         DRM_MODE_CONNECTOR_Composite,
 301         DRM_MODE_CONNECTOR_LVDS,
 302         DRM_MODE_CONNECTOR_Unknown,
 303         DRM_MODE_CONNECTOR_Unknown,
 304         DRM_MODE_CONNECTOR_HDMIA,
 305         DRM_MODE_CONNECTOR_HDMIB,
 306         DRM_MODE_CONNECTOR_Unknown,
 307         DRM_MODE_CONNECTOR_Unknown,
 308         DRM_MODE_CONNECTOR_9PinDIN,
 309         DRM_MODE_CONNECTOR_DisplayPort
 310 };
 311
 312 const uint16_t supported_devices_connector_object_id_convert[] = {
 313         CONNECTOR_OBJECT_ID_NONE,
 314         CONNECTOR_OBJECT_ID_VGA,
 315         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
 316         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
 317         CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
 318         CONNECTOR_OBJECT_ID_COMPOSITE,
 319         CONNECTOR_OBJECT_ID_SVIDEO,
 320         CONNECTOR_OBJECT_ID_LVDS,
 321         CONNECTOR_OBJECT_ID_9PIN_DIN,
 322         CONNECTOR_OBJECT_ID_9PIN_DIN,
 323         CONNECTOR_OBJECT_ID_DISPLAYPORT,
 324         CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
 325         CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
 326         CONNECTOR_OBJECT_ID_SVIDEO
 327 };
 328
 329 const int object_connector_convert[] = {
 330         DRM_MODE_CONNECTOR_Unknown,
 331         DRM_MODE_CONNECTOR_DVII,
 332         DRM_MODE_CONNECTOR_DVII,
 333         DRM_MODE_CONNECTOR_DVID,
 334         DRM_MODE_CONNECTOR_DVID,
 335         DRM_MODE_CONNECTOR_VGA,
 336         DRM_MODE_CONNECTOR_Composite,
 337         DRM_MODE_CONNECTOR_SVIDEO,
 338         DRM_MODE_CONNECTOR_Unknown,
 339         DRM_MODE_CONNECTOR_Unknown,
 340         DRM_MODE_CONNECTOR_9PinDIN,
 341         DRM_MODE_CONNECTOR_Unknown,
 342         DRM_MODE_CONNECTOR_HDMIA,
 343         DRM_MODE_CONNECTOR_HDMIB,
 344         DRM_MODE_CONNECTOR_LVDS,
 345         DRM_MODE_CONNECTOR_9PinDIN,
 346         DRM_MODE_CONNECTOR_Unknown,
 347         DRM_MODE_CONNECTOR_Unknown,
 348         DRM_MODE_CONNECTOR_Unknown,
 349         DRM_MODE_CONNECTOR_DisplayPort,
 350         DRM_MODE_CONNECTOR_eDP,
 351         DRM_MODE_CONNECTOR_Unknown
 352 };
 353
 354 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
 355 {
 356         struct radeon_device *rdev = dev->dev_private;
 357         struct radeon_mode_info *mode_info = &rdev->mode_info;
 358         struct atom_context *ctx = mode_info->atom_context;
 359         int index = GetIndexIntoMasterTable(DATA, Object_Header);
 360         u16 size, data_offset;
 361         u8 frev, crev;
 362         ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
 363         ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
 364         ATOM_OBJECT_HEADER *obj_header;
 365         int i, j, path_size, device_support;
 366         int connector_type;
 367         u16 igp_lane_info, conn_id, connector_object_id;
 368         bool linkb;
 369         struct radeon_i2c_bus_rec ddc_bus;
 370         struct radeon_gpio_rec gpio;
 371         struct radeon_hpd hpd;
 372
 373         atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
 374
 375         if (data_offset == 0)
 376                 return false;
 377
 378         if (crev < 2)
 379                 return false;
 380
 381         obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
 382         path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
 383             (ctx->bios + data_offset +
 384              le16_to_cpu(obj_header->usDisplayPathTableOffset));
 385         con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
 386             (ctx->bios + data_offset +
 387              le16_to_cpu(obj_header->usConnectorObjectTableOffset));
 388         device_support = le16_to_cpu(obj_header->usDeviceSupport);
 389
 390         path_size = 0;
 391         for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
 392                 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
 393                 ATOM_DISPLAY_OBJECT_PATH *path;
 394                 addr += path_size;
 395                 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
 396                 path_size += le16_to_cpu(path->usSize);
 397                 linkb = false;
 398                 if (device_support & le16_to_cpu(path->usDeviceTag)) {
 399                         uint8_t con_obj_id, con_obj_num, con_obj_type;
 400
 401                         con_obj_id =
 402                             (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
 403                             >> OBJECT_ID_SHIFT;
 404                         con_obj_num =
 405                             (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
 406                             >> ENUM_ID_SHIFT;
 407                         con_obj_type =
 408                             (le16_to_cpu(path->usConnObjectId) &
 409                              OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 410
 411                         /* TODO CV support */
 412                         if (le16_to_cpu(path->usDeviceTag) ==
 413                                 ATOM_DEVICE_CV_SUPPORT)
 414                                 continue;
 415
 416                         /* IGP chips */
 417                         if ((rdev->flags & RADEON_IS_IGP) &&
 418                             (con_obj_id ==
 419                              CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
 420                                 uint16_t igp_offset = 0;
 421                                 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
 422
 423                                 index =
 424                                     GetIndexIntoMasterTable(DATA,
 425                                                             IntegratedSystemInfo);
 426
 427                                 atom_parse_data_header(ctx, index, &size, &frev,
 428                                                        &crev, &igp_offset);
 429
 430                                 if (crev >= 2) {
 431                                         igp_obj =
 432                                             (ATOM_INTEGRATED_SYSTEM_INFO_V2
 433                                              *) (ctx->bios + igp_offset);
 434
 435                                         if (igp_obj) {
 436                                                 uint32_t slot_config, ct;
 437
 438                                                 if (con_obj_num == 1)
 439                                                         slot_config =
 440                                                             igp_obj->
 441                                                             ulDDISlot1Config;
 442                                                 else
 443                                                         slot_config =
 444                                                             igp_obj->
 445                                                             ulDDISlot2Config;
 446
 447                                                 ct = (slot_config >> 16) & 0xff;
 448                                                 connector_type =
 449                                                     object_connector_convert
 450                                                     [ct];
 451                                                 connector_object_id = ct;
 452                                                 igp_lane_info =
 453                                                     slot_config & 0xffff;
 454                                         } else
 455                                                 continue;
 456                                 } else
 457                                         continue;
 458                         } else {
 459                                 igp_lane_info = 0;
 460                                 connector_type =
 461                                     object_connector_convert[con_obj_id];
 462                                 connector_object_id = con_obj_id;
 463                         }
 464
 465                         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
 466                                 continue;
 467
 468                         for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2);
 469                              j++) {
 470                                 uint8_t enc_obj_id, enc_obj_num, enc_obj_type;
 471
 472                                 enc_obj_id =
 473                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 474                                      OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 475                                 enc_obj_num =
 476                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 477                                      ENUM_ID_MASK) >> ENUM_ID_SHIFT;
 478                                 enc_obj_type =
 479                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 480                                      OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 481
 482                                 /* FIXME: add support for router objects */
 483                                 if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
 484                                         if (enc_obj_num == 2)
 485                                                 linkb = true;
 486                                         else
 487                                                 linkb = false;
 488
 489                                         radeon_add_atom_encoder(dev,
 490                                                                 enc_obj_id,
 491                                                                 le16_to_cpu
 492                                                                 (path->
 493                                                                  usDeviceTag));
 494
 495                                 }
 496                         }
 497
 498                         /* look up gpio for ddc, hpd */
 499                         if ((le16_to_cpu(path->usDeviceTag) &
 500                              (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
 501                                 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
 502                                         if (le16_to_cpu(path->usConnObjectId) ==
 503                                             le16_to_cpu(con_obj->asObjects[j].
 504                                                         usObjectID)) {
 505                                                 ATOM_COMMON_RECORD_HEADER
 506                                                     *record =
 507                                                     (ATOM_COMMON_RECORD_HEADER
 508                                                      *)
 509                                                     (ctx->bios + data_offset +
 510                                                      le16_to_cpu(con_obj->
 511                                                                  asObjects[j].
 512                                                                  usRecordOffset));
 513                                                 ATOM_I2C_RECORD *i2c_record;
 514                                                 ATOM_HPD_INT_RECORD *hpd_record;
 515                                                 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 516                                                 hpd.hpd = RADEON_HPD_NONE;
 517
 518                                                 while (record->ucRecordType > 0
 519                                                        && record->
 520                                                        ucRecordType <=
 521                                                        ATOM_MAX_OBJECT_RECORD_NUMBER) {
 522                                                         switch (record->ucRecordType) {
 523                                                         case ATOM_I2C_RECORD_TYPE:
 524                                                                 i2c_record =
 525                                                                     (ATOM_I2C_RECORD *)
 526                                                                         record;
 527                                                                 i2c_config =
 528                                                                         (ATOM_I2C_ID_CONFIG_ACCESS *)
 529                                                                         &i2c_record->sucI2cId;
 530                                                                 ddc_bus = radeon_lookup_i2c_gpio(rdev,
 531                                                                                                  i2c_config->
 532                                                                                                  ucAccess);
 533                                                                 break;
 534                                                         case ATOM_HPD_INT_RECORD_TYPE:
 535                                                                 hpd_record =
 536                                                                         (ATOM_HPD_INT_RECORD *)
 537                                                                         record;
 538                                                                 gpio = radeon_lookup_gpio(rdev,
 539                                                                                           hpd_record->ucHPDIntGPIOID);
 540                                                                 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
 541                                                                 hpd.plugged_state = hpd_record->ucPlugged_PinState;
 542                                                                 break;
 543                                                         }
 544                                                         record =
 545                                                             (ATOM_COMMON_RECORD_HEADER
 546                                                              *) ((char *)record
 547                                                                  +
 548                                                                  record->
 549                                                                  ucRecordSize);
 550                                                 }
 551                                                 break;
 552                                         }
 553                                 }
 554                         } else {
 555                                 hpd.hpd = RADEON_HPD_NONE;
 556                                 ddc_bus.valid = false;
 557                         }
 558
 559                         conn_id = le16_to_cpu(path->usConnObjectId);
 560
 561                         if (!radeon_atom_apply_quirks
 562                             (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
 563                              &ddc_bus, &conn_id, &hpd))
 564                                 continue;
 565
 566                         radeon_add_atom_connector(dev,
 567                                                   conn_id,
 568                                                   le16_to_cpu(path->
 569                                                               usDeviceTag),
 570                                                   connector_type, &ddc_bus,
 571                                                   linkb, igp_lane_info,
 572                                                   connector_object_id,
 573                                                   &hpd);
 574
 575                 }
 576         }
 577
 578         radeon_link_encoder_connector(dev);
 579
 580         return true;
 581 }
 582
 583 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
 584                                                  int connector_type,
 585                                                  uint16_t devices)
 586 {
 587         struct radeon_device *rdev = dev->dev_private;
 588
 589         if (rdev->flags & RADEON_IS_IGP) {
 590                 return supported_devices_connector_object_id_convert
 591                         [connector_type];
 592         } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
 593                     (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
 594                    (devices & ATOM_DEVICE_DFP2_SUPPORT))  {
 595                 struct radeon_mode_info *mode_info = &rdev->mode_info;
 596                 struct atom_context *ctx = mode_info->atom_context;
 597                 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
 598                 uint16_t size, data_offset;
 599                 uint8_t frev, crev;
 600                 ATOM_XTMDS_INFO *xtmds;
 601
 602                 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
 603                 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
 604
 605                 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
 606                         if (connector_type == DRM_MODE_CONNECTOR_DVII)
 607                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
 608                         else
 609                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
 610                 } else {
 611                         if (connector_type == DRM_MODE_CONNECTOR_DVII)
 612                                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
 613                         else
 614                                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
 615                 }
 616         } else {
 617                 return supported_devices_connector_object_id_convert
 618                         [connector_type];
 619         }
 620 }
 621
 622 struct bios_connector {
 623         bool valid;
 624         uint16_t line_mux;
 625         uint16_t devices;
 626         int connector_type;
 627         struct radeon_i2c_bus_rec ddc_bus;
 628         struct radeon_hpd hpd;
 629 };
 630
 631 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
 632                                                                  drm_device
 633                                                                  *dev)
 634 {
 635         struct radeon_device *rdev = dev->dev_private;
 636         struct radeon_mode_info *mode_info = &rdev->mode_info;
 637         struct atom_context *ctx = mode_info->atom_context;
 638         int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
 639         uint16_t size, data_offset;
 640         uint8_t frev, crev;
 641         uint16_t device_support;
 642         uint8_t dac;
 643         union atom_supported_devices *supported_devices;
 644         int i, j, max_device;
 645         struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE];
 646
 647         atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
 648
 649         supported_devices =
 650             (union atom_supported_devices *)(ctx->bios + data_offset);
 651
 652         device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
 653
 654         if (frev > 1)
 655                 max_device = ATOM_MAX_SUPPORTED_DEVICE;
 656         else
 657                 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
 658
 659         for (i = 0; i < max_device; i++) {
 660                 ATOM_CONNECTOR_INFO_I2C ci =
 661                     supported_devices->info.asConnInfo[i];
 662
 663                 bios_connectors[i].valid = false;
 664
 665                 if (!(device_support & (1 << i))) {
 666                         continue;
 667                 }
 668
 669                 if (i == ATOM_DEVICE_CV_INDEX) {
 670                         DRM_DEBUG("Skipping Component Video\n");
 671                         continue;
 672                 }
 673
 674                 bios_connectors[i].connector_type =
 675                     supported_devices_connector_convert[ci.sucConnectorInfo.
 676                                                         sbfAccess.
 677                                                         bfConnectorType];
 678
 679                 if (bios_connectors[i].connector_type ==
 680                     DRM_MODE_CONNECTOR_Unknown)
 681                         continue;
 682
 683                 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
 684
 685                 bios_connectors[i].line_mux =
 686                         ci.sucI2cId.ucAccess;
 687
 688                 /* give tv unique connector ids */
 689                 if (i == ATOM_DEVICE_TV1_INDEX) {
 690                         bios_connectors[i].ddc_bus.valid = false;
 691                         bios_connectors[i].line_mux = 50;
 692                 } else if (i == ATOM_DEVICE_TV2_INDEX) {
 693                         bios_connectors[i].ddc_bus.valid = false;
 694                         bios_connectors[i].line_mux = 51;
 695                 } else if (i == ATOM_DEVICE_CV_INDEX) {
 696                         bios_connectors[i].ddc_bus.valid = false;
 697                         bios_connectors[i].line_mux = 52;
 698                 } else
 699                         bios_connectors[i].ddc_bus =
 700                             radeon_lookup_i2c_gpio(rdev,
 701                                                    bios_connectors[i].line_mux);
 702
 703                 if ((crev > 1) && (frev > 1)) {
 704                         u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
 705                         switch (isb) {
 706                         case 0x4:
 707                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
 708                                 break;
 709                         case 0xa:
 710                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
 711                                 break;
 712                         default:
 713                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
 714                                 break;
 715                         }
 716                 } else {
 717                         if (i == ATOM_DEVICE_DFP1_INDEX)
 718                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
 719                         else if (i == ATOM_DEVICE_DFP2_INDEX)
 720                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
 721                         else
 722                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
 723                 }
 724
 725                 /* Always set the connector type to VGA for CRT1/CRT2. if they are
 726                  * shared with a DVI port, we'll pick up the DVI connector when we
 727                  * merge the outputs.  Some bioses incorrectly list VGA ports as DVI.
 728                  */
 729                 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
 730                         bios_connectors[i].connector_type =
 731                             DRM_MODE_CONNECTOR_VGA;
 732
 733                 if (!radeon_atom_apply_quirks
 734                     (dev, (1 << i), &bios_connectors[i].connector_type,
 735                      &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
 736                      &bios_connectors[i].hpd))
 737                         continue;
 738
 739                 bios_connectors[i].valid = true;
 740                 bios_connectors[i].devices = (1 << i);
 741
 742                 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
 743                         radeon_add_atom_encoder(dev,
 744                                                 radeon_get_encoder_id(dev,
 745                                                                       (1 << i),
 746                                                                       dac),
 747                                                 (1 << i));
 748                 else
 749                         radeon_add_legacy_encoder(dev,
 750                                                   radeon_get_encoder_id(dev,
 751                                                                         (1 << i),
 752                                                                         dac),
 753                                                   (1 << i));
 754         }
 755
 756         /* combine shared connectors */
 757         for (i = 0; i < max_device; i++) {
 758                 if (bios_connectors[i].valid) {
 759                         for (j = 0; j < max_device; j++) {
 760                                 if (bios_connectors[j].valid && (i != j)) {
 761                                         if (bios_connectors[i].line_mux ==
 762                                             bios_connectors[j].line_mux) {
 763                                                 /* make sure not to combine LVDS */
 764                                                 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 765                                                         bios_connectors[i].line_mux = 53;
 766                                                         bios_connectors[i].ddc_bus.valid = false;
 767                                                         continue;
 768                                                 }
 769                                                 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 770                                                         bios_connectors[j].line_mux = 53;
 771                                                         bios_connectors[j].ddc_bus.valid = false;
 772                                                         continue;
 773                                                 }
 774                                                 /* combine analog and digital for DVI-I */
 775                                                 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
 776                                                      (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
 777                                                     ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
 778                                                      (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
 779                                                         bios_connectors[i].devices |=
 780                                                                 bios_connectors[j].devices;
 781                                                         bios_connectors[i].connector_type =
 782                                                                 DRM_MODE_CONNECTOR_DVII;
 783                                                         if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
 784                                                                 bios_connectors[i].hpd =
 785                                                                         bios_connectors[j].hpd;
 786                                                         bios_connectors[j].valid = false;
 787                                                 }
 788                                         }
 789                                 }
 790                         }
 791                 }
 792         }
 793
 794         /* add the connectors */
 795         for (i = 0; i < max_device; i++) {
 796                 if (bios_connectors[i].valid) {
 797                         uint16_t connector_object_id =
 798                                 atombios_get_connector_object_id(dev,
 799                                                       bios_connectors[i].connector_type,
 800                                                       bios_connectors[i].devices);
 801                         radeon_add_atom_connector(dev,
 802                                                   bios_connectors[i].line_mux,
 803                                                   bios_connectors[i].devices,
 804                                                   bios_connectors[i].
 805                                                   connector_type,
 806                                                   &bios_connectors[i].ddc_bus,
 807                                                   false, 0,
 808                                                   connector_object_id,
 809                                                   &bios_connectors[i].hpd);
 810                 }
 811         }
 812
 813         radeon_link_encoder_connector(dev);
 814
 815         return true;
 816 }
 817
 818 union firmware_info {
 819         ATOM_FIRMWARE_INFO info;
 820         ATOM_FIRMWARE_INFO_V1_2 info_12;
 821         ATOM_FIRMWARE_INFO_V1_3 info_13;
 822         ATOM_FIRMWARE_INFO_V1_4 info_14;
 823 };
 824
 825 bool radeon_atom_get_clock_info(struct drm_device *dev)
 826 {
 827         struct radeon_device *rdev = dev->dev_private;
 828         struct radeon_mode_info *mode_info = &rdev->mode_info;
 829         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
 830         union firmware_info *firmware_info;
 831         uint8_t frev, crev;
 832         struct radeon_pll *p1pll = &rdev->clock.p1pll;
 833         struct radeon_pll *p2pll = &rdev->clock.p2pll;
 834         struct radeon_pll *spll = &rdev->clock.spll;
 835         struct radeon_pll *mpll = &rdev->clock.mpll;
 836         uint16_t data_offset;
 837
 838         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
 839                                &crev, &data_offset);
 840
 841         firmware_info =
 842             (union firmware_info *)(mode_info->atom_context->bios +
 843                                     data_offset);
 844
 845         if (firmware_info) {
 846                 /* pixel clocks */
 847                 p1pll->reference_freq =
 848                     le16_to_cpu(firmware_info->info.usReferenceClock);
 849                 p1pll->reference_div = 0;
 850
 851                 if (crev < 2)
 852                         p1pll->pll_out_min =
 853                                 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
 854                 else
 855                         p1pll->pll_out_min =
 856                                 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
 857                 p1pll->pll_out_max =
 858                     le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
 859
 860                 if (p1pll->pll_out_min == 0) {
 861                         if (ASIC_IS_AVIVO(rdev))
 862                                 p1pll->pll_out_min = 64800;
 863                         else
 864                                 p1pll->pll_out_min = 20000;
 865                 } else if (p1pll->pll_out_min > 64800) {
 866                         /* Limiting the pll output range is a good thing generally as
 867                          * it limits the number of possible pll combinations for a given
 868                          * frequency presumably to the ones that work best on each card.
 869                          * However, certain duallink DVI monitors seem to like
 870                          * pll combinations that would be limited by this at least on
 871                          * pre-DCE 3.0 r6xx hardware.  This might need to be adjusted per
 872                          * family.
 873                          */
 874                         if (!radeon_new_pll)
 875                                 p1pll->pll_out_min = 64800;
 876                 }
 877
 878                 p1pll->pll_in_min =
 879                     le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
 880                 p1pll->pll_in_max =
 881                     le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
 882
 883                 *p2pll = *p1pll;
 884
 885                 /* system clock */
 886                 spll->reference_freq =
 887                     le16_to_cpu(firmware_info->info.usReferenceClock);
 888                 spll->reference_div = 0;
 889
 890                 spll->pll_out_min =
 891                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
 892                 spll->pll_out_max =
 893                     le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
 894
 895                 /* ??? */
 896                 if (spll->pll_out_min == 0) {
 897                         if (ASIC_IS_AVIVO(rdev))
 898                                 spll->pll_out_min = 64800;
 899                         else
 900                                 spll->pll_out_min = 20000;
 901                 }
 902
 903                 spll->pll_in_min =
 904                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
 905                 spll->pll_in_max =
 906                     le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
 907
 908                 /* memory clock */
 909                 mpll->reference_freq =
 910                     le16_to_cpu(firmware_info->info.usReferenceClock);
 911                 mpll->reference_div = 0;
 912
 913                 mpll->pll_out_min =
 914                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
 915                 mpll->pll_out_max =
 916                     le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
 917
 918                 /* ??? */
 919                 if (mpll->pll_out_min == 0) {
 920                         if (ASIC_IS_AVIVO(rdev))
 921                                 mpll->pll_out_min = 64800;
 922                         else
 923                                 mpll->pll_out_min = 20000;
 924                 }
 925
 926                 mpll->pll_in_min =
 927                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
 928                 mpll->pll_in_max =
 929                     le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
 930
 931                 rdev->clock.default_sclk =
 932                     le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
 933                 rdev->clock.default_mclk =
 934                     le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
 935
 936                 return true;
 937         }
 938         return false;
 939 }
 940
 941 union igp_info {
 942         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
 943         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
 944 };
 945
 946 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
 947 {
 948         struct radeon_mode_info *mode_info = &rdev->mode_info;
 949         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
 950         union igp_info *igp_info;
 951         u8 frev, crev;
 952         u16 data_offset;
 953
 954         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
 955                                &crev, &data_offset);
 956
 957         igp_info = (union igp_info *)(mode_info->atom_context->bios +
 958                                       data_offset);
 959
 960         if (igp_info) {
 961                 switch (crev) {
 962                 case 1:
 963                         if (igp_info->info.ucMemoryType & 0xf0)
 964                                 return true;
 965                         break;
 966                 case 2:
 967                         if (igp_info->info_2.ucMemoryType & 0x0f)
 968                                 return true;
 969                         break;
 970                 default:
 971                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
 972                         break;
 973                 }
 974         }
 975         return false;
 976 }
 977
 978 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
 979                                    struct radeon_encoder_int_tmds *tmds)
 980 {
 981         struct drm_device *dev = encoder->base.dev;
 982         struct radeon_device *rdev = dev->dev_private;
 983         struct radeon_mode_info *mode_info = &rdev->mode_info;
 984         int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
 985         uint16_t data_offset;
 986         struct _ATOM_TMDS_INFO *tmds_info;
 987         uint8_t frev, crev;
 988         uint16_t maxfreq;
 989         int i;
 990
 991         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
 992                                &crev, &data_offset);
 993
 994         tmds_info =
 995             (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
 996                                        data_offset);
 997
 998         if (tmds_info) {
 999                 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1000                 for (i = 0; i < 4; i++) {
1001                         tmds->tmds_pll[i].freq =
1002                             le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1003                         tmds->tmds_pll[i].value =
1004                             tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1005                         tmds->tmds_pll[i].value |=
1006                             (tmds_info->asMiscInfo[i].
1007                              ucPLL_VCO_Gain & 0x3f) << 6;
1008                         tmds->tmds_pll[i].value |=
1009                             (tmds_info->asMiscInfo[i].
1010                              ucPLL_DutyCycle & 0xf) << 12;
1011                         tmds->tmds_pll[i].value |=
1012                             (tmds_info->asMiscInfo[i].
1013                              ucPLL_VoltageSwing & 0xf) << 16;
1014
1015                         DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
1016                                   tmds->tmds_pll[i].freq,
1017                                   tmds->tmds_pll[i].value);
1018
1019                         if (maxfreq == tmds->tmds_pll[i].freq) {
1020                                 tmds->tmds_pll[i].freq = 0xffffffff;
1021                                 break;
1022                         }
1023                 }
1024                 return true;
1025         }
1026         return false;
1027 }
1028
1029 static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct
1030                                                           radeon_encoder
1031                                                           *encoder,
1032                                                           int id)
1033 {
1034         struct drm_device *dev = encoder->base.dev;
1035         struct radeon_device *rdev = dev->dev_private;
1036         struct radeon_mode_info *mode_info = &rdev->mode_info;
1037         int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1038         uint16_t data_offset;
1039         struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1040         uint8_t frev, crev;
1041         struct radeon_atom_ss *ss = NULL;
1042         int i;
1043
1044         if (id > ATOM_MAX_SS_ENTRY)
1045                 return NULL;
1046
1047         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
1048                                &crev, &data_offset);
1049
1050         ss_info =
1051             (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1052
1053         if (ss_info) {
1054                 ss =
1055                     kzalloc(sizeof(struct radeon_atom_ss), GFP_KERNEL);
1056
1057                 if (!ss)
1058                         return NULL;
1059
1060                 for (i = 0; i < ATOM_MAX_SS_ENTRY; i++) {
1061                         if (ss_info->asSS_Info[i].ucSS_Id == id) {
1062                                 ss->percentage =
1063                                         le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1064                                 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1065                                 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1066                                 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1067                                 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1068                                 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1069                                 break;
1070                         }
1071                 }
1072         }
1073         return ss;
1074 }
1075
1076 union lvds_info {
1077         struct _ATOM_LVDS_INFO info;
1078         struct _ATOM_LVDS_INFO_V12 info_12;
1079 };
1080
1081 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1082                                                               radeon_encoder
1083                                                               *encoder)
1084 {
1085         struct drm_device *dev = encoder->base.dev;
1086         struct radeon_device *rdev = dev->dev_private;
1087         struct radeon_mode_info *mode_info = &rdev->mode_info;
1088         int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1089         uint16_t data_offset, misc;
1090         union lvds_info *lvds_info;
1091         uint8_t frev, crev;
1092         struct radeon_encoder_atom_dig *lvds = NULL;
1093
1094         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
1095                                &crev, &data_offset);
1096
1097         lvds_info =
1098             (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1099
1100         if (lvds_info) {
1101                 lvds =
1102                     kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1103
1104                 if (!lvds)
1105                         return NULL;
1106
1107                 lvds->native_mode.clock =
1108                     le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1109                 lvds->native_mode.hdisplay =
1110                     le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1111                 lvds->native_mode.vdisplay =
1112                     le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1113                 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1114                         le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1115                 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1116                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1117                 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1118                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1119                 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1120                         le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1121                 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1122                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1123                 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1124                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1125                 lvds->panel_pwr_delay =
1126                     le16_to_cpu(lvds_info->info.usOffDelayInMs);
1127                 lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
1128
1129                 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1130                 if (misc & ATOM_VSYNC_POLARITY)
1131                         lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1132                 if (misc & ATOM_HSYNC_POLARITY)
1133                         lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1134                 if (misc & ATOM_COMPOSITESYNC)
1135                         lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1136                 if (misc & ATOM_INTERLACE)
1137                         lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1138                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1139                         lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1140
1141                 /* set crtc values */
1142                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1143
1144                 lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id);
1145
1146                 encoder->native_mode = lvds->native_mode;
1147         }
1148         return lvds;
1149 }
1150
1151 struct radeon_encoder_primary_dac *
1152 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1153 {
1154         struct drm_device *dev = encoder->base.dev;
1155         struct radeon_device *rdev = dev->dev_private;
1156         struct radeon_mode_info *mode_info = &rdev->mode_info;
1157         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1158         uint16_t data_offset;
1159         struct _COMPASSIONATE_DATA *dac_info;
1160         uint8_t frev, crev;
1161         uint8_t bg, dac;
1162         struct radeon_encoder_primary_dac *p_dac = NULL;
1163
1164         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
1165
1166         dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
1167
1168         if (dac_info) {
1169                 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1170
1171                 if (!p_dac)
1172                         return NULL;
1173
1174                 bg = dac_info->ucDAC1_BG_Adjustment;
1175                 dac = dac_info->ucDAC1_DAC_Adjustment;
1176                 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1177
1178         }
1179         return p_dac;
1180 }
1181
1182 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1183                                 struct drm_display_mode *mode)
1184 {
1185         struct radeon_mode_info *mode_info = &rdev->mode_info;
1186         ATOM_ANALOG_TV_INFO *tv_info;
1187         ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1188         ATOM_DTD_FORMAT *dtd_timings;
1189         int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1190         u8 frev, crev;
1191         u16 data_offset, misc;
1192
1193         atom_parse_data_header(mode_info->atom_context, data_index, NULL, &frev, &crev, &data_offset);
1194
1195         switch (crev) {
1196         case 1:
1197                 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1198                 if (index > MAX_SUPPORTED_TV_TIMING)
1199                         return false;
1200
1201                 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1202                 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1203                 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1204                 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1205                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1206
1207                 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1208                 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1209                 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1210                 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1211                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1212
1213                 mode->flags = 0;
1214                 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1215                 if (misc & ATOM_VSYNC_POLARITY)
1216                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1217                 if (misc & ATOM_HSYNC_POLARITY)
1218                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1219                 if (misc & ATOM_COMPOSITESYNC)
1220                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1221                 if (misc & ATOM_INTERLACE)
1222                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1223                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1224                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1225
1226                 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1227
1228                 if (index == 1) {
1229                         /* PAL timings appear to have wrong values for totals */
1230                         mode->crtc_htotal -= 1;
1231                         mode->crtc_vtotal -= 1;
1232                 }
1233                 break;
1234         case 2:
1235                 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1236                 if (index > MAX_SUPPORTED_TV_TIMING_V1_2)
1237                         return false;
1238
1239                 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1240                 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1241                         le16_to_cpu(dtd_timings->usHBlanking_Time);
1242                 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1243                 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1244                         le16_to_cpu(dtd_timings->usHSyncOffset);
1245                 mode->crtc_hsync_end = mode->crtc_hsync_start +
1246                         le16_to_cpu(dtd_timings->usHSyncWidth);
1247
1248                 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1249                         le16_to_cpu(dtd_timings->usVBlanking_Time);
1250                 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1251                 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1252                         le16_to_cpu(dtd_timings->usVSyncOffset);
1253                 mode->crtc_vsync_end = mode->crtc_vsync_start +
1254                         le16_to_cpu(dtd_timings->usVSyncWidth);
1255
1256                 mode->flags = 0;
1257                 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1258                 if (misc & ATOM_VSYNC_POLARITY)
1259                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1260                 if (misc & ATOM_HSYNC_POLARITY)
1261                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1262                 if (misc & ATOM_COMPOSITESYNC)
1263                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1264                 if (misc & ATOM_INTERLACE)
1265                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1266                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1267                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1268
1269                 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1270                 break;
1271         }
1272         return true;
1273 }
1274
1275 enum radeon_tv_std
1276 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1277 {
1278         struct radeon_mode_info *mode_info = &rdev->mode_info;
1279         int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1280         uint16_t data_offset;
1281         uint8_t frev, crev;
1282         struct _ATOM_ANALOG_TV_INFO *tv_info;
1283         enum radeon_tv_std tv_std = TV_STD_NTSC;
1284
1285         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
1286
1287         tv_info = (struct _ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1288
1289         switch (tv_info->ucTV_BootUpDefaultStandard) {
1290         case ATOM_TV_NTSC:
1291                 tv_std = TV_STD_NTSC;
1292                 DRM_INFO("Default TV standard: NTSC\n");
1293                 break;
1294         case ATOM_TV_NTSCJ:
1295                 tv_std = TV_STD_NTSC_J;
1296                 DRM_INFO("Default TV standard: NTSC-J\n");
1297                 break;
1298         case ATOM_TV_PAL:
1299                 tv_std = TV_STD_PAL;
1300                 DRM_INFO("Default TV standard: PAL\n");
1301                 break;
1302         case ATOM_TV_PALM:
1303                 tv_std = TV_STD_PAL_M;
1304                 DRM_INFO("Default TV standard: PAL-M\n");
1305                 break;
1306         case ATOM_TV_PALN:
1307                 tv_std = TV_STD_PAL_N;
1308                 DRM_INFO("Default TV standard: PAL-N\n");
1309                 break;
1310         case ATOM_TV_PALCN:
1311                 tv_std = TV_STD_PAL_CN;
1312                 DRM_INFO("Default TV standard: PAL-CN\n");
1313                 break;
1314         case ATOM_TV_PAL60:
1315                 tv_std = TV_STD_PAL_60;
1316                 DRM_INFO("Default TV standard: PAL-60\n");
1317                 break;
1318         case ATOM_TV_SECAM:
1319                 tv_std = TV_STD_SECAM;
1320                 DRM_INFO("Default TV standard: SECAM\n");
1321                 break;
1322         default:
1323                 tv_std = TV_STD_NTSC;
1324                 DRM_INFO("Unknown TV standard; defaulting to NTSC\n");
1325                 break;
1326         }
1327         return tv_std;
1328 }
1329
1330 struct radeon_encoder_tv_dac *
1331 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1332 {
1333         struct drm_device *dev = encoder->base.dev;
1334         struct radeon_device *rdev = dev->dev_private;
1335         struct radeon_mode_info *mode_info = &rdev->mode_info;
1336         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1337         uint16_t data_offset;
1338         struct _COMPASSIONATE_DATA *dac_info;
1339         uint8_t frev, crev;
1340         uint8_t bg, dac;
1341         struct radeon_encoder_tv_dac *tv_dac = NULL;
1342
1343         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
1344
1345         dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
1346
1347         if (dac_info) {
1348                 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1349
1350                 if (!tv_dac)
1351                         return NULL;
1352
1353                 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1354                 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1355                 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1356
1357                 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1358                 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1359                 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1360
1361                 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1362                 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1363                 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1364
1365                 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1366         }
1367         return tv_dac;
1368 }
1369
1370 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
1371 {
1372         DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
1373         int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
1374
1375         args.ucEnable = enable;
1376
1377         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1378 }
1379
1380 void radeon_atom_static_pwrmgt_setup(struct radeon_device *rdev, int enable)
1381 {
1382         ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION args;
1383         int index = GetIndexIntoMasterTable(COMMAND, EnableASIC_StaticPwrMgt);
1384
1385         args.ucEnable = enable;
1386
1387         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1388 }
1389
1390 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
1391 {
1392         GET_ENGINE_CLOCK_PS_ALLOCATION args;
1393         int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
1394
1395         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1396         return args.ulReturnEngineClock;
1397 }
1398
1399 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
1400 {
1401         GET_MEMORY_CLOCK_PS_ALLOCATION args;
1402         int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
1403
1404         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1405         return args.ulReturnMemoryClock;
1406 }
1407
1408 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
1409                                   uint32_t eng_clock)
1410 {
1411         SET_ENGINE_CLOCK_PS_ALLOCATION args;
1412         int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
1413
1414         args.ulTargetEngineClock = eng_clock;   /* 10 khz */
1415
1416         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1417 }
1418
1419 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
1420                                   uint32_t mem_clock)
1421 {
1422         SET_MEMORY_CLOCK_PS_ALLOCATION args;
1423         int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
1424
1425         if (rdev->flags & RADEON_IS_IGP)
1426                 return;
1427
1428         args.ulTargetMemoryClock = mem_clock;   /* 10 khz */
1429
1430         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1431 }
1432
1433 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
1434 {
1435         struct radeon_device *rdev = dev->dev_private;
1436         uint32_t bios_2_scratch, bios_6_scratch;
1437
1438         if (rdev->family >= CHIP_R600) {
1439                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
1440                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1441         } else {
1442                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
1443                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1444         }
1445
1446         /* let the bios control the backlight */
1447         bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
1448
1449         /* tell the bios not to handle mode switching */
1450         bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
1451
1452         if (rdev->family >= CHIP_R600) {
1453                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
1454                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1455         } else {
1456                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
1457                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1458         }
1459
1460 }
1461
1462 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
1463 {
1464         uint32_t scratch_reg;
1465         int i;
1466
1467         if (rdev->family >= CHIP_R600)
1468                 scratch_reg = R600_BIOS_0_SCRATCH;
1469         else
1470                 scratch_reg = RADEON_BIOS_0_SCRATCH;
1471
1472         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1473                 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
1474 }
1475
1476 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
1477 {
1478         uint32_t scratch_reg;
1479         int i;
1480
1481         if (rdev->family >= CHIP_R600)
1482                 scratch_reg = R600_BIOS_0_SCRATCH;
1483         else
1484                 scratch_reg = RADEON_BIOS_0_SCRATCH;
1485
1486         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1487                 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
1488 }
1489
1490 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
1491 {
1492         struct drm_device *dev = encoder->dev;
1493         struct radeon_device *rdev = dev->dev_private;
1494         uint32_t bios_6_scratch;
1495
1496         if (rdev->family >= CHIP_R600)
1497                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1498         else
1499                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1500
1501         if (lock)
1502                 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
1503         else
1504                 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
1505
1506         if (rdev->family >= CHIP_R600)
1507                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1508         else
1509                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1510 }
1511
1512 /* at some point we may want to break this out into individual functions */
1513 void
1514 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
1515                                        struct drm_encoder *encoder,
1516                                        bool connected)
1517 {
1518         struct drm_device *dev = connector->dev;
1519         struct radeon_device *rdev = dev->dev_private;
1520         struct radeon_connector *radeon_connector =
1521             to_radeon_connector(connector);
1522         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1523         uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
1524
1525         if (rdev->family >= CHIP_R600) {
1526                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1527                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
1528                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1529         } else {
1530                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1531                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
1532                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1533         }
1534
1535         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
1536             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
1537                 if (connected) {
1538                         DRM_DEBUG("TV1 connected\n");
1539                         bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
1540                         bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
1541                 } else {
1542                         DRM_DEBUG("TV1 disconnected\n");
1543                         bios_0_scratch &= ~ATOM_S0_TV1_MASK;
1544                         bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
1545                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
1546                 }
1547         }
1548         if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
1549             (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
1550                 if (connected) {
1551                         DRM_DEBUG("CV connected\n");
1552                         bios_3_scratch |= ATOM_S3_CV_ACTIVE;
1553                         bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
1554                 } else {
1555                         DRM_DEBUG("CV disconnected\n");
1556                         bios_0_scratch &= ~ATOM_S0_CV_MASK;
1557                         bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
1558                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
1559                 }
1560         }
1561         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
1562             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
1563                 if (connected) {
1564                         DRM_DEBUG("LCD1 connected\n");
1565                         bios_0_scratch |= ATOM_S0_LCD1;
1566                         bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
1567                         bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
1568                 } else {
1569                         DRM_DEBUG("LCD1 disconnected\n");
1570                         bios_0_scratch &= ~ATOM_S0_LCD1;
1571                         bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
1572                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
1573                 }
1574         }
1575         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
1576             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
1577                 if (connected) {
1578                         DRM_DEBUG("CRT1 connected\n");
1579                         bios_0_scratch |= ATOM_S0_CRT1_COLOR;
1580                         bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
1581                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
1582                 } else {
1583                         DRM_DEBUG("CRT1 disconnected\n");
1584                         bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
1585                         bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
1586                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
1587                 }
1588         }
1589         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
1590             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
1591                 if (connected) {
1592                         DRM_DEBUG("CRT2 connected\n");
1593                         bios_0_scratch |= ATOM_S0_CRT2_COLOR;
1594                         bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
1595                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
1596                 } else {
1597                         DRM_DEBUG("CRT2 disconnected\n");
1598                         bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
1599                         bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
1600                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
1601                 }
1602         }
1603         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
1604             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
1605                 if (connected) {
1606                         DRM_DEBUG("DFP1 connected\n");
1607                         bios_0_scratch |= ATOM_S0_DFP1;
1608                         bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
1609                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
1610                 } else {
1611                         DRM_DEBUG("DFP1 disconnected\n");
1612                         bios_0_scratch &= ~ATOM_S0_DFP1;
1613                         bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
1614                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
1615                 }
1616         }
1617         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
1618             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
1619                 if (connected) {
1620                         DRM_DEBUG("DFP2 connected\n");
1621                         bios_0_scratch |= ATOM_S0_DFP2;
1622                         bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
1623                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
1624                 } else {
1625                         DRM_DEBUG("DFP2 disconnected\n");
1626                         bios_0_scratch &= ~ATOM_S0_DFP2;
1627                         bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
1628                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
1629                 }
1630         }
1631         if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
1632             (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
1633                 if (connected) {
1634                         DRM_DEBUG("DFP3 connected\n");
1635                         bios_0_scratch |= ATOM_S0_DFP3;
1636                         bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
1637                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
1638                 } else {
1639                         DRM_DEBUG("DFP3 disconnected\n");
1640                         bios_0_scratch &= ~ATOM_S0_DFP3;
1641                         bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
1642                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
1643                 }
1644         }
1645         if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
1646             (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
1647                 if (connected) {
1648                         DRM_DEBUG("DFP4 connected\n");
1649                         bios_0_scratch |= ATOM_S0_DFP4;
1650                         bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
1651                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
1652                 } else {
1653                         DRM_DEBUG("DFP4 disconnected\n");
1654                         bios_0_scratch &= ~ATOM_S0_DFP4;
1655                         bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
1656                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
1657                 }
1658         }
1659         if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
1660             (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
1661                 if (connected) {
1662                         DRM_DEBUG("DFP5 connected\n");
1663                         bios_0_scratch |= ATOM_S0_DFP5;
1664                         bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
1665                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
1666                 } else {
1667                         DRM_DEBUG("DFP5 disconnected\n");
1668                         bios_0_scratch &= ~ATOM_S0_DFP5;
1669                         bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
1670                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
1671                 }
1672         }
1673
1674         if (rdev->family >= CHIP_R600) {
1675                 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
1676                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
1677                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1678         } else {
1679                 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
1680                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
1681                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1682         }
1683 }
1684
1685 void
1686 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
1687 {
1688         struct drm_device *dev = encoder->dev;
1689         struct radeon_device *rdev = dev->dev_private;
1690         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1691         uint32_t bios_3_scratch;
1692
1693         if (rdev->family >= CHIP_R600)
1694                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
1695         else
1696                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
1697
1698         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
1699                 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
1700                 bios_3_scratch |= (crtc << 18);
1701         }
1702         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
1703                 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
1704                 bios_3_scratch |= (crtc << 24);
1705         }
1706         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1707                 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
1708                 bios_3_scratch |= (crtc << 16);
1709         }
1710         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1711                 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
1712                 bios_3_scratch |= (crtc << 20);
1713         }
1714         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1715                 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
1716                 bios_3_scratch |= (crtc << 17);
1717         }
1718         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
1719                 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
1720                 bios_3_scratch |= (crtc << 19);
1721         }
1722         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
1723                 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
1724                 bios_3_scratch |= (crtc << 23);
1725         }
1726         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
1727                 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
1728                 bios_3_scratch |= (crtc << 25);
1729         }
1730
1731         if (rdev->family >= CHIP_R600)
1732                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
1733         else
1734                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
1735 }
1736
1737 void
1738 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
1739 {
1740         struct drm_device *dev = encoder->dev;
1741         struct radeon_device *rdev = dev->dev_private;
1742         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1743         uint32_t bios_2_scratch;
1744
1745         if (rdev->family >= CHIP_R600)
1746                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
1747         else
1748                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
1749
1750         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
1751                 if (on)
1752                         bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
1753                 else
1754                         bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
1755         }
1756         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
1757                 if (on)
1758                         bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
1759                 else
1760                         bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
1761         }
1762         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1763                 if (on)
1764                         bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
1765                 else
1766                         bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
1767         }
1768         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1769                 if (on)
1770                         bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
1771                 else
1772                         bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
1773         }
1774         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1775                 if (on)
1776                         bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
1777                 else
1778                         bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
1779         }
1780         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
1781                 if (on)
1782                         bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
1783                 else
1784                         bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
1785         }
1786         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
1787                 if (on)
1788                         bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
1789                 else
1790                         bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
1791         }
1792         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
1793                 if (on)
1794                         bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
1795                 else
1796                         bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
1797         }
1798         if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
1799                 if (on)
1800                         bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
1801                 else
1802                         bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
1803         }
1804         if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
1805                 if (on)
1806                         bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
1807                 else
1808                         bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
1809         }
1810
1811         if (rdev->family >= CHIP_R600)
1812                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
1813         else
1814                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
1815 }