SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/radeon_atombios.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "radeon_drm.h"
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include "atom-bits.h"
  32
  33 /* from radeon_encoder.c */
  34 extern uint32_t
  35 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
  36                       uint8_t dac);
  37 extern void radeon_link_encoder_connector(struct drm_device *dev);
  38 extern void
  39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id,
  40                         uint32_t supported_device);
  41
  42 /* from radeon_connector.c */
  43 extern void
  44 radeon_add_atom_connector(struct drm_device *dev,
  45                           uint32_t connector_id,
  46                           uint32_t supported_device,
  47                           int connector_type,
  48                           struct radeon_i2c_bus_rec *i2c_bus,
  49                           bool linkb, uint32_t igp_lane_info,
  50                           uint16_t connector_object_id,
  51                           struct radeon_hpd *hpd);
  52
  53 /* from radeon_legacy_encoder.c */
  54 extern void
  55 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
  56                           uint32_t supported_device);
  57
  58 union atom_supported_devices {
  59         struct _ATOM_SUPPORTED_DEVICES_INFO info;
  60         struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
  61         struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
  62 };
  63
  64 static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
  65                                                                uint8_t id)
  66 {
  67         struct atom_context *ctx = rdev->mode_info.atom_context;
  68         ATOM_GPIO_I2C_ASSIGMENT *gpio;
  69         struct radeon_i2c_bus_rec i2c;
  70         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
  71         struct _ATOM_GPIO_I2C_INFO *i2c_info;
  72         uint16_t data_offset, size;
  73         int i, num_indices;
  74
  75         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
  76         i2c.valid = false;
  77
  78         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
  79                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
  80
  81                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
  82                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
  83
  84                 for (i = 0; i < num_indices; i++) {
  85                         gpio = &i2c_info->asGPIO_Info[i];
  86
  87                         if (gpio->sucI2cId.ucAccess == id) {
  88                                 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
  89                                 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
  90                                 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
  91                                 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
  92                                 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
  93                                 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
  94                                 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
  95                                 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
  96                                 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
  97                                 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
  98                                 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
  99                                 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
 100                                 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
 101                                 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
 102                                 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
 103                                 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
 104
 105                                 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
 106                                         i2c.hw_capable = true;
 107                                 else
 108                                         i2c.hw_capable = false;
 109
 110                                 if (gpio->sucI2cId.ucAccess == 0xa0)
 111                                         i2c.mm_i2c = true;
 112                                 else
 113                                         i2c.mm_i2c = false;
 114
 115                                 i2c.i2c_id = gpio->sucI2cId.ucAccess;
 116
 117                                 i2c.valid = true;
 118                                 break;
 119                         }
 120                 }
 121         }
 122
 123         return i2c;
 124 }
 125
 126 static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
 127                                                         u8 id)
 128 {
 129         struct atom_context *ctx = rdev->mode_info.atom_context;
 130         struct radeon_gpio_rec gpio;
 131         int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
 132         struct _ATOM_GPIO_PIN_LUT *gpio_info;
 133         ATOM_GPIO_PIN_ASSIGNMENT *pin;
 134         u16 data_offset, size;
 135         int i, num_indices;
 136
 137         memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
 138         gpio.valid = false;
 139
 140         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 141                 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
 142
 143                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 144                         sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
 145
 146                 for (i = 0; i < num_indices; i++) {
 147                         pin = &gpio_info->asGPIO_Pin[i];
 148                         if (id == pin->ucGPIO_ID) {
 149                                 gpio.id = pin->ucGPIO_ID;
 150                                 gpio.reg = pin->usGpioPin_AIndex * 4;
 151                                 gpio.mask = (1 << pin->ucGpioPinBitShift);
 152                                 gpio.valid = true;
 153                                 break;
 154                         }
 155                 }
 156         }
 157
 158         return gpio;
 159 }
 160
 161 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
 162                                                             struct radeon_gpio_rec *gpio)
 163 {
 164         struct radeon_hpd hpd;
 165         u32 reg;
 166
 167         if (ASIC_IS_DCE4(rdev))
 168                 reg = EVERGREEN_DC_GPIO_HPD_A;
 169         else
 170                 reg = AVIVO_DC_GPIO_HPD_A;
 171
 172         hpd.gpio = *gpio;
 173         if (gpio->reg == reg) {
 174                 switch(gpio->mask) {
 175                 case (1 << 0):
 176                         hpd.hpd = RADEON_HPD_1;
 177                         break;
 178                 case (1 << 8):
 179                         hpd.hpd = RADEON_HPD_2;
 180                         break;
 181                 case (1 << 16):
 182                         hpd.hpd = RADEON_HPD_3;
 183                         break;
 184                 case (1 << 24):
 185                         hpd.hpd = RADEON_HPD_4;
 186                         break;
 187                 case (1 << 26):
 188                         hpd.hpd = RADEON_HPD_5;
 189                         break;
 190                 case (1 << 28):
 191                         hpd.hpd = RADEON_HPD_6;
 192                         break;
 193                 default:
 194                         hpd.hpd = RADEON_HPD_NONE;
 195                         break;
 196                 }
 197         } else
 198                 hpd.hpd = RADEON_HPD_NONE;
 199         return hpd;
 200 }
 201
 202 static bool radeon_atom_apply_quirks(struct drm_device *dev,
 203                                      uint32_t supported_device,
 204                                      int *connector_type,
 205                                      struct radeon_i2c_bus_rec *i2c_bus,
 206                                      uint16_t *line_mux,
 207                                      struct radeon_hpd *hpd)
 208 {
 209
 210         /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
 211         if ((dev->pdev->device == 0x791e) &&
 212             (dev->pdev->subsystem_vendor == 0x1043) &&
 213             (dev->pdev->subsystem_device == 0x826d)) {
 214                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 215                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 216                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 217         }
 218
 219         /* Asrock RS600 board lists the DVI port as HDMI */
 220         if ((dev->pdev->device == 0x7941) &&
 221             (dev->pdev->subsystem_vendor == 0x1849) &&
 222             (dev->pdev->subsystem_device == 0x7941)) {
 223                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 224                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 225                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 226         }
 227
 228         /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
 229         if ((dev->pdev->device == 0x7941) &&
 230             (dev->pdev->subsystem_vendor == 0x147b) &&
 231             (dev->pdev->subsystem_device == 0x2412)) {
 232                 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
 233                         return false;
 234         }
 235
 236         /* Falcon NW laptop lists vga ddc line for LVDS */
 237         if ((dev->pdev->device == 0x5653) &&
 238             (dev->pdev->subsystem_vendor == 0x1462) &&
 239             (dev->pdev->subsystem_device == 0x0291)) {
 240                 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
 241                         i2c_bus->valid = false;
 242                         *line_mux = 53;
 243                 }
 244         }
 245
 246         /* HIS X1300 is DVI+VGA, not DVI+DVI */
 247         if ((dev->pdev->device == 0x7146) &&
 248             (dev->pdev->subsystem_vendor == 0x17af) &&
 249             (dev->pdev->subsystem_device == 0x2058)) {
 250                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 251                         return false;
 252         }
 253
 254         /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
 255         if ((dev->pdev->device == 0x7142) &&
 256             (dev->pdev->subsystem_vendor == 0x1458) &&
 257             (dev->pdev->subsystem_device == 0x2134)) {
 258                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 259                         return false;
 260         }
 261
 262
 263         /* Funky macbooks */
 264         if ((dev->pdev->device == 0x71C5) &&
 265             (dev->pdev->subsystem_vendor == 0x106b) &&
 266             (dev->pdev->subsystem_device == 0x0080)) {
 267                 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
 268                     (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
 269                         return false;
 270                 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
 271                         *line_mux = 0x90;
 272         }
 273
 274         /* ASUS HD 3600 XT board lists the DVI port as HDMI */
 275         if ((dev->pdev->device == 0x9598) &&
 276             (dev->pdev->subsystem_vendor == 0x1043) &&
 277             (dev->pdev->subsystem_device == 0x01da)) {
 278                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 279                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 280                 }
 281         }
 282
 283         /* ASUS HD 3450 board lists the DVI port as HDMI */
 284         if ((dev->pdev->device == 0x95C5) &&
 285             (dev->pdev->subsystem_vendor == 0x1043) &&
 286             (dev->pdev->subsystem_device == 0x01e2)) {
 287                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 288                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 289                 }
 290         }
 291
 292         /* some BIOSes seem to report DAC on HDMI - usually this is a board with
 293          * HDMI + VGA reporting as HDMI
 294          */
 295         if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 296                 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
 297                         *connector_type = DRM_MODE_CONNECTOR_VGA;
 298                         *line_mux = 0;
 299                 }
 300         }
 301
 302         /* Acer laptop reports DVI-D as DVI-I */
 303         if ((dev->pdev->device == 0x95c4) &&
 304             (dev->pdev->subsystem_vendor == 0x1025) &&
 305             (dev->pdev->subsystem_device == 0x013c)) {
 306                 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
 307                     (supported_device == ATOM_DEVICE_DFP1_SUPPORT))
 308                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 309         }
 310
 311         /* XFX Pine Group device rv730 reports no VGA DDC lines
 312          * even though they are wired up to record 0x93
 313          */
 314         if ((dev->pdev->device == 0x9498) &&
 315             (dev->pdev->subsystem_vendor == 0x1682) &&
 316             (dev->pdev->subsystem_device == 0x2452)) {
 317                 struct radeon_device *rdev = dev->dev_private;
 318                 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
 319         }
 320         return true;
 321 }
 322
 323 const int supported_devices_connector_convert[] = {
 324         DRM_MODE_CONNECTOR_Unknown,
 325         DRM_MODE_CONNECTOR_VGA,
 326         DRM_MODE_CONNECTOR_DVII,
 327         DRM_MODE_CONNECTOR_DVID,
 328         DRM_MODE_CONNECTOR_DVIA,
 329         DRM_MODE_CONNECTOR_SVIDEO,
 330         DRM_MODE_CONNECTOR_Composite,
 331         DRM_MODE_CONNECTOR_LVDS,
 332         DRM_MODE_CONNECTOR_Unknown,
 333         DRM_MODE_CONNECTOR_Unknown,
 334         DRM_MODE_CONNECTOR_HDMIA,
 335         DRM_MODE_CONNECTOR_HDMIB,
 336         DRM_MODE_CONNECTOR_Unknown,
 337         DRM_MODE_CONNECTOR_Unknown,
 338         DRM_MODE_CONNECTOR_9PinDIN,
 339         DRM_MODE_CONNECTOR_DisplayPort
 340 };
 341
 342 const uint16_t supported_devices_connector_object_id_convert[] = {
 343         CONNECTOR_OBJECT_ID_NONE,
 344         CONNECTOR_OBJECT_ID_VGA,
 345         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
 346         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
 347         CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
 348         CONNECTOR_OBJECT_ID_COMPOSITE,
 349         CONNECTOR_OBJECT_ID_SVIDEO,
 350         CONNECTOR_OBJECT_ID_LVDS,
 351         CONNECTOR_OBJECT_ID_9PIN_DIN,
 352         CONNECTOR_OBJECT_ID_9PIN_DIN,
 353         CONNECTOR_OBJECT_ID_DISPLAYPORT,
 354         CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
 355         CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
 356         CONNECTOR_OBJECT_ID_SVIDEO
 357 };
 358
 359 const int object_connector_convert[] = {
 360         DRM_MODE_CONNECTOR_Unknown,
 361         DRM_MODE_CONNECTOR_DVII,
 362         DRM_MODE_CONNECTOR_DVII,
 363         DRM_MODE_CONNECTOR_DVID,
 364         DRM_MODE_CONNECTOR_DVID,
 365         DRM_MODE_CONNECTOR_VGA,
 366         DRM_MODE_CONNECTOR_Composite,
 367         DRM_MODE_CONNECTOR_SVIDEO,
 368         DRM_MODE_CONNECTOR_Unknown,
 369         DRM_MODE_CONNECTOR_Unknown,
 370         DRM_MODE_CONNECTOR_9PinDIN,
 371         DRM_MODE_CONNECTOR_Unknown,
 372         DRM_MODE_CONNECTOR_HDMIA,
 373         DRM_MODE_CONNECTOR_HDMIB,
 374         DRM_MODE_CONNECTOR_LVDS,
 375         DRM_MODE_CONNECTOR_9PinDIN,
 376         DRM_MODE_CONNECTOR_Unknown,
 377         DRM_MODE_CONNECTOR_Unknown,
 378         DRM_MODE_CONNECTOR_Unknown,
 379         DRM_MODE_CONNECTOR_DisplayPort,
 380         DRM_MODE_CONNECTOR_eDP,
 381         DRM_MODE_CONNECTOR_Unknown
 382 };
 383
 384 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
 385 {
 386         struct radeon_device *rdev = dev->dev_private;
 387         struct radeon_mode_info *mode_info = &rdev->mode_info;
 388         struct atom_context *ctx = mode_info->atom_context;
 389         int index = GetIndexIntoMasterTable(DATA, Object_Header);
 390         u16 size, data_offset;
 391         u8 frev, crev;
 392         ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
 393         ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
 394         ATOM_OBJECT_HEADER *obj_header;
 395         int i, j, path_size, device_support;
 396         int connector_type;
 397         u16 igp_lane_info, conn_id, connector_object_id;
 398         bool linkb;
 399         struct radeon_i2c_bus_rec ddc_bus;
 400         struct radeon_gpio_rec gpio;
 401         struct radeon_hpd hpd;
 402
 403         if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
 404                 return false;
 405
 406         if (crev < 2)
 407                 return false;
 408
 409         obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
 410         path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
 411             (ctx->bios + data_offset +
 412              le16_to_cpu(obj_header->usDisplayPathTableOffset));
 413         con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
 414             (ctx->bios + data_offset +
 415              le16_to_cpu(obj_header->usConnectorObjectTableOffset));
 416         device_support = le16_to_cpu(obj_header->usDeviceSupport);
 417
 418         path_size = 0;
 419         for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
 420                 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
 421                 ATOM_DISPLAY_OBJECT_PATH *path;
 422                 addr += path_size;
 423                 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
 424                 path_size += le16_to_cpu(path->usSize);
 425                 linkb = false;
 426                 if (device_support & le16_to_cpu(path->usDeviceTag)) {
 427                         uint8_t con_obj_id, con_obj_num, con_obj_type;
 428
 429                         con_obj_id =
 430                             (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
 431                             >> OBJECT_ID_SHIFT;
 432                         con_obj_num =
 433                             (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
 434                             >> ENUM_ID_SHIFT;
 435                         con_obj_type =
 436                             (le16_to_cpu(path->usConnObjectId) &
 437                              OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 438
 439                         /* TODO CV support */
 440                         if (le16_to_cpu(path->usDeviceTag) ==
 441                                 ATOM_DEVICE_CV_SUPPORT)
 442                                 continue;
 443
 444                         /* IGP chips */
 445                         if ((rdev->flags & RADEON_IS_IGP) &&
 446                             (con_obj_id ==
 447                              CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
 448                                 uint16_t igp_offset = 0;
 449                                 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
 450
 451                                 index =
 452                                     GetIndexIntoMasterTable(DATA,
 453                                                             IntegratedSystemInfo);
 454
 455                                 if (atom_parse_data_header(ctx, index, &size, &frev,
 456                                                            &crev, &igp_offset)) {
 457
 458                                         if (crev >= 2) {
 459                                                 igp_obj =
 460                                                         (ATOM_INTEGRATED_SYSTEM_INFO_V2
 461                                                          *) (ctx->bios + igp_offset);
 462
 463                                                 if (igp_obj) {
 464                                                         uint32_t slot_config, ct;
 465
 466                                                         if (con_obj_num == 1)
 467                                                                 slot_config =
 468                                                                         igp_obj->
 469                                                                         ulDDISlot1Config;
 470                                                         else
 471                                                                 slot_config =
 472                                                                         igp_obj->
 473                                                                         ulDDISlot2Config;
 474
 475                                                         ct = (slot_config >> 16) & 0xff;
 476                                                         connector_type =
 477                                                                 object_connector_convert
 478                                                                 [ct];
 479                                                         connector_object_id = ct;
 480                                                         igp_lane_info =
 481                                                                 slot_config & 0xffff;
 482                                                 } else
 483                                                         continue;
 484                                         } else
 485                                                 continue;
 486                                 } else {
 487                                         igp_lane_info = 0;
 488                                         connector_type =
 489                                                 object_connector_convert[con_obj_id];
 490                                         connector_object_id = con_obj_id;
 491                                 }
 492                         } else {
 493                                 igp_lane_info = 0;
 494                                 connector_type =
 495                                     object_connector_convert[con_obj_id];
 496                                 connector_object_id = con_obj_id;
 497                         }
 498
 499                         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
 500                                 continue;
 501
 502                         for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2);
 503                              j++) {
 504                                 uint8_t enc_obj_id, enc_obj_num, enc_obj_type;
 505
 506                                 enc_obj_id =
 507                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 508                                      OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 509                                 enc_obj_num =
 510                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 511                                      ENUM_ID_MASK) >> ENUM_ID_SHIFT;
 512                                 enc_obj_type =
 513                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 514                                      OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 515
 516                                 /* FIXME: add support for router objects */
 517                                 if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
 518                                         if (enc_obj_num == 2)
 519                                                 linkb = true;
 520                                         else
 521                                                 linkb = false;
 522
 523                                         radeon_add_atom_encoder(dev,
 524                                                                 enc_obj_id,
 525                                                                 le16_to_cpu
 526                                                                 (path->
 527                                                                  usDeviceTag));
 528
 529                                 }
 530                         }
 531
 532                         /* look up gpio for ddc, hpd */
 533                         ddc_bus.valid = false;
 534                         hpd.hpd = RADEON_HPD_NONE;
 535                         if ((le16_to_cpu(path->usDeviceTag) &
 536                              (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
 537                                 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
 538                                         if (le16_to_cpu(path->usConnObjectId) ==
 539                                             le16_to_cpu(con_obj->asObjects[j].
 540                                                         usObjectID)) {
 541                                                 ATOM_COMMON_RECORD_HEADER
 542                                                     *record =
 543                                                     (ATOM_COMMON_RECORD_HEADER
 544                                                      *)
 545                                                     (ctx->bios + data_offset +
 546                                                      le16_to_cpu(con_obj->
 547                                                                  asObjects[j].
 548                                                                  usRecordOffset));
 549                                                 ATOM_I2C_RECORD *i2c_record;
 550                                                 ATOM_HPD_INT_RECORD *hpd_record;
 551                                                 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 552                                                 hpd.hpd = RADEON_HPD_NONE;
 553
 554                                                 while (record->ucRecordType > 0
 555                                                        && record->
 556                                                        ucRecordType <=
 557                                                        ATOM_MAX_OBJECT_RECORD_NUMBER) {
 558                                                         switch (record->ucRecordType) {
 559                                                         case ATOM_I2C_RECORD_TYPE:
 560                                                                 i2c_record =
 561                                                                     (ATOM_I2C_RECORD *)
 562                                                                         record;
 563                                                                 i2c_config =
 564                                                                         (ATOM_I2C_ID_CONFIG_ACCESS *)
 565                                                                         &i2c_record->sucI2cId;
 566                                                                 ddc_bus = radeon_lookup_i2c_gpio(rdev,
 567                                                                                                  i2c_config->
 568                                                                                                  ucAccess);
 569                                                                 break;
 570                                                         case ATOM_HPD_INT_RECORD_TYPE:
 571                                                                 hpd_record =
 572                                                                         (ATOM_HPD_INT_RECORD *)
 573                                                                         record;
 574                                                                 gpio = radeon_lookup_gpio(rdev,
 575                                                                                           hpd_record->ucHPDIntGPIOID);
 576                                                                 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
 577                                                                 hpd.plugged_state = hpd_record->ucPlugged_PinState;
 578                                                                 break;
 579                                                         }
 580                                                         record =
 581                                                             (ATOM_COMMON_RECORD_HEADER
 582                                                              *) ((char *)record
 583                                                                  +
 584                                                                  record->
 585                                                                  ucRecordSize);
 586                                                 }
 587                                                 break;
 588                                         }
 589                                 }
 590                         }
 591
 592                         /* needed for aux chan transactions */
 593                         ddc_bus.hpd_id = hpd.hpd ? (hpd.hpd - 1) : 0;
 594
 595                         conn_id = le16_to_cpu(path->usConnObjectId);
 596
 597                         if (!radeon_atom_apply_quirks
 598                             (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
 599                              &ddc_bus, &conn_id, &hpd))
 600                                 continue;
 601
 602                         radeon_add_atom_connector(dev,
 603                                                   conn_id,
 604                                                   le16_to_cpu(path->
 605                                                               usDeviceTag),
 606                                                   connector_type, &ddc_bus,
 607                                                   linkb, igp_lane_info,
 608                                                   connector_object_id,
 609                                                   &hpd);
 610
 611                 }
 612         }
 613
 614         radeon_link_encoder_connector(dev);
 615
 616         return true;
 617 }
 618
 619 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
 620                                                  int connector_type,
 621                                                  uint16_t devices)
 622 {
 623         struct radeon_device *rdev = dev->dev_private;
 624
 625         if (rdev->flags & RADEON_IS_IGP) {
 626                 return supported_devices_connector_object_id_convert
 627                         [connector_type];
 628         } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
 629                     (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
 630                    (devices & ATOM_DEVICE_DFP2_SUPPORT))  {
 631                 struct radeon_mode_info *mode_info = &rdev->mode_info;
 632                 struct atom_context *ctx = mode_info->atom_context;
 633                 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
 634                 uint16_t size, data_offset;
 635                 uint8_t frev, crev;
 636                 ATOM_XTMDS_INFO *xtmds;
 637
 638                 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
 639                         xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
 640
 641                         if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
 642                                 if (connector_type == DRM_MODE_CONNECTOR_DVII)
 643                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
 644                                 else
 645                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
 646                         } else {
 647                                 if (connector_type == DRM_MODE_CONNECTOR_DVII)
 648                                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
 649                                 else
 650                                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
 651                         }
 652                 } else
 653                         return supported_devices_connector_object_id_convert
 654                                 [connector_type];
 655         } else {
 656                 return supported_devices_connector_object_id_convert
 657                         [connector_type];
 658         }
 659 }
 660
 661 struct bios_connector {
 662         bool valid;
 663         uint16_t line_mux;
 664         uint16_t devices;
 665         int connector_type;
 666         struct radeon_i2c_bus_rec ddc_bus;
 667         struct radeon_hpd hpd;
 668 };
 669
 670 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
 671                                                                  drm_device
 672                                                                  *dev)
 673 {
 674         struct radeon_device *rdev = dev->dev_private;
 675         struct radeon_mode_info *mode_info = &rdev->mode_info;
 676         struct atom_context *ctx = mode_info->atom_context;
 677         int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
 678         uint16_t size, data_offset;
 679         uint8_t frev, crev;
 680         uint16_t device_support;
 681         uint8_t dac;
 682         union atom_supported_devices *supported_devices;
 683         int i, j, max_device;
 684         struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE];
 685
 686         if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
 687                 return false;
 688
 689         supported_devices =
 690             (union atom_supported_devices *)(ctx->bios + data_offset);
 691
 692         device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
 693
 694         if (frev > 1)
 695                 max_device = ATOM_MAX_SUPPORTED_DEVICE;
 696         else
 697                 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
 698
 699         for (i = 0; i < max_device; i++) {
 700                 ATOM_CONNECTOR_INFO_I2C ci =
 701                     supported_devices->info.asConnInfo[i];
 702
 703                 bios_connectors[i].valid = false;
 704
 705                 if (!(device_support & (1 << i))) {
 706                         continue;
 707                 }
 708
 709                 if (i == ATOM_DEVICE_CV_INDEX) {
 710                         DRM_DEBUG("Skipping Component Video\n");
 711                         continue;
 712                 }
 713
 714                 bios_connectors[i].connector_type =
 715                     supported_devices_connector_convert[ci.sucConnectorInfo.
 716                                                         sbfAccess.
 717                                                         bfConnectorType];
 718
 719                 if (bios_connectors[i].connector_type ==
 720                     DRM_MODE_CONNECTOR_Unknown)
 721                         continue;
 722
 723                 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
 724
 725                 bios_connectors[i].line_mux =
 726                         ci.sucI2cId.ucAccess;
 727
 728                 /* give tv unique connector ids */
 729                 if (i == ATOM_DEVICE_TV1_INDEX) {
 730                         bios_connectors[i].ddc_bus.valid = false;
 731                         bios_connectors[i].line_mux = 50;
 732                 } else if (i == ATOM_DEVICE_TV2_INDEX) {
 733                         bios_connectors[i].ddc_bus.valid = false;
 734                         bios_connectors[i].line_mux = 51;
 735                 } else if (i == ATOM_DEVICE_CV_INDEX) {
 736                         bios_connectors[i].ddc_bus.valid = false;
 737                         bios_connectors[i].line_mux = 52;
 738                 } else
 739                         bios_connectors[i].ddc_bus =
 740                             radeon_lookup_i2c_gpio(rdev,
 741                                                    bios_connectors[i].line_mux);
 742
 743                 if ((crev > 1) && (frev > 1)) {
 744                         u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
 745                         switch (isb) {
 746                         case 0x4:
 747                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
 748                                 break;
 749                         case 0xa:
 750                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
 751                                 break;
 752                         default:
 753                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
 754                                 break;
 755                         }
 756                 } else {
 757                         if (i == ATOM_DEVICE_DFP1_INDEX)
 758                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
 759                         else if (i == ATOM_DEVICE_DFP2_INDEX)
 760                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
 761                         else
 762                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
 763                 }
 764
 765                 /* Always set the connector type to VGA for CRT1/CRT2. if they are
 766                  * shared with a DVI port, we'll pick up the DVI connector when we
 767                  * merge the outputs.  Some bioses incorrectly list VGA ports as DVI.
 768                  */
 769                 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
 770                         bios_connectors[i].connector_type =
 771                             DRM_MODE_CONNECTOR_VGA;
 772
 773                 if (!radeon_atom_apply_quirks
 774                     (dev, (1 << i), &bios_connectors[i].connector_type,
 775                      &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
 776                      &bios_connectors[i].hpd))
 777                         continue;
 778
 779                 bios_connectors[i].valid = true;
 780                 bios_connectors[i].devices = (1 << i);
 781
 782                 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
 783                         radeon_add_atom_encoder(dev,
 784                                                 radeon_get_encoder_id(dev,
 785                                                                       (1 << i),
 786                                                                       dac),
 787                                                 (1 << i));
 788                 else
 789                         radeon_add_legacy_encoder(dev,
 790                                                   radeon_get_encoder_id(dev,
 791                                                                         (1 << i),
 792                                                                         dac),
 793                                                   (1 << i));
 794         }
 795
 796         /* combine shared connectors */
 797         for (i = 0; i < max_device; i++) {
 798                 if (bios_connectors[i].valid) {
 799                         for (j = 0; j < max_device; j++) {
 800                                 if (bios_connectors[j].valid && (i != j)) {
 801                                         if (bios_connectors[i].line_mux ==
 802                                             bios_connectors[j].line_mux) {
 803                                                 /* make sure not to combine LVDS */
 804                                                 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 805                                                         bios_connectors[i].line_mux = 53;
 806                                                         bios_connectors[i].ddc_bus.valid = false;
 807                                                         continue;
 808                                                 }
 809                                                 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 810                                                         bios_connectors[j].line_mux = 53;
 811                                                         bios_connectors[j].ddc_bus.valid = false;
 812                                                         continue;
 813                                                 }
 814                                                 /* combine analog and digital for DVI-I */
 815                                                 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
 816                                                      (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
 817                                                     ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
 818                                                      (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
 819                                                         bios_connectors[i].devices |=
 820                                                                 bios_connectors[j].devices;
 821                                                         bios_connectors[i].connector_type =
 822                                                                 DRM_MODE_CONNECTOR_DVII;
 823                                                         if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
 824                                                                 bios_connectors[i].hpd =
 825                                                                         bios_connectors[j].hpd;
 826                                                         bios_connectors[j].valid = false;
 827                                                 }
 828                                         }
 829                                 }
 830                         }
 831                 }
 832         }
 833
 834         /* add the connectors */
 835         for (i = 0; i < max_device; i++) {
 836                 if (bios_connectors[i].valid) {
 837                         uint16_t connector_object_id =
 838                                 atombios_get_connector_object_id(dev,
 839                                                       bios_connectors[i].connector_type,
 840                                                       bios_connectors[i].devices);
 841                         radeon_add_atom_connector(dev,
 842                                                   bios_connectors[i].line_mux,
 843                                                   bios_connectors[i].devices,
 844                                                   bios_connectors[i].
 845                                                   connector_type,
 846                                                   &bios_connectors[i].ddc_bus,
 847                                                   false, 0,
 848                                                   connector_object_id,
 849                                                   &bios_connectors[i].hpd);
 850                 }
 851         }
 852
 853         radeon_link_encoder_connector(dev);
 854
 855         return true;
 856 }
 857
 858 union firmware_info {
 859         ATOM_FIRMWARE_INFO info;
 860         ATOM_FIRMWARE_INFO_V1_2 info_12;
 861         ATOM_FIRMWARE_INFO_V1_3 info_13;
 862         ATOM_FIRMWARE_INFO_V1_4 info_14;
 863         ATOM_FIRMWARE_INFO_V2_1 info_21;
 864 };
 865
 866 bool radeon_atom_get_clock_info(struct drm_device *dev)
 867 {
 868         struct radeon_device *rdev = dev->dev_private;
 869         struct radeon_mode_info *mode_info = &rdev->mode_info;
 870         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
 871         union firmware_info *firmware_info;
 872         uint8_t frev, crev;
 873         struct radeon_pll *p1pll = &rdev->clock.p1pll;
 874         struct radeon_pll *p2pll = &rdev->clock.p2pll;
 875         struct radeon_pll *dcpll = &rdev->clock.dcpll;
 876         struct radeon_pll *spll = &rdev->clock.spll;
 877         struct radeon_pll *mpll = &rdev->clock.mpll;
 878         uint16_t data_offset;
 879
 880         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
 881                                    &frev, &crev, &data_offset)) {
 882                 firmware_info =
 883                         (union firmware_info *)(mode_info->atom_context->bios +
 884                                                 data_offset);
 885                 /* pixel clocks */
 886                 p1pll->reference_freq =
 887                     le16_to_cpu(firmware_info->info.usReferenceClock);
 888                 p1pll->reference_div = 0;
 889
 890                 if (crev < 2)
 891                         p1pll->pll_out_min =
 892                                 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
 893                 else
 894                         p1pll->pll_out_min =
 895                                 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
 896                 p1pll->pll_out_max =
 897                     le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
 898
 899                 if (crev >= 4) {
 900                         p1pll->lcd_pll_out_min =
 901                                 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
 902                         if (p1pll->lcd_pll_out_min == 0)
 903                                 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
 904                         p1pll->lcd_pll_out_max =
 905                                 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
 906                         if (p1pll->lcd_pll_out_max == 0)
 907                                 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
 908                 } else {
 909                         p1pll->lcd_pll_out_min = p1pll->pll_out_min;
 910                         p1pll->lcd_pll_out_max = p1pll->pll_out_max;
 911                 }
 912
 913                 if (p1pll->pll_out_min == 0) {
 914                         if (ASIC_IS_AVIVO(rdev))
 915                                 p1pll->pll_out_min = 64800;
 916                         else
 917                                 p1pll->pll_out_min = 20000;
 918                 } else if (p1pll->pll_out_min > 64800) {
 919                         /* Limiting the pll output range is a good thing generally as
 920                          * it limits the number of possible pll combinations for a given
 921                          * frequency presumably to the ones that work best on each card.
 922                          * However, certain duallink DVI monitors seem to like
 923                          * pll combinations that would be limited by this at least on
 924                          * pre-DCE 3.0 r6xx hardware.  This might need to be adjusted per
 925                          * family.
 926                          */
 927                         if (!radeon_new_pll)
 928                                 p1pll->pll_out_min = 64800;
 929                 }
 930
 931                 p1pll->pll_in_min =
 932                     le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
 933                 p1pll->pll_in_max =
 934                     le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
 935
 936                 *p2pll = *p1pll;
 937
 938                 /* system clock */
 939                 spll->reference_freq =
 940                     le16_to_cpu(firmware_info->info.usReferenceClock);
 941                 spll->reference_div = 0;
 942
 943                 spll->pll_out_min =
 944                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
 945                 spll->pll_out_max =
 946                     le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
 947
 948                 /* ??? */
 949                 if (spll->pll_out_min == 0) {
 950                         if (ASIC_IS_AVIVO(rdev))
 951                                 spll->pll_out_min = 64800;
 952                         else
 953                                 spll->pll_out_min = 20000;
 954                 }
 955
 956                 spll->pll_in_min =
 957                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
 958                 spll->pll_in_max =
 959                     le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
 960
 961                 /* memory clock */
 962                 mpll->reference_freq =
 963                     le16_to_cpu(firmware_info->info.usReferenceClock);
 964                 mpll->reference_div = 0;
 965
 966                 mpll->pll_out_min =
 967                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
 968                 mpll->pll_out_max =
 969                     le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
 970
 971                 /* ??? */
 972                 if (mpll->pll_out_min == 0) {
 973                         if (ASIC_IS_AVIVO(rdev))
 974                                 mpll->pll_out_min = 64800;
 975                         else
 976                                 mpll->pll_out_min = 20000;
 977                 }
 978
 979                 mpll->pll_in_min =
 980                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
 981                 mpll->pll_in_max =
 982                     le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
 983
 984                 rdev->clock.default_sclk =
 985                     le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
 986                 rdev->clock.default_mclk =
 987                     le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
 988
 989                 if (ASIC_IS_DCE4(rdev)) {
 990                         rdev->clock.default_dispclk =
 991                                 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
 992                         if (rdev->clock.default_dispclk == 0)
 993                                 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
 994                         rdev->clock.dp_extclk =
 995                                 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
 996                 }
 997                 *dcpll = *p1pll;
 998
 999                 return true;
1000         }
1001
1002         return false;
1003 }
1004
1005 union igp_info {
1006         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1007         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1008 };
1009
1010 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1011 {
1012         struct radeon_mode_info *mode_info = &rdev->mode_info;
1013         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1014         union igp_info *igp_info;
1015         u8 frev, crev;
1016         u16 data_offset;
1017
1018         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1019                                    &frev, &crev, &data_offset)) {
1020                 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1021                                       data_offset);
1022                 switch (crev) {
1023                 case 1:
1024                         if (igp_info->info.ucMemoryType & 0xf0)
1025                                 return true;
1026                         break;
1027                 case 2:
1028                         if (igp_info->info_2.ucMemoryType & 0x0f)
1029                                 return true;
1030                         break;
1031                 default:
1032                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1033                         break;
1034                 }
1035         }
1036         return false;
1037 }
1038
1039 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1040                                    struct radeon_encoder_int_tmds *tmds)
1041 {
1042         struct drm_device *dev = encoder->base.dev;
1043         struct radeon_device *rdev = dev->dev_private;
1044         struct radeon_mode_info *mode_info = &rdev->mode_info;
1045         int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1046         uint16_t data_offset;
1047         struct _ATOM_TMDS_INFO *tmds_info;
1048         uint8_t frev, crev;
1049         uint16_t maxfreq;
1050         int i;
1051
1052         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1053                                    &frev, &crev, &data_offset)) {
1054                 tmds_info =
1055                         (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1056                                                    data_offset);
1057
1058                 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1059                 for (i = 0; i < 4; i++) {
1060                         tmds->tmds_pll[i].freq =
1061                             le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1062                         tmds->tmds_pll[i].value =
1063                             tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1064                         tmds->tmds_pll[i].value |=
1065                             (tmds_info->asMiscInfo[i].
1066                              ucPLL_VCO_Gain & 0x3f) << 6;
1067                         tmds->tmds_pll[i].value |=
1068                             (tmds_info->asMiscInfo[i].
1069                              ucPLL_DutyCycle & 0xf) << 12;
1070                         tmds->tmds_pll[i].value |=
1071                             (tmds_info->asMiscInfo[i].
1072                              ucPLL_VoltageSwing & 0xf) << 16;
1073
1074                         DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
1075                                   tmds->tmds_pll[i].freq,
1076                                   tmds->tmds_pll[i].value);
1077
1078                         if (maxfreq == tmds->tmds_pll[i].freq) {
1079                                 tmds->tmds_pll[i].freq = 0xffffffff;
1080                                 break;
1081                         }
1082                 }
1083                 return true;
1084         }
1085         return false;
1086 }
1087
1088 static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct
1089                                                           radeon_encoder
1090                                                           *encoder,
1091                                                           int id)
1092 {
1093         struct drm_device *dev = encoder->base.dev;
1094         struct radeon_device *rdev = dev->dev_private;
1095         struct radeon_mode_info *mode_info = &rdev->mode_info;
1096         int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1097         uint16_t data_offset;
1098         struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1099         uint8_t frev, crev;
1100         struct radeon_atom_ss *ss = NULL;
1101         int i;
1102
1103         if (id > ATOM_MAX_SS_ENTRY)
1104                 return NULL;
1105
1106         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1107                                    &frev, &crev, &data_offset)) {
1108                 ss_info =
1109                         (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1110
1111                 ss =
1112                     kzalloc(sizeof(struct radeon_atom_ss), GFP_KERNEL);
1113
1114                 if (!ss)
1115                         return NULL;
1116
1117                 for (i = 0; i < ATOM_MAX_SS_ENTRY; i++) {
1118                         if (ss_info->asSS_Info[i].ucSS_Id == id) {
1119                                 ss->percentage =
1120                                         le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1121                                 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1122                                 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1123                                 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1124                                 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1125                                 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1126                                 break;
1127                         }
1128                 }
1129         }
1130         return ss;
1131 }
1132
1133 union lvds_info {
1134         struct _ATOM_LVDS_INFO info;
1135         struct _ATOM_LVDS_INFO_V12 info_12;
1136 };
1137
1138 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1139                                                               radeon_encoder
1140                                                               *encoder)
1141 {
1142         struct drm_device *dev = encoder->base.dev;
1143         struct radeon_device *rdev = dev->dev_private;
1144         struct radeon_mode_info *mode_info = &rdev->mode_info;
1145         int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1146         uint16_t data_offset, misc;
1147         union lvds_info *lvds_info;
1148         uint8_t frev, crev;
1149         struct radeon_encoder_atom_dig *lvds = NULL;
1150
1151         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1152                                    &frev, &crev, &data_offset)) {
1153                 lvds_info =
1154                         (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1155                 lvds =
1156                     kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1157
1158                 if (!lvds)
1159                         return NULL;
1160
1161                 lvds->native_mode.clock =
1162                     le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1163                 lvds->native_mode.hdisplay =
1164                     le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1165                 lvds->native_mode.vdisplay =
1166                     le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1167                 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1168                         le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1169                 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1170                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1171                 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1172                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1173                 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1174                         le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1175                 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1176                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1177                 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1178                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1179                 lvds->panel_pwr_delay =
1180                     le16_to_cpu(lvds_info->info.usOffDelayInMs);
1181                 lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
1182
1183                 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1184                 if (misc & ATOM_VSYNC_POLARITY)
1185                         lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1186                 if (misc & ATOM_HSYNC_POLARITY)
1187                         lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1188                 if (misc & ATOM_COMPOSITESYNC)
1189                         lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1190                 if (misc & ATOM_INTERLACE)
1191                         lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1192                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1193                         lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1194
1195                 /* set crtc values */
1196                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1197
1198                 lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id);
1199
1200                 if (ASIC_IS_AVIVO(rdev)) {
1201                         if (radeon_new_pll == 0)
1202                                 lvds->pll_algo = PLL_ALGO_LEGACY;
1203                         else
1204                                 lvds->pll_algo = PLL_ALGO_NEW;
1205                 } else {
1206                         if (radeon_new_pll == 1)
1207                                 lvds->pll_algo = PLL_ALGO_NEW;
1208                         else
1209                                 lvds->pll_algo = PLL_ALGO_LEGACY;
1210                 }
1211
1212                 encoder->native_mode = lvds->native_mode;
1213         }
1214         return lvds;
1215 }
1216
1217 struct radeon_encoder_primary_dac *
1218 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1219 {
1220         struct drm_device *dev = encoder->base.dev;
1221         struct radeon_device *rdev = dev->dev_private;
1222         struct radeon_mode_info *mode_info = &rdev->mode_info;
1223         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1224         uint16_t data_offset;
1225         struct _COMPASSIONATE_DATA *dac_info;
1226         uint8_t frev, crev;
1227         uint8_t bg, dac;
1228         struct radeon_encoder_primary_dac *p_dac = NULL;
1229
1230         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1231                                    &frev, &crev, &data_offset)) {
1232                 dac_info = (struct _COMPASSIONATE_DATA *)
1233                         (mode_info->atom_context->bios + data_offset);
1234
1235                 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1236
1237                 if (!p_dac)
1238                         return NULL;
1239
1240                 bg = dac_info->ucDAC1_BG_Adjustment;
1241                 dac = dac_info->ucDAC1_DAC_Adjustment;
1242                 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1243
1244         }
1245         return p_dac;
1246 }
1247
1248 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1249                                 struct drm_display_mode *mode)
1250 {
1251         struct radeon_mode_info *mode_info = &rdev->mode_info;
1252         ATOM_ANALOG_TV_INFO *tv_info;
1253         ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1254         ATOM_DTD_FORMAT *dtd_timings;
1255         int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1256         u8 frev, crev;
1257         u16 data_offset, misc;
1258
1259         if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1260                                     &frev, &crev, &data_offset))
1261                 return false;
1262
1263         switch (crev) {
1264         case 1:
1265                 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1266                 if (index >= MAX_SUPPORTED_TV_TIMING)
1267                         return false;
1268
1269                 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1270                 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1271                 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1272                 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1273                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1274
1275                 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1276                 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1277                 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1278                 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1279                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1280
1281                 mode->flags = 0;
1282                 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1283                 if (misc & ATOM_VSYNC_POLARITY)
1284                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1285                 if (misc & ATOM_HSYNC_POLARITY)
1286                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1287                 if (misc & ATOM_COMPOSITESYNC)
1288                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1289                 if (misc & ATOM_INTERLACE)
1290                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1291                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1292                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1293
1294                 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1295
1296                 if (index == 1) {
1297                         /* PAL timings appear to have wrong values for totals */
1298                         mode->crtc_htotal -= 1;
1299                         mode->crtc_vtotal -= 1;
1300                 }
1301                 break;
1302         case 2:
1303                 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1304                 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1305                         return false;
1306
1307                 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1308                 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1309                         le16_to_cpu(dtd_timings->usHBlanking_Time);
1310                 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1311                 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1312                         le16_to_cpu(dtd_timings->usHSyncOffset);
1313                 mode->crtc_hsync_end = mode->crtc_hsync_start +
1314                         le16_to_cpu(dtd_timings->usHSyncWidth);
1315
1316                 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1317                         le16_to_cpu(dtd_timings->usVBlanking_Time);
1318                 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1319                 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1320                         le16_to_cpu(dtd_timings->usVSyncOffset);
1321                 mode->crtc_vsync_end = mode->crtc_vsync_start +
1322                         le16_to_cpu(dtd_timings->usVSyncWidth);
1323
1324                 mode->flags = 0;
1325                 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1326                 if (misc & ATOM_VSYNC_POLARITY)
1327                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1328                 if (misc & ATOM_HSYNC_POLARITY)
1329                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1330                 if (misc & ATOM_COMPOSITESYNC)
1331                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1332                 if (misc & ATOM_INTERLACE)
1333                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1334                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1335                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1336
1337                 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1338                 break;
1339         }
1340         return true;
1341 }
1342
1343 enum radeon_tv_std
1344 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1345 {
1346         struct radeon_mode_info *mode_info = &rdev->mode_info;
1347         int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1348         uint16_t data_offset;
1349         uint8_t frev, crev;
1350         struct _ATOM_ANALOG_TV_INFO *tv_info;
1351         enum radeon_tv_std tv_std = TV_STD_NTSC;
1352
1353         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1354                                    &frev, &crev, &data_offset)) {
1355
1356                 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1357                         (mode_info->atom_context->bios + data_offset);
1358
1359                 switch (tv_info->ucTV_BootUpDefaultStandard) {
1360                 case ATOM_TV_NTSC:
1361                         tv_std = TV_STD_NTSC;
1362                         DRM_INFO("Default TV standard: NTSC\n");
1363                         break;
1364                 case ATOM_TV_NTSCJ:
1365                         tv_std = TV_STD_NTSC_J;
1366                         DRM_INFO("Default TV standard: NTSC-J\n");
1367                         break;
1368                 case ATOM_TV_PAL:
1369                         tv_std = TV_STD_PAL;
1370                         DRM_INFO("Default TV standard: PAL\n");
1371                         break;
1372                 case ATOM_TV_PALM:
1373                         tv_std = TV_STD_PAL_M;
1374                         DRM_INFO("Default TV standard: PAL-M\n");
1375                         break;
1376                 case ATOM_TV_PALN:
1377                         tv_std = TV_STD_PAL_N;
1378                         DRM_INFO("Default TV standard: PAL-N\n");
1379                         break;
1380                 case ATOM_TV_PALCN:
1381                         tv_std = TV_STD_PAL_CN;
1382                         DRM_INFO("Default TV standard: PAL-CN\n");
1383                         break;
1384                 case ATOM_TV_PAL60:
1385                         tv_std = TV_STD_PAL_60;
1386                         DRM_INFO("Default TV standard: PAL-60\n");
1387                         break;
1388                 case ATOM_TV_SECAM:
1389                         tv_std = TV_STD_SECAM;
1390                         DRM_INFO("Default TV standard: SECAM\n");
1391                         break;
1392                 default:
1393                         tv_std = TV_STD_NTSC;
1394                         DRM_INFO("Unknown TV standard; defaulting to NTSC\n");
1395                         break;
1396                 }
1397         }
1398         return tv_std;
1399 }
1400
1401 struct radeon_encoder_tv_dac *
1402 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1403 {
1404         struct drm_device *dev = encoder->base.dev;
1405         struct radeon_device *rdev = dev->dev_private;
1406         struct radeon_mode_info *mode_info = &rdev->mode_info;
1407         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1408         uint16_t data_offset;
1409         struct _COMPASSIONATE_DATA *dac_info;
1410         uint8_t frev, crev;
1411         uint8_t bg, dac;
1412         struct radeon_encoder_tv_dac *tv_dac = NULL;
1413
1414         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1415                                    &frev, &crev, &data_offset)) {
1416
1417                 dac_info = (struct _COMPASSIONATE_DATA *)
1418                         (mode_info->atom_context->bios + data_offset);
1419
1420                 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1421
1422                 if (!tv_dac)
1423                         return NULL;
1424
1425                 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1426                 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1427                 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1428
1429                 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1430                 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1431                 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1432
1433                 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1434                 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1435                 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1436
1437                 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1438         }
1439         return tv_dac;
1440 }
1441
1442 static const char *thermal_controller_names[] = {
1443         "NONE",
1444         "lm63",
1445         "adm1032",
1446         "adm1030",
1447         "max6649",
1448         "lm64",
1449         "f75375",
1450         "asc7xxx",
1451 };
1452
1453 static const char *pp_lib_thermal_controller_names[] = {
1454         "NONE",
1455         "lm63",
1456         "adm1032",
1457         "adm1030",
1458         "max6649",
1459         "lm64",
1460         "f75375",
1461         "RV6xx",
1462         "RV770",
1463         "adt7473",
1464         "External GPIO",
1465         "Evergreen",
1466         "adt7473 with internal",
1467
1468 };
1469
1470 union power_info {
1471         struct _ATOM_POWERPLAY_INFO info;
1472         struct _ATOM_POWERPLAY_INFO_V2 info_2;
1473         struct _ATOM_POWERPLAY_INFO_V3 info_3;
1474         struct _ATOM_PPLIB_POWERPLAYTABLE info_4;
1475 };
1476
1477 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1478 {
1479         struct radeon_mode_info *mode_info = &rdev->mode_info;
1480         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1481         u16 data_offset;
1482         u8 frev, crev;
1483         u32 misc, misc2 = 0, sclk, mclk;
1484         union power_info *power_info;
1485         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
1486         struct _ATOM_PPLIB_STATE *power_state;
1487         int num_modes = 0, i, j;
1488         int state_index = 0, mode_index = 0;
1489         struct radeon_i2c_bus_rec i2c_bus;
1490
1491         rdev->pm.default_power_state_index = -1;
1492
1493         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1494                                    &frev, &crev, &data_offset)) {
1495                 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1496                 if (frev < 4) {
1497                         /* add the i2c bus for thermal/fan chip */
1498                         if (power_info->info.ucOverdriveThermalController > 0) {
1499                                 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1500                                          thermal_controller_names[power_info->info.ucOverdriveThermalController],
1501                                          power_info->info.ucOverdriveControllerAddress >> 1);
1502                                 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
1503                                 rdev->pm.i2c_bus = radeon_i2c_create(rdev->ddev, &i2c_bus, "Thermal");
1504                                 if (rdev->pm.i2c_bus) {
1505                                         struct i2c_board_info info = { };
1506                                         const char *name = thermal_controller_names[power_info->info.
1507                                                                                     ucOverdriveThermalController];
1508                                         info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
1509                                         strlcpy(info.type, name, sizeof(info.type));
1510                                         i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1511                                 }
1512                         }
1513                         num_modes = power_info->info.ucNumOfPowerModeEntries;
1514                         if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
1515                                 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
1516                         /* last mode is usually default, array is low to high */
1517                         for (i = 0; i < num_modes; i++) {
1518                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1519                                 switch (frev) {
1520                                 case 1:
1521                                         rdev->pm.power_state[state_index].num_clock_modes = 1;
1522                                         rdev->pm.power_state[state_index].clock_info[0].mclk =
1523                                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
1524                                         rdev->pm.power_state[state_index].clock_info[0].sclk =
1525                                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
1526                                         /* skip invalid modes */
1527                                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1528                                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1529                                                 continue;
1530                                         rdev->pm.power_state[state_index].pcie_lanes =
1531                                                 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
1532                                         misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
1533                                         if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
1534                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1535                                                         VOLTAGE_GPIO;
1536                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1537                                                         radeon_lookup_gpio(rdev,
1538                                                         power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
1539                                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1540                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1541                                                                 true;
1542                                                 else
1543                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1544                                                                 false;
1545                                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1546                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1547                                                         VOLTAGE_VDDC;
1548                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1549                                                         power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
1550                                         }
1551                                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1552                                         rdev->pm.power_state[state_index].misc = misc;
1553                                         /* order matters! */
1554                                         if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1555                                                 rdev->pm.power_state[state_index].type =
1556                                                         POWER_STATE_TYPE_POWERSAVE;
1557                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1558                                                 rdev->pm.power_state[state_index].type =
1559                                                         POWER_STATE_TYPE_BATTERY;
1560                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1561                                                 rdev->pm.power_state[state_index].type =
1562                                                         POWER_STATE_TYPE_BATTERY;
1563                                         if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1564                                                 rdev->pm.power_state[state_index].type =
1565                                                         POWER_STATE_TYPE_BALANCED;
1566                                         if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1567                                                 rdev->pm.power_state[state_index].type =
1568                                                         POWER_STATE_TYPE_PERFORMANCE;
1569                                                 rdev->pm.power_state[state_index].flags &=
1570                                                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1571                                         }
1572                                         if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1573                                                 rdev->pm.power_state[state_index].type =
1574                                                         POWER_STATE_TYPE_DEFAULT;
1575                                                 rdev->pm.default_power_state_index = state_index;
1576                                                 rdev->pm.power_state[state_index].default_clock_mode =
1577                                                         &rdev->pm.power_state[state_index].clock_info[0];
1578                                                 rdev->pm.power_state[state_index].flags &=
1579                                                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1580                                         } else if (state_index == 0) {
1581                                                 rdev->pm.power_state[state_index].clock_info[0].flags |=
1582                                                         RADEON_PM_MODE_NO_DISPLAY;
1583                                         }
1584                                         state_index++;
1585                                         break;
1586                                 case 2:
1587                                         rdev->pm.power_state[state_index].num_clock_modes = 1;
1588                                         rdev->pm.power_state[state_index].clock_info[0].mclk =
1589                                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
1590                                         rdev->pm.power_state[state_index].clock_info[0].sclk =
1591                                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
1592                                         /* skip invalid modes */
1593                                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1594                                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1595                                                 continue;
1596                                         rdev->pm.power_state[state_index].pcie_lanes =
1597                                                 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
1598                                         misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
1599                                         misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
1600                                         if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
1601                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1602                                                         VOLTAGE_GPIO;
1603                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1604                                                         radeon_lookup_gpio(rdev,
1605                                                         power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
1606                                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1607                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1608                                                                 true;
1609                                                 else
1610                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1611                                                                 false;
1612                                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1613                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1614                                                         VOLTAGE_VDDC;
1615                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1616                                                         power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
1617                                         }
1618                                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1619                                         rdev->pm.power_state[state_index].misc = misc;
1620                                         rdev->pm.power_state[state_index].misc2 = misc2;
1621                                         /* order matters! */
1622                                         if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1623                                                 rdev->pm.power_state[state_index].type =
1624                                                         POWER_STATE_TYPE_POWERSAVE;
1625                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1626                                                 rdev->pm.power_state[state_index].type =
1627                                                         POWER_STATE_TYPE_BATTERY;
1628                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1629                                                 rdev->pm.power_state[state_index].type =
1630                                                         POWER_STATE_TYPE_BATTERY;
1631                                         if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1632                                                 rdev->pm.power_state[state_index].type =
1633                                                         POWER_STATE_TYPE_BALANCED;
1634                                         if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1635                                                 rdev->pm.power_state[state_index].type =
1636                                                         POWER_STATE_TYPE_PERFORMANCE;
1637                                                 rdev->pm.power_state[state_index].flags &=
1638                                                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1639                                         }
1640                                         if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1641                                                 rdev->pm.power_state[state_index].type =
1642                                                         POWER_STATE_TYPE_BALANCED;
1643                                         if (misc2 & ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT)
1644                                                 rdev->pm.power_state[state_index].flags &=
1645                                                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1646                                         if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1647                                                 rdev->pm.power_state[state_index].type =
1648                                                         POWER_STATE_TYPE_DEFAULT;
1649                                                 rdev->pm.default_power_state_index = state_index;
1650                                                 rdev->pm.power_state[state_index].default_clock_mode =
1651                                                         &rdev->pm.power_state[state_index].clock_info[0];
1652                                                 rdev->pm.power_state[state_index].flags &=
1653                                                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1654                                         } else if (state_index == 0) {
1655                                                 rdev->pm.power_state[state_index].clock_info[0].flags |=
1656                                                         RADEON_PM_MODE_NO_DISPLAY;
1657                                         }
1658                                         state_index++;
1659                                         break;
1660                                 case 3:
1661                                         rdev->pm.power_state[state_index].num_clock_modes = 1;
1662                                         rdev->pm.power_state[state_index].clock_info[0].mclk =
1663                                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
1664                                         rdev->pm.power_state[state_index].clock_info[0].sclk =
1665                                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
1666                                         /* skip invalid modes */
1667                                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1668                                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1669                                                 continue;
1670                                         rdev->pm.power_state[state_index].pcie_lanes =
1671                                                 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
1672                                         misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
1673                                         misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
1674                                         if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
1675                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1676                                                         VOLTAGE_GPIO;
1677                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1678                                                         radeon_lookup_gpio(rdev,
1679                                                         power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
1680                                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1681                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1682                                                                 true;
1683                                                 else
1684                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1685                                                                 false;
1686                                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1687                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1688                                                         VOLTAGE_VDDC;
1689                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1690                                                         power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
1691                                                 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
1692                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
1693                                                                 true;
1694                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
1695                                                         power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
1696                                                 }
1697                                         }
1698                                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1699                                         rdev->pm.power_state[state_index].misc = misc;
1700                                         rdev->pm.power_state[state_index].misc2 = misc2;
1701                                         /* order matters! */
1702                                         if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1703                                                 rdev->pm.power_state[state_index].type =
1704                                                         POWER_STATE_TYPE_POWERSAVE;
1705                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1706                                                 rdev->pm.power_state[state_index].type =
1707                                                         POWER_STATE_TYPE_BATTERY;
1708                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1709                                                 rdev->pm.power_state[state_index].type =
1710                                                         POWER_STATE_TYPE_BATTERY;
1711                                         if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1712                                                 rdev->pm.power_state[state_index].type =
1713                                                         POWER_STATE_TYPE_BALANCED;
1714                                         if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1715                                                 rdev->pm.power_state[state_index].type =
1716                                                         POWER_STATE_TYPE_PERFORMANCE;
1717                                                 rdev->pm.power_state[state_index].flags &=
1718                                                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1719                                         }
1720                                         if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1721                                                 rdev->pm.power_state[state_index].type =
1722                                                         POWER_STATE_TYPE_BALANCED;
1723                                         if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1724                                                 rdev->pm.power_state[state_index].type =
1725                                                         POWER_STATE_TYPE_DEFAULT;
1726                                                 rdev->pm.default_power_state_index = state_index;
1727                                                 rdev->pm.power_state[state_index].default_clock_mode =
1728                                                         &rdev->pm.power_state[state_index].clock_info[0];
1729                                         } else if (state_index == 0) {
1730                                                 rdev->pm.power_state[state_index].clock_info[0].flags |=
1731                                                         RADEON_PM_MODE_NO_DISPLAY;
1732                                         }
1733                                         state_index++;
1734                                         break;
1735                                 }
1736                         }
1737                         /* last mode is usually default */
1738                         if (rdev->pm.default_power_state_index == -1) {
1739                                 rdev->pm.power_state[state_index - 1].type =
1740                                         POWER_STATE_TYPE_DEFAULT;
1741                                 rdev->pm.default_power_state_index = state_index - 1;
1742                                 rdev->pm.power_state[state_index - 1].default_clock_mode =
1743                                         &rdev->pm.power_state[state_index - 1].clock_info[0];
1744                                 rdev->pm.power_state[state_index].flags &=
1745                                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1746                                 rdev->pm.power_state[state_index].misc = 0;
1747                                 rdev->pm.power_state[state_index].misc2 = 0;
1748                         }
1749                 } else {
1750                         /* add the i2c bus for thermal/fan chip */
1751                         /* no support for internal controller yet */
1752                         ATOM_PPLIB_THERMALCONTROLLER *controller = &power_info->info_4.sThermalController;
1753                         if (controller->ucType > 0) {
1754                                 if ((controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) ||
1755                                     (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) ||
1756                                     (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN)) {
1757                                         DRM_INFO("Internal thermal controller %s fan control\n",
1758                                                  (controller->ucFanParameters &
1759                                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1760                                 } else if ((controller->ucType ==
1761                                             ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
1762                                            (controller->ucType ==
1763                                             ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL)) {
1764                                         DRM_INFO("Special thermal controller config\n");
1765                                 } else {
1766                                         DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
1767                                                  pp_lib_thermal_controller_names[controller->ucType],
1768                                                  controller->ucI2cAddress >> 1,
1769                                                  (controller->ucFanParameters &
1770                                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1771                                         i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
1772                                         rdev->pm.i2c_bus = radeon_i2c_create(rdev->ddev, &i2c_bus, "Thermal");
1773                                         if (rdev->pm.i2c_bus) {
1774                                                 struct i2c_board_info info = { };
1775                                                 const char *name = pp_lib_thermal_controller_names[controller->ucType];
1776                                                 info.addr = controller->ucI2cAddress >> 1;
1777                                                 strlcpy(info.type, name, sizeof(info.type));
1778                                                 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1779                                         }
1780
1781                                 }
1782                         }
1783                         /* first mode is usually default, followed by low to high */
1784                         for (i = 0; i < power_info->info_4.ucNumStates; i++) {
1785                                 mode_index = 0;
1786                                 power_state = (struct _ATOM_PPLIB_STATE *)
1787                                         (mode_info->atom_context->bios +
1788                                          data_offset +
1789                                          le16_to_cpu(power_info->info_4.usStateArrayOffset) +
1790                                          i * power_info->info_4.ucStateEntrySize);
1791                                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
1792                                         (mode_info->atom_context->bios +
1793                                          data_offset +
1794                                          le16_to_cpu(power_info->info_4.usNonClockInfoArrayOffset) +
1795                                          (power_state->ucNonClockStateIndex *
1796                                           power_info->info_4.ucNonClockSize));
1797                                 for (j = 0; j < (power_info->info_4.ucStateEntrySize - 1); j++) {
1798                                         if (rdev->flags & RADEON_IS_IGP) {
1799                                                 struct _ATOM_PPLIB_RS780_CLOCK_INFO *clock_info =
1800                                                         (struct _ATOM_PPLIB_RS780_CLOCK_INFO *)
1801                                                         (mode_info->atom_context->bios +
1802                                                          data_offset +
1803                                                          le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1804                                                          (power_state->ucClockStateIndices[j] *
1805                                                           power_info->info_4.ucClockInfoSize));
1806                                                 sclk = le16_to_cpu(clock_info->usLowEngineClockLow);
1807                                                 sclk |= clock_info->ucLowEngineClockHigh << 16;
1808                                                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1809                                                 /* skip invalid modes */
1810                                                 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
1811                                                         continue;
1812                                                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
1813                                                         VOLTAGE_SW;
1814                                                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
1815                                                         clock_info->usVDDC;
1816                                                 mode_index++;
1817                                         } else if (ASIC_IS_DCE4(rdev)) {
1818                                                 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO *clock_info =
1819                                                         (struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO *)
1820                                                         (mode_info->atom_context->bios +
1821                                                          data_offset +
1822                                                          le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1823                                                          (power_state->ucClockStateIndices[j] *
1824                                                           power_info->info_4.ucClockInfoSize));
1825                                                 sclk = le16_to_cpu(clock_info->usEngineClockLow);
1826                                                 sclk |= clock_info->ucEngineClockHigh << 16;
1827                                                 mclk = le16_to_cpu(clock_info->usMemoryClockLow);
1828                                                 mclk |= clock_info->ucMemoryClockHigh << 16;
1829                                                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
1830                                                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1831                                                 /* skip invalid modes */
1832                                                 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
1833                                                     (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
1834                                                         continue;
1835                                                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
1836                                                         VOLTAGE_SW;
1837                                                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
1838                                                         clock_info->usVDDC;
1839                                                 /* XXX usVDDCI */
1840                                                 mode_index++;
1841                                         } else {
1842                                                 struct _ATOM_PPLIB_R600_CLOCK_INFO *clock_info =
1843                                                         (struct _ATOM_PPLIB_R600_CLOCK_INFO *)
1844                                                         (mode_info->atom_context->bios +
1845                                                          data_offset +
1846                                                          le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1847                                                          (power_state->ucClockStateIndices[j] *
1848                                                           power_info->info_4.ucClockInfoSize));
1849                                                 sclk = le16_to_cpu(clock_info->usEngineClockLow);
1850                                                 sclk |= clock_info->ucEngineClockHigh << 16;
1851                                                 mclk = le16_to_cpu(clock_info->usMemoryClockLow);
1852                                                 mclk |= clock_info->ucMemoryClockHigh << 16;
1853                                                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
1854                                                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1855                                                 /* skip invalid modes */
1856                                                 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
1857                                                     (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
1858                                                         continue;
1859                                                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
1860                                                         VOLTAGE_SW;
1861                                                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
1862                                                         clock_info->usVDDC;
1863                                                 mode_index++;
1864                                         }
1865                                 }
1866                                 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
1867                                 if (mode_index) {
1868                                         misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
1869                                         misc2 = le16_to_cpu(non_clock_info->usClassification);
1870                                         rdev->pm.power_state[state_index].misc = misc;
1871                                         rdev->pm.power_state[state_index].misc2 = misc2;
1872                                         rdev->pm.power_state[state_index].pcie_lanes =
1873                                                 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
1874                                                 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
1875                                         switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
1876                                         case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
1877                                                 rdev->pm.power_state[state_index].type =
1878                                                         POWER_STATE_TYPE_BATTERY;
1879                                                 break;
1880                                         case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
1881                                                 rdev->pm.power_state[state_index].type =
1882                                                         POWER_STATE_TYPE_BALANCED;
1883                                                 break;
1884                                         case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
1885                                                 rdev->pm.power_state[state_index].type =
1886                                                         POWER_STATE_TYPE_PERFORMANCE;
1887                                                 break;
1888                                         }
1889                                         rdev->pm.power_state[state_index].flags = 0;
1890                                         if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
1891                                                 rdev->pm.power_state[state_index].flags |=
1892                                                         RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1893                                         if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
1894                                                 rdev->pm.power_state[state_index].type =
1895                                                         POWER_STATE_TYPE_DEFAULT;
1896                                                 rdev->pm.default_power_state_index = state_index;
1897                                                 rdev->pm.power_state[state_index].default_clock_mode =
1898                                                         &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
1899                                         }
1900                                         state_index++;
1901                                 }
1902                         }
1903                         /* if multiple clock modes, mark the lowest as no display */
1904                         for (i = 0; i < state_index; i++) {
1905                                 if (rdev->pm.power_state[i].num_clock_modes > 1)
1906                                         rdev->pm.power_state[i].clock_info[0].flags |=
1907                                                 RADEON_PM_MODE_NO_DISPLAY;
1908                         }
1909                         /* first mode is usually default */
1910                         if (rdev->pm.default_power_state_index == -1) {
1911                                 rdev->pm.power_state[0].type =
1912                                         POWER_STATE_TYPE_DEFAULT;
1913                                 rdev->pm.default_power_state_index = 0;
1914                                 rdev->pm.power_state[0].default_clock_mode =
1915                                         &rdev->pm.power_state[0].clock_info[0];
1916                         }
1917                 }
1918         } else {
1919                 /* add the default mode */
1920                 rdev->pm.power_state[state_index].type =
1921                         POWER_STATE_TYPE_DEFAULT;
1922                 rdev->pm.power_state[state_index].num_clock_modes = 1;
1923                 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
1924                 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
1925                 rdev->pm.power_state[state_index].default_clock_mode =
1926                         &rdev->pm.power_state[state_index].clock_info[0];
1927                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1928                 rdev->pm.power_state[state_index].pcie_lanes = 16;
1929                 rdev->pm.default_power_state_index = state_index;
1930                 rdev->pm.power_state[state_index].flags = 0;
1931                 state_index++;
1932         }
1933
1934         rdev->pm.num_power_states = state_index;
1935
1936         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
1937         rdev->pm.current_clock_mode_index = 0;
1938 }
1939
1940 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
1941 {
1942         DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
1943         int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
1944
1945         args.ucEnable = enable;
1946
1947         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1948 }
1949
1950 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
1951 {
1952         GET_ENGINE_CLOCK_PS_ALLOCATION args;
1953         int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
1954
1955         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1956         return args.ulReturnEngineClock;
1957 }
1958
1959 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
1960 {
1961         GET_MEMORY_CLOCK_PS_ALLOCATION args;
1962         int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
1963
1964         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1965         return args.ulReturnMemoryClock;
1966 }
1967
1968 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
1969                                   uint32_t eng_clock)
1970 {
1971         SET_ENGINE_CLOCK_PS_ALLOCATION args;
1972         int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
1973
1974         args.ulTargetEngineClock = eng_clock;   /* 10 khz */
1975
1976         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1977 }
1978
1979 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
1980                                   uint32_t mem_clock)
1981 {
1982         SET_MEMORY_CLOCK_PS_ALLOCATION args;
1983         int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
1984
1985         if (rdev->flags & RADEON_IS_IGP)
1986                 return;
1987
1988         args.ulTargetMemoryClock = mem_clock;   /* 10 khz */
1989
1990         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1991 }
1992
1993 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
1994 {
1995         struct radeon_device *rdev = dev->dev_private;
1996         uint32_t bios_2_scratch, bios_6_scratch;
1997
1998         if (rdev->family >= CHIP_R600) {
1999                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2000                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2001         } else {
2002                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2003                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2004         }
2005
2006         /* let the bios control the backlight */
2007         bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
2008
2009         /* tell the bios not to handle mode switching */
2010         bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
2011
2012         if (rdev->family >= CHIP_R600) {
2013                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2014                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2015         } else {
2016                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2017                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2018         }
2019
2020 }
2021
2022 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
2023 {
2024         uint32_t scratch_reg;
2025         int i;
2026
2027         if (rdev->family >= CHIP_R600)
2028                 scratch_reg = R600_BIOS_0_SCRATCH;
2029         else
2030                 scratch_reg = RADEON_BIOS_0_SCRATCH;
2031
2032         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2033                 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
2034 }
2035
2036 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
2037 {
2038         uint32_t scratch_reg;
2039         int i;
2040
2041         if (rdev->family >= CHIP_R600)
2042                 scratch_reg = R600_BIOS_0_SCRATCH;
2043         else
2044                 scratch_reg = RADEON_BIOS_0_SCRATCH;
2045
2046         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2047                 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
2048 }
2049
2050 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
2051 {
2052         struct drm_device *dev = encoder->dev;
2053         struct radeon_device *rdev = dev->dev_private;
2054         uint32_t bios_6_scratch;
2055
2056         if (rdev->family >= CHIP_R600)
2057                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2058         else
2059                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2060
2061         if (lock)
2062                 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
2063         else
2064                 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
2065
2066         if (rdev->family >= CHIP_R600)
2067                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2068         else
2069                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2070 }
2071
2072 /* at some point we may want to break this out into individual functions */
2073 void
2074 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2075                                        struct drm_encoder *encoder,
2076                                        bool connected)
2077 {
2078         struct drm_device *dev = connector->dev;
2079         struct radeon_device *rdev = dev->dev_private;
2080         struct radeon_connector *radeon_connector =
2081             to_radeon_connector(connector);
2082         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2083         uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2084
2085         if (rdev->family >= CHIP_R600) {
2086                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2087                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2088                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2089         } else {
2090                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2091                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2092                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2093         }
2094
2095         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2096             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2097                 if (connected) {
2098                         DRM_DEBUG("TV1 connected\n");
2099                         bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2100                         bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2101                 } else {
2102                         DRM_DEBUG("TV1 disconnected\n");
2103                         bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2104                         bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2105                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2106                 }
2107         }
2108         if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2109             (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2110                 if (connected) {
2111                         DRM_DEBUG("CV connected\n");
2112                         bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2113                         bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2114                 } else {
2115                         DRM_DEBUG("CV disconnected\n");
2116                         bios_0_scratch &= ~ATOM_S0_CV_MASK;
2117                         bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2118                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2119                 }
2120         }
2121         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2122             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2123                 if (connected) {
2124                         DRM_DEBUG("LCD1 connected\n");
2125                         bios_0_scratch |= ATOM_S0_LCD1;
2126                         bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2127                         bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2128                 } else {
2129                         DRM_DEBUG("LCD1 disconnected\n");
2130                         bios_0_scratch &= ~ATOM_S0_LCD1;
2131                         bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2132                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2133                 }
2134         }
2135         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2136             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2137                 if (connected) {
2138                         DRM_DEBUG("CRT1 connected\n");
2139                         bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2140                         bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2141                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2142                 } else {
2143                         DRM_DEBUG("CRT1 disconnected\n");
2144                         bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2145                         bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2146                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2147                 }
2148         }
2149         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2150             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2151                 if (connected) {
2152                         DRM_DEBUG("CRT2 connected\n");
2153                         bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2154                         bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2155                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2156                 } else {
2157                         DRM_DEBUG("CRT2 disconnected\n");
2158                         bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2159                         bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2160                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2161                 }
2162         }
2163         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2164             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2165                 if (connected) {
2166                         DRM_DEBUG("DFP1 connected\n");
2167                         bios_0_scratch |= ATOM_S0_DFP1;
2168                         bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2169                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2170                 } else {
2171                         DRM_DEBUG("DFP1 disconnected\n");
2172                         bios_0_scratch &= ~ATOM_S0_DFP1;
2173                         bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2174                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2175                 }
2176         }
2177         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2178             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2179                 if (connected) {
2180                         DRM_DEBUG("DFP2 connected\n");
2181                         bios_0_scratch |= ATOM_S0_DFP2;
2182                         bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2183                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2184                 } else {
2185                         DRM_DEBUG("DFP2 disconnected\n");
2186                         bios_0_scratch &= ~ATOM_S0_DFP2;
2187                         bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2188                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2189                 }
2190         }
2191         if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2192             (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2193                 if (connected) {
2194                         DRM_DEBUG("DFP3 connected\n");
2195                         bios_0_scratch |= ATOM_S0_DFP3;
2196                         bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2197                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2198                 } else {
2199                         DRM_DEBUG("DFP3 disconnected\n");
2200                         bios_0_scratch &= ~ATOM_S0_DFP3;
2201                         bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2202                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2203                 }
2204         }
2205         if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2206             (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2207                 if (connected) {
2208                         DRM_DEBUG("DFP4 connected\n");
2209                         bios_0_scratch |= ATOM_S0_DFP4;
2210                         bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2211                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2212                 } else {
2213                         DRM_DEBUG("DFP4 disconnected\n");
2214                         bios_0_scratch &= ~ATOM_S0_DFP4;
2215                         bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2216                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2217                 }
2218         }
2219         if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2220             (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2221                 if (connected) {
2222                         DRM_DEBUG("DFP5 connected\n");
2223                         bios_0_scratch |= ATOM_S0_DFP5;
2224                         bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2225                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2226                 } else {
2227                         DRM_DEBUG("DFP5 disconnected\n");
2228                         bios_0_scratch &= ~ATOM_S0_DFP5;
2229                         bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2230                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2231                 }
2232         }
2233
2234         if (rdev->family >= CHIP_R600) {
2235                 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2236                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2237                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2238         } else {
2239                 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2240                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2241                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2242         }
2243 }
2244
2245 void
2246 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2247 {
2248         struct drm_device *dev = encoder->dev;
2249         struct radeon_device *rdev = dev->dev_private;
2250         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2251         uint32_t bios_3_scratch;
2252
2253         if (rdev->family >= CHIP_R600)
2254                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2255         else
2256                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2257
2258         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2259                 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2260                 bios_3_scratch |= (crtc << 18);
2261         }
2262         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2263                 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2264                 bios_3_scratch |= (crtc << 24);
2265         }
2266         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2267                 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
2268                 bios_3_scratch |= (crtc << 16);
2269         }
2270         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2271                 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
2272                 bios_3_scratch |= (crtc << 20);
2273         }
2274         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2275                 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
2276                 bios_3_scratch |= (crtc << 17);
2277         }
2278         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2279                 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
2280                 bios_3_scratch |= (crtc << 19);
2281         }
2282         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2283                 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
2284                 bios_3_scratch |= (crtc << 23);
2285         }
2286         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2287                 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
2288                 bios_3_scratch |= (crtc << 25);
2289         }
2290
2291         if (rdev->family >= CHIP_R600)
2292                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2293         else
2294                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2295 }
2296
2297 void
2298 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2299 {
2300         struct drm_device *dev = encoder->dev;
2301         struct radeon_device *rdev = dev->dev_private;
2302         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2303         uint32_t bios_2_scratch;
2304
2305         if (rdev->family >= CHIP_R600)
2306                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2307         else
2308                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2309
2310         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2311                 if (on)
2312                         bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
2313                 else
2314                         bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
2315         }
2316         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2317                 if (on)
2318                         bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
2319                 else
2320                         bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
2321         }
2322         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2323                 if (on)
2324                         bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
2325                 else
2326                         bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
2327         }
2328         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2329                 if (on)
2330                         bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
2331                 else
2332                         bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
2333         }
2334         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2335                 if (on)
2336                         bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
2337                 else
2338                         bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
2339         }
2340         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2341                 if (on)
2342                         bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
2343                 else
2344                         bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
2345         }
2346         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2347                 if (on)
2348                         bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
2349                 else
2350                         bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
2351         }
2352         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2353                 if (on)
2354                         bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
2355                 else
2356                         bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
2357         }
2358         if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
2359                 if (on)
2360                         bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
2361                 else
2362                         bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
2363         }
2364         if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
2365                 if (on)
2366                         bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
2367                 else
2368                         bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
2369         }
2370
2371         if (rdev->family >= CHIP_R600)
2372                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2373         else
2374                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2375 }