2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #ifndef __RADEON_ASIC_H__
29 #define __RADEON_ASIC_H__
34 uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev);
35 void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
36 uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev);
37 void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
39 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev);
40 void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
41 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev);
42 void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
43 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
46 * r100,rv100,rs100,rv200,rs200
56 int r100_init(struct radeon_device *rdev);
57 void r100_fini(struct radeon_device *rdev);
58 int r100_suspend(struct radeon_device *rdev);
59 int r100_resume(struct radeon_device *rdev);
60 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
61 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
62 void r100_vga_set_state(struct radeon_device *rdev, bool state);
63 bool r100_gpu_is_lockup(struct radeon_device *rdev);
64 int r100_gpu_reset(struct radeon_device *rdev);
65 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
66 void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
67 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
68 void r100_cp_commit(struct radeon_device *rdev);
69 void r100_ring_start(struct radeon_device *rdev);
70 int r100_irq_set(struct radeon_device *rdev);
71 int r100_irq_process(struct radeon_device *rdev);
72 void r100_fence_ring_emit(struct radeon_device *rdev,
73 struct radeon_fence *fence);
74 int r100_cs_parse(struct radeon_cs_parser *p);
75 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
76 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
77 int r100_copy_blit(struct radeon_device *rdev,
81 struct radeon_fence *fence);
82 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
83 uint32_t tiling_flags, uint32_t pitch,
84 uint32_t offset, uint32_t obj_size);
85 void r100_clear_surface_reg(struct radeon_device *rdev, int reg);
86 void r100_bandwidth_update(struct radeon_device *rdev);
87 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
88 int r100_ring_test(struct radeon_device *rdev);
89 void r100_hpd_init(struct radeon_device *rdev);
90 void r100_hpd_fini(struct radeon_device *rdev);
91 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
92 void r100_hpd_set_polarity(struct radeon_device *rdev,
93 enum radeon_hpd_id hpd);
94 int r100_debugfs_rbbm_init(struct radeon_device *rdev);
95 int r100_debugfs_cp_init(struct radeon_device *rdev);
96 void r100_cp_disable(struct radeon_device *rdev);
97 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
98 void r100_cp_fini(struct radeon_device *rdev);
99 int r100_pci_gart_init(struct radeon_device *rdev);
100 void r100_pci_gart_fini(struct radeon_device *rdev);
101 int r100_pci_gart_enable(struct radeon_device *rdev);
102 void r100_pci_gart_disable(struct radeon_device *rdev);
103 int r100_debugfs_mc_info_init(struct radeon_device *rdev);
104 int r100_gui_wait_for_idle(struct radeon_device *rdev);
105 void r100_ib_fini(struct radeon_device *rdev);
106 int r100_ib_init(struct radeon_device *rdev);
107 void r100_irq_disable(struct radeon_device *rdev);
108 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
109 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
110 void r100_vram_init_sizes(struct radeon_device *rdev);
111 void r100_wb_disable(struct radeon_device *rdev);
112 void r100_wb_fini(struct radeon_device *rdev);
113 int r100_wb_init(struct radeon_device *rdev);
114 void r100_hdp_reset(struct radeon_device *rdev);
115 int r100_rb2d_reset(struct radeon_device *rdev);
116 int r100_cp_reset(struct radeon_device *rdev);
117 void r100_vga_render_disable(struct radeon_device *rdev);
118 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
119 struct radeon_cs_packet *pkt,
120 struct radeon_bo *robj);
121 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
122 struct radeon_cs_packet *pkt,
123 const unsigned *auth, unsigned n,
124 radeon_packet0_check_t check);
125 int r100_cs_packet_parse(struct radeon_cs_parser *p,
126 struct radeon_cs_packet *pkt,
128 void r100_enable_bm(struct radeon_device *rdev);
129 void r100_set_common_regs(struct radeon_device *rdev);
132 * r200,rv250,rs300,rv280
134 extern int r200_copy_dma(struct radeon_device *rdev,
138 struct radeon_fence *fence);
141 * r300,r350,rv350,rv380
143 extern int r300_init(struct radeon_device *rdev);
144 extern void r300_fini(struct radeon_device *rdev);
145 extern int r300_suspend(struct radeon_device *rdev);
146 extern int r300_resume(struct radeon_device *rdev);
147 extern bool r300_gpu_is_lockup(struct radeon_device *rdev);
148 extern int r300_gpu_reset(struct radeon_device *rdev);
149 extern void r300_ring_start(struct radeon_device *rdev);
150 extern void r300_fence_ring_emit(struct radeon_device *rdev,
151 struct radeon_fence *fence);
152 extern int r300_cs_parse(struct radeon_cs_parser *p);
153 extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
154 extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
155 extern uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
156 extern void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
157 extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
158 extern int rv370_get_pcie_lanes(struct radeon_device *rdev);
163 extern int r420_init(struct radeon_device *rdev);
164 extern void r420_fini(struct radeon_device *rdev);
165 extern int r420_suspend(struct radeon_device *rdev);
166 extern int r420_resume(struct radeon_device *rdev);
171 extern int rs400_init(struct radeon_device *rdev);
172 extern void rs400_fini(struct radeon_device *rdev);
173 extern int rs400_suspend(struct radeon_device *rdev);
174 extern int rs400_resume(struct radeon_device *rdev);
175 void rs400_gart_tlb_flush(struct radeon_device *rdev);
176 int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
177 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
178 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
183 extern int rs600_init(struct radeon_device *rdev);
184 extern void rs600_fini(struct radeon_device *rdev);
185 extern int rs600_suspend(struct radeon_device *rdev);
186 extern int rs600_resume(struct radeon_device *rdev);
187 int rs600_irq_set(struct radeon_device *rdev);
188 int rs600_irq_process(struct radeon_device *rdev);
189 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
190 void rs600_gart_tlb_flush(struct radeon_device *rdev);
191 int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
192 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
193 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
194 void rs600_bandwidth_update(struct radeon_device *rdev);
195 void rs600_hpd_init(struct radeon_device *rdev);
196 void rs600_hpd_fini(struct radeon_device *rdev);
197 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
198 void rs600_hpd_set_polarity(struct radeon_device *rdev,
199 enum radeon_hpd_id hpd);
204 int rs690_init(struct radeon_device *rdev);
205 void rs690_fini(struct radeon_device *rdev);
206 int rs690_resume(struct radeon_device *rdev);
207 int rs690_suspend(struct radeon_device *rdev);
208 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
209 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
210 void rs690_bandwidth_update(struct radeon_device *rdev);
215 int rv515_init(struct radeon_device *rdev);
216 void rv515_fini(struct radeon_device *rdev);
217 int rv515_gpu_reset(struct radeon_device *rdev);
218 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
219 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
220 void rv515_ring_start(struct radeon_device *rdev);
221 uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
222 void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
223 void rv515_bandwidth_update(struct radeon_device *rdev);
224 int rv515_resume(struct radeon_device *rdev);
225 int rv515_suspend(struct radeon_device *rdev);
228 * r520,rv530,rv560,rv570,r580
230 int r520_init(struct radeon_device *rdev);
231 int r520_resume(struct radeon_device *rdev);
234 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
236 int r600_init(struct radeon_device *rdev);
237 void r600_fini(struct radeon_device *rdev);
238 int r600_suspend(struct radeon_device *rdev);
239 int r600_resume(struct radeon_device *rdev);
240 void r600_vga_set_state(struct radeon_device *rdev, bool state);
241 int r600_wb_init(struct radeon_device *rdev);
242 void r600_wb_fini(struct radeon_device *rdev);
243 void r600_cp_commit(struct radeon_device *rdev);
244 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
245 uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
246 void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
247 int r600_cs_parse(struct radeon_cs_parser *p);
248 void r600_fence_ring_emit(struct radeon_device *rdev,
249 struct radeon_fence *fence);
250 int r600_copy_dma(struct radeon_device *rdev,
254 struct radeon_fence *fence);
255 int r600_irq_process(struct radeon_device *rdev);
256 int r600_irq_set(struct radeon_device *rdev);
257 bool r600_gpu_is_lockup(struct radeon_device *rdev);
258 int r600_gpu_reset(struct radeon_device *rdev);
259 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
260 uint32_t tiling_flags, uint32_t pitch,
261 uint32_t offset, uint32_t obj_size);
262 void r600_clear_surface_reg(struct radeon_device *rdev, int reg);
263 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
264 int r600_ring_test(struct radeon_device *rdev);
265 int r600_copy_blit(struct radeon_device *rdev,
266 uint64_t src_offset, uint64_t dst_offset,
267 unsigned num_pages, struct radeon_fence *fence);
268 void r600_hpd_init(struct radeon_device *rdev);
269 void r600_hpd_fini(struct radeon_device *rdev);
270 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
271 void r600_hpd_set_polarity(struct radeon_device *rdev,
272 enum radeon_hpd_id hpd);
273 extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo);
276 * rv770,rv730,rv710,rv740
278 int rv770_init(struct radeon_device *rdev);
279 void rv770_fini(struct radeon_device *rdev);
280 int rv770_suspend(struct radeon_device *rdev);
281 int rv770_resume(struct radeon_device *rdev);
286 int evergreen_init(struct radeon_device *rdev);
287 void evergreen_fini(struct radeon_device *rdev);
288 int evergreen_suspend(struct radeon_device *rdev);
289 int evergreen_resume(struct radeon_device *rdev);
290 bool evergreen_gpu_is_lockup(struct radeon_device *rdev);
291 int evergreen_gpu_reset(struct radeon_device *rdev);
292 void evergreen_bandwidth_update(struct radeon_device *rdev);
293 void evergreen_hpd_init(struct radeon_device *rdev);
294 void evergreen_hpd_fini(struct radeon_device *rdev);
295 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
296 void evergreen_hpd_set_polarity(struct radeon_device *rdev,
297 enum radeon_hpd_id hpd);