SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/radeon_asic.h

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #ifndef __RADEON_ASIC_H__
  29 #define __RADEON_ASIC_H__
  30
  31 /*
  32  * common functions
  33  */
  34 uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev);
  35 void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
  36 void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
  37
  38 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev);
  39 void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
  40 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev);
  41 void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
  42 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
  43
  44 /*
  45  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
  46  */
  47 extern int r100_init(struct radeon_device *rdev);
  48 extern void r100_fini(struct radeon_device *rdev);
  49 extern int r100_suspend(struct radeon_device *rdev);
  50 extern int r100_resume(struct radeon_device *rdev);
  51 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
  52 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
  53 void r100_vga_set_state(struct radeon_device *rdev, bool state);
  54 int r100_gpu_reset(struct radeon_device *rdev);
  55 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
  56 void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
  57 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
  58 void r100_cp_commit(struct radeon_device *rdev);
  59 void r100_ring_start(struct radeon_device *rdev);
  60 int r100_irq_set(struct radeon_device *rdev);
  61 int r100_irq_process(struct radeon_device *rdev);
  62 void r100_fence_ring_emit(struct radeon_device *rdev,
  63                           struct radeon_fence *fence);
  64 int r100_cs_parse(struct radeon_cs_parser *p);
  65 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
  66 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
  67 int r100_copy_blit(struct radeon_device *rdev,
  68                    uint64_t src_offset,
  69                    uint64_t dst_offset,
  70                    unsigned num_pages,
  71                    struct radeon_fence *fence);
  72 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
  73                          uint32_t tiling_flags, uint32_t pitch,
  74                          uint32_t offset, uint32_t obj_size);
  75 int r100_clear_surface_reg(struct radeon_device *rdev, int reg);
  76 void r100_bandwidth_update(struct radeon_device *rdev);
  77 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
  78 int r100_ring_test(struct radeon_device *rdev);
  79 void r100_hdp_flush(struct radeon_device *rdev);
  80
  81 static struct radeon_asic r100_asic = {
  82         .init = &r100_init,
  83         .fini = &r100_fini,
  84         .suspend = &r100_suspend,
  85         .resume = &r100_resume,
  86         .vga_set_state = &r100_vga_set_state,
  87         .gpu_reset = &r100_gpu_reset,
  88         .gart_tlb_flush = &r100_pci_gart_tlb_flush,
  89         .gart_set_page = &r100_pci_gart_set_page,
  90         .cp_commit = &r100_cp_commit,
  91         .ring_start = &r100_ring_start,
  92         .ring_test = &r100_ring_test,
  93         .ring_ib_execute = &r100_ring_ib_execute,
  94         .irq_set = &r100_irq_set,
  95         .irq_process = &r100_irq_process,
  96         .get_vblank_counter = &r100_get_vblank_counter,
  97         .fence_ring_emit = &r100_fence_ring_emit,
  98         .cs_parse = &r100_cs_parse,
  99         .copy_blit = &r100_copy_blit,
 100         .copy_dma = NULL,
 101         .copy = &r100_copy_blit,
 102         .get_engine_clock = &radeon_legacy_get_engine_clock,
 103         .set_engine_clock = &radeon_legacy_set_engine_clock,
 104         .get_memory_clock = NULL,
 105         .set_memory_clock = NULL,
 106         .set_pcie_lanes = NULL,
 107         .set_clock_gating = &radeon_legacy_set_clock_gating,
 108         .set_surface_reg = r100_set_surface_reg,
 109         .clear_surface_reg = r100_clear_surface_reg,
 110         .bandwidth_update = &r100_bandwidth_update,
 111         .hdp_flush = &r100_hdp_flush,
 112 };
 113
 114
 115 /*
 116  * r300,r350,rv350,rv380
 117  */
 118 extern int r300_init(struct radeon_device *rdev);
 119 extern void r300_fini(struct radeon_device *rdev);
 120 extern int r300_suspend(struct radeon_device *rdev);
 121 extern int r300_resume(struct radeon_device *rdev);
 122 extern int r300_gpu_reset(struct radeon_device *rdev);
 123 extern void r300_ring_start(struct radeon_device *rdev);
 124 extern void r300_fence_ring_emit(struct radeon_device *rdev,
 125                                 struct radeon_fence *fence);
 126 extern int r300_cs_parse(struct radeon_cs_parser *p);
 127 extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
 128 extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
 129 extern uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
 130 extern void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 131 extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
 132 extern int r300_copy_dma(struct radeon_device *rdev,
 133                         uint64_t src_offset,
 134                         uint64_t dst_offset,
 135                         unsigned num_pages,
 136                         struct radeon_fence *fence);
 137 static struct radeon_asic r300_asic = {
 138         .init = &r300_init,
 139         .fini = &r300_fini,
 140         .suspend = &r300_suspend,
 141         .resume = &r300_resume,
 142         .vga_set_state = &r100_vga_set_state,
 143         .gpu_reset = &r300_gpu_reset,
 144         .gart_tlb_flush = &r100_pci_gart_tlb_flush,
 145         .gart_set_page = &r100_pci_gart_set_page,
 146         .cp_commit = &r100_cp_commit,
 147         .ring_start = &r300_ring_start,
 148         .ring_test = &r100_ring_test,
 149         .ring_ib_execute = &r100_ring_ib_execute,
 150         .irq_set = &r100_irq_set,
 151         .irq_process = &r100_irq_process,
 152         .get_vblank_counter = &r100_get_vblank_counter,
 153         .fence_ring_emit = &r300_fence_ring_emit,
 154         .cs_parse = &r300_cs_parse,
 155         .copy_blit = &r100_copy_blit,
 156         .copy_dma = &r300_copy_dma,
 157         .copy = &r100_copy_blit,
 158         .get_engine_clock = &radeon_legacy_get_engine_clock,
 159         .set_engine_clock = &radeon_legacy_set_engine_clock,
 160         .get_memory_clock = NULL,
 161         .set_memory_clock = NULL,
 162         .set_pcie_lanes = &rv370_set_pcie_lanes,
 163         .set_clock_gating = &radeon_legacy_set_clock_gating,
 164         .set_surface_reg = r100_set_surface_reg,
 165         .clear_surface_reg = r100_clear_surface_reg,
 166         .bandwidth_update = &r100_bandwidth_update,
 167         .hdp_flush = &r100_hdp_flush,
 168 };
 169
 170 /*
 171  * r420,r423,rv410
 172  */
 173 extern int r420_init(struct radeon_device *rdev);
 174 extern void r420_fini(struct radeon_device *rdev);
 175 extern int r420_suspend(struct radeon_device *rdev);
 176 extern int r420_resume(struct radeon_device *rdev);
 177 static struct radeon_asic r420_asic = {
 178         .init = &r420_init,
 179         .fini = &r420_fini,
 180         .suspend = &r420_suspend,
 181         .resume = &r420_resume,
 182         .vga_set_state = &r100_vga_set_state,
 183         .gpu_reset = &r300_gpu_reset,
 184         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
 185         .gart_set_page = &rv370_pcie_gart_set_page,
 186         .cp_commit = &r100_cp_commit,
 187         .ring_start = &r300_ring_start,
 188         .ring_test = &r100_ring_test,
 189         .ring_ib_execute = &r100_ring_ib_execute,
 190         .irq_set = &r100_irq_set,
 191         .irq_process = &r100_irq_process,
 192         .get_vblank_counter = &r100_get_vblank_counter,
 193         .fence_ring_emit = &r300_fence_ring_emit,
 194         .cs_parse = &r300_cs_parse,
 195         .copy_blit = &r100_copy_blit,
 196         .copy_dma = &r300_copy_dma,
 197         .copy = &r100_copy_blit,
 198         .get_engine_clock = &radeon_atom_get_engine_clock,
 199         .set_engine_clock = &radeon_atom_set_engine_clock,
 200         .get_memory_clock = &radeon_atom_get_memory_clock,
 201         .set_memory_clock = &radeon_atom_set_memory_clock,
 202         .set_pcie_lanes = &rv370_set_pcie_lanes,
 203         .set_clock_gating = &radeon_atom_set_clock_gating,
 204         .set_surface_reg = r100_set_surface_reg,
 205         .clear_surface_reg = r100_clear_surface_reg,
 206         .bandwidth_update = &r100_bandwidth_update,
 207         .hdp_flush = &r100_hdp_flush,
 208 };
 209
 210
 211 /*
 212  * rs400,rs480
 213  */
 214 extern int rs400_init(struct radeon_device *rdev);
 215 extern void rs400_fini(struct radeon_device *rdev);
 216 extern int rs400_suspend(struct radeon_device *rdev);
 217 extern int rs400_resume(struct radeon_device *rdev);
 218 void rs400_gart_tlb_flush(struct radeon_device *rdev);
 219 int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
 220 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 221 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 222 static struct radeon_asic rs400_asic = {
 223         .init = &rs400_init,
 224         .fini = &rs400_fini,
 225         .suspend = &rs400_suspend,
 226         .resume = &rs400_resume,
 227         .vga_set_state = &r100_vga_set_state,
 228         .gpu_reset = &r300_gpu_reset,
 229         .gart_tlb_flush = &rs400_gart_tlb_flush,
 230         .gart_set_page = &rs400_gart_set_page,
 231         .cp_commit = &r100_cp_commit,
 232         .ring_start = &r300_ring_start,
 233         .ring_test = &r100_ring_test,
 234         .ring_ib_execute = &r100_ring_ib_execute,
 235         .irq_set = &r100_irq_set,
 236         .irq_process = &r100_irq_process,
 237         .get_vblank_counter = &r100_get_vblank_counter,
 238         .fence_ring_emit = &r300_fence_ring_emit,
 239         .cs_parse = &r300_cs_parse,
 240         .copy_blit = &r100_copy_blit,
 241         .copy_dma = &r300_copy_dma,
 242         .copy = &r100_copy_blit,
 243         .get_engine_clock = &radeon_legacy_get_engine_clock,
 244         .set_engine_clock = &radeon_legacy_set_engine_clock,
 245         .get_memory_clock = NULL,
 246         .set_memory_clock = NULL,
 247         .set_pcie_lanes = NULL,
 248         .set_clock_gating = &radeon_legacy_set_clock_gating,
 249         .set_surface_reg = r100_set_surface_reg,
 250         .clear_surface_reg = r100_clear_surface_reg,
 251         .bandwidth_update = &r100_bandwidth_update,
 252         .hdp_flush = &r100_hdp_flush,
 253 };
 254
 255
 256 /*
 257  * rs600.
 258  */
 259 extern int rs600_init(struct radeon_device *rdev);
 260 extern void rs600_fini(struct radeon_device *rdev);
 261 extern int rs600_suspend(struct radeon_device *rdev);
 262 extern int rs600_resume(struct radeon_device *rdev);
 263 int rs600_irq_set(struct radeon_device *rdev);
 264 int rs600_irq_process(struct radeon_device *rdev);
 265 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
 266 void rs600_gart_tlb_flush(struct radeon_device *rdev);
 267 int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
 268 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 269 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 270 void rs600_bandwidth_update(struct radeon_device *rdev);
 271 static struct radeon_asic rs600_asic = {
 272         .init = &rs600_init,
 273         .fini = &rs600_fini,
 274         .suspend = &rs600_suspend,
 275         .resume = &rs600_resume,
 276         .vga_set_state = &r100_vga_set_state,
 277         .gpu_reset = &r300_gpu_reset,
 278         .gart_tlb_flush = &rs600_gart_tlb_flush,
 279         .gart_set_page = &rs600_gart_set_page,
 280         .cp_commit = &r100_cp_commit,
 281         .ring_start = &r300_ring_start,
 282         .ring_test = &r100_ring_test,
 283         .ring_ib_execute = &r100_ring_ib_execute,
 284         .irq_set = &rs600_irq_set,
 285         .irq_process = &rs600_irq_process,
 286         .get_vblank_counter = &rs600_get_vblank_counter,
 287         .fence_ring_emit = &r300_fence_ring_emit,
 288         .cs_parse = &r300_cs_parse,
 289         .copy_blit = &r100_copy_blit,
 290         .copy_dma = &r300_copy_dma,
 291         .copy = &r100_copy_blit,
 292         .get_engine_clock = &radeon_atom_get_engine_clock,
 293         .set_engine_clock = &radeon_atom_set_engine_clock,
 294         .get_memory_clock = &radeon_atom_get_memory_clock,
 295         .set_memory_clock = &radeon_atom_set_memory_clock,
 296         .set_pcie_lanes = NULL,
 297         .set_clock_gating = &radeon_atom_set_clock_gating,
 298         .bandwidth_update = &rs600_bandwidth_update,
 299         .hdp_flush = &r100_hdp_flush,
 300 };
 301
 302
 303 /*
 304  * rs690,rs740
 305  */
 306 int rs690_init(struct radeon_device *rdev);
 307 void rs690_fini(struct radeon_device *rdev);
 308 int rs690_resume(struct radeon_device *rdev);
 309 int rs690_suspend(struct radeon_device *rdev);
 310 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 311 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 312 void rs690_bandwidth_update(struct radeon_device *rdev);
 313 static struct radeon_asic rs690_asic = {
 314         .init = &rs690_init,
 315         .fini = &rs690_fini,
 316         .suspend = &rs690_suspend,
 317         .resume = &rs690_resume,
 318         .vga_set_state = &r100_vga_set_state,
 319         .gpu_reset = &r300_gpu_reset,
 320         .gart_tlb_flush = &rs400_gart_tlb_flush,
 321         .gart_set_page = &rs400_gart_set_page,
 322         .cp_commit = &r100_cp_commit,
 323         .ring_start = &r300_ring_start,
 324         .ring_test = &r100_ring_test,
 325         .ring_ib_execute = &r100_ring_ib_execute,
 326         .irq_set = &rs600_irq_set,
 327         .irq_process = &rs600_irq_process,
 328         .get_vblank_counter = &rs600_get_vblank_counter,
 329         .fence_ring_emit = &r300_fence_ring_emit,
 330         .cs_parse = &r300_cs_parse,
 331         .copy_blit = &r100_copy_blit,
 332         .copy_dma = &r300_copy_dma,
 333         .copy = &r300_copy_dma,
 334         .get_engine_clock = &radeon_atom_get_engine_clock,
 335         .set_engine_clock = &radeon_atom_set_engine_clock,
 336         .get_memory_clock = &radeon_atom_get_memory_clock,
 337         .set_memory_clock = &radeon_atom_set_memory_clock,
 338         .set_pcie_lanes = NULL,
 339         .set_clock_gating = &radeon_atom_set_clock_gating,
 340         .set_surface_reg = r100_set_surface_reg,
 341         .clear_surface_reg = r100_clear_surface_reg,
 342         .bandwidth_update = &rs690_bandwidth_update,
 343         .hdp_flush = &r100_hdp_flush,
 344 };
 345
 346
 347 /*
 348  * rv515
 349  */
 350 int rv515_init(struct radeon_device *rdev);
 351 void rv515_fini(struct radeon_device *rdev);
 352 int rv515_gpu_reset(struct radeon_device *rdev);
 353 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 354 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 355 void rv515_ring_start(struct radeon_device *rdev);
 356 uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
 357 void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 358 void rv515_bandwidth_update(struct radeon_device *rdev);
 359 int rv515_resume(struct radeon_device *rdev);
 360 int rv515_suspend(struct radeon_device *rdev);
 361 static struct radeon_asic rv515_asic = {
 362         .init = &rv515_init,
 363         .fini = &rv515_fini,
 364         .suspend = &rv515_suspend,
 365         .resume = &rv515_resume,
 366         .vga_set_state = &r100_vga_set_state,
 367         .gpu_reset = &rv515_gpu_reset,
 368         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
 369         .gart_set_page = &rv370_pcie_gart_set_page,
 370         .cp_commit = &r100_cp_commit,
 371         .ring_start = &rv515_ring_start,
 372         .ring_test = &r100_ring_test,
 373         .ring_ib_execute = &r100_ring_ib_execute,
 374         .irq_set = &rs600_irq_set,
 375         .irq_process = &rs600_irq_process,
 376         .get_vblank_counter = &rs600_get_vblank_counter,
 377         .fence_ring_emit = &r300_fence_ring_emit,
 378         .cs_parse = &r300_cs_parse,
 379         .copy_blit = &r100_copy_blit,
 380         .copy_dma = &r300_copy_dma,
 381         .copy = &r100_copy_blit,
 382         .get_engine_clock = &radeon_atom_get_engine_clock,
 383         .set_engine_clock = &radeon_atom_set_engine_clock,
 384         .get_memory_clock = &radeon_atom_get_memory_clock,
 385         .set_memory_clock = &radeon_atom_set_memory_clock,
 386         .set_pcie_lanes = &rv370_set_pcie_lanes,
 387         .set_clock_gating = &radeon_atom_set_clock_gating,
 388         .set_surface_reg = r100_set_surface_reg,
 389         .clear_surface_reg = r100_clear_surface_reg,
 390         .bandwidth_update = &rv515_bandwidth_update,
 391         .hdp_flush = &r100_hdp_flush,
 392 };
 393
 394
 395 /*
 396  * r520,rv530,rv560,rv570,r580
 397  */
 398 int r520_init(struct radeon_device *rdev);
 399 int r520_resume(struct radeon_device *rdev);
 400 static struct radeon_asic r520_asic = {
 401         .init = &r520_init,
 402         .fini = &rv515_fini,
 403         .suspend = &rv515_suspend,
 404         .resume = &r520_resume,
 405         .vga_set_state = &r100_vga_set_state,
 406         .gpu_reset = &rv515_gpu_reset,
 407         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
 408         .gart_set_page = &rv370_pcie_gart_set_page,
 409         .cp_commit = &r100_cp_commit,
 410         .ring_start = &rv515_ring_start,
 411         .ring_test = &r100_ring_test,
 412         .ring_ib_execute = &r100_ring_ib_execute,
 413         .irq_set = &rs600_irq_set,
 414         .irq_process = &rs600_irq_process,
 415         .get_vblank_counter = &rs600_get_vblank_counter,
 416         .fence_ring_emit = &r300_fence_ring_emit,
 417         .cs_parse = &r300_cs_parse,
 418         .copy_blit = &r100_copy_blit,
 419         .copy_dma = &r300_copy_dma,
 420         .copy = &r100_copy_blit,
 421         .get_engine_clock = &radeon_atom_get_engine_clock,
 422         .set_engine_clock = &radeon_atom_set_engine_clock,
 423         .get_memory_clock = &radeon_atom_get_memory_clock,
 424         .set_memory_clock = &radeon_atom_set_memory_clock,
 425         .set_pcie_lanes = &rv370_set_pcie_lanes,
 426         .set_clock_gating = &radeon_atom_set_clock_gating,
 427         .set_surface_reg = r100_set_surface_reg,
 428         .clear_surface_reg = r100_clear_surface_reg,
 429         .bandwidth_update = &rv515_bandwidth_update,
 430         .hdp_flush = &r100_hdp_flush,
 431 };
 432
 433 /*
 434  * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
 435  */
 436 int r600_init(struct radeon_device *rdev);
 437 void r600_fini(struct radeon_device *rdev);
 438 int r600_suspend(struct radeon_device *rdev);
 439 int r600_resume(struct radeon_device *rdev);
 440 void r600_vga_set_state(struct radeon_device *rdev, bool state);
 441 int r600_wb_init(struct radeon_device *rdev);
 442 void r600_wb_fini(struct radeon_device *rdev);
 443 void r600_cp_commit(struct radeon_device *rdev);
 444 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
 445 uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
 446 void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 447 int r600_cs_parse(struct radeon_cs_parser *p);
 448 void r600_fence_ring_emit(struct radeon_device *rdev,
 449                           struct radeon_fence *fence);
 450 int r600_copy_dma(struct radeon_device *rdev,
 451                   uint64_t src_offset,
 452                   uint64_t dst_offset,
 453                   unsigned num_pages,
 454                   struct radeon_fence *fence);
 455 int r600_irq_process(struct radeon_device *rdev);
 456 int r600_irq_set(struct radeon_device *rdev);
 457 int r600_gpu_reset(struct radeon_device *rdev);
 458 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
 459                          uint32_t tiling_flags, uint32_t pitch,
 460                          uint32_t offset, uint32_t obj_size);
 461 int r600_clear_surface_reg(struct radeon_device *rdev, int reg);
 462 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
 463 int r600_ring_test(struct radeon_device *rdev);
 464 int r600_copy_blit(struct radeon_device *rdev,
 465                    uint64_t src_offset, uint64_t dst_offset,
 466                    unsigned num_pages, struct radeon_fence *fence);
 467 void r600_hdp_flush(struct radeon_device *rdev);
 468
 469 static struct radeon_asic r600_asic = {
 470         .init = &r600_init,
 471         .fini = &r600_fini,
 472         .suspend = &r600_suspend,
 473         .resume = &r600_resume,
 474         .cp_commit = &r600_cp_commit,
 475         .vga_set_state = &r600_vga_set_state,
 476         .gpu_reset = &r600_gpu_reset,
 477         .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
 478         .gart_set_page = &rs600_gart_set_page,
 479         .ring_test = &r600_ring_test,
 480         .ring_ib_execute = &r600_ring_ib_execute,
 481         .irq_set = &r600_irq_set,
 482         .irq_process = &r600_irq_process,
 483         .fence_ring_emit = &r600_fence_ring_emit,
 484         .cs_parse = &r600_cs_parse,
 485         .copy_blit = &r600_copy_blit,
 486         .copy_dma = &r600_copy_blit,
 487         .copy = &r600_copy_blit,
 488         .get_engine_clock = &radeon_atom_get_engine_clock,
 489         .set_engine_clock = &radeon_atom_set_engine_clock,
 490         .get_memory_clock = &radeon_atom_get_memory_clock,
 491         .set_memory_clock = &radeon_atom_set_memory_clock,
 492         .set_pcie_lanes = NULL,
 493         .set_clock_gating = &radeon_atom_set_clock_gating,
 494         .set_surface_reg = r600_set_surface_reg,
 495         .clear_surface_reg = r600_clear_surface_reg,
 496         .bandwidth_update = &rv515_bandwidth_update,
 497         .hdp_flush = &r600_hdp_flush,
 498 };
 499
 500 /*
 501  * rv770,rv730,rv710,rv740
 502  */
 503 int rv770_init(struct radeon_device *rdev);
 504 void rv770_fini(struct radeon_device *rdev);
 505 int rv770_suspend(struct radeon_device *rdev);
 506 int rv770_resume(struct radeon_device *rdev);
 507 int rv770_gpu_reset(struct radeon_device *rdev);
 508
 509 static struct radeon_asic rv770_asic = {
 510         .init = &rv770_init,
 511         .fini = &rv770_fini,
 512         .suspend = &rv770_suspend,
 513         .resume = &rv770_resume,
 514         .cp_commit = &r600_cp_commit,
 515         .gpu_reset = &rv770_gpu_reset,
 516         .vga_set_state = &r600_vga_set_state,
 517         .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
 518         .gart_set_page = &rs600_gart_set_page,
 519         .ring_test = &r600_ring_test,
 520         .ring_ib_execute = &r600_ring_ib_execute,
 521         .irq_set = &r600_irq_set,
 522         .irq_process = &r600_irq_process,
 523         .fence_ring_emit = &r600_fence_ring_emit,
 524         .cs_parse = &r600_cs_parse,
 525         .copy_blit = &r600_copy_blit,
 526         .copy_dma = &r600_copy_blit,
 527         .copy = &r600_copy_blit,
 528         .get_engine_clock = &radeon_atom_get_engine_clock,
 529         .set_engine_clock = &radeon_atom_set_engine_clock,
 530         .get_memory_clock = &radeon_atom_get_memory_clock,
 531         .set_memory_clock = &radeon_atom_set_memory_clock,
 532         .set_pcie_lanes = NULL,
 533         .set_clock_gating = &radeon_atom_set_clock_gating,
 534         .set_surface_reg = r600_set_surface_reg,
 535         .clear_surface_reg = r600_clear_surface_reg,
 536         .bandwidth_update = &rv515_bandwidth_update,
 537         .hdp_flush = &r600_hdp_flush,
 538 };
 539
 540 #endif