2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
63 #include <asm/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
73 #include "radeon_family.h"
74 #include "radeon_mode.h"
75 #include "radeon_reg.h"
80 extern int radeon_no_wb;
81 extern int radeon_modeset;
82 extern int radeon_dynclks;
83 extern int radeon_r4xx_atom;
84 extern int radeon_agpmode;
85 extern int radeon_vram_limit;
86 extern int radeon_gart_size;
87 extern int radeon_benchmarking;
88 extern int radeon_testing;
89 extern int radeon_connector_table;
91 extern int radeon_new_pll;
92 extern int radeon_dynpm;
93 extern int radeon_audio;
96 * Copy from radeon_drv.h so we don't have to include both and have conflicting
99 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
100 /* RADEON_IB_POOL_SIZE must be a power of 2 */
101 #define RADEON_IB_POOL_SIZE 16
102 #define RADEON_DEBUGFS_MAX_NUM_FILES 32
103 #define RADEONFB_CONN_LIMIT 4
104 #define RADEON_BIOS_NUM_SCRATCH 8
107 * Errata workarounds.
109 enum radeon_pll_errata {
110 CHIP_ERRATA_R300_CG = 0x00000001,
111 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
112 CHIP_ERRATA_PLL_DELAY = 0x00000004
116 struct radeon_device;
122 bool radeon_get_bios(struct radeon_device *rdev);
128 struct radeon_dummy_page {
132 int radeon_dummy_page_init(struct radeon_device *rdev);
133 void radeon_dummy_page_fini(struct radeon_device *rdev);
139 struct radeon_clock {
140 struct radeon_pll p1pll;
141 struct radeon_pll p2pll;
142 struct radeon_pll dcpll;
143 struct radeon_pll spll;
144 struct radeon_pll mpll;
146 uint32_t default_mclk;
147 uint32_t default_sclk;
148 uint32_t default_dispclk;
155 int radeon_pm_init(struct radeon_device *rdev);
156 void radeon_pm_compute_clocks(struct radeon_device *rdev);
157 void radeon_combios_get_power_modes(struct radeon_device *rdev);
158 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
163 struct radeon_fence_driver {
164 uint32_t scratch_reg;
167 unsigned long count_timeout;
168 wait_queue_head_t queue;
170 struct list_head created;
171 struct list_head emited;
172 struct list_head signaled;
176 struct radeon_fence {
177 struct radeon_device *rdev;
179 struct list_head list;
180 /* protected by radeon_fence.lock */
182 unsigned long timeout;
187 int radeon_fence_driver_init(struct radeon_device *rdev);
188 void radeon_fence_driver_fini(struct radeon_device *rdev);
189 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
190 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
191 void radeon_fence_process(struct radeon_device *rdev);
192 bool radeon_fence_signaled(struct radeon_fence *fence);
193 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
194 int radeon_fence_wait_next(struct radeon_device *rdev);
195 int radeon_fence_wait_last(struct radeon_device *rdev);
196 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
197 void radeon_fence_unref(struct radeon_fence **fence);
202 struct radeon_surface_reg {
203 struct radeon_bo *bo;
206 #define RADEON_GEM_MAX_SURFACES 8
212 struct ttm_bo_global_ref bo_global_ref;
213 struct ttm_global_reference mem_global_ref;
214 struct ttm_bo_device bdev;
215 bool mem_global_referenced;
220 /* Protected by gem.mutex */
221 struct list_head list;
222 /* Protected by tbo.reserved */
224 struct ttm_placement placement;
225 struct ttm_buffer_object tbo;
226 struct ttm_bo_kmap_obj kmap;
232 /* Constant after initialization */
233 struct radeon_device *rdev;
234 struct drm_gem_object *gobj;
237 struct radeon_bo_list {
238 struct list_head list;
239 struct radeon_bo *bo;
251 struct list_head objects;
254 int radeon_gem_init(struct radeon_device *rdev);
255 void radeon_gem_fini(struct radeon_device *rdev);
256 int radeon_gem_object_create(struct radeon_device *rdev, int size,
257 int alignment, int initial_domain,
258 bool discardable, bool kernel,
259 struct drm_gem_object **obj);
260 int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
262 void radeon_gem_object_unpin(struct drm_gem_object *obj);
266 * GART structures, functions & helpers
270 struct radeon_gart_table_ram {
271 volatile uint32_t *ptr;
274 struct radeon_gart_table_vram {
275 struct radeon_bo *robj;
276 volatile uint32_t *ptr;
279 union radeon_gart_table {
280 struct radeon_gart_table_ram ram;
281 struct radeon_gart_table_vram vram;
284 #define RADEON_GPU_PAGE_SIZE 4096
287 dma_addr_t table_addr;
288 unsigned num_gpu_pages;
289 unsigned num_cpu_pages;
291 union radeon_gart_table table;
293 dma_addr_t *pages_addr;
297 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
298 void radeon_gart_table_ram_free(struct radeon_device *rdev);
299 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
300 void radeon_gart_table_vram_free(struct radeon_device *rdev);
301 int radeon_gart_init(struct radeon_device *rdev);
302 void radeon_gart_fini(struct radeon_device *rdev);
303 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
305 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
306 int pages, struct page **pagelist);
310 * GPU MC structures, functions & helpers
313 resource_size_t aper_size;
314 resource_size_t aper_base;
315 resource_size_t agp_base;
316 /* for some chips with <= 32MB we need to lie
317 * about vram size near mc fb location */
330 bool igp_sideport_enabled;
333 int radeon_mc_setup(struct radeon_device *rdev);
334 bool radeon_combios_sideport_present(struct radeon_device *rdev);
335 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
338 * GPU scratch registers structures, functions & helpers
340 struct radeon_scratch {
346 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
347 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
356 /* FIXME: use a define max crtc rather than hardcode it */
357 bool crtc_vblank_int[2];
358 wait_queue_head_t vblank_queue;
359 /* FIXME: use defines for max hpd/dacs */
365 int radeon_irq_kms_init(struct radeon_device *rdev);
366 void radeon_irq_kms_fini(struct radeon_device *rdev);
367 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
368 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
374 struct list_head list;
377 struct radeon_fence *fence;
385 * mutex protects scheduled_ibs, ready, alloc_bm
387 struct radeon_ib_pool {
389 struct radeon_bo *robj;
390 struct list_head bogus_ib;
391 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
397 struct radeon_bo *ring_obj;
398 volatile uint32_t *ring;
403 unsigned ring_free_dw;
416 struct radeon_bo *ring_obj;
417 volatile uint32_t *ring;
430 struct radeon_bo *shader_obj;
432 u32 vs_offset, ps_offset;
435 u32 vb_used, vb_total;
436 struct radeon_ib *vb_ib;
439 int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
440 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
441 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
442 int radeon_ib_pool_init(struct radeon_device *rdev);
443 void radeon_ib_pool_fini(struct radeon_device *rdev);
444 int radeon_ib_test(struct radeon_device *rdev);
445 extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib);
446 /* Ring access between begin & end cannot sleep */
447 void radeon_ring_free_size(struct radeon_device *rdev);
448 int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
449 void radeon_ring_unlock_commit(struct radeon_device *rdev);
450 void radeon_ring_unlock_undo(struct radeon_device *rdev);
451 int radeon_ring_test(struct radeon_device *rdev);
452 int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
453 void radeon_ring_fini(struct radeon_device *rdev);
459 struct radeon_cs_reloc {
460 struct drm_gem_object *gobj;
461 struct radeon_bo *robj;
462 struct radeon_bo_list lobj;
467 struct radeon_cs_chunk {
473 void __user *user_ptr;
474 int last_copied_page;
478 struct radeon_cs_parser {
480 struct radeon_device *rdev;
481 struct drm_file *filp;
484 struct radeon_cs_chunk *chunks;
485 uint64_t *chunks_array;
490 struct radeon_cs_reloc *relocs;
491 struct radeon_cs_reloc **relocs_ptr;
492 struct list_head validated;
493 /* indices of various chunks */
495 int chunk_relocs_idx;
496 struct radeon_ib *ib;
502 extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
503 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
506 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
508 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
509 u32 pg_idx, pg_offset;
513 pg_idx = (idx * 4) / PAGE_SIZE;
514 pg_offset = (idx * 4) % PAGE_SIZE;
516 if (ibc->kpage_idx[0] == pg_idx)
517 return ibc->kpage[0][pg_offset/4];
518 if (ibc->kpage_idx[1] == pg_idx)
519 return ibc->kpage[1][pg_offset/4];
521 new_page = radeon_cs_update_pages(p, pg_idx);
523 p->parser_error = new_page;
527 idx_value = ibc->kpage[new_page][pg_offset/4];
531 struct radeon_cs_packet {
540 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
541 struct radeon_cs_packet *pkt,
542 unsigned idx, unsigned reg);
543 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
544 struct radeon_cs_packet *pkt);
550 int radeon_agp_init(struct radeon_device *rdev);
551 void radeon_agp_resume(struct radeon_device *rdev);
552 void radeon_agp_fini(struct radeon_device *rdev);
559 struct radeon_bo *wb_obj;
560 volatile uint32_t *wb;
565 * struct radeon_pm - power management datas
566 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
567 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
568 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
569 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
570 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
571 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
572 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
573 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
574 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
575 * @sclk: GPU clock Mhz (core bandwith depends of this clock)
576 * @needed_bandwidth: current bandwidth needs
578 * It keeps track of various data needed to take powermanagement decision.
579 * Bandwith need is used to determine minimun clock of the GPU and memory.
580 * Equation between gpu/memory clock and available bandwidth is hw dependent
581 * (type of memory, bus size, efficiency, ...)
583 enum radeon_pm_state {
589 enum radeon_pm_action {
596 enum radeon_voltage_type {
603 enum radeon_pm_state_type {
604 POWER_STATE_TYPE_DEFAULT,
605 POWER_STATE_TYPE_POWERSAVE,
606 POWER_STATE_TYPE_BATTERY,
607 POWER_STATE_TYPE_BALANCED,
608 POWER_STATE_TYPE_PERFORMANCE,
611 enum radeon_pm_clock_mode_type {
612 POWER_MODE_TYPE_DEFAULT,
615 POWER_MODE_TYPE_HIGH,
618 struct radeon_voltage {
619 enum radeon_voltage_type type;
621 struct radeon_gpio_rec gpio;
622 u32 delay; /* delay in usec from voltage drop to sclk change */
623 bool active_high; /* voltage drop is active when bit is high */
625 u8 vddc_id; /* index into vddc voltage table */
626 u8 vddci_id; /* index into vddci voltage table */
632 struct radeon_pm_non_clock_info {
635 /* standardized non-clock flags */
639 struct radeon_pm_clock_info {
645 struct radeon_voltage voltage;
646 /* standardized clock flags - not sure we'll need these */
650 struct radeon_power_state {
651 enum radeon_pm_state_type type;
652 /* XXX: use a define for num clock modes */
653 struct radeon_pm_clock_info clock_info[8];
654 /* number of valid clock modes in this power state */
656 /* currently selected clock mode */
657 struct radeon_pm_clock_info *current_clock_mode;
658 struct radeon_pm_clock_info *requested_clock_mode;
659 struct radeon_pm_clock_info *default_clock_mode;
660 /* non clock info about this state */
661 struct radeon_pm_non_clock_info non_clock_info;
662 bool voltage_drop_active;
667 struct delayed_work idle_work;
668 enum radeon_pm_state state;
669 enum radeon_pm_action planned_action;
670 unsigned long action_timeout;
674 fixed20_12 max_bandwidth;
675 fixed20_12 igp_sideport_mclk;
676 fixed20_12 igp_system_mclk;
677 fixed20_12 igp_ht_link_clk;
678 fixed20_12 igp_ht_link_width;
679 fixed20_12 k8_bandwidth;
680 fixed20_12 sideport_bandwidth;
681 fixed20_12 ht_bandwidth;
682 fixed20_12 core_bandwidth;
684 fixed20_12 needed_bandwidth;
685 /* XXX: use a define for num power modes */
686 struct radeon_power_state power_state[8];
687 /* number of valid power states */
688 int num_power_states;
689 struct radeon_power_state *current_power_state;
690 struct radeon_power_state *requested_power_state;
691 struct radeon_power_state *default_power_state;
698 void radeon_benchmark(struct radeon_device *rdev);
704 void radeon_test_moves(struct radeon_device *rdev);
710 int radeon_debugfs_add_files(struct radeon_device *rdev,
711 struct drm_info_list *files,
713 int radeon_debugfs_fence_init(struct radeon_device *rdev);
714 int r100_debugfs_rbbm_init(struct radeon_device *rdev);
715 int r100_debugfs_cp_init(struct radeon_device *rdev);
719 * ASIC specific functions.
722 int (*init)(struct radeon_device *rdev);
723 void (*fini)(struct radeon_device *rdev);
724 int (*resume)(struct radeon_device *rdev);
725 int (*suspend)(struct radeon_device *rdev);
726 void (*vga_set_state)(struct radeon_device *rdev, bool state);
727 int (*gpu_reset)(struct radeon_device *rdev);
728 void (*gart_tlb_flush)(struct radeon_device *rdev);
729 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
730 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
731 void (*cp_fini)(struct radeon_device *rdev);
732 void (*cp_disable)(struct radeon_device *rdev);
733 void (*cp_commit)(struct radeon_device *rdev);
734 void (*ring_start)(struct radeon_device *rdev);
735 int (*ring_test)(struct radeon_device *rdev);
736 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
737 int (*irq_set)(struct radeon_device *rdev);
738 int (*irq_process)(struct radeon_device *rdev);
739 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
740 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
741 int (*cs_parse)(struct radeon_cs_parser *p);
742 int (*copy_blit)(struct radeon_device *rdev,
746 struct radeon_fence *fence);
747 int (*copy_dma)(struct radeon_device *rdev,
751 struct radeon_fence *fence);
752 int (*copy)(struct radeon_device *rdev,
756 struct radeon_fence *fence);
757 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
758 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
759 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
760 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
761 int (*get_pcie_lanes)(struct radeon_device *rdev);
762 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
763 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
764 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
765 uint32_t tiling_flags, uint32_t pitch,
766 uint32_t offset, uint32_t obj_size);
767 int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
768 void (*bandwidth_update)(struct radeon_device *rdev);
769 void (*hpd_init)(struct radeon_device *rdev);
770 void (*hpd_fini)(struct radeon_device *rdev);
771 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
772 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
773 /* ioctl hw specific callback. Some hw might want to perform special
774 * operation on specific ioctl. For instance on wait idle some hw
775 * might want to perform and HDP flush through MMIO as it seems that
776 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
779 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
786 const unsigned *reg_safe_bm;
787 unsigned reg_safe_bm_size;
792 const unsigned *reg_safe_bm;
793 unsigned reg_safe_bm_size;
800 unsigned max_tile_pipes;
802 unsigned max_backends;
804 unsigned max_threads;
805 unsigned max_stack_entries;
806 unsigned max_hw_contexts;
807 unsigned max_gs_threads;
808 unsigned sx_max_export_size;
809 unsigned sx_max_export_pos_size;
810 unsigned sx_max_export_smx_size;
811 unsigned sq_num_cf_insts;
812 unsigned tiling_nbanks;
813 unsigned tiling_npipes;
814 unsigned tiling_group_size;
819 unsigned max_tile_pipes;
821 unsigned max_backends;
823 unsigned max_threads;
824 unsigned max_stack_entries;
825 unsigned max_hw_contexts;
826 unsigned max_gs_threads;
827 unsigned sx_max_export_size;
828 unsigned sx_max_export_pos_size;
829 unsigned sx_max_export_smx_size;
830 unsigned sq_num_cf_insts;
831 unsigned sx_num_of_sets;
832 unsigned sc_prim_fifo_size;
833 unsigned sc_hiz_tile_fifo_size;
834 unsigned sc_earlyz_tile_fifo_fize;
835 unsigned tiling_nbanks;
836 unsigned tiling_npipes;
837 unsigned tiling_group_size;
840 union radeon_asic_config {
841 struct r300_asic r300;
842 struct r100_asic r100;
843 struct r600_asic r600;
844 struct rv770_asic rv770;
851 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
852 struct drm_file *filp);
853 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
854 struct drm_file *filp);
855 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
856 struct drm_file *file_priv);
857 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
858 struct drm_file *file_priv);
859 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
860 struct drm_file *file_priv);
861 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
862 struct drm_file *file_priv);
863 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
864 struct drm_file *filp);
865 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
866 struct drm_file *filp);
867 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
868 struct drm_file *filp);
869 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
870 struct drm_file *filp);
871 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
872 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
873 struct drm_file *filp);
874 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
875 struct drm_file *filp);
879 * Core structure, functions and helpers.
881 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
882 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
884 struct radeon_device {
886 struct drm_device *ddev;
887 struct pci_dev *pdev;
889 union radeon_asic_config config;
890 enum radeon_family family;
893 enum radeon_pll_errata pll_errata;
900 uint16_t bios_header_start;
901 struct radeon_bo *stollen_vga_memory;
902 struct fb_info *fbdev_info;
903 struct radeon_bo *fbdev_rbo;
904 struct radeon_framebuffer *fbdev_rfb;
906 resource_size_t rmmio_base;
907 resource_size_t rmmio_size;
909 radeon_rreg_t mc_rreg;
910 radeon_wreg_t mc_wreg;
911 radeon_rreg_t pll_rreg;
912 radeon_wreg_t pll_wreg;
913 uint32_t pcie_reg_mask;
914 radeon_rreg_t pciep_rreg;
915 radeon_wreg_t pciep_wreg;
916 struct radeon_clock clock;
918 struct radeon_gart gart;
919 struct radeon_mode_info mode_info;
920 struct radeon_scratch scratch;
921 struct radeon_mman mman;
922 struct radeon_fence_driver fence_drv;
924 struct radeon_ib_pool ib_pool;
925 struct radeon_irq irq;
926 struct radeon_asic *asic;
927 struct radeon_gem gem;
929 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
930 struct mutex cs_mutex;
932 struct radeon_dummy_page dummy_page;
938 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
939 const struct firmware *me_fw; /* all family ME firmware */
940 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
941 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
942 struct r600_blit r600_blit;
943 int msi_enabled; /* msi enabled */
944 struct r600_ih ih; /* r6/700 interrupt ring */
945 struct workqueue_struct *wq;
946 struct work_struct hotplug_work;
947 int num_crtc; /* number of crtcs */
948 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
951 struct timer_list audio_timer;
954 int audio_bits_per_sample;
955 uint8_t audio_status_bits;
956 uint8_t audio_category_code;
959 int radeon_device_init(struct radeon_device *rdev,
960 struct drm_device *ddev,
961 struct pci_dev *pdev,
963 void radeon_device_fini(struct radeon_device *rdev);
964 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
967 int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
968 void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
969 void r600_kms_blit_copy(struct radeon_device *rdev,
970 u64 src_gpu_addr, u64 dst_gpu_addr,
973 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
975 if (reg < rdev->rmmio_size)
976 return readl(((void __iomem *)rdev->rmmio) + reg);
978 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
979 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
983 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
985 if (reg < rdev->rmmio_size)
986 writel(v, ((void __iomem *)rdev->rmmio) + reg);
988 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
989 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
996 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
999 * Registers read & write functions.
1001 #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
1002 #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
1003 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
1004 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
1005 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
1006 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1007 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1008 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1009 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1010 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1011 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1012 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1013 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1014 #define WREG32_P(reg, val, mask) \
1016 uint32_t tmp_ = RREG32(reg); \
1018 tmp_ |= ((val) & ~(mask)); \
1019 WREG32(reg, tmp_); \
1021 #define WREG32_PLL_P(reg, val, mask) \
1023 uint32_t tmp_ = RREG32_PLL(reg); \
1025 tmp_ |= ((val) & ~(mask)); \
1026 WREG32_PLL(reg, tmp_); \
1028 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1031 * Indirect registers accessor
1033 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1037 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1038 r = RREG32(RADEON_PCIE_DATA);
1042 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1044 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1045 WREG32(RADEON_PCIE_DATA, (v));
1048 void r100_pll_errata_after_index(struct radeon_device *rdev);
1054 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1055 (rdev->pdev->device == 0x5969))
1056 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1057 (rdev->family == CHIP_RV200) || \
1058 (rdev->family == CHIP_RS100) || \
1059 (rdev->family == CHIP_RS200) || \
1060 (rdev->family == CHIP_RV250) || \
1061 (rdev->family == CHIP_RV280) || \
1062 (rdev->family == CHIP_RS300))
1063 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1064 (rdev->family == CHIP_RV350) || \
1065 (rdev->family == CHIP_R350) || \
1066 (rdev->family == CHIP_RV380) || \
1067 (rdev->family == CHIP_R420) || \
1068 (rdev->family == CHIP_R423) || \
1069 (rdev->family == CHIP_RV410) || \
1070 (rdev->family == CHIP_RS400) || \
1071 (rdev->family == CHIP_RS480))
1072 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1073 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1074 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1075 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1080 #define RBIOS8(i) (rdev->bios[i])
1081 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1082 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1084 int radeon_combios_init(struct radeon_device *rdev);
1085 void radeon_combios_fini(struct radeon_device *rdev);
1086 int radeon_atombios_init(struct radeon_device *rdev);
1087 void radeon_atombios_fini(struct radeon_device *rdev);
1093 static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
1096 if (rdev->cp.count_dw <= 0) {
1097 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
1100 rdev->cp.ring[rdev->cp.wptr++] = v;
1101 rdev->cp.wptr &= rdev->cp.ptr_mask;
1102 rdev->cp.count_dw--;
1103 rdev->cp.ring_free_dw--;
1110 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1111 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1112 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1113 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1114 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
1115 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1116 #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
1117 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
1118 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
1119 #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
1120 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
1121 #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
1122 #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
1123 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
1124 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
1125 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
1126 #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
1127 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1128 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1129 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
1130 #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
1131 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
1132 #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
1133 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
1134 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
1135 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1136 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
1137 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1138 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
1139 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
1140 #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1141 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1142 #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1143 #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
1145 /* Common functions */
1147 extern void radeon_agp_disable(struct radeon_device *rdev);
1148 extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
1149 extern void radeon_gart_restore(struct radeon_device *rdev);
1150 extern int radeon_modeset_init(struct radeon_device *rdev);
1151 extern void radeon_modeset_fini(struct radeon_device *rdev);
1152 extern bool radeon_card_posted(struct radeon_device *rdev);
1153 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1154 extern int radeon_clocks_init(struct radeon_device *rdev);
1155 extern void radeon_clocks_fini(struct radeon_device *rdev);
1156 extern void radeon_scratch_init(struct radeon_device *rdev);
1157 extern void radeon_surface_init(struct radeon_device *rdev);
1158 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1159 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1160 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1161 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1162 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1164 /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
1165 struct r100_mc_save {
1173 extern void r100_cp_disable(struct radeon_device *rdev);
1174 extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
1175 extern void r100_cp_fini(struct radeon_device *rdev);
1176 extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
1177 extern int r100_pci_gart_init(struct radeon_device *rdev);
1178 extern void r100_pci_gart_fini(struct radeon_device *rdev);
1179 extern int r100_pci_gart_enable(struct radeon_device *rdev);
1180 extern void r100_pci_gart_disable(struct radeon_device *rdev);
1181 extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
1182 extern int r100_debugfs_mc_info_init(struct radeon_device *rdev);
1183 extern int r100_gui_wait_for_idle(struct radeon_device *rdev);
1184 extern void r100_ib_fini(struct radeon_device *rdev);
1185 extern int r100_ib_init(struct radeon_device *rdev);
1186 extern void r100_irq_disable(struct radeon_device *rdev);
1187 extern int r100_irq_set(struct radeon_device *rdev);
1188 extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
1189 extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
1190 extern void r100_vram_init_sizes(struct radeon_device *rdev);
1191 extern void r100_wb_disable(struct radeon_device *rdev);
1192 extern void r100_wb_fini(struct radeon_device *rdev);
1193 extern int r100_wb_init(struct radeon_device *rdev);
1194 extern void r100_hdp_reset(struct radeon_device *rdev);
1195 extern int r100_rb2d_reset(struct radeon_device *rdev);
1196 extern int r100_cp_reset(struct radeon_device *rdev);
1197 extern void r100_vga_render_disable(struct radeon_device *rdev);
1198 extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1199 struct radeon_cs_packet *pkt,
1200 struct radeon_bo *robj);
1201 extern int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1202 struct radeon_cs_packet *pkt,
1203 const unsigned *auth, unsigned n,
1204 radeon_packet0_check_t check);
1205 extern int r100_cs_packet_parse(struct radeon_cs_parser *p,
1206 struct radeon_cs_packet *pkt,
1208 extern void r100_enable_bm(struct radeon_device *rdev);
1209 extern void r100_set_common_regs(struct radeon_device *rdev);
1211 /* rv200,rv250,rv280 */
1212 extern void r200_set_safe_registers(struct radeon_device *rdev);
1214 /* r300,r350,rv350,rv370,rv380 */
1215 extern void r300_set_reg_safe(struct radeon_device *rdev);
1216 extern void r300_mc_program(struct radeon_device *rdev);
1217 extern void r300_vram_info(struct radeon_device *rdev);
1218 extern void r300_clock_startup(struct radeon_device *rdev);
1219 extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
1220 extern int rv370_pcie_gart_init(struct radeon_device *rdev);
1221 extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
1222 extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
1223 extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
1225 /* r420,r423,rv410 */
1226 extern int r420_mc_init(struct radeon_device *rdev);
1227 extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
1228 extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1229 extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
1230 extern void r420_pipes_init(struct radeon_device *rdev);
1233 struct rv515_mc_save {
1236 u32 vga_render_control;
1237 u32 vga_hdp_control;
1241 extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
1242 extern void rv515_vga_render_disable(struct radeon_device *rdev);
1243 extern void rv515_set_safe_registers(struct radeon_device *rdev);
1244 extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
1245 extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
1246 extern void rv515_clock_startup(struct radeon_device *rdev);
1247 extern void rv515_debugfs(struct radeon_device *rdev);
1248 extern int rv515_suspend(struct radeon_device *rdev);
1251 extern int rs400_gart_init(struct radeon_device *rdev);
1252 extern int rs400_gart_enable(struct radeon_device *rdev);
1253 extern void rs400_gart_adjust_size(struct radeon_device *rdev);
1254 extern void rs400_gart_disable(struct radeon_device *rdev);
1255 extern void rs400_gart_fini(struct radeon_device *rdev);
1258 extern void rs600_set_safe_registers(struct radeon_device *rdev);
1259 extern int rs600_irq_set(struct radeon_device *rdev);
1260 extern void rs600_irq_disable(struct radeon_device *rdev);
1263 extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
1264 struct drm_display_mode *mode1,
1265 struct drm_display_mode *mode2);
1267 /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
1268 extern bool r600_card_posted(struct radeon_device *rdev);
1269 extern void r600_cp_stop(struct radeon_device *rdev);
1270 extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
1271 extern int r600_cp_resume(struct radeon_device *rdev);
1272 extern void r600_cp_fini(struct radeon_device *rdev);
1273 extern int r600_count_pipe_bits(uint32_t val);
1274 extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
1275 extern int r600_pcie_gart_init(struct radeon_device *rdev);
1276 extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
1277 extern int r600_ib_test(struct radeon_device *rdev);
1278 extern int r600_ring_test(struct radeon_device *rdev);
1279 extern void r600_wb_fini(struct radeon_device *rdev);
1280 extern int r600_wb_enable(struct radeon_device *rdev);
1281 extern void r600_wb_disable(struct radeon_device *rdev);
1282 extern void r600_scratch_init(struct radeon_device *rdev);
1283 extern int r600_blit_init(struct radeon_device *rdev);
1284 extern void r600_blit_fini(struct radeon_device *rdev);
1285 extern int r600_init_microcode(struct radeon_device *rdev);
1286 extern int r600_gpu_reset(struct radeon_device *rdev);
1288 extern int r600_irq_init(struct radeon_device *rdev);
1289 extern void r600_irq_fini(struct radeon_device *rdev);
1290 extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
1291 extern int r600_irq_set(struct radeon_device *rdev);
1292 extern void r600_irq_suspend(struct radeon_device *rdev);
1294 extern int r600_audio_init(struct radeon_device *rdev);
1295 extern int r600_audio_tmds_index(struct drm_encoder *encoder);
1296 extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
1297 extern void r600_audio_fini(struct radeon_device *rdev);
1298 extern void r600_hdmi_init(struct drm_encoder *encoder);
1299 extern void r600_hdmi_enable(struct drm_encoder *encoder, int enable);
1300 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1301 extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
1302 extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder,
1306 uint8_t status_bits,
1307 uint8_t category_code);
1310 struct evergreen_mc_save {
1312 u32 vga_render_control;
1313 u32 vga_hdp_control;
1314 u32 crtc_control[6];
1317 #include "radeon_object.h"