2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 #include "radeon_object.h"
33 /* TODO: Here are things that needs to be done :
34 * - surface allocator & initializer : (bit like scratch reg) should
35 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
37 * - WB : write back stuff (do it bit like scratch reg things)
38 * - Vblank : look at Jesse's rework and what we should do
39 * - r600/r700: gart & cp
40 * - cs : clean cs ioctl use bitmap & things like that.
41 * - power management stuff
42 * - Barrier in gart code
43 * - Unmappabled vram ?
44 * - TESTING, TESTING, TESTING
47 #include <asm/atomic.h>
48 #include <linux/wait.h>
49 #include <linux/list.h>
50 #include <linux/kref.h>
52 #include "radeon_family.h"
53 #include "radeon_mode.h"
54 #include "radeon_reg.h"
59 extern int radeon_no_wb;
60 extern int radeon_modeset;
61 extern int radeon_dynclks;
62 extern int radeon_r4xx_atom;
63 extern int radeon_agpmode;
64 extern int radeon_vram_limit;
65 extern int radeon_gart_size;
66 extern int radeon_benchmarking;
67 extern int radeon_testing;
68 extern int radeon_connector_table;
72 * Copy from radeon_drv.h so we don't have to include both and have conflicting
75 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
76 #define RADEON_IB_POOL_SIZE 16
77 #define RADEON_DEBUGFS_MAX_NUM_FILES 32
78 #define RADEONFB_CONN_LIMIT 4
79 #define RADEON_BIOS_NUM_SCRATCH 8
84 enum radeon_pll_errata {
85 CHIP_ERRATA_R300_CG = 0x00000001,
86 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
87 CHIP_ERRATA_PLL_DELAY = 0x00000004
97 bool radeon_get_bios(struct radeon_device *rdev);
103 struct radeon_dummy_page {
107 int radeon_dummy_page_init(struct radeon_device *rdev);
108 void radeon_dummy_page_fini(struct radeon_device *rdev);
114 struct radeon_clock {
115 struct radeon_pll p1pll;
116 struct radeon_pll p2pll;
117 struct radeon_pll spll;
118 struct radeon_pll mpll;
120 uint32_t default_mclk;
121 uint32_t default_sclk;
128 struct radeon_fence_driver {
129 uint32_t scratch_reg;
132 unsigned long count_timeout;
133 wait_queue_head_t queue;
135 struct list_head created;
136 struct list_head emited;
137 struct list_head signaled;
140 struct radeon_fence {
141 struct radeon_device *rdev;
143 struct list_head list;
144 /* protected by radeon_fence.lock */
146 unsigned long timeout;
151 int radeon_fence_driver_init(struct radeon_device *rdev);
152 void radeon_fence_driver_fini(struct radeon_device *rdev);
153 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
154 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
155 void radeon_fence_process(struct radeon_device *rdev);
156 bool radeon_fence_signaled(struct radeon_fence *fence);
157 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
158 int radeon_fence_wait_next(struct radeon_device *rdev);
159 int radeon_fence_wait_last(struct radeon_device *rdev);
160 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
161 void radeon_fence_unref(struct radeon_fence **fence);
166 struct radeon_surface_reg {
167 struct radeon_object *robj;
170 #define RADEON_GEM_MAX_SURFACES 8
175 struct radeon_object;
177 struct radeon_object_list {
178 struct list_head list;
179 struct radeon_object *robj;
183 uint32_t tiling_flags;
186 int radeon_object_init(struct radeon_device *rdev);
187 void radeon_object_fini(struct radeon_device *rdev);
188 int radeon_object_create(struct radeon_device *rdev,
189 struct drm_gem_object *gobj,
194 struct radeon_object **robj_ptr);
195 int radeon_object_kmap(struct radeon_object *robj, void **ptr);
196 void radeon_object_kunmap(struct radeon_object *robj);
197 void radeon_object_unref(struct radeon_object **robj);
198 int radeon_object_pin(struct radeon_object *robj, uint32_t domain,
200 void radeon_object_unpin(struct radeon_object *robj);
201 int radeon_object_wait(struct radeon_object *robj);
202 int radeon_object_busy_domain(struct radeon_object *robj, uint32_t *cur_placement);
203 int radeon_object_evict_vram(struct radeon_device *rdev);
204 int radeon_object_mmap(struct radeon_object *robj, uint64_t *offset);
205 void radeon_object_force_delete(struct radeon_device *rdev);
206 void radeon_object_list_add_object(struct radeon_object_list *lobj,
207 struct list_head *head);
208 int radeon_object_list_validate(struct list_head *head, void *fence);
209 void radeon_object_list_unvalidate(struct list_head *head);
210 void radeon_object_list_clean(struct list_head *head);
211 int radeon_object_fbdev_mmap(struct radeon_object *robj,
212 struct vm_area_struct *vma);
213 unsigned long radeon_object_size(struct radeon_object *robj);
214 void radeon_object_clear_surface_reg(struct radeon_object *robj);
215 int radeon_object_check_tiling(struct radeon_object *robj, bool has_moved,
217 void radeon_object_set_tiling_flags(struct radeon_object *robj,
218 uint32_t tiling_flags, uint32_t pitch);
219 void radeon_object_get_tiling_flags(struct radeon_object *robj, uint32_t *tiling_flags, uint32_t *pitch);
220 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
221 struct ttm_mem_reg *mem);
222 void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
227 struct list_head objects;
230 int radeon_gem_init(struct radeon_device *rdev);
231 void radeon_gem_fini(struct radeon_device *rdev);
232 int radeon_gem_object_create(struct radeon_device *rdev, int size,
233 int alignment, int initial_domain,
234 bool discardable, bool kernel,
236 struct drm_gem_object **obj);
237 int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
239 void radeon_gem_object_unpin(struct drm_gem_object *obj);
243 * GART structures, functions & helpers
247 struct radeon_gart_table_ram {
248 volatile uint32_t *ptr;
251 struct radeon_gart_table_vram {
252 struct radeon_object *robj;
253 volatile uint32_t *ptr;
256 union radeon_gart_table {
257 struct radeon_gart_table_ram ram;
258 struct radeon_gart_table_vram vram;
262 dma_addr_t table_addr;
263 unsigned num_gpu_pages;
264 unsigned num_cpu_pages;
266 union radeon_gart_table table;
268 dma_addr_t *pages_addr;
272 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
273 void radeon_gart_table_ram_free(struct radeon_device *rdev);
274 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
275 void radeon_gart_table_vram_free(struct radeon_device *rdev);
276 int radeon_gart_init(struct radeon_device *rdev);
277 void radeon_gart_fini(struct radeon_device *rdev);
278 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
280 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
281 int pages, struct page **pagelist);
285 * GPU MC structures, functions & helpers
288 resource_size_t aper_size;
289 resource_size_t aper_base;
290 resource_size_t agp_base;
291 /* for some chips with <= 32MB we need to lie
292 * about vram size near mc fb location */
307 int radeon_mc_setup(struct radeon_device *rdev);
311 * GPU scratch registers structures, functions & helpers
313 struct radeon_scratch {
319 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
320 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
329 /* FIXME: use a define max crtc rather than hardcode it */
330 bool crtc_vblank_int[2];
333 int radeon_irq_kms_init(struct radeon_device *rdev);
334 void radeon_irq_kms_fini(struct radeon_device *rdev);
341 struct list_head list;
344 struct radeon_fence *fence;
351 * mutex protects scheduled_ibs, ready, alloc_bm
353 struct radeon_ib_pool {
355 struct radeon_object *robj;
356 struct list_head scheduled_ibs;
357 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
359 DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
363 struct radeon_object *ring_obj;
364 volatile uint32_t *ring;
369 unsigned ring_free_dw;
379 struct radeon_object *shader_obj;
381 u32 vs_offset, ps_offset;
384 u32 vb_used, vb_total;
385 struct radeon_ib *vb_ib;
388 int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
389 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
390 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
391 int radeon_ib_pool_init(struct radeon_device *rdev);
392 void radeon_ib_pool_fini(struct radeon_device *rdev);
393 int radeon_ib_test(struct radeon_device *rdev);
394 /* Ring access between begin & end cannot sleep */
395 void radeon_ring_free_size(struct radeon_device *rdev);
396 int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
397 void radeon_ring_unlock_commit(struct radeon_device *rdev);
398 void radeon_ring_unlock_undo(struct radeon_device *rdev);
399 int radeon_ring_test(struct radeon_device *rdev);
400 int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
401 void radeon_ring_fini(struct radeon_device *rdev);
407 struct radeon_cs_reloc {
408 struct drm_gem_object *gobj;
409 struct radeon_object *robj;
410 struct radeon_object_list lobj;
415 struct radeon_cs_chunk {
421 void __user *user_ptr;
422 int last_copied_page;
426 struct radeon_cs_parser {
427 struct radeon_device *rdev;
428 struct drm_file *filp;
431 struct radeon_cs_chunk *chunks;
432 uint64_t *chunks_array;
437 struct radeon_cs_reloc *relocs;
438 struct radeon_cs_reloc **relocs_ptr;
439 struct list_head validated;
440 /* indices of various chunks */
442 int chunk_relocs_idx;
443 struct radeon_ib *ib;
449 extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
450 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
453 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
455 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
456 u32 pg_idx, pg_offset;
460 pg_idx = (idx * 4) / PAGE_SIZE;
461 pg_offset = (idx * 4) % PAGE_SIZE;
463 if (ibc->kpage_idx[0] == pg_idx)
464 return ibc->kpage[0][pg_offset/4];
465 if (ibc->kpage_idx[1] == pg_idx)
466 return ibc->kpage[1][pg_offset/4];
468 new_page = radeon_cs_update_pages(p, pg_idx);
470 p->parser_error = new_page;
474 idx_value = ibc->kpage[new_page][pg_offset/4];
478 struct radeon_cs_packet {
487 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
488 struct radeon_cs_packet *pkt,
489 unsigned idx, unsigned reg);
490 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
491 struct radeon_cs_packet *pkt);
497 int radeon_agp_init(struct radeon_device *rdev);
498 void radeon_agp_fini(struct radeon_device *rdev);
505 struct radeon_object *wb_obj;
506 volatile uint32_t *wb;
511 * struct radeon_pm - power management datas
512 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
513 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
514 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
515 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
516 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
517 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
518 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
519 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
520 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
521 * @sclk: GPU clock Mhz (core bandwith depends of this clock)
522 * @needed_bandwidth: current bandwidth needs
524 * It keeps track of various data needed to take powermanagement decision.
525 * Bandwith need is used to determine minimun clock of the GPU and memory.
526 * Equation between gpu/memory clock and available bandwidth is hw dependent
527 * (type of memory, bus size, efficiency, ...)
530 fixed20_12 max_bandwidth;
531 fixed20_12 igp_sideport_mclk;
532 fixed20_12 igp_system_mclk;
533 fixed20_12 igp_ht_link_clk;
534 fixed20_12 igp_ht_link_width;
535 fixed20_12 k8_bandwidth;
536 fixed20_12 sideport_bandwidth;
537 fixed20_12 ht_bandwidth;
538 fixed20_12 core_bandwidth;
540 fixed20_12 needed_bandwidth;
547 void radeon_benchmark(struct radeon_device *rdev);
553 void radeon_test_moves(struct radeon_device *rdev);
559 int radeon_debugfs_add_files(struct radeon_device *rdev,
560 struct drm_info_list *files,
562 int radeon_debugfs_fence_init(struct radeon_device *rdev);
563 int r100_debugfs_rbbm_init(struct radeon_device *rdev);
564 int r100_debugfs_cp_init(struct radeon_device *rdev);
568 * ASIC specific functions.
571 int (*init)(struct radeon_device *rdev);
572 void (*fini)(struct radeon_device *rdev);
573 int (*resume)(struct radeon_device *rdev);
574 int (*suspend)(struct radeon_device *rdev);
575 void (*errata)(struct radeon_device *rdev);
576 void (*vram_info)(struct radeon_device *rdev);
577 int (*gpu_reset)(struct radeon_device *rdev);
578 int (*mc_init)(struct radeon_device *rdev);
579 void (*mc_fini)(struct radeon_device *rdev);
580 int (*wb_init)(struct radeon_device *rdev);
581 void (*wb_fini)(struct radeon_device *rdev);
582 int (*gart_init)(struct radeon_device *rdev);
583 void (*gart_fini)(struct radeon_device *rdev);
584 int (*gart_enable)(struct radeon_device *rdev);
585 void (*gart_disable)(struct radeon_device *rdev);
586 void (*gart_tlb_flush)(struct radeon_device *rdev);
587 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
588 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
589 void (*cp_fini)(struct radeon_device *rdev);
590 void (*cp_disable)(struct radeon_device *rdev);
591 void (*cp_commit)(struct radeon_device *rdev);
592 void (*ring_start)(struct radeon_device *rdev);
593 int (*ring_test)(struct radeon_device *rdev);
594 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
595 int (*ib_test)(struct radeon_device *rdev);
596 int (*irq_set)(struct radeon_device *rdev);
597 int (*irq_process)(struct radeon_device *rdev);
598 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
599 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
600 int (*cs_parse)(struct radeon_cs_parser *p);
601 int (*copy_blit)(struct radeon_device *rdev,
605 struct radeon_fence *fence);
606 int (*copy_dma)(struct radeon_device *rdev,
610 struct radeon_fence *fence);
611 int (*copy)(struct radeon_device *rdev,
615 struct radeon_fence *fence);
616 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
617 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
618 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
619 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
620 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
621 uint32_t tiling_flags, uint32_t pitch,
622 uint32_t offset, uint32_t obj_size);
623 int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
624 void (*bandwidth_update)(struct radeon_device *rdev);
631 const unsigned *reg_safe_bm;
632 unsigned reg_safe_bm_size;
636 const unsigned *reg_safe_bm;
637 unsigned reg_safe_bm_size;
642 unsigned max_tile_pipes;
644 unsigned max_backends;
646 unsigned max_threads;
647 unsigned max_stack_entries;
648 unsigned max_hw_contexts;
649 unsigned max_gs_threads;
650 unsigned sx_max_export_size;
651 unsigned sx_max_export_pos_size;
652 unsigned sx_max_export_smx_size;
653 unsigned sq_num_cf_insts;
658 unsigned max_tile_pipes;
660 unsigned max_backends;
662 unsigned max_threads;
663 unsigned max_stack_entries;
664 unsigned max_hw_contexts;
665 unsigned max_gs_threads;
666 unsigned sx_max_export_size;
667 unsigned sx_max_export_pos_size;
668 unsigned sx_max_export_smx_size;
669 unsigned sq_num_cf_insts;
670 unsigned sx_num_of_sets;
671 unsigned sc_prim_fifo_size;
672 unsigned sc_hiz_tile_fifo_size;
673 unsigned sc_earlyz_tile_fifo_fize;
676 union radeon_asic_config {
677 struct r300_asic r300;
678 struct r100_asic r100;
679 struct r600_asic r600;
680 struct rv770_asic rv770;
687 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
688 struct drm_file *filp);
689 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
690 struct drm_file *filp);
691 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
692 struct drm_file *file_priv);
693 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
694 struct drm_file *file_priv);
695 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
696 struct drm_file *file_priv);
697 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
698 struct drm_file *file_priv);
699 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
700 struct drm_file *filp);
701 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
702 struct drm_file *filp);
703 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
704 struct drm_file *filp);
705 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
706 struct drm_file *filp);
707 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
708 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
709 struct drm_file *filp);
710 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
711 struct drm_file *filp);
715 * Core structure, functions and helpers.
717 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
718 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
720 struct radeon_device {
722 struct drm_device *ddev;
723 struct pci_dev *pdev;
725 union radeon_asic_config config;
726 enum radeon_family family;
729 enum radeon_pll_errata pll_errata;
736 uint16_t bios_header_start;
737 struct radeon_object *stollen_vga_memory;
738 struct fb_info *fbdev_info;
739 struct radeon_object *fbdev_robj;
740 struct radeon_framebuffer *fbdev_rfb;
742 resource_size_t rmmio_base;
743 resource_size_t rmmio_size;
745 radeon_rreg_t mc_rreg;
746 radeon_wreg_t mc_wreg;
747 radeon_rreg_t pll_rreg;
748 radeon_wreg_t pll_wreg;
749 uint32_t pcie_reg_mask;
750 radeon_rreg_t pciep_rreg;
751 radeon_wreg_t pciep_wreg;
752 struct radeon_clock clock;
754 struct radeon_gart gart;
755 struct radeon_mode_info mode_info;
756 struct radeon_scratch scratch;
757 struct radeon_mman mman;
758 struct radeon_fence_driver fence_drv;
760 struct radeon_ib_pool ib_pool;
761 struct radeon_irq irq;
762 struct radeon_asic *asic;
763 struct radeon_gem gem;
765 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
766 struct mutex cs_mutex;
768 struct radeon_dummy_page dummy_page;
775 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
776 const struct firmware *me_fw; /* all family ME firmware */
777 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
778 struct r600_blit r600_blit;
781 int radeon_device_init(struct radeon_device *rdev,
782 struct drm_device *ddev,
783 struct pci_dev *pdev,
785 void radeon_device_fini(struct radeon_device *rdev);
786 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
789 int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
790 void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
791 void r600_kms_blit_copy(struct radeon_device *rdev,
792 u64 src_gpu_addr, u64 dst_gpu_addr,
795 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
798 return readl(((void __iomem *)rdev->rmmio) + reg);
800 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
801 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
805 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
808 writel(v, ((void __iomem *)rdev->rmmio) + reg);
810 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
811 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
817 * Registers read & write functions.
819 #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
820 #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
821 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
822 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
823 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
824 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
825 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
826 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
827 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
828 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
829 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
830 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
831 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
832 #define WREG32_P(reg, val, mask) \
834 uint32_t tmp_ = RREG32(reg); \
836 tmp_ |= ((val) & ~(mask)); \
839 #define WREG32_PLL_P(reg, val, mask) \
841 uint32_t tmp_ = RREG32_PLL(reg); \
843 tmp_ |= ((val) & ~(mask)); \
844 WREG32_PLL(reg, tmp_); \
846 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
849 * Indirect registers accessor
851 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
855 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
856 r = RREG32(RADEON_PCIE_DATA);
860 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
862 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
863 WREG32(RADEON_PCIE_DATA, (v));
866 void r100_pll_errata_after_index(struct radeon_device *rdev);
872 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
873 (rdev->pdev->device == 0x5969))
874 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
875 (rdev->family == CHIP_RV200) || \
876 (rdev->family == CHIP_RS100) || \
877 (rdev->family == CHIP_RS200) || \
878 (rdev->family == CHIP_RV250) || \
879 (rdev->family == CHIP_RV280) || \
880 (rdev->family == CHIP_RS300))
881 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
882 (rdev->family == CHIP_RV350) || \
883 (rdev->family == CHIP_R350) || \
884 (rdev->family == CHIP_RV380) || \
885 (rdev->family == CHIP_R420) || \
886 (rdev->family == CHIP_R423) || \
887 (rdev->family == CHIP_RV410) || \
888 (rdev->family == CHIP_RS400) || \
889 (rdev->family == CHIP_RS480))
890 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
891 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
892 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
898 #define RBIOS8(i) (rdev->bios[i])
899 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
900 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
902 int radeon_combios_init(struct radeon_device *rdev);
903 void radeon_combios_fini(struct radeon_device *rdev);
904 int radeon_atombios_init(struct radeon_device *rdev);
905 void radeon_atombios_fini(struct radeon_device *rdev);
911 static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
914 if (rdev->cp.count_dw <= 0) {
915 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
918 rdev->cp.ring[rdev->cp.wptr++] = v;
919 rdev->cp.wptr &= rdev->cp.ptr_mask;
921 rdev->cp.ring_free_dw--;
928 #define radeon_init(rdev) (rdev)->asic->init((rdev))
929 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
930 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
931 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
932 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
933 #define radeon_errata(rdev) (rdev)->asic->errata((rdev))
934 #define radeon_vram_info(rdev) (rdev)->asic->vram_info((rdev))
935 #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
936 #define radeon_mc_init(rdev) (rdev)->asic->mc_init((rdev))
937 #define radeon_mc_fini(rdev) (rdev)->asic->mc_fini((rdev))
938 #define radeon_wb_init(rdev) (rdev)->asic->wb_init((rdev))
939 #define radeon_wb_fini(rdev) (rdev)->asic->wb_fini((rdev))
940 #define radeon_gpu_gart_init(rdev) (rdev)->asic->gart_init((rdev))
941 #define radeon_gpu_gart_fini(rdev) (rdev)->asic->gart_fini((rdev))
942 #define radeon_gart_enable(rdev) (rdev)->asic->gart_enable((rdev))
943 #define radeon_gart_disable(rdev) (rdev)->asic->gart_disable((rdev))
944 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
945 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
946 #define radeon_cp_init(rdev,rsize) (rdev)->asic->cp_init((rdev), (rsize))
947 #define radeon_cp_fini(rdev) (rdev)->asic->cp_fini((rdev))
948 #define radeon_cp_disable(rdev) (rdev)->asic->cp_disable((rdev))
949 #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
950 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
951 #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
952 #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
953 #define radeon_ib_test(rdev) (rdev)->asic->ib_test((rdev))
954 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
955 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
956 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
957 #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
958 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
959 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
960 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
961 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
962 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
963 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
964 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
965 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
966 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
967 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
969 /* Common functions */
970 extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
971 extern int radeon_modeset_init(struct radeon_device *rdev);
972 extern void radeon_modeset_fini(struct radeon_device *rdev);
973 extern bool radeon_card_posted(struct radeon_device *rdev);
974 extern int radeon_clocks_init(struct radeon_device *rdev);
975 extern void radeon_clocks_fini(struct radeon_device *rdev);
976 extern void radeon_scratch_init(struct radeon_device *rdev);
977 extern void radeon_surface_init(struct radeon_device *rdev);
978 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
980 /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
981 struct r100_mc_save {
989 extern void r100_cp_disable(struct radeon_device *rdev);
990 extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
991 extern void r100_cp_fini(struct radeon_device *rdev);
992 extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
993 extern int r100_pci_gart_init(struct radeon_device *rdev);
994 extern void r100_pci_gart_fini(struct radeon_device *rdev);
995 extern int r100_pci_gart_enable(struct radeon_device *rdev);
996 extern void r100_pci_gart_disable(struct radeon_device *rdev);
997 extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
998 extern int r100_debugfs_mc_info_init(struct radeon_device *rdev);
999 extern int r100_gui_wait_for_idle(struct radeon_device *rdev);
1000 extern void r100_ib_fini(struct radeon_device *rdev);
1001 extern int r100_ib_init(struct radeon_device *rdev);
1002 extern void r100_irq_disable(struct radeon_device *rdev);
1003 extern int r100_irq_set(struct radeon_device *rdev);
1004 extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
1005 extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
1006 extern void r100_vram_init_sizes(struct radeon_device *rdev);
1007 extern void r100_wb_disable(struct radeon_device *rdev);
1008 extern void r100_wb_fini(struct radeon_device *rdev);
1009 extern int r100_wb_init(struct radeon_device *rdev);
1011 /* r300,r350,rv350,rv370,rv380 */
1012 extern void r300_set_reg_safe(struct radeon_device *rdev);
1013 extern void r300_mc_program(struct radeon_device *rdev);
1014 extern void r300_vram_info(struct radeon_device *rdev);
1015 extern int rv370_pcie_gart_init(struct radeon_device *rdev);
1016 extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
1017 extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
1018 extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
1020 /* r420,r423,rv410 */
1021 extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
1022 extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1023 extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
1026 extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
1029 extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
1030 struct drm_display_mode *mode1,
1031 struct drm_display_mode *mode2);
1033 /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
1034 extern bool r600_card_posted(struct radeon_device *rdev);
1035 extern void r600_cp_stop(struct radeon_device *rdev);
1036 extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
1037 extern int r600_cp_resume(struct radeon_device *rdev);
1038 extern int r600_count_pipe_bits(uint32_t val);
1039 extern int r600_gart_clear_page(struct radeon_device *rdev, int i);
1040 extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
1041 extern int r600_pcie_gart_init(struct radeon_device *rdev);
1042 extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
1043 extern int r600_ib_test(struct radeon_device *rdev);
1044 extern int r600_ring_test(struct radeon_device *rdev);
1045 extern int r600_wb_init(struct radeon_device *rdev);
1046 extern void r600_wb_fini(struct radeon_device *rdev);
1047 extern void r600_scratch_init(struct radeon_device *rdev);
1048 extern int r600_blit_init(struct radeon_device *rdev);
1049 extern void r600_blit_fini(struct radeon_device *rdev);
1050 extern int r600_cp_init_microcode(struct radeon_device *rdev);
1051 extern int r600_gpu_reset(struct radeon_device *rdev);