2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 #include "radeon_object.h"
33 /* TODO: Here are things that needs to be done :
34 * - surface allocator & initializer : (bit like scratch reg) should
35 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
37 * - WB : write back stuff (do it bit like scratch reg things)
38 * - Vblank : look at Jesse's rework and what we should do
39 * - r600/r700: gart & cp
40 * - cs : clean cs ioctl use bitmap & things like that.
41 * - power management stuff
42 * - Barrier in gart code
43 * - Unmappabled vram ?
44 * - TESTING, TESTING, TESTING
47 #include <asm/atomic.h>
48 #include <linux/wait.h>
49 #include <linux/list.h>
50 #include <linux/kref.h>
52 #include "radeon_mode.h"
53 #include "radeon_reg.h"
59 extern int radeon_no_wb;
60 extern int radeon_modeset;
61 extern int radeon_dynclks;
62 extern int radeon_r4xx_atom;
63 extern int radeon_agpmode;
64 extern int radeon_vram_limit;
65 extern int radeon_gart_size;
66 extern int radeon_benchmarking;
67 extern int radeon_testing;
68 extern int radeon_connector_table;
72 * Copy from radeon_drv.h so we don't have to include both and have conflicting
75 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
76 #define RADEON_IB_POOL_SIZE 16
77 #define RADEON_DEBUGFS_MAX_NUM_FILES 32
78 #define RADEONFB_CONN_LIMIT 4
122 enum radeon_chip_flags {
123 RADEON_FAMILY_MASK = 0x0000ffffUL,
124 RADEON_FLAGS_MASK = 0xffff0000UL,
125 RADEON_IS_MOBILITY = 0x00010000UL,
126 RADEON_IS_IGP = 0x00020000UL,
127 RADEON_SINGLE_CRTC = 0x00040000UL,
128 RADEON_IS_AGP = 0x00080000UL,
129 RADEON_HAS_HIERZ = 0x00100000UL,
130 RADEON_IS_PCIE = 0x00200000UL,
131 RADEON_NEW_MEMMAP = 0x00400000UL,
132 RADEON_IS_PCI = 0x00800000UL,
133 RADEON_IS_IGPGART = 0x01000000UL,
138 * Errata workarounds.
140 enum radeon_pll_errata {
141 CHIP_ERRATA_R300_CG = 0x00000001,
142 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
143 CHIP_ERRATA_PLL_DELAY = 0x00000004
147 struct radeon_device;
153 bool radeon_get_bios(struct radeon_device *rdev);
159 struct radeon_clock {
160 struct radeon_pll p1pll;
161 struct radeon_pll p2pll;
162 struct radeon_pll spll;
163 struct radeon_pll mpll;
165 uint32_t default_mclk;
166 uint32_t default_sclk;
172 struct radeon_fence_driver {
173 uint32_t scratch_reg;
176 unsigned long count_timeout;
177 wait_queue_head_t queue;
179 struct list_head created;
180 struct list_head emited;
181 struct list_head signaled;
184 struct radeon_fence {
185 struct radeon_device *rdev;
187 struct list_head list;
188 /* protected by radeon_fence.lock */
190 unsigned long timeout;
195 int radeon_fence_driver_init(struct radeon_device *rdev);
196 void radeon_fence_driver_fini(struct radeon_device *rdev);
197 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
198 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
199 void radeon_fence_process(struct radeon_device *rdev);
200 bool radeon_fence_signaled(struct radeon_fence *fence);
201 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
202 int radeon_fence_wait_next(struct radeon_device *rdev);
203 int radeon_fence_wait_last(struct radeon_device *rdev);
204 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
205 void radeon_fence_unref(struct radeon_fence **fence);
210 struct radeon_surface_reg {
211 struct radeon_object *robj;
214 #define RADEON_GEM_MAX_SURFACES 8
219 struct radeon_object;
221 struct radeon_object_list {
222 struct list_head list;
223 struct radeon_object *robj;
227 uint32_t tiling_flags;
230 int radeon_object_init(struct radeon_device *rdev);
231 void radeon_object_fini(struct radeon_device *rdev);
232 int radeon_object_create(struct radeon_device *rdev,
233 struct drm_gem_object *gobj,
238 struct radeon_object **robj_ptr);
239 int radeon_object_kmap(struct radeon_object *robj, void **ptr);
240 void radeon_object_kunmap(struct radeon_object *robj);
241 void radeon_object_unref(struct radeon_object **robj);
242 int radeon_object_pin(struct radeon_object *robj, uint32_t domain,
244 void radeon_object_unpin(struct radeon_object *robj);
245 int radeon_object_wait(struct radeon_object *robj);
246 int radeon_object_busy_domain(struct radeon_object *robj, uint32_t *cur_placement);
247 int radeon_object_evict_vram(struct radeon_device *rdev);
248 int radeon_object_mmap(struct radeon_object *robj, uint64_t *offset);
249 void radeon_object_force_delete(struct radeon_device *rdev);
250 void radeon_object_list_add_object(struct radeon_object_list *lobj,
251 struct list_head *head);
252 int radeon_object_list_validate(struct list_head *head, void *fence);
253 void radeon_object_list_unvalidate(struct list_head *head);
254 void radeon_object_list_clean(struct list_head *head);
255 int radeon_object_fbdev_mmap(struct radeon_object *robj,
256 struct vm_area_struct *vma);
257 unsigned long radeon_object_size(struct radeon_object *robj);
258 void radeon_object_clear_surface_reg(struct radeon_object *robj);
259 int radeon_object_check_tiling(struct radeon_object *robj, bool has_moved,
261 void radeon_object_set_tiling_flags(struct radeon_object *robj,
262 uint32_t tiling_flags, uint32_t pitch);
263 void radeon_object_get_tiling_flags(struct radeon_object *robj, uint32_t *tiling_flags, uint32_t *pitch);
264 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
265 struct ttm_mem_reg *mem);
266 void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
271 struct list_head objects;
274 int radeon_gem_init(struct radeon_device *rdev);
275 void radeon_gem_fini(struct radeon_device *rdev);
276 int radeon_gem_object_create(struct radeon_device *rdev, int size,
277 int alignment, int initial_domain,
278 bool discardable, bool kernel,
280 struct drm_gem_object **obj);
281 int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
283 void radeon_gem_object_unpin(struct drm_gem_object *obj);
287 * GART structures, functions & helpers
291 struct radeon_gart_table_ram {
292 volatile uint32_t *ptr;
295 struct radeon_gart_table_vram {
296 struct radeon_object *robj;
297 volatile uint32_t *ptr;
300 union radeon_gart_table {
301 struct radeon_gart_table_ram ram;
302 struct radeon_gart_table_vram vram;
306 dma_addr_t table_addr;
307 unsigned num_gpu_pages;
308 unsigned num_cpu_pages;
310 union radeon_gart_table table;
312 dma_addr_t *pages_addr;
316 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
317 void radeon_gart_table_ram_free(struct radeon_device *rdev);
318 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
319 void radeon_gart_table_vram_free(struct radeon_device *rdev);
320 int radeon_gart_init(struct radeon_device *rdev);
321 void radeon_gart_fini(struct radeon_device *rdev);
322 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
324 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
325 int pages, struct page **pagelist);
329 * GPU MC structures, functions & helpers
332 resource_size_t aper_size;
333 resource_size_t aper_base;
334 resource_size_t agp_base;
335 unsigned gtt_location;
337 unsigned vram_location;
338 /* for some chips with <= 32MB we need to lie
339 * about vram size near mc fb location */
340 unsigned mc_vram_size;
342 unsigned real_vram_size;
347 int radeon_mc_setup(struct radeon_device *rdev);
351 * GPU scratch registers structures, functions & helpers
353 struct radeon_scratch {
359 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
360 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
369 /* FIXME: use a define max crtc rather than hardcode it */
370 bool crtc_vblank_int[2];
373 int radeon_irq_kms_init(struct radeon_device *rdev);
374 void radeon_irq_kms_fini(struct radeon_device *rdev);
381 struct list_head list;
384 struct radeon_fence *fence;
385 volatile uint32_t *ptr;
389 struct radeon_ib_pool {
391 struct radeon_object *robj;
392 struct list_head scheduled_ibs;
393 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
395 DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
399 struct radeon_object *ring_obj;
400 volatile uint32_t *ring;
405 unsigned ring_free_dw;
414 int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
415 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
416 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
417 int radeon_ib_pool_init(struct radeon_device *rdev);
418 void radeon_ib_pool_fini(struct radeon_device *rdev);
419 int radeon_ib_test(struct radeon_device *rdev);
420 /* Ring access between begin & end cannot sleep */
421 void radeon_ring_free_size(struct radeon_device *rdev);
422 int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
423 void radeon_ring_unlock_commit(struct radeon_device *rdev);
424 void radeon_ring_unlock_undo(struct radeon_device *rdev);
425 int radeon_ring_test(struct radeon_device *rdev);
426 int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
427 void radeon_ring_fini(struct radeon_device *rdev);
433 struct radeon_cs_reloc {
434 struct drm_gem_object *gobj;
435 struct radeon_object *robj;
436 struct radeon_object_list lobj;
441 struct radeon_cs_chunk {
447 struct radeon_cs_parser {
448 struct radeon_device *rdev;
449 struct drm_file *filp;
452 struct radeon_cs_chunk *chunks;
453 uint64_t *chunks_array;
458 struct radeon_cs_reloc *relocs;
459 struct radeon_cs_reloc **relocs_ptr;
460 struct list_head validated;
461 /* indices of various chunks */
463 int chunk_relocs_idx;
464 struct radeon_ib *ib;
468 struct radeon_cs_packet {
477 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
478 struct radeon_cs_packet *pkt,
479 unsigned idx, unsigned reg);
480 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
481 struct radeon_cs_packet *pkt);
487 int radeon_agp_init(struct radeon_device *rdev);
488 void radeon_agp_fini(struct radeon_device *rdev);
495 struct radeon_object *wb_obj;
496 volatile uint32_t *wb;
501 * struct radeon_pm - power management datas
502 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
503 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
504 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
505 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
506 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
507 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
508 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
509 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
510 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
511 * @sclk: GPU clock Mhz (core bandwith depends of this clock)
512 * @needed_bandwidth: current bandwidth needs
514 * It keeps track of various data needed to take powermanagement decision.
515 * Bandwith need is used to determine minimun clock of the GPU and memory.
516 * Equation between gpu/memory clock and available bandwidth is hw dependent
517 * (type of memory, bus size, efficiency, ...)
520 fixed20_12 max_bandwidth;
521 fixed20_12 igp_sideport_mclk;
522 fixed20_12 igp_system_mclk;
523 fixed20_12 igp_ht_link_clk;
524 fixed20_12 igp_ht_link_width;
525 fixed20_12 k8_bandwidth;
526 fixed20_12 sideport_bandwidth;
527 fixed20_12 ht_bandwidth;
528 fixed20_12 core_bandwidth;
530 fixed20_12 needed_bandwidth;
537 void radeon_benchmark(struct radeon_device *rdev);
543 void radeon_test_moves(struct radeon_device *rdev);
549 int radeon_debugfs_add_files(struct radeon_device *rdev,
550 struct drm_info_list *files,
552 int radeon_debugfs_fence_init(struct radeon_device *rdev);
553 int r100_debugfs_rbbm_init(struct radeon_device *rdev);
554 int r100_debugfs_cp_init(struct radeon_device *rdev);
558 * ASIC specific functions.
561 int (*init)(struct radeon_device *rdev);
562 void (*errata)(struct radeon_device *rdev);
563 void (*vram_info)(struct radeon_device *rdev);
564 int (*gpu_reset)(struct radeon_device *rdev);
565 int (*mc_init)(struct radeon_device *rdev);
566 void (*mc_fini)(struct radeon_device *rdev);
567 int (*wb_init)(struct radeon_device *rdev);
568 void (*wb_fini)(struct radeon_device *rdev);
569 int (*gart_enable)(struct radeon_device *rdev);
570 void (*gart_disable)(struct radeon_device *rdev);
571 void (*gart_tlb_flush)(struct radeon_device *rdev);
572 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
573 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
574 void (*cp_fini)(struct radeon_device *rdev);
575 void (*cp_disable)(struct radeon_device *rdev);
576 void (*ring_start)(struct radeon_device *rdev);
577 int (*irq_set)(struct radeon_device *rdev);
578 int (*irq_process)(struct radeon_device *rdev);
579 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
580 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
581 int (*cs_parse)(struct radeon_cs_parser *p);
582 int (*copy_blit)(struct radeon_device *rdev,
586 struct radeon_fence *fence);
587 int (*copy_dma)(struct radeon_device *rdev,
591 struct radeon_fence *fence);
592 int (*copy)(struct radeon_device *rdev,
596 struct radeon_fence *fence);
597 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
598 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
599 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
600 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
601 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
602 uint32_t tiling_flags, uint32_t pitch,
603 uint32_t offset, uint32_t obj_size);
604 int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
605 void (*bandwidth_update)(struct radeon_device *rdev);
609 const unsigned *reg_safe_bm;
610 unsigned reg_safe_bm_size;
613 union radeon_asic_config {
614 struct r300_asic r300;
615 struct r100_asic r100;
622 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
623 struct drm_file *filp);
624 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
625 struct drm_file *filp);
626 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
627 struct drm_file *file_priv);
628 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
629 struct drm_file *file_priv);
630 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
631 struct drm_file *file_priv);
632 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
633 struct drm_file *file_priv);
634 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
635 struct drm_file *filp);
636 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
637 struct drm_file *filp);
638 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
639 struct drm_file *filp);
640 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
641 struct drm_file *filp);
642 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
643 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
644 struct drm_file *filp);
645 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
646 struct drm_file *filp);
650 * Core structure, functions and helpers.
652 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
653 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
655 struct radeon_device {
656 struct drm_device *ddev;
657 struct pci_dev *pdev;
659 union radeon_asic_config config;
660 enum radeon_family family;
663 enum radeon_pll_errata pll_errata;
670 uint16_t bios_header_start;
671 struct radeon_object *stollen_vga_memory;
672 struct fb_info *fbdev_info;
673 struct radeon_object *fbdev_robj;
674 struct radeon_framebuffer *fbdev_rfb;
676 resource_size_t rmmio_base;
677 resource_size_t rmmio_size;
679 radeon_rreg_t mc_rreg;
680 radeon_wreg_t mc_wreg;
681 radeon_rreg_t pll_rreg;
682 radeon_wreg_t pll_wreg;
683 uint32_t pcie_reg_mask;
684 radeon_rreg_t pciep_rreg;
685 radeon_wreg_t pciep_wreg;
686 struct radeon_clock clock;
688 struct radeon_gart gart;
689 struct radeon_mode_info mode_info;
690 struct radeon_scratch scratch;
691 struct radeon_mman mman;
692 struct radeon_fence_driver fence_drv;
694 struct radeon_ib_pool ib_pool;
695 struct radeon_irq irq;
696 struct radeon_asic *asic;
697 struct radeon_gem gem;
699 struct mutex cs_mutex;
705 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
706 const struct firmware *fw; /* firmware */
709 int radeon_device_init(struct radeon_device *rdev,
710 struct drm_device *ddev,
711 struct pci_dev *pdev,
713 void radeon_device_fini(struct radeon_device *rdev);
714 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
716 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
719 return readl(((void __iomem *)rdev->rmmio) + reg);
721 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
722 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
726 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
729 writel(v, ((void __iomem *)rdev->rmmio) + reg);
731 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
732 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
738 * Registers read & write functions.
740 #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
741 #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
742 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
743 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
744 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
745 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
746 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
747 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
748 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
749 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
750 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
751 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
752 #define WREG32_P(reg, val, mask) \
754 uint32_t tmp_ = RREG32(reg); \
756 tmp_ |= ((val) & ~(mask)); \
759 #define WREG32_PLL_P(reg, val, mask) \
761 uint32_t tmp_ = RREG32_PLL(reg); \
763 tmp_ |= ((val) & ~(mask)); \
764 WREG32_PLL(reg, tmp_); \
768 * Indirect registers accessor
770 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
774 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
775 r = RREG32(RADEON_PCIE_DATA);
779 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
781 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
782 WREG32(RADEON_PCIE_DATA, (v));
785 void r100_pll_errata_after_index(struct radeon_device *rdev);
791 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
792 (rdev->pdev->device == 0x5969))
793 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
794 (rdev->family == CHIP_RV200) || \
795 (rdev->family == CHIP_RS100) || \
796 (rdev->family == CHIP_RS200) || \
797 (rdev->family == CHIP_RV250) || \
798 (rdev->family == CHIP_RV280) || \
799 (rdev->family == CHIP_RS300))
800 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
801 (rdev->family == CHIP_RV350) || \
802 (rdev->family == CHIP_R350) || \
803 (rdev->family == CHIP_RV380) || \
804 (rdev->family == CHIP_R420) || \
805 (rdev->family == CHIP_R423) || \
806 (rdev->family == CHIP_RV410) || \
807 (rdev->family == CHIP_RS400) || \
808 (rdev->family == CHIP_RS480))
809 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
810 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
811 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
817 #define RBIOS8(i) (rdev->bios[i])
818 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
819 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
821 int radeon_combios_init(struct radeon_device *rdev);
822 void radeon_combios_fini(struct radeon_device *rdev);
823 int radeon_atombios_init(struct radeon_device *rdev);
824 void radeon_atombios_fini(struct radeon_device *rdev);
830 #define CP_PACKET0 0x00000000
831 #define PACKET0_BASE_INDEX_SHIFT 0
832 #define PACKET0_BASE_INDEX_MASK (0x1ffff << 0)
833 #define PACKET0_COUNT_SHIFT 16
834 #define PACKET0_COUNT_MASK (0x3fff << 16)
835 #define CP_PACKET1 0x40000000
836 #define CP_PACKET2 0x80000000
837 #define PACKET2_PAD_SHIFT 0
838 #define PACKET2_PAD_MASK (0x3fffffff << 0)
839 #define CP_PACKET3 0xC0000000
840 #define PACKET3_IT_OPCODE_SHIFT 8
841 #define PACKET3_IT_OPCODE_MASK (0xff << 8)
842 #define PACKET3_COUNT_SHIFT 16
843 #define PACKET3_COUNT_MASK (0x3fff << 16)
844 /* PACKET3 op code */
845 #define PACKET3_NOP 0x10
846 #define PACKET3_3D_DRAW_VBUF 0x28
847 #define PACKET3_3D_DRAW_IMMD 0x29
848 #define PACKET3_3D_DRAW_INDX 0x2A
849 #define PACKET3_3D_LOAD_VBPNTR 0x2F
850 #define PACKET3_INDX_BUFFER 0x33
851 #define PACKET3_3D_DRAW_VBUF_2 0x34
852 #define PACKET3_3D_DRAW_IMMD_2 0x35
853 #define PACKET3_3D_DRAW_INDX_2 0x36
854 #define PACKET3_BITBLT_MULTI 0x9B
856 #define PACKET0(reg, n) (CP_PACKET0 | \
857 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
858 REG_SET(PACKET0_COUNT, (n)))
859 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
860 #define PACKET3(op, n) (CP_PACKET3 | \
861 REG_SET(PACKET3_IT_OPCODE, (op)) | \
862 REG_SET(PACKET3_COUNT, (n)))
864 #define PACKET_TYPE0 0
865 #define PACKET_TYPE1 1
866 #define PACKET_TYPE2 2
867 #define PACKET_TYPE3 3
869 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
870 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
871 #define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2)
872 #define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1)
873 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
875 static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
878 if (rdev->cp.count_dw <= 0) {
879 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
882 rdev->cp.ring[rdev->cp.wptr++] = v;
883 rdev->cp.wptr &= rdev->cp.ptr_mask;
885 rdev->cp.ring_free_dw--;
892 #define radeon_init(rdev) (rdev)->asic->init((rdev))
893 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
894 #define radeon_errata(rdev) (rdev)->asic->errata((rdev))
895 #define radeon_vram_info(rdev) (rdev)->asic->vram_info((rdev))
896 #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
897 #define radeon_mc_init(rdev) (rdev)->asic->mc_init((rdev))
898 #define radeon_mc_fini(rdev) (rdev)->asic->mc_fini((rdev))
899 #define radeon_wb_init(rdev) (rdev)->asic->wb_init((rdev))
900 #define radeon_wb_fini(rdev) (rdev)->asic->wb_fini((rdev))
901 #define radeon_gart_enable(rdev) (rdev)->asic->gart_enable((rdev))
902 #define radeon_gart_disable(rdev) (rdev)->asic->gart_disable((rdev))
903 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
904 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
905 #define radeon_cp_init(rdev,rsize) (rdev)->asic->cp_init((rdev), (rsize))
906 #define radeon_cp_fini(rdev) (rdev)->asic->cp_fini((rdev))
907 #define radeon_cp_disable(rdev) (rdev)->asic->cp_disable((rdev))
908 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
909 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
910 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
911 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
912 #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
913 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
914 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
915 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
916 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
917 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
918 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
919 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
920 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
921 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
922 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))