2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
63 #include <asm/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
73 #include "radeon_family.h"
74 #include "radeon_mode.h"
75 #include "radeon_reg.h"
80 extern int radeon_no_wb;
81 extern int radeon_modeset;
82 extern int radeon_dynclks;
83 extern int radeon_r4xx_atom;
84 extern int radeon_agpmode;
85 extern int radeon_vram_limit;
86 extern int radeon_gart_size;
87 extern int radeon_benchmarking;
88 extern int radeon_testing;
89 extern int radeon_connector_table;
93 * Copy from radeon_drv.h so we don't have to include both and have conflicting
96 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
97 #define RADEON_IB_POOL_SIZE 16
98 #define RADEON_DEBUGFS_MAX_NUM_FILES 32
99 #define RADEONFB_CONN_LIMIT 4
100 #define RADEON_BIOS_NUM_SCRATCH 8
103 * Errata workarounds.
105 enum radeon_pll_errata {
106 CHIP_ERRATA_R300_CG = 0x00000001,
107 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
108 CHIP_ERRATA_PLL_DELAY = 0x00000004
112 struct radeon_device;
118 bool radeon_get_bios(struct radeon_device *rdev);
124 struct radeon_dummy_page {
128 int radeon_dummy_page_init(struct radeon_device *rdev);
129 void radeon_dummy_page_fini(struct radeon_device *rdev);
135 struct radeon_clock {
136 struct radeon_pll p1pll;
137 struct radeon_pll p2pll;
138 struct radeon_pll spll;
139 struct radeon_pll mpll;
141 uint32_t default_mclk;
142 uint32_t default_sclk;
148 int radeon_pm_init(struct radeon_device *rdev);
153 struct radeon_fence_driver {
154 uint32_t scratch_reg;
157 unsigned long count_timeout;
158 wait_queue_head_t queue;
160 struct list_head created;
161 struct list_head emited;
162 struct list_head signaled;
165 struct radeon_fence {
166 struct radeon_device *rdev;
168 struct list_head list;
169 /* protected by radeon_fence.lock */
171 unsigned long timeout;
176 int radeon_fence_driver_init(struct radeon_device *rdev);
177 void radeon_fence_driver_fini(struct radeon_device *rdev);
178 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
179 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
180 void radeon_fence_process(struct radeon_device *rdev);
181 bool radeon_fence_signaled(struct radeon_fence *fence);
182 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
183 int radeon_fence_wait_next(struct radeon_device *rdev);
184 int radeon_fence_wait_last(struct radeon_device *rdev);
185 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
186 void radeon_fence_unref(struct radeon_fence **fence);
191 struct radeon_surface_reg {
192 struct radeon_bo *bo;
195 #define RADEON_GEM_MAX_SURFACES 8
201 struct ttm_bo_global_ref bo_global_ref;
202 struct ttm_global_reference mem_global_ref;
203 bool mem_global_referenced;
204 struct ttm_bo_device bdev;
208 /* Protected by gem.mutex */
209 struct list_head list;
210 /* Protected by tbo.reserved */
212 struct ttm_placement placement;
213 struct ttm_buffer_object tbo;
214 struct ttm_bo_kmap_obj kmap;
220 /* Constant after initialization */
221 struct radeon_device *rdev;
222 struct drm_gem_object *gobj;
225 struct radeon_bo_list {
226 struct list_head list;
227 struct radeon_bo *bo;
239 struct list_head objects;
242 int radeon_gem_init(struct radeon_device *rdev);
243 void radeon_gem_fini(struct radeon_device *rdev);
244 int radeon_gem_object_create(struct radeon_device *rdev, int size,
245 int alignment, int initial_domain,
246 bool discardable, bool kernel,
247 struct drm_gem_object **obj);
248 int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
250 void radeon_gem_object_unpin(struct drm_gem_object *obj);
254 * GART structures, functions & helpers
258 struct radeon_gart_table_ram {
259 volatile uint32_t *ptr;
262 struct radeon_gart_table_vram {
263 struct radeon_bo *robj;
264 volatile uint32_t *ptr;
267 union radeon_gart_table {
268 struct radeon_gart_table_ram ram;
269 struct radeon_gart_table_vram vram;
272 #define RADEON_GPU_PAGE_SIZE 4096
275 dma_addr_t table_addr;
276 unsigned num_gpu_pages;
277 unsigned num_cpu_pages;
279 union radeon_gart_table table;
281 dma_addr_t *pages_addr;
285 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
286 void radeon_gart_table_ram_free(struct radeon_device *rdev);
287 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
288 void radeon_gart_table_vram_free(struct radeon_device *rdev);
289 int radeon_gart_init(struct radeon_device *rdev);
290 void radeon_gart_fini(struct radeon_device *rdev);
291 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
293 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
294 int pages, struct page **pagelist);
298 * GPU MC structures, functions & helpers
301 resource_size_t aper_size;
302 resource_size_t aper_base;
303 resource_size_t agp_base;
304 /* for some chips with <= 32MB we need to lie
305 * about vram size near mc fb location */
320 int radeon_mc_setup(struct radeon_device *rdev);
324 * GPU scratch registers structures, functions & helpers
326 struct radeon_scratch {
332 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
333 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
342 /* FIXME: use a define max crtc rather than hardcode it */
343 bool crtc_vblank_int[2];
344 /* FIXME: use defines for max hpd/dacs */
350 int radeon_irq_kms_init(struct radeon_device *rdev);
351 void radeon_irq_kms_fini(struct radeon_device *rdev);
352 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
353 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
359 struct list_head list;
362 struct radeon_fence *fence;
369 * mutex protects scheduled_ibs, ready, alloc_bm
371 struct radeon_ib_pool {
373 struct radeon_bo *robj;
374 struct list_head scheduled_ibs;
375 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
377 DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
381 struct radeon_bo *ring_obj;
382 volatile uint32_t *ring;
387 unsigned ring_free_dw;
400 struct radeon_bo *ring_obj;
401 volatile uint32_t *ring;
414 struct radeon_bo *shader_obj;
416 u32 vs_offset, ps_offset;
419 u32 vb_used, vb_total;
420 struct radeon_ib *vb_ib;
423 int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
424 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
425 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
426 int radeon_ib_pool_init(struct radeon_device *rdev);
427 void radeon_ib_pool_fini(struct radeon_device *rdev);
428 int radeon_ib_test(struct radeon_device *rdev);
429 /* Ring access between begin & end cannot sleep */
430 void radeon_ring_free_size(struct radeon_device *rdev);
431 int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
432 void radeon_ring_unlock_commit(struct radeon_device *rdev);
433 void radeon_ring_unlock_undo(struct radeon_device *rdev);
434 int radeon_ring_test(struct radeon_device *rdev);
435 int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
436 void radeon_ring_fini(struct radeon_device *rdev);
442 struct radeon_cs_reloc {
443 struct drm_gem_object *gobj;
444 struct radeon_bo *robj;
445 struct radeon_bo_list lobj;
450 struct radeon_cs_chunk {
456 void __user *user_ptr;
457 int last_copied_page;
461 struct radeon_cs_parser {
462 struct radeon_device *rdev;
463 struct drm_file *filp;
466 struct radeon_cs_chunk *chunks;
467 uint64_t *chunks_array;
472 struct radeon_cs_reloc *relocs;
473 struct radeon_cs_reloc **relocs_ptr;
474 struct list_head validated;
475 /* indices of various chunks */
477 int chunk_relocs_idx;
478 struct radeon_ib *ib;
484 extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
485 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
488 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
490 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
491 u32 pg_idx, pg_offset;
495 pg_idx = (idx * 4) / PAGE_SIZE;
496 pg_offset = (idx * 4) % PAGE_SIZE;
498 if (ibc->kpage_idx[0] == pg_idx)
499 return ibc->kpage[0][pg_offset/4];
500 if (ibc->kpage_idx[1] == pg_idx)
501 return ibc->kpage[1][pg_offset/4];
503 new_page = radeon_cs_update_pages(p, pg_idx);
505 p->parser_error = new_page;
509 idx_value = ibc->kpage[new_page][pg_offset/4];
513 struct radeon_cs_packet {
522 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
523 struct radeon_cs_packet *pkt,
524 unsigned idx, unsigned reg);
525 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
526 struct radeon_cs_packet *pkt);
532 int radeon_agp_init(struct radeon_device *rdev);
533 void radeon_agp_resume(struct radeon_device *rdev);
534 void radeon_agp_fini(struct radeon_device *rdev);
541 struct radeon_bo *wb_obj;
542 volatile uint32_t *wb;
547 * struct radeon_pm - power management datas
548 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
549 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
550 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
551 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
552 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
553 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
554 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
555 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
556 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
557 * @sclk: GPU clock Mhz (core bandwith depends of this clock)
558 * @needed_bandwidth: current bandwidth needs
560 * It keeps track of various data needed to take powermanagement decision.
561 * Bandwith need is used to determine minimun clock of the GPU and memory.
562 * Equation between gpu/memory clock and available bandwidth is hw dependent
563 * (type of memory, bus size, efficiency, ...)
566 fixed20_12 max_bandwidth;
567 fixed20_12 igp_sideport_mclk;
568 fixed20_12 igp_system_mclk;
569 fixed20_12 igp_ht_link_clk;
570 fixed20_12 igp_ht_link_width;
571 fixed20_12 k8_bandwidth;
572 fixed20_12 sideport_bandwidth;
573 fixed20_12 ht_bandwidth;
574 fixed20_12 core_bandwidth;
576 fixed20_12 needed_bandwidth;
583 void radeon_benchmark(struct radeon_device *rdev);
589 void radeon_test_moves(struct radeon_device *rdev);
595 int radeon_debugfs_add_files(struct radeon_device *rdev,
596 struct drm_info_list *files,
598 int radeon_debugfs_fence_init(struct radeon_device *rdev);
599 int r100_debugfs_rbbm_init(struct radeon_device *rdev);
600 int r100_debugfs_cp_init(struct radeon_device *rdev);
604 * ASIC specific functions.
607 int (*init)(struct radeon_device *rdev);
608 void (*fini)(struct radeon_device *rdev);
609 int (*resume)(struct radeon_device *rdev);
610 int (*suspend)(struct radeon_device *rdev);
611 void (*vga_set_state)(struct radeon_device *rdev, bool state);
612 int (*gpu_reset)(struct radeon_device *rdev);
613 void (*gart_tlb_flush)(struct radeon_device *rdev);
614 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
615 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
616 void (*cp_fini)(struct radeon_device *rdev);
617 void (*cp_disable)(struct radeon_device *rdev);
618 void (*cp_commit)(struct radeon_device *rdev);
619 void (*ring_start)(struct radeon_device *rdev);
620 int (*ring_test)(struct radeon_device *rdev);
621 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
622 int (*irq_set)(struct radeon_device *rdev);
623 int (*irq_process)(struct radeon_device *rdev);
624 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
625 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
626 int (*cs_parse)(struct radeon_cs_parser *p);
627 int (*copy_blit)(struct radeon_device *rdev,
631 struct radeon_fence *fence);
632 int (*copy_dma)(struct radeon_device *rdev,
636 struct radeon_fence *fence);
637 int (*copy)(struct radeon_device *rdev,
641 struct radeon_fence *fence);
642 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
643 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
644 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
645 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
646 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
647 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
648 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
649 uint32_t tiling_flags, uint32_t pitch,
650 uint32_t offset, uint32_t obj_size);
651 int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
652 void (*bandwidth_update)(struct radeon_device *rdev);
653 void (*hdp_flush)(struct radeon_device *rdev);
654 void (*hpd_init)(struct radeon_device *rdev);
655 void (*hpd_fini)(struct radeon_device *rdev);
656 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
657 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
664 const unsigned *reg_safe_bm;
665 unsigned reg_safe_bm_size;
669 const unsigned *reg_safe_bm;
670 unsigned reg_safe_bm_size;
675 unsigned max_tile_pipes;
677 unsigned max_backends;
679 unsigned max_threads;
680 unsigned max_stack_entries;
681 unsigned max_hw_contexts;
682 unsigned max_gs_threads;
683 unsigned sx_max_export_size;
684 unsigned sx_max_export_pos_size;
685 unsigned sx_max_export_smx_size;
686 unsigned sq_num_cf_insts;
691 unsigned max_tile_pipes;
693 unsigned max_backends;
695 unsigned max_threads;
696 unsigned max_stack_entries;
697 unsigned max_hw_contexts;
698 unsigned max_gs_threads;
699 unsigned sx_max_export_size;
700 unsigned sx_max_export_pos_size;
701 unsigned sx_max_export_smx_size;
702 unsigned sq_num_cf_insts;
703 unsigned sx_num_of_sets;
704 unsigned sc_prim_fifo_size;
705 unsigned sc_hiz_tile_fifo_size;
706 unsigned sc_earlyz_tile_fifo_fize;
709 union radeon_asic_config {
710 struct r300_asic r300;
711 struct r100_asic r100;
712 struct r600_asic r600;
713 struct rv770_asic rv770;
720 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
721 struct drm_file *filp);
722 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
723 struct drm_file *filp);
724 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
725 struct drm_file *file_priv);
726 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
727 struct drm_file *file_priv);
728 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
729 struct drm_file *file_priv);
730 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
731 struct drm_file *file_priv);
732 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
733 struct drm_file *filp);
734 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
735 struct drm_file *filp);
736 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
737 struct drm_file *filp);
738 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
739 struct drm_file *filp);
740 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
741 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
742 struct drm_file *filp);
743 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
744 struct drm_file *filp);
748 * Core structure, functions and helpers.
750 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
751 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
753 struct radeon_device {
755 struct drm_device *ddev;
756 struct pci_dev *pdev;
758 union radeon_asic_config config;
759 enum radeon_family family;
762 enum radeon_pll_errata pll_errata;
769 uint16_t bios_header_start;
770 struct radeon_bo *stollen_vga_memory;
771 struct fb_info *fbdev_info;
772 struct radeon_bo *fbdev_rbo;
773 struct radeon_framebuffer *fbdev_rfb;
775 resource_size_t rmmio_base;
776 resource_size_t rmmio_size;
778 radeon_rreg_t mc_rreg;
779 radeon_wreg_t mc_wreg;
780 radeon_rreg_t pll_rreg;
781 radeon_wreg_t pll_wreg;
782 uint32_t pcie_reg_mask;
783 radeon_rreg_t pciep_rreg;
784 radeon_wreg_t pciep_wreg;
785 struct radeon_clock clock;
787 struct radeon_gart gart;
788 struct radeon_mode_info mode_info;
789 struct radeon_scratch scratch;
790 struct radeon_mman mman;
791 struct radeon_fence_driver fence_drv;
793 struct radeon_ib_pool ib_pool;
794 struct radeon_irq irq;
795 struct radeon_asic *asic;
796 struct radeon_gem gem;
798 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
799 struct mutex cs_mutex;
801 struct radeon_dummy_page dummy_page;
807 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
808 const struct firmware *me_fw; /* all family ME firmware */
809 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
810 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
811 struct r600_blit r600_blit;
812 int msi_enabled; /* msi enabled */
813 struct r600_ih ih; /* r6/700 interrupt ring */
814 struct workqueue_struct *wq;
815 struct work_struct hotplug_work;
818 int radeon_device_init(struct radeon_device *rdev,
819 struct drm_device *ddev,
820 struct pci_dev *pdev,
822 void radeon_device_fini(struct radeon_device *rdev);
823 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
826 int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
827 void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
828 void r600_kms_blit_copy(struct radeon_device *rdev,
829 u64 src_gpu_addr, u64 dst_gpu_addr,
832 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
835 return readl(((void __iomem *)rdev->rmmio) + reg);
837 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
838 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
842 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
845 writel(v, ((void __iomem *)rdev->rmmio) + reg);
847 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
848 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
855 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
858 * Registers read & write functions.
860 #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
861 #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
862 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
863 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
864 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
865 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
866 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
867 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
868 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
869 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
870 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
871 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
872 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
873 #define WREG32_P(reg, val, mask) \
875 uint32_t tmp_ = RREG32(reg); \
877 tmp_ |= ((val) & ~(mask)); \
880 #define WREG32_PLL_P(reg, val, mask) \
882 uint32_t tmp_ = RREG32_PLL(reg); \
884 tmp_ |= ((val) & ~(mask)); \
885 WREG32_PLL(reg, tmp_); \
887 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
890 * Indirect registers accessor
892 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
896 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
897 r = RREG32(RADEON_PCIE_DATA);
901 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
903 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
904 WREG32(RADEON_PCIE_DATA, (v));
907 void r100_pll_errata_after_index(struct radeon_device *rdev);
913 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
914 (rdev->pdev->device == 0x5969))
915 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
916 (rdev->family == CHIP_RV200) || \
917 (rdev->family == CHIP_RS100) || \
918 (rdev->family == CHIP_RS200) || \
919 (rdev->family == CHIP_RV250) || \
920 (rdev->family == CHIP_RV280) || \
921 (rdev->family == CHIP_RS300))
922 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
923 (rdev->family == CHIP_RV350) || \
924 (rdev->family == CHIP_R350) || \
925 (rdev->family == CHIP_RV380) || \
926 (rdev->family == CHIP_R420) || \
927 (rdev->family == CHIP_R423) || \
928 (rdev->family == CHIP_RV410) || \
929 (rdev->family == CHIP_RS400) || \
930 (rdev->family == CHIP_RS480))
931 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
932 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
933 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
939 #define RBIOS8(i) (rdev->bios[i])
940 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
941 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
943 int radeon_combios_init(struct radeon_device *rdev);
944 void radeon_combios_fini(struct radeon_device *rdev);
945 int radeon_atombios_init(struct radeon_device *rdev);
946 void radeon_atombios_fini(struct radeon_device *rdev);
952 static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
955 if (rdev->cp.count_dw <= 0) {
956 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
959 rdev->cp.ring[rdev->cp.wptr++] = v;
960 rdev->cp.wptr &= rdev->cp.ptr_mask;
962 rdev->cp.ring_free_dw--;
969 #define radeon_init(rdev) (rdev)->asic->init((rdev))
970 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
971 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
972 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
973 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
974 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
975 #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
976 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
977 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
978 #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
979 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
980 #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
981 #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
982 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
983 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
984 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
985 #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
986 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
987 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
988 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
989 #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
990 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
991 #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
992 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
993 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
994 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
995 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
996 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
997 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
998 #define radeon_hdp_flush(rdev) (rdev)->asic->hdp_flush((rdev))
999 #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1000 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1001 #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1002 #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
1004 /* Common functions */
1005 extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
1006 extern int radeon_modeset_init(struct radeon_device *rdev);
1007 extern void radeon_modeset_fini(struct radeon_device *rdev);
1008 extern bool radeon_card_posted(struct radeon_device *rdev);
1009 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1010 extern int radeon_clocks_init(struct radeon_device *rdev);
1011 extern void radeon_clocks_fini(struct radeon_device *rdev);
1012 extern void radeon_scratch_init(struct radeon_device *rdev);
1013 extern void radeon_surface_init(struct radeon_device *rdev);
1014 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1015 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1016 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1017 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1019 /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
1020 struct r100_mc_save {
1028 extern void r100_cp_disable(struct radeon_device *rdev);
1029 extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
1030 extern void r100_cp_fini(struct radeon_device *rdev);
1031 extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
1032 extern int r100_pci_gart_init(struct radeon_device *rdev);
1033 extern void r100_pci_gart_fini(struct radeon_device *rdev);
1034 extern int r100_pci_gart_enable(struct radeon_device *rdev);
1035 extern void r100_pci_gart_disable(struct radeon_device *rdev);
1036 extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
1037 extern int r100_debugfs_mc_info_init(struct radeon_device *rdev);
1038 extern int r100_gui_wait_for_idle(struct radeon_device *rdev);
1039 extern void r100_ib_fini(struct radeon_device *rdev);
1040 extern int r100_ib_init(struct radeon_device *rdev);
1041 extern void r100_irq_disable(struct radeon_device *rdev);
1042 extern int r100_irq_set(struct radeon_device *rdev);
1043 extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
1044 extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
1045 extern void r100_vram_init_sizes(struct radeon_device *rdev);
1046 extern void r100_wb_disable(struct radeon_device *rdev);
1047 extern void r100_wb_fini(struct radeon_device *rdev);
1048 extern int r100_wb_init(struct radeon_device *rdev);
1049 extern void r100_hdp_reset(struct radeon_device *rdev);
1050 extern int r100_rb2d_reset(struct radeon_device *rdev);
1051 extern int r100_cp_reset(struct radeon_device *rdev);
1052 extern void r100_vga_render_disable(struct radeon_device *rdev);
1053 extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1054 struct radeon_cs_packet *pkt,
1055 struct radeon_bo *robj);
1056 extern int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1057 struct radeon_cs_packet *pkt,
1058 const unsigned *auth, unsigned n,
1059 radeon_packet0_check_t check);
1060 extern int r100_cs_packet_parse(struct radeon_cs_parser *p,
1061 struct radeon_cs_packet *pkt,
1063 extern void r100_enable_bm(struct radeon_device *rdev);
1064 extern void r100_set_common_regs(struct radeon_device *rdev);
1066 /* rv200,rv250,rv280 */
1067 extern void r200_set_safe_registers(struct radeon_device *rdev);
1069 /* r300,r350,rv350,rv370,rv380 */
1070 extern void r300_set_reg_safe(struct radeon_device *rdev);
1071 extern void r300_mc_program(struct radeon_device *rdev);
1072 extern void r300_vram_info(struct radeon_device *rdev);
1073 extern void r300_clock_startup(struct radeon_device *rdev);
1074 extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
1075 extern int rv370_pcie_gart_init(struct radeon_device *rdev);
1076 extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
1077 extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
1078 extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
1080 /* r420,r423,rv410 */
1081 extern int r420_mc_init(struct radeon_device *rdev);
1082 extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
1083 extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1084 extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
1085 extern void r420_pipes_init(struct radeon_device *rdev);
1088 struct rv515_mc_save {
1091 u32 vga_render_control;
1092 u32 vga_hdp_control;
1096 extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
1097 extern void rv515_vga_render_disable(struct radeon_device *rdev);
1098 extern void rv515_set_safe_registers(struct radeon_device *rdev);
1099 extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
1100 extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
1101 extern void rv515_clock_startup(struct radeon_device *rdev);
1102 extern void rv515_debugfs(struct radeon_device *rdev);
1103 extern int rv515_suspend(struct radeon_device *rdev);
1106 extern int rs400_gart_init(struct radeon_device *rdev);
1107 extern int rs400_gart_enable(struct radeon_device *rdev);
1108 extern void rs400_gart_adjust_size(struct radeon_device *rdev);
1109 extern void rs400_gart_disable(struct radeon_device *rdev);
1110 extern void rs400_gart_fini(struct radeon_device *rdev);
1113 extern void rs600_set_safe_registers(struct radeon_device *rdev);
1114 extern int rs600_irq_set(struct radeon_device *rdev);
1115 extern void rs600_irq_disable(struct radeon_device *rdev);
1118 extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
1119 struct drm_display_mode *mode1,
1120 struct drm_display_mode *mode2);
1122 /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
1123 extern bool r600_card_posted(struct radeon_device *rdev);
1124 extern void r600_cp_stop(struct radeon_device *rdev);
1125 extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
1126 extern int r600_cp_resume(struct radeon_device *rdev);
1127 extern int r600_count_pipe_bits(uint32_t val);
1128 extern int r600_gart_clear_page(struct radeon_device *rdev, int i);
1129 extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
1130 extern int r600_pcie_gart_init(struct radeon_device *rdev);
1131 extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
1132 extern int r600_ib_test(struct radeon_device *rdev);
1133 extern int r600_ring_test(struct radeon_device *rdev);
1134 extern void r600_wb_fini(struct radeon_device *rdev);
1135 extern int r600_wb_enable(struct radeon_device *rdev);
1136 extern void r600_wb_disable(struct radeon_device *rdev);
1137 extern void r600_scratch_init(struct radeon_device *rdev);
1138 extern int r600_blit_init(struct radeon_device *rdev);
1139 extern void r600_blit_fini(struct radeon_device *rdev);
1140 extern int r600_init_microcode(struct radeon_device *rdev);
1141 extern int r600_gpu_reset(struct radeon_device *rdev);
1143 extern int r600_irq_init(struct radeon_device *rdev);
1144 extern void r600_irq_fini(struct radeon_device *rdev);
1145 extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
1146 extern int r600_irq_set(struct radeon_device *rdev);
1148 #include "radeon_object.h"