2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 #include "radeon_object.h"
33 /* TODO: Here are things that needs to be done :
34 * - surface allocator & initializer : (bit like scratch reg) should
35 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
37 * - WB : write back stuff (do it bit like scratch reg things)
38 * - Vblank : look at Jesse's rework and what we should do
39 * - r600/r700: gart & cp
40 * - cs : clean cs ioctl use bitmap & things like that.
41 * - power management stuff
42 * - Barrier in gart code
43 * - Unmappabled vram ?
44 * - TESTING, TESTING, TESTING
47 /* Initialization path:
48 * We expect that acceleration initialization might fail for various
49 * reasons even thought we work hard to make it works on most
50 * configurations. In order to still have a working userspace in such
51 * situation the init path must succeed up to the memory controller
52 * initialization point. Failure before this point are considered as
53 * fatal error. Here is the init callchain :
54 * radeon_device_init perform common structure, mutex initialization
55 * asic_init setup the GPU memory layout and perform all
56 * one time initialization (failure in this
57 * function are considered fatal)
58 * asic_startup setup the GPU acceleration, in order to
59 * follow guideline the first thing this
60 * function should do is setting the GPU
61 * memory controller (only MC setup failure
62 * are considered as fatal)
65 #include <asm/atomic.h>
66 #include <linux/wait.h>
67 #include <linux/list.h>
68 #include <linux/kref.h>
70 #include "radeon_family.h"
71 #include "radeon_mode.h"
72 #include "radeon_reg.h"
77 extern int radeon_no_wb;
78 extern int radeon_modeset;
79 extern int radeon_dynclks;
80 extern int radeon_r4xx_atom;
81 extern int radeon_agpmode;
82 extern int radeon_vram_limit;
83 extern int radeon_gart_size;
84 extern int radeon_benchmarking;
85 extern int radeon_testing;
86 extern int radeon_connector_table;
90 * Copy from radeon_drv.h so we don't have to include both and have conflicting
93 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
94 #define RADEON_IB_POOL_SIZE 16
95 #define RADEON_DEBUGFS_MAX_NUM_FILES 32
96 #define RADEONFB_CONN_LIMIT 4
97 #define RADEON_BIOS_NUM_SCRATCH 8
100 * Errata workarounds.
102 enum radeon_pll_errata {
103 CHIP_ERRATA_R300_CG = 0x00000001,
104 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
105 CHIP_ERRATA_PLL_DELAY = 0x00000004
109 struct radeon_device;
115 bool radeon_get_bios(struct radeon_device *rdev);
121 struct radeon_dummy_page {
125 int radeon_dummy_page_init(struct radeon_device *rdev);
126 void radeon_dummy_page_fini(struct radeon_device *rdev);
132 struct radeon_clock {
133 struct radeon_pll p1pll;
134 struct radeon_pll p2pll;
135 struct radeon_pll spll;
136 struct radeon_pll mpll;
138 uint32_t default_mclk;
139 uint32_t default_sclk;
145 int radeon_pm_init(struct radeon_device *rdev);
150 struct radeon_fence_driver {
151 uint32_t scratch_reg;
154 unsigned long count_timeout;
155 wait_queue_head_t queue;
157 struct list_head created;
158 struct list_head emited;
159 struct list_head signaled;
162 struct radeon_fence {
163 struct radeon_device *rdev;
165 struct list_head list;
166 /* protected by radeon_fence.lock */
168 unsigned long timeout;
173 int radeon_fence_driver_init(struct radeon_device *rdev);
174 void radeon_fence_driver_fini(struct radeon_device *rdev);
175 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
176 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
177 void radeon_fence_process(struct radeon_device *rdev);
178 bool radeon_fence_signaled(struct radeon_fence *fence);
179 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
180 int radeon_fence_wait_next(struct radeon_device *rdev);
181 int radeon_fence_wait_last(struct radeon_device *rdev);
182 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
183 void radeon_fence_unref(struct radeon_fence **fence);
188 struct radeon_surface_reg {
189 struct radeon_object *robj;
192 #define RADEON_GEM_MAX_SURFACES 8
197 struct radeon_object;
199 struct radeon_object_list {
200 struct list_head list;
201 struct radeon_object *robj;
205 uint32_t tiling_flags;
208 int radeon_object_init(struct radeon_device *rdev);
209 void radeon_object_fini(struct radeon_device *rdev);
210 int radeon_object_create(struct radeon_device *rdev,
211 struct drm_gem_object *gobj,
216 struct radeon_object **robj_ptr);
217 int radeon_object_kmap(struct radeon_object *robj, void **ptr);
218 void radeon_object_kunmap(struct radeon_object *robj);
219 void radeon_object_unref(struct radeon_object **robj);
220 int radeon_object_pin(struct radeon_object *robj, uint32_t domain,
222 void radeon_object_unpin(struct radeon_object *robj);
223 int radeon_object_wait(struct radeon_object *robj);
224 int radeon_object_busy_domain(struct radeon_object *robj, uint32_t *cur_placement);
225 int radeon_object_evict_vram(struct radeon_device *rdev);
226 int radeon_object_mmap(struct radeon_object *robj, uint64_t *offset);
227 void radeon_object_force_delete(struct radeon_device *rdev);
228 void radeon_object_list_add_object(struct radeon_object_list *lobj,
229 struct list_head *head);
230 int radeon_object_list_validate(struct list_head *head, void *fence);
231 void radeon_object_list_unvalidate(struct list_head *head);
232 void radeon_object_list_clean(struct list_head *head);
233 int radeon_object_fbdev_mmap(struct radeon_object *robj,
234 struct vm_area_struct *vma);
235 unsigned long radeon_object_size(struct radeon_object *robj);
236 void radeon_object_clear_surface_reg(struct radeon_object *robj);
237 int radeon_object_check_tiling(struct radeon_object *robj, bool has_moved,
239 void radeon_object_set_tiling_flags(struct radeon_object *robj,
240 uint32_t tiling_flags, uint32_t pitch);
241 void radeon_object_get_tiling_flags(struct radeon_object *robj, uint32_t *tiling_flags, uint32_t *pitch);
242 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
243 struct ttm_mem_reg *mem);
244 void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
249 struct list_head objects;
252 int radeon_gem_init(struct radeon_device *rdev);
253 void radeon_gem_fini(struct radeon_device *rdev);
254 int radeon_gem_object_create(struct radeon_device *rdev, int size,
255 int alignment, int initial_domain,
256 bool discardable, bool kernel,
258 struct drm_gem_object **obj);
259 int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
261 void radeon_gem_object_unpin(struct drm_gem_object *obj);
265 * GART structures, functions & helpers
269 struct radeon_gart_table_ram {
270 volatile uint32_t *ptr;
273 struct radeon_gart_table_vram {
274 struct radeon_object *robj;
275 volatile uint32_t *ptr;
278 union radeon_gart_table {
279 struct radeon_gart_table_ram ram;
280 struct radeon_gart_table_vram vram;
283 #define RADEON_GPU_PAGE_SIZE 4096
286 dma_addr_t table_addr;
287 unsigned num_gpu_pages;
288 unsigned num_cpu_pages;
290 union radeon_gart_table table;
292 dma_addr_t *pages_addr;
296 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
297 void radeon_gart_table_ram_free(struct radeon_device *rdev);
298 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
299 void radeon_gart_table_vram_free(struct radeon_device *rdev);
300 int radeon_gart_init(struct radeon_device *rdev);
301 void radeon_gart_fini(struct radeon_device *rdev);
302 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
304 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
305 int pages, struct page **pagelist);
309 * GPU MC structures, functions & helpers
312 resource_size_t aper_size;
313 resource_size_t aper_base;
314 resource_size_t agp_base;
315 /* for some chips with <= 32MB we need to lie
316 * about vram size near mc fb location */
331 int radeon_mc_setup(struct radeon_device *rdev);
335 * GPU scratch registers structures, functions & helpers
337 struct radeon_scratch {
343 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
344 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
353 /* FIXME: use a define max crtc rather than hardcode it */
354 bool crtc_vblank_int[2];
359 int radeon_irq_kms_init(struct radeon_device *rdev);
360 void radeon_irq_kms_fini(struct radeon_device *rdev);
361 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
362 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
368 struct list_head list;
371 struct radeon_fence *fence;
378 * mutex protects scheduled_ibs, ready, alloc_bm
380 struct radeon_ib_pool {
382 struct radeon_object *robj;
383 struct list_head scheduled_ibs;
384 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
386 DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
390 struct radeon_object *ring_obj;
391 volatile uint32_t *ring;
396 unsigned ring_free_dw;
409 struct radeon_object *ring_obj;
410 volatile uint32_t *ring;
423 struct radeon_object *shader_obj;
425 u32 vs_offset, ps_offset;
428 u32 vb_used, vb_total;
429 struct radeon_ib *vb_ib;
432 int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
433 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
434 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
435 int radeon_ib_pool_init(struct radeon_device *rdev);
436 void radeon_ib_pool_fini(struct radeon_device *rdev);
437 int radeon_ib_test(struct radeon_device *rdev);
438 /* Ring access between begin & end cannot sleep */
439 void radeon_ring_free_size(struct radeon_device *rdev);
440 int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
441 void radeon_ring_unlock_commit(struct radeon_device *rdev);
442 void radeon_ring_unlock_undo(struct radeon_device *rdev);
443 int radeon_ring_test(struct radeon_device *rdev);
444 int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
445 void radeon_ring_fini(struct radeon_device *rdev);
451 struct radeon_cs_reloc {
452 struct drm_gem_object *gobj;
453 struct radeon_object *robj;
454 struct radeon_object_list lobj;
459 struct radeon_cs_chunk {
465 void __user *user_ptr;
466 int last_copied_page;
470 struct radeon_cs_parser {
471 struct radeon_device *rdev;
472 struct drm_file *filp;
475 struct radeon_cs_chunk *chunks;
476 uint64_t *chunks_array;
481 struct radeon_cs_reloc *relocs;
482 struct radeon_cs_reloc **relocs_ptr;
483 struct list_head validated;
484 /* indices of various chunks */
486 int chunk_relocs_idx;
487 struct radeon_ib *ib;
493 extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
494 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
497 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
499 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
500 u32 pg_idx, pg_offset;
504 pg_idx = (idx * 4) / PAGE_SIZE;
505 pg_offset = (idx * 4) % PAGE_SIZE;
507 if (ibc->kpage_idx[0] == pg_idx)
508 return ibc->kpage[0][pg_offset/4];
509 if (ibc->kpage_idx[1] == pg_idx)
510 return ibc->kpage[1][pg_offset/4];
512 new_page = radeon_cs_update_pages(p, pg_idx);
514 p->parser_error = new_page;
518 idx_value = ibc->kpage[new_page][pg_offset/4];
522 struct radeon_cs_packet {
531 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
532 struct radeon_cs_packet *pkt,
533 unsigned idx, unsigned reg);
534 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
535 struct radeon_cs_packet *pkt);
541 int radeon_agp_init(struct radeon_device *rdev);
542 void radeon_agp_resume(struct radeon_device *rdev);
543 void radeon_agp_fini(struct radeon_device *rdev);
550 struct radeon_object *wb_obj;
551 volatile uint32_t *wb;
556 * struct radeon_pm - power management datas
557 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
558 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
559 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
560 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
561 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
562 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
563 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
564 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
565 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
566 * @sclk: GPU clock Mhz (core bandwith depends of this clock)
567 * @needed_bandwidth: current bandwidth needs
569 * It keeps track of various data needed to take powermanagement decision.
570 * Bandwith need is used to determine minimun clock of the GPU and memory.
571 * Equation between gpu/memory clock and available bandwidth is hw dependent
572 * (type of memory, bus size, efficiency, ...)
575 fixed20_12 max_bandwidth;
576 fixed20_12 igp_sideport_mclk;
577 fixed20_12 igp_system_mclk;
578 fixed20_12 igp_ht_link_clk;
579 fixed20_12 igp_ht_link_width;
580 fixed20_12 k8_bandwidth;
581 fixed20_12 sideport_bandwidth;
582 fixed20_12 ht_bandwidth;
583 fixed20_12 core_bandwidth;
585 fixed20_12 needed_bandwidth;
592 void radeon_benchmark(struct radeon_device *rdev);
598 void radeon_test_moves(struct radeon_device *rdev);
604 int radeon_debugfs_add_files(struct radeon_device *rdev,
605 struct drm_info_list *files,
607 int radeon_debugfs_fence_init(struct radeon_device *rdev);
608 int r100_debugfs_rbbm_init(struct radeon_device *rdev);
609 int r100_debugfs_cp_init(struct radeon_device *rdev);
613 * ASIC specific functions.
616 int (*init)(struct radeon_device *rdev);
617 void (*fini)(struct radeon_device *rdev);
618 int (*resume)(struct radeon_device *rdev);
619 int (*suspend)(struct radeon_device *rdev);
620 void (*vga_set_state)(struct radeon_device *rdev, bool state);
621 int (*gpu_reset)(struct radeon_device *rdev);
622 void (*gart_tlb_flush)(struct radeon_device *rdev);
623 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
624 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
625 void (*cp_fini)(struct radeon_device *rdev);
626 void (*cp_disable)(struct radeon_device *rdev);
627 void (*cp_commit)(struct radeon_device *rdev);
628 void (*ring_start)(struct radeon_device *rdev);
629 int (*ring_test)(struct radeon_device *rdev);
630 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
631 int (*irq_set)(struct radeon_device *rdev);
632 int (*irq_process)(struct radeon_device *rdev);
633 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
634 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
635 int (*cs_parse)(struct radeon_cs_parser *p);
636 int (*copy_blit)(struct radeon_device *rdev,
640 struct radeon_fence *fence);
641 int (*copy_dma)(struct radeon_device *rdev,
645 struct radeon_fence *fence);
646 int (*copy)(struct radeon_device *rdev,
650 struct radeon_fence *fence);
651 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
652 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
653 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
654 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
655 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
656 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
657 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
658 uint32_t tiling_flags, uint32_t pitch,
659 uint32_t offset, uint32_t obj_size);
660 int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
661 void (*bandwidth_update)(struct radeon_device *rdev);
662 void (*hdp_flush)(struct radeon_device *rdev);
669 const unsigned *reg_safe_bm;
670 unsigned reg_safe_bm_size;
674 const unsigned *reg_safe_bm;
675 unsigned reg_safe_bm_size;
680 unsigned max_tile_pipes;
682 unsigned max_backends;
684 unsigned max_threads;
685 unsigned max_stack_entries;
686 unsigned max_hw_contexts;
687 unsigned max_gs_threads;
688 unsigned sx_max_export_size;
689 unsigned sx_max_export_pos_size;
690 unsigned sx_max_export_smx_size;
691 unsigned sq_num_cf_insts;
696 unsigned max_tile_pipes;
698 unsigned max_backends;
700 unsigned max_threads;
701 unsigned max_stack_entries;
702 unsigned max_hw_contexts;
703 unsigned max_gs_threads;
704 unsigned sx_max_export_size;
705 unsigned sx_max_export_pos_size;
706 unsigned sx_max_export_smx_size;
707 unsigned sq_num_cf_insts;
708 unsigned sx_num_of_sets;
709 unsigned sc_prim_fifo_size;
710 unsigned sc_hiz_tile_fifo_size;
711 unsigned sc_earlyz_tile_fifo_fize;
714 union radeon_asic_config {
715 struct r300_asic r300;
716 struct r100_asic r100;
717 struct r600_asic r600;
718 struct rv770_asic rv770;
725 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
726 struct drm_file *filp);
727 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
728 struct drm_file *filp);
729 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
730 struct drm_file *file_priv);
731 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
732 struct drm_file *file_priv);
733 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
734 struct drm_file *file_priv);
735 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
736 struct drm_file *file_priv);
737 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
738 struct drm_file *filp);
739 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
740 struct drm_file *filp);
741 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
742 struct drm_file *filp);
743 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
744 struct drm_file *filp);
745 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
746 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
747 struct drm_file *filp);
748 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
749 struct drm_file *filp);
753 * Core structure, functions and helpers.
755 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
756 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
758 struct radeon_device {
760 struct drm_device *ddev;
761 struct pci_dev *pdev;
763 union radeon_asic_config config;
764 enum radeon_family family;
767 enum radeon_pll_errata pll_errata;
774 uint16_t bios_header_start;
775 struct radeon_object *stollen_vga_memory;
776 struct fb_info *fbdev_info;
777 struct radeon_object *fbdev_robj;
778 struct radeon_framebuffer *fbdev_rfb;
780 resource_size_t rmmio_base;
781 resource_size_t rmmio_size;
783 radeon_rreg_t mc_rreg;
784 radeon_wreg_t mc_wreg;
785 radeon_rreg_t pll_rreg;
786 radeon_wreg_t pll_wreg;
787 uint32_t pcie_reg_mask;
788 radeon_rreg_t pciep_rreg;
789 radeon_wreg_t pciep_wreg;
790 struct radeon_clock clock;
792 struct radeon_gart gart;
793 struct radeon_mode_info mode_info;
794 struct radeon_scratch scratch;
795 struct radeon_mman mman;
796 struct radeon_fence_driver fence_drv;
798 struct radeon_ib_pool ib_pool;
799 struct radeon_irq irq;
800 struct radeon_asic *asic;
801 struct radeon_gem gem;
803 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
804 struct mutex cs_mutex;
806 struct radeon_dummy_page dummy_page;
812 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
813 const struct firmware *me_fw; /* all family ME firmware */
814 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
815 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
816 struct r600_blit r600_blit;
817 int msi_enabled; /* msi enabled */
818 struct r600_ih ih; /* r6/700 interrupt ring */
821 int radeon_device_init(struct radeon_device *rdev,
822 struct drm_device *ddev,
823 struct pci_dev *pdev,
825 void radeon_device_fini(struct radeon_device *rdev);
826 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
829 int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
830 void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
831 void r600_kms_blit_copy(struct radeon_device *rdev,
832 u64 src_gpu_addr, u64 dst_gpu_addr,
835 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
838 return readl(((void __iomem *)rdev->rmmio) + reg);
840 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
841 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
845 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
848 writel(v, ((void __iomem *)rdev->rmmio) + reg);
850 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
851 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
857 * Registers read & write functions.
859 #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
860 #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
861 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
862 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
863 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
864 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
865 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
866 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
867 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
868 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
869 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
870 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
871 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
872 #define WREG32_P(reg, val, mask) \
874 uint32_t tmp_ = RREG32(reg); \
876 tmp_ |= ((val) & ~(mask)); \
879 #define WREG32_PLL_P(reg, val, mask) \
881 uint32_t tmp_ = RREG32_PLL(reg); \
883 tmp_ |= ((val) & ~(mask)); \
884 WREG32_PLL(reg, tmp_); \
886 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
889 * Indirect registers accessor
891 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
895 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
896 r = RREG32(RADEON_PCIE_DATA);
900 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
902 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
903 WREG32(RADEON_PCIE_DATA, (v));
906 void r100_pll_errata_after_index(struct radeon_device *rdev);
912 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
913 (rdev->pdev->device == 0x5969))
914 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
915 (rdev->family == CHIP_RV200) || \
916 (rdev->family == CHIP_RS100) || \
917 (rdev->family == CHIP_RS200) || \
918 (rdev->family == CHIP_RV250) || \
919 (rdev->family == CHIP_RV280) || \
920 (rdev->family == CHIP_RS300))
921 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
922 (rdev->family == CHIP_RV350) || \
923 (rdev->family == CHIP_R350) || \
924 (rdev->family == CHIP_RV380) || \
925 (rdev->family == CHIP_R420) || \
926 (rdev->family == CHIP_R423) || \
927 (rdev->family == CHIP_RV410) || \
928 (rdev->family == CHIP_RS400) || \
929 (rdev->family == CHIP_RS480))
930 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
931 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
932 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
938 #define RBIOS8(i) (rdev->bios[i])
939 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
940 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
942 int radeon_combios_init(struct radeon_device *rdev);
943 void radeon_combios_fini(struct radeon_device *rdev);
944 int radeon_atombios_init(struct radeon_device *rdev);
945 void radeon_atombios_fini(struct radeon_device *rdev);
951 static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
954 if (rdev->cp.count_dw <= 0) {
955 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
958 rdev->cp.ring[rdev->cp.wptr++] = v;
959 rdev->cp.wptr &= rdev->cp.ptr_mask;
961 rdev->cp.ring_free_dw--;
968 #define radeon_init(rdev) (rdev)->asic->init((rdev))
969 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
970 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
971 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
972 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
973 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
974 #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
975 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
976 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
977 #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
978 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
979 #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
980 #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
981 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
982 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
983 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
984 #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
985 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
986 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
987 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
988 #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
989 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
990 #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
991 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
992 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
993 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
994 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
995 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
996 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
997 #define radeon_hdp_flush(rdev) (rdev)->asic->hdp_flush((rdev))
999 /* Common functions */
1000 extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
1001 extern int radeon_modeset_init(struct radeon_device *rdev);
1002 extern void radeon_modeset_fini(struct radeon_device *rdev);
1003 extern bool radeon_card_posted(struct radeon_device *rdev);
1004 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1005 extern int radeon_clocks_init(struct radeon_device *rdev);
1006 extern void radeon_clocks_fini(struct radeon_device *rdev);
1007 extern void radeon_scratch_init(struct radeon_device *rdev);
1008 extern void radeon_surface_init(struct radeon_device *rdev);
1009 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1010 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1011 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1013 /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
1014 struct r100_mc_save {
1022 extern void r100_cp_disable(struct radeon_device *rdev);
1023 extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
1024 extern void r100_cp_fini(struct radeon_device *rdev);
1025 extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
1026 extern int r100_pci_gart_init(struct radeon_device *rdev);
1027 extern void r100_pci_gart_fini(struct radeon_device *rdev);
1028 extern int r100_pci_gart_enable(struct radeon_device *rdev);
1029 extern void r100_pci_gart_disable(struct radeon_device *rdev);
1030 extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
1031 extern int r100_debugfs_mc_info_init(struct radeon_device *rdev);
1032 extern int r100_gui_wait_for_idle(struct radeon_device *rdev);
1033 extern void r100_ib_fini(struct radeon_device *rdev);
1034 extern int r100_ib_init(struct radeon_device *rdev);
1035 extern void r100_irq_disable(struct radeon_device *rdev);
1036 extern int r100_irq_set(struct radeon_device *rdev);
1037 extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
1038 extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
1039 extern void r100_vram_init_sizes(struct radeon_device *rdev);
1040 extern void r100_wb_disable(struct radeon_device *rdev);
1041 extern void r100_wb_fini(struct radeon_device *rdev);
1042 extern int r100_wb_init(struct radeon_device *rdev);
1043 extern void r100_hdp_reset(struct radeon_device *rdev);
1044 extern int r100_rb2d_reset(struct radeon_device *rdev);
1045 extern int r100_cp_reset(struct radeon_device *rdev);
1046 extern void r100_vga_render_disable(struct radeon_device *rdev);
1047 extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1048 struct radeon_cs_packet *pkt,
1049 struct radeon_object *robj);
1050 extern int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1051 struct radeon_cs_packet *pkt,
1052 const unsigned *auth, unsigned n,
1053 radeon_packet0_check_t check);
1054 extern int r100_cs_packet_parse(struct radeon_cs_parser *p,
1055 struct radeon_cs_packet *pkt,
1057 extern void r100_enable_bm(struct radeon_device *rdev);
1059 /* rv200,rv250,rv280 */
1060 extern void r200_set_safe_registers(struct radeon_device *rdev);
1062 /* r300,r350,rv350,rv370,rv380 */
1063 extern void r300_set_reg_safe(struct radeon_device *rdev);
1064 extern void r300_mc_program(struct radeon_device *rdev);
1065 extern void r300_vram_info(struct radeon_device *rdev);
1066 extern void r300_clock_startup(struct radeon_device *rdev);
1067 extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
1068 extern int rv370_pcie_gart_init(struct radeon_device *rdev);
1069 extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
1070 extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
1071 extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
1073 /* r420,r423,rv410 */
1074 extern int r420_mc_init(struct radeon_device *rdev);
1075 extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
1076 extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1077 extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
1078 extern void r420_pipes_init(struct radeon_device *rdev);
1081 struct rv515_mc_save {
1084 u32 vga_render_control;
1085 u32 vga_hdp_control;
1089 extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
1090 extern void rv515_vga_render_disable(struct radeon_device *rdev);
1091 extern void rv515_set_safe_registers(struct radeon_device *rdev);
1092 extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
1093 extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
1094 extern void rv515_clock_startup(struct radeon_device *rdev);
1095 extern void rv515_debugfs(struct radeon_device *rdev);
1096 extern int rv515_suspend(struct radeon_device *rdev);
1099 extern int rs400_gart_init(struct radeon_device *rdev);
1100 extern int rs400_gart_enable(struct radeon_device *rdev);
1101 extern void rs400_gart_adjust_size(struct radeon_device *rdev);
1102 extern void rs400_gart_disable(struct radeon_device *rdev);
1103 extern void rs400_gart_fini(struct radeon_device *rdev);
1106 extern void rs600_set_safe_registers(struct radeon_device *rdev);
1107 extern int rs600_irq_set(struct radeon_device *rdev);
1108 extern void rs600_irq_disable(struct radeon_device *rdev);
1111 extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
1112 struct drm_display_mode *mode1,
1113 struct drm_display_mode *mode2);
1115 /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
1116 extern bool r600_card_posted(struct radeon_device *rdev);
1117 extern void r600_cp_stop(struct radeon_device *rdev);
1118 extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
1119 extern int r600_cp_resume(struct radeon_device *rdev);
1120 extern int r600_count_pipe_bits(uint32_t val);
1121 extern int r600_gart_clear_page(struct radeon_device *rdev, int i);
1122 extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
1123 extern int r600_pcie_gart_init(struct radeon_device *rdev);
1124 extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
1125 extern int r600_ib_test(struct radeon_device *rdev);
1126 extern int r600_ring_test(struct radeon_device *rdev);
1127 extern void r600_wb_fini(struct radeon_device *rdev);
1128 extern int r600_wb_enable(struct radeon_device *rdev);
1129 extern void r600_wb_disable(struct radeon_device *rdev);
1130 extern void r600_scratch_init(struct radeon_device *rdev);
1131 extern int r600_blit_init(struct radeon_device *rdev);
1132 extern void r600_blit_fini(struct radeon_device *rdev);
1133 extern int r600_init_microcode(struct radeon_device *rdev);
1134 extern int r600_gpu_reset(struct radeon_device *rdev);
1136 extern int r600_irq_init(struct radeon_device *rdev);
1137 extern void r600_irq_fini(struct radeon_device *rdev);
1138 extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
1139 extern int r600_irq_set(struct radeon_device *rdev);