SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/r600.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include <linux/firmware.h>
  30 #include <linux/platform_device.h>
  31 #include "drmP.h"
  32 #include "radeon_drm.h"
  33 #include "radeon.h"
  34 #include "radeon_mode.h"
  35 #include "r600d.h"
  36 #include "atom.h"
  37 #include "avivod.h"
  38
  39 #define PFP_UCODE_SIZE 576
  40 #define PM4_UCODE_SIZE 1792
  41 #define RLC_UCODE_SIZE 768
  42 #define R700_PFP_UCODE_SIZE 848
  43 #define R700_PM4_UCODE_SIZE 1360
  44 #define R700_RLC_UCODE_SIZE 1024
  45
  46 /* Firmware Names */
  47 MODULE_FIRMWARE("radeon/R600_pfp.bin");
  48 MODULE_FIRMWARE("radeon/R600_me.bin");
  49 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
  50 MODULE_FIRMWARE("radeon/RV610_me.bin");
  51 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
  52 MODULE_FIRMWARE("radeon/RV630_me.bin");
  53 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
  54 MODULE_FIRMWARE("radeon/RV620_me.bin");
  55 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
  56 MODULE_FIRMWARE("radeon/RV635_me.bin");
  57 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
  58 MODULE_FIRMWARE("radeon/RV670_me.bin");
  59 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
  60 MODULE_FIRMWARE("radeon/RS780_me.bin");
  61 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
  62 MODULE_FIRMWARE("radeon/RV770_me.bin");
  63 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
  64 MODULE_FIRMWARE("radeon/RV730_me.bin");
  65 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
  66 MODULE_FIRMWARE("radeon/RV710_me.bin");
  67 MODULE_FIRMWARE("radeon/R600_rlc.bin");
  68 MODULE_FIRMWARE("radeon/R700_rlc.bin");
  69
  70 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
  71
  72 /* r600,rv610,rv630,rv620,rv635,rv670 */
  73 int r600_mc_wait_for_idle(struct radeon_device *rdev);
  74 void r600_gpu_init(struct radeon_device *rdev);
  75 void r600_fini(struct radeon_device *rdev);
  76
  77 /* hpd for digital panel detect/disconnect */
  78 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
  79 {
  80         bool connected = false;
  81
  82         if (ASIC_IS_DCE3(rdev)) {
  83                 switch (hpd) {
  84                 case RADEON_HPD_1:
  85                         if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
  86                                 connected = true;
  87                         break;
  88                 case RADEON_HPD_2:
  89                         if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
  90                                 connected = true;
  91                         break;
  92                 case RADEON_HPD_3:
  93                         if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
  94                                 connected = true;
  95                         break;
  96                 case RADEON_HPD_4:
  97                         if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
  98                                 connected = true;
  99                         break;
 100                         /* DCE 3.2 */
 101                 case RADEON_HPD_5:
 102                         if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 103                                 connected = true;
 104                         break;
 105                 case RADEON_HPD_6:
 106                         if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 107                                 connected = true;
 108                         break;
 109                 default:
 110                         break;
 111                 }
 112         } else {
 113                 switch (hpd) {
 114                 case RADEON_HPD_1:
 115                         if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 116                                 connected = true;
 117                         break;
 118                 case RADEON_HPD_2:
 119                         if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 120                                 connected = true;
 121                         break;
 122                 case RADEON_HPD_3:
 123                         if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 124                                 connected = true;
 125                         break;
 126                 default:
 127                         break;
 128                 }
 129         }
 130         return connected;
 131 }
 132
 133 void r600_hpd_set_polarity(struct radeon_device *rdev,
 134                            enum radeon_hpd_id hpd)
 135 {
 136         u32 tmp;
 137         bool connected = r600_hpd_sense(rdev, hpd);
 138
 139         if (ASIC_IS_DCE3(rdev)) {
 140                 switch (hpd) {
 141                 case RADEON_HPD_1:
 142                         tmp = RREG32(DC_HPD1_INT_CONTROL);
 143                         if (connected)
 144                                 tmp &= ~DC_HPDx_INT_POLARITY;
 145                         else
 146                                 tmp |= DC_HPDx_INT_POLARITY;
 147                         WREG32(DC_HPD1_INT_CONTROL, tmp);
 148                         break;
 149                 case RADEON_HPD_2:
 150                         tmp = RREG32(DC_HPD2_INT_CONTROL);
 151                         if (connected)
 152                                 tmp &= ~DC_HPDx_INT_POLARITY;
 153                         else
 154                                 tmp |= DC_HPDx_INT_POLARITY;
 155                         WREG32(DC_HPD2_INT_CONTROL, tmp);
 156                         break;
 157                 case RADEON_HPD_3:
 158                         tmp = RREG32(DC_HPD3_INT_CONTROL);
 159                         if (connected)
 160                                 tmp &= ~DC_HPDx_INT_POLARITY;
 161                         else
 162                                 tmp |= DC_HPDx_INT_POLARITY;
 163                         WREG32(DC_HPD3_INT_CONTROL, tmp);
 164                         break;
 165                 case RADEON_HPD_4:
 166                         tmp = RREG32(DC_HPD4_INT_CONTROL);
 167                         if (connected)
 168                                 tmp &= ~DC_HPDx_INT_POLARITY;
 169                         else
 170                                 tmp |= DC_HPDx_INT_POLARITY;
 171                         WREG32(DC_HPD4_INT_CONTROL, tmp);
 172                         break;
 173                 case RADEON_HPD_5:
 174                         tmp = RREG32(DC_HPD5_INT_CONTROL);
 175                         if (connected)
 176                                 tmp &= ~DC_HPDx_INT_POLARITY;
 177                         else
 178                                 tmp |= DC_HPDx_INT_POLARITY;
 179                         WREG32(DC_HPD5_INT_CONTROL, tmp);
 180                         break;
 181                         /* DCE 3.2 */
 182                 case RADEON_HPD_6:
 183                         tmp = RREG32(DC_HPD6_INT_CONTROL);
 184                         if (connected)
 185                                 tmp &= ~DC_HPDx_INT_POLARITY;
 186                         else
 187                                 tmp |= DC_HPDx_INT_POLARITY;
 188                         WREG32(DC_HPD6_INT_CONTROL, tmp);
 189                         break;
 190                 default:
 191                         break;
 192                 }
 193         } else {
 194                 switch (hpd) {
 195                 case RADEON_HPD_1:
 196                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
 197                         if (connected)
 198                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 199                         else
 200                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 201                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
 202                         break;
 203                 case RADEON_HPD_2:
 204                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
 205                         if (connected)
 206                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 207                         else
 208                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 209                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
 210                         break;
 211                 case RADEON_HPD_3:
 212                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
 213                         if (connected)
 214                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 215                         else
 216                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 217                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
 218                         break;
 219                 default:
 220                         break;
 221                 }
 222         }
 223 }
 224
 225 void r600_hpd_init(struct radeon_device *rdev)
 226 {
 227         struct drm_device *dev = rdev->ddev;
 228         struct drm_connector *connector;
 229
 230         if (ASIC_IS_DCE3(rdev)) {
 231                 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
 232                 if (ASIC_IS_DCE32(rdev))
 233                         tmp |= DC_HPDx_EN;
 234
 235                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 236                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 237                         switch (radeon_connector->hpd.hpd) {
 238                         case RADEON_HPD_1:
 239                                 WREG32(DC_HPD1_CONTROL, tmp);
 240                                 rdev->irq.hpd[0] = true;
 241                                 break;
 242                         case RADEON_HPD_2:
 243                                 WREG32(DC_HPD2_CONTROL, tmp);
 244                                 rdev->irq.hpd[1] = true;
 245                                 break;
 246                         case RADEON_HPD_3:
 247                                 WREG32(DC_HPD3_CONTROL, tmp);
 248                                 rdev->irq.hpd[2] = true;
 249                                 break;
 250                         case RADEON_HPD_4:
 251                                 WREG32(DC_HPD4_CONTROL, tmp);
 252                                 rdev->irq.hpd[3] = true;
 253                                 break;
 254                                 /* DCE 3.2 */
 255                         case RADEON_HPD_5:
 256                                 WREG32(DC_HPD5_CONTROL, tmp);
 257                                 rdev->irq.hpd[4] = true;
 258                                 break;
 259                         case RADEON_HPD_6:
 260                                 WREG32(DC_HPD6_CONTROL, tmp);
 261                                 rdev->irq.hpd[5] = true;
 262                                 break;
 263                         default:
 264                                 break;
 265                         }
 266                 }
 267         } else {
 268                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 269                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 270                         switch (radeon_connector->hpd.hpd) {
 271                         case RADEON_HPD_1:
 272                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 273                                 rdev->irq.hpd[0] = true;
 274                                 break;
 275                         case RADEON_HPD_2:
 276                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 277                                 rdev->irq.hpd[1] = true;
 278                                 break;
 279                         case RADEON_HPD_3:
 280                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 281                                 rdev->irq.hpd[2] = true;
 282                                 break;
 283                         default:
 284                                 break;
 285                         }
 286                 }
 287         }
 288         if (rdev->irq.installed)
 289                 r600_irq_set(rdev);
 290 }
 291
 292 void r600_hpd_fini(struct radeon_device *rdev)
 293 {
 294         struct drm_device *dev = rdev->ddev;
 295         struct drm_connector *connector;
 296
 297         if (ASIC_IS_DCE3(rdev)) {
 298                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 299                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 300                         switch (radeon_connector->hpd.hpd) {
 301                         case RADEON_HPD_1:
 302                                 WREG32(DC_HPD1_CONTROL, 0);
 303                                 rdev->irq.hpd[0] = false;
 304                                 break;
 305                         case RADEON_HPD_2:
 306                                 WREG32(DC_HPD2_CONTROL, 0);
 307                                 rdev->irq.hpd[1] = false;
 308                                 break;
 309                         case RADEON_HPD_3:
 310                                 WREG32(DC_HPD3_CONTROL, 0);
 311                                 rdev->irq.hpd[2] = false;
 312                                 break;
 313                         case RADEON_HPD_4:
 314                                 WREG32(DC_HPD4_CONTROL, 0);
 315                                 rdev->irq.hpd[3] = false;
 316                                 break;
 317                                 /* DCE 3.2 */
 318                         case RADEON_HPD_5:
 319                                 WREG32(DC_HPD5_CONTROL, 0);
 320                                 rdev->irq.hpd[4] = false;
 321                                 break;
 322                         case RADEON_HPD_6:
 323                                 WREG32(DC_HPD6_CONTROL, 0);
 324                                 rdev->irq.hpd[5] = false;
 325                                 break;
 326                         default:
 327                                 break;
 328                         }
 329                 }
 330         } else {
 331                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 332                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 333                         switch (radeon_connector->hpd.hpd) {
 334                         case RADEON_HPD_1:
 335                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
 336                                 rdev->irq.hpd[0] = false;
 337                                 break;
 338                         case RADEON_HPD_2:
 339                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
 340                                 rdev->irq.hpd[1] = false;
 341                                 break;
 342                         case RADEON_HPD_3:
 343                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
 344                                 rdev->irq.hpd[2] = false;
 345                                 break;
 346                         default:
 347                                 break;
 348                         }
 349                 }
 350         }
 351 }
 352
 353 /*
 354  * R600 PCIE GART
 355  */
 356 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
 357 {
 358         unsigned i;
 359         u32 tmp;
 360
 361         /* flush hdp cache so updates hit vram */
 362         WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
 363
 364         WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
 365         WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
 366         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
 367         for (i = 0; i < rdev->usec_timeout; i++) {
 368                 /* read MC_STATUS */
 369                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
 370                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
 371                 if (tmp == 2) {
 372                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
 373                         return;
 374                 }
 375                 if (tmp) {
 376                         return;
 377                 }
 378                 udelay(1);
 379         }
 380 }
 381
 382 int r600_pcie_gart_init(struct radeon_device *rdev)
 383 {
 384         int r;
 385
 386         if (rdev->gart.table.vram.robj) {
 387                 WARN(1, "R600 PCIE GART already initialized.\n");
 388                 return 0;
 389         }
 390         /* Initialize common gart structure */
 391         r = radeon_gart_init(rdev);
 392         if (r)
 393                 return r;
 394         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
 395         return radeon_gart_table_vram_alloc(rdev);
 396 }
 397
 398 int r600_pcie_gart_enable(struct radeon_device *rdev)
 399 {
 400         u32 tmp;
 401         int r, i;
 402
 403         if (rdev->gart.table.vram.robj == NULL) {
 404                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 405                 return -EINVAL;
 406         }
 407         r = radeon_gart_table_vram_pin(rdev);
 408         if (r)
 409                 return r;
 410         radeon_gart_restore(rdev);
 411
 412         /* Setup L2 cache */
 413         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 414                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 415                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 416         WREG32(VM_L2_CNTL2, 0);
 417         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 418         /* Setup TLB control */
 419         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 420                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 421                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 422                 ENABLE_WAIT_L2_QUERY;
 423         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 424         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 425         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
 426         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 427         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 428         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 429         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 430         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 431         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 432         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 433         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 434         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 435         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 436         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 437         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 438         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 439         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 440         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 441                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 442         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 443                         (u32)(rdev->dummy_page.addr >> 12));
 444         for (i = 1; i < 7; i++)
 445                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 446
 447         r600_pcie_gart_tlb_flush(rdev);
 448         rdev->gart.ready = true;
 449         return 0;
 450 }
 451
 452 void r600_pcie_gart_disable(struct radeon_device *rdev)
 453 {
 454         u32 tmp;
 455         int i, r;
 456
 457         /* Disable all tables */
 458         for (i = 0; i < 7; i++)
 459                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 460
 461         /* Disable L2 cache */
 462         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
 463                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 464         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 465         /* Setup L1 TLB control */
 466         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 467                 ENABLE_WAIT_L2_QUERY;
 468         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 469         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 470         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 471         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 472         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 473         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 474         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 475         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 476         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
 477         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
 478         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 479         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 480         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
 481         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 482         if (rdev->gart.table.vram.robj) {
 483                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
 484                 if (likely(r == 0)) {
 485                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
 486                         radeon_bo_unpin(rdev->gart.table.vram.robj);
 487                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
 488                 }
 489         }
 490 }
 491
 492 void r600_pcie_gart_fini(struct radeon_device *rdev)
 493 {
 494         r600_pcie_gart_disable(rdev);
 495         radeon_gart_table_vram_free(rdev);
 496         radeon_gart_fini(rdev);
 497 }
 498
 499 void r600_agp_enable(struct radeon_device *rdev)
 500 {
 501         u32 tmp;
 502         int i;
 503
 504         /* Setup L2 cache */
 505         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 506                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 507                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 508         WREG32(VM_L2_CNTL2, 0);
 509         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 510         /* Setup TLB control */
 511         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 512                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 513                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 514                 ENABLE_WAIT_L2_QUERY;
 515         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 516         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 517         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
 518         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 519         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 520         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 521         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 522         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 523         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 524         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 525         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 526         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 527         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 528         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 529         for (i = 0; i < 7; i++)
 530                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 531 }
 532
 533 int r600_mc_wait_for_idle(struct radeon_device *rdev)
 534 {
 535         unsigned i;
 536         u32 tmp;
 537
 538         for (i = 0; i < rdev->usec_timeout; i++) {
 539                 /* read MC_STATUS */
 540                 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
 541                 if (!tmp)
 542                         return 0;
 543                 udelay(1);
 544         }
 545         return -1;
 546 }
 547
 548 static void r600_mc_program(struct radeon_device *rdev)
 549 {
 550         struct rv515_mc_save save;
 551         u32 tmp;
 552         int i, j;
 553
 554         /* Initialize HDP */
 555         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
 556                 WREG32((0x2c14 + j), 0x00000000);
 557                 WREG32((0x2c18 + j), 0x00000000);
 558                 WREG32((0x2c1c + j), 0x00000000);
 559                 WREG32((0x2c20 + j), 0x00000000);
 560                 WREG32((0x2c24 + j), 0x00000000);
 561         }
 562         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
 563
 564         rv515_mc_stop(rdev, &save);
 565         if (r600_mc_wait_for_idle(rdev)) {
 566                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 567         }
 568         /* Lockout access through VGA aperture (doesn't exist before R600) */
 569         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
 570         /* Update configuration */
 571         if (rdev->flags & RADEON_IS_AGP) {
 572                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
 573                         /* VRAM before AGP */
 574                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 575                                 rdev->mc.vram_start >> 12);
 576                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 577                                 rdev->mc.gtt_end >> 12);
 578                 } else {
 579                         /* VRAM after AGP */
 580                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 581                                 rdev->mc.gtt_start >> 12);
 582                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 583                                 rdev->mc.vram_end >> 12);
 584                 }
 585         } else {
 586                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
 587                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
 588         }
 589         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
 590         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
 591         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
 592         WREG32(MC_VM_FB_LOCATION, tmp);
 593         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
 594         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
 595         WREG32(HDP_NONSURFACE_SIZE, rdev->mc.mc_vram_size | 0x3FF);
 596         if (rdev->flags & RADEON_IS_AGP) {
 597                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
 598                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
 599                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
 600         } else {
 601                 WREG32(MC_VM_AGP_BASE, 0);
 602                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
 603                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
 604         }
 605         if (r600_mc_wait_for_idle(rdev)) {
 606                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 607         }
 608         rv515_mc_resume(rdev, &save);
 609         /* we need to own VRAM, so turn off the VGA renderer here
 610          * to stop it overwriting our objects */
 611         rv515_vga_render_disable(rdev);
 612 }
 613
 614 /**
 615  * r600_vram_gtt_location - try to find VRAM & GTT location
 616  * @rdev: radeon device structure holding all necessary informations
 617  * @mc: memory controller structure holding memory informations
 618  *
 619  * Function will place try to place VRAM at same place as in CPU (PCI)
 620  * address space as some GPU seems to have issue when we reprogram at
 621  * different address space.
 622  *
 623  * If there is not enough space to fit the unvisible VRAM after the
 624  * aperture then we limit the VRAM size to the aperture.
 625  *
 626  * If we are using AGP then place VRAM adjacent to AGP aperture are we need
 627  * them to be in one from GPU point of view so that we can program GPU to
 628  * catch access outside them (weird GPU policy see ??).
 629  *
 630  * This function will never fails, worst case are limiting VRAM or GTT.
 631  *
 632  * Note: GTT start, end, size should be initialized before calling this
 633  * function on AGP platform.
 634  */
 635 void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
 636 {
 637         u64 size_bf, size_af;
 638
 639         if (mc->mc_vram_size > 0xE0000000) {
 640                 /* leave room for at least 512M GTT */
 641                 dev_warn(rdev->dev, "limiting VRAM\n");
 642                 mc->real_vram_size = 0xE0000000;
 643                 mc->mc_vram_size = 0xE0000000;
 644         }
 645         if (rdev->flags & RADEON_IS_AGP) {
 646                 size_bf = mc->gtt_start;
 647                 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
 648                 if (size_bf > size_af) {
 649                         if (mc->mc_vram_size > size_bf) {
 650                                 dev_warn(rdev->dev, "limiting VRAM\n");
 651                                 mc->real_vram_size = size_bf;
 652                                 mc->mc_vram_size = size_bf;
 653                         }
 654                         mc->vram_start = mc->gtt_start - mc->mc_vram_size;
 655                 } else {
 656                         if (mc->mc_vram_size > size_af) {
 657                                 dev_warn(rdev->dev, "limiting VRAM\n");
 658                                 mc->real_vram_size = size_af;
 659                                 mc->mc_vram_size = size_af;
 660                         }
 661                         mc->vram_start = mc->gtt_end;
 662                 }
 663                 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
 664                 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
 665                                 mc->mc_vram_size >> 20, mc->vram_start,
 666                                 mc->vram_end, mc->real_vram_size >> 20);
 667         } else {
 668                 u64 base = 0;
 669                 if (rdev->flags & RADEON_IS_IGP)
 670                         base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
 671                 radeon_vram_location(rdev, &rdev->mc, base);
 672                 radeon_gtt_location(rdev, mc);
 673         }
 674 }
 675
 676 int r600_mc_init(struct radeon_device *rdev)
 677 {
 678         fixed20_12 a;
 679         u32 tmp;
 680         int chansize, numchan;
 681
 682         /* Get VRAM informations */
 683         rdev->mc.vram_is_ddr = true;
 684         tmp = RREG32(RAMCFG);
 685         if (tmp & CHANSIZE_OVERRIDE) {
 686                 chansize = 16;
 687         } else if (tmp & CHANSIZE_MASK) {
 688                 chansize = 64;
 689         } else {
 690                 chansize = 32;
 691         }
 692         tmp = RREG32(CHMAP);
 693         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
 694         case 0:
 695         default:
 696                 numchan = 1;
 697                 break;
 698         case 1:
 699                 numchan = 2;
 700                 break;
 701         case 2:
 702                 numchan = 4;
 703                 break;
 704         case 3:
 705                 numchan = 8;
 706                 break;
 707         }
 708         rdev->mc.vram_width = numchan * chansize;
 709         /* Could aper size report 0 ? */
 710         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
 711         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
 712         /* Setup GPU memory space */
 713         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
 714         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
 715         /* FIXME remove this once we support unmappable VRAM */
 716         if (rdev->mc.mc_vram_size > rdev->mc.aper_size) {
 717                 rdev->mc.mc_vram_size = rdev->mc.aper_size;
 718                 rdev->mc.real_vram_size = rdev->mc.aper_size;
 719         }
 720         r600_vram_gtt_location(rdev, &rdev->mc);
 721         /* FIXME: we should enforce default clock in case GPU is not in
 722          * default setup
 723          */
 724         a.full = rfixed_const(100);
 725         rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
 726         rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
 727         if (rdev->flags & RADEON_IS_IGP)
 728                 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
 729         return 0;
 730 }
 731
 732 /* We doesn't check that the GPU really needs a reset we simply do the
 733  * reset, it's up to the caller to determine if the GPU needs one. We
 734  * might add an helper function to check that.
 735  */
 736 int r600_gpu_soft_reset(struct radeon_device *rdev)
 737 {
 738         struct rv515_mc_save save;
 739         u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
 740                                 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
 741                                 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
 742                                 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
 743                                 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
 744                                 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
 745                                 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
 746                                 S_008010_GUI_ACTIVE(1);
 747         u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
 748                         S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
 749                         S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
 750                         S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
 751                         S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
 752                         S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
 753                         S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
 754                         S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
 755         u32 srbm_reset = 0;
 756         u32 tmp;
 757
 758         dev_info(rdev->dev, "GPU softreset \n");
 759         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
 760                 RREG32(R_008010_GRBM_STATUS));
 761         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
 762                 RREG32(R_008014_GRBM_STATUS2));
 763         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
 764                 RREG32(R_000E50_SRBM_STATUS));
 765         rv515_mc_stop(rdev, &save);
 766         if (r600_mc_wait_for_idle(rdev)) {
 767                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 768         }
 769         /* Disable CP parsing/prefetching */
 770         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(0xff));
 771         /* Check if any of the rendering block is busy and reset it */
 772         if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
 773             (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
 774                 tmp = S_008020_SOFT_RESET_CR(1) |
 775                         S_008020_SOFT_RESET_DB(1) |
 776                         S_008020_SOFT_RESET_CB(1) |
 777                         S_008020_SOFT_RESET_PA(1) |
 778                         S_008020_SOFT_RESET_SC(1) |
 779                         S_008020_SOFT_RESET_SMX(1) |
 780                         S_008020_SOFT_RESET_SPI(1) |
 781                         S_008020_SOFT_RESET_SX(1) |
 782                         S_008020_SOFT_RESET_SH(1) |
 783                         S_008020_SOFT_RESET_TC(1) |
 784                         S_008020_SOFT_RESET_TA(1) |
 785                         S_008020_SOFT_RESET_VC(1) |
 786                         S_008020_SOFT_RESET_VGT(1);
 787                 dev_info(rdev->dev, "  R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
 788                 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
 789                 (void)RREG32(R_008020_GRBM_SOFT_RESET);
 790                 udelay(50);
 791                 WREG32(R_008020_GRBM_SOFT_RESET, 0);
 792                 (void)RREG32(R_008020_GRBM_SOFT_RESET);
 793         }
 794         /* Reset CP (we always reset CP) */
 795         tmp = S_008020_SOFT_RESET_CP(1);
 796         dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
 797         WREG32(R_008020_GRBM_SOFT_RESET, tmp);
 798         (void)RREG32(R_008020_GRBM_SOFT_RESET);
 799         udelay(50);
 800         WREG32(R_008020_GRBM_SOFT_RESET, 0);
 801         (void)RREG32(R_008020_GRBM_SOFT_RESET);
 802         /* Reset others GPU block if necessary */
 803         if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 804                 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
 805         if (G_000E50_GRBM_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
 806                 srbm_reset |= S_000E60_SOFT_RESET_GRBM(1);
 807         if (G_000E50_HI_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
 808                 srbm_reset |= S_000E60_SOFT_RESET_IH(1);
 809         if (G_000E50_VMC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 810                 srbm_reset |= S_000E60_SOFT_RESET_VMC(1);
 811         if (G_000E50_MCB_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 812                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 813         if (G_000E50_MCDZ_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 814                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 815         if (G_000E50_MCDY_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 816                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 817         if (G_000E50_MCDX_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 818                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 819         if (G_000E50_MCDW_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 820                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 821         if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 822                 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
 823         if (G_000E50_SEM_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 824                 srbm_reset |= S_000E60_SOFT_RESET_SEM(1);
 825         if (G_000E50_BIF_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 826                 srbm_reset |= S_000E60_SOFT_RESET_BIF(1);
 827         dev_info(rdev->dev, "  R_000E60_SRBM_SOFT_RESET=0x%08X\n", srbm_reset);
 828         WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
 829         (void)RREG32(R_000E60_SRBM_SOFT_RESET);
 830         udelay(50);
 831         WREG32(R_000E60_SRBM_SOFT_RESET, 0);
 832         (void)RREG32(R_000E60_SRBM_SOFT_RESET);
 833         WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
 834         (void)RREG32(R_000E60_SRBM_SOFT_RESET);
 835         udelay(50);
 836         WREG32(R_000E60_SRBM_SOFT_RESET, 0);
 837         (void)RREG32(R_000E60_SRBM_SOFT_RESET);
 838         /* Wait a little for things to settle down */
 839         udelay(50);
 840         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
 841                 RREG32(R_008010_GRBM_STATUS));
 842         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
 843                 RREG32(R_008014_GRBM_STATUS2));
 844         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
 845                 RREG32(R_000E50_SRBM_STATUS));
 846         /* After reset we need to reinit the asic as GPU often endup in an
 847          * incoherent state.
 848          */
 849         atom_asic_init(rdev->mode_info.atom_context);
 850         rv515_mc_resume(rdev, &save);
 851         return 0;
 852 }
 853
 854 int r600_gpu_reset(struct radeon_device *rdev)
 855 {
 856         return r600_gpu_soft_reset(rdev);
 857 }
 858
 859 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
 860                                              u32 num_backends,
 861                                              u32 backend_disable_mask)
 862 {
 863         u32 backend_map = 0;
 864         u32 enabled_backends_mask;
 865         u32 enabled_backends_count;
 866         u32 cur_pipe;
 867         u32 swizzle_pipe[R6XX_MAX_PIPES];
 868         u32 cur_backend;
 869         u32 i;
 870
 871         if (num_tile_pipes > R6XX_MAX_PIPES)
 872                 num_tile_pipes = R6XX_MAX_PIPES;
 873         if (num_tile_pipes < 1)
 874                 num_tile_pipes = 1;
 875         if (num_backends > R6XX_MAX_BACKENDS)
 876                 num_backends = R6XX_MAX_BACKENDS;
 877         if (num_backends < 1)
 878                 num_backends = 1;
 879
 880         enabled_backends_mask = 0;
 881         enabled_backends_count = 0;
 882         for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
 883                 if (((backend_disable_mask >> i) & 1) == 0) {
 884                         enabled_backends_mask |= (1 << i);
 885                         ++enabled_backends_count;
 886                 }
 887                 if (enabled_backends_count == num_backends)
 888                         break;
 889         }
 890
 891         if (enabled_backends_count == 0) {
 892                 enabled_backends_mask = 1;
 893                 enabled_backends_count = 1;
 894         }
 895
 896         if (enabled_backends_count != num_backends)
 897                 num_backends = enabled_backends_count;
 898
 899         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
 900         switch (num_tile_pipes) {
 901         case 1:
 902                 swizzle_pipe[0] = 0;
 903                 break;
 904         case 2:
 905                 swizzle_pipe[0] = 0;
 906                 swizzle_pipe[1] = 1;
 907                 break;
 908         case 3:
 909                 swizzle_pipe[0] = 0;
 910                 swizzle_pipe[1] = 1;
 911                 swizzle_pipe[2] = 2;
 912                 break;
 913         case 4:
 914                 swizzle_pipe[0] = 0;
 915                 swizzle_pipe[1] = 1;
 916                 swizzle_pipe[2] = 2;
 917                 swizzle_pipe[3] = 3;
 918                 break;
 919         case 5:
 920                 swizzle_pipe[0] = 0;
 921                 swizzle_pipe[1] = 1;
 922                 swizzle_pipe[2] = 2;
 923                 swizzle_pipe[3] = 3;
 924                 swizzle_pipe[4] = 4;
 925                 break;
 926         case 6:
 927                 swizzle_pipe[0] = 0;
 928                 swizzle_pipe[1] = 2;
 929                 swizzle_pipe[2] = 4;
 930                 swizzle_pipe[3] = 5;
 931                 swizzle_pipe[4] = 1;
 932                 swizzle_pipe[5] = 3;
 933                 break;
 934         case 7:
 935                 swizzle_pipe[0] = 0;
 936                 swizzle_pipe[1] = 2;
 937                 swizzle_pipe[2] = 4;
 938                 swizzle_pipe[3] = 6;
 939                 swizzle_pipe[4] = 1;
 940                 swizzle_pipe[5] = 3;
 941                 swizzle_pipe[6] = 5;
 942                 break;
 943         case 8:
 944                 swizzle_pipe[0] = 0;
 945                 swizzle_pipe[1] = 2;
 946                 swizzle_pipe[2] = 4;
 947                 swizzle_pipe[3] = 6;
 948                 swizzle_pipe[4] = 1;
 949                 swizzle_pipe[5] = 3;
 950                 swizzle_pipe[6] = 5;
 951                 swizzle_pipe[7] = 7;
 952                 break;
 953         }
 954
 955         cur_backend = 0;
 956         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
 957                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
 958                         cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
 959
 960                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
 961
 962                 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
 963         }
 964
 965         return backend_map;
 966 }
 967
 968 int r600_count_pipe_bits(uint32_t val)
 969 {
 970         int i, ret = 0;
 971
 972         for (i = 0; i < 32; i++) {
 973                 ret += val & 1;
 974                 val >>= 1;
 975         }
 976         return ret;
 977 }
 978
 979 void r600_gpu_init(struct radeon_device *rdev)
 980 {
 981         u32 tiling_config;
 982         u32 ramcfg;
 983         u32 backend_map;
 984         u32 cc_rb_backend_disable;
 985         u32 cc_gc_shader_pipe_config;
 986         u32 tmp;
 987         int i, j;
 988         u32 sq_config;
 989         u32 sq_gpr_resource_mgmt_1 = 0;
 990         u32 sq_gpr_resource_mgmt_2 = 0;
 991         u32 sq_thread_resource_mgmt = 0;
 992         u32 sq_stack_resource_mgmt_1 = 0;
 993         u32 sq_stack_resource_mgmt_2 = 0;
 994
 995         /* FIXME: implement */
 996         switch (rdev->family) {
 997         case CHIP_R600:
 998                 rdev->config.r600.max_pipes = 4;
 999                 rdev->config.r600.max_tile_pipes = 8;
1000                 rdev->config.r600.max_simds = 4;
1001                 rdev->config.r600.max_backends = 4;
1002                 rdev->config.r600.max_gprs = 256;
1003                 rdev->config.r600.max_threads = 192;
1004                 rdev->config.r600.max_stack_entries = 256;
1005                 rdev->config.r600.max_hw_contexts = 8;
1006                 rdev->config.r600.max_gs_threads = 16;
1007                 rdev->config.r600.sx_max_export_size = 128;
1008                 rdev->config.r600.sx_max_export_pos_size = 16;
1009                 rdev->config.r600.sx_max_export_smx_size = 128;
1010                 rdev->config.r600.sq_num_cf_insts = 2;
1011                 break;
1012         case CHIP_RV630:
1013         case CHIP_RV635:
1014                 rdev->config.r600.max_pipes = 2;
1015                 rdev->config.r600.max_tile_pipes = 2;
1016                 rdev->config.r600.max_simds = 3;
1017                 rdev->config.r600.max_backends = 1;
1018                 rdev->config.r600.max_gprs = 128;
1019                 rdev->config.r600.max_threads = 192;
1020                 rdev->config.r600.max_stack_entries = 128;
1021                 rdev->config.r600.max_hw_contexts = 8;
1022                 rdev->config.r600.max_gs_threads = 4;
1023                 rdev->config.r600.sx_max_export_size = 128;
1024                 rdev->config.r600.sx_max_export_pos_size = 16;
1025                 rdev->config.r600.sx_max_export_smx_size = 128;
1026                 rdev->config.r600.sq_num_cf_insts = 2;
1027                 break;
1028         case CHIP_RV610:
1029         case CHIP_RV620:
1030         case CHIP_RS780:
1031         case CHIP_RS880:
1032                 rdev->config.r600.max_pipes = 1;
1033                 rdev->config.r600.max_tile_pipes = 1;
1034                 rdev->config.r600.max_simds = 2;
1035                 rdev->config.r600.max_backends = 1;
1036                 rdev->config.r600.max_gprs = 128;
1037                 rdev->config.r600.max_threads = 192;
1038                 rdev->config.r600.max_stack_entries = 128;
1039                 rdev->config.r600.max_hw_contexts = 4;
1040                 rdev->config.r600.max_gs_threads = 4;
1041                 rdev->config.r600.sx_max_export_size = 128;
1042                 rdev->config.r600.sx_max_export_pos_size = 16;
1043                 rdev->config.r600.sx_max_export_smx_size = 128;
1044                 rdev->config.r600.sq_num_cf_insts = 1;
1045                 break;
1046         case CHIP_RV670:
1047                 rdev->config.r600.max_pipes = 4;
1048                 rdev->config.r600.max_tile_pipes = 4;
1049                 rdev->config.r600.max_simds = 4;
1050                 rdev->config.r600.max_backends = 4;
1051                 rdev->config.r600.max_gprs = 192;
1052                 rdev->config.r600.max_threads = 192;
1053                 rdev->config.r600.max_stack_entries = 256;
1054                 rdev->config.r600.max_hw_contexts = 8;
1055                 rdev->config.r600.max_gs_threads = 16;
1056                 rdev->config.r600.sx_max_export_size = 128;
1057                 rdev->config.r600.sx_max_export_pos_size = 16;
1058                 rdev->config.r600.sx_max_export_smx_size = 128;
1059                 rdev->config.r600.sq_num_cf_insts = 2;
1060                 break;
1061         default:
1062                 break;
1063         }
1064
1065         /* Initialize HDP */
1066         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1067                 WREG32((0x2c14 + j), 0x00000000);
1068                 WREG32((0x2c18 + j), 0x00000000);
1069                 WREG32((0x2c1c + j), 0x00000000);
1070                 WREG32((0x2c20 + j), 0x00000000);
1071                 WREG32((0x2c24 + j), 0x00000000);
1072         }
1073
1074         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1075
1076         /* Setup tiling */
1077         tiling_config = 0;
1078         ramcfg = RREG32(RAMCFG);
1079         switch (rdev->config.r600.max_tile_pipes) {
1080         case 1:
1081                 tiling_config |= PIPE_TILING(0);
1082                 break;
1083         case 2:
1084                 tiling_config |= PIPE_TILING(1);
1085                 break;
1086         case 4:
1087                 tiling_config |= PIPE_TILING(2);
1088                 break;
1089         case 8:
1090                 tiling_config |= PIPE_TILING(3);
1091                 break;
1092         default:
1093                 break;
1094         }
1095         rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
1096         rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1097         tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1098         tiling_config |= GROUP_SIZE(0);
1099         rdev->config.r600.tiling_group_size = 256;
1100         tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1101         if (tmp > 3) {
1102                 tiling_config |= ROW_TILING(3);
1103                 tiling_config |= SAMPLE_SPLIT(3);
1104         } else {
1105                 tiling_config |= ROW_TILING(tmp);
1106                 tiling_config |= SAMPLE_SPLIT(tmp);
1107         }
1108         tiling_config |= BANK_SWAPS(1);
1109
1110         cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1111         cc_rb_backend_disable |=
1112                 BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1113
1114         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1115         cc_gc_shader_pipe_config |=
1116                 INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1117         cc_gc_shader_pipe_config |=
1118                 INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1119
1120         backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1121                                                         (R6XX_MAX_BACKENDS -
1122                                                          r600_count_pipe_bits((cc_rb_backend_disable &
1123                                                                                R6XX_MAX_BACKENDS_MASK) >> 16)),
1124                                                         (cc_rb_backend_disable >> 16));
1125
1126         tiling_config |= BACKEND_MAP(backend_map);
1127         WREG32(GB_TILING_CONFIG, tiling_config);
1128         WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1129         WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1130
1131         /* Setup pipes */
1132         WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1133         WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1134
1135         tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1136         WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1137         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1138
1139         /* Setup some CP states */
1140         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1141         WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1142
1143         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1144                              SYNC_WALKER | SYNC_ALIGNER));
1145         /* Setup various GPU states */
1146         if (rdev->family == CHIP_RV670)
1147                 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1148
1149         tmp = RREG32(SX_DEBUG_1);
1150         tmp |= SMX_EVENT_RELEASE;
1151         if ((rdev->family > CHIP_R600))
1152                 tmp |= ENABLE_NEW_SMX_ADDRESS;
1153         WREG32(SX_DEBUG_1, tmp);
1154
1155         if (((rdev->family) == CHIP_R600) ||
1156             ((rdev->family) == CHIP_RV630) ||
1157             ((rdev->family) == CHIP_RV610) ||
1158             ((rdev->family) == CHIP_RV620) ||
1159             ((rdev->family) == CHIP_RS780) ||
1160             ((rdev->family) == CHIP_RS880)) {
1161                 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1162         } else {
1163                 WREG32(DB_DEBUG, 0);
1164         }
1165         WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1166                                DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1167
1168         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1169         WREG32(VGT_NUM_INSTANCES, 0);
1170
1171         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1172         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1173
1174         tmp = RREG32(SQ_MS_FIFO_SIZES);
1175         if (((rdev->family) == CHIP_RV610) ||
1176             ((rdev->family) == CHIP_RV620) ||
1177             ((rdev->family) == CHIP_RS780) ||
1178             ((rdev->family) == CHIP_RS880)) {
1179                 tmp = (CACHE_FIFO_SIZE(0xa) |
1180                        FETCH_FIFO_HIWATER(0xa) |
1181                        DONE_FIFO_HIWATER(0xe0) |
1182                        ALU_UPDATE_FIFO_HIWATER(0x8));
1183         } else if (((rdev->family) == CHIP_R600) ||
1184                    ((rdev->family) == CHIP_RV630)) {
1185                 tmp &= ~DONE_FIFO_HIWATER(0xff);
1186                 tmp |= DONE_FIFO_HIWATER(0x4);
1187         }
1188         WREG32(SQ_MS_FIFO_SIZES, tmp);
1189
1190         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1191          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
1192          */
1193         sq_config = RREG32(SQ_CONFIG);
1194         sq_config &= ~(PS_PRIO(3) |
1195                        VS_PRIO(3) |
1196                        GS_PRIO(3) |
1197                        ES_PRIO(3));
1198         sq_config |= (DX9_CONSTS |
1199                       VC_ENABLE |
1200                       PS_PRIO(0) |
1201                       VS_PRIO(1) |
1202                       GS_PRIO(2) |
1203                       ES_PRIO(3));
1204
1205         if ((rdev->family) == CHIP_R600) {
1206                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1207                                           NUM_VS_GPRS(124) |
1208                                           NUM_CLAUSE_TEMP_GPRS(4));
1209                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1210                                           NUM_ES_GPRS(0));
1211                 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1212                                            NUM_VS_THREADS(48) |
1213                                            NUM_GS_THREADS(4) |
1214                                            NUM_ES_THREADS(4));
1215                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1216                                             NUM_VS_STACK_ENTRIES(128));
1217                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1218                                             NUM_ES_STACK_ENTRIES(0));
1219         } else if (((rdev->family) == CHIP_RV610) ||
1220                    ((rdev->family) == CHIP_RV620) ||
1221                    ((rdev->family) == CHIP_RS780) ||
1222                    ((rdev->family) == CHIP_RS880)) {
1223                 /* no vertex cache */
1224                 sq_config &= ~VC_ENABLE;
1225
1226                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1227                                           NUM_VS_GPRS(44) |
1228                                           NUM_CLAUSE_TEMP_GPRS(2));
1229                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1230                                           NUM_ES_GPRS(17));
1231                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1232                                            NUM_VS_THREADS(78) |
1233                                            NUM_GS_THREADS(4) |
1234                                            NUM_ES_THREADS(31));
1235                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1236                                             NUM_VS_STACK_ENTRIES(40));
1237                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1238                                             NUM_ES_STACK_ENTRIES(16));
1239         } else if (((rdev->family) == CHIP_RV630) ||
1240                    ((rdev->family) == CHIP_RV635)) {
1241                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1242                                           NUM_VS_GPRS(44) |
1243                                           NUM_CLAUSE_TEMP_GPRS(2));
1244                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1245                                           NUM_ES_GPRS(18));
1246                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1247                                            NUM_VS_THREADS(78) |
1248                                            NUM_GS_THREADS(4) |
1249                                            NUM_ES_THREADS(31));
1250                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1251                                             NUM_VS_STACK_ENTRIES(40));
1252                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1253                                             NUM_ES_STACK_ENTRIES(16));
1254         } else if ((rdev->family) == CHIP_RV670) {
1255                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1256                                           NUM_VS_GPRS(44) |
1257                                           NUM_CLAUSE_TEMP_GPRS(2));
1258                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1259                                           NUM_ES_GPRS(17));
1260                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1261                                            NUM_VS_THREADS(78) |
1262                                            NUM_GS_THREADS(4) |
1263                                            NUM_ES_THREADS(31));
1264                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1265                                             NUM_VS_STACK_ENTRIES(64));
1266                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1267                                             NUM_ES_STACK_ENTRIES(64));
1268         }
1269
1270         WREG32(SQ_CONFIG, sq_config);
1271         WREG32(SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
1272         WREG32(SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
1273         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1274         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1275         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1276
1277         if (((rdev->family) == CHIP_RV610) ||
1278             ((rdev->family) == CHIP_RV620) ||
1279             ((rdev->family) == CHIP_RS780) ||
1280             ((rdev->family) == CHIP_RS880)) {
1281                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1282         } else {
1283                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1284         }
1285
1286         /* More default values. 2D/3D driver should adjust as needed */
1287         WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1288                                          S1_X(0x4) | S1_Y(0xc)));
1289         WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1290                                          S1_X(0x2) | S1_Y(0x2) |
1291                                          S2_X(0xa) | S2_Y(0x6) |
1292                                          S3_X(0x6) | S3_Y(0xa)));
1293         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1294                                              S1_X(0x4) | S1_Y(0xc) |
1295                                              S2_X(0x1) | S2_Y(0x6) |
1296                                              S3_X(0xa) | S3_Y(0xe)));
1297         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1298                                              S5_X(0x0) | S5_Y(0x0) |
1299                                              S6_X(0xb) | S6_Y(0x4) |
1300                                              S7_X(0x7) | S7_Y(0x8)));
1301
1302         WREG32(VGT_STRMOUT_EN, 0);
1303         tmp = rdev->config.r600.max_pipes * 16;
1304         switch (rdev->family) {
1305         case CHIP_RV610:
1306         case CHIP_RV620:
1307         case CHIP_RS780:
1308         case CHIP_RS880:
1309                 tmp += 32;
1310                 break;
1311         case CHIP_RV670:
1312                 tmp += 128;
1313                 break;
1314         default:
1315                 break;
1316         }
1317         if (tmp > 256) {
1318                 tmp = 256;
1319         }
1320         WREG32(VGT_ES_PER_GS, 128);
1321         WREG32(VGT_GS_PER_ES, tmp);
1322         WREG32(VGT_GS_PER_VS, 2);
1323         WREG32(VGT_GS_VERTEX_REUSE, 16);
1324
1325         /* more default values. 2D/3D driver should adjust as needed */
1326         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1327         WREG32(VGT_STRMOUT_EN, 0);
1328         WREG32(SX_MISC, 0);
1329         WREG32(PA_SC_MODE_CNTL, 0);
1330         WREG32(PA_SC_AA_CONFIG, 0);
1331         WREG32(PA_SC_LINE_STIPPLE, 0);
1332         WREG32(SPI_INPUT_Z, 0);
1333         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1334         WREG32(CB_COLOR7_FRAG, 0);
1335
1336         /* Clear render buffer base addresses */
1337         WREG32(CB_COLOR0_BASE, 0);
1338         WREG32(CB_COLOR1_BASE, 0);
1339         WREG32(CB_COLOR2_BASE, 0);
1340         WREG32(CB_COLOR3_BASE, 0);
1341         WREG32(CB_COLOR4_BASE, 0);
1342         WREG32(CB_COLOR5_BASE, 0);
1343         WREG32(CB_COLOR6_BASE, 0);
1344         WREG32(CB_COLOR7_BASE, 0);
1345         WREG32(CB_COLOR7_FRAG, 0);
1346
1347         switch (rdev->family) {
1348         case CHIP_RV610:
1349         case CHIP_RV620:
1350         case CHIP_RS780:
1351         case CHIP_RS880:
1352                 tmp = TC_L2_SIZE(8);
1353                 break;
1354         case CHIP_RV630:
1355         case CHIP_RV635:
1356                 tmp = TC_L2_SIZE(4);
1357                 break;
1358         case CHIP_R600:
1359                 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1360                 break;
1361         default:
1362                 tmp = TC_L2_SIZE(0);
1363                 break;
1364         }
1365         WREG32(TC_CNTL, tmp);
1366
1367         tmp = RREG32(HDP_HOST_PATH_CNTL);
1368         WREG32(HDP_HOST_PATH_CNTL, tmp);
1369
1370         tmp = RREG32(ARB_POP);
1371         tmp |= ENABLE_TC128;
1372         WREG32(ARB_POP, tmp);
1373
1374         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1375         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1376                                NUM_CLIP_SEQ(3)));
1377         WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1378 }
1379
1380
1381 /*
1382  * Indirect registers accessor
1383  */
1384 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1385 {
1386         u32 r;
1387
1388         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1389         (void)RREG32(PCIE_PORT_INDEX);
1390         r = RREG32(PCIE_PORT_DATA);
1391         return r;
1392 }
1393
1394 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1395 {
1396         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1397         (void)RREG32(PCIE_PORT_INDEX);
1398         WREG32(PCIE_PORT_DATA, (v));
1399         (void)RREG32(PCIE_PORT_DATA);
1400 }
1401
1402 /*
1403  * CP & Ring
1404  */
1405 void r600_cp_stop(struct radeon_device *rdev)
1406 {
1407         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1408 }
1409
1410 int r600_init_microcode(struct radeon_device *rdev)
1411 {
1412         struct platform_device *pdev;
1413         const char *chip_name;
1414         const char *rlc_chip_name;
1415         size_t pfp_req_size, me_req_size, rlc_req_size;
1416         char fw_name[30];
1417         int err;
1418
1419         DRM_DEBUG("\n");
1420
1421         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1422         err = IS_ERR(pdev);
1423         if (err) {
1424                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1425                 return -EINVAL;
1426         }
1427
1428         switch (rdev->family) {
1429         case CHIP_R600:
1430                 chip_name = "R600";
1431                 rlc_chip_name = "R600";
1432                 break;
1433         case CHIP_RV610:
1434                 chip_name = "RV610";
1435                 rlc_chip_name = "R600";
1436                 break;
1437         case CHIP_RV630:
1438                 chip_name = "RV630";
1439                 rlc_chip_name = "R600";
1440                 break;
1441         case CHIP_RV620:
1442                 chip_name = "RV620";
1443                 rlc_chip_name = "R600";
1444                 break;
1445         case CHIP_RV635:
1446                 chip_name = "RV635";
1447                 rlc_chip_name = "R600";
1448                 break;
1449         case CHIP_RV670:
1450                 chip_name = "RV670";
1451                 rlc_chip_name = "R600";
1452                 break;
1453         case CHIP_RS780:
1454         case CHIP_RS880:
1455                 chip_name = "RS780";
1456                 rlc_chip_name = "R600";
1457                 break;
1458         case CHIP_RV770:
1459                 chip_name = "RV770";
1460                 rlc_chip_name = "R700";
1461                 break;
1462         case CHIP_RV730:
1463         case CHIP_RV740:
1464                 chip_name = "RV730";
1465                 rlc_chip_name = "R700";
1466                 break;
1467         case CHIP_RV710:
1468                 chip_name = "RV710";
1469                 rlc_chip_name = "R700";
1470                 break;
1471         default: BUG();
1472         }
1473
1474         if (rdev->family >= CHIP_RV770) {
1475                 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
1476                 me_req_size = R700_PM4_UCODE_SIZE * 4;
1477                 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
1478         } else {
1479                 pfp_req_size = PFP_UCODE_SIZE * 4;
1480                 me_req_size = PM4_UCODE_SIZE * 12;
1481                 rlc_req_size = RLC_UCODE_SIZE * 4;
1482         }
1483
1484         DRM_INFO("Loading %s Microcode\n", chip_name);
1485
1486         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
1487         err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
1488         if (err)
1489                 goto out;
1490         if (rdev->pfp_fw->size != pfp_req_size) {
1491                 printk(KERN_ERR
1492                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1493                        rdev->pfp_fw->size, fw_name);
1494                 err = -EINVAL;
1495                 goto out;
1496         }
1497
1498         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
1499         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
1500         if (err)
1501                 goto out;
1502         if (rdev->me_fw->size != me_req_size) {
1503                 printk(KERN_ERR
1504                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1505                        rdev->me_fw->size, fw_name);
1506                 err = -EINVAL;
1507         }
1508
1509         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
1510         err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
1511         if (err)
1512                 goto out;
1513         if (rdev->rlc_fw->size != rlc_req_size) {
1514                 printk(KERN_ERR
1515                        "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
1516                        rdev->rlc_fw->size, fw_name);
1517                 err = -EINVAL;
1518         }
1519
1520 out:
1521         platform_device_unregister(pdev);
1522
1523         if (err) {
1524                 if (err != -EINVAL)
1525                         printk(KERN_ERR
1526                                "r600_cp: Failed to load firmware \"%s\"\n",
1527                                fw_name);
1528                 release_firmware(rdev->pfp_fw);
1529                 rdev->pfp_fw = NULL;
1530                 release_firmware(rdev->me_fw);
1531                 rdev->me_fw = NULL;
1532                 release_firmware(rdev->rlc_fw);
1533                 rdev->rlc_fw = NULL;
1534         }
1535         return err;
1536 }
1537
1538 static int r600_cp_load_microcode(struct radeon_device *rdev)
1539 {
1540         const __be32 *fw_data;
1541         int i;
1542
1543         if (!rdev->me_fw || !rdev->pfp_fw)
1544                 return -EINVAL;
1545
1546         r600_cp_stop(rdev);
1547
1548         WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1549
1550         /* Reset cp */
1551         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1552         RREG32(GRBM_SOFT_RESET);
1553         mdelay(15);
1554         WREG32(GRBM_SOFT_RESET, 0);
1555
1556         WREG32(CP_ME_RAM_WADDR, 0);
1557
1558         fw_data = (const __be32 *)rdev->me_fw->data;
1559         WREG32(CP_ME_RAM_WADDR, 0);
1560         for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
1561                 WREG32(CP_ME_RAM_DATA,
1562                        be32_to_cpup(fw_data++));
1563
1564         fw_data = (const __be32 *)rdev->pfp_fw->data;
1565         WREG32(CP_PFP_UCODE_ADDR, 0);
1566         for (i = 0; i < PFP_UCODE_SIZE; i++)
1567                 WREG32(CP_PFP_UCODE_DATA,
1568                        be32_to_cpup(fw_data++));
1569
1570         WREG32(CP_PFP_UCODE_ADDR, 0);
1571         WREG32(CP_ME_RAM_WADDR, 0);
1572         WREG32(CP_ME_RAM_RADDR, 0);
1573         return 0;
1574 }
1575
1576 int r600_cp_start(struct radeon_device *rdev)
1577 {
1578         int r;
1579         uint32_t cp_me;
1580
1581         r = radeon_ring_lock(rdev, 7);
1582         if (r) {
1583                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1584                 return r;
1585         }
1586         radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1587         radeon_ring_write(rdev, 0x1);
1588         if (rdev->family < CHIP_RV770) {
1589                 radeon_ring_write(rdev, 0x3);
1590                 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
1591         } else {
1592                 radeon_ring_write(rdev, 0x0);
1593                 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
1594         }
1595         radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1596         radeon_ring_write(rdev, 0);
1597         radeon_ring_write(rdev, 0);
1598         radeon_ring_unlock_commit(rdev);
1599
1600         cp_me = 0xff;
1601         WREG32(R_0086D8_CP_ME_CNTL, cp_me);
1602         return 0;
1603 }
1604
1605 int r600_cp_resume(struct radeon_device *rdev)
1606 {
1607         u32 tmp;
1608         u32 rb_bufsz;
1609         int r;
1610
1611         /* Reset cp */
1612         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1613         RREG32(GRBM_SOFT_RESET);
1614         mdelay(15);
1615         WREG32(GRBM_SOFT_RESET, 0);
1616
1617         /* Set ring buffer size */
1618         rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1619         tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1620 #ifdef __BIG_ENDIAN
1621         tmp |= BUF_SWAP_32BIT;
1622 #endif
1623         WREG32(CP_RB_CNTL, tmp);
1624         WREG32(CP_SEM_WAIT_TIMER, 0x4);
1625
1626         /* Set the write pointer delay */
1627         WREG32(CP_RB_WPTR_DELAY, 0);
1628
1629         /* Initialize the ring buffer's read and write pointers */
1630         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1631         WREG32(CP_RB_RPTR_WR, 0);
1632         WREG32(CP_RB_WPTR, 0);
1633         WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
1634         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
1635         mdelay(1);
1636         WREG32(CP_RB_CNTL, tmp);
1637
1638         WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1639         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1640
1641         rdev->cp.rptr = RREG32(CP_RB_RPTR);
1642         rdev->cp.wptr = RREG32(CP_RB_WPTR);
1643
1644         r600_cp_start(rdev);
1645         rdev->cp.ready = true;
1646         r = radeon_ring_test(rdev);
1647         if (r) {
1648                 rdev->cp.ready = false;
1649                 return r;
1650         }
1651         return 0;
1652 }
1653
1654 void r600_cp_commit(struct radeon_device *rdev)
1655 {
1656         WREG32(CP_RB_WPTR, rdev->cp.wptr);
1657         (void)RREG32(CP_RB_WPTR);
1658 }
1659
1660 void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
1661 {
1662         u32 rb_bufsz;
1663
1664         /* Align ring size */
1665         rb_bufsz = drm_order(ring_size / 8);
1666         ring_size = (1 << (rb_bufsz + 1)) * 4;
1667         rdev->cp.ring_size = ring_size;
1668         rdev->cp.align_mask = 16 - 1;
1669 }
1670
1671 void r600_cp_fini(struct radeon_device *rdev)
1672 {
1673         r600_cp_stop(rdev);
1674         radeon_ring_fini(rdev);
1675 }
1676
1677
1678 /*
1679  * GPU scratch registers helpers function.
1680  */
1681 void r600_scratch_init(struct radeon_device *rdev)
1682 {
1683         int i;
1684
1685         rdev->scratch.num_reg = 7;
1686         for (i = 0; i < rdev->scratch.num_reg; i++) {
1687                 rdev->scratch.free[i] = true;
1688                 rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4);
1689         }
1690 }
1691
1692 int r600_ring_test(struct radeon_device *rdev)
1693 {
1694         uint32_t scratch;
1695         uint32_t tmp = 0;
1696         unsigned i;
1697         int r;
1698
1699         r = radeon_scratch_get(rdev, &scratch);
1700         if (r) {
1701                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
1702                 return r;
1703         }
1704         WREG32(scratch, 0xCAFEDEAD);
1705         r = radeon_ring_lock(rdev, 3);
1706         if (r) {
1707                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1708                 radeon_scratch_free(rdev, scratch);
1709                 return r;
1710         }
1711         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1712         radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1713         radeon_ring_write(rdev, 0xDEADBEEF);
1714         radeon_ring_unlock_commit(rdev);
1715         for (i = 0; i < rdev->usec_timeout; i++) {
1716                 tmp = RREG32(scratch);
1717                 if (tmp == 0xDEADBEEF)
1718                         break;
1719                 DRM_UDELAY(1);
1720         }
1721         if (i < rdev->usec_timeout) {
1722                 DRM_INFO("ring test succeeded in %d usecs\n", i);
1723         } else {
1724                 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
1725                           scratch, tmp);
1726                 r = -EINVAL;
1727         }
1728         radeon_scratch_free(rdev, scratch);
1729         return r;
1730 }
1731
1732 void r600_wb_disable(struct radeon_device *rdev)
1733 {
1734         int r;
1735
1736         WREG32(SCRATCH_UMSK, 0);
1737         if (rdev->wb.wb_obj) {
1738                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
1739                 if (unlikely(r != 0))
1740                         return;
1741                 radeon_bo_kunmap(rdev->wb.wb_obj);
1742                 radeon_bo_unpin(rdev->wb.wb_obj);
1743                 radeon_bo_unreserve(rdev->wb.wb_obj);
1744         }
1745 }
1746
1747 void r600_wb_fini(struct radeon_device *rdev)
1748 {
1749         r600_wb_disable(rdev);
1750         if (rdev->wb.wb_obj) {
1751                 radeon_bo_unref(&rdev->wb.wb_obj);
1752                 rdev->wb.wb = NULL;
1753                 rdev->wb.wb_obj = NULL;
1754         }
1755 }
1756
1757 int r600_wb_enable(struct radeon_device *rdev)
1758 {
1759         int r;
1760
1761         if (rdev->wb.wb_obj == NULL) {
1762                 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
1763                                 RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj);
1764                 if (r) {
1765                         dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
1766                         return r;
1767                 }
1768                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
1769                 if (unlikely(r != 0)) {
1770                         r600_wb_fini(rdev);
1771                         return r;
1772                 }
1773                 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
1774                                 &rdev->wb.gpu_addr);
1775                 if (r) {
1776                         radeon_bo_unreserve(rdev->wb.wb_obj);
1777                         dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
1778                         r600_wb_fini(rdev);
1779                         return r;
1780                 }
1781                 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
1782                 radeon_bo_unreserve(rdev->wb.wb_obj);
1783                 if (r) {
1784                         dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
1785                         r600_wb_fini(rdev);
1786                         return r;
1787                 }
1788         }
1789         WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF);
1790         WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC);
1791         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF);
1792         WREG32(SCRATCH_UMSK, 0xff);
1793         return 0;
1794 }
1795
1796 void r600_fence_ring_emit(struct radeon_device *rdev,
1797                           struct radeon_fence *fence)
1798 {
1799         /* Also consider EVENT_WRITE_EOP.  it handles the interrupts + timestamps + events */
1800
1801         radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
1802         radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT);
1803         /* wait for 3D idle clean */
1804         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1805         radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
1806         radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
1807         /* Emit fence sequence & fire IRQ */
1808         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1809         radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1810         radeon_ring_write(rdev, fence->seq);
1811         /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
1812         radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
1813         radeon_ring_write(rdev, RB_INT_STAT);
1814 }
1815
1816 int r600_copy_blit(struct radeon_device *rdev,
1817                    uint64_t src_offset, uint64_t dst_offset,
1818                    unsigned num_pages, struct radeon_fence *fence)
1819 {
1820         int r;
1821
1822         mutex_lock(&rdev->r600_blit.mutex);
1823         rdev->r600_blit.vb_ib = NULL;
1824         r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
1825         if (r) {
1826                 if (rdev->r600_blit.vb_ib)
1827                         radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
1828                 mutex_unlock(&rdev->r600_blit.mutex);
1829                 return r;
1830         }
1831         r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
1832         r600_blit_done_copy(rdev, fence);
1833         mutex_unlock(&rdev->r600_blit.mutex);
1834         return 0;
1835 }
1836
1837 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
1838                          uint32_t tiling_flags, uint32_t pitch,
1839                          uint32_t offset, uint32_t obj_size)
1840 {
1841         /* FIXME: implement */
1842         return 0;
1843 }
1844
1845 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
1846 {
1847         /* FIXME: implement */
1848 }
1849
1850
1851 bool r600_card_posted(struct radeon_device *rdev)
1852 {
1853         uint32_t reg;
1854
1855         /* first check CRTCs */
1856         reg = RREG32(D1CRTC_CONTROL) |
1857                 RREG32(D2CRTC_CONTROL);
1858         if (reg & CRTC_EN)
1859                 return true;
1860
1861         /* then check MEM_SIZE, in case the crtcs are off */
1862         if (RREG32(CONFIG_MEMSIZE))
1863                 return true;
1864
1865         return false;
1866 }
1867
1868 int r600_startup(struct radeon_device *rdev)
1869 {
1870         int r;
1871
1872         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1873                 r = r600_init_microcode(rdev);
1874                 if (r) {
1875                         DRM_ERROR("Failed to load firmware!\n");
1876                         return r;
1877                 }
1878         }
1879
1880         r600_mc_program(rdev);
1881         if (rdev->flags & RADEON_IS_AGP) {
1882                 r600_agp_enable(rdev);
1883         } else {
1884                 r = r600_pcie_gart_enable(rdev);
1885                 if (r)
1886                         return r;
1887         }
1888         r600_gpu_init(rdev);
1889         r = r600_blit_init(rdev);
1890         if (r) {
1891                 r600_blit_fini(rdev);
1892                 rdev->asic->copy = NULL;
1893                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1894         }
1895         /* pin copy shader into vram */
1896         if (rdev->r600_blit.shader_obj) {
1897                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1898                 if (unlikely(r != 0))
1899                         return r;
1900                 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
1901                                 &rdev->r600_blit.shader_gpu_addr);
1902                 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1903                 if (r) {
1904                         dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
1905                         return r;
1906                 }
1907         }
1908         /* Enable IRQ */
1909         r = r600_irq_init(rdev);
1910         if (r) {
1911                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1912                 radeon_irq_kms_fini(rdev);
1913                 return r;
1914         }
1915         r600_irq_set(rdev);
1916
1917         r = radeon_ring_init(rdev, rdev->cp.ring_size);
1918         if (r)
1919                 return r;
1920         r = r600_cp_load_microcode(rdev);
1921         if (r)
1922                 return r;
1923         r = r600_cp_resume(rdev);
1924         if (r)
1925                 return r;
1926         /* write back buffer are not vital so don't worry about failure */
1927         r600_wb_enable(rdev);
1928         return 0;
1929 }
1930
1931 void r600_vga_set_state(struct radeon_device *rdev, bool state)
1932 {
1933         uint32_t temp;
1934
1935         temp = RREG32(CONFIG_CNTL);
1936         if (state == false) {
1937                 temp &= ~(1<<0);
1938                 temp |= (1<<1);
1939         } else {
1940                 temp &= ~(1<<1);
1941         }
1942         WREG32(CONFIG_CNTL, temp);
1943 }
1944
1945 int r600_resume(struct radeon_device *rdev)
1946 {
1947         int r;
1948
1949         /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
1950          * posting will perform necessary task to bring back GPU into good
1951          * shape.
1952          */
1953         /* post card */
1954         atom_asic_init(rdev->mode_info.atom_context);
1955         /* Initialize clocks */
1956         r = radeon_clocks_init(rdev);
1957         if (r) {
1958                 return r;
1959         }
1960
1961         r = r600_startup(rdev);
1962         if (r) {
1963                 DRM_ERROR("r600 startup failed on resume\n");
1964                 return r;
1965         }
1966
1967         r = r600_ib_test(rdev);
1968         if (r) {
1969                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1970                 return r;
1971         }
1972         return r;
1973 }
1974
1975 int r600_suspend(struct radeon_device *rdev)
1976 {
1977         int r;
1978
1979         /* FIXME: we should wait for ring to be empty */
1980         r600_cp_stop(rdev);
1981         rdev->cp.ready = false;
1982         r600_irq_suspend(rdev);
1983         r600_wb_disable(rdev);
1984         r600_pcie_gart_disable(rdev);
1985         /* unpin shaders bo */
1986         if (rdev->r600_blit.shader_obj) {
1987                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1988                 if (!r) {
1989                         radeon_bo_unpin(rdev->r600_blit.shader_obj);
1990                         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1991                 }
1992         }
1993         return 0;
1994 }
1995
1996 /* Plan is to move initialization in that function and use
1997  * helper function so that radeon_device_init pretty much
1998  * do nothing more than calling asic specific function. This
1999  * should also allow to remove a bunch of callback function
2000  * like vram_info.
2001  */
2002 int r600_init(struct radeon_device *rdev)
2003 {
2004         int r;
2005
2006         r = radeon_dummy_page_init(rdev);
2007         if (r)
2008                 return r;
2009         if (r600_debugfs_mc_info_init(rdev)) {
2010                 DRM_ERROR("Failed to register debugfs file for mc !\n");
2011         }
2012         /* This don't do much */
2013         r = radeon_gem_init(rdev);
2014         if (r)
2015                 return r;
2016         /* Read BIOS */
2017         if (!radeon_get_bios(rdev)) {
2018                 if (ASIC_IS_AVIVO(rdev))
2019                         return -EINVAL;
2020         }
2021         /* Must be an ATOMBIOS */
2022         if (!rdev->is_atom_bios) {
2023                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2024                 return -EINVAL;
2025         }
2026         r = radeon_atombios_init(rdev);
2027         if (r)
2028                 return r;
2029         /* Post card if necessary */
2030         if (!r600_card_posted(rdev)) {
2031                 if (!rdev->bios) {
2032                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2033                         return -EINVAL;
2034                 }
2035                 DRM_INFO("GPU not posted. posting now...\n");
2036                 atom_asic_init(rdev->mode_info.atom_context);
2037         }
2038         /* Initialize scratch registers */
2039         r600_scratch_init(rdev);
2040         /* Initialize surface registers */
2041         radeon_surface_init(rdev);
2042         /* Initialize clocks */
2043         radeon_get_clock_info(rdev->ddev);
2044         r = radeon_clocks_init(rdev);
2045         if (r)
2046                 return r;
2047         /* Initialize power management */
2048         radeon_pm_init(rdev);
2049         /* Fence driver */
2050         r = radeon_fence_driver_init(rdev);
2051         if (r)
2052                 return r;
2053         if (rdev->flags & RADEON_IS_AGP) {
2054                 r = radeon_agp_init(rdev);
2055                 if (r)
2056                         radeon_agp_disable(rdev);
2057         }
2058         r = r600_mc_init(rdev);
2059         if (r)
2060                 return r;
2061         /* Memory manager */
2062         r = radeon_bo_init(rdev);
2063         if (r)
2064                 return r;
2065
2066         r = radeon_irq_kms_init(rdev);
2067         if (r)
2068                 return r;
2069
2070         rdev->cp.ring_obj = NULL;
2071         r600_ring_init(rdev, 1024 * 1024);
2072
2073         rdev->ih.ring_obj = NULL;
2074         r600_ih_ring_init(rdev, 64 * 1024);
2075
2076         r = r600_pcie_gart_init(rdev);
2077         if (r)
2078                 return r;
2079
2080         rdev->accel_working = true;
2081         r = r600_startup(rdev);
2082         if (r) {
2083                 dev_err(rdev->dev, "disabling GPU acceleration\n");
2084                 r600_cp_fini(rdev);
2085                 r600_wb_fini(rdev);
2086                 r600_irq_fini(rdev);
2087                 radeon_irq_kms_fini(rdev);
2088                 r600_pcie_gart_fini(rdev);
2089                 rdev->accel_working = false;
2090         }
2091         if (rdev->accel_working) {
2092                 r = radeon_ib_pool_init(rdev);
2093                 if (r) {
2094                         dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2095                         rdev->accel_working = false;
2096                 } else {
2097                         r = r600_ib_test(rdev);
2098                         if (r) {
2099                                 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2100                                 rdev->accel_working = false;
2101                         }
2102                 }
2103         }
2104
2105         r = r600_audio_init(rdev);
2106         if (r)
2107                 return r; /* TODO error handling */
2108         return 0;
2109 }
2110
2111 void r600_fini(struct radeon_device *rdev)
2112 {
2113         r600_audio_fini(rdev);
2114         r600_blit_fini(rdev);
2115         r600_cp_fini(rdev);
2116         r600_wb_fini(rdev);
2117         r600_irq_fini(rdev);
2118         radeon_irq_kms_fini(rdev);
2119         r600_pcie_gart_fini(rdev);
2120         radeon_agp_fini(rdev);
2121         radeon_gem_fini(rdev);
2122         radeon_fence_driver_fini(rdev);
2123         radeon_clocks_fini(rdev);
2124         radeon_bo_fini(rdev);
2125         radeon_atombios_fini(rdev);
2126         kfree(rdev->bios);
2127         rdev->bios = NULL;
2128         radeon_dummy_page_fini(rdev);
2129 }
2130
2131
2132 /*
2133  * CS stuff
2134  */
2135 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2136 {
2137         /* FIXME: implement */
2138         radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2139         radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
2140         radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
2141         radeon_ring_write(rdev, ib->length_dw);
2142 }
2143
2144 int r600_ib_test(struct radeon_device *rdev)
2145 {
2146         struct radeon_ib *ib;
2147         uint32_t scratch;
2148         uint32_t tmp = 0;
2149         unsigned i;
2150         int r;
2151
2152         r = radeon_scratch_get(rdev, &scratch);
2153         if (r) {
2154                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2155                 return r;
2156         }
2157         WREG32(scratch, 0xCAFEDEAD);
2158         r = radeon_ib_get(rdev, &ib);
2159         if (r) {
2160                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2161                 return r;
2162         }
2163         ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2164         ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2165         ib->ptr[2] = 0xDEADBEEF;
2166         ib->ptr[3] = PACKET2(0);
2167         ib->ptr[4] = PACKET2(0);
2168         ib->ptr[5] = PACKET2(0);
2169         ib->ptr[6] = PACKET2(0);
2170         ib->ptr[7] = PACKET2(0);
2171         ib->ptr[8] = PACKET2(0);
2172         ib->ptr[9] = PACKET2(0);
2173         ib->ptr[10] = PACKET2(0);
2174         ib->ptr[11] = PACKET2(0);
2175         ib->ptr[12] = PACKET2(0);
2176         ib->ptr[13] = PACKET2(0);
2177         ib->ptr[14] = PACKET2(0);
2178         ib->ptr[15] = PACKET2(0);
2179         ib->length_dw = 16;
2180         r = radeon_ib_schedule(rdev, ib);
2181         if (r) {
2182                 radeon_scratch_free(rdev, scratch);
2183                 radeon_ib_free(rdev, &ib);
2184                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2185                 return r;
2186         }
2187         r = radeon_fence_wait(ib->fence, false);
2188         if (r) {
2189                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2190                 return r;
2191         }
2192         for (i = 0; i < rdev->usec_timeout; i++) {
2193                 tmp = RREG32(scratch);
2194                 if (tmp == 0xDEADBEEF)
2195                         break;
2196                 DRM_UDELAY(1);
2197         }
2198         if (i < rdev->usec_timeout) {
2199                 DRM_INFO("ib test succeeded in %u usecs\n", i);
2200         } else {
2201                 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
2202                           scratch, tmp);
2203                 r = -EINVAL;
2204         }
2205         radeon_scratch_free(rdev, scratch);
2206         radeon_ib_free(rdev, &ib);
2207         return r;
2208 }
2209
2210 /*
2211  * Interrupts
2212  *
2213  * Interrupts use a ring buffer on r6xx/r7xx hardware.  It works pretty
2214  * the same as the CP ring buffer, but in reverse.  Rather than the CPU
2215  * writing to the ring and the GPU consuming, the GPU writes to the ring
2216  * and host consumes.  As the host irq handler processes interrupts, it
2217  * increments the rptr.  When the rptr catches up with the wptr, all the
2218  * current interrupts have been processed.
2219  */
2220
2221 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2222 {
2223         u32 rb_bufsz;
2224
2225         /* Align ring size */
2226         rb_bufsz = drm_order(ring_size / 4);
2227         ring_size = (1 << rb_bufsz) * 4;
2228         rdev->ih.ring_size = ring_size;
2229         rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2230         rdev->ih.rptr = 0;
2231 }
2232
2233 static int r600_ih_ring_alloc(struct radeon_device *rdev)
2234 {
2235         int r;
2236
2237         /* Allocate ring buffer */
2238         if (rdev->ih.ring_obj == NULL) {
2239                 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size,
2240                                      true,
2241                                      RADEON_GEM_DOMAIN_GTT,
2242                                      &rdev->ih.ring_obj);
2243                 if (r) {
2244                         DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2245                         return r;
2246                 }
2247                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2248                 if (unlikely(r != 0))
2249                         return r;
2250                 r = radeon_bo_pin(rdev->ih.ring_obj,
2251                                   RADEON_GEM_DOMAIN_GTT,
2252                                   &rdev->ih.gpu_addr);
2253                 if (r) {
2254                         radeon_bo_unreserve(rdev->ih.ring_obj);
2255                         DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2256                         return r;
2257                 }
2258                 r = radeon_bo_kmap(rdev->ih.ring_obj,
2259                                    (void **)&rdev->ih.ring);
2260                 radeon_bo_unreserve(rdev->ih.ring_obj);
2261                 if (r) {
2262                         DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2263                         return r;
2264                 }
2265         }
2266         return 0;
2267 }
2268
2269 static void r600_ih_ring_fini(struct radeon_device *rdev)
2270 {
2271         int r;
2272         if (rdev->ih.ring_obj) {
2273                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2274                 if (likely(r == 0)) {
2275                         radeon_bo_kunmap(rdev->ih.ring_obj);
2276                         radeon_bo_unpin(rdev->ih.ring_obj);
2277                         radeon_bo_unreserve(rdev->ih.ring_obj);
2278                 }
2279                 radeon_bo_unref(&rdev->ih.ring_obj);
2280                 rdev->ih.ring = NULL;
2281                 rdev->ih.ring_obj = NULL;
2282         }
2283 }
2284
2285 static void r600_rlc_stop(struct radeon_device *rdev)
2286 {
2287
2288         if (rdev->family >= CHIP_RV770) {
2289                 /* r7xx asics need to soft reset RLC before halting */
2290                 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2291                 RREG32(SRBM_SOFT_RESET);
2292                 udelay(15000);
2293                 WREG32(SRBM_SOFT_RESET, 0);
2294                 RREG32(SRBM_SOFT_RESET);
2295         }
2296
2297         WREG32(RLC_CNTL, 0);
2298 }
2299
2300 static void r600_rlc_start(struct radeon_device *rdev)
2301 {
2302         WREG32(RLC_CNTL, RLC_ENABLE);
2303 }
2304
2305 static int r600_rlc_init(struct radeon_device *rdev)
2306 {
2307         u32 i;
2308         const __be32 *fw_data;
2309
2310         if (!rdev->rlc_fw)
2311                 return -EINVAL;
2312
2313         r600_rlc_stop(rdev);
2314
2315         WREG32(RLC_HB_BASE, 0);
2316         WREG32(RLC_HB_CNTL, 0);
2317         WREG32(RLC_HB_RPTR, 0);
2318         WREG32(RLC_HB_WPTR, 0);
2319         WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2320         WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2321         WREG32(RLC_MC_CNTL, 0);
2322         WREG32(RLC_UCODE_CNTL, 0);
2323
2324         fw_data = (const __be32 *)rdev->rlc_fw->data;
2325         if (rdev->family >= CHIP_RV770) {
2326                 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2327                         WREG32(RLC_UCODE_ADDR, i);
2328                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2329                 }
2330         } else {
2331                 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2332                         WREG32(RLC_UCODE_ADDR, i);
2333                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2334                 }
2335         }
2336         WREG32(RLC_UCODE_ADDR, 0);
2337
2338         r600_rlc_start(rdev);
2339
2340         return 0;
2341 }
2342
2343 static void r600_enable_interrupts(struct radeon_device *rdev)
2344 {
2345         u32 ih_cntl = RREG32(IH_CNTL);
2346         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2347
2348         ih_cntl |= ENABLE_INTR;
2349         ih_rb_cntl |= IH_RB_ENABLE;
2350         WREG32(IH_CNTL, ih_cntl);
2351         WREG32(IH_RB_CNTL, ih_rb_cntl);
2352         rdev->ih.enabled = true;
2353 }
2354
2355 static void r600_disable_interrupts(struct radeon_device *rdev)
2356 {
2357         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2358         u32 ih_cntl = RREG32(IH_CNTL);
2359
2360         ih_rb_cntl &= ~IH_RB_ENABLE;
2361         ih_cntl &= ~ENABLE_INTR;
2362         WREG32(IH_RB_CNTL, ih_rb_cntl);
2363         WREG32(IH_CNTL, ih_cntl);
2364         /* set rptr, wptr to 0 */
2365         WREG32(IH_RB_RPTR, 0);
2366         WREG32(IH_RB_WPTR, 0);
2367         rdev->ih.enabled = false;
2368         rdev->ih.wptr = 0;
2369         rdev->ih.rptr = 0;
2370 }
2371
2372 static void r600_disable_interrupt_state(struct radeon_device *rdev)
2373 {
2374         u32 tmp;
2375
2376         WREG32(CP_INT_CNTL, 0);
2377         WREG32(GRBM_INT_CNTL, 0);
2378         WREG32(DxMODE_INT_MASK, 0);
2379         if (ASIC_IS_DCE3(rdev)) {
2380                 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2381                 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2382                 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2383                 WREG32(DC_HPD1_INT_CONTROL, tmp);
2384                 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2385                 WREG32(DC_HPD2_INT_CONTROL, tmp);
2386                 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2387                 WREG32(DC_HPD3_INT_CONTROL, tmp);
2388                 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2389                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2390                 if (ASIC_IS_DCE32(rdev)) {
2391                         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2392                         WREG32(DC_HPD5_INT_CONTROL, 0);
2393                         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2394                         WREG32(DC_HPD6_INT_CONTROL, 0);
2395                 }
2396         } else {
2397                 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2398                 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2399                 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2400                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, 0);
2401                 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2402                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, 0);
2403                 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2404                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, 0);
2405         }
2406 }
2407
2408 int r600_irq_init(struct radeon_device *rdev)
2409 {
2410         int ret = 0;
2411         int rb_bufsz;
2412         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2413
2414         /* allocate ring */
2415         ret = r600_ih_ring_alloc(rdev);
2416         if (ret)
2417                 return ret;
2418
2419         /* disable irqs */
2420         r600_disable_interrupts(rdev);
2421
2422         /* init rlc */
2423         ret = r600_rlc_init(rdev);
2424         if (ret) {
2425                 r600_ih_ring_fini(rdev);
2426                 return ret;
2427         }
2428
2429         /* setup interrupt control */
2430         /* set dummy read address to ring address */
2431         WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2432         interrupt_cntl = RREG32(INTERRUPT_CNTL);
2433         /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2434          * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2435          */
2436         interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
2437         /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2438         interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
2439         WREG32(INTERRUPT_CNTL, interrupt_cntl);
2440
2441         WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
2442         rb_bufsz = drm_order(rdev->ih.ring_size / 4);
2443
2444         ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
2445                       IH_WPTR_OVERFLOW_CLEAR |
2446                       (rb_bufsz << 1));
2447         /* WPTR writeback, not yet */
2448         /*ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;*/
2449         WREG32(IH_RB_WPTR_ADDR_LO, 0);
2450         WREG32(IH_RB_WPTR_ADDR_HI, 0);
2451
2452         WREG32(IH_RB_CNTL, ih_rb_cntl);
2453
2454         /* set rptr, wptr to 0 */
2455         WREG32(IH_RB_RPTR, 0);
2456         WREG32(IH_RB_WPTR, 0);
2457
2458         /* Default settings for IH_CNTL (disabled at first) */
2459         ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2460         /* RPTR_REARM only works if msi's are enabled */
2461         if (rdev->msi_enabled)
2462                 ih_cntl |= RPTR_REARM;
2463
2464 #ifdef __BIG_ENDIAN
2465         ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT);
2466 #endif
2467         WREG32(IH_CNTL, ih_cntl);
2468
2469         /* force the active interrupt state to all disabled */
2470         r600_disable_interrupt_state(rdev);
2471
2472         /* enable irqs */
2473         r600_enable_interrupts(rdev);
2474
2475         return ret;
2476 }
2477
2478 void r600_irq_suspend(struct radeon_device *rdev)
2479 {
2480         r600_disable_interrupts(rdev);
2481         r600_rlc_stop(rdev);
2482 }
2483
2484 void r600_irq_fini(struct radeon_device *rdev)
2485 {
2486         r600_irq_suspend(rdev);
2487         r600_ih_ring_fini(rdev);
2488 }
2489
2490 int r600_irq_set(struct radeon_device *rdev)
2491 {
2492         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2493         u32 mode_int = 0;
2494         u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
2495
2496         if (!rdev->irq.installed) {
2497                 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
2498                 return -EINVAL;
2499         }
2500         /* don't enable anything if the ih is disabled */
2501         if (!rdev->ih.enabled) {
2502                 r600_disable_interrupts(rdev);
2503                 /* force the active interrupt state to all disabled */
2504                 r600_disable_interrupt_state(rdev);
2505                 return 0;
2506         }
2507
2508         if (ASIC_IS_DCE3(rdev)) {
2509                 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2510                 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2511                 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2512                 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2513                 if (ASIC_IS_DCE32(rdev)) {
2514                         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2515                         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2516                 }
2517         } else {
2518                 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2519                 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2520                 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2521         }
2522
2523         if (rdev->irq.sw_int) {
2524                 DRM_DEBUG("r600_irq_set: sw int\n");
2525                 cp_int_cntl |= RB_INT_ENABLE;
2526         }
2527         if (rdev->irq.crtc_vblank_int[0]) {
2528                 DRM_DEBUG("r600_irq_set: vblank 0\n");
2529                 mode_int |= D1MODE_VBLANK_INT_MASK;
2530         }
2531         if (rdev->irq.crtc_vblank_int[1]) {
2532                 DRM_DEBUG("r600_irq_set: vblank 1\n");
2533                 mode_int |= D2MODE_VBLANK_INT_MASK;
2534         }
2535         if (rdev->irq.hpd[0]) {
2536                 DRM_DEBUG("r600_irq_set: hpd 1\n");
2537                 hpd1 |= DC_HPDx_INT_EN;
2538         }
2539         if (rdev->irq.hpd[1]) {
2540                 DRM_DEBUG("r600_irq_set: hpd 2\n");
2541                 hpd2 |= DC_HPDx_INT_EN;
2542         }
2543         if (rdev->irq.hpd[2]) {
2544                 DRM_DEBUG("r600_irq_set: hpd 3\n");
2545                 hpd3 |= DC_HPDx_INT_EN;
2546         }
2547         if (rdev->irq.hpd[3]) {
2548                 DRM_DEBUG("r600_irq_set: hpd 4\n");
2549                 hpd4 |= DC_HPDx_INT_EN;
2550         }
2551         if (rdev->irq.hpd[4]) {
2552                 DRM_DEBUG("r600_irq_set: hpd 5\n");
2553                 hpd5 |= DC_HPDx_INT_EN;
2554         }
2555         if (rdev->irq.hpd[5]) {
2556                 DRM_DEBUG("r600_irq_set: hpd 6\n");
2557                 hpd6 |= DC_HPDx_INT_EN;
2558         }
2559
2560         WREG32(CP_INT_CNTL, cp_int_cntl);
2561         WREG32(DxMODE_INT_MASK, mode_int);
2562         if (ASIC_IS_DCE3(rdev)) {
2563                 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2564                 WREG32(DC_HPD2_INT_CONTROL, hpd2);
2565                 WREG32(DC_HPD3_INT_CONTROL, hpd3);
2566                 WREG32(DC_HPD4_INT_CONTROL, hpd4);
2567                 if (ASIC_IS_DCE32(rdev)) {
2568                         WREG32(DC_HPD5_INT_CONTROL, hpd5);
2569                         WREG32(DC_HPD6_INT_CONTROL, hpd6);
2570                 }
2571         } else {
2572                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
2573                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
2574                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
2575         }
2576
2577         return 0;
2578 }
2579
2580 static inline void r600_irq_ack(struct radeon_device *rdev,
2581                                 u32 *disp_int,
2582                                 u32 *disp_int_cont,
2583                                 u32 *disp_int_cont2)
2584 {
2585         u32 tmp;
2586
2587         if (ASIC_IS_DCE3(rdev)) {
2588                 *disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
2589                 *disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
2590                 *disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
2591         } else {
2592                 *disp_int = RREG32(DISP_INTERRUPT_STATUS);
2593                 *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2594                 *disp_int_cont2 = 0;
2595         }
2596
2597         if (*disp_int & LB_D1_VBLANK_INTERRUPT)
2598                 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
2599         if (*disp_int & LB_D1_VLINE_INTERRUPT)
2600                 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
2601         if (*disp_int & LB_D2_VBLANK_INTERRUPT)
2602                 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
2603         if (*disp_int & LB_D2_VLINE_INTERRUPT)
2604                 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
2605         if (*disp_int & DC_HPD1_INTERRUPT) {
2606                 if (ASIC_IS_DCE3(rdev)) {
2607                         tmp = RREG32(DC_HPD1_INT_CONTROL);
2608                         tmp |= DC_HPDx_INT_ACK;
2609                         WREG32(DC_HPD1_INT_CONTROL, tmp);
2610                 } else {
2611                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
2612                         tmp |= DC_HPDx_INT_ACK;
2613                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
2614                 }
2615         }
2616         if (*disp_int & DC_HPD2_INTERRUPT) {
2617                 if (ASIC_IS_DCE3(rdev)) {
2618                         tmp = RREG32(DC_HPD2_INT_CONTROL);
2619                         tmp |= DC_HPDx_INT_ACK;
2620                         WREG32(DC_HPD2_INT_CONTROL, tmp);
2621                 } else {
2622                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
2623                         tmp |= DC_HPDx_INT_ACK;
2624                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
2625                 }
2626         }
2627         if (*disp_int_cont & DC_HPD3_INTERRUPT) {
2628                 if (ASIC_IS_DCE3(rdev)) {
2629                         tmp = RREG32(DC_HPD3_INT_CONTROL);
2630                         tmp |= DC_HPDx_INT_ACK;
2631                         WREG32(DC_HPD3_INT_CONTROL, tmp);
2632                 } else {
2633                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
2634                         tmp |= DC_HPDx_INT_ACK;
2635                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
2636                 }
2637         }
2638         if (*disp_int_cont & DC_HPD4_INTERRUPT) {
2639                 tmp = RREG32(DC_HPD4_INT_CONTROL);
2640                 tmp |= DC_HPDx_INT_ACK;
2641                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2642         }
2643         if (ASIC_IS_DCE32(rdev)) {
2644                 if (*disp_int_cont2 & DC_HPD5_INTERRUPT) {
2645                         tmp = RREG32(DC_HPD5_INT_CONTROL);
2646                         tmp |= DC_HPDx_INT_ACK;
2647                         WREG32(DC_HPD5_INT_CONTROL, tmp);
2648                 }
2649                 if (*disp_int_cont2 & DC_HPD6_INTERRUPT) {
2650                         tmp = RREG32(DC_HPD5_INT_CONTROL);
2651                         tmp |= DC_HPDx_INT_ACK;
2652                         WREG32(DC_HPD6_INT_CONTROL, tmp);
2653                 }
2654         }
2655 }
2656
2657 void r600_irq_disable(struct radeon_device *rdev)
2658 {
2659         u32 disp_int, disp_int_cont, disp_int_cont2;
2660
2661         r600_disable_interrupts(rdev);
2662         /* Wait and acknowledge irq */
2663         mdelay(1);
2664         r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
2665         r600_disable_interrupt_state(rdev);
2666 }
2667
2668 static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
2669 {
2670         u32 wptr, tmp;
2671
2672         /* XXX use writeback */
2673         wptr = RREG32(IH_RB_WPTR);
2674
2675         if (wptr & RB_OVERFLOW) {
2676                 /* When a ring buffer overflow happen start parsing interrupt
2677                  * from the last not overwritten vector (wptr + 16). Hopefully
2678                  * this should allow us to catchup.
2679                  */
2680                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2681                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2682                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2683                 tmp = RREG32(IH_RB_CNTL);
2684                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2685                 WREG32(IH_RB_CNTL, tmp);
2686         }
2687         return (wptr & rdev->ih.ptr_mask);
2688 }
2689
2690 /*        r600 IV Ring
2691  * Each IV ring entry is 128 bits:
2692  * [7:0]    - interrupt source id
2693  * [31:8]   - reserved
2694  * [59:32]  - interrupt source data
2695  * [127:60]  - reserved
2696  *
2697  * The basic interrupt vector entries
2698  * are decoded as follows:
2699  * src_id  src_data  description
2700  *      1         0  D1 Vblank
2701  *      1         1  D1 Vline
2702  *      5         0  D2 Vblank
2703  *      5         1  D2 Vline
2704  *     19         0  FP Hot plug detection A
2705  *     19         1  FP Hot plug detection B
2706  *     19         2  DAC A auto-detection
2707  *     19         3  DAC B auto-detection
2708  *    176         -  CP_INT RB
2709  *    177         -  CP_INT IB1
2710  *    178         -  CP_INT IB2
2711  *    181         -  EOP Interrupt
2712  *    233         -  GUI Idle
2713  *
2714  * Note, these are based on r600 and may need to be
2715  * adjusted or added to on newer asics
2716  */
2717
2718 int r600_irq_process(struct radeon_device *rdev)
2719 {
2720         u32 wptr = r600_get_ih_wptr(rdev);
2721         u32 rptr = rdev->ih.rptr;
2722         u32 src_id, src_data;
2723         u32 ring_index, disp_int, disp_int_cont, disp_int_cont2;
2724         unsigned long flags;
2725         bool queue_hotplug = false;
2726
2727         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2728         if (!rdev->ih.enabled)
2729                 return IRQ_NONE;
2730
2731         spin_lock_irqsave(&rdev->ih.lock, flags);
2732
2733         if (rptr == wptr) {
2734                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2735                 return IRQ_NONE;
2736         }
2737         if (rdev->shutdown) {
2738                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2739                 return IRQ_NONE;
2740         }
2741
2742 restart_ih:
2743         /* display interrupts */
2744         r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
2745
2746         rdev->ih.wptr = wptr;
2747         while (rptr != wptr) {
2748                 /* wptr/rptr are in bytes! */
2749                 ring_index = rptr / 4;
2750                 src_id =  rdev->ih.ring[ring_index] & 0xff;
2751                 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
2752
2753                 switch (src_id) {
2754                 case 1: /* D1 vblank/vline */
2755                         switch (src_data) {
2756                         case 0: /* D1 vblank */
2757                                 if (disp_int & LB_D1_VBLANK_INTERRUPT) {
2758                                         drm_handle_vblank(rdev->ddev, 0);
2759                                         wake_up(&rdev->irq.vblank_queue);
2760                                         disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2761                                         DRM_DEBUG("IH: D1 vblank\n");
2762                                 }
2763                                 break;
2764                         case 1: /* D1 vline */
2765                                 if (disp_int & LB_D1_VLINE_INTERRUPT) {
2766                                         disp_int &= ~LB_D1_VLINE_INTERRUPT;
2767                                         DRM_DEBUG("IH: D1 vline\n");
2768                                 }
2769                                 break;
2770                         default:
2771                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2772                                 break;
2773                         }
2774                         break;
2775                 case 5: /* D2 vblank/vline */
2776                         switch (src_data) {
2777                         case 0: /* D2 vblank */
2778                                 if (disp_int & LB_D2_VBLANK_INTERRUPT) {
2779                                         drm_handle_vblank(rdev->ddev, 1);
2780                                         wake_up(&rdev->irq.vblank_queue);
2781                                         disp_int &= ~LB_D2_VBLANK_INTERRUPT;
2782                                         DRM_DEBUG("IH: D2 vblank\n");
2783                                 }
2784                                 break;
2785                         case 1: /* D1 vline */
2786                                 if (disp_int & LB_D2_VLINE_INTERRUPT) {
2787                                         disp_int &= ~LB_D2_VLINE_INTERRUPT;
2788                                         DRM_DEBUG("IH: D2 vline\n");
2789                                 }
2790                                 break;
2791                         default:
2792                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2793                                 break;
2794                         }
2795                         break;
2796                 case 19: /* HPD/DAC hotplug */
2797                         switch (src_data) {
2798                         case 0:
2799                                 if (disp_int & DC_HPD1_INTERRUPT) {
2800                                         disp_int &= ~DC_HPD1_INTERRUPT;
2801                                         queue_hotplug = true;
2802                                         DRM_DEBUG("IH: HPD1\n");
2803                                 }
2804                                 break;
2805                         case 1:
2806                                 if (disp_int & DC_HPD2_INTERRUPT) {
2807                                         disp_int &= ~DC_HPD2_INTERRUPT;
2808                                         queue_hotplug = true;
2809                                         DRM_DEBUG("IH: HPD2\n");
2810                                 }
2811                                 break;
2812                         case 4:
2813                                 if (disp_int_cont & DC_HPD3_INTERRUPT) {
2814                                         disp_int_cont &= ~DC_HPD3_INTERRUPT;
2815                                         queue_hotplug = true;
2816                                         DRM_DEBUG("IH: HPD3\n");
2817                                 }
2818                                 break;
2819                         case 5:
2820                                 if (disp_int_cont & DC_HPD4_INTERRUPT) {
2821                                         disp_int_cont &= ~DC_HPD4_INTERRUPT;
2822                                         queue_hotplug = true;
2823                                         DRM_DEBUG("IH: HPD4\n");
2824                                 }
2825                                 break;
2826                         case 10:
2827                                 if (disp_int_cont2 & DC_HPD5_INTERRUPT) {
2828                                         disp_int_cont &= ~DC_HPD5_INTERRUPT;
2829                                         queue_hotplug = true;
2830                                         DRM_DEBUG("IH: HPD5\n");
2831                                 }
2832                                 break;
2833                         case 12:
2834                                 if (disp_int_cont2 & DC_HPD6_INTERRUPT) {
2835                                         disp_int_cont &= ~DC_HPD6_INTERRUPT;
2836                                         queue_hotplug = true;
2837                                         DRM_DEBUG("IH: HPD6\n");
2838                                 }
2839                                 break;
2840                         default:
2841                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2842                                 break;
2843                         }
2844                         break;
2845                 case 176: /* CP_INT in ring buffer */
2846                 case 177: /* CP_INT in IB1 */
2847                 case 178: /* CP_INT in IB2 */
2848                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
2849                         radeon_fence_process(rdev);
2850                         break;
2851                 case 181: /* CP EOP event */
2852                         DRM_DEBUG("IH: CP EOP\n");
2853                         break;
2854                 default:
2855                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2856                         break;
2857                 }
2858
2859                 /* wptr/rptr are in bytes! */
2860                 rptr += 16;
2861                 rptr &= rdev->ih.ptr_mask;
2862         }
2863         /* make sure wptr hasn't changed while processing */
2864         wptr = r600_get_ih_wptr(rdev);
2865         if (wptr != rdev->ih.wptr)
2866                 goto restart_ih;
2867         if (queue_hotplug)
2868                 queue_work(rdev->wq, &rdev->hotplug_work);
2869         rdev->ih.rptr = rptr;
2870         WREG32(IH_RB_RPTR, rdev->ih.rptr);
2871         spin_unlock_irqrestore(&rdev->ih.lock, flags);
2872         return IRQ_HANDLED;
2873 }
2874
2875 /*
2876  * Debugfs info
2877  */
2878 #if defined(CONFIG_DEBUG_FS)
2879
2880 static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
2881 {
2882         struct drm_info_node *node = (struct drm_info_node *) m->private;
2883         struct drm_device *dev = node->minor->dev;
2884         struct radeon_device *rdev = dev->dev_private;
2885         unsigned count, i, j;
2886
2887         radeon_ring_free_size(rdev);
2888         count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
2889         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
2890         seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
2891         seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
2892         seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
2893         seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
2894         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2895         seq_printf(m, "%u dwords in ring\n", count);
2896         i = rdev->cp.rptr;
2897         for (j = 0; j <= count; j++) {
2898                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2899                 i = (i + 1) & rdev->cp.ptr_mask;
2900         }
2901         return 0;
2902 }
2903
2904 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
2905 {
2906         struct drm_info_node *node = (struct drm_info_node *) m->private;
2907         struct drm_device *dev = node->minor->dev;
2908         struct radeon_device *rdev = dev->dev_private;
2909
2910         DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
2911         DREG32_SYS(m, rdev, VM_L2_STATUS);
2912         return 0;
2913 }
2914
2915 static struct drm_info_list r600_mc_info_list[] = {
2916         {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
2917         {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
2918 };
2919 #endif
2920
2921 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
2922 {
2923 #if defined(CONFIG_DEBUG_FS)
2924         return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
2925 #else
2926         return 0;
2927 #endif
2928 }
2929
2930 /**
2931  * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
2932  * rdev: radeon device structure
2933  * bo: buffer object struct which userspace is waiting for idle
2934  *
2935  * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
2936  * through ring buffer, this leads to corruption in rendering, see
2937  * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
2938  * directly perform HDP flush by writing register through MMIO.
2939  */
2940 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
2941 {
2942         WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2943 }