SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/r600.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include <linux/firmware.h>
  30 #include <linux/platform_device.h>
  31 #include "drmP.h"
  32 #include "radeon_drm.h"
  33 #include "radeon.h"
  34 #include "radeon_mode.h"
  35 #include "r600d.h"
  36 #include "atom.h"
  37 #include "avivod.h"
  38
  39 #define PFP_UCODE_SIZE 576
  40 #define PM4_UCODE_SIZE 1792
  41 #define RLC_UCODE_SIZE 768
  42 #define R700_PFP_UCODE_SIZE 848
  43 #define R700_PM4_UCODE_SIZE 1360
  44 #define R700_RLC_UCODE_SIZE 1024
  45
  46 /* Firmware Names */
  47 MODULE_FIRMWARE("radeon/R600_pfp.bin");
  48 MODULE_FIRMWARE("radeon/R600_me.bin");
  49 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
  50 MODULE_FIRMWARE("radeon/RV610_me.bin");
  51 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
  52 MODULE_FIRMWARE("radeon/RV630_me.bin");
  53 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
  54 MODULE_FIRMWARE("radeon/RV620_me.bin");
  55 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
  56 MODULE_FIRMWARE("radeon/RV635_me.bin");
  57 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
  58 MODULE_FIRMWARE("radeon/RV670_me.bin");
  59 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
  60 MODULE_FIRMWARE("radeon/RS780_me.bin");
  61 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
  62 MODULE_FIRMWARE("radeon/RV770_me.bin");
  63 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
  64 MODULE_FIRMWARE("radeon/RV730_me.bin");
  65 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
  66 MODULE_FIRMWARE("radeon/RV710_me.bin");
  67 MODULE_FIRMWARE("radeon/R600_rlc.bin");
  68 MODULE_FIRMWARE("radeon/R700_rlc.bin");
  69
  70 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
  71
  72 /* r600,rv610,rv630,rv620,rv635,rv670 */
  73 int r600_mc_wait_for_idle(struct radeon_device *rdev);
  74 void r600_gpu_init(struct radeon_device *rdev);
  75 void r600_fini(struct radeon_device *rdev);
  76
  77 /* hpd for digital panel detect/disconnect */
  78 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
  79 {
  80         bool connected = false;
  81
  82         if (ASIC_IS_DCE3(rdev)) {
  83                 switch (hpd) {
  84                 case RADEON_HPD_1:
  85                         if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
  86                                 connected = true;
  87                         break;
  88                 case RADEON_HPD_2:
  89                         if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
  90                                 connected = true;
  91                         break;
  92                 case RADEON_HPD_3:
  93                         if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
  94                                 connected = true;
  95                         break;
  96                 case RADEON_HPD_4:
  97                         if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
  98                                 connected = true;
  99                         break;
 100                         /* DCE 3.2 */
 101                 case RADEON_HPD_5:
 102                         if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 103                                 connected = true;
 104                         break;
 105                 case RADEON_HPD_6:
 106                         if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 107                                 connected = true;
 108                         break;
 109                 default:
 110                         break;
 111                 }
 112         } else {
 113                 switch (hpd) {
 114                 case RADEON_HPD_1:
 115                         if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 116                                 connected = true;
 117                         break;
 118                 case RADEON_HPD_2:
 119                         if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 120                                 connected = true;
 121                         break;
 122                 case RADEON_HPD_3:
 123                         if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 124                                 connected = true;
 125                         break;
 126                 default:
 127                         break;
 128                 }
 129         }
 130         return connected;
 131 }
 132
 133 void r600_hpd_set_polarity(struct radeon_device *rdev,
 134                            enum radeon_hpd_id hpd)
 135 {
 136         u32 tmp;
 137         bool connected = r600_hpd_sense(rdev, hpd);
 138
 139         if (ASIC_IS_DCE3(rdev)) {
 140                 switch (hpd) {
 141                 case RADEON_HPD_1:
 142                         tmp = RREG32(DC_HPD1_INT_CONTROL);
 143                         if (connected)
 144                                 tmp &= ~DC_HPDx_INT_POLARITY;
 145                         else
 146                                 tmp |= DC_HPDx_INT_POLARITY;
 147                         WREG32(DC_HPD1_INT_CONTROL, tmp);
 148                         break;
 149                 case RADEON_HPD_2:
 150                         tmp = RREG32(DC_HPD2_INT_CONTROL);
 151                         if (connected)
 152                                 tmp &= ~DC_HPDx_INT_POLARITY;
 153                         else
 154                                 tmp |= DC_HPDx_INT_POLARITY;
 155                         WREG32(DC_HPD2_INT_CONTROL, tmp);
 156                         break;
 157                 case RADEON_HPD_3:
 158                         tmp = RREG32(DC_HPD3_INT_CONTROL);
 159                         if (connected)
 160                                 tmp &= ~DC_HPDx_INT_POLARITY;
 161                         else
 162                                 tmp |= DC_HPDx_INT_POLARITY;
 163                         WREG32(DC_HPD3_INT_CONTROL, tmp);
 164                         break;
 165                 case RADEON_HPD_4:
 166                         tmp = RREG32(DC_HPD4_INT_CONTROL);
 167                         if (connected)
 168                                 tmp &= ~DC_HPDx_INT_POLARITY;
 169                         else
 170                                 tmp |= DC_HPDx_INT_POLARITY;
 171                         WREG32(DC_HPD4_INT_CONTROL, tmp);
 172                         break;
 173                 case RADEON_HPD_5:
 174                         tmp = RREG32(DC_HPD5_INT_CONTROL);
 175                         if (connected)
 176                                 tmp &= ~DC_HPDx_INT_POLARITY;
 177                         else
 178                                 tmp |= DC_HPDx_INT_POLARITY;
 179                         WREG32(DC_HPD5_INT_CONTROL, tmp);
 180                         break;
 181                         /* DCE 3.2 */
 182                 case RADEON_HPD_6:
 183                         tmp = RREG32(DC_HPD6_INT_CONTROL);
 184                         if (connected)
 185                                 tmp &= ~DC_HPDx_INT_POLARITY;
 186                         else
 187                                 tmp |= DC_HPDx_INT_POLARITY;
 188                         WREG32(DC_HPD6_INT_CONTROL, tmp);
 189                         break;
 190                 default:
 191                         break;
 192                 }
 193         } else {
 194                 switch (hpd) {
 195                 case RADEON_HPD_1:
 196                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
 197                         if (connected)
 198                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 199                         else
 200                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 201                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
 202                         break;
 203                 case RADEON_HPD_2:
 204                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
 205                         if (connected)
 206                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 207                         else
 208                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 209                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
 210                         break;
 211                 case RADEON_HPD_3:
 212                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
 213                         if (connected)
 214                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 215                         else
 216                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 217                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
 218                         break;
 219                 default:
 220                         break;
 221                 }
 222         }
 223 }
 224
 225 void r600_hpd_init(struct radeon_device *rdev)
 226 {
 227         struct drm_device *dev = rdev->ddev;
 228         struct drm_connector *connector;
 229
 230         if (ASIC_IS_DCE3(rdev)) {
 231                 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
 232                 if (ASIC_IS_DCE32(rdev))
 233                         tmp |= DC_HPDx_EN;
 234
 235                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 236                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 237                         switch (radeon_connector->hpd.hpd) {
 238                         case RADEON_HPD_1:
 239                                 WREG32(DC_HPD1_CONTROL, tmp);
 240                                 rdev->irq.hpd[0] = true;
 241                                 break;
 242                         case RADEON_HPD_2:
 243                                 WREG32(DC_HPD2_CONTROL, tmp);
 244                                 rdev->irq.hpd[1] = true;
 245                                 break;
 246                         case RADEON_HPD_3:
 247                                 WREG32(DC_HPD3_CONTROL, tmp);
 248                                 rdev->irq.hpd[2] = true;
 249                                 break;
 250                         case RADEON_HPD_4:
 251                                 WREG32(DC_HPD4_CONTROL, tmp);
 252                                 rdev->irq.hpd[3] = true;
 253                                 break;
 254                                 /* DCE 3.2 */
 255                         case RADEON_HPD_5:
 256                                 WREG32(DC_HPD5_CONTROL, tmp);
 257                                 rdev->irq.hpd[4] = true;
 258                                 break;
 259                         case RADEON_HPD_6:
 260                                 WREG32(DC_HPD6_CONTROL, tmp);
 261                                 rdev->irq.hpd[5] = true;
 262                                 break;
 263                         default:
 264                                 break;
 265                         }
 266                 }
 267         } else {
 268                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 269                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 270                         switch (radeon_connector->hpd.hpd) {
 271                         case RADEON_HPD_1:
 272                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 273                                 rdev->irq.hpd[0] = true;
 274                                 break;
 275                         case RADEON_HPD_2:
 276                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 277                                 rdev->irq.hpd[1] = true;
 278                                 break;
 279                         case RADEON_HPD_3:
 280                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 281                                 rdev->irq.hpd[2] = true;
 282                                 break;
 283                         default:
 284                                 break;
 285                         }
 286                 }
 287         }
 288         if (rdev->irq.installed)
 289                 r600_irq_set(rdev);
 290 }
 291
 292 void r600_hpd_fini(struct radeon_device *rdev)
 293 {
 294         struct drm_device *dev = rdev->ddev;
 295         struct drm_connector *connector;
 296
 297         if (ASIC_IS_DCE3(rdev)) {
 298                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 299                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 300                         switch (radeon_connector->hpd.hpd) {
 301                         case RADEON_HPD_1:
 302                                 WREG32(DC_HPD1_CONTROL, 0);
 303                                 rdev->irq.hpd[0] = false;
 304                                 break;
 305                         case RADEON_HPD_2:
 306                                 WREG32(DC_HPD2_CONTROL, 0);
 307                                 rdev->irq.hpd[1] = false;
 308                                 break;
 309                         case RADEON_HPD_3:
 310                                 WREG32(DC_HPD3_CONTROL, 0);
 311                                 rdev->irq.hpd[2] = false;
 312                                 break;
 313                         case RADEON_HPD_4:
 314                                 WREG32(DC_HPD4_CONTROL, 0);
 315                                 rdev->irq.hpd[3] = false;
 316                                 break;
 317                                 /* DCE 3.2 */
 318                         case RADEON_HPD_5:
 319                                 WREG32(DC_HPD5_CONTROL, 0);
 320                                 rdev->irq.hpd[4] = false;
 321                                 break;
 322                         case RADEON_HPD_6:
 323                                 WREG32(DC_HPD6_CONTROL, 0);
 324                                 rdev->irq.hpd[5] = false;
 325                                 break;
 326                         default:
 327                                 break;
 328                         }
 329                 }
 330         } else {
 331                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 332                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 333                         switch (radeon_connector->hpd.hpd) {
 334                         case RADEON_HPD_1:
 335                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
 336                                 rdev->irq.hpd[0] = false;
 337                                 break;
 338                         case RADEON_HPD_2:
 339                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
 340                                 rdev->irq.hpd[1] = false;
 341                                 break;
 342                         case RADEON_HPD_3:
 343                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
 344                                 rdev->irq.hpd[2] = false;
 345                                 break;
 346                         default:
 347                                 break;
 348                         }
 349                 }
 350         }
 351 }
 352
 353 /*
 354  * R600 PCIE GART
 355  */
 356 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
 357 {
 358         unsigned i;
 359         u32 tmp;
 360
 361         /* flush hdp cache so updates hit vram */
 362         WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
 363
 364         WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
 365         WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
 366         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
 367         for (i = 0; i < rdev->usec_timeout; i++) {
 368                 /* read MC_STATUS */
 369                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
 370                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
 371                 if (tmp == 2) {
 372                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
 373                         return;
 374                 }
 375                 if (tmp) {
 376                         return;
 377                 }
 378                 udelay(1);
 379         }
 380 }
 381
 382 int r600_pcie_gart_init(struct radeon_device *rdev)
 383 {
 384         int r;
 385
 386         if (rdev->gart.table.vram.robj) {
 387                 WARN(1, "R600 PCIE GART already initialized.\n");
 388                 return 0;
 389         }
 390         /* Initialize common gart structure */
 391         r = radeon_gart_init(rdev);
 392         if (r)
 393                 return r;
 394         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
 395         return radeon_gart_table_vram_alloc(rdev);
 396 }
 397
 398 int r600_pcie_gart_enable(struct radeon_device *rdev)
 399 {
 400         u32 tmp;
 401         int r, i;
 402
 403         if (rdev->gart.table.vram.robj == NULL) {
 404                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 405                 return -EINVAL;
 406         }
 407         r = radeon_gart_table_vram_pin(rdev);
 408         if (r)
 409                 return r;
 410         radeon_gart_restore(rdev);
 411
 412         /* Setup L2 cache */
 413         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 414                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 415                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 416         WREG32(VM_L2_CNTL2, 0);
 417         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 418         /* Setup TLB control */
 419         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 420                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 421                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 422                 ENABLE_WAIT_L2_QUERY;
 423         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 424         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 425         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
 426         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 427         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 428         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 429         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 430         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 431         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 432         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 433         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 434         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 435         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 436         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 437         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 438         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 439         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 440         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 441                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 442         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 443                         (u32)(rdev->dummy_page.addr >> 12));
 444         for (i = 1; i < 7; i++)
 445                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 446
 447         r600_pcie_gart_tlb_flush(rdev);
 448         rdev->gart.ready = true;
 449         return 0;
 450 }
 451
 452 void r600_pcie_gart_disable(struct radeon_device *rdev)
 453 {
 454         u32 tmp;
 455         int i, r;
 456
 457         /* Disable all tables */
 458         for (i = 0; i < 7; i++)
 459                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 460
 461         /* Disable L2 cache */
 462         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
 463                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 464         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 465         /* Setup L1 TLB control */
 466         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 467                 ENABLE_WAIT_L2_QUERY;
 468         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 469         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 470         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 471         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 472         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 473         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 474         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 475         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 476         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
 477         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
 478         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 479         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 480         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
 481         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 482         if (rdev->gart.table.vram.robj) {
 483                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
 484                 if (likely(r == 0)) {
 485                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
 486                         radeon_bo_unpin(rdev->gart.table.vram.robj);
 487                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
 488                 }
 489         }
 490 }
 491
 492 void r600_pcie_gart_fini(struct radeon_device *rdev)
 493 {
 494         r600_pcie_gart_disable(rdev);
 495         radeon_gart_table_vram_free(rdev);
 496         radeon_gart_fini(rdev);
 497 }
 498
 499 void r600_agp_enable(struct radeon_device *rdev)
 500 {
 501         u32 tmp;
 502         int i;
 503
 504         /* Setup L2 cache */
 505         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 506                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 507                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 508         WREG32(VM_L2_CNTL2, 0);
 509         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 510         /* Setup TLB control */
 511         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 512                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 513                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 514                 ENABLE_WAIT_L2_QUERY;
 515         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 516         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 517         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
 518         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 519         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 520         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 521         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 522         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 523         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 524         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 525         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 526         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 527         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 528         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 529         for (i = 0; i < 7; i++)
 530                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 531 }
 532
 533 int r600_mc_wait_for_idle(struct radeon_device *rdev)
 534 {
 535         unsigned i;
 536         u32 tmp;
 537
 538         for (i = 0; i < rdev->usec_timeout; i++) {
 539                 /* read MC_STATUS */
 540                 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
 541                 if (!tmp)
 542                         return 0;
 543                 udelay(1);
 544         }
 545         return -1;
 546 }
 547
 548 static void r600_mc_program(struct radeon_device *rdev)
 549 {
 550         struct rv515_mc_save save;
 551         u32 tmp;
 552         int i, j;
 553
 554         /* Initialize HDP */
 555         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
 556                 WREG32((0x2c14 + j), 0x00000000);
 557                 WREG32((0x2c18 + j), 0x00000000);
 558                 WREG32((0x2c1c + j), 0x00000000);
 559                 WREG32((0x2c20 + j), 0x00000000);
 560                 WREG32((0x2c24 + j), 0x00000000);
 561         }
 562         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
 563
 564         rv515_mc_stop(rdev, &save);
 565         if (r600_mc_wait_for_idle(rdev)) {
 566                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 567         }
 568         /* Lockout access through VGA aperture (doesn't exist before R600) */
 569         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
 570         /* Update configuration */
 571         if (rdev->flags & RADEON_IS_AGP) {
 572                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
 573                         /* VRAM before AGP */
 574                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 575                                 rdev->mc.vram_start >> 12);
 576                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 577                                 rdev->mc.gtt_end >> 12);
 578                 } else {
 579                         /* VRAM after AGP */
 580                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 581                                 rdev->mc.gtt_start >> 12);
 582                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 583                                 rdev->mc.vram_end >> 12);
 584                 }
 585         } else {
 586                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
 587                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
 588         }
 589         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
 590         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
 591         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
 592         WREG32(MC_VM_FB_LOCATION, tmp);
 593         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
 594         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
 595         WREG32(HDP_NONSURFACE_SIZE, rdev->mc.mc_vram_size | 0x3FF);
 596         if (rdev->flags & RADEON_IS_AGP) {
 597                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
 598                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
 599                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
 600         } else {
 601                 WREG32(MC_VM_AGP_BASE, 0);
 602                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
 603                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
 604         }
 605         if (r600_mc_wait_for_idle(rdev)) {
 606                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 607         }
 608         rv515_mc_resume(rdev, &save);
 609         /* we need to own VRAM, so turn off the VGA renderer here
 610          * to stop it overwriting our objects */
 611         rv515_vga_render_disable(rdev);
 612 }
 613
 614 int r600_mc_init(struct radeon_device *rdev)
 615 {
 616         fixed20_12 a;
 617         u32 tmp;
 618         int chansize, numchan;
 619
 620         /* Get VRAM informations */
 621         rdev->mc.vram_is_ddr = true;
 622         tmp = RREG32(RAMCFG);
 623         if (tmp & CHANSIZE_OVERRIDE) {
 624                 chansize = 16;
 625         } else if (tmp & CHANSIZE_MASK) {
 626                 chansize = 64;
 627         } else {
 628                 chansize = 32;
 629         }
 630         tmp = RREG32(CHMAP);
 631         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
 632         case 0:
 633         default:
 634                 numchan = 1;
 635                 break;
 636         case 1:
 637                 numchan = 2;
 638                 break;
 639         case 2:
 640                 numchan = 4;
 641                 break;
 642         case 3:
 643                 numchan = 8;
 644                 break;
 645         }
 646         rdev->mc.vram_width = numchan * chansize;
 647         /* Could aper size report 0 ? */
 648         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
 649         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
 650         /* Setup GPU memory space */
 651         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
 652         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
 653
 654         if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
 655                 rdev->mc.mc_vram_size = rdev->mc.aper_size;
 656
 657         if (rdev->mc.real_vram_size > rdev->mc.aper_size)
 658                 rdev->mc.real_vram_size = rdev->mc.aper_size;
 659
 660         if (rdev->flags & RADEON_IS_AGP) {
 661                 /* gtt_size is setup by radeon_agp_init */
 662                 rdev->mc.gtt_location = rdev->mc.agp_base;
 663                 tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
 664                 /* Try to put vram before or after AGP because we
 665                  * we want SYSTEM_APERTURE to cover both VRAM and
 666                  * AGP so that GPU can catch out of VRAM/AGP access
 667                  */
 668                 if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) {
 669                         /* Enought place before */
 670                         rdev->mc.vram_location = rdev->mc.gtt_location -
 671                                                         rdev->mc.mc_vram_size;
 672                 } else if (tmp > rdev->mc.mc_vram_size) {
 673                         /* Enought place after */
 674                         rdev->mc.vram_location = rdev->mc.gtt_location +
 675                                                         rdev->mc.gtt_size;
 676                 } else {
 677                         /* Try to setup VRAM then AGP might not
 678                          * not work on some card
 679                          */
 680                         rdev->mc.vram_location = 0x00000000UL;
 681                         rdev->mc.gtt_location = rdev->mc.mc_vram_size;
 682                 }
 683         } else {
 684                 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 685                 rdev->mc.vram_location = (RREG32(MC_VM_FB_LOCATION) &
 686                                                         0xFFFF) << 24;
 687                 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
 688                 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
 689                         /* Enough place after vram */
 690                         rdev->mc.gtt_location = tmp;
 691                 } else if (rdev->mc.vram_location >= rdev->mc.gtt_size) {
 692                         /* Enough place before vram */
 693                         rdev->mc.gtt_location = 0;
 694                 } else {
 695                         /* Not enough place after or before shrink
 696                          * gart size
 697                          */
 698                         if (rdev->mc.vram_location > (0xFFFFFFFFUL - tmp)) {
 699                                 rdev->mc.gtt_location = 0;
 700                                 rdev->mc.gtt_size = rdev->mc.vram_location;
 701                         } else {
 702                                 rdev->mc.gtt_location = tmp;
 703                                 rdev->mc.gtt_size = 0xFFFFFFFFUL - tmp;
 704                         }
 705                 }
 706                 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
 707         }
 708         rdev->mc.vram_start = rdev->mc.vram_location;
 709         rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
 710         rdev->mc.gtt_start = rdev->mc.gtt_location;
 711         rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
 712         /* FIXME: we should enforce default clock in case GPU is not in
 713          * default setup
 714          */
 715         a.full = rfixed_const(100);
 716         rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
 717         rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
 718
 719         if (rdev->flags & RADEON_IS_IGP)
 720                 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
 721
 722         return 0;
 723 }
 724
 725 /* We doesn't check that the GPU really needs a reset we simply do the
 726  * reset, it's up to the caller to determine if the GPU needs one. We
 727  * might add an helper function to check that.
 728  */
 729 int r600_gpu_soft_reset(struct radeon_device *rdev)
 730 {
 731         struct rv515_mc_save save;
 732         u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
 733                                 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
 734                                 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
 735                                 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
 736                                 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
 737                                 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
 738                                 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
 739                                 S_008010_GUI_ACTIVE(1);
 740         u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
 741                         S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
 742                         S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
 743                         S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
 744                         S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
 745                         S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
 746                         S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
 747                         S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
 748         u32 srbm_reset = 0;
 749         u32 tmp;
 750
 751         dev_info(rdev->dev, "GPU softreset \n");
 752         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
 753                 RREG32(R_008010_GRBM_STATUS));
 754         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
 755                 RREG32(R_008014_GRBM_STATUS2));
 756         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
 757                 RREG32(R_000E50_SRBM_STATUS));
 758         rv515_mc_stop(rdev, &save);
 759         if (r600_mc_wait_for_idle(rdev)) {
 760                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 761         }
 762         /* Disable CP parsing/prefetching */
 763         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(0xff));
 764         /* Check if any of the rendering block is busy and reset it */
 765         if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
 766             (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
 767                 tmp = S_008020_SOFT_RESET_CR(1) |
 768                         S_008020_SOFT_RESET_DB(1) |
 769                         S_008020_SOFT_RESET_CB(1) |
 770                         S_008020_SOFT_RESET_PA(1) |
 771                         S_008020_SOFT_RESET_SC(1) |
 772                         S_008020_SOFT_RESET_SMX(1) |
 773                         S_008020_SOFT_RESET_SPI(1) |
 774                         S_008020_SOFT_RESET_SX(1) |
 775                         S_008020_SOFT_RESET_SH(1) |
 776                         S_008020_SOFT_RESET_TC(1) |
 777                         S_008020_SOFT_RESET_TA(1) |
 778                         S_008020_SOFT_RESET_VC(1) |
 779                         S_008020_SOFT_RESET_VGT(1);
 780                 dev_info(rdev->dev, "  R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
 781                 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
 782                 (void)RREG32(R_008020_GRBM_SOFT_RESET);
 783                 udelay(50);
 784                 WREG32(R_008020_GRBM_SOFT_RESET, 0);
 785                 (void)RREG32(R_008020_GRBM_SOFT_RESET);
 786         }
 787         /* Reset CP (we always reset CP) */
 788         tmp = S_008020_SOFT_RESET_CP(1);
 789         dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
 790         WREG32(R_008020_GRBM_SOFT_RESET, tmp);
 791         (void)RREG32(R_008020_GRBM_SOFT_RESET);
 792         udelay(50);
 793         WREG32(R_008020_GRBM_SOFT_RESET, 0);
 794         (void)RREG32(R_008020_GRBM_SOFT_RESET);
 795         /* Reset others GPU block if necessary */
 796         if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 797                 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
 798         if (G_000E50_GRBM_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
 799                 srbm_reset |= S_000E60_SOFT_RESET_GRBM(1);
 800         if (G_000E50_HI_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
 801                 srbm_reset |= S_000E60_SOFT_RESET_IH(1);
 802         if (G_000E50_VMC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 803                 srbm_reset |= S_000E60_SOFT_RESET_VMC(1);
 804         if (G_000E50_MCB_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 805                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 806         if (G_000E50_MCDZ_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 807                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 808         if (G_000E50_MCDY_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 809                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 810         if (G_000E50_MCDX_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 811                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 812         if (G_000E50_MCDW_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 813                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 814         if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 815                 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
 816         if (G_000E50_SEM_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 817                 srbm_reset |= S_000E60_SOFT_RESET_SEM(1);
 818         if (G_000E50_BIF_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 819                 srbm_reset |= S_000E60_SOFT_RESET_BIF(1);
 820         dev_info(rdev->dev, "  R_000E60_SRBM_SOFT_RESET=0x%08X\n", srbm_reset);
 821         WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
 822         (void)RREG32(R_000E60_SRBM_SOFT_RESET);
 823         udelay(50);
 824         WREG32(R_000E60_SRBM_SOFT_RESET, 0);
 825         (void)RREG32(R_000E60_SRBM_SOFT_RESET);
 826         WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
 827         (void)RREG32(R_000E60_SRBM_SOFT_RESET);
 828         udelay(50);
 829         WREG32(R_000E60_SRBM_SOFT_RESET, 0);
 830         (void)RREG32(R_000E60_SRBM_SOFT_RESET);
 831         /* Wait a little for things to settle down */
 832         udelay(50);
 833         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
 834                 RREG32(R_008010_GRBM_STATUS));
 835         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
 836                 RREG32(R_008014_GRBM_STATUS2));
 837         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
 838                 RREG32(R_000E50_SRBM_STATUS));
 839         /* After reset we need to reinit the asic as GPU often endup in an
 840          * incoherent state.
 841          */
 842         atom_asic_init(rdev->mode_info.atom_context);
 843         rv515_mc_resume(rdev, &save);
 844         return 0;
 845 }
 846
 847 int r600_gpu_reset(struct radeon_device *rdev)
 848 {
 849         return r600_gpu_soft_reset(rdev);
 850 }
 851
 852 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
 853                                              u32 num_backends,
 854                                              u32 backend_disable_mask)
 855 {
 856         u32 backend_map = 0;
 857         u32 enabled_backends_mask;
 858         u32 enabled_backends_count;
 859         u32 cur_pipe;
 860         u32 swizzle_pipe[R6XX_MAX_PIPES];
 861         u32 cur_backend;
 862         u32 i;
 863
 864         if (num_tile_pipes > R6XX_MAX_PIPES)
 865                 num_tile_pipes = R6XX_MAX_PIPES;
 866         if (num_tile_pipes < 1)
 867                 num_tile_pipes = 1;
 868         if (num_backends > R6XX_MAX_BACKENDS)
 869                 num_backends = R6XX_MAX_BACKENDS;
 870         if (num_backends < 1)
 871                 num_backends = 1;
 872
 873         enabled_backends_mask = 0;
 874         enabled_backends_count = 0;
 875         for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
 876                 if (((backend_disable_mask >> i) & 1) == 0) {
 877                         enabled_backends_mask |= (1 << i);
 878                         ++enabled_backends_count;
 879                 }
 880                 if (enabled_backends_count == num_backends)
 881                         break;
 882         }
 883
 884         if (enabled_backends_count == 0) {
 885                 enabled_backends_mask = 1;
 886                 enabled_backends_count = 1;
 887         }
 888
 889         if (enabled_backends_count != num_backends)
 890                 num_backends = enabled_backends_count;
 891
 892         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
 893         switch (num_tile_pipes) {
 894         case 1:
 895                 swizzle_pipe[0] = 0;
 896                 break;
 897         case 2:
 898                 swizzle_pipe[0] = 0;
 899                 swizzle_pipe[1] = 1;
 900                 break;
 901         case 3:
 902                 swizzle_pipe[0] = 0;
 903                 swizzle_pipe[1] = 1;
 904                 swizzle_pipe[2] = 2;
 905                 break;
 906         case 4:
 907                 swizzle_pipe[0] = 0;
 908                 swizzle_pipe[1] = 1;
 909                 swizzle_pipe[2] = 2;
 910                 swizzle_pipe[3] = 3;
 911                 break;
 912         case 5:
 913                 swizzle_pipe[0] = 0;
 914                 swizzle_pipe[1] = 1;
 915                 swizzle_pipe[2] = 2;
 916                 swizzle_pipe[3] = 3;
 917                 swizzle_pipe[4] = 4;
 918                 break;
 919         case 6:
 920                 swizzle_pipe[0] = 0;
 921                 swizzle_pipe[1] = 2;
 922                 swizzle_pipe[2] = 4;
 923                 swizzle_pipe[3] = 5;
 924                 swizzle_pipe[4] = 1;
 925                 swizzle_pipe[5] = 3;
 926                 break;
 927         case 7:
 928                 swizzle_pipe[0] = 0;
 929                 swizzle_pipe[1] = 2;
 930                 swizzle_pipe[2] = 4;
 931                 swizzle_pipe[3] = 6;
 932                 swizzle_pipe[4] = 1;
 933                 swizzle_pipe[5] = 3;
 934                 swizzle_pipe[6] = 5;
 935                 break;
 936         case 8:
 937                 swizzle_pipe[0] = 0;
 938                 swizzle_pipe[1] = 2;
 939                 swizzle_pipe[2] = 4;
 940                 swizzle_pipe[3] = 6;
 941                 swizzle_pipe[4] = 1;
 942                 swizzle_pipe[5] = 3;
 943                 swizzle_pipe[6] = 5;
 944                 swizzle_pipe[7] = 7;
 945                 break;
 946         }
 947
 948         cur_backend = 0;
 949         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
 950                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
 951                         cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
 952
 953                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
 954
 955                 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
 956         }
 957
 958         return backend_map;
 959 }
 960
 961 int r600_count_pipe_bits(uint32_t val)
 962 {
 963         int i, ret = 0;
 964
 965         for (i = 0; i < 32; i++) {
 966                 ret += val & 1;
 967                 val >>= 1;
 968         }
 969         return ret;
 970 }
 971
 972 void r600_gpu_init(struct radeon_device *rdev)
 973 {
 974         u32 tiling_config;
 975         u32 ramcfg;
 976         u32 tmp;
 977         int i, j;
 978         u32 sq_config;
 979         u32 sq_gpr_resource_mgmt_1 = 0;
 980         u32 sq_gpr_resource_mgmt_2 = 0;
 981         u32 sq_thread_resource_mgmt = 0;
 982         u32 sq_stack_resource_mgmt_1 = 0;
 983         u32 sq_stack_resource_mgmt_2 = 0;
 984
 985         /* FIXME: implement */
 986         switch (rdev->family) {
 987         case CHIP_R600:
 988                 rdev->config.r600.max_pipes = 4;
 989                 rdev->config.r600.max_tile_pipes = 8;
 990                 rdev->config.r600.max_simds = 4;
 991                 rdev->config.r600.max_backends = 4;
 992                 rdev->config.r600.max_gprs = 256;
 993                 rdev->config.r600.max_threads = 192;
 994                 rdev->config.r600.max_stack_entries = 256;
 995                 rdev->config.r600.max_hw_contexts = 8;
 996                 rdev->config.r600.max_gs_threads = 16;
 997                 rdev->config.r600.sx_max_export_size = 128;
 998                 rdev->config.r600.sx_max_export_pos_size = 16;
 999                 rdev->config.r600.sx_max_export_smx_size = 128;
1000                 rdev->config.r600.sq_num_cf_insts = 2;
1001                 break;
1002         case CHIP_RV630:
1003         case CHIP_RV635:
1004                 rdev->config.r600.max_pipes = 2;
1005                 rdev->config.r600.max_tile_pipes = 2;
1006                 rdev->config.r600.max_simds = 3;
1007                 rdev->config.r600.max_backends = 1;
1008                 rdev->config.r600.max_gprs = 128;
1009                 rdev->config.r600.max_threads = 192;
1010                 rdev->config.r600.max_stack_entries = 128;
1011                 rdev->config.r600.max_hw_contexts = 8;
1012                 rdev->config.r600.max_gs_threads = 4;
1013                 rdev->config.r600.sx_max_export_size = 128;
1014                 rdev->config.r600.sx_max_export_pos_size = 16;
1015                 rdev->config.r600.sx_max_export_smx_size = 128;
1016                 rdev->config.r600.sq_num_cf_insts = 2;
1017                 break;
1018         case CHIP_RV610:
1019         case CHIP_RV620:
1020         case CHIP_RS780:
1021         case CHIP_RS880:
1022                 rdev->config.r600.max_pipes = 1;
1023                 rdev->config.r600.max_tile_pipes = 1;
1024                 rdev->config.r600.max_simds = 2;
1025                 rdev->config.r600.max_backends = 1;
1026                 rdev->config.r600.max_gprs = 128;
1027                 rdev->config.r600.max_threads = 192;
1028                 rdev->config.r600.max_stack_entries = 128;
1029                 rdev->config.r600.max_hw_contexts = 4;
1030                 rdev->config.r600.max_gs_threads = 4;
1031                 rdev->config.r600.sx_max_export_size = 128;
1032                 rdev->config.r600.sx_max_export_pos_size = 16;
1033                 rdev->config.r600.sx_max_export_smx_size = 128;
1034                 rdev->config.r600.sq_num_cf_insts = 1;
1035                 break;
1036         case CHIP_RV670:
1037                 rdev->config.r600.max_pipes = 4;
1038                 rdev->config.r600.max_tile_pipes = 4;
1039                 rdev->config.r600.max_simds = 4;
1040                 rdev->config.r600.max_backends = 4;
1041                 rdev->config.r600.max_gprs = 192;
1042                 rdev->config.r600.max_threads = 192;
1043                 rdev->config.r600.max_stack_entries = 256;
1044                 rdev->config.r600.max_hw_contexts = 8;
1045                 rdev->config.r600.max_gs_threads = 16;
1046                 rdev->config.r600.sx_max_export_size = 128;
1047                 rdev->config.r600.sx_max_export_pos_size = 16;
1048                 rdev->config.r600.sx_max_export_smx_size = 128;
1049                 rdev->config.r600.sq_num_cf_insts = 2;
1050                 break;
1051         default:
1052                 break;
1053         }
1054
1055         /* Initialize HDP */
1056         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1057                 WREG32((0x2c14 + j), 0x00000000);
1058                 WREG32((0x2c18 + j), 0x00000000);
1059                 WREG32((0x2c1c + j), 0x00000000);
1060                 WREG32((0x2c20 + j), 0x00000000);
1061                 WREG32((0x2c24 + j), 0x00000000);
1062         }
1063
1064         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1065
1066         /* Setup tiling */
1067         tiling_config = 0;
1068         ramcfg = RREG32(RAMCFG);
1069         switch (rdev->config.r600.max_tile_pipes) {
1070         case 1:
1071                 tiling_config |= PIPE_TILING(0);
1072                 rdev->config.r600.tiling_npipes = 1;
1073                 break;
1074         case 2:
1075                 tiling_config |= PIPE_TILING(1);
1076                 rdev->config.r600.tiling_npipes = 2;
1077                 break;
1078         case 4:
1079                 tiling_config |= PIPE_TILING(2);
1080                 rdev->config.r600.tiling_npipes = 4;
1081                 break;
1082         case 8:
1083                 tiling_config |= PIPE_TILING(3);
1084                 rdev->config.r600.tiling_npipes = 8;
1085                 break;
1086         default:
1087                 break;
1088         }
1089         rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1090         tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1091         tiling_config |= GROUP_SIZE(0);
1092         rdev->config.r600.tiling_group_size = 256;
1093         tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1094         if (tmp > 3) {
1095                 tiling_config |= ROW_TILING(3);
1096                 tiling_config |= SAMPLE_SPLIT(3);
1097         } else {
1098                 tiling_config |= ROW_TILING(tmp);
1099                 tiling_config |= SAMPLE_SPLIT(tmp);
1100         }
1101         tiling_config |= BANK_SWAPS(1);
1102         tmp = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1103                                                 rdev->config.r600.max_backends,
1104                                                 (0xff << rdev->config.r600.max_backends) & 0xff);
1105         tiling_config |= BACKEND_MAP(tmp);
1106         WREG32(GB_TILING_CONFIG, tiling_config);
1107         WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1108         WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1109
1110         tmp = BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1111         WREG32(CC_RB_BACKEND_DISABLE, tmp);
1112
1113         /* Setup pipes */
1114         tmp = INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1115         tmp |= INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1116         WREG32(CC_GC_SHADER_PIPE_CONFIG, tmp);
1117         WREG32(GC_USER_SHADER_PIPE_CONFIG, tmp);
1118
1119         tmp = R6XX_MAX_BACKENDS - r600_count_pipe_bits(tmp & INACTIVE_QD_PIPES_MASK);
1120         WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1121         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1122
1123         /* Setup some CP states */
1124         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1125         WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1126
1127         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1128                              SYNC_WALKER | SYNC_ALIGNER));
1129         /* Setup various GPU states */
1130         if (rdev->family == CHIP_RV670)
1131                 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1132
1133         tmp = RREG32(SX_DEBUG_1);
1134         tmp |= SMX_EVENT_RELEASE;
1135         if ((rdev->family > CHIP_R600))
1136                 tmp |= ENABLE_NEW_SMX_ADDRESS;
1137         WREG32(SX_DEBUG_1, tmp);
1138
1139         if (((rdev->family) == CHIP_R600) ||
1140             ((rdev->family) == CHIP_RV630) ||
1141             ((rdev->family) == CHIP_RV610) ||
1142             ((rdev->family) == CHIP_RV620) ||
1143             ((rdev->family) == CHIP_RS780) ||
1144             ((rdev->family) == CHIP_RS880)) {
1145                 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1146         } else {
1147                 WREG32(DB_DEBUG, 0);
1148         }
1149         WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1150                                DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1151
1152         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1153         WREG32(VGT_NUM_INSTANCES, 0);
1154
1155         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1156         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1157
1158         tmp = RREG32(SQ_MS_FIFO_SIZES);
1159         if (((rdev->family) == CHIP_RV610) ||
1160             ((rdev->family) == CHIP_RV620) ||
1161             ((rdev->family) == CHIP_RS780) ||
1162             ((rdev->family) == CHIP_RS880)) {
1163                 tmp = (CACHE_FIFO_SIZE(0xa) |
1164                        FETCH_FIFO_HIWATER(0xa) |
1165                        DONE_FIFO_HIWATER(0xe0) |
1166                        ALU_UPDATE_FIFO_HIWATER(0x8));
1167         } else if (((rdev->family) == CHIP_R600) ||
1168                    ((rdev->family) == CHIP_RV630)) {
1169                 tmp &= ~DONE_FIFO_HIWATER(0xff);
1170                 tmp |= DONE_FIFO_HIWATER(0x4);
1171         }
1172         WREG32(SQ_MS_FIFO_SIZES, tmp);
1173
1174         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1175          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
1176          */
1177         sq_config = RREG32(SQ_CONFIG);
1178         sq_config &= ~(PS_PRIO(3) |
1179                        VS_PRIO(3) |
1180                        GS_PRIO(3) |
1181                        ES_PRIO(3));
1182         sq_config |= (DX9_CONSTS |
1183                       VC_ENABLE |
1184                       PS_PRIO(0) |
1185                       VS_PRIO(1) |
1186                       GS_PRIO(2) |
1187                       ES_PRIO(3));
1188
1189         if ((rdev->family) == CHIP_R600) {
1190                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1191                                           NUM_VS_GPRS(124) |
1192                                           NUM_CLAUSE_TEMP_GPRS(4));
1193                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1194                                           NUM_ES_GPRS(0));
1195                 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1196                                            NUM_VS_THREADS(48) |
1197                                            NUM_GS_THREADS(4) |
1198                                            NUM_ES_THREADS(4));
1199                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1200                                             NUM_VS_STACK_ENTRIES(128));
1201                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1202                                             NUM_ES_STACK_ENTRIES(0));
1203         } else if (((rdev->family) == CHIP_RV610) ||
1204                    ((rdev->family) == CHIP_RV620) ||
1205                    ((rdev->family) == CHIP_RS780) ||
1206                    ((rdev->family) == CHIP_RS880)) {
1207                 /* no vertex cache */
1208                 sq_config &= ~VC_ENABLE;
1209
1210                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1211                                           NUM_VS_GPRS(44) |
1212                                           NUM_CLAUSE_TEMP_GPRS(2));
1213                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1214                                           NUM_ES_GPRS(17));
1215                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1216                                            NUM_VS_THREADS(78) |
1217                                            NUM_GS_THREADS(4) |
1218                                            NUM_ES_THREADS(31));
1219                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1220                                             NUM_VS_STACK_ENTRIES(40));
1221                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1222                                             NUM_ES_STACK_ENTRIES(16));
1223         } else if (((rdev->family) == CHIP_RV630) ||
1224                    ((rdev->family) == CHIP_RV635)) {
1225                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1226                                           NUM_VS_GPRS(44) |
1227                                           NUM_CLAUSE_TEMP_GPRS(2));
1228                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1229                                           NUM_ES_GPRS(18));
1230                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1231                                            NUM_VS_THREADS(78) |
1232                                            NUM_GS_THREADS(4) |
1233                                            NUM_ES_THREADS(31));
1234                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1235                                             NUM_VS_STACK_ENTRIES(40));
1236                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1237                                             NUM_ES_STACK_ENTRIES(16));
1238         } else if ((rdev->family) == CHIP_RV670) {
1239                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1240                                           NUM_VS_GPRS(44) |
1241                                           NUM_CLAUSE_TEMP_GPRS(2));
1242                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1243                                           NUM_ES_GPRS(17));
1244                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1245                                            NUM_VS_THREADS(78) |
1246                                            NUM_GS_THREADS(4) |
1247                                            NUM_ES_THREADS(31));
1248                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1249                                             NUM_VS_STACK_ENTRIES(64));
1250                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1251                                             NUM_ES_STACK_ENTRIES(64));
1252         }
1253
1254         WREG32(SQ_CONFIG, sq_config);
1255         WREG32(SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
1256         WREG32(SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
1257         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1258         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1259         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1260
1261         if (((rdev->family) == CHIP_RV610) ||
1262             ((rdev->family) == CHIP_RV620) ||
1263             ((rdev->family) == CHIP_RS780) ||
1264             ((rdev->family) == CHIP_RS880)) {
1265                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1266         } else {
1267                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1268         }
1269
1270         /* More default values. 2D/3D driver should adjust as needed */
1271         WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1272                                          S1_X(0x4) | S1_Y(0xc)));
1273         WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1274                                          S1_X(0x2) | S1_Y(0x2) |
1275                                          S2_X(0xa) | S2_Y(0x6) |
1276                                          S3_X(0x6) | S3_Y(0xa)));
1277         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1278                                              S1_X(0x4) | S1_Y(0xc) |
1279                                              S2_X(0x1) | S2_Y(0x6) |
1280                                              S3_X(0xa) | S3_Y(0xe)));
1281         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1282                                              S5_X(0x0) | S5_Y(0x0) |
1283                                              S6_X(0xb) | S6_Y(0x4) |
1284                                              S7_X(0x7) | S7_Y(0x8)));
1285
1286         WREG32(VGT_STRMOUT_EN, 0);
1287         tmp = rdev->config.r600.max_pipes * 16;
1288         switch (rdev->family) {
1289         case CHIP_RV610:
1290         case CHIP_RV620:
1291         case CHIP_RS780:
1292         case CHIP_RS880:
1293                 tmp += 32;
1294                 break;
1295         case CHIP_RV670:
1296                 tmp += 128;
1297                 break;
1298         default:
1299                 break;
1300         }
1301         if (tmp > 256) {
1302                 tmp = 256;
1303         }
1304         WREG32(VGT_ES_PER_GS, 128);
1305         WREG32(VGT_GS_PER_ES, tmp);
1306         WREG32(VGT_GS_PER_VS, 2);
1307         WREG32(VGT_GS_VERTEX_REUSE, 16);
1308
1309         /* more default values. 2D/3D driver should adjust as needed */
1310         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1311         WREG32(VGT_STRMOUT_EN, 0);
1312         WREG32(SX_MISC, 0);
1313         WREG32(PA_SC_MODE_CNTL, 0);
1314         WREG32(PA_SC_AA_CONFIG, 0);
1315         WREG32(PA_SC_LINE_STIPPLE, 0);
1316         WREG32(SPI_INPUT_Z, 0);
1317         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1318         WREG32(CB_COLOR7_FRAG, 0);
1319
1320         /* Clear render buffer base addresses */
1321         WREG32(CB_COLOR0_BASE, 0);
1322         WREG32(CB_COLOR1_BASE, 0);
1323         WREG32(CB_COLOR2_BASE, 0);
1324         WREG32(CB_COLOR3_BASE, 0);
1325         WREG32(CB_COLOR4_BASE, 0);
1326         WREG32(CB_COLOR5_BASE, 0);
1327         WREG32(CB_COLOR6_BASE, 0);
1328         WREG32(CB_COLOR7_BASE, 0);
1329         WREG32(CB_COLOR7_FRAG, 0);
1330
1331         switch (rdev->family) {
1332         case CHIP_RV610:
1333         case CHIP_RV620:
1334         case CHIP_RS780:
1335         case CHIP_RS880:
1336                 tmp = TC_L2_SIZE(8);
1337                 break;
1338         case CHIP_RV630:
1339         case CHIP_RV635:
1340                 tmp = TC_L2_SIZE(4);
1341                 break;
1342         case CHIP_R600:
1343                 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1344                 break;
1345         default:
1346                 tmp = TC_L2_SIZE(0);
1347                 break;
1348         }
1349         WREG32(TC_CNTL, tmp);
1350
1351         tmp = RREG32(HDP_HOST_PATH_CNTL);
1352         WREG32(HDP_HOST_PATH_CNTL, tmp);
1353
1354         tmp = RREG32(ARB_POP);
1355         tmp |= ENABLE_TC128;
1356         WREG32(ARB_POP, tmp);
1357
1358         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1359         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1360                                NUM_CLIP_SEQ(3)));
1361         WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1362 }
1363
1364
1365 /*
1366  * Indirect registers accessor
1367  */
1368 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1369 {
1370         u32 r;
1371
1372         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1373         (void)RREG32(PCIE_PORT_INDEX);
1374         r = RREG32(PCIE_PORT_DATA);
1375         return r;
1376 }
1377
1378 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1379 {
1380         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1381         (void)RREG32(PCIE_PORT_INDEX);
1382         WREG32(PCIE_PORT_DATA, (v));
1383         (void)RREG32(PCIE_PORT_DATA);
1384 }
1385
1386 /*
1387  * CP & Ring
1388  */
1389 void r600_cp_stop(struct radeon_device *rdev)
1390 {
1391         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1392 }
1393
1394 int r600_init_microcode(struct radeon_device *rdev)
1395 {
1396         struct platform_device *pdev;
1397         const char *chip_name;
1398         const char *rlc_chip_name;
1399         size_t pfp_req_size, me_req_size, rlc_req_size;
1400         char fw_name[30];
1401         int err;
1402
1403         DRM_DEBUG("\n");
1404
1405         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1406         err = IS_ERR(pdev);
1407         if (err) {
1408                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1409                 return -EINVAL;
1410         }
1411
1412         switch (rdev->family) {
1413         case CHIP_R600:
1414                 chip_name = "R600";
1415                 rlc_chip_name = "R600";
1416                 break;
1417         case CHIP_RV610:
1418                 chip_name = "RV610";
1419                 rlc_chip_name = "R600";
1420                 break;
1421         case CHIP_RV630:
1422                 chip_name = "RV630";
1423                 rlc_chip_name = "R600";
1424                 break;
1425         case CHIP_RV620:
1426                 chip_name = "RV620";
1427                 rlc_chip_name = "R600";
1428                 break;
1429         case CHIP_RV635:
1430                 chip_name = "RV635";
1431                 rlc_chip_name = "R600";
1432                 break;
1433         case CHIP_RV670:
1434                 chip_name = "RV670";
1435                 rlc_chip_name = "R600";
1436                 break;
1437         case CHIP_RS780:
1438         case CHIP_RS880:
1439                 chip_name = "RS780";
1440                 rlc_chip_name = "R600";
1441                 break;
1442         case CHIP_RV770:
1443                 chip_name = "RV770";
1444                 rlc_chip_name = "R700";
1445                 break;
1446         case CHIP_RV730:
1447         case CHIP_RV740:
1448                 chip_name = "RV730";
1449                 rlc_chip_name = "R700";
1450                 break;
1451         case CHIP_RV710:
1452                 chip_name = "RV710";
1453                 rlc_chip_name = "R700";
1454                 break;
1455         default: BUG();
1456         }
1457
1458         if (rdev->family >= CHIP_RV770) {
1459                 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
1460                 me_req_size = R700_PM4_UCODE_SIZE * 4;
1461                 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
1462         } else {
1463                 pfp_req_size = PFP_UCODE_SIZE * 4;
1464                 me_req_size = PM4_UCODE_SIZE * 12;
1465                 rlc_req_size = RLC_UCODE_SIZE * 4;
1466         }
1467
1468         DRM_INFO("Loading %s Microcode\n", chip_name);
1469
1470         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
1471         err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
1472         if (err)
1473                 goto out;
1474         if (rdev->pfp_fw->size != pfp_req_size) {
1475                 printk(KERN_ERR
1476                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1477                        rdev->pfp_fw->size, fw_name);
1478                 err = -EINVAL;
1479                 goto out;
1480         }
1481
1482         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
1483         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
1484         if (err)
1485                 goto out;
1486         if (rdev->me_fw->size != me_req_size) {
1487                 printk(KERN_ERR
1488                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1489                        rdev->me_fw->size, fw_name);
1490                 err = -EINVAL;
1491         }
1492
1493         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
1494         err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
1495         if (err)
1496                 goto out;
1497         if (rdev->rlc_fw->size != rlc_req_size) {
1498                 printk(KERN_ERR
1499                        "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
1500                        rdev->rlc_fw->size, fw_name);
1501                 err = -EINVAL;
1502         }
1503
1504 out:
1505         platform_device_unregister(pdev);
1506
1507         if (err) {
1508                 if (err != -EINVAL)
1509                         printk(KERN_ERR
1510                                "r600_cp: Failed to load firmware \"%s\"\n",
1511                                fw_name);
1512                 release_firmware(rdev->pfp_fw);
1513                 rdev->pfp_fw = NULL;
1514                 release_firmware(rdev->me_fw);
1515                 rdev->me_fw = NULL;
1516                 release_firmware(rdev->rlc_fw);
1517                 rdev->rlc_fw = NULL;
1518         }
1519         return err;
1520 }
1521
1522 static int r600_cp_load_microcode(struct radeon_device *rdev)
1523 {
1524         const __be32 *fw_data;
1525         int i;
1526
1527         if (!rdev->me_fw || !rdev->pfp_fw)
1528                 return -EINVAL;
1529
1530         r600_cp_stop(rdev);
1531
1532         WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1533
1534         /* Reset cp */
1535         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1536         RREG32(GRBM_SOFT_RESET);
1537         mdelay(15);
1538         WREG32(GRBM_SOFT_RESET, 0);
1539
1540         WREG32(CP_ME_RAM_WADDR, 0);
1541
1542         fw_data = (const __be32 *)rdev->me_fw->data;
1543         WREG32(CP_ME_RAM_WADDR, 0);
1544         for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
1545                 WREG32(CP_ME_RAM_DATA,
1546                        be32_to_cpup(fw_data++));
1547
1548         fw_data = (const __be32 *)rdev->pfp_fw->data;
1549         WREG32(CP_PFP_UCODE_ADDR, 0);
1550         for (i = 0; i < PFP_UCODE_SIZE; i++)
1551                 WREG32(CP_PFP_UCODE_DATA,
1552                        be32_to_cpup(fw_data++));
1553
1554         WREG32(CP_PFP_UCODE_ADDR, 0);
1555         WREG32(CP_ME_RAM_WADDR, 0);
1556         WREG32(CP_ME_RAM_RADDR, 0);
1557         return 0;
1558 }
1559
1560 int r600_cp_start(struct radeon_device *rdev)
1561 {
1562         int r;
1563         uint32_t cp_me;
1564
1565         r = radeon_ring_lock(rdev, 7);
1566         if (r) {
1567                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1568                 return r;
1569         }
1570         radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1571         radeon_ring_write(rdev, 0x1);
1572         if (rdev->family < CHIP_RV770) {
1573                 radeon_ring_write(rdev, 0x3);
1574                 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
1575         } else {
1576                 radeon_ring_write(rdev, 0x0);
1577                 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
1578         }
1579         radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1580         radeon_ring_write(rdev, 0);
1581         radeon_ring_write(rdev, 0);
1582         radeon_ring_unlock_commit(rdev);
1583
1584         cp_me = 0xff;
1585         WREG32(R_0086D8_CP_ME_CNTL, cp_me);
1586         return 0;
1587 }
1588
1589 int r600_cp_resume(struct radeon_device *rdev)
1590 {
1591         u32 tmp;
1592         u32 rb_bufsz;
1593         int r;
1594
1595         /* Reset cp */
1596         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1597         RREG32(GRBM_SOFT_RESET);
1598         mdelay(15);
1599         WREG32(GRBM_SOFT_RESET, 0);
1600
1601         /* Set ring buffer size */
1602         rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1603         tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1604 #ifdef __BIG_ENDIAN
1605         tmp |= BUF_SWAP_32BIT;
1606 #endif
1607         WREG32(CP_RB_CNTL, tmp);
1608         WREG32(CP_SEM_WAIT_TIMER, 0x4);
1609
1610         /* Set the write pointer delay */
1611         WREG32(CP_RB_WPTR_DELAY, 0);
1612
1613         /* Initialize the ring buffer's read and write pointers */
1614         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1615         WREG32(CP_RB_RPTR_WR, 0);
1616         WREG32(CP_RB_WPTR, 0);
1617         WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
1618         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
1619         mdelay(1);
1620         WREG32(CP_RB_CNTL, tmp);
1621
1622         WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1623         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1624
1625         rdev->cp.rptr = RREG32(CP_RB_RPTR);
1626         rdev->cp.wptr = RREG32(CP_RB_WPTR);
1627
1628         r600_cp_start(rdev);
1629         rdev->cp.ready = true;
1630         r = radeon_ring_test(rdev);
1631         if (r) {
1632                 rdev->cp.ready = false;
1633                 return r;
1634         }
1635         return 0;
1636 }
1637
1638 void r600_cp_commit(struct radeon_device *rdev)
1639 {
1640         WREG32(CP_RB_WPTR, rdev->cp.wptr);
1641         (void)RREG32(CP_RB_WPTR);
1642 }
1643
1644 void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
1645 {
1646         u32 rb_bufsz;
1647
1648         /* Align ring size */
1649         rb_bufsz = drm_order(ring_size / 8);
1650         ring_size = (1 << (rb_bufsz + 1)) * 4;
1651         rdev->cp.ring_size = ring_size;
1652         rdev->cp.align_mask = 16 - 1;
1653 }
1654
1655 void r600_cp_fini(struct radeon_device *rdev)
1656 {
1657         r600_cp_stop(rdev);
1658         radeon_ring_fini(rdev);
1659 }
1660
1661
1662 /*
1663  * GPU scratch registers helpers function.
1664  */
1665 void r600_scratch_init(struct radeon_device *rdev)
1666 {
1667         int i;
1668
1669         rdev->scratch.num_reg = 7;
1670         for (i = 0; i < rdev->scratch.num_reg; i++) {
1671                 rdev->scratch.free[i] = true;
1672                 rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4);
1673         }
1674 }
1675
1676 int r600_ring_test(struct radeon_device *rdev)
1677 {
1678         uint32_t scratch;
1679         uint32_t tmp = 0;
1680         unsigned i;
1681         int r;
1682
1683         r = radeon_scratch_get(rdev, &scratch);
1684         if (r) {
1685                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
1686                 return r;
1687         }
1688         WREG32(scratch, 0xCAFEDEAD);
1689         r = radeon_ring_lock(rdev, 3);
1690         if (r) {
1691                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1692                 radeon_scratch_free(rdev, scratch);
1693                 return r;
1694         }
1695         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1696         radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1697         radeon_ring_write(rdev, 0xDEADBEEF);
1698         radeon_ring_unlock_commit(rdev);
1699         for (i = 0; i < rdev->usec_timeout; i++) {
1700                 tmp = RREG32(scratch);
1701                 if (tmp == 0xDEADBEEF)
1702                         break;
1703                 DRM_UDELAY(1);
1704         }
1705         if (i < rdev->usec_timeout) {
1706                 DRM_INFO("ring test succeeded in %d usecs\n", i);
1707         } else {
1708                 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
1709                           scratch, tmp);
1710                 r = -EINVAL;
1711         }
1712         radeon_scratch_free(rdev, scratch);
1713         return r;
1714 }
1715
1716 void r600_wb_disable(struct radeon_device *rdev)
1717 {
1718         int r;
1719
1720         WREG32(SCRATCH_UMSK, 0);
1721         if (rdev->wb.wb_obj) {
1722                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
1723                 if (unlikely(r != 0))
1724                         return;
1725                 radeon_bo_kunmap(rdev->wb.wb_obj);
1726                 radeon_bo_unpin(rdev->wb.wb_obj);
1727                 radeon_bo_unreserve(rdev->wb.wb_obj);
1728         }
1729 }
1730
1731 void r600_wb_fini(struct radeon_device *rdev)
1732 {
1733         r600_wb_disable(rdev);
1734         if (rdev->wb.wb_obj) {
1735                 radeon_bo_unref(&rdev->wb.wb_obj);
1736                 rdev->wb.wb = NULL;
1737                 rdev->wb.wb_obj = NULL;
1738         }
1739 }
1740
1741 int r600_wb_enable(struct radeon_device *rdev)
1742 {
1743         int r;
1744
1745         if (rdev->wb.wb_obj == NULL) {
1746                 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
1747                                 RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj);
1748                 if (r) {
1749                         dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
1750                         return r;
1751                 }
1752                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
1753                 if (unlikely(r != 0)) {
1754                         r600_wb_fini(rdev);
1755                         return r;
1756                 }
1757                 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
1758                                 &rdev->wb.gpu_addr);
1759                 if (r) {
1760                         radeon_bo_unreserve(rdev->wb.wb_obj);
1761                         dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
1762                         r600_wb_fini(rdev);
1763                         return r;
1764                 }
1765                 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
1766                 radeon_bo_unreserve(rdev->wb.wb_obj);
1767                 if (r) {
1768                         dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
1769                         r600_wb_fini(rdev);
1770                         return r;
1771                 }
1772         }
1773         WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF);
1774         WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC);
1775         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF);
1776         WREG32(SCRATCH_UMSK, 0xff);
1777         return 0;
1778 }
1779
1780 void r600_fence_ring_emit(struct radeon_device *rdev,
1781                           struct radeon_fence *fence)
1782 {
1783         /* Also consider EVENT_WRITE_EOP.  it handles the interrupts + timestamps + events */
1784
1785         radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
1786         radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT);
1787         /* wait for 3D idle clean */
1788         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1789         radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
1790         radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
1791         /* Emit fence sequence & fire IRQ */
1792         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1793         radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1794         radeon_ring_write(rdev, fence->seq);
1795         /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
1796         radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
1797         radeon_ring_write(rdev, RB_INT_STAT);
1798 }
1799
1800 int r600_copy_blit(struct radeon_device *rdev,
1801                    uint64_t src_offset, uint64_t dst_offset,
1802                    unsigned num_pages, struct radeon_fence *fence)
1803 {
1804         int r;
1805
1806         mutex_lock(&rdev->r600_blit.mutex);
1807         rdev->r600_blit.vb_ib = NULL;
1808         r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
1809         if (r) {
1810                 if (rdev->r600_blit.vb_ib)
1811                         radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
1812                 mutex_unlock(&rdev->r600_blit.mutex);
1813                 return r;
1814         }
1815         r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
1816         r600_blit_done_copy(rdev, fence);
1817         mutex_unlock(&rdev->r600_blit.mutex);
1818         return 0;
1819 }
1820
1821 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
1822                          uint32_t tiling_flags, uint32_t pitch,
1823                          uint32_t offset, uint32_t obj_size)
1824 {
1825         /* FIXME: implement */
1826         return 0;
1827 }
1828
1829 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
1830 {
1831         /* FIXME: implement */
1832 }
1833
1834
1835 bool r600_card_posted(struct radeon_device *rdev)
1836 {
1837         uint32_t reg;
1838
1839         /* first check CRTCs */
1840         reg = RREG32(D1CRTC_CONTROL) |
1841                 RREG32(D2CRTC_CONTROL);
1842         if (reg & CRTC_EN)
1843                 return true;
1844
1845         /* then check MEM_SIZE, in case the crtcs are off */
1846         if (RREG32(CONFIG_MEMSIZE))
1847                 return true;
1848
1849         return false;
1850 }
1851
1852 int r600_startup(struct radeon_device *rdev)
1853 {
1854         int r;
1855
1856         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1857                 r = r600_init_microcode(rdev);
1858                 if (r) {
1859                         DRM_ERROR("Failed to load firmware!\n");
1860                         return r;
1861                 }
1862         }
1863
1864         r600_mc_program(rdev);
1865         if (rdev->flags & RADEON_IS_AGP) {
1866                 r600_agp_enable(rdev);
1867         } else {
1868                 r = r600_pcie_gart_enable(rdev);
1869                 if (r)
1870                         return r;
1871         }
1872         r600_gpu_init(rdev);
1873         r = r600_blit_init(rdev);
1874         if (r) {
1875                 r600_blit_fini(rdev);
1876                 rdev->asic->copy = NULL;
1877                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1878         }
1879         /* pin copy shader into vram */
1880         if (rdev->r600_blit.shader_obj) {
1881                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1882                 if (unlikely(r != 0))
1883                         return r;
1884                 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
1885                                 &rdev->r600_blit.shader_gpu_addr);
1886                 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1887                 if (r) {
1888                         dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
1889                         return r;
1890                 }
1891         }
1892         /* Enable IRQ */
1893         r = r600_irq_init(rdev);
1894         if (r) {
1895                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1896                 radeon_irq_kms_fini(rdev);
1897                 return r;
1898         }
1899         r600_irq_set(rdev);
1900
1901         r = radeon_ring_init(rdev, rdev->cp.ring_size);
1902         if (r)
1903                 return r;
1904         r = r600_cp_load_microcode(rdev);
1905         if (r)
1906                 return r;
1907         r = r600_cp_resume(rdev);
1908         if (r)
1909                 return r;
1910         /* write back buffer are not vital so don't worry about failure */
1911         r600_wb_enable(rdev);
1912         return 0;
1913 }
1914
1915 void r600_vga_set_state(struct radeon_device *rdev, bool state)
1916 {
1917         uint32_t temp;
1918
1919         temp = RREG32(CONFIG_CNTL);
1920         if (state == false) {
1921                 temp &= ~(1<<0);
1922                 temp |= (1<<1);
1923         } else {
1924                 temp &= ~(1<<1);
1925         }
1926         WREG32(CONFIG_CNTL, temp);
1927 }
1928
1929 int r600_resume(struct radeon_device *rdev)
1930 {
1931         int r;
1932
1933         /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
1934          * posting will perform necessary task to bring back GPU into good
1935          * shape.
1936          */
1937         /* post card */
1938         atom_asic_init(rdev->mode_info.atom_context);
1939         /* Initialize clocks */
1940         r = radeon_clocks_init(rdev);
1941         if (r) {
1942                 return r;
1943         }
1944
1945         r = r600_startup(rdev);
1946         if (r) {
1947                 DRM_ERROR("r600 startup failed on resume\n");
1948                 return r;
1949         }
1950
1951         r = r600_ib_test(rdev);
1952         if (r) {
1953                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1954                 return r;
1955         }
1956         return r;
1957 }
1958
1959 int r600_suspend(struct radeon_device *rdev)
1960 {
1961         int r;
1962
1963         /* FIXME: we should wait for ring to be empty */
1964         r600_cp_stop(rdev);
1965         rdev->cp.ready = false;
1966         r600_irq_suspend(rdev);
1967         r600_wb_disable(rdev);
1968         r600_pcie_gart_disable(rdev);
1969         /* unpin shaders bo */
1970         if (rdev->r600_blit.shader_obj) {
1971                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1972                 if (!r) {
1973                         radeon_bo_unpin(rdev->r600_blit.shader_obj);
1974                         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1975                 }
1976         }
1977         return 0;
1978 }
1979
1980 /* Plan is to move initialization in that function and use
1981  * helper function so that radeon_device_init pretty much
1982  * do nothing more than calling asic specific function. This
1983  * should also allow to remove a bunch of callback function
1984  * like vram_info.
1985  */
1986 int r600_init(struct radeon_device *rdev)
1987 {
1988         int r;
1989
1990         r = radeon_dummy_page_init(rdev);
1991         if (r)
1992                 return r;
1993         if (r600_debugfs_mc_info_init(rdev)) {
1994                 DRM_ERROR("Failed to register debugfs file for mc !\n");
1995         }
1996         /* This don't do much */
1997         r = radeon_gem_init(rdev);
1998         if (r)
1999                 return r;
2000         /* Read BIOS */
2001         if (!radeon_get_bios(rdev)) {
2002                 if (ASIC_IS_AVIVO(rdev))
2003                         return -EINVAL;
2004         }
2005         /* Must be an ATOMBIOS */
2006         if (!rdev->is_atom_bios) {
2007                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2008                 return -EINVAL;
2009         }
2010         r = radeon_atombios_init(rdev);
2011         if (r)
2012                 return r;
2013         /* Post card if necessary */
2014         if (!r600_card_posted(rdev)) {
2015                 if (!rdev->bios) {
2016                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2017                         return -EINVAL;
2018                 }
2019                 DRM_INFO("GPU not posted. posting now...\n");
2020                 atom_asic_init(rdev->mode_info.atom_context);
2021         }
2022         /* Initialize scratch registers */
2023         r600_scratch_init(rdev);
2024         /* Initialize surface registers */
2025         radeon_surface_init(rdev);
2026         /* Initialize clocks */
2027         radeon_get_clock_info(rdev->ddev);
2028         r = radeon_clocks_init(rdev);
2029         if (r)
2030                 return r;
2031         /* Initialize power management */
2032         radeon_pm_init(rdev);
2033         /* Fence driver */
2034         r = radeon_fence_driver_init(rdev);
2035         if (r)
2036                 return r;
2037         if (rdev->flags & RADEON_IS_AGP) {
2038                 r = radeon_agp_init(rdev);
2039                 if (r)
2040                         radeon_agp_disable(rdev);
2041         }
2042         r = r600_mc_init(rdev);
2043         if (r)
2044                 return r;
2045         /* Memory manager */
2046         r = radeon_bo_init(rdev);
2047         if (r)
2048                 return r;
2049
2050         r = radeon_irq_kms_init(rdev);
2051         if (r)
2052                 return r;
2053
2054         rdev->cp.ring_obj = NULL;
2055         r600_ring_init(rdev, 1024 * 1024);
2056
2057         rdev->ih.ring_obj = NULL;
2058         r600_ih_ring_init(rdev, 64 * 1024);
2059
2060         r = r600_pcie_gart_init(rdev);
2061         if (r)
2062                 return r;
2063
2064         rdev->accel_working = true;
2065         r = r600_startup(rdev);
2066         if (r) {
2067                 dev_err(rdev->dev, "disabling GPU acceleration\n");
2068                 r600_cp_fini(rdev);
2069                 r600_wb_fini(rdev);
2070                 r600_irq_fini(rdev);
2071                 radeon_irq_kms_fini(rdev);
2072                 r600_pcie_gart_fini(rdev);
2073                 rdev->accel_working = false;
2074         }
2075         if (rdev->accel_working) {
2076                 r = radeon_ib_pool_init(rdev);
2077                 if (r) {
2078                         dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2079                         rdev->accel_working = false;
2080                 } else {
2081                         r = r600_ib_test(rdev);
2082                         if (r) {
2083                                 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2084                                 rdev->accel_working = false;
2085                         }
2086                 }
2087         }
2088
2089         r = r600_audio_init(rdev);
2090         if (r)
2091                 return r; /* TODO error handling */
2092         return 0;
2093 }
2094
2095 void r600_fini(struct radeon_device *rdev)
2096 {
2097         r600_audio_fini(rdev);
2098         r600_blit_fini(rdev);
2099         r600_cp_fini(rdev);
2100         r600_wb_fini(rdev);
2101         r600_irq_fini(rdev);
2102         radeon_irq_kms_fini(rdev);
2103         r600_pcie_gart_fini(rdev);
2104         radeon_agp_fini(rdev);
2105         radeon_gem_fini(rdev);
2106         radeon_fence_driver_fini(rdev);
2107         radeon_clocks_fini(rdev);
2108         radeon_bo_fini(rdev);
2109         radeon_atombios_fini(rdev);
2110         kfree(rdev->bios);
2111         rdev->bios = NULL;
2112         radeon_dummy_page_fini(rdev);
2113 }
2114
2115
2116 /*
2117  * CS stuff
2118  */
2119 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2120 {
2121         /* FIXME: implement */
2122         radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2123         radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
2124         radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
2125         radeon_ring_write(rdev, ib->length_dw);
2126 }
2127
2128 int r600_ib_test(struct radeon_device *rdev)
2129 {
2130         struct radeon_ib *ib;
2131         uint32_t scratch;
2132         uint32_t tmp = 0;
2133         unsigned i;
2134         int r;
2135
2136         r = radeon_scratch_get(rdev, &scratch);
2137         if (r) {
2138                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2139                 return r;
2140         }
2141         WREG32(scratch, 0xCAFEDEAD);
2142         r = radeon_ib_get(rdev, &ib);
2143         if (r) {
2144                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2145                 return r;
2146         }
2147         ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2148         ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2149         ib->ptr[2] = 0xDEADBEEF;
2150         ib->ptr[3] = PACKET2(0);
2151         ib->ptr[4] = PACKET2(0);
2152         ib->ptr[5] = PACKET2(0);
2153         ib->ptr[6] = PACKET2(0);
2154         ib->ptr[7] = PACKET2(0);
2155         ib->ptr[8] = PACKET2(0);
2156         ib->ptr[9] = PACKET2(0);
2157         ib->ptr[10] = PACKET2(0);
2158         ib->ptr[11] = PACKET2(0);
2159         ib->ptr[12] = PACKET2(0);
2160         ib->ptr[13] = PACKET2(0);
2161         ib->ptr[14] = PACKET2(0);
2162         ib->ptr[15] = PACKET2(0);
2163         ib->length_dw = 16;
2164         r = radeon_ib_schedule(rdev, ib);
2165         if (r) {
2166                 radeon_scratch_free(rdev, scratch);
2167                 radeon_ib_free(rdev, &ib);
2168                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2169                 return r;
2170         }
2171         r = radeon_fence_wait(ib->fence, false);
2172         if (r) {
2173                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2174                 return r;
2175         }
2176         for (i = 0; i < rdev->usec_timeout; i++) {
2177                 tmp = RREG32(scratch);
2178                 if (tmp == 0xDEADBEEF)
2179                         break;
2180                 DRM_UDELAY(1);
2181         }
2182         if (i < rdev->usec_timeout) {
2183                 DRM_INFO("ib test succeeded in %u usecs\n", i);
2184         } else {
2185                 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
2186                           scratch, tmp);
2187                 r = -EINVAL;
2188         }
2189         radeon_scratch_free(rdev, scratch);
2190         radeon_ib_free(rdev, &ib);
2191         return r;
2192 }
2193
2194 /*
2195  * Interrupts
2196  *
2197  * Interrupts use a ring buffer on r6xx/r7xx hardware.  It works pretty
2198  * the same as the CP ring buffer, but in reverse.  Rather than the CPU
2199  * writing to the ring and the GPU consuming, the GPU writes to the ring
2200  * and host consumes.  As the host irq handler processes interrupts, it
2201  * increments the rptr.  When the rptr catches up with the wptr, all the
2202  * current interrupts have been processed.
2203  */
2204
2205 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2206 {
2207         u32 rb_bufsz;
2208
2209         /* Align ring size */
2210         rb_bufsz = drm_order(ring_size / 4);
2211         ring_size = (1 << rb_bufsz) * 4;
2212         rdev->ih.ring_size = ring_size;
2213         rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2214         rdev->ih.rptr = 0;
2215 }
2216
2217 static int r600_ih_ring_alloc(struct radeon_device *rdev)
2218 {
2219         int r;
2220
2221         /* Allocate ring buffer */
2222         if (rdev->ih.ring_obj == NULL) {
2223                 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size,
2224                                      true,
2225                                      RADEON_GEM_DOMAIN_GTT,
2226                                      &rdev->ih.ring_obj);
2227                 if (r) {
2228                         DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2229                         return r;
2230                 }
2231                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2232                 if (unlikely(r != 0))
2233                         return r;
2234                 r = radeon_bo_pin(rdev->ih.ring_obj,
2235                                   RADEON_GEM_DOMAIN_GTT,
2236                                   &rdev->ih.gpu_addr);
2237                 if (r) {
2238                         radeon_bo_unreserve(rdev->ih.ring_obj);
2239                         DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2240                         return r;
2241                 }
2242                 r = radeon_bo_kmap(rdev->ih.ring_obj,
2243                                    (void **)&rdev->ih.ring);
2244                 radeon_bo_unreserve(rdev->ih.ring_obj);
2245                 if (r) {
2246                         DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2247                         return r;
2248                 }
2249         }
2250         return 0;
2251 }
2252
2253 static void r600_ih_ring_fini(struct radeon_device *rdev)
2254 {
2255         int r;
2256         if (rdev->ih.ring_obj) {
2257                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2258                 if (likely(r == 0)) {
2259                         radeon_bo_kunmap(rdev->ih.ring_obj);
2260                         radeon_bo_unpin(rdev->ih.ring_obj);
2261                         radeon_bo_unreserve(rdev->ih.ring_obj);
2262                 }
2263                 radeon_bo_unref(&rdev->ih.ring_obj);
2264                 rdev->ih.ring = NULL;
2265                 rdev->ih.ring_obj = NULL;
2266         }
2267 }
2268
2269 static void r600_rlc_stop(struct radeon_device *rdev)
2270 {
2271
2272         if (rdev->family >= CHIP_RV770) {
2273                 /* r7xx asics need to soft reset RLC before halting */
2274                 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2275                 RREG32(SRBM_SOFT_RESET);
2276                 udelay(15000);
2277                 WREG32(SRBM_SOFT_RESET, 0);
2278                 RREG32(SRBM_SOFT_RESET);
2279         }
2280
2281         WREG32(RLC_CNTL, 0);
2282 }
2283
2284 static void r600_rlc_start(struct radeon_device *rdev)
2285 {
2286         WREG32(RLC_CNTL, RLC_ENABLE);
2287 }
2288
2289 static int r600_rlc_init(struct radeon_device *rdev)
2290 {
2291         u32 i;
2292         const __be32 *fw_data;
2293
2294         if (!rdev->rlc_fw)
2295                 return -EINVAL;
2296
2297         r600_rlc_stop(rdev);
2298
2299         WREG32(RLC_HB_BASE, 0);
2300         WREG32(RLC_HB_CNTL, 0);
2301         WREG32(RLC_HB_RPTR, 0);
2302         WREG32(RLC_HB_WPTR, 0);
2303         WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2304         WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2305         WREG32(RLC_MC_CNTL, 0);
2306         WREG32(RLC_UCODE_CNTL, 0);
2307
2308         fw_data = (const __be32 *)rdev->rlc_fw->data;
2309         if (rdev->family >= CHIP_RV770) {
2310                 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2311                         WREG32(RLC_UCODE_ADDR, i);
2312                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2313                 }
2314         } else {
2315                 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2316                         WREG32(RLC_UCODE_ADDR, i);
2317                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2318                 }
2319         }
2320         WREG32(RLC_UCODE_ADDR, 0);
2321
2322         r600_rlc_start(rdev);
2323
2324         return 0;
2325 }
2326
2327 static void r600_enable_interrupts(struct radeon_device *rdev)
2328 {
2329         u32 ih_cntl = RREG32(IH_CNTL);
2330         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2331
2332         ih_cntl |= ENABLE_INTR;
2333         ih_rb_cntl |= IH_RB_ENABLE;
2334         WREG32(IH_CNTL, ih_cntl);
2335         WREG32(IH_RB_CNTL, ih_rb_cntl);
2336         rdev->ih.enabled = true;
2337 }
2338
2339 static void r600_disable_interrupts(struct radeon_device *rdev)
2340 {
2341         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2342         u32 ih_cntl = RREG32(IH_CNTL);
2343
2344         ih_rb_cntl &= ~IH_RB_ENABLE;
2345         ih_cntl &= ~ENABLE_INTR;
2346         WREG32(IH_RB_CNTL, ih_rb_cntl);
2347         WREG32(IH_CNTL, ih_cntl);
2348         /* set rptr, wptr to 0 */
2349         WREG32(IH_RB_RPTR, 0);
2350         WREG32(IH_RB_WPTR, 0);
2351         rdev->ih.enabled = false;
2352         rdev->ih.wptr = 0;
2353         rdev->ih.rptr = 0;
2354 }
2355
2356 static void r600_disable_interrupt_state(struct radeon_device *rdev)
2357 {
2358         u32 tmp;
2359
2360         WREG32(CP_INT_CNTL, 0);
2361         WREG32(GRBM_INT_CNTL, 0);
2362         WREG32(DxMODE_INT_MASK, 0);
2363         if (ASIC_IS_DCE3(rdev)) {
2364                 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2365                 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2366                 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2367                 WREG32(DC_HPD1_INT_CONTROL, tmp);
2368                 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2369                 WREG32(DC_HPD2_INT_CONTROL, tmp);
2370                 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2371                 WREG32(DC_HPD3_INT_CONTROL, tmp);
2372                 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2373                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2374                 if (ASIC_IS_DCE32(rdev)) {
2375                         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2376                         WREG32(DC_HPD5_INT_CONTROL, 0);
2377                         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2378                         WREG32(DC_HPD6_INT_CONTROL, 0);
2379                 }
2380         } else {
2381                 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2382                 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2383                 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2384                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, 0);
2385                 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2386                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, 0);
2387                 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2388                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, 0);
2389         }
2390 }
2391
2392 int r600_irq_init(struct radeon_device *rdev)
2393 {
2394         int ret = 0;
2395         int rb_bufsz;
2396         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2397
2398         /* allocate ring */
2399         ret = r600_ih_ring_alloc(rdev);
2400         if (ret)
2401                 return ret;
2402
2403         /* disable irqs */
2404         r600_disable_interrupts(rdev);
2405
2406         /* init rlc */
2407         ret = r600_rlc_init(rdev);
2408         if (ret) {
2409                 r600_ih_ring_fini(rdev);
2410                 return ret;
2411         }
2412
2413         /* setup interrupt control */
2414         /* set dummy read address to ring address */
2415         WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2416         interrupt_cntl = RREG32(INTERRUPT_CNTL);
2417         /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2418          * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2419          */
2420         interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
2421         /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2422         interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
2423         WREG32(INTERRUPT_CNTL, interrupt_cntl);
2424
2425         WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
2426         rb_bufsz = drm_order(rdev->ih.ring_size / 4);
2427
2428         ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
2429                       IH_WPTR_OVERFLOW_CLEAR |
2430                       (rb_bufsz << 1));
2431         /* WPTR writeback, not yet */
2432         /*ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;*/
2433         WREG32(IH_RB_WPTR_ADDR_LO, 0);
2434         WREG32(IH_RB_WPTR_ADDR_HI, 0);
2435
2436         WREG32(IH_RB_CNTL, ih_rb_cntl);
2437
2438         /* set rptr, wptr to 0 */
2439         WREG32(IH_RB_RPTR, 0);
2440         WREG32(IH_RB_WPTR, 0);
2441
2442         /* Default settings for IH_CNTL (disabled at first) */
2443         ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2444         /* RPTR_REARM only works if msi's are enabled */
2445         if (rdev->msi_enabled)
2446                 ih_cntl |= RPTR_REARM;
2447
2448 #ifdef __BIG_ENDIAN
2449         ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT);
2450 #endif
2451         WREG32(IH_CNTL, ih_cntl);
2452
2453         /* force the active interrupt state to all disabled */
2454         r600_disable_interrupt_state(rdev);
2455
2456         /* enable irqs */
2457         r600_enable_interrupts(rdev);
2458
2459         return ret;
2460 }
2461
2462 void r600_irq_suspend(struct radeon_device *rdev)
2463 {
2464         r600_disable_interrupts(rdev);
2465         r600_rlc_stop(rdev);
2466 }
2467
2468 void r600_irq_fini(struct radeon_device *rdev)
2469 {
2470         r600_irq_suspend(rdev);
2471         r600_ih_ring_fini(rdev);
2472 }
2473
2474 int r600_irq_set(struct radeon_device *rdev)
2475 {
2476         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2477         u32 mode_int = 0;
2478         u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
2479
2480         if (!rdev->irq.installed) {
2481                 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
2482                 return -EINVAL;
2483         }
2484         /* don't enable anything if the ih is disabled */
2485         if (!rdev->ih.enabled) {
2486                 r600_disable_interrupts(rdev);
2487                 /* force the active interrupt state to all disabled */
2488                 r600_disable_interrupt_state(rdev);
2489                 return 0;
2490         }
2491
2492         if (ASIC_IS_DCE3(rdev)) {
2493                 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2494                 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2495                 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2496                 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2497                 if (ASIC_IS_DCE32(rdev)) {
2498                         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2499                         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2500                 }
2501         } else {
2502                 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2503                 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2504                 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2505         }
2506
2507         if (rdev->irq.sw_int) {
2508                 DRM_DEBUG("r600_irq_set: sw int\n");
2509                 cp_int_cntl |= RB_INT_ENABLE;
2510         }
2511         if (rdev->irq.crtc_vblank_int[0]) {
2512                 DRM_DEBUG("r600_irq_set: vblank 0\n");
2513                 mode_int |= D1MODE_VBLANK_INT_MASK;
2514         }
2515         if (rdev->irq.crtc_vblank_int[1]) {
2516                 DRM_DEBUG("r600_irq_set: vblank 1\n");
2517                 mode_int |= D2MODE_VBLANK_INT_MASK;
2518         }
2519         if (rdev->irq.hpd[0]) {
2520                 DRM_DEBUG("r600_irq_set: hpd 1\n");
2521                 hpd1 |= DC_HPDx_INT_EN;
2522         }
2523         if (rdev->irq.hpd[1]) {
2524                 DRM_DEBUG("r600_irq_set: hpd 2\n");
2525                 hpd2 |= DC_HPDx_INT_EN;
2526         }
2527         if (rdev->irq.hpd[2]) {
2528                 DRM_DEBUG("r600_irq_set: hpd 3\n");
2529                 hpd3 |= DC_HPDx_INT_EN;
2530         }
2531         if (rdev->irq.hpd[3]) {
2532                 DRM_DEBUG("r600_irq_set: hpd 4\n");
2533                 hpd4 |= DC_HPDx_INT_EN;
2534         }
2535         if (rdev->irq.hpd[4]) {
2536                 DRM_DEBUG("r600_irq_set: hpd 5\n");
2537                 hpd5 |= DC_HPDx_INT_EN;
2538         }
2539         if (rdev->irq.hpd[5]) {
2540                 DRM_DEBUG("r600_irq_set: hpd 6\n");
2541                 hpd6 |= DC_HPDx_INT_EN;
2542         }
2543
2544         WREG32(CP_INT_CNTL, cp_int_cntl);
2545         WREG32(DxMODE_INT_MASK, mode_int);
2546         if (ASIC_IS_DCE3(rdev)) {
2547                 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2548                 WREG32(DC_HPD2_INT_CONTROL, hpd2);
2549                 WREG32(DC_HPD3_INT_CONTROL, hpd3);
2550                 WREG32(DC_HPD4_INT_CONTROL, hpd4);
2551                 if (ASIC_IS_DCE32(rdev)) {
2552                         WREG32(DC_HPD5_INT_CONTROL, hpd5);
2553                         WREG32(DC_HPD6_INT_CONTROL, hpd6);
2554                 }
2555         } else {
2556                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
2557                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
2558                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
2559         }
2560
2561         return 0;
2562 }
2563
2564 static inline void r600_irq_ack(struct radeon_device *rdev,
2565                                 u32 *disp_int,
2566                                 u32 *disp_int_cont,
2567                                 u32 *disp_int_cont2)
2568 {
2569         u32 tmp;
2570
2571         if (ASIC_IS_DCE3(rdev)) {
2572                 *disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
2573                 *disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
2574                 *disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
2575         } else {
2576                 *disp_int = RREG32(DISP_INTERRUPT_STATUS);
2577                 *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2578                 *disp_int_cont2 = 0;
2579         }
2580
2581         if (*disp_int & LB_D1_VBLANK_INTERRUPT)
2582                 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
2583         if (*disp_int & LB_D1_VLINE_INTERRUPT)
2584                 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
2585         if (*disp_int & LB_D2_VBLANK_INTERRUPT)
2586                 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
2587         if (*disp_int & LB_D2_VLINE_INTERRUPT)
2588                 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
2589         if (*disp_int & DC_HPD1_INTERRUPT) {
2590                 if (ASIC_IS_DCE3(rdev)) {
2591                         tmp = RREG32(DC_HPD1_INT_CONTROL);
2592                         tmp |= DC_HPDx_INT_ACK;
2593                         WREG32(DC_HPD1_INT_CONTROL, tmp);
2594                 } else {
2595                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
2596                         tmp |= DC_HPDx_INT_ACK;
2597                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
2598                 }
2599         }
2600         if (*disp_int & DC_HPD2_INTERRUPT) {
2601                 if (ASIC_IS_DCE3(rdev)) {
2602                         tmp = RREG32(DC_HPD2_INT_CONTROL);
2603                         tmp |= DC_HPDx_INT_ACK;
2604                         WREG32(DC_HPD2_INT_CONTROL, tmp);
2605                 } else {
2606                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
2607                         tmp |= DC_HPDx_INT_ACK;
2608                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
2609                 }
2610         }
2611         if (*disp_int_cont & DC_HPD3_INTERRUPT) {
2612                 if (ASIC_IS_DCE3(rdev)) {
2613                         tmp = RREG32(DC_HPD3_INT_CONTROL);
2614                         tmp |= DC_HPDx_INT_ACK;
2615                         WREG32(DC_HPD3_INT_CONTROL, tmp);
2616                 } else {
2617                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
2618                         tmp |= DC_HPDx_INT_ACK;
2619                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
2620                 }
2621         }
2622         if (*disp_int_cont & DC_HPD4_INTERRUPT) {
2623                 tmp = RREG32(DC_HPD4_INT_CONTROL);
2624                 tmp |= DC_HPDx_INT_ACK;
2625                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2626         }
2627         if (ASIC_IS_DCE32(rdev)) {
2628                 if (*disp_int_cont2 & DC_HPD5_INTERRUPT) {
2629                         tmp = RREG32(DC_HPD5_INT_CONTROL);
2630                         tmp |= DC_HPDx_INT_ACK;
2631                         WREG32(DC_HPD5_INT_CONTROL, tmp);
2632                 }
2633                 if (*disp_int_cont2 & DC_HPD6_INTERRUPT) {
2634                         tmp = RREG32(DC_HPD5_INT_CONTROL);
2635                         tmp |= DC_HPDx_INT_ACK;
2636                         WREG32(DC_HPD6_INT_CONTROL, tmp);
2637                 }
2638         }
2639 }
2640
2641 void r600_irq_disable(struct radeon_device *rdev)
2642 {
2643         u32 disp_int, disp_int_cont, disp_int_cont2;
2644
2645         r600_disable_interrupts(rdev);
2646         /* Wait and acknowledge irq */
2647         mdelay(1);
2648         r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
2649         r600_disable_interrupt_state(rdev);
2650 }
2651
2652 static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
2653 {
2654         u32 wptr, tmp;
2655
2656         /* XXX use writeback */
2657         wptr = RREG32(IH_RB_WPTR);
2658
2659         if (wptr & RB_OVERFLOW) {
2660                 /* When a ring buffer overflow happen start parsing interrupt
2661                  * from the last not overwritten vector (wptr + 16). Hopefully
2662                  * this should allow us to catchup.
2663                  */
2664                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2665                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2666                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2667                 tmp = RREG32(IH_RB_CNTL);
2668                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2669                 WREG32(IH_RB_CNTL, tmp);
2670         }
2671         return (wptr & rdev->ih.ptr_mask);
2672 }
2673
2674 /*        r600 IV Ring
2675  * Each IV ring entry is 128 bits:
2676  * [7:0]    - interrupt source id
2677  * [31:8]   - reserved
2678  * [59:32]  - interrupt source data
2679  * [127:60]  - reserved
2680  *
2681  * The basic interrupt vector entries
2682  * are decoded as follows:
2683  * src_id  src_data  description
2684  *      1         0  D1 Vblank
2685  *      1         1  D1 Vline
2686  *      5         0  D2 Vblank
2687  *      5         1  D2 Vline
2688  *     19         0  FP Hot plug detection A
2689  *     19         1  FP Hot plug detection B
2690  *     19         2  DAC A auto-detection
2691  *     19         3  DAC B auto-detection
2692  *    176         -  CP_INT RB
2693  *    177         -  CP_INT IB1
2694  *    178         -  CP_INT IB2
2695  *    181         -  EOP Interrupt
2696  *    233         -  GUI Idle
2697  *
2698  * Note, these are based on r600 and may need to be
2699  * adjusted or added to on newer asics
2700  */
2701
2702 int r600_irq_process(struct radeon_device *rdev)
2703 {
2704         u32 wptr = r600_get_ih_wptr(rdev);
2705         u32 rptr = rdev->ih.rptr;
2706         u32 src_id, src_data;
2707         u32 ring_index, disp_int, disp_int_cont, disp_int_cont2;
2708         unsigned long flags;
2709         bool queue_hotplug = false;
2710
2711         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2712         if (!rdev->ih.enabled)
2713                 return IRQ_NONE;
2714
2715         spin_lock_irqsave(&rdev->ih.lock, flags);
2716
2717         if (rptr == wptr) {
2718                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2719                 return IRQ_NONE;
2720         }
2721         if (rdev->shutdown) {
2722                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2723                 return IRQ_NONE;
2724         }
2725
2726 restart_ih:
2727         /* display interrupts */
2728         r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
2729
2730         rdev->ih.wptr = wptr;
2731         while (rptr != wptr) {
2732                 /* wptr/rptr are in bytes! */
2733                 ring_index = rptr / 4;
2734                 src_id =  rdev->ih.ring[ring_index] & 0xff;
2735                 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
2736
2737                 switch (src_id) {
2738                 case 1: /* D1 vblank/vline */
2739                         switch (src_data) {
2740                         case 0: /* D1 vblank */
2741                                 if (disp_int & LB_D1_VBLANK_INTERRUPT) {
2742                                         drm_handle_vblank(rdev->ddev, 0);
2743                                         wake_up(&rdev->irq.vblank_queue);
2744                                         disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2745                                         DRM_DEBUG("IH: D1 vblank\n");
2746                                 }
2747                                 break;
2748                         case 1: /* D1 vline */
2749                                 if (disp_int & LB_D1_VLINE_INTERRUPT) {
2750                                         disp_int &= ~LB_D1_VLINE_INTERRUPT;
2751                                         DRM_DEBUG("IH: D1 vline\n");
2752                                 }
2753                                 break;
2754                         default:
2755                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2756                                 break;
2757                         }
2758                         break;
2759                 case 5: /* D2 vblank/vline */
2760                         switch (src_data) {
2761                         case 0: /* D2 vblank */
2762                                 if (disp_int & LB_D2_VBLANK_INTERRUPT) {
2763                                         drm_handle_vblank(rdev->ddev, 1);
2764                                         wake_up(&rdev->irq.vblank_queue);
2765                                         disp_int &= ~LB_D2_VBLANK_INTERRUPT;
2766                                         DRM_DEBUG("IH: D2 vblank\n");
2767                                 }
2768                                 break;
2769                         case 1: /* D1 vline */
2770                                 if (disp_int & LB_D2_VLINE_INTERRUPT) {
2771                                         disp_int &= ~LB_D2_VLINE_INTERRUPT;
2772                                         DRM_DEBUG("IH: D2 vline\n");
2773                                 }
2774                                 break;
2775                         default:
2776                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2777                                 break;
2778                         }
2779                         break;
2780                 case 19: /* HPD/DAC hotplug */
2781                         switch (src_data) {
2782                         case 0:
2783                                 if (disp_int & DC_HPD1_INTERRUPT) {
2784                                         disp_int &= ~DC_HPD1_INTERRUPT;
2785                                         queue_hotplug = true;
2786                                         DRM_DEBUG("IH: HPD1\n");
2787                                 }
2788                                 break;
2789                         case 1:
2790                                 if (disp_int & DC_HPD2_INTERRUPT) {
2791                                         disp_int &= ~DC_HPD2_INTERRUPT;
2792                                         queue_hotplug = true;
2793                                         DRM_DEBUG("IH: HPD2\n");
2794                                 }
2795                                 break;
2796                         case 4:
2797                                 if (disp_int_cont & DC_HPD3_INTERRUPT) {
2798                                         disp_int_cont &= ~DC_HPD3_INTERRUPT;
2799                                         queue_hotplug = true;
2800                                         DRM_DEBUG("IH: HPD3\n");
2801                                 }
2802                                 break;
2803                         case 5:
2804                                 if (disp_int_cont & DC_HPD4_INTERRUPT) {
2805                                         disp_int_cont &= ~DC_HPD4_INTERRUPT;
2806                                         queue_hotplug = true;
2807                                         DRM_DEBUG("IH: HPD4\n");
2808                                 }
2809                                 break;
2810                         case 10:
2811                                 if (disp_int_cont2 & DC_HPD5_INTERRUPT) {
2812                                         disp_int_cont &= ~DC_HPD5_INTERRUPT;
2813                                         queue_hotplug = true;
2814                                         DRM_DEBUG("IH: HPD5\n");
2815                                 }
2816                                 break;
2817                         case 12:
2818                                 if (disp_int_cont2 & DC_HPD6_INTERRUPT) {
2819                                         disp_int_cont &= ~DC_HPD6_INTERRUPT;
2820                                         queue_hotplug = true;
2821                                         DRM_DEBUG("IH: HPD6\n");
2822                                 }
2823                                 break;
2824                         default:
2825                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2826                                 break;
2827                         }
2828                         break;
2829                 case 176: /* CP_INT in ring buffer */
2830                 case 177: /* CP_INT in IB1 */
2831                 case 178: /* CP_INT in IB2 */
2832                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
2833                         radeon_fence_process(rdev);
2834                         break;
2835                 case 181: /* CP EOP event */
2836                         DRM_DEBUG("IH: CP EOP\n");
2837                         break;
2838                 default:
2839                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2840                         break;
2841                 }
2842
2843                 /* wptr/rptr are in bytes! */
2844                 rptr += 16;
2845                 rptr &= rdev->ih.ptr_mask;
2846         }
2847         /* make sure wptr hasn't changed while processing */
2848         wptr = r600_get_ih_wptr(rdev);
2849         if (wptr != rdev->ih.wptr)
2850                 goto restart_ih;
2851         if (queue_hotplug)
2852                 queue_work(rdev->wq, &rdev->hotplug_work);
2853         rdev->ih.rptr = rptr;
2854         WREG32(IH_RB_RPTR, rdev->ih.rptr);
2855         spin_unlock_irqrestore(&rdev->ih.lock, flags);
2856         return IRQ_HANDLED;
2857 }
2858
2859 /*
2860  * Debugfs info
2861  */
2862 #if defined(CONFIG_DEBUG_FS)
2863
2864 static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
2865 {
2866         struct drm_info_node *node = (struct drm_info_node *) m->private;
2867         struct drm_device *dev = node->minor->dev;
2868         struct radeon_device *rdev = dev->dev_private;
2869         unsigned count, i, j;
2870
2871         radeon_ring_free_size(rdev);
2872         count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
2873         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
2874         seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
2875         seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
2876         seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
2877         seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
2878         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2879         seq_printf(m, "%u dwords in ring\n", count);
2880         i = rdev->cp.rptr;
2881         for (j = 0; j <= count; j++) {
2882                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2883                 i = (i + 1) & rdev->cp.ptr_mask;
2884         }
2885         return 0;
2886 }
2887
2888 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
2889 {
2890         struct drm_info_node *node = (struct drm_info_node *) m->private;
2891         struct drm_device *dev = node->minor->dev;
2892         struct radeon_device *rdev = dev->dev_private;
2893
2894         DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
2895         DREG32_SYS(m, rdev, VM_L2_STATUS);
2896         return 0;
2897 }
2898
2899 static struct drm_info_list r600_mc_info_list[] = {
2900         {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
2901         {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
2902 };
2903 #endif
2904
2905 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
2906 {
2907 #if defined(CONFIG_DEBUG_FS)
2908         return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
2909 #else
2910         return 0;
2911 #endif
2912 }
2913
2914 /**
2915  * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
2916  * rdev: radeon device structure
2917  * bo: buffer object struct which userspace is waiting for idle
2918  *
2919  * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
2920  * through ring buffer, this leads to corruption in rendering, see
2921  * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
2922  * directly perform HDP flush by writing register through MMIO.
2923  */
2924 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
2925 {
2926         WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2927 }