SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/r600.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include <linux/firmware.h>
  30 #include <linux/platform_device.h>
  31 #include "drmP.h"
  32 #include "radeon_drm.h"
  33 #include "radeon.h"
  34 #include "radeon_asic.h"
  35 #include "radeon_mode.h"
  36 #include "r600d.h"
  37 #include "atom.h"
  38 #include "avivod.h"
  39
  40 #define PFP_UCODE_SIZE 576
  41 #define PM4_UCODE_SIZE 1792
  42 #define RLC_UCODE_SIZE 768
  43 #define R700_PFP_UCODE_SIZE 848
  44 #define R700_PM4_UCODE_SIZE 1360
  45 #define R700_RLC_UCODE_SIZE 1024
  46
  47 /* Firmware Names */
  48 MODULE_FIRMWARE("radeon/R600_pfp.bin");
  49 MODULE_FIRMWARE("radeon/R600_me.bin");
  50 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
  51 MODULE_FIRMWARE("radeon/RV610_me.bin");
  52 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
  53 MODULE_FIRMWARE("radeon/RV630_me.bin");
  54 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
  55 MODULE_FIRMWARE("radeon/RV620_me.bin");
  56 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
  57 MODULE_FIRMWARE("radeon/RV635_me.bin");
  58 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
  59 MODULE_FIRMWARE("radeon/RV670_me.bin");
  60 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
  61 MODULE_FIRMWARE("radeon/RS780_me.bin");
  62 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
  63 MODULE_FIRMWARE("radeon/RV770_me.bin");
  64 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
  65 MODULE_FIRMWARE("radeon/RV730_me.bin");
  66 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
  67 MODULE_FIRMWARE("radeon/RV710_me.bin");
  68 MODULE_FIRMWARE("radeon/R600_rlc.bin");
  69 MODULE_FIRMWARE("radeon/R700_rlc.bin");
  70
  71 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
  72
  73 /* r600,rv610,rv630,rv620,rv635,rv670 */
  74 int r600_mc_wait_for_idle(struct radeon_device *rdev);
  75 void r600_gpu_init(struct radeon_device *rdev);
  76 void r600_fini(struct radeon_device *rdev);
  77
  78 /* hpd for digital panel detect/disconnect */
  79 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
  80 {
  81         bool connected = false;
  82
  83         if (ASIC_IS_DCE3(rdev)) {
  84                 switch (hpd) {
  85                 case RADEON_HPD_1:
  86                         if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
  87                                 connected = true;
  88                         break;
  89                 case RADEON_HPD_2:
  90                         if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
  91                                 connected = true;
  92                         break;
  93                 case RADEON_HPD_3:
  94                         if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
  95                                 connected = true;
  96                         break;
  97                 case RADEON_HPD_4:
  98                         if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
  99                                 connected = true;
 100                         break;
 101                         /* DCE 3.2 */
 102                 case RADEON_HPD_5:
 103                         if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 104                                 connected = true;
 105                         break;
 106                 case RADEON_HPD_6:
 107                         if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 108                                 connected = true;
 109                         break;
 110                 default:
 111                         break;
 112                 }
 113         } else {
 114                 switch (hpd) {
 115                 case RADEON_HPD_1:
 116                         if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 117                                 connected = true;
 118                         break;
 119                 case RADEON_HPD_2:
 120                         if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 121                                 connected = true;
 122                         break;
 123                 case RADEON_HPD_3:
 124                         if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 125                                 connected = true;
 126                         break;
 127                 default:
 128                         break;
 129                 }
 130         }
 131         return connected;
 132 }
 133
 134 void r600_hpd_set_polarity(struct radeon_device *rdev,
 135                            enum radeon_hpd_id hpd)
 136 {
 137         u32 tmp;
 138         bool connected = r600_hpd_sense(rdev, hpd);
 139
 140         if (ASIC_IS_DCE3(rdev)) {
 141                 switch (hpd) {
 142                 case RADEON_HPD_1:
 143                         tmp = RREG32(DC_HPD1_INT_CONTROL);
 144                         if (connected)
 145                                 tmp &= ~DC_HPDx_INT_POLARITY;
 146                         else
 147                                 tmp |= DC_HPDx_INT_POLARITY;
 148                         WREG32(DC_HPD1_INT_CONTROL, tmp);
 149                         break;
 150                 case RADEON_HPD_2:
 151                         tmp = RREG32(DC_HPD2_INT_CONTROL);
 152                         if (connected)
 153                                 tmp &= ~DC_HPDx_INT_POLARITY;
 154                         else
 155                                 tmp |= DC_HPDx_INT_POLARITY;
 156                         WREG32(DC_HPD2_INT_CONTROL, tmp);
 157                         break;
 158                 case RADEON_HPD_3:
 159                         tmp = RREG32(DC_HPD3_INT_CONTROL);
 160                         if (connected)
 161                                 tmp &= ~DC_HPDx_INT_POLARITY;
 162                         else
 163                                 tmp |= DC_HPDx_INT_POLARITY;
 164                         WREG32(DC_HPD3_INT_CONTROL, tmp);
 165                         break;
 166                 case RADEON_HPD_4:
 167                         tmp = RREG32(DC_HPD4_INT_CONTROL);
 168                         if (connected)
 169                                 tmp &= ~DC_HPDx_INT_POLARITY;
 170                         else
 171                                 tmp |= DC_HPDx_INT_POLARITY;
 172                         WREG32(DC_HPD4_INT_CONTROL, tmp);
 173                         break;
 174                 case RADEON_HPD_5:
 175                         tmp = RREG32(DC_HPD5_INT_CONTROL);
 176                         if (connected)
 177                                 tmp &= ~DC_HPDx_INT_POLARITY;
 178                         else
 179                                 tmp |= DC_HPDx_INT_POLARITY;
 180                         WREG32(DC_HPD5_INT_CONTROL, tmp);
 181                         break;
 182                         /* DCE 3.2 */
 183                 case RADEON_HPD_6:
 184                         tmp = RREG32(DC_HPD6_INT_CONTROL);
 185                         if (connected)
 186                                 tmp &= ~DC_HPDx_INT_POLARITY;
 187                         else
 188                                 tmp |= DC_HPDx_INT_POLARITY;
 189                         WREG32(DC_HPD6_INT_CONTROL, tmp);
 190                         break;
 191                 default:
 192                         break;
 193                 }
 194         } else {
 195                 switch (hpd) {
 196                 case RADEON_HPD_1:
 197                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
 198                         if (connected)
 199                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 200                         else
 201                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 202                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
 203                         break;
 204                 case RADEON_HPD_2:
 205                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
 206                         if (connected)
 207                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 208                         else
 209                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 210                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
 211                         break;
 212                 case RADEON_HPD_3:
 213                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
 214                         if (connected)
 215                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 216                         else
 217                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 218                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
 219                         break;
 220                 default:
 221                         break;
 222                 }
 223         }
 224 }
 225
 226 void r600_hpd_init(struct radeon_device *rdev)
 227 {
 228         struct drm_device *dev = rdev->ddev;
 229         struct drm_connector *connector;
 230
 231         if (ASIC_IS_DCE3(rdev)) {
 232                 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
 233                 if (ASIC_IS_DCE32(rdev))
 234                         tmp |= DC_HPDx_EN;
 235
 236                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 237                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 238                         switch (radeon_connector->hpd.hpd) {
 239                         case RADEON_HPD_1:
 240                                 WREG32(DC_HPD1_CONTROL, tmp);
 241                                 rdev->irq.hpd[0] = true;
 242                                 break;
 243                         case RADEON_HPD_2:
 244                                 WREG32(DC_HPD2_CONTROL, tmp);
 245                                 rdev->irq.hpd[1] = true;
 246                                 break;
 247                         case RADEON_HPD_3:
 248                                 WREG32(DC_HPD3_CONTROL, tmp);
 249                                 rdev->irq.hpd[2] = true;
 250                                 break;
 251                         case RADEON_HPD_4:
 252                                 WREG32(DC_HPD4_CONTROL, tmp);
 253                                 rdev->irq.hpd[3] = true;
 254                                 break;
 255                                 /* DCE 3.2 */
 256                         case RADEON_HPD_5:
 257                                 WREG32(DC_HPD5_CONTROL, tmp);
 258                                 rdev->irq.hpd[4] = true;
 259                                 break;
 260                         case RADEON_HPD_6:
 261                                 WREG32(DC_HPD6_CONTROL, tmp);
 262                                 rdev->irq.hpd[5] = true;
 263                                 break;
 264                         default:
 265                                 break;
 266                         }
 267                 }
 268         } else {
 269                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 270                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 271                         switch (radeon_connector->hpd.hpd) {
 272                         case RADEON_HPD_1:
 273                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 274                                 rdev->irq.hpd[0] = true;
 275                                 break;
 276                         case RADEON_HPD_2:
 277                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 278                                 rdev->irq.hpd[1] = true;
 279                                 break;
 280                         case RADEON_HPD_3:
 281                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 282                                 rdev->irq.hpd[2] = true;
 283                                 break;
 284                         default:
 285                                 break;
 286                         }
 287                 }
 288         }
 289         if (rdev->irq.installed)
 290                 r600_irq_set(rdev);
 291 }
 292
 293 void r600_hpd_fini(struct radeon_device *rdev)
 294 {
 295         struct drm_device *dev = rdev->ddev;
 296         struct drm_connector *connector;
 297
 298         if (ASIC_IS_DCE3(rdev)) {
 299                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 300                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 301                         switch (radeon_connector->hpd.hpd) {
 302                         case RADEON_HPD_1:
 303                                 WREG32(DC_HPD1_CONTROL, 0);
 304                                 rdev->irq.hpd[0] = false;
 305                                 break;
 306                         case RADEON_HPD_2:
 307                                 WREG32(DC_HPD2_CONTROL, 0);
 308                                 rdev->irq.hpd[1] = false;
 309                                 break;
 310                         case RADEON_HPD_3:
 311                                 WREG32(DC_HPD3_CONTROL, 0);
 312                                 rdev->irq.hpd[2] = false;
 313                                 break;
 314                         case RADEON_HPD_4:
 315                                 WREG32(DC_HPD4_CONTROL, 0);
 316                                 rdev->irq.hpd[3] = false;
 317                                 break;
 318                                 /* DCE 3.2 */
 319                         case RADEON_HPD_5:
 320                                 WREG32(DC_HPD5_CONTROL, 0);
 321                                 rdev->irq.hpd[4] = false;
 322                                 break;
 323                         case RADEON_HPD_6:
 324                                 WREG32(DC_HPD6_CONTROL, 0);
 325                                 rdev->irq.hpd[5] = false;
 326                                 break;
 327                         default:
 328                                 break;
 329                         }
 330                 }
 331         } else {
 332                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 333                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 334                         switch (radeon_connector->hpd.hpd) {
 335                         case RADEON_HPD_1:
 336                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
 337                                 rdev->irq.hpd[0] = false;
 338                                 break;
 339                         case RADEON_HPD_2:
 340                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
 341                                 rdev->irq.hpd[1] = false;
 342                                 break;
 343                         case RADEON_HPD_3:
 344                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
 345                                 rdev->irq.hpd[2] = false;
 346                                 break;
 347                         default:
 348                                 break;
 349                         }
 350                 }
 351         }
 352 }
 353
 354 /*
 355  * R600 PCIE GART
 356  */
 357 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
 358 {
 359         unsigned i;
 360         u32 tmp;
 361
 362         /* flush hdp cache so updates hit vram */
 363         WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
 364
 365         WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
 366         WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
 367         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
 368         for (i = 0; i < rdev->usec_timeout; i++) {
 369                 /* read MC_STATUS */
 370                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
 371                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
 372                 if (tmp == 2) {
 373                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
 374                         return;
 375                 }
 376                 if (tmp) {
 377                         return;
 378                 }
 379                 udelay(1);
 380         }
 381 }
 382
 383 int r600_pcie_gart_init(struct radeon_device *rdev)
 384 {
 385         int r;
 386
 387         if (rdev->gart.table.vram.robj) {
 388                 WARN(1, "R600 PCIE GART already initialized.\n");
 389                 return 0;
 390         }
 391         /* Initialize common gart structure */
 392         r = radeon_gart_init(rdev);
 393         if (r)
 394                 return r;
 395         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
 396         return radeon_gart_table_vram_alloc(rdev);
 397 }
 398
 399 int r600_pcie_gart_enable(struct radeon_device *rdev)
 400 {
 401         u32 tmp;
 402         int r, i;
 403
 404         if (rdev->gart.table.vram.robj == NULL) {
 405                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 406                 return -EINVAL;
 407         }
 408         r = radeon_gart_table_vram_pin(rdev);
 409         if (r)
 410                 return r;
 411         radeon_gart_restore(rdev);
 412
 413         /* Setup L2 cache */
 414         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 415                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 416                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 417         WREG32(VM_L2_CNTL2, 0);
 418         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 419         /* Setup TLB control */
 420         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 421                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 422                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 423                 ENABLE_WAIT_L2_QUERY;
 424         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 425         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 426         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
 427         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 428         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 429         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 430         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 431         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 432         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 433         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 434         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 435         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 436         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 437         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 438         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 439         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 440         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 441         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 442                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 443         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 444                         (u32)(rdev->dummy_page.addr >> 12));
 445         for (i = 1; i < 7; i++)
 446                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 447
 448         r600_pcie_gart_tlb_flush(rdev);
 449         rdev->gart.ready = true;
 450         return 0;
 451 }
 452
 453 void r600_pcie_gart_disable(struct radeon_device *rdev)
 454 {
 455         u32 tmp;
 456         int i, r;
 457
 458         /* Disable all tables */
 459         for (i = 0; i < 7; i++)
 460                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 461
 462         /* Disable L2 cache */
 463         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
 464                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 465         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 466         /* Setup L1 TLB control */
 467         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 468                 ENABLE_WAIT_L2_QUERY;
 469         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 470         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 471         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 472         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 473         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 474         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 475         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 476         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 477         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
 478         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
 479         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 480         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 481         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
 482         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 483         if (rdev->gart.table.vram.robj) {
 484                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
 485                 if (likely(r == 0)) {
 486                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
 487                         radeon_bo_unpin(rdev->gart.table.vram.robj);
 488                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
 489                 }
 490         }
 491 }
 492
 493 void r600_pcie_gart_fini(struct radeon_device *rdev)
 494 {
 495         radeon_gart_fini(rdev);
 496         r600_pcie_gart_disable(rdev);
 497         radeon_gart_table_vram_free(rdev);
 498 }
 499
 500 void r600_agp_enable(struct radeon_device *rdev)
 501 {
 502         u32 tmp;
 503         int i;
 504
 505         /* Setup L2 cache */
 506         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 507                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 508                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 509         WREG32(VM_L2_CNTL2, 0);
 510         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 511         /* Setup TLB control */
 512         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 513                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 514                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 515                 ENABLE_WAIT_L2_QUERY;
 516         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 517         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 518         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
 519         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 520         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 521         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 522         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 523         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 524         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 525         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 526         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 527         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 528         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 529         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 530         for (i = 0; i < 7; i++)
 531                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 532 }
 533
 534 int r600_mc_wait_for_idle(struct radeon_device *rdev)
 535 {
 536         unsigned i;
 537         u32 tmp;
 538
 539         for (i = 0; i < rdev->usec_timeout; i++) {
 540                 /* read MC_STATUS */
 541                 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
 542                 if (!tmp)
 543                         return 0;
 544                 udelay(1);
 545         }
 546         return -1;
 547 }
 548
 549 static void r600_mc_program(struct radeon_device *rdev)
 550 {
 551         struct rv515_mc_save save;
 552         u32 tmp;
 553         int i, j;
 554
 555         /* Initialize HDP */
 556         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
 557                 WREG32((0x2c14 + j), 0x00000000);
 558                 WREG32((0x2c18 + j), 0x00000000);
 559                 WREG32((0x2c1c + j), 0x00000000);
 560                 WREG32((0x2c20 + j), 0x00000000);
 561                 WREG32((0x2c24 + j), 0x00000000);
 562         }
 563         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
 564
 565         rv515_mc_stop(rdev, &save);
 566         if (r600_mc_wait_for_idle(rdev)) {
 567                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 568         }
 569         /* Lockout access through VGA aperture (doesn't exist before R600) */
 570         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
 571         /* Update configuration */
 572         if (rdev->flags & RADEON_IS_AGP) {
 573                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
 574                         /* VRAM before AGP */
 575                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 576                                 rdev->mc.vram_start >> 12);
 577                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 578                                 rdev->mc.gtt_end >> 12);
 579                 } else {
 580                         /* VRAM after AGP */
 581                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 582                                 rdev->mc.gtt_start >> 12);
 583                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 584                                 rdev->mc.vram_end >> 12);
 585                 }
 586         } else {
 587                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
 588                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
 589         }
 590         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
 591         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
 592         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
 593         WREG32(MC_VM_FB_LOCATION, tmp);
 594         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
 595         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
 596         WREG32(HDP_NONSURFACE_SIZE, rdev->mc.mc_vram_size | 0x3FF);
 597         if (rdev->flags & RADEON_IS_AGP) {
 598                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
 599                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
 600                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
 601         } else {
 602                 WREG32(MC_VM_AGP_BASE, 0);
 603                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
 604                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
 605         }
 606         if (r600_mc_wait_for_idle(rdev)) {
 607                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 608         }
 609         rv515_mc_resume(rdev, &save);
 610         /* we need to own VRAM, so turn off the VGA renderer here
 611          * to stop it overwriting our objects */
 612         rv515_vga_render_disable(rdev);
 613 }
 614
 615 /**
 616  * r600_vram_gtt_location - try to find VRAM & GTT location
 617  * @rdev: radeon device structure holding all necessary informations
 618  * @mc: memory controller structure holding memory informations
 619  *
 620  * Function will place try to place VRAM at same place as in CPU (PCI)
 621  * address space as some GPU seems to have issue when we reprogram at
 622  * different address space.
 623  *
 624  * If there is not enough space to fit the unvisible VRAM after the
 625  * aperture then we limit the VRAM size to the aperture.
 626  *
 627  * If we are using AGP then place VRAM adjacent to AGP aperture are we need
 628  * them to be in one from GPU point of view so that we can program GPU to
 629  * catch access outside them (weird GPU policy see ??).
 630  *
 631  * This function will never fails, worst case are limiting VRAM or GTT.
 632  *
 633  * Note: GTT start, end, size should be initialized before calling this
 634  * function on AGP platform.
 635  */
 636 void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
 637 {
 638         u64 size_bf, size_af;
 639
 640         if (mc->mc_vram_size > 0xE0000000) {
 641                 /* leave room for at least 512M GTT */
 642                 dev_warn(rdev->dev, "limiting VRAM\n");
 643                 mc->real_vram_size = 0xE0000000;
 644                 mc->mc_vram_size = 0xE0000000;
 645         }
 646         if (rdev->flags & RADEON_IS_AGP) {
 647                 size_bf = mc->gtt_start;
 648                 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
 649                 if (size_bf > size_af) {
 650                         if (mc->mc_vram_size > size_bf) {
 651                                 dev_warn(rdev->dev, "limiting VRAM\n");
 652                                 mc->real_vram_size = size_bf;
 653                                 mc->mc_vram_size = size_bf;
 654                         }
 655                         mc->vram_start = mc->gtt_start - mc->mc_vram_size;
 656                 } else {
 657                         if (mc->mc_vram_size > size_af) {
 658                                 dev_warn(rdev->dev, "limiting VRAM\n");
 659                                 mc->real_vram_size = size_af;
 660                                 mc->mc_vram_size = size_af;
 661                         }
 662                         mc->vram_start = mc->gtt_end;
 663                 }
 664                 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
 665                 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
 666                                 mc->mc_vram_size >> 20, mc->vram_start,
 667                                 mc->vram_end, mc->real_vram_size >> 20);
 668         } else {
 669                 u64 base = 0;
 670                 if (rdev->flags & RADEON_IS_IGP)
 671                         base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
 672                 radeon_vram_location(rdev, &rdev->mc, base);
 673                 radeon_gtt_location(rdev, mc);
 674         }
 675 }
 676
 677 int r600_mc_init(struct radeon_device *rdev)
 678 {
 679         u32 tmp;
 680         int chansize, numchan;
 681
 682         /* Get VRAM informations */
 683         rdev->mc.vram_is_ddr = true;
 684         tmp = RREG32(RAMCFG);
 685         if (tmp & CHANSIZE_OVERRIDE) {
 686                 chansize = 16;
 687         } else if (tmp & CHANSIZE_MASK) {
 688                 chansize = 64;
 689         } else {
 690                 chansize = 32;
 691         }
 692         tmp = RREG32(CHMAP);
 693         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
 694         case 0:
 695         default:
 696                 numchan = 1;
 697                 break;
 698         case 1:
 699                 numchan = 2;
 700                 break;
 701         case 2:
 702                 numchan = 4;
 703                 break;
 704         case 3:
 705                 numchan = 8;
 706                 break;
 707         }
 708         rdev->mc.vram_width = numchan * chansize;
 709         /* Could aper size report 0 ? */
 710         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
 711         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
 712         /* Setup GPU memory space */
 713         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
 714         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
 715         rdev->mc.visible_vram_size = rdev->mc.aper_size;
 716         /* FIXME remove this once we support unmappable VRAM */
 717         if (rdev->mc.mc_vram_size > rdev->mc.aper_size) {
 718                 rdev->mc.mc_vram_size = rdev->mc.aper_size;
 719                 rdev->mc.real_vram_size = rdev->mc.aper_size;
 720         }
 721         r600_vram_gtt_location(rdev, &rdev->mc);
 722
 723         if (rdev->flags & RADEON_IS_IGP)
 724                 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
 725         radeon_update_bandwidth_info(rdev);
 726         return 0;
 727 }
 728
 729 /* We doesn't check that the GPU really needs a reset we simply do the
 730  * reset, it's up to the caller to determine if the GPU needs one. We
 731  * might add an helper function to check that.
 732  */
 733 int r600_gpu_soft_reset(struct radeon_device *rdev)
 734 {
 735         struct rv515_mc_save save;
 736         u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
 737                                 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
 738                                 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
 739                                 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
 740                                 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
 741                                 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
 742                                 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
 743                                 S_008010_GUI_ACTIVE(1);
 744         u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
 745                         S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
 746                         S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
 747                         S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
 748                         S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
 749                         S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
 750                         S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
 751                         S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
 752         u32 srbm_reset = 0;
 753         u32 tmp;
 754
 755         dev_info(rdev->dev, "GPU softreset \n");
 756         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
 757                 RREG32(R_008010_GRBM_STATUS));
 758         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
 759                 RREG32(R_008014_GRBM_STATUS2));
 760         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
 761                 RREG32(R_000E50_SRBM_STATUS));
 762         rv515_mc_stop(rdev, &save);
 763         if (r600_mc_wait_for_idle(rdev)) {
 764                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 765         }
 766         /* Disable CP parsing/prefetching */
 767         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(0xff));
 768         /* Check if any of the rendering block is busy and reset it */
 769         if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
 770             (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
 771                 tmp = S_008020_SOFT_RESET_CR(1) |
 772                         S_008020_SOFT_RESET_DB(1) |
 773                         S_008020_SOFT_RESET_CB(1) |
 774                         S_008020_SOFT_RESET_PA(1) |
 775                         S_008020_SOFT_RESET_SC(1) |
 776                         S_008020_SOFT_RESET_SMX(1) |
 777                         S_008020_SOFT_RESET_SPI(1) |
 778                         S_008020_SOFT_RESET_SX(1) |
 779                         S_008020_SOFT_RESET_SH(1) |
 780                         S_008020_SOFT_RESET_TC(1) |
 781                         S_008020_SOFT_RESET_TA(1) |
 782                         S_008020_SOFT_RESET_VC(1) |
 783                         S_008020_SOFT_RESET_VGT(1);
 784                 dev_info(rdev->dev, "  R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
 785                 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
 786                 (void)RREG32(R_008020_GRBM_SOFT_RESET);
 787                 mdelay(1);
 788                 WREG32(R_008020_GRBM_SOFT_RESET, 0);
 789                 (void)RREG32(R_008020_GRBM_SOFT_RESET);
 790         }
 791         /* Reset CP (we always reset CP) */
 792         tmp = S_008020_SOFT_RESET_CP(1);
 793         dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
 794         WREG32(R_008020_GRBM_SOFT_RESET, tmp);
 795         (void)RREG32(R_008020_GRBM_SOFT_RESET);
 796         udelay(50);
 797         WREG32(R_008020_GRBM_SOFT_RESET, 0);
 798         (void)RREG32(R_008020_GRBM_SOFT_RESET);
 799         /* Reset others GPU block if necessary */
 800         if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 801                 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
 802         if (G_000E50_GRBM_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
 803                 srbm_reset |= S_000E60_SOFT_RESET_GRBM(1);
 804         if (G_000E50_HI_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
 805                 srbm_reset |= S_000E60_SOFT_RESET_IH(1);
 806         if (G_000E50_VMC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 807                 srbm_reset |= S_000E60_SOFT_RESET_VMC(1);
 808         if (G_000E50_MCB_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 809                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 810         if (G_000E50_MCDZ_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 811                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 812         if (G_000E50_MCDY_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 813                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 814         if (G_000E50_MCDX_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 815                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 816         if (G_000E50_MCDW_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 817                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 818         if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 819                 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
 820         if (G_000E50_SEM_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 821                 srbm_reset |= S_000E60_SOFT_RESET_SEM(1);
 822         if (G_000E50_BIF_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 823                 srbm_reset |= S_000E60_SOFT_RESET_BIF(1);
 824         dev_info(rdev->dev, "  R_000E60_SRBM_SOFT_RESET=0x%08X\n", srbm_reset);
 825         WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
 826         (void)RREG32(R_000E60_SRBM_SOFT_RESET);
 827         mdelay(1);
 828         WREG32(R_000E60_SRBM_SOFT_RESET, 0);
 829         (void)RREG32(R_000E60_SRBM_SOFT_RESET);
 830         WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
 831         (void)RREG32(R_000E60_SRBM_SOFT_RESET);
 832         mdelay(1);
 833         WREG32(R_000E60_SRBM_SOFT_RESET, 0);
 834         (void)RREG32(R_000E60_SRBM_SOFT_RESET);
 835         /* Wait a little for things to settle down */
 836         mdelay(1);
 837         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
 838                 RREG32(R_008010_GRBM_STATUS));
 839         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
 840                 RREG32(R_008014_GRBM_STATUS2));
 841         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
 842                 RREG32(R_000E50_SRBM_STATUS));
 843         /* After reset we need to reinit the asic as GPU often endup in an
 844          * incoherent state.
 845          */
 846         atom_asic_init(rdev->mode_info.atom_context);
 847         rv515_mc_resume(rdev, &save);
 848         return 0;
 849 }
 850
 851 bool r600_gpu_is_lockup(struct radeon_device *rdev)
 852 {
 853         u32 srbm_status;
 854         u32 grbm_status;
 855         u32 grbm_status2;
 856         int r;
 857
 858         srbm_status = RREG32(R_000E50_SRBM_STATUS);
 859         grbm_status = RREG32(R_008010_GRBM_STATUS);
 860         grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
 861         if (!G_008010_GUI_ACTIVE(grbm_status)) {
 862                 r100_gpu_lockup_update(&rdev->config.r300.lockup, &rdev->cp);
 863                 return false;
 864         }
 865         /* force CP activities */
 866         r = radeon_ring_lock(rdev, 2);
 867         if (!r) {
 868                 /* PACKET2 NOP */
 869                 radeon_ring_write(rdev, 0x80000000);
 870                 radeon_ring_write(rdev, 0x80000000);
 871                 radeon_ring_unlock_commit(rdev);
 872         }
 873         rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
 874         return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, &rdev->cp);
 875 }
 876
 877 int r600_gpu_reset(struct radeon_device *rdev)
 878 {
 879         return r600_gpu_soft_reset(rdev);
 880 }
 881
 882 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
 883                                              u32 num_backends,
 884                                              u32 backend_disable_mask)
 885 {
 886         u32 backend_map = 0;
 887         u32 enabled_backends_mask;
 888         u32 enabled_backends_count;
 889         u32 cur_pipe;
 890         u32 swizzle_pipe[R6XX_MAX_PIPES];
 891         u32 cur_backend;
 892         u32 i;
 893
 894         if (num_tile_pipes > R6XX_MAX_PIPES)
 895                 num_tile_pipes = R6XX_MAX_PIPES;
 896         if (num_tile_pipes < 1)
 897                 num_tile_pipes = 1;
 898         if (num_backends > R6XX_MAX_BACKENDS)
 899                 num_backends = R6XX_MAX_BACKENDS;
 900         if (num_backends < 1)
 901                 num_backends = 1;
 902
 903         enabled_backends_mask = 0;
 904         enabled_backends_count = 0;
 905         for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
 906                 if (((backend_disable_mask >> i) & 1) == 0) {
 907                         enabled_backends_mask |= (1 << i);
 908                         ++enabled_backends_count;
 909                 }
 910                 if (enabled_backends_count == num_backends)
 911                         break;
 912         }
 913
 914         if (enabled_backends_count == 0) {
 915                 enabled_backends_mask = 1;
 916                 enabled_backends_count = 1;
 917         }
 918
 919         if (enabled_backends_count != num_backends)
 920                 num_backends = enabled_backends_count;
 921
 922         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
 923         switch (num_tile_pipes) {
 924         case 1:
 925                 swizzle_pipe[0] = 0;
 926                 break;
 927         case 2:
 928                 swizzle_pipe[0] = 0;
 929                 swizzle_pipe[1] = 1;
 930                 break;
 931         case 3:
 932                 swizzle_pipe[0] = 0;
 933                 swizzle_pipe[1] = 1;
 934                 swizzle_pipe[2] = 2;
 935                 break;
 936         case 4:
 937                 swizzle_pipe[0] = 0;
 938                 swizzle_pipe[1] = 1;
 939                 swizzle_pipe[2] = 2;
 940                 swizzle_pipe[3] = 3;
 941                 break;
 942         case 5:
 943                 swizzle_pipe[0] = 0;
 944                 swizzle_pipe[1] = 1;
 945                 swizzle_pipe[2] = 2;
 946                 swizzle_pipe[3] = 3;
 947                 swizzle_pipe[4] = 4;
 948                 break;
 949         case 6:
 950                 swizzle_pipe[0] = 0;
 951                 swizzle_pipe[1] = 2;
 952                 swizzle_pipe[2] = 4;
 953                 swizzle_pipe[3] = 5;
 954                 swizzle_pipe[4] = 1;
 955                 swizzle_pipe[5] = 3;
 956                 break;
 957         case 7:
 958                 swizzle_pipe[0] = 0;
 959                 swizzle_pipe[1] = 2;
 960                 swizzle_pipe[2] = 4;
 961                 swizzle_pipe[3] = 6;
 962                 swizzle_pipe[4] = 1;
 963                 swizzle_pipe[5] = 3;
 964                 swizzle_pipe[6] = 5;
 965                 break;
 966         case 8:
 967                 swizzle_pipe[0] = 0;
 968                 swizzle_pipe[1] = 2;
 969                 swizzle_pipe[2] = 4;
 970                 swizzle_pipe[3] = 6;
 971                 swizzle_pipe[4] = 1;
 972                 swizzle_pipe[5] = 3;
 973                 swizzle_pipe[6] = 5;
 974                 swizzle_pipe[7] = 7;
 975                 break;
 976         }
 977
 978         cur_backend = 0;
 979         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
 980                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
 981                         cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
 982
 983                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
 984
 985                 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
 986         }
 987
 988         return backend_map;
 989 }
 990
 991 int r600_count_pipe_bits(uint32_t val)
 992 {
 993         int i, ret = 0;
 994
 995         for (i = 0; i < 32; i++) {
 996                 ret += val & 1;
 997                 val >>= 1;
 998         }
 999         return ret;
1000 }
1001
1002 void r600_gpu_init(struct radeon_device *rdev)
1003 {
1004         u32 tiling_config;
1005         u32 ramcfg;
1006         u32 backend_map;
1007         u32 cc_rb_backend_disable;
1008         u32 cc_gc_shader_pipe_config;
1009         u32 tmp;
1010         int i, j;
1011         u32 sq_config;
1012         u32 sq_gpr_resource_mgmt_1 = 0;
1013         u32 sq_gpr_resource_mgmt_2 = 0;
1014         u32 sq_thread_resource_mgmt = 0;
1015         u32 sq_stack_resource_mgmt_1 = 0;
1016         u32 sq_stack_resource_mgmt_2 = 0;
1017
1018         /* FIXME: implement */
1019         switch (rdev->family) {
1020         case CHIP_R600:
1021                 rdev->config.r600.max_pipes = 4;
1022                 rdev->config.r600.max_tile_pipes = 8;
1023                 rdev->config.r600.max_simds = 4;
1024                 rdev->config.r600.max_backends = 4;
1025                 rdev->config.r600.max_gprs = 256;
1026                 rdev->config.r600.max_threads = 192;
1027                 rdev->config.r600.max_stack_entries = 256;
1028                 rdev->config.r600.max_hw_contexts = 8;
1029                 rdev->config.r600.max_gs_threads = 16;
1030                 rdev->config.r600.sx_max_export_size = 128;
1031                 rdev->config.r600.sx_max_export_pos_size = 16;
1032                 rdev->config.r600.sx_max_export_smx_size = 128;
1033                 rdev->config.r600.sq_num_cf_insts = 2;
1034                 break;
1035         case CHIP_RV630:
1036         case CHIP_RV635:
1037                 rdev->config.r600.max_pipes = 2;
1038                 rdev->config.r600.max_tile_pipes = 2;
1039                 rdev->config.r600.max_simds = 3;
1040                 rdev->config.r600.max_backends = 1;
1041                 rdev->config.r600.max_gprs = 128;
1042                 rdev->config.r600.max_threads = 192;
1043                 rdev->config.r600.max_stack_entries = 128;
1044                 rdev->config.r600.max_hw_contexts = 8;
1045                 rdev->config.r600.max_gs_threads = 4;
1046                 rdev->config.r600.sx_max_export_size = 128;
1047                 rdev->config.r600.sx_max_export_pos_size = 16;
1048                 rdev->config.r600.sx_max_export_smx_size = 128;
1049                 rdev->config.r600.sq_num_cf_insts = 2;
1050                 break;
1051         case CHIP_RV610:
1052         case CHIP_RV620:
1053         case CHIP_RS780:
1054         case CHIP_RS880:
1055                 rdev->config.r600.max_pipes = 1;
1056                 rdev->config.r600.max_tile_pipes = 1;
1057                 rdev->config.r600.max_simds = 2;
1058                 rdev->config.r600.max_backends = 1;
1059                 rdev->config.r600.max_gprs = 128;
1060                 rdev->config.r600.max_threads = 192;
1061                 rdev->config.r600.max_stack_entries = 128;
1062                 rdev->config.r600.max_hw_contexts = 4;
1063                 rdev->config.r600.max_gs_threads = 4;
1064                 rdev->config.r600.sx_max_export_size = 128;
1065                 rdev->config.r600.sx_max_export_pos_size = 16;
1066                 rdev->config.r600.sx_max_export_smx_size = 128;
1067                 rdev->config.r600.sq_num_cf_insts = 1;
1068                 break;
1069         case CHIP_RV670:
1070                 rdev->config.r600.max_pipes = 4;
1071                 rdev->config.r600.max_tile_pipes = 4;
1072                 rdev->config.r600.max_simds = 4;
1073                 rdev->config.r600.max_backends = 4;
1074                 rdev->config.r600.max_gprs = 192;
1075                 rdev->config.r600.max_threads = 192;
1076                 rdev->config.r600.max_stack_entries = 256;
1077                 rdev->config.r600.max_hw_contexts = 8;
1078                 rdev->config.r600.max_gs_threads = 16;
1079                 rdev->config.r600.sx_max_export_size = 128;
1080                 rdev->config.r600.sx_max_export_pos_size = 16;
1081                 rdev->config.r600.sx_max_export_smx_size = 128;
1082                 rdev->config.r600.sq_num_cf_insts = 2;
1083                 break;
1084         default:
1085                 break;
1086         }
1087
1088         /* Initialize HDP */
1089         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1090                 WREG32((0x2c14 + j), 0x00000000);
1091                 WREG32((0x2c18 + j), 0x00000000);
1092                 WREG32((0x2c1c + j), 0x00000000);
1093                 WREG32((0x2c20 + j), 0x00000000);
1094                 WREG32((0x2c24 + j), 0x00000000);
1095         }
1096
1097         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1098
1099         /* Setup tiling */
1100         tiling_config = 0;
1101         ramcfg = RREG32(RAMCFG);
1102         switch (rdev->config.r600.max_tile_pipes) {
1103         case 1:
1104                 tiling_config |= PIPE_TILING(0);
1105                 break;
1106         case 2:
1107                 tiling_config |= PIPE_TILING(1);
1108                 break;
1109         case 4:
1110                 tiling_config |= PIPE_TILING(2);
1111                 break;
1112         case 8:
1113                 tiling_config |= PIPE_TILING(3);
1114                 break;
1115         default:
1116                 break;
1117         }
1118         rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
1119         rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1120         tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1121         tiling_config |= GROUP_SIZE(0);
1122         rdev->config.r600.tiling_group_size = 256;
1123         tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1124         if (tmp > 3) {
1125                 tiling_config |= ROW_TILING(3);
1126                 tiling_config |= SAMPLE_SPLIT(3);
1127         } else {
1128                 tiling_config |= ROW_TILING(tmp);
1129                 tiling_config |= SAMPLE_SPLIT(tmp);
1130         }
1131         tiling_config |= BANK_SWAPS(1);
1132
1133         cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1134         cc_rb_backend_disable |=
1135                 BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1136
1137         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1138         cc_gc_shader_pipe_config |=
1139                 INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1140         cc_gc_shader_pipe_config |=
1141                 INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1142
1143         backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1144                                                         (R6XX_MAX_BACKENDS -
1145                                                          r600_count_pipe_bits((cc_rb_backend_disable &
1146                                                                                R6XX_MAX_BACKENDS_MASK) >> 16)),
1147                                                         (cc_rb_backend_disable >> 16));
1148
1149         tiling_config |= BACKEND_MAP(backend_map);
1150         WREG32(GB_TILING_CONFIG, tiling_config);
1151         WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1152         WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1153
1154         /* Setup pipes */
1155         WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1156         WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1157         WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1158
1159         tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1160         WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1161         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1162
1163         /* Setup some CP states */
1164         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1165         WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1166
1167         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1168                              SYNC_WALKER | SYNC_ALIGNER));
1169         /* Setup various GPU states */
1170         if (rdev->family == CHIP_RV670)
1171                 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1172
1173         tmp = RREG32(SX_DEBUG_1);
1174         tmp |= SMX_EVENT_RELEASE;
1175         if ((rdev->family > CHIP_R600))
1176                 tmp |= ENABLE_NEW_SMX_ADDRESS;
1177         WREG32(SX_DEBUG_1, tmp);
1178
1179         if (((rdev->family) == CHIP_R600) ||
1180             ((rdev->family) == CHIP_RV630) ||
1181             ((rdev->family) == CHIP_RV610) ||
1182             ((rdev->family) == CHIP_RV620) ||
1183             ((rdev->family) == CHIP_RS780) ||
1184             ((rdev->family) == CHIP_RS880)) {
1185                 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1186         } else {
1187                 WREG32(DB_DEBUG, 0);
1188         }
1189         WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1190                                DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1191
1192         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1193         WREG32(VGT_NUM_INSTANCES, 0);
1194
1195         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1196         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1197
1198         tmp = RREG32(SQ_MS_FIFO_SIZES);
1199         if (((rdev->family) == CHIP_RV610) ||
1200             ((rdev->family) == CHIP_RV620) ||
1201             ((rdev->family) == CHIP_RS780) ||
1202             ((rdev->family) == CHIP_RS880)) {
1203                 tmp = (CACHE_FIFO_SIZE(0xa) |
1204                        FETCH_FIFO_HIWATER(0xa) |
1205                        DONE_FIFO_HIWATER(0xe0) |
1206                        ALU_UPDATE_FIFO_HIWATER(0x8));
1207         } else if (((rdev->family) == CHIP_R600) ||
1208                    ((rdev->family) == CHIP_RV630)) {
1209                 tmp &= ~DONE_FIFO_HIWATER(0xff);
1210                 tmp |= DONE_FIFO_HIWATER(0x4);
1211         }
1212         WREG32(SQ_MS_FIFO_SIZES, tmp);
1213
1214         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1215          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
1216          */
1217         sq_config = RREG32(SQ_CONFIG);
1218         sq_config &= ~(PS_PRIO(3) |
1219                        VS_PRIO(3) |
1220                        GS_PRIO(3) |
1221                        ES_PRIO(3));
1222         sq_config |= (DX9_CONSTS |
1223                       VC_ENABLE |
1224                       PS_PRIO(0) |
1225                       VS_PRIO(1) |
1226                       GS_PRIO(2) |
1227                       ES_PRIO(3));
1228
1229         if ((rdev->family) == CHIP_R600) {
1230                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1231                                           NUM_VS_GPRS(124) |
1232                                           NUM_CLAUSE_TEMP_GPRS(4));
1233                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1234                                           NUM_ES_GPRS(0));
1235                 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1236                                            NUM_VS_THREADS(48) |
1237                                            NUM_GS_THREADS(4) |
1238                                            NUM_ES_THREADS(4));
1239                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1240                                             NUM_VS_STACK_ENTRIES(128));
1241                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1242                                             NUM_ES_STACK_ENTRIES(0));
1243         } else if (((rdev->family) == CHIP_RV610) ||
1244                    ((rdev->family) == CHIP_RV620) ||
1245                    ((rdev->family) == CHIP_RS780) ||
1246                    ((rdev->family) == CHIP_RS880)) {
1247                 /* no vertex cache */
1248                 sq_config &= ~VC_ENABLE;
1249
1250                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1251                                           NUM_VS_GPRS(44) |
1252                                           NUM_CLAUSE_TEMP_GPRS(2));
1253                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1254                                           NUM_ES_GPRS(17));
1255                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1256                                            NUM_VS_THREADS(78) |
1257                                            NUM_GS_THREADS(4) |
1258                                            NUM_ES_THREADS(31));
1259                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1260                                             NUM_VS_STACK_ENTRIES(40));
1261                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1262                                             NUM_ES_STACK_ENTRIES(16));
1263         } else if (((rdev->family) == CHIP_RV630) ||
1264                    ((rdev->family) == CHIP_RV635)) {
1265                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1266                                           NUM_VS_GPRS(44) |
1267                                           NUM_CLAUSE_TEMP_GPRS(2));
1268                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1269                                           NUM_ES_GPRS(18));
1270                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1271                                            NUM_VS_THREADS(78) |
1272                                            NUM_GS_THREADS(4) |
1273                                            NUM_ES_THREADS(31));
1274                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1275                                             NUM_VS_STACK_ENTRIES(40));
1276                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1277                                             NUM_ES_STACK_ENTRIES(16));
1278         } else if ((rdev->family) == CHIP_RV670) {
1279                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1280                                           NUM_VS_GPRS(44) |
1281                                           NUM_CLAUSE_TEMP_GPRS(2));
1282                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1283                                           NUM_ES_GPRS(17));
1284                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1285                                            NUM_VS_THREADS(78) |
1286                                            NUM_GS_THREADS(4) |
1287                                            NUM_ES_THREADS(31));
1288                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1289                                             NUM_VS_STACK_ENTRIES(64));
1290                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1291                                             NUM_ES_STACK_ENTRIES(64));
1292         }
1293
1294         WREG32(SQ_CONFIG, sq_config);
1295         WREG32(SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
1296         WREG32(SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
1297         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1298         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1299         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1300
1301         if (((rdev->family) == CHIP_RV610) ||
1302             ((rdev->family) == CHIP_RV620) ||
1303             ((rdev->family) == CHIP_RS780) ||
1304             ((rdev->family) == CHIP_RS880)) {
1305                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1306         } else {
1307                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1308         }
1309
1310         /* More default values. 2D/3D driver should adjust as needed */
1311         WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1312                                          S1_X(0x4) | S1_Y(0xc)));
1313         WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1314                                          S1_X(0x2) | S1_Y(0x2) |
1315                                          S2_X(0xa) | S2_Y(0x6) |
1316                                          S3_X(0x6) | S3_Y(0xa)));
1317         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1318                                              S1_X(0x4) | S1_Y(0xc) |
1319                                              S2_X(0x1) | S2_Y(0x6) |
1320                                              S3_X(0xa) | S3_Y(0xe)));
1321         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1322                                              S5_X(0x0) | S5_Y(0x0) |
1323                                              S6_X(0xb) | S6_Y(0x4) |
1324                                              S7_X(0x7) | S7_Y(0x8)));
1325
1326         WREG32(VGT_STRMOUT_EN, 0);
1327         tmp = rdev->config.r600.max_pipes * 16;
1328         switch (rdev->family) {
1329         case CHIP_RV610:
1330         case CHIP_RV620:
1331         case CHIP_RS780:
1332         case CHIP_RS880:
1333                 tmp += 32;
1334                 break;
1335         case CHIP_RV670:
1336                 tmp += 128;
1337                 break;
1338         default:
1339                 break;
1340         }
1341         if (tmp > 256) {
1342                 tmp = 256;
1343         }
1344         WREG32(VGT_ES_PER_GS, 128);
1345         WREG32(VGT_GS_PER_ES, tmp);
1346         WREG32(VGT_GS_PER_VS, 2);
1347         WREG32(VGT_GS_VERTEX_REUSE, 16);
1348
1349         /* more default values. 2D/3D driver should adjust as needed */
1350         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1351         WREG32(VGT_STRMOUT_EN, 0);
1352         WREG32(SX_MISC, 0);
1353         WREG32(PA_SC_MODE_CNTL, 0);
1354         WREG32(PA_SC_AA_CONFIG, 0);
1355         WREG32(PA_SC_LINE_STIPPLE, 0);
1356         WREG32(SPI_INPUT_Z, 0);
1357         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1358         WREG32(CB_COLOR7_FRAG, 0);
1359
1360         /* Clear render buffer base addresses */
1361         WREG32(CB_COLOR0_BASE, 0);
1362         WREG32(CB_COLOR1_BASE, 0);
1363         WREG32(CB_COLOR2_BASE, 0);
1364         WREG32(CB_COLOR3_BASE, 0);
1365         WREG32(CB_COLOR4_BASE, 0);
1366         WREG32(CB_COLOR5_BASE, 0);
1367         WREG32(CB_COLOR6_BASE, 0);
1368         WREG32(CB_COLOR7_BASE, 0);
1369         WREG32(CB_COLOR7_FRAG, 0);
1370
1371         switch (rdev->family) {
1372         case CHIP_RV610:
1373         case CHIP_RV620:
1374         case CHIP_RS780:
1375         case CHIP_RS880:
1376                 tmp = TC_L2_SIZE(8);
1377                 break;
1378         case CHIP_RV630:
1379         case CHIP_RV635:
1380                 tmp = TC_L2_SIZE(4);
1381                 break;
1382         case CHIP_R600:
1383                 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1384                 break;
1385         default:
1386                 tmp = TC_L2_SIZE(0);
1387                 break;
1388         }
1389         WREG32(TC_CNTL, tmp);
1390
1391         tmp = RREG32(HDP_HOST_PATH_CNTL);
1392         WREG32(HDP_HOST_PATH_CNTL, tmp);
1393
1394         tmp = RREG32(ARB_POP);
1395         tmp |= ENABLE_TC128;
1396         WREG32(ARB_POP, tmp);
1397
1398         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1399         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1400                                NUM_CLIP_SEQ(3)));
1401         WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1402 }
1403
1404
1405 /*
1406  * Indirect registers accessor
1407  */
1408 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1409 {
1410         u32 r;
1411
1412         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1413         (void)RREG32(PCIE_PORT_INDEX);
1414         r = RREG32(PCIE_PORT_DATA);
1415         return r;
1416 }
1417
1418 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1419 {
1420         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1421         (void)RREG32(PCIE_PORT_INDEX);
1422         WREG32(PCIE_PORT_DATA, (v));
1423         (void)RREG32(PCIE_PORT_DATA);
1424 }
1425
1426 /*
1427  * CP & Ring
1428  */
1429 void r600_cp_stop(struct radeon_device *rdev)
1430 {
1431         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1432 }
1433
1434 int r600_init_microcode(struct radeon_device *rdev)
1435 {
1436         struct platform_device *pdev;
1437         const char *chip_name;
1438         const char *rlc_chip_name;
1439         size_t pfp_req_size, me_req_size, rlc_req_size;
1440         char fw_name[30];
1441         int err;
1442
1443         DRM_DEBUG("\n");
1444
1445         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1446         err = IS_ERR(pdev);
1447         if (err) {
1448                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1449                 return -EINVAL;
1450         }
1451
1452         switch (rdev->family) {
1453         case CHIP_R600:
1454                 chip_name = "R600";
1455                 rlc_chip_name = "R600";
1456                 break;
1457         case CHIP_RV610:
1458                 chip_name = "RV610";
1459                 rlc_chip_name = "R600";
1460                 break;
1461         case CHIP_RV630:
1462                 chip_name = "RV630";
1463                 rlc_chip_name = "R600";
1464                 break;
1465         case CHIP_RV620:
1466                 chip_name = "RV620";
1467                 rlc_chip_name = "R600";
1468                 break;
1469         case CHIP_RV635:
1470                 chip_name = "RV635";
1471                 rlc_chip_name = "R600";
1472                 break;
1473         case CHIP_RV670:
1474                 chip_name = "RV670";
1475                 rlc_chip_name = "R600";
1476                 break;
1477         case CHIP_RS780:
1478         case CHIP_RS880:
1479                 chip_name = "RS780";
1480                 rlc_chip_name = "R600";
1481                 break;
1482         case CHIP_RV770:
1483                 chip_name = "RV770";
1484                 rlc_chip_name = "R700";
1485                 break;
1486         case CHIP_RV730:
1487         case CHIP_RV740:
1488                 chip_name = "RV730";
1489                 rlc_chip_name = "R700";
1490                 break;
1491         case CHIP_RV710:
1492                 chip_name = "RV710";
1493                 rlc_chip_name = "R700";
1494                 break;
1495         default: BUG();
1496         }
1497
1498         if (rdev->family >= CHIP_RV770) {
1499                 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
1500                 me_req_size = R700_PM4_UCODE_SIZE * 4;
1501                 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
1502         } else {
1503                 pfp_req_size = PFP_UCODE_SIZE * 4;
1504                 me_req_size = PM4_UCODE_SIZE * 12;
1505                 rlc_req_size = RLC_UCODE_SIZE * 4;
1506         }
1507
1508         DRM_INFO("Loading %s Microcode\n", chip_name);
1509
1510         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
1511         err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
1512         if (err)
1513                 goto out;
1514         if (rdev->pfp_fw->size != pfp_req_size) {
1515                 printk(KERN_ERR
1516                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1517                        rdev->pfp_fw->size, fw_name);
1518                 err = -EINVAL;
1519                 goto out;
1520         }
1521
1522         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
1523         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
1524         if (err)
1525                 goto out;
1526         if (rdev->me_fw->size != me_req_size) {
1527                 printk(KERN_ERR
1528                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1529                        rdev->me_fw->size, fw_name);
1530                 err = -EINVAL;
1531         }
1532
1533         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
1534         err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
1535         if (err)
1536                 goto out;
1537         if (rdev->rlc_fw->size != rlc_req_size) {
1538                 printk(KERN_ERR
1539                        "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
1540                        rdev->rlc_fw->size, fw_name);
1541                 err = -EINVAL;
1542         }
1543
1544 out:
1545         platform_device_unregister(pdev);
1546
1547         if (err) {
1548                 if (err != -EINVAL)
1549                         printk(KERN_ERR
1550                                "r600_cp: Failed to load firmware \"%s\"\n",
1551                                fw_name);
1552                 release_firmware(rdev->pfp_fw);
1553                 rdev->pfp_fw = NULL;
1554                 release_firmware(rdev->me_fw);
1555                 rdev->me_fw = NULL;
1556                 release_firmware(rdev->rlc_fw);
1557                 rdev->rlc_fw = NULL;
1558         }
1559         return err;
1560 }
1561
1562 static int r600_cp_load_microcode(struct radeon_device *rdev)
1563 {
1564         const __be32 *fw_data;
1565         int i;
1566
1567         if (!rdev->me_fw || !rdev->pfp_fw)
1568                 return -EINVAL;
1569
1570         r600_cp_stop(rdev);
1571
1572         WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1573
1574         /* Reset cp */
1575         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1576         RREG32(GRBM_SOFT_RESET);
1577         mdelay(15);
1578         WREG32(GRBM_SOFT_RESET, 0);
1579
1580         WREG32(CP_ME_RAM_WADDR, 0);
1581
1582         fw_data = (const __be32 *)rdev->me_fw->data;
1583         WREG32(CP_ME_RAM_WADDR, 0);
1584         for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
1585                 WREG32(CP_ME_RAM_DATA,
1586                        be32_to_cpup(fw_data++));
1587
1588         fw_data = (const __be32 *)rdev->pfp_fw->data;
1589         WREG32(CP_PFP_UCODE_ADDR, 0);
1590         for (i = 0; i < PFP_UCODE_SIZE; i++)
1591                 WREG32(CP_PFP_UCODE_DATA,
1592                        be32_to_cpup(fw_data++));
1593
1594         WREG32(CP_PFP_UCODE_ADDR, 0);
1595         WREG32(CP_ME_RAM_WADDR, 0);
1596         WREG32(CP_ME_RAM_RADDR, 0);
1597         return 0;
1598 }
1599
1600 int r600_cp_start(struct radeon_device *rdev)
1601 {
1602         int r;
1603         uint32_t cp_me;
1604
1605         r = radeon_ring_lock(rdev, 7);
1606         if (r) {
1607                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1608                 return r;
1609         }
1610         radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1611         radeon_ring_write(rdev, 0x1);
1612         if (rdev->family < CHIP_RV770) {
1613                 radeon_ring_write(rdev, 0x3);
1614                 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
1615         } else {
1616                 radeon_ring_write(rdev, 0x0);
1617                 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
1618         }
1619         radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1620         radeon_ring_write(rdev, 0);
1621         radeon_ring_write(rdev, 0);
1622         radeon_ring_unlock_commit(rdev);
1623
1624         cp_me = 0xff;
1625         WREG32(R_0086D8_CP_ME_CNTL, cp_me);
1626         return 0;
1627 }
1628
1629 int r600_cp_resume(struct radeon_device *rdev)
1630 {
1631         u32 tmp;
1632         u32 rb_bufsz;
1633         int r;
1634
1635         /* Reset cp */
1636         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1637         RREG32(GRBM_SOFT_RESET);
1638         mdelay(15);
1639         WREG32(GRBM_SOFT_RESET, 0);
1640
1641         /* Set ring buffer size */
1642         rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1643         tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1644 #ifdef __BIG_ENDIAN
1645         tmp |= BUF_SWAP_32BIT;
1646 #endif
1647         WREG32(CP_RB_CNTL, tmp);
1648         WREG32(CP_SEM_WAIT_TIMER, 0x4);
1649
1650         /* Set the write pointer delay */
1651         WREG32(CP_RB_WPTR_DELAY, 0);
1652
1653         /* Initialize the ring buffer's read and write pointers */
1654         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1655         WREG32(CP_RB_RPTR_WR, 0);
1656         WREG32(CP_RB_WPTR, 0);
1657         WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
1658         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
1659         mdelay(1);
1660         WREG32(CP_RB_CNTL, tmp);
1661
1662         WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1663         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1664
1665         rdev->cp.rptr = RREG32(CP_RB_RPTR);
1666         rdev->cp.wptr = RREG32(CP_RB_WPTR);
1667
1668         r600_cp_start(rdev);
1669         rdev->cp.ready = true;
1670         r = radeon_ring_test(rdev);
1671         if (r) {
1672                 rdev->cp.ready = false;
1673                 return r;
1674         }
1675         return 0;
1676 }
1677
1678 void r600_cp_commit(struct radeon_device *rdev)
1679 {
1680         WREG32(CP_RB_WPTR, rdev->cp.wptr);
1681         (void)RREG32(CP_RB_WPTR);
1682 }
1683
1684 void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
1685 {
1686         u32 rb_bufsz;
1687
1688         /* Align ring size */
1689         rb_bufsz = drm_order(ring_size / 8);
1690         ring_size = (1 << (rb_bufsz + 1)) * 4;
1691         rdev->cp.ring_size = ring_size;
1692         rdev->cp.align_mask = 16 - 1;
1693 }
1694
1695 void r600_cp_fini(struct radeon_device *rdev)
1696 {
1697         r600_cp_stop(rdev);
1698         radeon_ring_fini(rdev);
1699 }
1700
1701
1702 /*
1703  * GPU scratch registers helpers function.
1704  */
1705 void r600_scratch_init(struct radeon_device *rdev)
1706 {
1707         int i;
1708
1709         rdev->scratch.num_reg = 7;
1710         for (i = 0; i < rdev->scratch.num_reg; i++) {
1711                 rdev->scratch.free[i] = true;
1712                 rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4);
1713         }
1714 }
1715
1716 int r600_ring_test(struct radeon_device *rdev)
1717 {
1718         uint32_t scratch;
1719         uint32_t tmp = 0;
1720         unsigned i;
1721         int r;
1722
1723         r = radeon_scratch_get(rdev, &scratch);
1724         if (r) {
1725                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
1726                 return r;
1727         }
1728         WREG32(scratch, 0xCAFEDEAD);
1729         r = radeon_ring_lock(rdev, 3);
1730         if (r) {
1731                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1732                 radeon_scratch_free(rdev, scratch);
1733                 return r;
1734         }
1735         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1736         radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1737         radeon_ring_write(rdev, 0xDEADBEEF);
1738         radeon_ring_unlock_commit(rdev);
1739         for (i = 0; i < rdev->usec_timeout; i++) {
1740                 tmp = RREG32(scratch);
1741                 if (tmp == 0xDEADBEEF)
1742                         break;
1743                 DRM_UDELAY(1);
1744         }
1745         if (i < rdev->usec_timeout) {
1746                 DRM_INFO("ring test succeeded in %d usecs\n", i);
1747         } else {
1748                 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
1749                           scratch, tmp);
1750                 r = -EINVAL;
1751         }
1752         radeon_scratch_free(rdev, scratch);
1753         return r;
1754 }
1755
1756 void r600_wb_disable(struct radeon_device *rdev)
1757 {
1758         int r;
1759
1760         WREG32(SCRATCH_UMSK, 0);
1761         if (rdev->wb.wb_obj) {
1762                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
1763                 if (unlikely(r != 0))
1764                         return;
1765                 radeon_bo_kunmap(rdev->wb.wb_obj);
1766                 radeon_bo_unpin(rdev->wb.wb_obj);
1767                 radeon_bo_unreserve(rdev->wb.wb_obj);
1768         }
1769 }
1770
1771 void r600_wb_fini(struct radeon_device *rdev)
1772 {
1773         r600_wb_disable(rdev);
1774         if (rdev->wb.wb_obj) {
1775                 radeon_bo_unref(&rdev->wb.wb_obj);
1776                 rdev->wb.wb = NULL;
1777                 rdev->wb.wb_obj = NULL;
1778         }
1779 }
1780
1781 int r600_wb_enable(struct radeon_device *rdev)
1782 {
1783         int r;
1784
1785         if (rdev->wb.wb_obj == NULL) {
1786                 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
1787                                 RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj);
1788                 if (r) {
1789                         dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
1790                         return r;
1791                 }
1792                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
1793                 if (unlikely(r != 0)) {
1794                         r600_wb_fini(rdev);
1795                         return r;
1796                 }
1797                 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
1798                                 &rdev->wb.gpu_addr);
1799                 if (r) {
1800                         radeon_bo_unreserve(rdev->wb.wb_obj);
1801                         dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
1802                         r600_wb_fini(rdev);
1803                         return r;
1804                 }
1805                 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
1806                 radeon_bo_unreserve(rdev->wb.wb_obj);
1807                 if (r) {
1808                         dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
1809                         r600_wb_fini(rdev);
1810                         return r;
1811                 }
1812         }
1813         WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF);
1814         WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC);
1815         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF);
1816         WREG32(SCRATCH_UMSK, 0xff);
1817         return 0;
1818 }
1819
1820 void r600_fence_ring_emit(struct radeon_device *rdev,
1821                           struct radeon_fence *fence)
1822 {
1823         /* Also consider EVENT_WRITE_EOP.  it handles the interrupts + timestamps + events */
1824
1825         radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
1826         radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT);
1827         /* wait for 3D idle clean */
1828         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1829         radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
1830         radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
1831         /* Emit fence sequence & fire IRQ */
1832         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1833         radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1834         radeon_ring_write(rdev, fence->seq);
1835         /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
1836         radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
1837         radeon_ring_write(rdev, RB_INT_STAT);
1838 }
1839
1840 int r600_copy_blit(struct radeon_device *rdev,
1841                    uint64_t src_offset, uint64_t dst_offset,
1842                    unsigned num_pages, struct radeon_fence *fence)
1843 {
1844         int r;
1845
1846         mutex_lock(&rdev->r600_blit.mutex);
1847         rdev->r600_blit.vb_ib = NULL;
1848         r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
1849         if (r) {
1850                 if (rdev->r600_blit.vb_ib)
1851                         radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
1852                 mutex_unlock(&rdev->r600_blit.mutex);
1853                 return r;
1854         }
1855         r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
1856         r600_blit_done_copy(rdev, fence);
1857         mutex_unlock(&rdev->r600_blit.mutex);
1858         return 0;
1859 }
1860
1861 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
1862                          uint32_t tiling_flags, uint32_t pitch,
1863                          uint32_t offset, uint32_t obj_size)
1864 {
1865         /* FIXME: implement */
1866         return 0;
1867 }
1868
1869 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
1870 {
1871         /* FIXME: implement */
1872 }
1873
1874
1875 bool r600_card_posted(struct radeon_device *rdev)
1876 {
1877         uint32_t reg;
1878
1879         /* first check CRTCs */
1880         reg = RREG32(D1CRTC_CONTROL) |
1881                 RREG32(D2CRTC_CONTROL);
1882         if (reg & CRTC_EN)
1883                 return true;
1884
1885         /* then check MEM_SIZE, in case the crtcs are off */
1886         if (RREG32(CONFIG_MEMSIZE))
1887                 return true;
1888
1889         return false;
1890 }
1891
1892 int r600_startup(struct radeon_device *rdev)
1893 {
1894         int r;
1895
1896         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1897                 r = r600_init_microcode(rdev);
1898                 if (r) {
1899                         DRM_ERROR("Failed to load firmware!\n");
1900                         return r;
1901                 }
1902         }
1903
1904         r600_mc_program(rdev);
1905         if (rdev->flags & RADEON_IS_AGP) {
1906                 r600_agp_enable(rdev);
1907         } else {
1908                 r = r600_pcie_gart_enable(rdev);
1909                 if (r)
1910                         return r;
1911         }
1912         r600_gpu_init(rdev);
1913         r = r600_blit_init(rdev);
1914         if (r) {
1915                 r600_blit_fini(rdev);
1916                 rdev->asic->copy = NULL;
1917                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1918         }
1919         /* pin copy shader into vram */
1920         if (rdev->r600_blit.shader_obj) {
1921                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1922                 if (unlikely(r != 0))
1923                         return r;
1924                 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
1925                                 &rdev->r600_blit.shader_gpu_addr);
1926                 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1927                 if (r) {
1928                         dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
1929                         return r;
1930                 }
1931         }
1932         /* Enable IRQ */
1933         r = r600_irq_init(rdev);
1934         if (r) {
1935                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1936                 radeon_irq_kms_fini(rdev);
1937                 return r;
1938         }
1939         r600_irq_set(rdev);
1940
1941         r = radeon_ring_init(rdev, rdev->cp.ring_size);
1942         if (r)
1943                 return r;
1944         r = r600_cp_load_microcode(rdev);
1945         if (r)
1946                 return r;
1947         r = r600_cp_resume(rdev);
1948         if (r)
1949                 return r;
1950         /* write back buffer are not vital so don't worry about failure */
1951         r600_wb_enable(rdev);
1952         return 0;
1953 }
1954
1955 void r600_vga_set_state(struct radeon_device *rdev, bool state)
1956 {
1957         uint32_t temp;
1958
1959         temp = RREG32(CONFIG_CNTL);
1960         if (state == false) {
1961                 temp &= ~(1<<0);
1962                 temp |= (1<<1);
1963         } else {
1964                 temp &= ~(1<<1);
1965         }
1966         WREG32(CONFIG_CNTL, temp);
1967 }
1968
1969 int r600_resume(struct radeon_device *rdev)
1970 {
1971         int r;
1972
1973         /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
1974          * posting will perform necessary task to bring back GPU into good
1975          * shape.
1976          */
1977         /* post card */
1978         atom_asic_init(rdev->mode_info.atom_context);
1979         /* Initialize clocks */
1980         r = radeon_clocks_init(rdev);
1981         if (r) {
1982                 return r;
1983         }
1984
1985         r = r600_startup(rdev);
1986         if (r) {
1987                 DRM_ERROR("r600 startup failed on resume\n");
1988                 return r;
1989         }
1990
1991         r = r600_ib_test(rdev);
1992         if (r) {
1993                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1994                 return r;
1995         }
1996
1997         r = r600_audio_init(rdev);
1998         if (r) {
1999                 DRM_ERROR("radeon: audio resume failed\n");
2000                 return r;
2001         }
2002
2003         return r;
2004 }
2005
2006 int r600_suspend(struct radeon_device *rdev)
2007 {
2008         int r;
2009
2010         r600_audio_fini(rdev);
2011         /* FIXME: we should wait for ring to be empty */
2012         r600_cp_stop(rdev);
2013         rdev->cp.ready = false;
2014         r600_irq_suspend(rdev);
2015         r600_wb_disable(rdev);
2016         r600_pcie_gart_disable(rdev);
2017         /* unpin shaders bo */
2018         if (rdev->r600_blit.shader_obj) {
2019                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2020                 if (!r) {
2021                         radeon_bo_unpin(rdev->r600_blit.shader_obj);
2022                         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2023                 }
2024         }
2025         return 0;
2026 }
2027
2028 /* Plan is to move initialization in that function and use
2029  * helper function so that radeon_device_init pretty much
2030  * do nothing more than calling asic specific function. This
2031  * should also allow to remove a bunch of callback function
2032  * like vram_info.
2033  */
2034 int r600_init(struct radeon_device *rdev)
2035 {
2036         int r;
2037
2038         r = radeon_dummy_page_init(rdev);
2039         if (r)
2040                 return r;
2041         if (r600_debugfs_mc_info_init(rdev)) {
2042                 DRM_ERROR("Failed to register debugfs file for mc !\n");
2043         }
2044         /* This don't do much */
2045         r = radeon_gem_init(rdev);
2046         if (r)
2047                 return r;
2048         /* Read BIOS */
2049         if (!radeon_get_bios(rdev)) {
2050                 if (ASIC_IS_AVIVO(rdev))
2051                         return -EINVAL;
2052         }
2053         /* Must be an ATOMBIOS */
2054         if (!rdev->is_atom_bios) {
2055                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2056                 return -EINVAL;
2057         }
2058         r = radeon_atombios_init(rdev);
2059         if (r)
2060                 return r;
2061         /* Post card if necessary */
2062         if (!r600_card_posted(rdev)) {
2063                 if (!rdev->bios) {
2064                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2065                         return -EINVAL;
2066                 }
2067                 DRM_INFO("GPU not posted. posting now...\n");
2068                 atom_asic_init(rdev->mode_info.atom_context);
2069         }
2070         /* Initialize scratch registers */
2071         r600_scratch_init(rdev);
2072         /* Initialize surface registers */
2073         radeon_surface_init(rdev);
2074         /* Initialize clocks */
2075         radeon_get_clock_info(rdev->ddev);
2076         r = radeon_clocks_init(rdev);
2077         if (r)
2078                 return r;
2079         /* Initialize power management */
2080         radeon_pm_init(rdev);
2081         /* Fence driver */
2082         r = radeon_fence_driver_init(rdev);
2083         if (r)
2084                 return r;
2085         if (rdev->flags & RADEON_IS_AGP) {
2086                 r = radeon_agp_init(rdev);
2087                 if (r)
2088                         radeon_agp_disable(rdev);
2089         }
2090         r = r600_mc_init(rdev);
2091         if (r)
2092                 return r;
2093         /* Memory manager */
2094         r = radeon_bo_init(rdev);
2095         if (r)
2096                 return r;
2097
2098         r = radeon_irq_kms_init(rdev);
2099         if (r)
2100                 return r;
2101
2102         rdev->cp.ring_obj = NULL;
2103         r600_ring_init(rdev, 1024 * 1024);
2104
2105         rdev->ih.ring_obj = NULL;
2106         r600_ih_ring_init(rdev, 64 * 1024);
2107
2108         r = r600_pcie_gart_init(rdev);
2109         if (r)
2110                 return r;
2111
2112         rdev->accel_working = true;
2113         r = r600_startup(rdev);
2114         if (r) {
2115                 dev_err(rdev->dev, "disabling GPU acceleration\n");
2116                 r600_cp_fini(rdev);
2117                 r600_wb_fini(rdev);
2118                 r600_irq_fini(rdev);
2119                 radeon_irq_kms_fini(rdev);
2120                 r600_pcie_gart_fini(rdev);
2121                 rdev->accel_working = false;
2122         }
2123         if (rdev->accel_working) {
2124                 r = radeon_ib_pool_init(rdev);
2125                 if (r) {
2126                         dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2127                         rdev->accel_working = false;
2128                 } else {
2129                         r = r600_ib_test(rdev);
2130                         if (r) {
2131                                 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2132                                 rdev->accel_working = false;
2133                         }
2134                 }
2135         }
2136
2137         r = r600_audio_init(rdev);
2138         if (r)
2139                 return r; /* TODO error handling */
2140         return 0;
2141 }
2142
2143 void r600_fini(struct radeon_device *rdev)
2144 {
2145         radeon_pm_fini(rdev);
2146         r600_audio_fini(rdev);
2147         r600_blit_fini(rdev);
2148         r600_cp_fini(rdev);
2149         r600_wb_fini(rdev);
2150         r600_irq_fini(rdev);
2151         radeon_irq_kms_fini(rdev);
2152         r600_pcie_gart_fini(rdev);
2153         radeon_agp_fini(rdev);
2154         radeon_gem_fini(rdev);
2155         radeon_fence_driver_fini(rdev);
2156         radeon_clocks_fini(rdev);
2157         radeon_bo_fini(rdev);
2158         radeon_atombios_fini(rdev);
2159         kfree(rdev->bios);
2160         rdev->bios = NULL;
2161         radeon_dummy_page_fini(rdev);
2162 }
2163
2164
2165 /*
2166  * CS stuff
2167  */
2168 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2169 {
2170         /* FIXME: implement */
2171         radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2172         radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
2173         radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
2174         radeon_ring_write(rdev, ib->length_dw);
2175 }
2176
2177 int r600_ib_test(struct radeon_device *rdev)
2178 {
2179         struct radeon_ib *ib;
2180         uint32_t scratch;
2181         uint32_t tmp = 0;
2182         unsigned i;
2183         int r;
2184
2185         r = radeon_scratch_get(rdev, &scratch);
2186         if (r) {
2187                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2188                 return r;
2189         }
2190         WREG32(scratch, 0xCAFEDEAD);
2191         r = radeon_ib_get(rdev, &ib);
2192         if (r) {
2193                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2194                 return r;
2195         }
2196         ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2197         ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2198         ib->ptr[2] = 0xDEADBEEF;
2199         ib->ptr[3] = PACKET2(0);
2200         ib->ptr[4] = PACKET2(0);
2201         ib->ptr[5] = PACKET2(0);
2202         ib->ptr[6] = PACKET2(0);
2203         ib->ptr[7] = PACKET2(0);
2204         ib->ptr[8] = PACKET2(0);
2205         ib->ptr[9] = PACKET2(0);
2206         ib->ptr[10] = PACKET2(0);
2207         ib->ptr[11] = PACKET2(0);
2208         ib->ptr[12] = PACKET2(0);
2209         ib->ptr[13] = PACKET2(0);
2210         ib->ptr[14] = PACKET2(0);
2211         ib->ptr[15] = PACKET2(0);
2212         ib->length_dw = 16;
2213         r = radeon_ib_schedule(rdev, ib);
2214         if (r) {
2215                 radeon_scratch_free(rdev, scratch);
2216                 radeon_ib_free(rdev, &ib);
2217                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2218                 return r;
2219         }
2220         r = radeon_fence_wait(ib->fence, false);
2221         if (r) {
2222                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2223                 return r;
2224         }
2225         for (i = 0; i < rdev->usec_timeout; i++) {
2226                 tmp = RREG32(scratch);
2227                 if (tmp == 0xDEADBEEF)
2228                         break;
2229                 DRM_UDELAY(1);
2230         }
2231         if (i < rdev->usec_timeout) {
2232                 DRM_INFO("ib test succeeded in %u usecs\n", i);
2233         } else {
2234                 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
2235                           scratch, tmp);
2236                 r = -EINVAL;
2237         }
2238         radeon_scratch_free(rdev, scratch);
2239         radeon_ib_free(rdev, &ib);
2240         return r;
2241 }
2242
2243 /*
2244  * Interrupts
2245  *
2246  * Interrupts use a ring buffer on r6xx/r7xx hardware.  It works pretty
2247  * the same as the CP ring buffer, but in reverse.  Rather than the CPU
2248  * writing to the ring and the GPU consuming, the GPU writes to the ring
2249  * and host consumes.  As the host irq handler processes interrupts, it
2250  * increments the rptr.  When the rptr catches up with the wptr, all the
2251  * current interrupts have been processed.
2252  */
2253
2254 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2255 {
2256         u32 rb_bufsz;
2257
2258         /* Align ring size */
2259         rb_bufsz = drm_order(ring_size / 4);
2260         ring_size = (1 << rb_bufsz) * 4;
2261         rdev->ih.ring_size = ring_size;
2262         rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2263         rdev->ih.rptr = 0;
2264 }
2265
2266 static int r600_ih_ring_alloc(struct radeon_device *rdev)
2267 {
2268         int r;
2269
2270         /* Allocate ring buffer */
2271         if (rdev->ih.ring_obj == NULL) {
2272                 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size,
2273                                      true,
2274                                      RADEON_GEM_DOMAIN_GTT,
2275                                      &rdev->ih.ring_obj);
2276                 if (r) {
2277                         DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2278                         return r;
2279                 }
2280                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2281                 if (unlikely(r != 0))
2282                         return r;
2283                 r = radeon_bo_pin(rdev->ih.ring_obj,
2284                                   RADEON_GEM_DOMAIN_GTT,
2285                                   &rdev->ih.gpu_addr);
2286                 if (r) {
2287                         radeon_bo_unreserve(rdev->ih.ring_obj);
2288                         DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2289                         return r;
2290                 }
2291                 r = radeon_bo_kmap(rdev->ih.ring_obj,
2292                                    (void **)&rdev->ih.ring);
2293                 radeon_bo_unreserve(rdev->ih.ring_obj);
2294                 if (r) {
2295                         DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2296                         return r;
2297                 }
2298         }
2299         return 0;
2300 }
2301
2302 static void r600_ih_ring_fini(struct radeon_device *rdev)
2303 {
2304         int r;
2305         if (rdev->ih.ring_obj) {
2306                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2307                 if (likely(r == 0)) {
2308                         radeon_bo_kunmap(rdev->ih.ring_obj);
2309                         radeon_bo_unpin(rdev->ih.ring_obj);
2310                         radeon_bo_unreserve(rdev->ih.ring_obj);
2311                 }
2312                 radeon_bo_unref(&rdev->ih.ring_obj);
2313                 rdev->ih.ring = NULL;
2314                 rdev->ih.ring_obj = NULL;
2315         }
2316 }
2317
2318 static void r600_rlc_stop(struct radeon_device *rdev)
2319 {
2320
2321         if (rdev->family >= CHIP_RV770) {
2322                 /* r7xx asics need to soft reset RLC before halting */
2323                 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2324                 RREG32(SRBM_SOFT_RESET);
2325                 udelay(15000);
2326                 WREG32(SRBM_SOFT_RESET, 0);
2327                 RREG32(SRBM_SOFT_RESET);
2328         }
2329
2330         WREG32(RLC_CNTL, 0);
2331 }
2332
2333 static void r600_rlc_start(struct radeon_device *rdev)
2334 {
2335         WREG32(RLC_CNTL, RLC_ENABLE);
2336 }
2337
2338 static int r600_rlc_init(struct radeon_device *rdev)
2339 {
2340         u32 i;
2341         const __be32 *fw_data;
2342
2343         if (!rdev->rlc_fw)
2344                 return -EINVAL;
2345
2346         r600_rlc_stop(rdev);
2347
2348         WREG32(RLC_HB_BASE, 0);
2349         WREG32(RLC_HB_CNTL, 0);
2350         WREG32(RLC_HB_RPTR, 0);
2351         WREG32(RLC_HB_WPTR, 0);
2352         WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2353         WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2354         WREG32(RLC_MC_CNTL, 0);
2355         WREG32(RLC_UCODE_CNTL, 0);
2356
2357         fw_data = (const __be32 *)rdev->rlc_fw->data;
2358         if (rdev->family >= CHIP_RV770) {
2359                 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2360                         WREG32(RLC_UCODE_ADDR, i);
2361                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2362                 }
2363         } else {
2364                 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2365                         WREG32(RLC_UCODE_ADDR, i);
2366                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2367                 }
2368         }
2369         WREG32(RLC_UCODE_ADDR, 0);
2370
2371         r600_rlc_start(rdev);
2372
2373         return 0;
2374 }
2375
2376 static void r600_enable_interrupts(struct radeon_device *rdev)
2377 {
2378         u32 ih_cntl = RREG32(IH_CNTL);
2379         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2380
2381         ih_cntl |= ENABLE_INTR;
2382         ih_rb_cntl |= IH_RB_ENABLE;
2383         WREG32(IH_CNTL, ih_cntl);
2384         WREG32(IH_RB_CNTL, ih_rb_cntl);
2385         rdev->ih.enabled = true;
2386 }
2387
2388 static void r600_disable_interrupts(struct radeon_device *rdev)
2389 {
2390         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2391         u32 ih_cntl = RREG32(IH_CNTL);
2392
2393         ih_rb_cntl &= ~IH_RB_ENABLE;
2394         ih_cntl &= ~ENABLE_INTR;
2395         WREG32(IH_RB_CNTL, ih_rb_cntl);
2396         WREG32(IH_CNTL, ih_cntl);
2397         /* set rptr, wptr to 0 */
2398         WREG32(IH_RB_RPTR, 0);
2399         WREG32(IH_RB_WPTR, 0);
2400         rdev->ih.enabled = false;
2401         rdev->ih.wptr = 0;
2402         rdev->ih.rptr = 0;
2403 }
2404
2405 static void r600_disable_interrupt_state(struct radeon_device *rdev)
2406 {
2407         u32 tmp;
2408
2409         WREG32(CP_INT_CNTL, 0);
2410         WREG32(GRBM_INT_CNTL, 0);
2411         WREG32(DxMODE_INT_MASK, 0);
2412         if (ASIC_IS_DCE3(rdev)) {
2413                 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2414                 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2415                 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2416                 WREG32(DC_HPD1_INT_CONTROL, tmp);
2417                 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2418                 WREG32(DC_HPD2_INT_CONTROL, tmp);
2419                 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2420                 WREG32(DC_HPD3_INT_CONTROL, tmp);
2421                 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2422                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2423                 if (ASIC_IS_DCE32(rdev)) {
2424                         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2425                         WREG32(DC_HPD5_INT_CONTROL, tmp);
2426                         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2427                         WREG32(DC_HPD6_INT_CONTROL, tmp);
2428                 }
2429         } else {
2430                 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2431                 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2432                 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2433                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
2434                 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2435                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
2436                 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2437                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
2438         }
2439 }
2440
2441 int r600_irq_init(struct radeon_device *rdev)
2442 {
2443         int ret = 0;
2444         int rb_bufsz;
2445         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2446
2447         /* allocate ring */
2448         ret = r600_ih_ring_alloc(rdev);
2449         if (ret)
2450                 return ret;
2451
2452         /* disable irqs */
2453         r600_disable_interrupts(rdev);
2454
2455         /* init rlc */
2456         ret = r600_rlc_init(rdev);
2457         if (ret) {
2458                 r600_ih_ring_fini(rdev);
2459                 return ret;
2460         }
2461
2462         /* setup interrupt control */
2463         /* set dummy read address to ring address */
2464         WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2465         interrupt_cntl = RREG32(INTERRUPT_CNTL);
2466         /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2467          * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2468          */
2469         interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
2470         /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2471         interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
2472         WREG32(INTERRUPT_CNTL, interrupt_cntl);
2473
2474         WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
2475         rb_bufsz = drm_order(rdev->ih.ring_size / 4);
2476
2477         ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
2478                       IH_WPTR_OVERFLOW_CLEAR |
2479                       (rb_bufsz << 1));
2480         /* WPTR writeback, not yet */
2481         /*ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;*/
2482         WREG32(IH_RB_WPTR_ADDR_LO, 0);
2483         WREG32(IH_RB_WPTR_ADDR_HI, 0);
2484
2485         WREG32(IH_RB_CNTL, ih_rb_cntl);
2486
2487         /* set rptr, wptr to 0 */
2488         WREG32(IH_RB_RPTR, 0);
2489         WREG32(IH_RB_WPTR, 0);
2490
2491         /* Default settings for IH_CNTL (disabled at first) */
2492         ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2493         /* RPTR_REARM only works if msi's are enabled */
2494         if (rdev->msi_enabled)
2495                 ih_cntl |= RPTR_REARM;
2496
2497 #ifdef __BIG_ENDIAN
2498         ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT);
2499 #endif
2500         WREG32(IH_CNTL, ih_cntl);
2501
2502         /* force the active interrupt state to all disabled */
2503         r600_disable_interrupt_state(rdev);
2504
2505         /* enable irqs */
2506         r600_enable_interrupts(rdev);
2507
2508         return ret;
2509 }
2510
2511 void r600_irq_suspend(struct radeon_device *rdev)
2512 {
2513         r600_disable_interrupts(rdev);
2514         r600_rlc_stop(rdev);
2515 }
2516
2517 void r600_irq_fini(struct radeon_device *rdev)
2518 {
2519         r600_irq_suspend(rdev);
2520         r600_ih_ring_fini(rdev);
2521 }
2522
2523 int r600_irq_set(struct radeon_device *rdev)
2524 {
2525         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2526         u32 mode_int = 0;
2527         u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
2528
2529         if (!rdev->irq.installed) {
2530                 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
2531                 return -EINVAL;
2532         }
2533         /* don't enable anything if the ih is disabled */
2534         if (!rdev->ih.enabled) {
2535                 r600_disable_interrupts(rdev);
2536                 /* force the active interrupt state to all disabled */
2537                 r600_disable_interrupt_state(rdev);
2538                 return 0;
2539         }
2540
2541         if (ASIC_IS_DCE3(rdev)) {
2542                 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2543                 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2544                 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2545                 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2546                 if (ASIC_IS_DCE32(rdev)) {
2547                         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2548                         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2549                 }
2550         } else {
2551                 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2552                 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2553                 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2554         }
2555
2556         if (rdev->irq.sw_int) {
2557                 DRM_DEBUG("r600_irq_set: sw int\n");
2558                 cp_int_cntl |= RB_INT_ENABLE;
2559         }
2560         if (rdev->irq.crtc_vblank_int[0]) {
2561                 DRM_DEBUG("r600_irq_set: vblank 0\n");
2562                 mode_int |= D1MODE_VBLANK_INT_MASK;
2563         }
2564         if (rdev->irq.crtc_vblank_int[1]) {
2565                 DRM_DEBUG("r600_irq_set: vblank 1\n");
2566                 mode_int |= D2MODE_VBLANK_INT_MASK;
2567         }
2568         if (rdev->irq.hpd[0]) {
2569                 DRM_DEBUG("r600_irq_set: hpd 1\n");
2570                 hpd1 |= DC_HPDx_INT_EN;
2571         }
2572         if (rdev->irq.hpd[1]) {
2573                 DRM_DEBUG("r600_irq_set: hpd 2\n");
2574                 hpd2 |= DC_HPDx_INT_EN;
2575         }
2576         if (rdev->irq.hpd[2]) {
2577                 DRM_DEBUG("r600_irq_set: hpd 3\n");
2578                 hpd3 |= DC_HPDx_INT_EN;
2579         }
2580         if (rdev->irq.hpd[3]) {
2581                 DRM_DEBUG("r600_irq_set: hpd 4\n");
2582                 hpd4 |= DC_HPDx_INT_EN;
2583         }
2584         if (rdev->irq.hpd[4]) {
2585                 DRM_DEBUG("r600_irq_set: hpd 5\n");
2586                 hpd5 |= DC_HPDx_INT_EN;
2587         }
2588         if (rdev->irq.hpd[5]) {
2589                 DRM_DEBUG("r600_irq_set: hpd 6\n");
2590                 hpd6 |= DC_HPDx_INT_EN;
2591         }
2592
2593         WREG32(CP_INT_CNTL, cp_int_cntl);
2594         WREG32(DxMODE_INT_MASK, mode_int);
2595         if (ASIC_IS_DCE3(rdev)) {
2596                 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2597                 WREG32(DC_HPD2_INT_CONTROL, hpd2);
2598                 WREG32(DC_HPD3_INT_CONTROL, hpd3);
2599                 WREG32(DC_HPD4_INT_CONTROL, hpd4);
2600                 if (ASIC_IS_DCE32(rdev)) {
2601                         WREG32(DC_HPD5_INT_CONTROL, hpd5);
2602                         WREG32(DC_HPD6_INT_CONTROL, hpd6);
2603                 }
2604         } else {
2605                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
2606                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
2607                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
2608         }
2609
2610         return 0;
2611 }
2612
2613 static inline void r600_irq_ack(struct radeon_device *rdev,
2614                                 u32 *disp_int,
2615                                 u32 *disp_int_cont,
2616                                 u32 *disp_int_cont2)
2617 {
2618         u32 tmp;
2619
2620         if (ASIC_IS_DCE3(rdev)) {
2621                 *disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
2622                 *disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
2623                 *disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
2624         } else {
2625                 *disp_int = RREG32(DISP_INTERRUPT_STATUS);
2626                 *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2627                 *disp_int_cont2 = 0;
2628         }
2629
2630         if (*disp_int & LB_D1_VBLANK_INTERRUPT)
2631                 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
2632         if (*disp_int & LB_D1_VLINE_INTERRUPT)
2633                 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
2634         if (*disp_int & LB_D2_VBLANK_INTERRUPT)
2635                 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
2636         if (*disp_int & LB_D2_VLINE_INTERRUPT)
2637                 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
2638         if (*disp_int & DC_HPD1_INTERRUPT) {
2639                 if (ASIC_IS_DCE3(rdev)) {
2640                         tmp = RREG32(DC_HPD1_INT_CONTROL);
2641                         tmp |= DC_HPDx_INT_ACK;
2642                         WREG32(DC_HPD1_INT_CONTROL, tmp);
2643                 } else {
2644                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
2645                         tmp |= DC_HPDx_INT_ACK;
2646                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
2647                 }
2648         }
2649         if (*disp_int & DC_HPD2_INTERRUPT) {
2650                 if (ASIC_IS_DCE3(rdev)) {
2651                         tmp = RREG32(DC_HPD2_INT_CONTROL);
2652                         tmp |= DC_HPDx_INT_ACK;
2653                         WREG32(DC_HPD2_INT_CONTROL, tmp);
2654                 } else {
2655                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
2656                         tmp |= DC_HPDx_INT_ACK;
2657                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
2658                 }
2659         }
2660         if (*disp_int_cont & DC_HPD3_INTERRUPT) {
2661                 if (ASIC_IS_DCE3(rdev)) {
2662                         tmp = RREG32(DC_HPD3_INT_CONTROL);
2663                         tmp |= DC_HPDx_INT_ACK;
2664                         WREG32(DC_HPD3_INT_CONTROL, tmp);
2665                 } else {
2666                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
2667                         tmp |= DC_HPDx_INT_ACK;
2668                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
2669                 }
2670         }
2671         if (*disp_int_cont & DC_HPD4_INTERRUPT) {
2672                 tmp = RREG32(DC_HPD4_INT_CONTROL);
2673                 tmp |= DC_HPDx_INT_ACK;
2674                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2675         }
2676         if (ASIC_IS_DCE32(rdev)) {
2677                 if (*disp_int_cont2 & DC_HPD5_INTERRUPT) {
2678                         tmp = RREG32(DC_HPD5_INT_CONTROL);
2679                         tmp |= DC_HPDx_INT_ACK;
2680                         WREG32(DC_HPD5_INT_CONTROL, tmp);
2681                 }
2682                 if (*disp_int_cont2 & DC_HPD6_INTERRUPT) {
2683                         tmp = RREG32(DC_HPD5_INT_CONTROL);
2684                         tmp |= DC_HPDx_INT_ACK;
2685                         WREG32(DC_HPD6_INT_CONTROL, tmp);
2686                 }
2687         }
2688 }
2689
2690 void r600_irq_disable(struct radeon_device *rdev)
2691 {
2692         u32 disp_int, disp_int_cont, disp_int_cont2;
2693
2694         r600_disable_interrupts(rdev);
2695         /* Wait and acknowledge irq */
2696         mdelay(1);
2697         r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
2698         r600_disable_interrupt_state(rdev);
2699 }
2700
2701 static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
2702 {
2703         u32 wptr, tmp;
2704
2705         /* XXX use writeback */
2706         wptr = RREG32(IH_RB_WPTR);
2707
2708         if (wptr & RB_OVERFLOW) {
2709                 /* When a ring buffer overflow happen start parsing interrupt
2710                  * from the last not overwritten vector (wptr + 16). Hopefully
2711                  * this should allow us to catchup.
2712                  */
2713                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2714                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2715                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2716                 tmp = RREG32(IH_RB_CNTL);
2717                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2718                 WREG32(IH_RB_CNTL, tmp);
2719         }
2720         return (wptr & rdev->ih.ptr_mask);
2721 }
2722
2723 /*        r600 IV Ring
2724  * Each IV ring entry is 128 bits:
2725  * [7:0]    - interrupt source id
2726  * [31:8]   - reserved
2727  * [59:32]  - interrupt source data
2728  * [127:60]  - reserved
2729  *
2730  * The basic interrupt vector entries
2731  * are decoded as follows:
2732  * src_id  src_data  description
2733  *      1         0  D1 Vblank
2734  *      1         1  D1 Vline
2735  *      5         0  D2 Vblank
2736  *      5         1  D2 Vline
2737  *     19         0  FP Hot plug detection A
2738  *     19         1  FP Hot plug detection B
2739  *     19         2  DAC A auto-detection
2740  *     19         3  DAC B auto-detection
2741  *    176         -  CP_INT RB
2742  *    177         -  CP_INT IB1
2743  *    178         -  CP_INT IB2
2744  *    181         -  EOP Interrupt
2745  *    233         -  GUI Idle
2746  *
2747  * Note, these are based on r600 and may need to be
2748  * adjusted or added to on newer asics
2749  */
2750
2751 int r600_irq_process(struct radeon_device *rdev)
2752 {
2753         u32 wptr = r600_get_ih_wptr(rdev);
2754         u32 rptr = rdev->ih.rptr;
2755         u32 src_id, src_data;
2756         u32 ring_index, disp_int, disp_int_cont, disp_int_cont2;
2757         unsigned long flags;
2758         bool queue_hotplug = false;
2759
2760         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2761         if (!rdev->ih.enabled)
2762                 return IRQ_NONE;
2763
2764         spin_lock_irqsave(&rdev->ih.lock, flags);
2765
2766         if (rptr == wptr) {
2767                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2768                 return IRQ_NONE;
2769         }
2770         if (rdev->shutdown) {
2771                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2772                 return IRQ_NONE;
2773         }
2774
2775 restart_ih:
2776         /* display interrupts */
2777         r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
2778
2779         rdev->ih.wptr = wptr;
2780         while (rptr != wptr) {
2781                 /* wptr/rptr are in bytes! */
2782                 ring_index = rptr / 4;
2783                 src_id =  rdev->ih.ring[ring_index] & 0xff;
2784                 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
2785
2786                 switch (src_id) {
2787                 case 1: /* D1 vblank/vline */
2788                         switch (src_data) {
2789                         case 0: /* D1 vblank */
2790                                 if (disp_int & LB_D1_VBLANK_INTERRUPT) {
2791                                         drm_handle_vblank(rdev->ddev, 0);
2792                                         rdev->pm.vblank_sync = true;
2793                                         wake_up(&rdev->irq.vblank_queue);
2794                                         disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2795                                         DRM_DEBUG("IH: D1 vblank\n");
2796                                 }
2797                                 break;
2798                         case 1: /* D1 vline */
2799                                 if (disp_int & LB_D1_VLINE_INTERRUPT) {
2800                                         disp_int &= ~LB_D1_VLINE_INTERRUPT;
2801                                         DRM_DEBUG("IH: D1 vline\n");
2802                                 }
2803                                 break;
2804                         default:
2805                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2806                                 break;
2807                         }
2808                         break;
2809                 case 5: /* D2 vblank/vline */
2810                         switch (src_data) {
2811                         case 0: /* D2 vblank */
2812                                 if (disp_int & LB_D2_VBLANK_INTERRUPT) {
2813                                         drm_handle_vblank(rdev->ddev, 1);
2814                                         rdev->pm.vblank_sync = true;
2815                                         wake_up(&rdev->irq.vblank_queue);
2816                                         disp_int &= ~LB_D2_VBLANK_INTERRUPT;
2817                                         DRM_DEBUG("IH: D2 vblank\n");
2818                                 }
2819                                 break;
2820                         case 1: /* D1 vline */
2821                                 if (disp_int & LB_D2_VLINE_INTERRUPT) {
2822                                         disp_int &= ~LB_D2_VLINE_INTERRUPT;
2823                                         DRM_DEBUG("IH: D2 vline\n");
2824                                 }
2825                                 break;
2826                         default:
2827                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2828                                 break;
2829                         }
2830                         break;
2831                 case 19: /* HPD/DAC hotplug */
2832                         switch (src_data) {
2833                         case 0:
2834                                 if (disp_int & DC_HPD1_INTERRUPT) {
2835                                         disp_int &= ~DC_HPD1_INTERRUPT;
2836                                         queue_hotplug = true;
2837                                         DRM_DEBUG("IH: HPD1\n");
2838                                 }
2839                                 break;
2840                         case 1:
2841                                 if (disp_int & DC_HPD2_INTERRUPT) {
2842                                         disp_int &= ~DC_HPD2_INTERRUPT;
2843                                         queue_hotplug = true;
2844                                         DRM_DEBUG("IH: HPD2\n");
2845                                 }
2846                                 break;
2847                         case 4:
2848                                 if (disp_int_cont & DC_HPD3_INTERRUPT) {
2849                                         disp_int_cont &= ~DC_HPD3_INTERRUPT;
2850                                         queue_hotplug = true;
2851                                         DRM_DEBUG("IH: HPD3\n");
2852                                 }
2853                                 break;
2854                         case 5:
2855                                 if (disp_int_cont & DC_HPD4_INTERRUPT) {
2856                                         disp_int_cont &= ~DC_HPD4_INTERRUPT;
2857                                         queue_hotplug = true;
2858                                         DRM_DEBUG("IH: HPD4\n");
2859                                 }
2860                                 break;
2861                         case 10:
2862                                 if (disp_int_cont2 & DC_HPD5_INTERRUPT) {
2863                                         disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
2864                                         queue_hotplug = true;
2865                                         DRM_DEBUG("IH: HPD5\n");
2866                                 }
2867                                 break;
2868                         case 12:
2869                                 if (disp_int_cont2 & DC_HPD6_INTERRUPT) {
2870                                         disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
2871                                         queue_hotplug = true;
2872                                         DRM_DEBUG("IH: HPD6\n");
2873                                 }
2874                                 break;
2875                         default:
2876                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2877                                 break;
2878                         }
2879                         break;
2880                 case 176: /* CP_INT in ring buffer */
2881                 case 177: /* CP_INT in IB1 */
2882                 case 178: /* CP_INT in IB2 */
2883                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
2884                         radeon_fence_process(rdev);
2885                         break;
2886                 case 181: /* CP EOP event */
2887                         DRM_DEBUG("IH: CP EOP\n");
2888                         break;
2889                 default:
2890                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2891                         break;
2892                 }
2893
2894                 /* wptr/rptr are in bytes! */
2895                 rptr += 16;
2896                 rptr &= rdev->ih.ptr_mask;
2897         }
2898         /* make sure wptr hasn't changed while processing */
2899         wptr = r600_get_ih_wptr(rdev);
2900         if (wptr != rdev->ih.wptr)
2901                 goto restart_ih;
2902         if (queue_hotplug)
2903                 queue_work(rdev->wq, &rdev->hotplug_work);
2904         rdev->ih.rptr = rptr;
2905         WREG32(IH_RB_RPTR, rdev->ih.rptr);
2906         spin_unlock_irqrestore(&rdev->ih.lock, flags);
2907         return IRQ_HANDLED;
2908 }
2909
2910 /*
2911  * Debugfs info
2912  */
2913 #if defined(CONFIG_DEBUG_FS)
2914
2915 static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
2916 {
2917         struct drm_info_node *node = (struct drm_info_node *) m->private;
2918         struct drm_device *dev = node->minor->dev;
2919         struct radeon_device *rdev = dev->dev_private;
2920         unsigned count, i, j;
2921
2922         radeon_ring_free_size(rdev);
2923         count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
2924         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
2925         seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
2926         seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
2927         seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
2928         seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
2929         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2930         seq_printf(m, "%u dwords in ring\n", count);
2931         i = rdev->cp.rptr;
2932         for (j = 0; j <= count; j++) {
2933                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2934                 i = (i + 1) & rdev->cp.ptr_mask;
2935         }
2936         return 0;
2937 }
2938
2939 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
2940 {
2941         struct drm_info_node *node = (struct drm_info_node *) m->private;
2942         struct drm_device *dev = node->minor->dev;
2943         struct radeon_device *rdev = dev->dev_private;
2944
2945         DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
2946         DREG32_SYS(m, rdev, VM_L2_STATUS);
2947         return 0;
2948 }
2949
2950 static struct drm_info_list r600_mc_info_list[] = {
2951         {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
2952         {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
2953 };
2954 #endif
2955
2956 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
2957 {
2958 #if defined(CONFIG_DEBUG_FS)
2959         return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
2960 #else
2961         return 0;
2962 #endif
2963 }
2964
2965 /**
2966  * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
2967  * rdev: radeon device structure
2968  * bo: buffer object struct which userspace is waiting for idle
2969  *
2970  * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
2971  * through ring buffer, this leads to corruption in rendering, see
2972  * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
2973  * directly perform HDP flush by writing register through MMIO.
2974  */
2975 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
2976 {
2977         WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2978 }