2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
29 #include <linux/firmware.h>
30 #include <linux/platform_device.h>
32 #include "radeon_drm.h"
34 #include "radeon_mode.h"
39 #define PFP_UCODE_SIZE 576
40 #define PM4_UCODE_SIZE 1792
41 #define RLC_UCODE_SIZE 768
42 #define R700_PFP_UCODE_SIZE 848
43 #define R700_PM4_UCODE_SIZE 1360
44 #define R700_RLC_UCODE_SIZE 1024
47 MODULE_FIRMWARE("radeon/R600_pfp.bin");
48 MODULE_FIRMWARE("radeon/R600_me.bin");
49 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
50 MODULE_FIRMWARE("radeon/RV610_me.bin");
51 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
52 MODULE_FIRMWARE("radeon/RV630_me.bin");
53 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
54 MODULE_FIRMWARE("radeon/RV620_me.bin");
55 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
56 MODULE_FIRMWARE("radeon/RV635_me.bin");
57 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
58 MODULE_FIRMWARE("radeon/RV670_me.bin");
59 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
60 MODULE_FIRMWARE("radeon/RS780_me.bin");
61 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
62 MODULE_FIRMWARE("radeon/RV770_me.bin");
63 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
64 MODULE_FIRMWARE("radeon/RV730_me.bin");
65 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
66 MODULE_FIRMWARE("radeon/RV710_me.bin");
67 MODULE_FIRMWARE("radeon/R600_rlc.bin");
68 MODULE_FIRMWARE("radeon/R700_rlc.bin");
70 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
72 /* r600,rv610,rv630,rv620,rv635,rv670 */
73 int r600_mc_wait_for_idle(struct radeon_device *rdev);
74 void r600_gpu_init(struct radeon_device *rdev);
75 void r600_fini(struct radeon_device *rdev);
77 /* hpd for digital panel detect/disconnect */
78 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
80 bool connected = false;
82 if (ASIC_IS_DCE3(rdev)) {
85 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
89 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
93 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
97 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
102 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
106 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
115 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
119 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
123 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
133 void r600_hpd_set_polarity(struct radeon_device *rdev,
134 enum radeon_hpd_id hpd)
137 bool connected = r600_hpd_sense(rdev, hpd);
139 if (ASIC_IS_DCE3(rdev)) {
142 tmp = RREG32(DC_HPD1_INT_CONTROL);
144 tmp &= ~DC_HPDx_INT_POLARITY;
146 tmp |= DC_HPDx_INT_POLARITY;
147 WREG32(DC_HPD1_INT_CONTROL, tmp);
150 tmp = RREG32(DC_HPD2_INT_CONTROL);
152 tmp &= ~DC_HPDx_INT_POLARITY;
154 tmp |= DC_HPDx_INT_POLARITY;
155 WREG32(DC_HPD2_INT_CONTROL, tmp);
158 tmp = RREG32(DC_HPD3_INT_CONTROL);
160 tmp &= ~DC_HPDx_INT_POLARITY;
162 tmp |= DC_HPDx_INT_POLARITY;
163 WREG32(DC_HPD3_INT_CONTROL, tmp);
166 tmp = RREG32(DC_HPD4_INT_CONTROL);
168 tmp &= ~DC_HPDx_INT_POLARITY;
170 tmp |= DC_HPDx_INT_POLARITY;
171 WREG32(DC_HPD4_INT_CONTROL, tmp);
174 tmp = RREG32(DC_HPD5_INT_CONTROL);
176 tmp &= ~DC_HPDx_INT_POLARITY;
178 tmp |= DC_HPDx_INT_POLARITY;
179 WREG32(DC_HPD5_INT_CONTROL, tmp);
183 tmp = RREG32(DC_HPD6_INT_CONTROL);
185 tmp &= ~DC_HPDx_INT_POLARITY;
187 tmp |= DC_HPDx_INT_POLARITY;
188 WREG32(DC_HPD6_INT_CONTROL, tmp);
196 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
198 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
200 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
201 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
204 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
206 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
208 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
209 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
212 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
214 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
216 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
217 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
225 void r600_hpd_init(struct radeon_device *rdev)
227 struct drm_device *dev = rdev->ddev;
228 struct drm_connector *connector;
230 if (ASIC_IS_DCE3(rdev)) {
231 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
232 if (ASIC_IS_DCE32(rdev))
235 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
236 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
237 switch (radeon_connector->hpd.hpd) {
239 WREG32(DC_HPD1_CONTROL, tmp);
240 rdev->irq.hpd[0] = true;
243 WREG32(DC_HPD2_CONTROL, tmp);
244 rdev->irq.hpd[1] = true;
247 WREG32(DC_HPD3_CONTROL, tmp);
248 rdev->irq.hpd[2] = true;
251 WREG32(DC_HPD4_CONTROL, tmp);
252 rdev->irq.hpd[3] = true;
256 WREG32(DC_HPD5_CONTROL, tmp);
257 rdev->irq.hpd[4] = true;
260 WREG32(DC_HPD6_CONTROL, tmp);
261 rdev->irq.hpd[5] = true;
268 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
269 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
270 switch (radeon_connector->hpd.hpd) {
272 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
273 rdev->irq.hpd[0] = true;
276 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
277 rdev->irq.hpd[1] = true;
280 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
281 rdev->irq.hpd[2] = true;
288 if (rdev->irq.installed)
292 void r600_hpd_fini(struct radeon_device *rdev)
294 struct drm_device *dev = rdev->ddev;
295 struct drm_connector *connector;
297 if (ASIC_IS_DCE3(rdev)) {
298 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
299 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
300 switch (radeon_connector->hpd.hpd) {
302 WREG32(DC_HPD1_CONTROL, 0);
303 rdev->irq.hpd[0] = false;
306 WREG32(DC_HPD2_CONTROL, 0);
307 rdev->irq.hpd[1] = false;
310 WREG32(DC_HPD3_CONTROL, 0);
311 rdev->irq.hpd[2] = false;
314 WREG32(DC_HPD4_CONTROL, 0);
315 rdev->irq.hpd[3] = false;
319 WREG32(DC_HPD5_CONTROL, 0);
320 rdev->irq.hpd[4] = false;
323 WREG32(DC_HPD6_CONTROL, 0);
324 rdev->irq.hpd[5] = false;
331 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
332 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
333 switch (radeon_connector->hpd.hpd) {
335 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
336 rdev->irq.hpd[0] = false;
339 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
340 rdev->irq.hpd[1] = false;
343 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
344 rdev->irq.hpd[2] = false;
356 int r600_gart_clear_page(struct radeon_device *rdev, int i)
358 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
361 if (i < 0 || i > rdev->gart.num_gpu_pages)
364 writeq(pte, ((void __iomem *)ptr) + (i * 8));
368 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
373 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
374 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
375 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
376 for (i = 0; i < rdev->usec_timeout; i++) {
378 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
379 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
381 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
391 int r600_pcie_gart_init(struct radeon_device *rdev)
395 if (rdev->gart.table.vram.robj) {
396 WARN(1, "R600 PCIE GART already initialized.\n");
399 /* Initialize common gart structure */
400 r = radeon_gart_init(rdev);
403 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
404 return radeon_gart_table_vram_alloc(rdev);
407 int r600_pcie_gart_enable(struct radeon_device *rdev)
412 if (rdev->gart.table.vram.robj == NULL) {
413 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
416 r = radeon_gart_table_vram_pin(rdev);
421 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
422 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
423 EFFECTIVE_L2_QUEUE_SIZE(7));
424 WREG32(VM_L2_CNTL2, 0);
425 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
426 /* Setup TLB control */
427 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
428 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
429 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
430 ENABLE_WAIT_L2_QUERY;
431 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
432 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
433 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
434 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
435 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
436 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
437 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
438 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
439 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
440 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
441 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
442 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
443 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
444 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
445 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
446 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
447 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
448 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
449 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
450 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
451 (u32)(rdev->dummy_page.addr >> 12));
452 for (i = 1; i < 7; i++)
453 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
455 r600_pcie_gart_tlb_flush(rdev);
456 rdev->gart.ready = true;
460 void r600_pcie_gart_disable(struct radeon_device *rdev)
465 /* Disable all tables */
466 for (i = 0; i < 7; i++)
467 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
469 /* Disable L2 cache */
470 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
471 EFFECTIVE_L2_QUEUE_SIZE(7));
472 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
473 /* Setup L1 TLB control */
474 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
475 ENABLE_WAIT_L2_QUERY;
476 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
477 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
478 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
479 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
480 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
481 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
482 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
483 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
484 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
485 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
486 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
487 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
488 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
489 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
490 if (rdev->gart.table.vram.robj) {
491 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
492 if (likely(r == 0)) {
493 radeon_bo_kunmap(rdev->gart.table.vram.robj);
494 radeon_bo_unpin(rdev->gart.table.vram.robj);
495 radeon_bo_unreserve(rdev->gart.table.vram.robj);
500 void r600_pcie_gart_fini(struct radeon_device *rdev)
502 r600_pcie_gart_disable(rdev);
503 radeon_gart_table_vram_free(rdev);
504 radeon_gart_fini(rdev);
507 void r600_agp_enable(struct radeon_device *rdev)
513 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
514 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
515 EFFECTIVE_L2_QUEUE_SIZE(7));
516 WREG32(VM_L2_CNTL2, 0);
517 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
518 /* Setup TLB control */
519 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
520 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
521 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
522 ENABLE_WAIT_L2_QUERY;
523 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
524 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
525 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
526 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
527 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
528 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
529 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
530 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
531 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
532 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
533 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
534 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
535 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
536 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
537 for (i = 0; i < 7; i++)
538 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
541 int r600_mc_wait_for_idle(struct radeon_device *rdev)
546 for (i = 0; i < rdev->usec_timeout; i++) {
548 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
556 static void r600_mc_program(struct radeon_device *rdev)
558 struct rv515_mc_save save;
563 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
564 WREG32((0x2c14 + j), 0x00000000);
565 WREG32((0x2c18 + j), 0x00000000);
566 WREG32((0x2c1c + j), 0x00000000);
567 WREG32((0x2c20 + j), 0x00000000);
568 WREG32((0x2c24 + j), 0x00000000);
570 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
572 rv515_mc_stop(rdev, &save);
573 if (r600_mc_wait_for_idle(rdev)) {
574 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
576 /* Lockout access through VGA aperture (doesn't exist before R600) */
577 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
578 /* Update configuration */
579 if (rdev->flags & RADEON_IS_AGP) {
580 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
581 /* VRAM before AGP */
582 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
583 rdev->mc.vram_start >> 12);
584 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
585 rdev->mc.gtt_end >> 12);
588 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
589 rdev->mc.gtt_start >> 12);
590 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
591 rdev->mc.vram_end >> 12);
594 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
595 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
597 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
598 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
599 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
600 WREG32(MC_VM_FB_LOCATION, tmp);
601 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
602 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
603 WREG32(HDP_NONSURFACE_SIZE, rdev->mc.mc_vram_size | 0x3FF);
604 if (rdev->flags & RADEON_IS_AGP) {
605 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
606 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
607 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
609 WREG32(MC_VM_AGP_BASE, 0);
610 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
611 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
613 if (r600_mc_wait_for_idle(rdev)) {
614 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
616 rv515_mc_resume(rdev, &save);
617 /* we need to own VRAM, so turn off the VGA renderer here
618 * to stop it overwriting our objects */
619 rv515_vga_render_disable(rdev);
622 int r600_mc_init(struct radeon_device *rdev)
626 int chansize, numchan;
629 /* Get VRAM informations */
630 rdev->mc.vram_is_ddr = true;
631 tmp = RREG32(RAMCFG);
632 if (tmp & CHANSIZE_OVERRIDE) {
634 } else if (tmp & CHANSIZE_MASK) {
640 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
655 rdev->mc.vram_width = numchan * chansize;
656 /* Could aper size report 0 ? */
657 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
658 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
659 /* Setup GPU memory space */
660 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
661 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
663 if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
664 rdev->mc.mc_vram_size = rdev->mc.aper_size;
666 if (rdev->mc.real_vram_size > rdev->mc.aper_size)
667 rdev->mc.real_vram_size = rdev->mc.aper_size;
669 if (rdev->flags & RADEON_IS_AGP) {
670 r = radeon_agp_init(rdev);
673 /* gtt_size is setup by radeon_agp_init */
674 rdev->mc.gtt_location = rdev->mc.agp_base;
675 tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
676 /* Try to put vram before or after AGP because we
677 * we want SYSTEM_APERTURE to cover both VRAM and
678 * AGP so that GPU can catch out of VRAM/AGP access
680 if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) {
681 /* Enought place before */
682 rdev->mc.vram_location = rdev->mc.gtt_location -
683 rdev->mc.mc_vram_size;
684 } else if (tmp > rdev->mc.mc_vram_size) {
685 /* Enought place after */
686 rdev->mc.vram_location = rdev->mc.gtt_location +
689 /* Try to setup VRAM then AGP might not
690 * not work on some card
692 rdev->mc.vram_location = 0x00000000UL;
693 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
696 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
697 rdev->mc.vram_location = (RREG32(MC_VM_FB_LOCATION) &
699 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
700 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
701 /* Enough place after vram */
702 rdev->mc.gtt_location = tmp;
703 } else if (rdev->mc.vram_location >= rdev->mc.gtt_size) {
704 /* Enough place before vram */
705 rdev->mc.gtt_location = 0;
707 /* Not enough place after or before shrink
710 if (rdev->mc.vram_location > (0xFFFFFFFFUL - tmp)) {
711 rdev->mc.gtt_location = 0;
712 rdev->mc.gtt_size = rdev->mc.vram_location;
714 rdev->mc.gtt_location = tmp;
715 rdev->mc.gtt_size = 0xFFFFFFFFUL - tmp;
718 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
720 rdev->mc.vram_start = rdev->mc.vram_location;
721 rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
722 rdev->mc.gtt_start = rdev->mc.gtt_location;
723 rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
724 /* FIXME: we should enforce default clock in case GPU is not in
727 a.full = rfixed_const(100);
728 rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
729 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
731 if (rdev->flags & RADEON_IS_IGP)
732 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
737 /* We doesn't check that the GPU really needs a reset we simply do the
738 * reset, it's up to the caller to determine if the GPU needs one. We
739 * might add an helper function to check that.
741 int r600_gpu_soft_reset(struct radeon_device *rdev)
743 struct rv515_mc_save save;
744 u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
745 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
746 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
747 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
748 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
749 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
750 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
751 S_008010_GUI_ACTIVE(1);
752 u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
753 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
754 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
755 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
756 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
757 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
758 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
759 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
763 dev_info(rdev->dev, "GPU softreset \n");
764 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
765 RREG32(R_008010_GRBM_STATUS));
766 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
767 RREG32(R_008014_GRBM_STATUS2));
768 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
769 RREG32(R_000E50_SRBM_STATUS));
770 rv515_mc_stop(rdev, &save);
771 if (r600_mc_wait_for_idle(rdev)) {
772 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
774 /* Disable CP parsing/prefetching */
775 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(0xff));
776 /* Check if any of the rendering block is busy and reset it */
777 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
778 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
779 tmp = S_008020_SOFT_RESET_CR(1) |
780 S_008020_SOFT_RESET_DB(1) |
781 S_008020_SOFT_RESET_CB(1) |
782 S_008020_SOFT_RESET_PA(1) |
783 S_008020_SOFT_RESET_SC(1) |
784 S_008020_SOFT_RESET_SMX(1) |
785 S_008020_SOFT_RESET_SPI(1) |
786 S_008020_SOFT_RESET_SX(1) |
787 S_008020_SOFT_RESET_SH(1) |
788 S_008020_SOFT_RESET_TC(1) |
789 S_008020_SOFT_RESET_TA(1) |
790 S_008020_SOFT_RESET_VC(1) |
791 S_008020_SOFT_RESET_VGT(1);
792 dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
793 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
794 (void)RREG32(R_008020_GRBM_SOFT_RESET);
796 WREG32(R_008020_GRBM_SOFT_RESET, 0);
797 (void)RREG32(R_008020_GRBM_SOFT_RESET);
799 /* Reset CP (we always reset CP) */
800 tmp = S_008020_SOFT_RESET_CP(1);
801 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
802 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
803 (void)RREG32(R_008020_GRBM_SOFT_RESET);
805 WREG32(R_008020_GRBM_SOFT_RESET, 0);
806 (void)RREG32(R_008020_GRBM_SOFT_RESET);
807 /* Reset others GPU block if necessary */
808 if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
809 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
810 if (G_000E50_GRBM_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
811 srbm_reset |= S_000E60_SOFT_RESET_GRBM(1);
812 if (G_000E50_HI_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
813 srbm_reset |= S_000E60_SOFT_RESET_IH(1);
814 if (G_000E50_VMC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
815 srbm_reset |= S_000E60_SOFT_RESET_VMC(1);
816 if (G_000E50_MCB_BUSY(RREG32(R_000E50_SRBM_STATUS)))
817 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
818 if (G_000E50_MCDZ_BUSY(RREG32(R_000E50_SRBM_STATUS)))
819 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
820 if (G_000E50_MCDY_BUSY(RREG32(R_000E50_SRBM_STATUS)))
821 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
822 if (G_000E50_MCDX_BUSY(RREG32(R_000E50_SRBM_STATUS)))
823 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
824 if (G_000E50_MCDW_BUSY(RREG32(R_000E50_SRBM_STATUS)))
825 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
826 if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
827 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
828 if (G_000E50_SEM_BUSY(RREG32(R_000E50_SRBM_STATUS)))
829 srbm_reset |= S_000E60_SOFT_RESET_SEM(1);
830 if (G_000E50_BIF_BUSY(RREG32(R_000E50_SRBM_STATUS)))
831 srbm_reset |= S_000E60_SOFT_RESET_BIF(1);
832 dev_info(rdev->dev, " R_000E60_SRBM_SOFT_RESET=0x%08X\n", srbm_reset);
833 WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
834 (void)RREG32(R_000E60_SRBM_SOFT_RESET);
836 WREG32(R_000E60_SRBM_SOFT_RESET, 0);
837 (void)RREG32(R_000E60_SRBM_SOFT_RESET);
838 WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
839 (void)RREG32(R_000E60_SRBM_SOFT_RESET);
841 WREG32(R_000E60_SRBM_SOFT_RESET, 0);
842 (void)RREG32(R_000E60_SRBM_SOFT_RESET);
843 /* Wait a little for things to settle down */
845 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
846 RREG32(R_008010_GRBM_STATUS));
847 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
848 RREG32(R_008014_GRBM_STATUS2));
849 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
850 RREG32(R_000E50_SRBM_STATUS));
851 /* After reset we need to reinit the asic as GPU often endup in an
854 atom_asic_init(rdev->mode_info.atom_context);
855 rv515_mc_resume(rdev, &save);
859 int r600_gpu_reset(struct radeon_device *rdev)
861 return r600_gpu_soft_reset(rdev);
864 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
866 u32 backend_disable_mask)
869 u32 enabled_backends_mask;
870 u32 enabled_backends_count;
872 u32 swizzle_pipe[R6XX_MAX_PIPES];
876 if (num_tile_pipes > R6XX_MAX_PIPES)
877 num_tile_pipes = R6XX_MAX_PIPES;
878 if (num_tile_pipes < 1)
880 if (num_backends > R6XX_MAX_BACKENDS)
881 num_backends = R6XX_MAX_BACKENDS;
882 if (num_backends < 1)
885 enabled_backends_mask = 0;
886 enabled_backends_count = 0;
887 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
888 if (((backend_disable_mask >> i) & 1) == 0) {
889 enabled_backends_mask |= (1 << i);
890 ++enabled_backends_count;
892 if (enabled_backends_count == num_backends)
896 if (enabled_backends_count == 0) {
897 enabled_backends_mask = 1;
898 enabled_backends_count = 1;
901 if (enabled_backends_count != num_backends)
902 num_backends = enabled_backends_count;
904 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
905 switch (num_tile_pipes) {
961 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
962 while (((1 << cur_backend) & enabled_backends_mask) == 0)
963 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
965 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
967 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
973 int r600_count_pipe_bits(uint32_t val)
977 for (i = 0; i < 32; i++) {
984 void r600_gpu_init(struct radeon_device *rdev)
991 u32 sq_gpr_resource_mgmt_1 = 0;
992 u32 sq_gpr_resource_mgmt_2 = 0;
993 u32 sq_thread_resource_mgmt = 0;
994 u32 sq_stack_resource_mgmt_1 = 0;
995 u32 sq_stack_resource_mgmt_2 = 0;
997 /* FIXME: implement */
998 switch (rdev->family) {
1000 rdev->config.r600.max_pipes = 4;
1001 rdev->config.r600.max_tile_pipes = 8;
1002 rdev->config.r600.max_simds = 4;
1003 rdev->config.r600.max_backends = 4;
1004 rdev->config.r600.max_gprs = 256;
1005 rdev->config.r600.max_threads = 192;
1006 rdev->config.r600.max_stack_entries = 256;
1007 rdev->config.r600.max_hw_contexts = 8;
1008 rdev->config.r600.max_gs_threads = 16;
1009 rdev->config.r600.sx_max_export_size = 128;
1010 rdev->config.r600.sx_max_export_pos_size = 16;
1011 rdev->config.r600.sx_max_export_smx_size = 128;
1012 rdev->config.r600.sq_num_cf_insts = 2;
1016 rdev->config.r600.max_pipes = 2;
1017 rdev->config.r600.max_tile_pipes = 2;
1018 rdev->config.r600.max_simds = 3;
1019 rdev->config.r600.max_backends = 1;
1020 rdev->config.r600.max_gprs = 128;
1021 rdev->config.r600.max_threads = 192;
1022 rdev->config.r600.max_stack_entries = 128;
1023 rdev->config.r600.max_hw_contexts = 8;
1024 rdev->config.r600.max_gs_threads = 4;
1025 rdev->config.r600.sx_max_export_size = 128;
1026 rdev->config.r600.sx_max_export_pos_size = 16;
1027 rdev->config.r600.sx_max_export_smx_size = 128;
1028 rdev->config.r600.sq_num_cf_insts = 2;
1034 rdev->config.r600.max_pipes = 1;
1035 rdev->config.r600.max_tile_pipes = 1;
1036 rdev->config.r600.max_simds = 2;
1037 rdev->config.r600.max_backends = 1;
1038 rdev->config.r600.max_gprs = 128;
1039 rdev->config.r600.max_threads = 192;
1040 rdev->config.r600.max_stack_entries = 128;
1041 rdev->config.r600.max_hw_contexts = 4;
1042 rdev->config.r600.max_gs_threads = 4;
1043 rdev->config.r600.sx_max_export_size = 128;
1044 rdev->config.r600.sx_max_export_pos_size = 16;
1045 rdev->config.r600.sx_max_export_smx_size = 128;
1046 rdev->config.r600.sq_num_cf_insts = 1;
1049 rdev->config.r600.max_pipes = 4;
1050 rdev->config.r600.max_tile_pipes = 4;
1051 rdev->config.r600.max_simds = 4;
1052 rdev->config.r600.max_backends = 4;
1053 rdev->config.r600.max_gprs = 192;
1054 rdev->config.r600.max_threads = 192;
1055 rdev->config.r600.max_stack_entries = 256;
1056 rdev->config.r600.max_hw_contexts = 8;
1057 rdev->config.r600.max_gs_threads = 16;
1058 rdev->config.r600.sx_max_export_size = 128;
1059 rdev->config.r600.sx_max_export_pos_size = 16;
1060 rdev->config.r600.sx_max_export_smx_size = 128;
1061 rdev->config.r600.sq_num_cf_insts = 2;
1067 /* Initialize HDP */
1068 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1069 WREG32((0x2c14 + j), 0x00000000);
1070 WREG32((0x2c18 + j), 0x00000000);
1071 WREG32((0x2c1c + j), 0x00000000);
1072 WREG32((0x2c20 + j), 0x00000000);
1073 WREG32((0x2c24 + j), 0x00000000);
1076 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1080 ramcfg = RREG32(RAMCFG);
1081 switch (rdev->config.r600.max_tile_pipes) {
1083 tiling_config |= PIPE_TILING(0);
1086 tiling_config |= PIPE_TILING(1);
1089 tiling_config |= PIPE_TILING(2);
1092 tiling_config |= PIPE_TILING(3);
1097 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1098 tiling_config |= GROUP_SIZE(0);
1099 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1101 tiling_config |= ROW_TILING(3);
1102 tiling_config |= SAMPLE_SPLIT(3);
1104 tiling_config |= ROW_TILING(tmp);
1105 tiling_config |= SAMPLE_SPLIT(tmp);
1107 tiling_config |= BANK_SWAPS(1);
1108 tmp = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1109 rdev->config.r600.max_backends,
1110 (0xff << rdev->config.r600.max_backends) & 0xff);
1111 tiling_config |= BACKEND_MAP(tmp);
1112 WREG32(GB_TILING_CONFIG, tiling_config);
1113 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1114 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1116 tmp = BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1117 WREG32(CC_RB_BACKEND_DISABLE, tmp);
1120 tmp = INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1121 tmp |= INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1122 WREG32(CC_GC_SHADER_PIPE_CONFIG, tmp);
1123 WREG32(GC_USER_SHADER_PIPE_CONFIG, tmp);
1125 tmp = R6XX_MAX_BACKENDS - r600_count_pipe_bits(tmp & INACTIVE_QD_PIPES_MASK);
1126 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1127 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1129 /* Setup some CP states */
1130 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1131 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1133 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1134 SYNC_WALKER | SYNC_ALIGNER));
1135 /* Setup various GPU states */
1136 if (rdev->family == CHIP_RV670)
1137 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1139 tmp = RREG32(SX_DEBUG_1);
1140 tmp |= SMX_EVENT_RELEASE;
1141 if ((rdev->family > CHIP_R600))
1142 tmp |= ENABLE_NEW_SMX_ADDRESS;
1143 WREG32(SX_DEBUG_1, tmp);
1145 if (((rdev->family) == CHIP_R600) ||
1146 ((rdev->family) == CHIP_RV630) ||
1147 ((rdev->family) == CHIP_RV610) ||
1148 ((rdev->family) == CHIP_RV620) ||
1149 ((rdev->family) == CHIP_RS780) ||
1150 ((rdev->family) == CHIP_RS880)) {
1151 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1153 WREG32(DB_DEBUG, 0);
1155 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1156 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1158 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1159 WREG32(VGT_NUM_INSTANCES, 0);
1161 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1162 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1164 tmp = RREG32(SQ_MS_FIFO_SIZES);
1165 if (((rdev->family) == CHIP_RV610) ||
1166 ((rdev->family) == CHIP_RV620) ||
1167 ((rdev->family) == CHIP_RS780) ||
1168 ((rdev->family) == CHIP_RS880)) {
1169 tmp = (CACHE_FIFO_SIZE(0xa) |
1170 FETCH_FIFO_HIWATER(0xa) |
1171 DONE_FIFO_HIWATER(0xe0) |
1172 ALU_UPDATE_FIFO_HIWATER(0x8));
1173 } else if (((rdev->family) == CHIP_R600) ||
1174 ((rdev->family) == CHIP_RV630)) {
1175 tmp &= ~DONE_FIFO_HIWATER(0xff);
1176 tmp |= DONE_FIFO_HIWATER(0x4);
1178 WREG32(SQ_MS_FIFO_SIZES, tmp);
1180 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1181 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1183 sq_config = RREG32(SQ_CONFIG);
1184 sq_config &= ~(PS_PRIO(3) |
1188 sq_config |= (DX9_CONSTS |
1195 if ((rdev->family) == CHIP_R600) {
1196 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1198 NUM_CLAUSE_TEMP_GPRS(4));
1199 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1201 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1202 NUM_VS_THREADS(48) |
1205 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1206 NUM_VS_STACK_ENTRIES(128));
1207 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1208 NUM_ES_STACK_ENTRIES(0));
1209 } else if (((rdev->family) == CHIP_RV610) ||
1210 ((rdev->family) == CHIP_RV620) ||
1211 ((rdev->family) == CHIP_RS780) ||
1212 ((rdev->family) == CHIP_RS880)) {
1213 /* no vertex cache */
1214 sq_config &= ~VC_ENABLE;
1216 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1218 NUM_CLAUSE_TEMP_GPRS(2));
1219 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1221 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1222 NUM_VS_THREADS(78) |
1224 NUM_ES_THREADS(31));
1225 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1226 NUM_VS_STACK_ENTRIES(40));
1227 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1228 NUM_ES_STACK_ENTRIES(16));
1229 } else if (((rdev->family) == CHIP_RV630) ||
1230 ((rdev->family) == CHIP_RV635)) {
1231 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1233 NUM_CLAUSE_TEMP_GPRS(2));
1234 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1236 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1237 NUM_VS_THREADS(78) |
1239 NUM_ES_THREADS(31));
1240 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1241 NUM_VS_STACK_ENTRIES(40));
1242 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1243 NUM_ES_STACK_ENTRIES(16));
1244 } else if ((rdev->family) == CHIP_RV670) {
1245 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1247 NUM_CLAUSE_TEMP_GPRS(2));
1248 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1250 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1251 NUM_VS_THREADS(78) |
1253 NUM_ES_THREADS(31));
1254 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1255 NUM_VS_STACK_ENTRIES(64));
1256 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1257 NUM_ES_STACK_ENTRIES(64));
1260 WREG32(SQ_CONFIG, sq_config);
1261 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1262 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1263 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1264 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1265 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1267 if (((rdev->family) == CHIP_RV610) ||
1268 ((rdev->family) == CHIP_RV620) ||
1269 ((rdev->family) == CHIP_RS780) ||
1270 ((rdev->family) == CHIP_RS880)) {
1271 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1273 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1276 /* More default values. 2D/3D driver should adjust as needed */
1277 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1278 S1_X(0x4) | S1_Y(0xc)));
1279 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1280 S1_X(0x2) | S1_Y(0x2) |
1281 S2_X(0xa) | S2_Y(0x6) |
1282 S3_X(0x6) | S3_Y(0xa)));
1283 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1284 S1_X(0x4) | S1_Y(0xc) |
1285 S2_X(0x1) | S2_Y(0x6) |
1286 S3_X(0xa) | S3_Y(0xe)));
1287 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1288 S5_X(0x0) | S5_Y(0x0) |
1289 S6_X(0xb) | S6_Y(0x4) |
1290 S7_X(0x7) | S7_Y(0x8)));
1292 WREG32(VGT_STRMOUT_EN, 0);
1293 tmp = rdev->config.r600.max_pipes * 16;
1294 switch (rdev->family) {
1310 WREG32(VGT_ES_PER_GS, 128);
1311 WREG32(VGT_GS_PER_ES, tmp);
1312 WREG32(VGT_GS_PER_VS, 2);
1313 WREG32(VGT_GS_VERTEX_REUSE, 16);
1315 /* more default values. 2D/3D driver should adjust as needed */
1316 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1317 WREG32(VGT_STRMOUT_EN, 0);
1319 WREG32(PA_SC_MODE_CNTL, 0);
1320 WREG32(PA_SC_AA_CONFIG, 0);
1321 WREG32(PA_SC_LINE_STIPPLE, 0);
1322 WREG32(SPI_INPUT_Z, 0);
1323 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1324 WREG32(CB_COLOR7_FRAG, 0);
1326 /* Clear render buffer base addresses */
1327 WREG32(CB_COLOR0_BASE, 0);
1328 WREG32(CB_COLOR1_BASE, 0);
1329 WREG32(CB_COLOR2_BASE, 0);
1330 WREG32(CB_COLOR3_BASE, 0);
1331 WREG32(CB_COLOR4_BASE, 0);
1332 WREG32(CB_COLOR5_BASE, 0);
1333 WREG32(CB_COLOR6_BASE, 0);
1334 WREG32(CB_COLOR7_BASE, 0);
1335 WREG32(CB_COLOR7_FRAG, 0);
1337 switch (rdev->family) {
1342 tmp = TC_L2_SIZE(8);
1346 tmp = TC_L2_SIZE(4);
1349 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1352 tmp = TC_L2_SIZE(0);
1355 WREG32(TC_CNTL, tmp);
1357 tmp = RREG32(HDP_HOST_PATH_CNTL);
1358 WREG32(HDP_HOST_PATH_CNTL, tmp);
1360 tmp = RREG32(ARB_POP);
1361 tmp |= ENABLE_TC128;
1362 WREG32(ARB_POP, tmp);
1364 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1365 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1367 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1372 * Indirect registers accessor
1374 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1378 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1379 (void)RREG32(PCIE_PORT_INDEX);
1380 r = RREG32(PCIE_PORT_DATA);
1384 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1386 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1387 (void)RREG32(PCIE_PORT_INDEX);
1388 WREG32(PCIE_PORT_DATA, (v));
1389 (void)RREG32(PCIE_PORT_DATA);
1395 void r600_cp_stop(struct radeon_device *rdev)
1397 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1400 int r600_init_microcode(struct radeon_device *rdev)
1402 struct platform_device *pdev;
1403 const char *chip_name;
1404 const char *rlc_chip_name;
1405 size_t pfp_req_size, me_req_size, rlc_req_size;
1411 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1414 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1418 switch (rdev->family) {
1421 rlc_chip_name = "R600";
1424 chip_name = "RV610";
1425 rlc_chip_name = "R600";
1428 chip_name = "RV630";
1429 rlc_chip_name = "R600";
1432 chip_name = "RV620";
1433 rlc_chip_name = "R600";
1436 chip_name = "RV635";
1437 rlc_chip_name = "R600";
1440 chip_name = "RV670";
1441 rlc_chip_name = "R600";
1445 chip_name = "RS780";
1446 rlc_chip_name = "R600";
1449 chip_name = "RV770";
1450 rlc_chip_name = "R700";
1454 chip_name = "RV730";
1455 rlc_chip_name = "R700";
1458 chip_name = "RV710";
1459 rlc_chip_name = "R700";
1464 if (rdev->family >= CHIP_RV770) {
1465 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
1466 me_req_size = R700_PM4_UCODE_SIZE * 4;
1467 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
1469 pfp_req_size = PFP_UCODE_SIZE * 4;
1470 me_req_size = PM4_UCODE_SIZE * 12;
1471 rlc_req_size = RLC_UCODE_SIZE * 4;
1474 DRM_INFO("Loading %s Microcode\n", chip_name);
1476 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
1477 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
1480 if (rdev->pfp_fw->size != pfp_req_size) {
1482 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1483 rdev->pfp_fw->size, fw_name);
1488 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
1489 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
1492 if (rdev->me_fw->size != me_req_size) {
1494 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1495 rdev->me_fw->size, fw_name);
1499 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
1500 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
1503 if (rdev->rlc_fw->size != rlc_req_size) {
1505 "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
1506 rdev->rlc_fw->size, fw_name);
1511 platform_device_unregister(pdev);
1516 "r600_cp: Failed to load firmware \"%s\"\n",
1518 release_firmware(rdev->pfp_fw);
1519 rdev->pfp_fw = NULL;
1520 release_firmware(rdev->me_fw);
1522 release_firmware(rdev->rlc_fw);
1523 rdev->rlc_fw = NULL;
1528 static int r600_cp_load_microcode(struct radeon_device *rdev)
1530 const __be32 *fw_data;
1533 if (!rdev->me_fw || !rdev->pfp_fw)
1538 WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1541 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1542 RREG32(GRBM_SOFT_RESET);
1544 WREG32(GRBM_SOFT_RESET, 0);
1546 WREG32(CP_ME_RAM_WADDR, 0);
1548 fw_data = (const __be32 *)rdev->me_fw->data;
1549 WREG32(CP_ME_RAM_WADDR, 0);
1550 for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
1551 WREG32(CP_ME_RAM_DATA,
1552 be32_to_cpup(fw_data++));
1554 fw_data = (const __be32 *)rdev->pfp_fw->data;
1555 WREG32(CP_PFP_UCODE_ADDR, 0);
1556 for (i = 0; i < PFP_UCODE_SIZE; i++)
1557 WREG32(CP_PFP_UCODE_DATA,
1558 be32_to_cpup(fw_data++));
1560 WREG32(CP_PFP_UCODE_ADDR, 0);
1561 WREG32(CP_ME_RAM_WADDR, 0);
1562 WREG32(CP_ME_RAM_RADDR, 0);
1566 int r600_cp_start(struct radeon_device *rdev)
1571 r = radeon_ring_lock(rdev, 7);
1573 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1576 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1577 radeon_ring_write(rdev, 0x1);
1578 if (rdev->family < CHIP_RV770) {
1579 radeon_ring_write(rdev, 0x3);
1580 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
1582 radeon_ring_write(rdev, 0x0);
1583 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
1585 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1586 radeon_ring_write(rdev, 0);
1587 radeon_ring_write(rdev, 0);
1588 radeon_ring_unlock_commit(rdev);
1591 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
1595 int r600_cp_resume(struct radeon_device *rdev)
1602 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1603 RREG32(GRBM_SOFT_RESET);
1605 WREG32(GRBM_SOFT_RESET, 0);
1607 /* Set ring buffer size */
1608 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1609 tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1611 tmp |= BUF_SWAP_32BIT;
1613 WREG32(CP_RB_CNTL, tmp);
1614 WREG32(CP_SEM_WAIT_TIMER, 0x4);
1616 /* Set the write pointer delay */
1617 WREG32(CP_RB_WPTR_DELAY, 0);
1619 /* Initialize the ring buffer's read and write pointers */
1620 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1621 WREG32(CP_RB_RPTR_WR, 0);
1622 WREG32(CP_RB_WPTR, 0);
1623 WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
1624 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
1626 WREG32(CP_RB_CNTL, tmp);
1628 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1629 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1631 rdev->cp.rptr = RREG32(CP_RB_RPTR);
1632 rdev->cp.wptr = RREG32(CP_RB_WPTR);
1634 r600_cp_start(rdev);
1635 rdev->cp.ready = true;
1636 r = radeon_ring_test(rdev);
1638 rdev->cp.ready = false;
1644 void r600_cp_commit(struct radeon_device *rdev)
1646 WREG32(CP_RB_WPTR, rdev->cp.wptr);
1647 (void)RREG32(CP_RB_WPTR);
1650 void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
1654 /* Align ring size */
1655 rb_bufsz = drm_order(ring_size / 8);
1656 ring_size = (1 << (rb_bufsz + 1)) * 4;
1657 rdev->cp.ring_size = ring_size;
1658 rdev->cp.align_mask = 16 - 1;
1663 * GPU scratch registers helpers function.
1665 void r600_scratch_init(struct radeon_device *rdev)
1669 rdev->scratch.num_reg = 7;
1670 for (i = 0; i < rdev->scratch.num_reg; i++) {
1671 rdev->scratch.free[i] = true;
1672 rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4);
1676 int r600_ring_test(struct radeon_device *rdev)
1683 r = radeon_scratch_get(rdev, &scratch);
1685 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
1688 WREG32(scratch, 0xCAFEDEAD);
1689 r = radeon_ring_lock(rdev, 3);
1691 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1692 radeon_scratch_free(rdev, scratch);
1695 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1696 radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1697 radeon_ring_write(rdev, 0xDEADBEEF);
1698 radeon_ring_unlock_commit(rdev);
1699 for (i = 0; i < rdev->usec_timeout; i++) {
1700 tmp = RREG32(scratch);
1701 if (tmp == 0xDEADBEEF)
1705 if (i < rdev->usec_timeout) {
1706 DRM_INFO("ring test succeeded in %d usecs\n", i);
1708 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
1712 radeon_scratch_free(rdev, scratch);
1716 void r600_wb_disable(struct radeon_device *rdev)
1720 WREG32(SCRATCH_UMSK, 0);
1721 if (rdev->wb.wb_obj) {
1722 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
1723 if (unlikely(r != 0))
1725 radeon_bo_kunmap(rdev->wb.wb_obj);
1726 radeon_bo_unpin(rdev->wb.wb_obj);
1727 radeon_bo_unreserve(rdev->wb.wb_obj);
1731 void r600_wb_fini(struct radeon_device *rdev)
1733 r600_wb_disable(rdev);
1734 if (rdev->wb.wb_obj) {
1735 radeon_bo_unref(&rdev->wb.wb_obj);
1737 rdev->wb.wb_obj = NULL;
1741 int r600_wb_enable(struct radeon_device *rdev)
1745 if (rdev->wb.wb_obj == NULL) {
1746 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
1747 RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj);
1749 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
1752 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
1753 if (unlikely(r != 0)) {
1757 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
1758 &rdev->wb.gpu_addr);
1760 radeon_bo_unreserve(rdev->wb.wb_obj);
1761 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
1765 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
1766 radeon_bo_unreserve(rdev->wb.wb_obj);
1768 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
1773 WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF);
1774 WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC);
1775 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF);
1776 WREG32(SCRATCH_UMSK, 0xff);
1780 void r600_fence_ring_emit(struct radeon_device *rdev,
1781 struct radeon_fence *fence)
1783 /* Also consider EVENT_WRITE_EOP. it handles the interrupts + timestamps + events */
1784 /* Emit fence sequence & fire IRQ */
1785 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1786 radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1787 radeon_ring_write(rdev, fence->seq);
1788 radeon_ring_write(rdev, PACKET0(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0));
1789 radeon_ring_write(rdev, 1);
1790 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
1791 radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
1792 radeon_ring_write(rdev, RB_INT_STAT);
1795 int r600_copy_dma(struct radeon_device *rdev,
1796 uint64_t src_offset,
1797 uint64_t dst_offset,
1799 struct radeon_fence *fence)
1801 /* FIXME: implement */
1805 int r600_copy_blit(struct radeon_device *rdev,
1806 uint64_t src_offset, uint64_t dst_offset,
1807 unsigned num_pages, struct radeon_fence *fence)
1809 r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
1810 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
1811 r600_blit_done_copy(rdev, fence);
1815 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
1816 uint32_t tiling_flags, uint32_t pitch,
1817 uint32_t offset, uint32_t obj_size)
1819 /* FIXME: implement */
1823 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
1825 /* FIXME: implement */
1829 bool r600_card_posted(struct radeon_device *rdev)
1833 /* first check CRTCs */
1834 reg = RREG32(D1CRTC_CONTROL) |
1835 RREG32(D2CRTC_CONTROL);
1839 /* then check MEM_SIZE, in case the crtcs are off */
1840 if (RREG32(CONFIG_MEMSIZE))
1846 int r600_startup(struct radeon_device *rdev)
1850 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1851 r = r600_init_microcode(rdev);
1853 DRM_ERROR("Failed to load firmware!\n");
1858 r600_mc_program(rdev);
1859 if (rdev->flags & RADEON_IS_AGP) {
1860 r600_agp_enable(rdev);
1862 r = r600_pcie_gart_enable(rdev);
1866 r600_gpu_init(rdev);
1868 if (!rdev->r600_blit.shader_obj) {
1869 r = r600_blit_init(rdev);
1871 DRM_ERROR("radeon: failed blitter (%d).\n", r);
1876 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1877 if (unlikely(r != 0))
1879 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
1880 &rdev->r600_blit.shader_gpu_addr);
1881 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1883 dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
1888 r = r600_irq_init(rdev);
1890 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1891 radeon_irq_kms_fini(rdev);
1896 r = radeon_ring_init(rdev, rdev->cp.ring_size);
1899 r = r600_cp_load_microcode(rdev);
1902 r = r600_cp_resume(rdev);
1905 /* write back buffer are not vital so don't worry about failure */
1906 r600_wb_enable(rdev);
1910 void r600_vga_set_state(struct radeon_device *rdev, bool state)
1914 temp = RREG32(CONFIG_CNTL);
1915 if (state == false) {
1921 WREG32(CONFIG_CNTL, temp);
1924 int r600_resume(struct radeon_device *rdev)
1928 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
1929 * posting will perform necessary task to bring back GPU into good
1933 atom_asic_init(rdev->mode_info.atom_context);
1934 /* Initialize clocks */
1935 r = radeon_clocks_init(rdev);
1940 r = r600_startup(rdev);
1942 DRM_ERROR("r600 startup failed on resume\n");
1946 r = r600_ib_test(rdev);
1948 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1954 int r600_suspend(struct radeon_device *rdev)
1958 /* FIXME: we should wait for ring to be empty */
1960 rdev->cp.ready = false;
1961 r600_wb_disable(rdev);
1962 r600_pcie_gart_disable(rdev);
1963 /* unpin shaders bo */
1964 if (rdev->r600_blit.shader_obj) {
1965 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1967 radeon_bo_unpin(rdev->r600_blit.shader_obj);
1968 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1974 /* Plan is to move initialization in that function and use
1975 * helper function so that radeon_device_init pretty much
1976 * do nothing more than calling asic specific function. This
1977 * should also allow to remove a bunch of callback function
1980 int r600_init(struct radeon_device *rdev)
1984 r = radeon_dummy_page_init(rdev);
1987 if (r600_debugfs_mc_info_init(rdev)) {
1988 DRM_ERROR("Failed to register debugfs file for mc !\n");
1990 /* This don't do much */
1991 r = radeon_gem_init(rdev);
1995 if (!radeon_get_bios(rdev)) {
1996 if (ASIC_IS_AVIVO(rdev))
1999 /* Must be an ATOMBIOS */
2000 if (!rdev->is_atom_bios) {
2001 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2004 r = radeon_atombios_init(rdev);
2007 /* Post card if necessary */
2008 if (!r600_card_posted(rdev)) {
2010 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2013 DRM_INFO("GPU not posted. posting now...\n");
2014 atom_asic_init(rdev->mode_info.atom_context);
2016 /* Initialize scratch registers */
2017 r600_scratch_init(rdev);
2018 /* Initialize surface registers */
2019 radeon_surface_init(rdev);
2020 /* Initialize clocks */
2021 radeon_get_clock_info(rdev->ddev);
2022 r = radeon_clocks_init(rdev);
2025 /* Initialize power management */
2026 radeon_pm_init(rdev);
2028 r = radeon_fence_driver_init(rdev);
2031 r = r600_mc_init(rdev);
2034 /* Memory manager */
2035 r = radeon_bo_init(rdev);
2039 r = radeon_irq_kms_init(rdev);
2043 rdev->cp.ring_obj = NULL;
2044 r600_ring_init(rdev, 1024 * 1024);
2046 rdev->ih.ring_obj = NULL;
2047 r600_ih_ring_init(rdev, 64 * 1024);
2049 r = r600_pcie_gart_init(rdev);
2053 rdev->accel_working = true;
2054 r = r600_startup(rdev);
2058 radeon_ring_fini(rdev);
2059 r600_pcie_gart_fini(rdev);
2060 rdev->accel_working = false;
2062 if (rdev->accel_working) {
2063 r = radeon_ib_pool_init(rdev);
2065 DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r);
2066 rdev->accel_working = false;
2068 r = r600_ib_test(rdev);
2070 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
2071 rdev->accel_working = false;
2075 r = r600_audio_init(rdev);
2077 return r; /* TODO error handling */
2081 void r600_fini(struct radeon_device *rdev)
2083 /* Suspend operations */
2086 r600_audio_fini(rdev);
2087 r600_blit_fini(rdev);
2088 r600_irq_fini(rdev);
2089 radeon_irq_kms_fini(rdev);
2090 radeon_ring_fini(rdev);
2092 r600_pcie_gart_fini(rdev);
2093 radeon_gem_fini(rdev);
2094 radeon_fence_driver_fini(rdev);
2095 radeon_clocks_fini(rdev);
2096 radeon_agp_fini(rdev);
2097 radeon_bo_fini(rdev);
2098 radeon_atombios_fini(rdev);
2101 radeon_dummy_page_fini(rdev);
2108 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2110 /* FIXME: implement */
2111 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2112 radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
2113 radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
2114 radeon_ring_write(rdev, ib->length_dw);
2117 int r600_ib_test(struct radeon_device *rdev)
2119 struct radeon_ib *ib;
2125 r = radeon_scratch_get(rdev, &scratch);
2127 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2130 WREG32(scratch, 0xCAFEDEAD);
2131 r = radeon_ib_get(rdev, &ib);
2133 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2136 ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2137 ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2138 ib->ptr[2] = 0xDEADBEEF;
2139 ib->ptr[3] = PACKET2(0);
2140 ib->ptr[4] = PACKET2(0);
2141 ib->ptr[5] = PACKET2(0);
2142 ib->ptr[6] = PACKET2(0);
2143 ib->ptr[7] = PACKET2(0);
2144 ib->ptr[8] = PACKET2(0);
2145 ib->ptr[9] = PACKET2(0);
2146 ib->ptr[10] = PACKET2(0);
2147 ib->ptr[11] = PACKET2(0);
2148 ib->ptr[12] = PACKET2(0);
2149 ib->ptr[13] = PACKET2(0);
2150 ib->ptr[14] = PACKET2(0);
2151 ib->ptr[15] = PACKET2(0);
2153 r = radeon_ib_schedule(rdev, ib);
2155 radeon_scratch_free(rdev, scratch);
2156 radeon_ib_free(rdev, &ib);
2157 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2160 r = radeon_fence_wait(ib->fence, false);
2162 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2165 for (i = 0; i < rdev->usec_timeout; i++) {
2166 tmp = RREG32(scratch);
2167 if (tmp == 0xDEADBEEF)
2171 if (i < rdev->usec_timeout) {
2172 DRM_INFO("ib test succeeded in %u usecs\n", i);
2174 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
2178 radeon_scratch_free(rdev, scratch);
2179 radeon_ib_free(rdev, &ib);
2186 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
2187 * the same as the CP ring buffer, but in reverse. Rather than the CPU
2188 * writing to the ring and the GPU consuming, the GPU writes to the ring
2189 * and host consumes. As the host irq handler processes interrupts, it
2190 * increments the rptr. When the rptr catches up with the wptr, all the
2191 * current interrupts have been processed.
2194 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2198 /* Align ring size */
2199 rb_bufsz = drm_order(ring_size / 4);
2200 ring_size = (1 << rb_bufsz) * 4;
2201 rdev->ih.ring_size = ring_size;
2202 rdev->ih.align_mask = 4 - 1;
2205 static int r600_ih_ring_alloc(struct radeon_device *rdev, unsigned ring_size)
2209 rdev->ih.ring_size = ring_size;
2210 /* Allocate ring buffer */
2211 if (rdev->ih.ring_obj == NULL) {
2212 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size,
2214 RADEON_GEM_DOMAIN_GTT,
2215 &rdev->ih.ring_obj);
2217 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2220 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2221 if (unlikely(r != 0))
2223 r = radeon_bo_pin(rdev->ih.ring_obj,
2224 RADEON_GEM_DOMAIN_GTT,
2225 &rdev->ih.gpu_addr);
2227 radeon_bo_unreserve(rdev->ih.ring_obj);
2228 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2231 r = radeon_bo_kmap(rdev->ih.ring_obj,
2232 (void **)&rdev->ih.ring);
2233 radeon_bo_unreserve(rdev->ih.ring_obj);
2235 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2239 rdev->ih.ptr_mask = (rdev->cp.ring_size / 4) - 1;
2245 static void r600_ih_ring_fini(struct radeon_device *rdev)
2248 if (rdev->ih.ring_obj) {
2249 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2250 if (likely(r == 0)) {
2251 radeon_bo_kunmap(rdev->ih.ring_obj);
2252 radeon_bo_unpin(rdev->ih.ring_obj);
2253 radeon_bo_unreserve(rdev->ih.ring_obj);
2255 radeon_bo_unref(&rdev->ih.ring_obj);
2256 rdev->ih.ring = NULL;
2257 rdev->ih.ring_obj = NULL;
2261 static void r600_rlc_stop(struct radeon_device *rdev)
2264 if (rdev->family >= CHIP_RV770) {
2265 /* r7xx asics need to soft reset RLC before halting */
2266 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2267 RREG32(SRBM_SOFT_RESET);
2269 WREG32(SRBM_SOFT_RESET, 0);
2270 RREG32(SRBM_SOFT_RESET);
2273 WREG32(RLC_CNTL, 0);
2276 static void r600_rlc_start(struct radeon_device *rdev)
2278 WREG32(RLC_CNTL, RLC_ENABLE);
2281 static int r600_rlc_init(struct radeon_device *rdev)
2284 const __be32 *fw_data;
2289 r600_rlc_stop(rdev);
2291 WREG32(RLC_HB_BASE, 0);
2292 WREG32(RLC_HB_CNTL, 0);
2293 WREG32(RLC_HB_RPTR, 0);
2294 WREG32(RLC_HB_WPTR, 0);
2295 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2296 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2297 WREG32(RLC_MC_CNTL, 0);
2298 WREG32(RLC_UCODE_CNTL, 0);
2300 fw_data = (const __be32 *)rdev->rlc_fw->data;
2301 if (rdev->family >= CHIP_RV770) {
2302 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2303 WREG32(RLC_UCODE_ADDR, i);
2304 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2307 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2308 WREG32(RLC_UCODE_ADDR, i);
2309 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2312 WREG32(RLC_UCODE_ADDR, 0);
2314 r600_rlc_start(rdev);
2319 static void r600_enable_interrupts(struct radeon_device *rdev)
2321 u32 ih_cntl = RREG32(IH_CNTL);
2322 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2324 ih_cntl |= ENABLE_INTR;
2325 ih_rb_cntl |= IH_RB_ENABLE;
2326 WREG32(IH_CNTL, ih_cntl);
2327 WREG32(IH_RB_CNTL, ih_rb_cntl);
2328 rdev->ih.enabled = true;
2331 static void r600_disable_interrupts(struct radeon_device *rdev)
2333 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2334 u32 ih_cntl = RREG32(IH_CNTL);
2336 ih_rb_cntl &= ~IH_RB_ENABLE;
2337 ih_cntl &= ~ENABLE_INTR;
2338 WREG32(IH_RB_CNTL, ih_rb_cntl);
2339 WREG32(IH_CNTL, ih_cntl);
2340 /* set rptr, wptr to 0 */
2341 WREG32(IH_RB_RPTR, 0);
2342 WREG32(IH_RB_WPTR, 0);
2343 rdev->ih.enabled = false;
2348 static void r600_disable_interrupt_state(struct radeon_device *rdev)
2352 WREG32(CP_INT_CNTL, 0);
2353 WREG32(GRBM_INT_CNTL, 0);
2354 WREG32(DxMODE_INT_MASK, 0);
2355 if (ASIC_IS_DCE3(rdev)) {
2356 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2357 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2358 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2359 WREG32(DC_HPD1_INT_CONTROL, tmp);
2360 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2361 WREG32(DC_HPD2_INT_CONTROL, tmp);
2362 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2363 WREG32(DC_HPD3_INT_CONTROL, tmp);
2364 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2365 WREG32(DC_HPD4_INT_CONTROL, tmp);
2366 if (ASIC_IS_DCE32(rdev)) {
2367 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2368 WREG32(DC_HPD5_INT_CONTROL, 0);
2369 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2370 WREG32(DC_HPD6_INT_CONTROL, 0);
2373 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2374 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2375 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2376 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, 0);
2377 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2378 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, 0);
2379 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2380 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, 0);
2384 int r600_irq_init(struct radeon_device *rdev)
2388 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2391 ret = r600_ih_ring_alloc(rdev, rdev->ih.ring_size);
2396 r600_disable_interrupts(rdev);
2399 ret = r600_rlc_init(rdev);
2401 r600_ih_ring_fini(rdev);
2405 /* setup interrupt control */
2406 /* set dummy read address to ring address */
2407 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2408 interrupt_cntl = RREG32(INTERRUPT_CNTL);
2409 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2410 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2412 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
2413 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2414 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
2415 WREG32(INTERRUPT_CNTL, interrupt_cntl);
2417 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
2418 rb_bufsz = drm_order(rdev->ih.ring_size / 4);
2420 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
2421 IH_WPTR_OVERFLOW_CLEAR |
2423 /* WPTR writeback, not yet */
2424 /*ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;*/
2425 WREG32(IH_RB_WPTR_ADDR_LO, 0);
2426 WREG32(IH_RB_WPTR_ADDR_HI, 0);
2428 WREG32(IH_RB_CNTL, ih_rb_cntl);
2430 /* set rptr, wptr to 0 */
2431 WREG32(IH_RB_RPTR, 0);
2432 WREG32(IH_RB_WPTR, 0);
2434 /* Default settings for IH_CNTL (disabled at first) */
2435 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2436 /* RPTR_REARM only works if msi's are enabled */
2437 if (rdev->msi_enabled)
2438 ih_cntl |= RPTR_REARM;
2441 ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT);
2443 WREG32(IH_CNTL, ih_cntl);
2445 /* force the active interrupt state to all disabled */
2446 r600_disable_interrupt_state(rdev);
2449 r600_enable_interrupts(rdev);
2454 void r600_irq_fini(struct radeon_device *rdev)
2456 r600_disable_interrupts(rdev);
2457 r600_rlc_stop(rdev);
2458 r600_ih_ring_fini(rdev);
2461 int r600_irq_set(struct radeon_device *rdev)
2463 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2465 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
2467 if (!rdev->irq.installed) {
2468 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
2471 /* don't enable anything if the ih is disabled */
2472 if (!rdev->ih.enabled)
2475 if (ASIC_IS_DCE3(rdev)) {
2476 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2477 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2478 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2479 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2480 if (ASIC_IS_DCE32(rdev)) {
2481 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2482 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2485 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2486 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2487 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2490 if (rdev->irq.sw_int) {
2491 DRM_DEBUG("r600_irq_set: sw int\n");
2492 cp_int_cntl |= RB_INT_ENABLE;
2494 if (rdev->irq.crtc_vblank_int[0]) {
2495 DRM_DEBUG("r600_irq_set: vblank 0\n");
2496 mode_int |= D1MODE_VBLANK_INT_MASK;
2498 if (rdev->irq.crtc_vblank_int[1]) {
2499 DRM_DEBUG("r600_irq_set: vblank 1\n");
2500 mode_int |= D2MODE_VBLANK_INT_MASK;
2502 if (rdev->irq.hpd[0]) {
2503 DRM_DEBUG("r600_irq_set: hpd 1\n");
2504 hpd1 |= DC_HPDx_INT_EN;
2506 if (rdev->irq.hpd[1]) {
2507 DRM_DEBUG("r600_irq_set: hpd 2\n");
2508 hpd2 |= DC_HPDx_INT_EN;
2510 if (rdev->irq.hpd[2]) {
2511 DRM_DEBUG("r600_irq_set: hpd 3\n");
2512 hpd3 |= DC_HPDx_INT_EN;
2514 if (rdev->irq.hpd[3]) {
2515 DRM_DEBUG("r600_irq_set: hpd 4\n");
2516 hpd4 |= DC_HPDx_INT_EN;
2518 if (rdev->irq.hpd[4]) {
2519 DRM_DEBUG("r600_irq_set: hpd 5\n");
2520 hpd5 |= DC_HPDx_INT_EN;
2522 if (rdev->irq.hpd[5]) {
2523 DRM_DEBUG("r600_irq_set: hpd 6\n");
2524 hpd6 |= DC_HPDx_INT_EN;
2527 WREG32(CP_INT_CNTL, cp_int_cntl);
2528 WREG32(DxMODE_INT_MASK, mode_int);
2529 if (ASIC_IS_DCE3(rdev)) {
2530 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2531 WREG32(DC_HPD2_INT_CONTROL, hpd2);
2532 WREG32(DC_HPD3_INT_CONTROL, hpd3);
2533 WREG32(DC_HPD4_INT_CONTROL, hpd4);
2534 if (ASIC_IS_DCE32(rdev)) {
2535 WREG32(DC_HPD5_INT_CONTROL, hpd5);
2536 WREG32(DC_HPD6_INT_CONTROL, hpd6);
2539 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
2540 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
2541 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
2547 static inline void r600_irq_ack(struct radeon_device *rdev,
2550 u32 *disp_int_cont2)
2554 if (ASIC_IS_DCE3(rdev)) {
2555 *disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
2556 *disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
2557 *disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
2559 *disp_int = RREG32(DISP_INTERRUPT_STATUS);
2560 *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2561 *disp_int_cont2 = 0;
2564 if (*disp_int & LB_D1_VBLANK_INTERRUPT)
2565 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
2566 if (*disp_int & LB_D1_VLINE_INTERRUPT)
2567 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
2568 if (*disp_int & LB_D2_VBLANK_INTERRUPT)
2569 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
2570 if (*disp_int & LB_D2_VLINE_INTERRUPT)
2571 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
2572 if (*disp_int & DC_HPD1_INTERRUPT) {
2573 if (ASIC_IS_DCE3(rdev)) {
2574 tmp = RREG32(DC_HPD1_INT_CONTROL);
2575 tmp |= DC_HPDx_INT_ACK;
2576 WREG32(DC_HPD1_INT_CONTROL, tmp);
2578 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
2579 tmp |= DC_HPDx_INT_ACK;
2580 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
2583 if (*disp_int & DC_HPD2_INTERRUPT) {
2584 if (ASIC_IS_DCE3(rdev)) {
2585 tmp = RREG32(DC_HPD2_INT_CONTROL);
2586 tmp |= DC_HPDx_INT_ACK;
2587 WREG32(DC_HPD2_INT_CONTROL, tmp);
2589 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
2590 tmp |= DC_HPDx_INT_ACK;
2591 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
2594 if (*disp_int_cont & DC_HPD3_INTERRUPT) {
2595 if (ASIC_IS_DCE3(rdev)) {
2596 tmp = RREG32(DC_HPD3_INT_CONTROL);
2597 tmp |= DC_HPDx_INT_ACK;
2598 WREG32(DC_HPD3_INT_CONTROL, tmp);
2600 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
2601 tmp |= DC_HPDx_INT_ACK;
2602 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
2605 if (*disp_int_cont & DC_HPD4_INTERRUPT) {
2606 tmp = RREG32(DC_HPD4_INT_CONTROL);
2607 tmp |= DC_HPDx_INT_ACK;
2608 WREG32(DC_HPD4_INT_CONTROL, tmp);
2610 if (ASIC_IS_DCE32(rdev)) {
2611 if (*disp_int_cont2 & DC_HPD5_INTERRUPT) {
2612 tmp = RREG32(DC_HPD5_INT_CONTROL);
2613 tmp |= DC_HPDx_INT_ACK;
2614 WREG32(DC_HPD5_INT_CONTROL, tmp);
2616 if (*disp_int_cont2 & DC_HPD6_INTERRUPT) {
2617 tmp = RREG32(DC_HPD5_INT_CONTROL);
2618 tmp |= DC_HPDx_INT_ACK;
2619 WREG32(DC_HPD6_INT_CONTROL, tmp);
2624 void r600_irq_disable(struct radeon_device *rdev)
2626 u32 disp_int, disp_int_cont, disp_int_cont2;
2628 r600_disable_interrupts(rdev);
2629 /* Wait and acknowledge irq */
2631 r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
2632 r600_disable_interrupt_state(rdev);
2635 static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
2639 /* XXX use writeback */
2640 wptr = RREG32(IH_RB_WPTR);
2642 if (wptr & RB_OVERFLOW) {
2644 /* XXX deal with overflow */
2645 DRM_ERROR("IH RB overflow\n");
2646 tmp = RREG32(IH_RB_CNTL);
2647 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2648 WREG32(IH_RB_CNTL, tmp);
2650 wptr = wptr & WPTR_OFFSET_MASK;
2656 * Each IV ring entry is 128 bits:
2657 * [7:0] - interrupt source id
2659 * [59:32] - interrupt source data
2660 * [127:60] - reserved
2662 * The basic interrupt vector entries
2663 * are decoded as follows:
2664 * src_id src_data description
2669 * 19 0 FP Hot plug detection A
2670 * 19 1 FP Hot plug detection B
2671 * 19 2 DAC A auto-detection
2672 * 19 3 DAC B auto-detection
2676 * 181 - EOP Interrupt
2679 * Note, these are based on r600 and may need to be
2680 * adjusted or added to on newer asics
2683 int r600_irq_process(struct radeon_device *rdev)
2685 u32 wptr = r600_get_ih_wptr(rdev);
2686 u32 rptr = rdev->ih.rptr;
2687 u32 src_id, src_data;
2688 u32 last_entry = rdev->ih.ring_size - 16;
2689 u32 ring_index, disp_int, disp_int_cont, disp_int_cont2;
2690 unsigned long flags;
2691 bool queue_hotplug = false;
2693 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2695 spin_lock_irqsave(&rdev->ih.lock, flags);
2698 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2701 if (rdev->shutdown) {
2702 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2707 /* display interrupts */
2708 r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
2710 rdev->ih.wptr = wptr;
2711 while (rptr != wptr) {
2712 /* wptr/rptr are in bytes! */
2713 ring_index = rptr / 4;
2714 src_id = rdev->ih.ring[ring_index] & 0xff;
2715 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
2718 case 1: /* D1 vblank/vline */
2720 case 0: /* D1 vblank */
2721 if (disp_int & LB_D1_VBLANK_INTERRUPT) {
2722 drm_handle_vblank(rdev->ddev, 0);
2723 disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2724 DRM_DEBUG("IH: D1 vblank\n");
2727 case 1: /* D1 vline */
2728 if (disp_int & LB_D1_VLINE_INTERRUPT) {
2729 disp_int &= ~LB_D1_VLINE_INTERRUPT;
2730 DRM_DEBUG("IH: D1 vline\n");
2734 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2738 case 5: /* D2 vblank/vline */
2740 case 0: /* D2 vblank */
2741 if (disp_int & LB_D2_VBLANK_INTERRUPT) {
2742 drm_handle_vblank(rdev->ddev, 1);
2743 disp_int &= ~LB_D2_VBLANK_INTERRUPT;
2744 DRM_DEBUG("IH: D2 vblank\n");
2747 case 1: /* D1 vline */
2748 if (disp_int & LB_D2_VLINE_INTERRUPT) {
2749 disp_int &= ~LB_D2_VLINE_INTERRUPT;
2750 DRM_DEBUG("IH: D2 vline\n");
2754 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2758 case 19: /* HPD/DAC hotplug */
2761 if (disp_int & DC_HPD1_INTERRUPT) {
2762 disp_int &= ~DC_HPD1_INTERRUPT;
2763 queue_hotplug = true;
2764 DRM_DEBUG("IH: HPD1\n");
2768 if (disp_int & DC_HPD2_INTERRUPT) {
2769 disp_int &= ~DC_HPD2_INTERRUPT;
2770 queue_hotplug = true;
2771 DRM_DEBUG("IH: HPD2\n");
2775 if (disp_int_cont & DC_HPD3_INTERRUPT) {
2776 disp_int_cont &= ~DC_HPD3_INTERRUPT;
2777 queue_hotplug = true;
2778 DRM_DEBUG("IH: HPD3\n");
2782 if (disp_int_cont & DC_HPD4_INTERRUPT) {
2783 disp_int_cont &= ~DC_HPD4_INTERRUPT;
2784 queue_hotplug = true;
2785 DRM_DEBUG("IH: HPD4\n");
2789 if (disp_int_cont2 & DC_HPD5_INTERRUPT) {
2790 disp_int_cont &= ~DC_HPD5_INTERRUPT;
2791 queue_hotplug = true;
2792 DRM_DEBUG("IH: HPD5\n");
2796 if (disp_int_cont2 & DC_HPD6_INTERRUPT) {
2797 disp_int_cont &= ~DC_HPD6_INTERRUPT;
2798 queue_hotplug = true;
2799 DRM_DEBUG("IH: HPD6\n");
2803 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2807 case 176: /* CP_INT in ring buffer */
2808 case 177: /* CP_INT in IB1 */
2809 case 178: /* CP_INT in IB2 */
2810 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
2811 radeon_fence_process(rdev);
2813 case 181: /* CP EOP event */
2814 DRM_DEBUG("IH: CP EOP\n");
2817 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2821 /* wptr/rptr are in bytes! */
2822 if (rptr == last_entry)
2827 /* make sure wptr hasn't changed while processing */
2828 wptr = r600_get_ih_wptr(rdev);
2829 if (wptr != rdev->ih.wptr)
2832 queue_work(rdev->wq, &rdev->hotplug_work);
2833 rdev->ih.rptr = rptr;
2834 WREG32(IH_RB_RPTR, rdev->ih.rptr);
2835 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2842 #if defined(CONFIG_DEBUG_FS)
2844 static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
2846 struct drm_info_node *node = (struct drm_info_node *) m->private;
2847 struct drm_device *dev = node->minor->dev;
2848 struct radeon_device *rdev = dev->dev_private;
2849 unsigned count, i, j;
2851 radeon_ring_free_size(rdev);
2852 count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
2853 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
2854 seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
2855 seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
2856 seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
2857 seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
2858 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2859 seq_printf(m, "%u dwords in ring\n", count);
2861 for (j = 0; j <= count; j++) {
2862 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2863 i = (i + 1) & rdev->cp.ptr_mask;
2868 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
2870 struct drm_info_node *node = (struct drm_info_node *) m->private;
2871 struct drm_device *dev = node->minor->dev;
2872 struct radeon_device *rdev = dev->dev_private;
2874 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
2875 DREG32_SYS(m, rdev, VM_L2_STATUS);
2879 static struct drm_info_list r600_mc_info_list[] = {
2880 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
2881 {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
2885 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
2887 #if defined(CONFIG_DEBUG_FS)
2888 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));