SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/r600.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/slab.h>
  29 #include <linux/seq_file.h>
  30 #include <linux/firmware.h>
  31 #include <linux/platform_device.h>
  32 #include "drmP.h"
  33 #include "radeon_drm.h"
  34 #include "radeon.h"
  35 #include "radeon_asic.h"
  36 #include "radeon_mode.h"
  37 #include "r600d.h"
  38 #include "atom.h"
  39 #include "avivod.h"
  40
  41 #define PFP_UCODE_SIZE 576
  42 #define PM4_UCODE_SIZE 1792
  43 #define RLC_UCODE_SIZE 768
  44 #define R700_PFP_UCODE_SIZE 848
  45 #define R700_PM4_UCODE_SIZE 1360
  46 #define R700_RLC_UCODE_SIZE 1024
  47 #define EVERGREEN_PFP_UCODE_SIZE 1120
  48 #define EVERGREEN_PM4_UCODE_SIZE 1376
  49 #define EVERGREEN_RLC_UCODE_SIZE 768
  50
  51 /* Firmware Names */
  52 MODULE_FIRMWARE("radeon/R600_pfp.bin");
  53 MODULE_FIRMWARE("radeon/R600_me.bin");
  54 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
  55 MODULE_FIRMWARE("radeon/RV610_me.bin");
  56 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
  57 MODULE_FIRMWARE("radeon/RV630_me.bin");
  58 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
  59 MODULE_FIRMWARE("radeon/RV620_me.bin");
  60 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
  61 MODULE_FIRMWARE("radeon/RV635_me.bin");
  62 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
  63 MODULE_FIRMWARE("radeon/RV670_me.bin");
  64 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
  65 MODULE_FIRMWARE("radeon/RS780_me.bin");
  66 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
  67 MODULE_FIRMWARE("radeon/RV770_me.bin");
  68 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
  69 MODULE_FIRMWARE("radeon/RV730_me.bin");
  70 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
  71 MODULE_FIRMWARE("radeon/RV710_me.bin");
  72 MODULE_FIRMWARE("radeon/R600_rlc.bin");
  73 MODULE_FIRMWARE("radeon/R700_rlc.bin");
  74 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
  75 MODULE_FIRMWARE("radeon/CEDAR_me.bin");
  76 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
  77 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
  78 MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
  79 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
  80 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
  81 MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
  82 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
  83 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
  84 MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
  85 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
  86
  87 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
  88
  89 /* r600,rv610,rv630,rv620,rv635,rv670 */
  90 int r600_mc_wait_for_idle(struct radeon_device *rdev);
  91 void r600_gpu_init(struct radeon_device *rdev);
  92 void r600_fini(struct radeon_device *rdev);
  93 void r600_irq_disable(struct radeon_device *rdev);
  94
  95 void r600_get_power_state(struct radeon_device *rdev,
  96                           enum radeon_pm_action action)
  97 {
  98         int i;
  99
 100         rdev->pm.can_upclock = true;
 101         rdev->pm.can_downclock = true;
 102
 103         /* power state array is low to high, default is first */
 104         if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
 105                 int min_power_state_index = 0;
 106
 107                 if (rdev->pm.num_power_states > 2)
 108                         min_power_state_index = 1;
 109
 110                 switch (action) {
 111                 case PM_ACTION_MINIMUM:
 112                         rdev->pm.requested_power_state_index = min_power_state_index;
 113                         rdev->pm.requested_clock_mode_index = 0;
 114                         rdev->pm.can_downclock = false;
 115                         break;
 116                 case PM_ACTION_DOWNCLOCK:
 117                         if (rdev->pm.current_power_state_index == min_power_state_index) {
 118                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 119                                 rdev->pm.can_downclock = false;
 120                         } else {
 121                                 if (rdev->pm.active_crtc_count > 1) {
 122                                         for (i = 0; i < rdev->pm.num_power_states; i++) {
 123                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)
 124                                                         continue;
 125                                                 else if (i >= rdev->pm.current_power_state_index) {
 126                                                         rdev->pm.requested_power_state_index =
 127                                                                 rdev->pm.current_power_state_index;
 128                                                         break;
 129                                                 } else {
 130                                                         rdev->pm.requested_power_state_index = i;
 131                                                         break;
 132                                                 }
 133                                         }
 134                                 } else
 135                                         rdev->pm.requested_power_state_index =
 136                                                 rdev->pm.current_power_state_index - 1;
 137                         }
 138                         rdev->pm.requested_clock_mode_index = 0;
 139                         break;
 140                 case PM_ACTION_UPCLOCK:
 141                         if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
 142                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 143                                 rdev->pm.can_upclock = false;
 144                         } else {
 145                                 if (rdev->pm.active_crtc_count > 1) {
 146                                         for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
 147                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)
 148                                                         continue;
 149                                                 else if (i <= rdev->pm.current_power_state_index) {
 150                                                         rdev->pm.requested_power_state_index =
 151                                                                 rdev->pm.current_power_state_index;
 152                                                         break;
 153                                                 } else {
 154                                                         rdev->pm.requested_power_state_index = i;
 155                                                         break;
 156                                                 }
 157                                         }
 158                                 } else
 159                                         rdev->pm.requested_power_state_index =
 160                                                 rdev->pm.current_power_state_index + 1;
 161                         }
 162                         rdev->pm.requested_clock_mode_index = 0;
 163                         break;
 164                 case PM_ACTION_DEFAULT:
 165                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 166                         rdev->pm.requested_clock_mode_index = 0;
 167                         rdev->pm.can_upclock = false;
 168                         break;
 169                 case PM_ACTION_NONE:
 170                 default:
 171                         DRM_ERROR("Requested mode for not defined action\n");
 172                         return;
 173                 }
 174         } else {
 175                 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
 176                 /* for now just select the first power state and switch between clock modes */
 177                 /* power state array is low to high, default is first (0) */
 178                 if (rdev->pm.active_crtc_count > 1) {
 179                         rdev->pm.requested_power_state_index = -1;
 180                         /* start at 1 as we don't want the default mode */
 181                         for (i = 1; i < rdev->pm.num_power_states; i++) {
 182                                 if (rdev->pm.power_state[i].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)
 183                                         continue;
 184                                 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
 185                                          (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
 186                                         rdev->pm.requested_power_state_index = i;
 187                                         break;
 188                                 }
 189                         }
 190                         /* if nothing selected, grab the default state. */
 191                         if (rdev->pm.requested_power_state_index == -1)
 192                                 rdev->pm.requested_power_state_index = 0;
 193                 } else
 194                         rdev->pm.requested_power_state_index = 1;
 195
 196                 switch (action) {
 197                 case PM_ACTION_MINIMUM:
 198                         rdev->pm.requested_clock_mode_index = 0;
 199                         rdev->pm.can_downclock = false;
 200                         break;
 201                 case PM_ACTION_DOWNCLOCK:
 202                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 203                                 if (rdev->pm.current_clock_mode_index == 0) {
 204                                         rdev->pm.requested_clock_mode_index = 0;
 205                                         rdev->pm.can_downclock = false;
 206                                 } else
 207                                         rdev->pm.requested_clock_mode_index =
 208                                                 rdev->pm.current_clock_mode_index - 1;
 209                         } else {
 210                                 rdev->pm.requested_clock_mode_index = 0;
 211                                 rdev->pm.can_downclock = false;
 212                         }
 213                         break;
 214                 case PM_ACTION_UPCLOCK:
 215                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 216                                 if (rdev->pm.current_clock_mode_index ==
 217                                     (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
 218                                         rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
 219                                         rdev->pm.can_upclock = false;
 220                                 } else
 221                                         rdev->pm.requested_clock_mode_index =
 222                                                 rdev->pm.current_clock_mode_index + 1;
 223                         } else {
 224                                 rdev->pm.requested_clock_mode_index =
 225                                         rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
 226                                 rdev->pm.can_upclock = false;
 227                         }
 228                         break;
 229                 case PM_ACTION_DEFAULT:
 230                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 231                         rdev->pm.requested_clock_mode_index = 0;
 232                         rdev->pm.can_upclock = false;
 233                         break;
 234                 case PM_ACTION_NONE:
 235                 default:
 236                         DRM_ERROR("Requested mode for not defined action\n");
 237                         return;
 238                 }
 239         }
 240
 241         DRM_INFO("Requested: e: %d m: %d p: %d\n",
 242                  rdev->pm.power_state[rdev->pm.requested_power_state_index].
 243                  clock_info[rdev->pm.requested_clock_mode_index].sclk,
 244                  rdev->pm.power_state[rdev->pm.requested_power_state_index].
 245                  clock_info[rdev->pm.requested_clock_mode_index].mclk,
 246                  rdev->pm.power_state[rdev->pm.requested_power_state_index].
 247                  pcie_lanes);
 248 }
 249
 250 void r600_set_power_state(struct radeon_device *rdev, bool static_switch)
 251 {
 252         u32 sclk, mclk;
 253
 254         if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
 255             (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
 256                 return;
 257
 258         if (radeon_gui_idle(rdev)) {
 259
 260                 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 261                         clock_info[rdev->pm.requested_clock_mode_index].sclk;
 262                 if (sclk > rdev->clock.default_sclk)
 263                         sclk = rdev->clock.default_sclk;
 264
 265                 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 266                         clock_info[rdev->pm.requested_clock_mode_index].mclk;
 267                 if (mclk > rdev->clock.default_mclk)
 268                         mclk = rdev->clock.default_mclk;
 269
 270                 /* voltage, pcie lanes, etc.*/
 271                 radeon_pm_misc(rdev);
 272
 273                 if (static_switch) {
 274
 275                         /* set engine clock */
 276                         if (sclk != rdev->pm.current_sclk) {
 277                                 radeon_set_engine_clock(rdev, sclk);
 278                                 rdev->pm.current_sclk = sclk;
 279                                 DRM_INFO("Setting: e: %d\n", sclk);
 280                         }
 281
 282                         /* set memory clock */
 283                         if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
 284                                 radeon_pm_prepare(rdev);
 285                                 radeon_set_memory_clock(rdev, mclk);
 286                                 radeon_pm_finish(rdev);
 287                                 rdev->pm.current_mclk = mclk;
 288                                 DRM_INFO("Setting: m: %d\n", mclk);
 289                         }
 290
 291                 } else {
 292                         radeon_sync_with_vblank(rdev);
 293
 294                         if (sclk != rdev->pm.current_sclk) {
 295                                 radeon_pm_debug_check_in_vbl(rdev, false);
 296                                 radeon_set_engine_clock(rdev, sclk);
 297                                 radeon_pm_debug_check_in_vbl(rdev, true);
 298                                 rdev->pm.current_sclk = sclk;
 299                                 DRM_INFO("Setting: e: %d\n", sclk);
 300                         }
 301
 302                         /* set memory clock */
 303                         if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
 304                                 radeon_pm_debug_check_in_vbl(rdev, false);
 305                                 radeon_pm_prepare(rdev);
 306                                 radeon_set_memory_clock(rdev, mclk);
 307                                 radeon_pm_finish(rdev);
 308                                 radeon_pm_debug_check_in_vbl(rdev, true);
 309                                 rdev->pm.current_mclk = mclk;
 310                                 DRM_INFO("Setting: m: %d\n", mclk);
 311                         }
 312                 }
 313
 314                 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
 315                 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
 316         } else
 317                 DRM_INFO("GUI not idle!!!\n");
 318 }
 319
 320 void r600_pm_misc(struct radeon_device *rdev)
 321 {
 322
 323 }
 324
 325 bool r600_gui_idle(struct radeon_device *rdev)
 326 {
 327         if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
 328                 return false;
 329         else
 330                 return true;
 331 }
 332
 333 /* hpd for digital panel detect/disconnect */
 334 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 335 {
 336         bool connected = false;
 337
 338         if (ASIC_IS_DCE3(rdev)) {
 339                 switch (hpd) {
 340                 case RADEON_HPD_1:
 341                         if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
 342                                 connected = true;
 343                         break;
 344                 case RADEON_HPD_2:
 345                         if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
 346                                 connected = true;
 347                         break;
 348                 case RADEON_HPD_3:
 349                         if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
 350                                 connected = true;
 351                         break;
 352                 case RADEON_HPD_4:
 353                         if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
 354                                 connected = true;
 355                         break;
 356                         /* DCE 3.2 */
 357                 case RADEON_HPD_5:
 358                         if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 359                                 connected = true;
 360                         break;
 361                 case RADEON_HPD_6:
 362                         if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 363                                 connected = true;
 364                         break;
 365                 default:
 366                         break;
 367                 }
 368         } else {
 369                 switch (hpd) {
 370                 case RADEON_HPD_1:
 371                         if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 372                                 connected = true;
 373                         break;
 374                 case RADEON_HPD_2:
 375                         if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 376                                 connected = true;
 377                         break;
 378                 case RADEON_HPD_3:
 379                         if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 380                                 connected = true;
 381                         break;
 382                 default:
 383                         break;
 384                 }
 385         }
 386         return connected;
 387 }
 388
 389 void r600_hpd_set_polarity(struct radeon_device *rdev,
 390                            enum radeon_hpd_id hpd)
 391 {
 392         u32 tmp;
 393         bool connected = r600_hpd_sense(rdev, hpd);
 394
 395         if (ASIC_IS_DCE3(rdev)) {
 396                 switch (hpd) {
 397                 case RADEON_HPD_1:
 398                         tmp = RREG32(DC_HPD1_INT_CONTROL);
 399                         if (connected)
 400                                 tmp &= ~DC_HPDx_INT_POLARITY;
 401                         else
 402                                 tmp |= DC_HPDx_INT_POLARITY;
 403                         WREG32(DC_HPD1_INT_CONTROL, tmp);
 404                         break;
 405                 case RADEON_HPD_2:
 406                         tmp = RREG32(DC_HPD2_INT_CONTROL);
 407                         if (connected)
 408                                 tmp &= ~DC_HPDx_INT_POLARITY;
 409                         else
 410                                 tmp |= DC_HPDx_INT_POLARITY;
 411                         WREG32(DC_HPD2_INT_CONTROL, tmp);
 412                         break;
 413                 case RADEON_HPD_3:
 414                         tmp = RREG32(DC_HPD3_INT_CONTROL);
 415                         if (connected)
 416                                 tmp &= ~DC_HPDx_INT_POLARITY;
 417                         else
 418                                 tmp |= DC_HPDx_INT_POLARITY;
 419                         WREG32(DC_HPD3_INT_CONTROL, tmp);
 420                         break;
 421                 case RADEON_HPD_4:
 422                         tmp = RREG32(DC_HPD4_INT_CONTROL);
 423                         if (connected)
 424                                 tmp &= ~DC_HPDx_INT_POLARITY;
 425                         else
 426                                 tmp |= DC_HPDx_INT_POLARITY;
 427                         WREG32(DC_HPD4_INT_CONTROL, tmp);
 428                         break;
 429                 case RADEON_HPD_5:
 430                         tmp = RREG32(DC_HPD5_INT_CONTROL);
 431                         if (connected)
 432                                 tmp &= ~DC_HPDx_INT_POLARITY;
 433                         else
 434                                 tmp |= DC_HPDx_INT_POLARITY;
 435                         WREG32(DC_HPD5_INT_CONTROL, tmp);
 436                         break;
 437                         /* DCE 3.2 */
 438                 case RADEON_HPD_6:
 439                         tmp = RREG32(DC_HPD6_INT_CONTROL);
 440                         if (connected)
 441                                 tmp &= ~DC_HPDx_INT_POLARITY;
 442                         else
 443                                 tmp |= DC_HPDx_INT_POLARITY;
 444                         WREG32(DC_HPD6_INT_CONTROL, tmp);
 445                         break;
 446                 default:
 447                         break;
 448                 }
 449         } else {
 450                 switch (hpd) {
 451                 case RADEON_HPD_1:
 452                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
 453                         if (connected)
 454                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 455                         else
 456                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 457                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
 458                         break;
 459                 case RADEON_HPD_2:
 460                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
 461                         if (connected)
 462                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 463                         else
 464                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 465                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
 466                         break;
 467                 case RADEON_HPD_3:
 468                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
 469                         if (connected)
 470                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 471                         else
 472                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 473                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
 474                         break;
 475                 default:
 476                         break;
 477                 }
 478         }
 479 }
 480
 481 void r600_hpd_init(struct radeon_device *rdev)
 482 {
 483         struct drm_device *dev = rdev->ddev;
 484         struct drm_connector *connector;
 485
 486         if (ASIC_IS_DCE3(rdev)) {
 487                 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
 488                 if (ASIC_IS_DCE32(rdev))
 489                         tmp |= DC_HPDx_EN;
 490
 491                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 492                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 493                         switch (radeon_connector->hpd.hpd) {
 494                         case RADEON_HPD_1:
 495                                 WREG32(DC_HPD1_CONTROL, tmp);
 496                                 rdev->irq.hpd[0] = true;
 497                                 break;
 498                         case RADEON_HPD_2:
 499                                 WREG32(DC_HPD2_CONTROL, tmp);
 500                                 rdev->irq.hpd[1] = true;
 501                                 break;
 502                         case RADEON_HPD_3:
 503                                 WREG32(DC_HPD3_CONTROL, tmp);
 504                                 rdev->irq.hpd[2] = true;
 505                                 break;
 506                         case RADEON_HPD_4:
 507                                 WREG32(DC_HPD4_CONTROL, tmp);
 508                                 rdev->irq.hpd[3] = true;
 509                                 break;
 510                                 /* DCE 3.2 */
 511                         case RADEON_HPD_5:
 512                                 WREG32(DC_HPD5_CONTROL, tmp);
 513                                 rdev->irq.hpd[4] = true;
 514                                 break;
 515                         case RADEON_HPD_6:
 516                                 WREG32(DC_HPD6_CONTROL, tmp);
 517                                 rdev->irq.hpd[5] = true;
 518                                 break;
 519                         default:
 520                                 break;
 521                         }
 522                 }
 523         } else {
 524                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 525                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 526                         switch (radeon_connector->hpd.hpd) {
 527                         case RADEON_HPD_1:
 528                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 529                                 rdev->irq.hpd[0] = true;
 530                                 break;
 531                         case RADEON_HPD_2:
 532                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 533                                 rdev->irq.hpd[1] = true;
 534                                 break;
 535                         case RADEON_HPD_3:
 536                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 537                                 rdev->irq.hpd[2] = true;
 538                                 break;
 539                         default:
 540                                 break;
 541                         }
 542                 }
 543         }
 544         if (rdev->irq.installed)
 545                 r600_irq_set(rdev);
 546 }
 547
 548 void r600_hpd_fini(struct radeon_device *rdev)
 549 {
 550         struct drm_device *dev = rdev->ddev;
 551         struct drm_connector *connector;
 552
 553         if (ASIC_IS_DCE3(rdev)) {
 554                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 555                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 556                         switch (radeon_connector->hpd.hpd) {
 557                         case RADEON_HPD_1:
 558                                 WREG32(DC_HPD1_CONTROL, 0);
 559                                 rdev->irq.hpd[0] = false;
 560                                 break;
 561                         case RADEON_HPD_2:
 562                                 WREG32(DC_HPD2_CONTROL, 0);
 563                                 rdev->irq.hpd[1] = false;
 564                                 break;
 565                         case RADEON_HPD_3:
 566                                 WREG32(DC_HPD3_CONTROL, 0);
 567                                 rdev->irq.hpd[2] = false;
 568                                 break;
 569                         case RADEON_HPD_4:
 570                                 WREG32(DC_HPD4_CONTROL, 0);
 571                                 rdev->irq.hpd[3] = false;
 572                                 break;
 573                                 /* DCE 3.2 */
 574                         case RADEON_HPD_5:
 575                                 WREG32(DC_HPD5_CONTROL, 0);
 576                                 rdev->irq.hpd[4] = false;
 577                                 break;
 578                         case RADEON_HPD_6:
 579                                 WREG32(DC_HPD6_CONTROL, 0);
 580                                 rdev->irq.hpd[5] = false;
 581                                 break;
 582                         default:
 583                                 break;
 584                         }
 585                 }
 586         } else {
 587                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 588                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 589                         switch (radeon_connector->hpd.hpd) {
 590                         case RADEON_HPD_1:
 591                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
 592                                 rdev->irq.hpd[0] = false;
 593                                 break;
 594                         case RADEON_HPD_2:
 595                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
 596                                 rdev->irq.hpd[1] = false;
 597                                 break;
 598                         case RADEON_HPD_3:
 599                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
 600                                 rdev->irq.hpd[2] = false;
 601                                 break;
 602                         default:
 603                                 break;
 604                         }
 605                 }
 606         }
 607 }
 608
 609 /*
 610  * R600 PCIE GART
 611  */
 612 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
 613 {
 614         unsigned i;
 615         u32 tmp;
 616
 617         /* flush hdp cache so updates hit vram */
 618         WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
 619
 620         WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
 621         WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
 622         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
 623         for (i = 0; i < rdev->usec_timeout; i++) {
 624                 /* read MC_STATUS */
 625                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
 626                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
 627                 if (tmp == 2) {
 628                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
 629                         return;
 630                 }
 631                 if (tmp) {
 632                         return;
 633                 }
 634                 udelay(1);
 635         }
 636 }
 637
 638 int r600_pcie_gart_init(struct radeon_device *rdev)
 639 {
 640         int r;
 641
 642         if (rdev->gart.table.vram.robj) {
 643                 WARN(1, "R600 PCIE GART already initialized.\n");
 644                 return 0;
 645         }
 646         /* Initialize common gart structure */
 647         r = radeon_gart_init(rdev);
 648         if (r)
 649                 return r;
 650         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
 651         return radeon_gart_table_vram_alloc(rdev);
 652 }
 653
 654 int r600_pcie_gart_enable(struct radeon_device *rdev)
 655 {
 656         u32 tmp;
 657         int r, i;
 658
 659         if (rdev->gart.table.vram.robj == NULL) {
 660                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 661                 return -EINVAL;
 662         }
 663         r = radeon_gart_table_vram_pin(rdev);
 664         if (r)
 665                 return r;
 666         radeon_gart_restore(rdev);
 667
 668         /* Setup L2 cache */
 669         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 670                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 671                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 672         WREG32(VM_L2_CNTL2, 0);
 673         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 674         /* Setup TLB control */
 675         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 676                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 677                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 678                 ENABLE_WAIT_L2_QUERY;
 679         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 680         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 681         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
 682         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 683         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 684         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 685         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 686         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 687         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 688         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 689         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 690         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 691         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 692         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 693         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 694         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 695         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 696         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 697                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 698         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 699                         (u32)(rdev->dummy_page.addr >> 12));
 700         for (i = 1; i < 7; i++)
 701                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 702
 703         r600_pcie_gart_tlb_flush(rdev);
 704         rdev->gart.ready = true;
 705         return 0;
 706 }
 707
 708 void r600_pcie_gart_disable(struct radeon_device *rdev)
 709 {
 710         u32 tmp;
 711         int i, r;
 712
 713         /* Disable all tables */
 714         for (i = 0; i < 7; i++)
 715                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 716
 717         /* Disable L2 cache */
 718         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
 719                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 720         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 721         /* Setup L1 TLB control */
 722         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 723                 ENABLE_WAIT_L2_QUERY;
 724         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 725         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 726         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 727         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 728         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 729         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 730         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 731         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 732         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
 733         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
 734         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 735         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 736         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
 737         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 738         if (rdev->gart.table.vram.robj) {
 739                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
 740                 if (likely(r == 0)) {
 741                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
 742                         radeon_bo_unpin(rdev->gart.table.vram.robj);
 743                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
 744                 }
 745         }
 746 }
 747
 748 void r600_pcie_gart_fini(struct radeon_device *rdev)
 749 {
 750         radeon_gart_fini(rdev);
 751         r600_pcie_gart_disable(rdev);
 752         radeon_gart_table_vram_free(rdev);
 753 }
 754
 755 void r600_agp_enable(struct radeon_device *rdev)
 756 {
 757         u32 tmp;
 758         int i;
 759
 760         /* Setup L2 cache */
 761         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 762                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 763                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 764         WREG32(VM_L2_CNTL2, 0);
 765         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 766         /* Setup TLB control */
 767         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 768                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 769                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 770                 ENABLE_WAIT_L2_QUERY;
 771         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 772         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 773         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
 774         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 775         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 776         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 777         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 778         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 779         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 780         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 781         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 782         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 783         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 784         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 785         for (i = 0; i < 7; i++)
 786                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 787 }
 788
 789 int r600_mc_wait_for_idle(struct radeon_device *rdev)
 790 {
 791         unsigned i;
 792         u32 tmp;
 793
 794         for (i = 0; i < rdev->usec_timeout; i++) {
 795                 /* read MC_STATUS */
 796                 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
 797                 if (!tmp)
 798                         return 0;
 799                 udelay(1);
 800         }
 801         return -1;
 802 }
 803
 804 static void r600_mc_program(struct radeon_device *rdev)
 805 {
 806         struct rv515_mc_save save;
 807         u32 tmp;
 808         int i, j;
 809
 810         /* Initialize HDP */
 811         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
 812                 WREG32((0x2c14 + j), 0x00000000);
 813                 WREG32((0x2c18 + j), 0x00000000);
 814                 WREG32((0x2c1c + j), 0x00000000);
 815                 WREG32((0x2c20 + j), 0x00000000);
 816                 WREG32((0x2c24 + j), 0x00000000);
 817         }
 818         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
 819
 820         rv515_mc_stop(rdev, &save);
 821         if (r600_mc_wait_for_idle(rdev)) {
 822                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 823         }
 824         /* Lockout access through VGA aperture (doesn't exist before R600) */
 825         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
 826         /* Update configuration */
 827         if (rdev->flags & RADEON_IS_AGP) {
 828                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
 829                         /* VRAM before AGP */
 830                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 831                                 rdev->mc.vram_start >> 12);
 832                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 833                                 rdev->mc.gtt_end >> 12);
 834                 } else {
 835                         /* VRAM after AGP */
 836                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 837                                 rdev->mc.gtt_start >> 12);
 838                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 839                                 rdev->mc.vram_end >> 12);
 840                 }
 841         } else {
 842                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
 843                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
 844         }
 845         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
 846         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
 847         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
 848         WREG32(MC_VM_FB_LOCATION, tmp);
 849         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
 850         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
 851         WREG32(HDP_NONSURFACE_SIZE, rdev->mc.mc_vram_size | 0x3FF);
 852         if (rdev->flags & RADEON_IS_AGP) {
 853                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
 854                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
 855                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
 856         } else {
 857                 WREG32(MC_VM_AGP_BASE, 0);
 858                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
 859                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
 860         }
 861         if (r600_mc_wait_for_idle(rdev)) {
 862                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 863         }
 864         rv515_mc_resume(rdev, &save);
 865         /* we need to own VRAM, so turn off the VGA renderer here
 866          * to stop it overwriting our objects */
 867         rv515_vga_render_disable(rdev);
 868 }
 869
 870 /**
 871  * r600_vram_gtt_location - try to find VRAM & GTT location
 872  * @rdev: radeon device structure holding all necessary informations
 873  * @mc: memory controller structure holding memory informations
 874  *
 875  * Function will place try to place VRAM at same place as in CPU (PCI)
 876  * address space as some GPU seems to have issue when we reprogram at
 877  * different address space.
 878  *
 879  * If there is not enough space to fit the unvisible VRAM after the
 880  * aperture then we limit the VRAM size to the aperture.
 881  *
 882  * If we are using AGP then place VRAM adjacent to AGP aperture are we need
 883  * them to be in one from GPU point of view so that we can program GPU to
 884  * catch access outside them (weird GPU policy see ??).
 885  *
 886  * This function will never fails, worst case are limiting VRAM or GTT.
 887  *
 888  * Note: GTT start, end, size should be initialized before calling this
 889  * function on AGP platform.
 890  */
 891 void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
 892 {
 893         u64 size_bf, size_af;
 894
 895         if (mc->mc_vram_size > 0xE0000000) {
 896                 /* leave room for at least 512M GTT */
 897                 dev_warn(rdev->dev, "limiting VRAM\n");
 898                 mc->real_vram_size = 0xE0000000;
 899                 mc->mc_vram_size = 0xE0000000;
 900         }
 901         if (rdev->flags & RADEON_IS_AGP) {
 902                 size_bf = mc->gtt_start;
 903                 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
 904                 if (size_bf > size_af) {
 905                         if (mc->mc_vram_size > size_bf) {
 906                                 dev_warn(rdev->dev, "limiting VRAM\n");
 907                                 mc->real_vram_size = size_bf;
 908                                 mc->mc_vram_size = size_bf;
 909                         }
 910                         mc->vram_start = mc->gtt_start - mc->mc_vram_size;
 911                 } else {
 912                         if (mc->mc_vram_size > size_af) {
 913                                 dev_warn(rdev->dev, "limiting VRAM\n");
 914                                 mc->real_vram_size = size_af;
 915                                 mc->mc_vram_size = size_af;
 916                         }
 917                         mc->vram_start = mc->gtt_end;
 918                 }
 919                 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
 920                 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
 921                                 mc->mc_vram_size >> 20, mc->vram_start,
 922                                 mc->vram_end, mc->real_vram_size >> 20);
 923         } else {
 924                 u64 base = 0;
 925                 if (rdev->flags & RADEON_IS_IGP)
 926                         base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
 927                 radeon_vram_location(rdev, &rdev->mc, base);
 928                 radeon_gtt_location(rdev, mc);
 929         }
 930 }
 931
 932 int r600_mc_init(struct radeon_device *rdev)
 933 {
 934         u32 tmp;
 935         int chansize, numchan;
 936
 937         /* Get VRAM informations */
 938         rdev->mc.vram_is_ddr = true;
 939         tmp = RREG32(RAMCFG);
 940         if (tmp & CHANSIZE_OVERRIDE) {
 941                 chansize = 16;
 942         } else if (tmp & CHANSIZE_MASK) {
 943                 chansize = 64;
 944         } else {
 945                 chansize = 32;
 946         }
 947         tmp = RREG32(CHMAP);
 948         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
 949         case 0:
 950         default:
 951                 numchan = 1;
 952                 break;
 953         case 1:
 954                 numchan = 2;
 955                 break;
 956         case 2:
 957                 numchan = 4;
 958                 break;
 959         case 3:
 960                 numchan = 8;
 961                 break;
 962         }
 963         rdev->mc.vram_width = numchan * chansize;
 964         /* Could aper size report 0 ? */
 965         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
 966         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
 967         /* Setup GPU memory space */
 968         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
 969         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
 970         rdev->mc.visible_vram_size = rdev->mc.aper_size;
 971         r600_vram_gtt_location(rdev, &rdev->mc);
 972
 973         if (rdev->flags & RADEON_IS_IGP)
 974                 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
 975         radeon_update_bandwidth_info(rdev);
 976         return 0;
 977 }
 978
 979 /* We doesn't check that the GPU really needs a reset we simply do the
 980  * reset, it's up to the caller to determine if the GPU needs one. We
 981  * might add an helper function to check that.
 982  */
 983 int r600_gpu_soft_reset(struct radeon_device *rdev)
 984 {
 985         struct rv515_mc_save save;
 986         u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
 987                                 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
 988                                 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
 989                                 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
 990                                 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
 991                                 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
 992                                 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
 993                                 S_008010_GUI_ACTIVE(1);
 994         u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
 995                         S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
 996                         S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
 997                         S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
 998                         S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
 999                         S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
1000                         S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
1001                         S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
1002         u32 tmp;
1003
1004         dev_info(rdev->dev, "GPU softreset \n");
1005         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
1006                 RREG32(R_008010_GRBM_STATUS));
1007         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
1008                 RREG32(R_008014_GRBM_STATUS2));
1009         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
1010                 RREG32(R_000E50_SRBM_STATUS));
1011         rv515_mc_stop(rdev, &save);
1012         if (r600_mc_wait_for_idle(rdev)) {
1013                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1014         }
1015         /* Disable CP parsing/prefetching */
1016         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1017         /* Check if any of the rendering block is busy and reset it */
1018         if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
1019             (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
1020                 tmp = S_008020_SOFT_RESET_CR(1) |
1021                         S_008020_SOFT_RESET_DB(1) |
1022                         S_008020_SOFT_RESET_CB(1) |
1023                         S_008020_SOFT_RESET_PA(1) |
1024                         S_008020_SOFT_RESET_SC(1) |
1025                         S_008020_SOFT_RESET_SMX(1) |
1026                         S_008020_SOFT_RESET_SPI(1) |
1027                         S_008020_SOFT_RESET_SX(1) |
1028                         S_008020_SOFT_RESET_SH(1) |
1029                         S_008020_SOFT_RESET_TC(1) |
1030                         S_008020_SOFT_RESET_TA(1) |
1031                         S_008020_SOFT_RESET_VC(1) |
1032                         S_008020_SOFT_RESET_VGT(1);
1033                 dev_info(rdev->dev, "  R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1034                 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1035                 RREG32(R_008020_GRBM_SOFT_RESET);
1036                 mdelay(15);
1037                 WREG32(R_008020_GRBM_SOFT_RESET, 0);
1038         }
1039         /* Reset CP (we always reset CP) */
1040         tmp = S_008020_SOFT_RESET_CP(1);
1041         dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1042         WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1043         RREG32(R_008020_GRBM_SOFT_RESET);
1044         mdelay(15);
1045         WREG32(R_008020_GRBM_SOFT_RESET, 0);
1046         /* Wait a little for things to settle down */
1047         mdelay(1);
1048         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
1049                 RREG32(R_008010_GRBM_STATUS));
1050         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
1051                 RREG32(R_008014_GRBM_STATUS2));
1052         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
1053                 RREG32(R_000E50_SRBM_STATUS));
1054         rv515_mc_resume(rdev, &save);
1055         return 0;
1056 }
1057
1058 bool r600_gpu_is_lockup(struct radeon_device *rdev)
1059 {
1060         u32 srbm_status;
1061         u32 grbm_status;
1062         u32 grbm_status2;
1063         int r;
1064
1065         srbm_status = RREG32(R_000E50_SRBM_STATUS);
1066         grbm_status = RREG32(R_008010_GRBM_STATUS);
1067         grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1068         if (!G_008010_GUI_ACTIVE(grbm_status)) {
1069                 r100_gpu_lockup_update(&rdev->config.r300.lockup, &rdev->cp);
1070                 return false;
1071         }
1072         /* force CP activities */
1073         r = radeon_ring_lock(rdev, 2);
1074         if (!r) {
1075                 /* PACKET2 NOP */
1076                 radeon_ring_write(rdev, 0x80000000);
1077                 radeon_ring_write(rdev, 0x80000000);
1078                 radeon_ring_unlock_commit(rdev);
1079         }
1080         rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
1081         return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, &rdev->cp);
1082 }
1083
1084 int r600_asic_reset(struct radeon_device *rdev)
1085 {
1086         return r600_gpu_soft_reset(rdev);
1087 }
1088
1089 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
1090                                              u32 num_backends,
1091                                              u32 backend_disable_mask)
1092 {
1093         u32 backend_map = 0;
1094         u32 enabled_backends_mask;
1095         u32 enabled_backends_count;
1096         u32 cur_pipe;
1097         u32 swizzle_pipe[R6XX_MAX_PIPES];
1098         u32 cur_backend;
1099         u32 i;
1100
1101         if (num_tile_pipes > R6XX_MAX_PIPES)
1102                 num_tile_pipes = R6XX_MAX_PIPES;
1103         if (num_tile_pipes < 1)
1104                 num_tile_pipes = 1;
1105         if (num_backends > R6XX_MAX_BACKENDS)
1106                 num_backends = R6XX_MAX_BACKENDS;
1107         if (num_backends < 1)
1108                 num_backends = 1;
1109
1110         enabled_backends_mask = 0;
1111         enabled_backends_count = 0;
1112         for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
1113                 if (((backend_disable_mask >> i) & 1) == 0) {
1114                         enabled_backends_mask |= (1 << i);
1115                         ++enabled_backends_count;
1116                 }
1117                 if (enabled_backends_count == num_backends)
1118                         break;
1119         }
1120
1121         if (enabled_backends_count == 0) {
1122                 enabled_backends_mask = 1;
1123                 enabled_backends_count = 1;
1124         }
1125
1126         if (enabled_backends_count != num_backends)
1127                 num_backends = enabled_backends_count;
1128
1129         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
1130         switch (num_tile_pipes) {
1131         case 1:
1132                 swizzle_pipe[0] = 0;
1133                 break;
1134         case 2:
1135                 swizzle_pipe[0] = 0;
1136                 swizzle_pipe[1] = 1;
1137                 break;
1138         case 3:
1139                 swizzle_pipe[0] = 0;
1140                 swizzle_pipe[1] = 1;
1141                 swizzle_pipe[2] = 2;
1142                 break;
1143         case 4:
1144                 swizzle_pipe[0] = 0;
1145                 swizzle_pipe[1] = 1;
1146                 swizzle_pipe[2] = 2;
1147                 swizzle_pipe[3] = 3;
1148                 break;
1149         case 5:
1150                 swizzle_pipe[0] = 0;
1151                 swizzle_pipe[1] = 1;
1152                 swizzle_pipe[2] = 2;
1153                 swizzle_pipe[3] = 3;
1154                 swizzle_pipe[4] = 4;
1155                 break;
1156         case 6:
1157                 swizzle_pipe[0] = 0;
1158                 swizzle_pipe[1] = 2;
1159                 swizzle_pipe[2] = 4;
1160                 swizzle_pipe[3] = 5;
1161                 swizzle_pipe[4] = 1;
1162                 swizzle_pipe[5] = 3;
1163                 break;
1164         case 7:
1165                 swizzle_pipe[0] = 0;
1166                 swizzle_pipe[1] = 2;
1167                 swizzle_pipe[2] = 4;
1168                 swizzle_pipe[3] = 6;
1169                 swizzle_pipe[4] = 1;
1170                 swizzle_pipe[5] = 3;
1171                 swizzle_pipe[6] = 5;
1172                 break;
1173         case 8:
1174                 swizzle_pipe[0] = 0;
1175                 swizzle_pipe[1] = 2;
1176                 swizzle_pipe[2] = 4;
1177                 swizzle_pipe[3] = 6;
1178                 swizzle_pipe[4] = 1;
1179                 swizzle_pipe[5] = 3;
1180                 swizzle_pipe[6] = 5;
1181                 swizzle_pipe[7] = 7;
1182                 break;
1183         }
1184
1185         cur_backend = 0;
1186         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1187                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1188                         cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1189
1190                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1191
1192                 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1193         }
1194
1195         return backend_map;
1196 }
1197
1198 int r600_count_pipe_bits(uint32_t val)
1199 {
1200         int i, ret = 0;
1201
1202         for (i = 0; i < 32; i++) {
1203                 ret += val & 1;
1204                 val >>= 1;
1205         }
1206         return ret;
1207 }
1208
1209 void r600_gpu_init(struct radeon_device *rdev)
1210 {
1211         u32 tiling_config;
1212         u32 ramcfg;
1213         u32 backend_map;
1214         u32 cc_rb_backend_disable;
1215         u32 cc_gc_shader_pipe_config;
1216         u32 tmp;
1217         int i, j;
1218         u32 sq_config;
1219         u32 sq_gpr_resource_mgmt_1 = 0;
1220         u32 sq_gpr_resource_mgmt_2 = 0;
1221         u32 sq_thread_resource_mgmt = 0;
1222         u32 sq_stack_resource_mgmt_1 = 0;
1223         u32 sq_stack_resource_mgmt_2 = 0;
1224
1225         /* FIXME: implement */
1226         switch (rdev->family) {
1227         case CHIP_R600:
1228                 rdev->config.r600.max_pipes = 4;
1229                 rdev->config.r600.max_tile_pipes = 8;
1230                 rdev->config.r600.max_simds = 4;
1231                 rdev->config.r600.max_backends = 4;
1232                 rdev->config.r600.max_gprs = 256;
1233                 rdev->config.r600.max_threads = 192;
1234                 rdev->config.r600.max_stack_entries = 256;
1235                 rdev->config.r600.max_hw_contexts = 8;
1236                 rdev->config.r600.max_gs_threads = 16;
1237                 rdev->config.r600.sx_max_export_size = 128;
1238                 rdev->config.r600.sx_max_export_pos_size = 16;
1239                 rdev->config.r600.sx_max_export_smx_size = 128;
1240                 rdev->config.r600.sq_num_cf_insts = 2;
1241                 break;
1242         case CHIP_RV630:
1243         case CHIP_RV635:
1244                 rdev->config.r600.max_pipes = 2;
1245                 rdev->config.r600.max_tile_pipes = 2;
1246                 rdev->config.r600.max_simds = 3;
1247                 rdev->config.r600.max_backends = 1;
1248                 rdev->config.r600.max_gprs = 128;
1249                 rdev->config.r600.max_threads = 192;
1250                 rdev->config.r600.max_stack_entries = 128;
1251                 rdev->config.r600.max_hw_contexts = 8;
1252                 rdev->config.r600.max_gs_threads = 4;
1253                 rdev->config.r600.sx_max_export_size = 128;
1254                 rdev->config.r600.sx_max_export_pos_size = 16;
1255                 rdev->config.r600.sx_max_export_smx_size = 128;
1256                 rdev->config.r600.sq_num_cf_insts = 2;
1257                 break;
1258         case CHIP_RV610:
1259         case CHIP_RV620:
1260         case CHIP_RS780:
1261         case CHIP_RS880:
1262                 rdev->config.r600.max_pipes = 1;
1263                 rdev->config.r600.max_tile_pipes = 1;
1264                 rdev->config.r600.max_simds = 2;
1265                 rdev->config.r600.max_backends = 1;
1266                 rdev->config.r600.max_gprs = 128;
1267                 rdev->config.r600.max_threads = 192;
1268                 rdev->config.r600.max_stack_entries = 128;
1269                 rdev->config.r600.max_hw_contexts = 4;
1270                 rdev->config.r600.max_gs_threads = 4;
1271                 rdev->config.r600.sx_max_export_size = 128;
1272                 rdev->config.r600.sx_max_export_pos_size = 16;
1273                 rdev->config.r600.sx_max_export_smx_size = 128;
1274                 rdev->config.r600.sq_num_cf_insts = 1;
1275                 break;
1276         case CHIP_RV670:
1277                 rdev->config.r600.max_pipes = 4;
1278                 rdev->config.r600.max_tile_pipes = 4;
1279                 rdev->config.r600.max_simds = 4;
1280                 rdev->config.r600.max_backends = 4;
1281                 rdev->config.r600.max_gprs = 192;
1282                 rdev->config.r600.max_threads = 192;
1283                 rdev->config.r600.max_stack_entries = 256;
1284                 rdev->config.r600.max_hw_contexts = 8;
1285                 rdev->config.r600.max_gs_threads = 16;
1286                 rdev->config.r600.sx_max_export_size = 128;
1287                 rdev->config.r600.sx_max_export_pos_size = 16;
1288                 rdev->config.r600.sx_max_export_smx_size = 128;
1289                 rdev->config.r600.sq_num_cf_insts = 2;
1290                 break;
1291         default:
1292                 break;
1293         }
1294
1295         /* Initialize HDP */
1296         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1297                 WREG32((0x2c14 + j), 0x00000000);
1298                 WREG32((0x2c18 + j), 0x00000000);
1299                 WREG32((0x2c1c + j), 0x00000000);
1300                 WREG32((0x2c20 + j), 0x00000000);
1301                 WREG32((0x2c24 + j), 0x00000000);
1302         }
1303
1304         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1305
1306         /* Setup tiling */
1307         tiling_config = 0;
1308         ramcfg = RREG32(RAMCFG);
1309         switch (rdev->config.r600.max_tile_pipes) {
1310         case 1:
1311                 tiling_config |= PIPE_TILING(0);
1312                 break;
1313         case 2:
1314                 tiling_config |= PIPE_TILING(1);
1315                 break;
1316         case 4:
1317                 tiling_config |= PIPE_TILING(2);
1318                 break;
1319         case 8:
1320                 tiling_config |= PIPE_TILING(3);
1321                 break;
1322         default:
1323                 break;
1324         }
1325         rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
1326         rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1327         tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1328         tiling_config |= GROUP_SIZE(0);
1329         rdev->config.r600.tiling_group_size = 256;
1330         tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1331         if (tmp > 3) {
1332                 tiling_config |= ROW_TILING(3);
1333                 tiling_config |= SAMPLE_SPLIT(3);
1334         } else {
1335                 tiling_config |= ROW_TILING(tmp);
1336                 tiling_config |= SAMPLE_SPLIT(tmp);
1337         }
1338         tiling_config |= BANK_SWAPS(1);
1339
1340         cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1341         cc_rb_backend_disable |=
1342                 BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1343
1344         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1345         cc_gc_shader_pipe_config |=
1346                 INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1347         cc_gc_shader_pipe_config |=
1348                 INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1349
1350         backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1351                                                         (R6XX_MAX_BACKENDS -
1352                                                          r600_count_pipe_bits((cc_rb_backend_disable &
1353                                                                                R6XX_MAX_BACKENDS_MASK) >> 16)),
1354                                                         (cc_rb_backend_disable >> 16));
1355
1356         tiling_config |= BACKEND_MAP(backend_map);
1357         WREG32(GB_TILING_CONFIG, tiling_config);
1358         WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1359         WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1360
1361         /* Setup pipes */
1362         WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1363         WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1364         WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1365
1366         tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1367         WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1368         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1369
1370         /* Setup some CP states */
1371         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1372         WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1373
1374         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1375                              SYNC_WALKER | SYNC_ALIGNER));
1376         /* Setup various GPU states */
1377         if (rdev->family == CHIP_RV670)
1378                 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1379
1380         tmp = RREG32(SX_DEBUG_1);
1381         tmp |= SMX_EVENT_RELEASE;
1382         if ((rdev->family > CHIP_R600))
1383                 tmp |= ENABLE_NEW_SMX_ADDRESS;
1384         WREG32(SX_DEBUG_1, tmp);
1385
1386         if (((rdev->family) == CHIP_R600) ||
1387             ((rdev->family) == CHIP_RV630) ||
1388             ((rdev->family) == CHIP_RV610) ||
1389             ((rdev->family) == CHIP_RV620) ||
1390             ((rdev->family) == CHIP_RS780) ||
1391             ((rdev->family) == CHIP_RS880)) {
1392                 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1393         } else {
1394                 WREG32(DB_DEBUG, 0);
1395         }
1396         WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1397                                DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1398
1399         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1400         WREG32(VGT_NUM_INSTANCES, 0);
1401
1402         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1403         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1404
1405         tmp = RREG32(SQ_MS_FIFO_SIZES);
1406         if (((rdev->family) == CHIP_RV610) ||
1407             ((rdev->family) == CHIP_RV620) ||
1408             ((rdev->family) == CHIP_RS780) ||
1409             ((rdev->family) == CHIP_RS880)) {
1410                 tmp = (CACHE_FIFO_SIZE(0xa) |
1411                        FETCH_FIFO_HIWATER(0xa) |
1412                        DONE_FIFO_HIWATER(0xe0) |
1413                        ALU_UPDATE_FIFO_HIWATER(0x8));
1414         } else if (((rdev->family) == CHIP_R600) ||
1415                    ((rdev->family) == CHIP_RV630)) {
1416                 tmp &= ~DONE_FIFO_HIWATER(0xff);
1417                 tmp |= DONE_FIFO_HIWATER(0x4);
1418         }
1419         WREG32(SQ_MS_FIFO_SIZES, tmp);
1420
1421         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1422          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
1423          */
1424         sq_config = RREG32(SQ_CONFIG);
1425         sq_config &= ~(PS_PRIO(3) |
1426                        VS_PRIO(3) |
1427                        GS_PRIO(3) |
1428                        ES_PRIO(3));
1429         sq_config |= (DX9_CONSTS |
1430                       VC_ENABLE |
1431                       PS_PRIO(0) |
1432                       VS_PRIO(1) |
1433                       GS_PRIO(2) |
1434                       ES_PRIO(3));
1435
1436         if ((rdev->family) == CHIP_R600) {
1437                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1438                                           NUM_VS_GPRS(124) |
1439                                           NUM_CLAUSE_TEMP_GPRS(4));
1440                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1441                                           NUM_ES_GPRS(0));
1442                 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1443                                            NUM_VS_THREADS(48) |
1444                                            NUM_GS_THREADS(4) |
1445                                            NUM_ES_THREADS(4));
1446                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1447                                             NUM_VS_STACK_ENTRIES(128));
1448                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1449                                             NUM_ES_STACK_ENTRIES(0));
1450         } else if (((rdev->family) == CHIP_RV610) ||
1451                    ((rdev->family) == CHIP_RV620) ||
1452                    ((rdev->family) == CHIP_RS780) ||
1453                    ((rdev->family) == CHIP_RS880)) {
1454                 /* no vertex cache */
1455                 sq_config &= ~VC_ENABLE;
1456
1457                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1458                                           NUM_VS_GPRS(44) |
1459                                           NUM_CLAUSE_TEMP_GPRS(2));
1460                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1461                                           NUM_ES_GPRS(17));
1462                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1463                                            NUM_VS_THREADS(78) |
1464                                            NUM_GS_THREADS(4) |
1465                                            NUM_ES_THREADS(31));
1466                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1467                                             NUM_VS_STACK_ENTRIES(40));
1468                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1469                                             NUM_ES_STACK_ENTRIES(16));
1470         } else if (((rdev->family) == CHIP_RV630) ||
1471                    ((rdev->family) == CHIP_RV635)) {
1472                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1473                                           NUM_VS_GPRS(44) |
1474                                           NUM_CLAUSE_TEMP_GPRS(2));
1475                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1476                                           NUM_ES_GPRS(18));
1477                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1478                                            NUM_VS_THREADS(78) |
1479                                            NUM_GS_THREADS(4) |
1480                                            NUM_ES_THREADS(31));
1481                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1482                                             NUM_VS_STACK_ENTRIES(40));
1483                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1484                                             NUM_ES_STACK_ENTRIES(16));
1485         } else if ((rdev->family) == CHIP_RV670) {
1486                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1487                                           NUM_VS_GPRS(44) |
1488                                           NUM_CLAUSE_TEMP_GPRS(2));
1489                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1490                                           NUM_ES_GPRS(17));
1491                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1492                                            NUM_VS_THREADS(78) |
1493                                            NUM_GS_THREADS(4) |
1494                                            NUM_ES_THREADS(31));
1495                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1496                                             NUM_VS_STACK_ENTRIES(64));
1497                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1498                                             NUM_ES_STACK_ENTRIES(64));
1499         }
1500
1501         WREG32(SQ_CONFIG, sq_config);
1502         WREG32(SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
1503         WREG32(SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
1504         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1505         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1506         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1507
1508         if (((rdev->family) == CHIP_RV610) ||
1509             ((rdev->family) == CHIP_RV620) ||
1510             ((rdev->family) == CHIP_RS780) ||
1511             ((rdev->family) == CHIP_RS880)) {
1512                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1513         } else {
1514                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1515         }
1516
1517         /* More default values. 2D/3D driver should adjust as needed */
1518         WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1519                                          S1_X(0x4) | S1_Y(0xc)));
1520         WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1521                                          S1_X(0x2) | S1_Y(0x2) |
1522                                          S2_X(0xa) | S2_Y(0x6) |
1523                                          S3_X(0x6) | S3_Y(0xa)));
1524         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1525                                              S1_X(0x4) | S1_Y(0xc) |
1526                                              S2_X(0x1) | S2_Y(0x6) |
1527                                              S3_X(0xa) | S3_Y(0xe)));
1528         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1529                                              S5_X(0x0) | S5_Y(0x0) |
1530                                              S6_X(0xb) | S6_Y(0x4) |
1531                                              S7_X(0x7) | S7_Y(0x8)));
1532
1533         WREG32(VGT_STRMOUT_EN, 0);
1534         tmp = rdev->config.r600.max_pipes * 16;
1535         switch (rdev->family) {
1536         case CHIP_RV610:
1537         case CHIP_RV620:
1538         case CHIP_RS780:
1539         case CHIP_RS880:
1540                 tmp += 32;
1541                 break;
1542         case CHIP_RV670:
1543                 tmp += 128;
1544                 break;
1545         default:
1546                 break;
1547         }
1548         if (tmp > 256) {
1549                 tmp = 256;
1550         }
1551         WREG32(VGT_ES_PER_GS, 128);
1552         WREG32(VGT_GS_PER_ES, tmp);
1553         WREG32(VGT_GS_PER_VS, 2);
1554         WREG32(VGT_GS_VERTEX_REUSE, 16);
1555
1556         /* more default values. 2D/3D driver should adjust as needed */
1557         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1558         WREG32(VGT_STRMOUT_EN, 0);
1559         WREG32(SX_MISC, 0);
1560         WREG32(PA_SC_MODE_CNTL, 0);
1561         WREG32(PA_SC_AA_CONFIG, 0);
1562         WREG32(PA_SC_LINE_STIPPLE, 0);
1563         WREG32(SPI_INPUT_Z, 0);
1564         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1565         WREG32(CB_COLOR7_FRAG, 0);
1566
1567         /* Clear render buffer base addresses */
1568         WREG32(CB_COLOR0_BASE, 0);
1569         WREG32(CB_COLOR1_BASE, 0);
1570         WREG32(CB_COLOR2_BASE, 0);
1571         WREG32(CB_COLOR3_BASE, 0);
1572         WREG32(CB_COLOR4_BASE, 0);
1573         WREG32(CB_COLOR5_BASE, 0);
1574         WREG32(CB_COLOR6_BASE, 0);
1575         WREG32(CB_COLOR7_BASE, 0);
1576         WREG32(CB_COLOR7_FRAG, 0);
1577
1578         switch (rdev->family) {
1579         case CHIP_RV610:
1580         case CHIP_RV620:
1581         case CHIP_RS780:
1582         case CHIP_RS880:
1583                 tmp = TC_L2_SIZE(8);
1584                 break;
1585         case CHIP_RV630:
1586         case CHIP_RV635:
1587                 tmp = TC_L2_SIZE(4);
1588                 break;
1589         case CHIP_R600:
1590                 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1591                 break;
1592         default:
1593                 tmp = TC_L2_SIZE(0);
1594                 break;
1595         }
1596         WREG32(TC_CNTL, tmp);
1597
1598         tmp = RREG32(HDP_HOST_PATH_CNTL);
1599         WREG32(HDP_HOST_PATH_CNTL, tmp);
1600
1601         tmp = RREG32(ARB_POP);
1602         tmp |= ENABLE_TC128;
1603         WREG32(ARB_POP, tmp);
1604
1605         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1606         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1607                                NUM_CLIP_SEQ(3)));
1608         WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1609 }
1610
1611
1612 /*
1613  * Indirect registers accessor
1614  */
1615 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1616 {
1617         u32 r;
1618
1619         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1620         (void)RREG32(PCIE_PORT_INDEX);
1621         r = RREG32(PCIE_PORT_DATA);
1622         return r;
1623 }
1624
1625 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1626 {
1627         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1628         (void)RREG32(PCIE_PORT_INDEX);
1629         WREG32(PCIE_PORT_DATA, (v));
1630         (void)RREG32(PCIE_PORT_DATA);
1631 }
1632
1633 /*
1634  * CP & Ring
1635  */
1636 void r600_cp_stop(struct radeon_device *rdev)
1637 {
1638         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1639 }
1640
1641 int r600_init_microcode(struct radeon_device *rdev)
1642 {
1643         struct platform_device *pdev;
1644         const char *chip_name;
1645         const char *rlc_chip_name;
1646         size_t pfp_req_size, me_req_size, rlc_req_size;
1647         char fw_name[30];
1648         int err;
1649
1650         DRM_DEBUG("\n");
1651
1652         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1653         err = IS_ERR(pdev);
1654         if (err) {
1655                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1656                 return -EINVAL;
1657         }
1658
1659         switch (rdev->family) {
1660         case CHIP_R600:
1661                 chip_name = "R600";
1662                 rlc_chip_name = "R600";
1663                 break;
1664         case CHIP_RV610:
1665                 chip_name = "RV610";
1666                 rlc_chip_name = "R600";
1667                 break;
1668         case CHIP_RV630:
1669                 chip_name = "RV630";
1670                 rlc_chip_name = "R600";
1671                 break;
1672         case CHIP_RV620:
1673                 chip_name = "RV620";
1674                 rlc_chip_name = "R600";
1675                 break;
1676         case CHIP_RV635:
1677                 chip_name = "RV635";
1678                 rlc_chip_name = "R600";
1679                 break;
1680         case CHIP_RV670:
1681                 chip_name = "RV670";
1682                 rlc_chip_name = "R600";
1683                 break;
1684         case CHIP_RS780:
1685         case CHIP_RS880:
1686                 chip_name = "RS780";
1687                 rlc_chip_name = "R600";
1688                 break;
1689         case CHIP_RV770:
1690                 chip_name = "RV770";
1691                 rlc_chip_name = "R700";
1692                 break;
1693         case CHIP_RV730:
1694         case CHIP_RV740:
1695                 chip_name = "RV730";
1696                 rlc_chip_name = "R700";
1697                 break;
1698         case CHIP_RV710:
1699                 chip_name = "RV710";
1700                 rlc_chip_name = "R700";
1701                 break;
1702         case CHIP_CEDAR:
1703                 chip_name = "CEDAR";
1704                 rlc_chip_name = "CEDAR";
1705                 break;
1706         case CHIP_REDWOOD:
1707                 chip_name = "REDWOOD";
1708                 rlc_chip_name = "REDWOOD";
1709                 break;
1710         case CHIP_JUNIPER:
1711                 chip_name = "JUNIPER";
1712                 rlc_chip_name = "JUNIPER";
1713                 break;
1714         case CHIP_CYPRESS:
1715         case CHIP_HEMLOCK:
1716                 chip_name = "CYPRESS";
1717                 rlc_chip_name = "CYPRESS";
1718                 break;
1719         default: BUG();
1720         }
1721
1722         if (rdev->family >= CHIP_CEDAR) {
1723                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
1724                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
1725                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
1726         } else if (rdev->family >= CHIP_RV770) {
1727                 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
1728                 me_req_size = R700_PM4_UCODE_SIZE * 4;
1729                 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
1730         } else {
1731                 pfp_req_size = PFP_UCODE_SIZE * 4;
1732                 me_req_size = PM4_UCODE_SIZE * 12;
1733                 rlc_req_size = RLC_UCODE_SIZE * 4;
1734         }
1735
1736         DRM_INFO("Loading %s Microcode\n", chip_name);
1737
1738         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
1739         err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
1740         if (err)
1741                 goto out;
1742         if (rdev->pfp_fw->size != pfp_req_size) {
1743                 printk(KERN_ERR
1744                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1745                        rdev->pfp_fw->size, fw_name);
1746                 err = -EINVAL;
1747                 goto out;
1748         }
1749
1750         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
1751         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
1752         if (err)
1753                 goto out;
1754         if (rdev->me_fw->size != me_req_size) {
1755                 printk(KERN_ERR
1756                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1757                        rdev->me_fw->size, fw_name);
1758                 err = -EINVAL;
1759         }
1760
1761         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
1762         err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
1763         if (err)
1764                 goto out;
1765         if (rdev->rlc_fw->size != rlc_req_size) {
1766                 printk(KERN_ERR
1767                        "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
1768                        rdev->rlc_fw->size, fw_name);
1769                 err = -EINVAL;
1770         }
1771
1772 out:
1773         platform_device_unregister(pdev);
1774
1775         if (err) {
1776                 if (err != -EINVAL)
1777                         printk(KERN_ERR
1778                                "r600_cp: Failed to load firmware \"%s\"\n",
1779                                fw_name);
1780                 release_firmware(rdev->pfp_fw);
1781                 rdev->pfp_fw = NULL;
1782                 release_firmware(rdev->me_fw);
1783                 rdev->me_fw = NULL;
1784                 release_firmware(rdev->rlc_fw);
1785                 rdev->rlc_fw = NULL;
1786         }
1787         return err;
1788 }
1789
1790 static int r600_cp_load_microcode(struct radeon_device *rdev)
1791 {
1792         const __be32 *fw_data;
1793         int i;
1794
1795         if (!rdev->me_fw || !rdev->pfp_fw)
1796                 return -EINVAL;
1797
1798         r600_cp_stop(rdev);
1799
1800         WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1801
1802         /* Reset cp */
1803         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1804         RREG32(GRBM_SOFT_RESET);
1805         mdelay(15);
1806         WREG32(GRBM_SOFT_RESET, 0);
1807
1808         WREG32(CP_ME_RAM_WADDR, 0);
1809
1810         fw_data = (const __be32 *)rdev->me_fw->data;
1811         WREG32(CP_ME_RAM_WADDR, 0);
1812         for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
1813                 WREG32(CP_ME_RAM_DATA,
1814                        be32_to_cpup(fw_data++));
1815
1816         fw_data = (const __be32 *)rdev->pfp_fw->data;
1817         WREG32(CP_PFP_UCODE_ADDR, 0);
1818         for (i = 0; i < PFP_UCODE_SIZE; i++)
1819                 WREG32(CP_PFP_UCODE_DATA,
1820                        be32_to_cpup(fw_data++));
1821
1822         WREG32(CP_PFP_UCODE_ADDR, 0);
1823         WREG32(CP_ME_RAM_WADDR, 0);
1824         WREG32(CP_ME_RAM_RADDR, 0);
1825         return 0;
1826 }
1827
1828 int r600_cp_start(struct radeon_device *rdev)
1829 {
1830         int r;
1831         uint32_t cp_me;
1832
1833         r = radeon_ring_lock(rdev, 7);
1834         if (r) {
1835                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1836                 return r;
1837         }
1838         radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1839         radeon_ring_write(rdev, 0x1);
1840         if (rdev->family >= CHIP_CEDAR) {
1841                 radeon_ring_write(rdev, 0x0);
1842                 radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);
1843         } else if (rdev->family >= CHIP_RV770) {
1844                 radeon_ring_write(rdev, 0x0);
1845                 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
1846         } else {
1847                 radeon_ring_write(rdev, 0x3);
1848                 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
1849         }
1850         radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1851         radeon_ring_write(rdev, 0);
1852         radeon_ring_write(rdev, 0);
1853         radeon_ring_unlock_commit(rdev);
1854
1855         cp_me = 0xff;
1856         WREG32(R_0086D8_CP_ME_CNTL, cp_me);
1857         return 0;
1858 }
1859
1860 int r600_cp_resume(struct radeon_device *rdev)
1861 {
1862         u32 tmp;
1863         u32 rb_bufsz;
1864         int r;
1865
1866         /* Reset cp */
1867         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1868         RREG32(GRBM_SOFT_RESET);
1869         mdelay(15);
1870         WREG32(GRBM_SOFT_RESET, 0);
1871
1872         /* Set ring buffer size */
1873         rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1874         tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1875 #ifdef __BIG_ENDIAN
1876         tmp |= BUF_SWAP_32BIT;
1877 #endif
1878         WREG32(CP_RB_CNTL, tmp);
1879         WREG32(CP_SEM_WAIT_TIMER, 0x4);
1880
1881         /* Set the write pointer delay */
1882         WREG32(CP_RB_WPTR_DELAY, 0);
1883
1884         /* Initialize the ring buffer's read and write pointers */
1885         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1886         WREG32(CP_RB_RPTR_WR, 0);
1887         WREG32(CP_RB_WPTR, 0);
1888         WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
1889         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
1890         mdelay(1);
1891         WREG32(CP_RB_CNTL, tmp);
1892
1893         WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1894         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1895
1896         rdev->cp.rptr = RREG32(CP_RB_RPTR);
1897         rdev->cp.wptr = RREG32(CP_RB_WPTR);
1898
1899         r600_cp_start(rdev);
1900         rdev->cp.ready = true;
1901         r = radeon_ring_test(rdev);
1902         if (r) {
1903                 rdev->cp.ready = false;
1904                 return r;
1905         }
1906         return 0;
1907 }
1908
1909 void r600_cp_commit(struct radeon_device *rdev)
1910 {
1911         WREG32(CP_RB_WPTR, rdev->cp.wptr);
1912         (void)RREG32(CP_RB_WPTR);
1913 }
1914
1915 void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
1916 {
1917         u32 rb_bufsz;
1918
1919         /* Align ring size */
1920         rb_bufsz = drm_order(ring_size / 8);
1921         ring_size = (1 << (rb_bufsz + 1)) * 4;
1922         rdev->cp.ring_size = ring_size;
1923         rdev->cp.align_mask = 16 - 1;
1924 }
1925
1926 void r600_cp_fini(struct radeon_device *rdev)
1927 {
1928         r600_cp_stop(rdev);
1929         radeon_ring_fini(rdev);
1930 }
1931
1932
1933 /*
1934  * GPU scratch registers helpers function.
1935  */
1936 void r600_scratch_init(struct radeon_device *rdev)
1937 {
1938         int i;
1939
1940         rdev->scratch.num_reg = 7;
1941         for (i = 0; i < rdev->scratch.num_reg; i++) {
1942                 rdev->scratch.free[i] = true;
1943                 rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4);
1944         }
1945 }
1946
1947 int r600_ring_test(struct radeon_device *rdev)
1948 {
1949         uint32_t scratch;
1950         uint32_t tmp = 0;
1951         unsigned i;
1952         int r;
1953
1954         r = radeon_scratch_get(rdev, &scratch);
1955         if (r) {
1956                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
1957                 return r;
1958         }
1959         WREG32(scratch, 0xCAFEDEAD);
1960         r = radeon_ring_lock(rdev, 3);
1961         if (r) {
1962                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1963                 radeon_scratch_free(rdev, scratch);
1964                 return r;
1965         }
1966         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1967         radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1968         radeon_ring_write(rdev, 0xDEADBEEF);
1969         radeon_ring_unlock_commit(rdev);
1970         for (i = 0; i < rdev->usec_timeout; i++) {
1971                 tmp = RREG32(scratch);
1972                 if (tmp == 0xDEADBEEF)
1973                         break;
1974                 DRM_UDELAY(1);
1975         }
1976         if (i < rdev->usec_timeout) {
1977                 DRM_INFO("ring test succeeded in %d usecs\n", i);
1978         } else {
1979                 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
1980                           scratch, tmp);
1981                 r = -EINVAL;
1982         }
1983         radeon_scratch_free(rdev, scratch);
1984         return r;
1985 }
1986
1987 void r600_wb_disable(struct radeon_device *rdev)
1988 {
1989         int r;
1990
1991         WREG32(SCRATCH_UMSK, 0);
1992         if (rdev->wb.wb_obj) {
1993                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
1994                 if (unlikely(r != 0))
1995                         return;
1996                 radeon_bo_kunmap(rdev->wb.wb_obj);
1997                 radeon_bo_unpin(rdev->wb.wb_obj);
1998                 radeon_bo_unreserve(rdev->wb.wb_obj);
1999         }
2000 }
2001
2002 void r600_wb_fini(struct radeon_device *rdev)
2003 {
2004         r600_wb_disable(rdev);
2005         if (rdev->wb.wb_obj) {
2006                 radeon_bo_unref(&rdev->wb.wb_obj);
2007                 rdev->wb.wb = NULL;
2008                 rdev->wb.wb_obj = NULL;
2009         }
2010 }
2011
2012 int r600_wb_enable(struct radeon_device *rdev)
2013 {
2014         int r;
2015
2016         if (rdev->wb.wb_obj == NULL) {
2017                 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
2018                                 RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj);
2019                 if (r) {
2020                         dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
2021                         return r;
2022                 }
2023                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
2024                 if (unlikely(r != 0)) {
2025                         r600_wb_fini(rdev);
2026                         return r;
2027                 }
2028                 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
2029                                 &rdev->wb.gpu_addr);
2030                 if (r) {
2031                         radeon_bo_unreserve(rdev->wb.wb_obj);
2032                         dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
2033                         r600_wb_fini(rdev);
2034                         return r;
2035                 }
2036                 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
2037                 radeon_bo_unreserve(rdev->wb.wb_obj);
2038                 if (r) {
2039                         dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
2040                         r600_wb_fini(rdev);
2041                         return r;
2042                 }
2043         }
2044         WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF);
2045         WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC);
2046         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF);
2047         WREG32(SCRATCH_UMSK, 0xff);
2048         return 0;
2049 }
2050
2051 void r600_fence_ring_emit(struct radeon_device *rdev,
2052                           struct radeon_fence *fence)
2053 {
2054         /* Also consider EVENT_WRITE_EOP.  it handles the interrupts + timestamps + events */
2055
2056         radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
2057         radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT);
2058         /* wait for 3D idle clean */
2059         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2060         radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2061         radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
2062         /* Emit fence sequence & fire IRQ */
2063         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2064         radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2065         radeon_ring_write(rdev, fence->seq);
2066         /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2067         radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
2068         radeon_ring_write(rdev, RB_INT_STAT);
2069 }
2070
2071 int r600_copy_blit(struct radeon_device *rdev,
2072                    uint64_t src_offset, uint64_t dst_offset,
2073                    unsigned num_pages, struct radeon_fence *fence)
2074 {
2075         int r;
2076
2077         mutex_lock(&rdev->r600_blit.mutex);
2078         rdev->r600_blit.vb_ib = NULL;
2079         r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
2080         if (r) {
2081                 if (rdev->r600_blit.vb_ib)
2082                         radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
2083                 mutex_unlock(&rdev->r600_blit.mutex);
2084                 return r;
2085         }
2086         r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
2087         r600_blit_done_copy(rdev, fence);
2088         mutex_unlock(&rdev->r600_blit.mutex);
2089         return 0;
2090 }
2091
2092 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2093                          uint32_t tiling_flags, uint32_t pitch,
2094                          uint32_t offset, uint32_t obj_size)
2095 {
2096         /* FIXME: implement */
2097         return 0;
2098 }
2099
2100 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2101 {
2102         /* FIXME: implement */
2103 }
2104
2105
2106 bool r600_card_posted(struct radeon_device *rdev)
2107 {
2108         uint32_t reg;
2109
2110         /* first check CRTCs */
2111         reg = RREG32(D1CRTC_CONTROL) |
2112                 RREG32(D2CRTC_CONTROL);
2113         if (reg & CRTC_EN)
2114                 return true;
2115
2116         /* then check MEM_SIZE, in case the crtcs are off */
2117         if (RREG32(CONFIG_MEMSIZE))
2118                 return true;
2119
2120         return false;
2121 }
2122
2123 int r600_startup(struct radeon_device *rdev)
2124 {
2125         int r;
2126
2127         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2128                 r = r600_init_microcode(rdev);
2129                 if (r) {
2130                         DRM_ERROR("Failed to load firmware!\n");
2131                         return r;
2132                 }
2133         }
2134
2135         r600_mc_program(rdev);
2136         if (rdev->flags & RADEON_IS_AGP) {
2137                 r600_agp_enable(rdev);
2138         } else {
2139                 r = r600_pcie_gart_enable(rdev);
2140                 if (r)
2141                         return r;
2142         }
2143         r600_gpu_init(rdev);
2144         r = r600_blit_init(rdev);
2145         if (r) {
2146                 r600_blit_fini(rdev);
2147                 rdev->asic->copy = NULL;
2148                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2149         }
2150         /* pin copy shader into vram */
2151         if (rdev->r600_blit.shader_obj) {
2152                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2153                 if (unlikely(r != 0))
2154                         return r;
2155                 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
2156                                 &rdev->r600_blit.shader_gpu_addr);
2157                 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2158                 if (r) {
2159                         dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
2160                         return r;
2161                 }
2162         }
2163         /* Enable IRQ */
2164         r = r600_irq_init(rdev);
2165         if (r) {
2166                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2167                 radeon_irq_kms_fini(rdev);
2168                 return r;
2169         }
2170         r600_irq_set(rdev);
2171
2172         r = radeon_ring_init(rdev, rdev->cp.ring_size);
2173         if (r)
2174                 return r;
2175         r = r600_cp_load_microcode(rdev);
2176         if (r)
2177                 return r;
2178         r = r600_cp_resume(rdev);
2179         if (r)
2180                 return r;
2181         /* write back buffer are not vital so don't worry about failure */
2182         r600_wb_enable(rdev);
2183         return 0;
2184 }
2185
2186 void r600_vga_set_state(struct radeon_device *rdev, bool state)
2187 {
2188         uint32_t temp;
2189
2190         temp = RREG32(CONFIG_CNTL);
2191         if (state == false) {
2192                 temp &= ~(1<<0);
2193                 temp |= (1<<1);
2194         } else {
2195                 temp &= ~(1<<1);
2196         }
2197         WREG32(CONFIG_CNTL, temp);
2198 }
2199
2200 int r600_resume(struct radeon_device *rdev)
2201 {
2202         int r;
2203
2204         /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2205          * posting will perform necessary task to bring back GPU into good
2206          * shape.
2207          */
2208         /* post card */
2209         atom_asic_init(rdev->mode_info.atom_context);
2210         /* Initialize clocks */
2211         r = radeon_clocks_init(rdev);
2212         if (r) {
2213                 return r;
2214         }
2215
2216         r = r600_startup(rdev);
2217         if (r) {
2218                 DRM_ERROR("r600 startup failed on resume\n");
2219                 return r;
2220         }
2221
2222         r = r600_ib_test(rdev);
2223         if (r) {
2224                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
2225                 return r;
2226         }
2227
2228         r = r600_audio_init(rdev);
2229         if (r) {
2230                 DRM_ERROR("radeon: audio resume failed\n");
2231                 return r;
2232         }
2233
2234         return r;
2235 }
2236
2237 int r600_suspend(struct radeon_device *rdev)
2238 {
2239         int r;
2240
2241         r600_audio_fini(rdev);
2242         /* FIXME: we should wait for ring to be empty */
2243         r600_cp_stop(rdev);
2244         rdev->cp.ready = false;
2245         r600_irq_suspend(rdev);
2246         r600_wb_disable(rdev);
2247         r600_pcie_gart_disable(rdev);
2248         /* unpin shaders bo */
2249         if (rdev->r600_blit.shader_obj) {
2250                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2251                 if (!r) {
2252                         radeon_bo_unpin(rdev->r600_blit.shader_obj);
2253                         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2254                 }
2255         }
2256         return 0;
2257 }
2258
2259 /* Plan is to move initialization in that function and use
2260  * helper function so that radeon_device_init pretty much
2261  * do nothing more than calling asic specific function. This
2262  * should also allow to remove a bunch of callback function
2263  * like vram_info.
2264  */
2265 int r600_init(struct radeon_device *rdev)
2266 {
2267         int r;
2268
2269         r = radeon_dummy_page_init(rdev);
2270         if (r)
2271                 return r;
2272         if (r600_debugfs_mc_info_init(rdev)) {
2273                 DRM_ERROR("Failed to register debugfs file for mc !\n");
2274         }
2275         /* This don't do much */
2276         r = radeon_gem_init(rdev);
2277         if (r)
2278                 return r;
2279         /* Read BIOS */
2280         if (!radeon_get_bios(rdev)) {
2281                 if (ASIC_IS_AVIVO(rdev))
2282                         return -EINVAL;
2283         }
2284         /* Must be an ATOMBIOS */
2285         if (!rdev->is_atom_bios) {
2286                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2287                 return -EINVAL;
2288         }
2289         r = radeon_atombios_init(rdev);
2290         if (r)
2291                 return r;
2292         /* Post card if necessary */
2293         if (!r600_card_posted(rdev)) {
2294                 if (!rdev->bios) {
2295                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2296                         return -EINVAL;
2297                 }
2298                 DRM_INFO("GPU not posted. posting now...\n");
2299                 atom_asic_init(rdev->mode_info.atom_context);
2300         }
2301         /* Initialize scratch registers */
2302         r600_scratch_init(rdev);
2303         /* Initialize surface registers */
2304         radeon_surface_init(rdev);
2305         /* Initialize clocks */
2306         radeon_get_clock_info(rdev->ddev);
2307         r = radeon_clocks_init(rdev);
2308         if (r)
2309                 return r;
2310         /* Initialize power management */
2311         radeon_pm_init(rdev);
2312         /* Fence driver */
2313         r = radeon_fence_driver_init(rdev);
2314         if (r)
2315                 return r;
2316         if (rdev->flags & RADEON_IS_AGP) {
2317                 r = radeon_agp_init(rdev);
2318                 if (r)
2319                         radeon_agp_disable(rdev);
2320         }
2321         r = r600_mc_init(rdev);
2322         if (r)
2323                 return r;
2324         /* Memory manager */
2325         r = radeon_bo_init(rdev);
2326         if (r)
2327                 return r;
2328
2329         r = radeon_irq_kms_init(rdev);
2330         if (r)
2331                 return r;
2332
2333         rdev->cp.ring_obj = NULL;
2334         r600_ring_init(rdev, 1024 * 1024);
2335
2336         rdev->ih.ring_obj = NULL;
2337         r600_ih_ring_init(rdev, 64 * 1024);
2338
2339         r = r600_pcie_gart_init(rdev);
2340         if (r)
2341                 return r;
2342
2343         rdev->accel_working = true;
2344         r = r600_startup(rdev);
2345         if (r) {
2346                 dev_err(rdev->dev, "disabling GPU acceleration\n");
2347                 r600_cp_fini(rdev);
2348                 r600_wb_fini(rdev);
2349                 r600_irq_fini(rdev);
2350                 radeon_irq_kms_fini(rdev);
2351                 r600_pcie_gart_fini(rdev);
2352                 rdev->accel_working = false;
2353         }
2354         if (rdev->accel_working) {
2355                 r = radeon_ib_pool_init(rdev);
2356                 if (r) {
2357                         dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2358                         rdev->accel_working = false;
2359                 } else {
2360                         r = r600_ib_test(rdev);
2361                         if (r) {
2362                                 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2363                                 rdev->accel_working = false;
2364                         }
2365                 }
2366         }
2367
2368         r = r600_audio_init(rdev);
2369         if (r)
2370                 return r; /* TODO error handling */
2371         return 0;
2372 }
2373
2374 void r600_fini(struct radeon_device *rdev)
2375 {
2376         radeon_pm_fini(rdev);
2377         r600_audio_fini(rdev);
2378         r600_blit_fini(rdev);
2379         r600_cp_fini(rdev);
2380         r600_wb_fini(rdev);
2381         r600_irq_fini(rdev);
2382         radeon_irq_kms_fini(rdev);
2383         r600_pcie_gart_fini(rdev);
2384         radeon_agp_fini(rdev);
2385         radeon_gem_fini(rdev);
2386         radeon_fence_driver_fini(rdev);
2387         radeon_clocks_fini(rdev);
2388         radeon_bo_fini(rdev);
2389         radeon_atombios_fini(rdev);
2390         kfree(rdev->bios);
2391         rdev->bios = NULL;
2392         radeon_dummy_page_fini(rdev);
2393 }
2394
2395
2396 /*
2397  * CS stuff
2398  */
2399 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2400 {
2401         /* FIXME: implement */
2402         radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2403         radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
2404         radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
2405         radeon_ring_write(rdev, ib->length_dw);
2406 }
2407
2408 int r600_ib_test(struct radeon_device *rdev)
2409 {
2410         struct radeon_ib *ib;
2411         uint32_t scratch;
2412         uint32_t tmp = 0;
2413         unsigned i;
2414         int r;
2415
2416         r = radeon_scratch_get(rdev, &scratch);
2417         if (r) {
2418                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2419                 return r;
2420         }
2421         WREG32(scratch, 0xCAFEDEAD);
2422         r = radeon_ib_get(rdev, &ib);
2423         if (r) {
2424                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2425                 return r;
2426         }
2427         ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2428         ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2429         ib->ptr[2] = 0xDEADBEEF;
2430         ib->ptr[3] = PACKET2(0);
2431         ib->ptr[4] = PACKET2(0);
2432         ib->ptr[5] = PACKET2(0);
2433         ib->ptr[6] = PACKET2(0);
2434         ib->ptr[7] = PACKET2(0);
2435         ib->ptr[8] = PACKET2(0);
2436         ib->ptr[9] = PACKET2(0);
2437         ib->ptr[10] = PACKET2(0);
2438         ib->ptr[11] = PACKET2(0);
2439         ib->ptr[12] = PACKET2(0);
2440         ib->ptr[13] = PACKET2(0);
2441         ib->ptr[14] = PACKET2(0);
2442         ib->ptr[15] = PACKET2(0);
2443         ib->length_dw = 16;
2444         r = radeon_ib_schedule(rdev, ib);
2445         if (r) {
2446                 radeon_scratch_free(rdev, scratch);
2447                 radeon_ib_free(rdev, &ib);
2448                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2449                 return r;
2450         }
2451         r = radeon_fence_wait(ib->fence, false);
2452         if (r) {
2453                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2454                 return r;
2455         }
2456         for (i = 0; i < rdev->usec_timeout; i++) {
2457                 tmp = RREG32(scratch);
2458                 if (tmp == 0xDEADBEEF)
2459                         break;
2460                 DRM_UDELAY(1);
2461         }
2462         if (i < rdev->usec_timeout) {
2463                 DRM_INFO("ib test succeeded in %u usecs\n", i);
2464         } else {
2465                 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
2466                           scratch, tmp);
2467                 r = -EINVAL;
2468         }
2469         radeon_scratch_free(rdev, scratch);
2470         radeon_ib_free(rdev, &ib);
2471         return r;
2472 }
2473
2474 /*
2475  * Interrupts
2476  *
2477  * Interrupts use a ring buffer on r6xx/r7xx hardware.  It works pretty
2478  * the same as the CP ring buffer, but in reverse.  Rather than the CPU
2479  * writing to the ring and the GPU consuming, the GPU writes to the ring
2480  * and host consumes.  As the host irq handler processes interrupts, it
2481  * increments the rptr.  When the rptr catches up with the wptr, all the
2482  * current interrupts have been processed.
2483  */
2484
2485 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2486 {
2487         u32 rb_bufsz;
2488
2489         /* Align ring size */
2490         rb_bufsz = drm_order(ring_size / 4);
2491         ring_size = (1 << rb_bufsz) * 4;
2492         rdev->ih.ring_size = ring_size;
2493         rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2494         rdev->ih.rptr = 0;
2495 }
2496
2497 static int r600_ih_ring_alloc(struct radeon_device *rdev)
2498 {
2499         int r;
2500
2501         /* Allocate ring buffer */
2502         if (rdev->ih.ring_obj == NULL) {
2503                 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size,
2504                                      true,
2505                                      RADEON_GEM_DOMAIN_GTT,
2506                                      &rdev->ih.ring_obj);
2507                 if (r) {
2508                         DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2509                         return r;
2510                 }
2511                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2512                 if (unlikely(r != 0))
2513                         return r;
2514                 r = radeon_bo_pin(rdev->ih.ring_obj,
2515                                   RADEON_GEM_DOMAIN_GTT,
2516                                   &rdev->ih.gpu_addr);
2517                 if (r) {
2518                         radeon_bo_unreserve(rdev->ih.ring_obj);
2519                         DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2520                         return r;
2521                 }
2522                 r = radeon_bo_kmap(rdev->ih.ring_obj,
2523                                    (void **)&rdev->ih.ring);
2524                 radeon_bo_unreserve(rdev->ih.ring_obj);
2525                 if (r) {
2526                         DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2527                         return r;
2528                 }
2529         }
2530         return 0;
2531 }
2532
2533 static void r600_ih_ring_fini(struct radeon_device *rdev)
2534 {
2535         int r;
2536         if (rdev->ih.ring_obj) {
2537                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2538                 if (likely(r == 0)) {
2539                         radeon_bo_kunmap(rdev->ih.ring_obj);
2540                         radeon_bo_unpin(rdev->ih.ring_obj);
2541                         radeon_bo_unreserve(rdev->ih.ring_obj);
2542                 }
2543                 radeon_bo_unref(&rdev->ih.ring_obj);
2544                 rdev->ih.ring = NULL;
2545                 rdev->ih.ring_obj = NULL;
2546         }
2547 }
2548
2549 void r600_rlc_stop(struct radeon_device *rdev)
2550 {
2551
2552         if ((rdev->family >= CHIP_RV770) &&
2553             (rdev->family <= CHIP_RV740)) {
2554                 /* r7xx asics need to soft reset RLC before halting */
2555                 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2556                 RREG32(SRBM_SOFT_RESET);
2557                 udelay(15000);
2558                 WREG32(SRBM_SOFT_RESET, 0);
2559                 RREG32(SRBM_SOFT_RESET);
2560         }
2561
2562         WREG32(RLC_CNTL, 0);
2563 }
2564
2565 static void r600_rlc_start(struct radeon_device *rdev)
2566 {
2567         WREG32(RLC_CNTL, RLC_ENABLE);
2568 }
2569
2570 static int r600_rlc_init(struct radeon_device *rdev)
2571 {
2572         u32 i;
2573         const __be32 *fw_data;
2574
2575         if (!rdev->rlc_fw)
2576                 return -EINVAL;
2577
2578         r600_rlc_stop(rdev);
2579
2580         WREG32(RLC_HB_BASE, 0);
2581         WREG32(RLC_HB_CNTL, 0);
2582         WREG32(RLC_HB_RPTR, 0);
2583         WREG32(RLC_HB_WPTR, 0);
2584         WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2585         WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2586         WREG32(RLC_MC_CNTL, 0);
2587         WREG32(RLC_UCODE_CNTL, 0);
2588
2589         fw_data = (const __be32 *)rdev->rlc_fw->data;
2590         if (rdev->family >= CHIP_CEDAR) {
2591                 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
2592                         WREG32(RLC_UCODE_ADDR, i);
2593                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2594                 }
2595         } else if (rdev->family >= CHIP_RV770) {
2596                 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2597                         WREG32(RLC_UCODE_ADDR, i);
2598                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2599                 }
2600         } else {
2601                 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2602                         WREG32(RLC_UCODE_ADDR, i);
2603                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2604                 }
2605         }
2606         WREG32(RLC_UCODE_ADDR, 0);
2607
2608         r600_rlc_start(rdev);
2609
2610         return 0;
2611 }
2612
2613 static void r600_enable_interrupts(struct radeon_device *rdev)
2614 {
2615         u32 ih_cntl = RREG32(IH_CNTL);
2616         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2617
2618         ih_cntl |= ENABLE_INTR;
2619         ih_rb_cntl |= IH_RB_ENABLE;
2620         WREG32(IH_CNTL, ih_cntl);
2621         WREG32(IH_RB_CNTL, ih_rb_cntl);
2622         rdev->ih.enabled = true;
2623 }
2624
2625 void r600_disable_interrupts(struct radeon_device *rdev)
2626 {
2627         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2628         u32 ih_cntl = RREG32(IH_CNTL);
2629
2630         ih_rb_cntl &= ~IH_RB_ENABLE;
2631         ih_cntl &= ~ENABLE_INTR;
2632         WREG32(IH_RB_CNTL, ih_rb_cntl);
2633         WREG32(IH_CNTL, ih_cntl);
2634         /* set rptr, wptr to 0 */
2635         WREG32(IH_RB_RPTR, 0);
2636         WREG32(IH_RB_WPTR, 0);
2637         rdev->ih.enabled = false;
2638         rdev->ih.wptr = 0;
2639         rdev->ih.rptr = 0;
2640 }
2641
2642 static void r600_disable_interrupt_state(struct radeon_device *rdev)
2643 {
2644         u32 tmp;
2645
2646         WREG32(CP_INT_CNTL, 0);
2647         WREG32(GRBM_INT_CNTL, 0);
2648         WREG32(DxMODE_INT_MASK, 0);
2649         if (ASIC_IS_DCE3(rdev)) {
2650                 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2651                 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2652                 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2653                 WREG32(DC_HPD1_INT_CONTROL, tmp);
2654                 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2655                 WREG32(DC_HPD2_INT_CONTROL, tmp);
2656                 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2657                 WREG32(DC_HPD3_INT_CONTROL, tmp);
2658                 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2659                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2660                 if (ASIC_IS_DCE32(rdev)) {
2661                         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2662                         WREG32(DC_HPD5_INT_CONTROL, tmp);
2663                         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2664                         WREG32(DC_HPD6_INT_CONTROL, tmp);
2665                 }
2666         } else {
2667                 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2668                 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2669                 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2670                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
2671                 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2672                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
2673                 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2674                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
2675         }
2676 }
2677
2678 int r600_irq_init(struct radeon_device *rdev)
2679 {
2680         int ret = 0;
2681         int rb_bufsz;
2682         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2683
2684         /* allocate ring */
2685         ret = r600_ih_ring_alloc(rdev);
2686         if (ret)
2687                 return ret;
2688
2689         /* disable irqs */
2690         r600_disable_interrupts(rdev);
2691
2692         /* init rlc */
2693         ret = r600_rlc_init(rdev);
2694         if (ret) {
2695                 r600_ih_ring_fini(rdev);
2696                 return ret;
2697         }
2698
2699         /* setup interrupt control */
2700         /* set dummy read address to ring address */
2701         WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2702         interrupt_cntl = RREG32(INTERRUPT_CNTL);
2703         /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2704          * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2705          */
2706         interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
2707         /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2708         interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
2709         WREG32(INTERRUPT_CNTL, interrupt_cntl);
2710
2711         WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
2712         rb_bufsz = drm_order(rdev->ih.ring_size / 4);
2713
2714         ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
2715                       IH_WPTR_OVERFLOW_CLEAR |
2716                       (rb_bufsz << 1));
2717         /* WPTR writeback, not yet */
2718         /*ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;*/
2719         WREG32(IH_RB_WPTR_ADDR_LO, 0);
2720         WREG32(IH_RB_WPTR_ADDR_HI, 0);
2721
2722         WREG32(IH_RB_CNTL, ih_rb_cntl);
2723
2724         /* set rptr, wptr to 0 */
2725         WREG32(IH_RB_RPTR, 0);
2726         WREG32(IH_RB_WPTR, 0);
2727
2728         /* Default settings for IH_CNTL (disabled at first) */
2729         ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2730         /* RPTR_REARM only works if msi's are enabled */
2731         if (rdev->msi_enabled)
2732                 ih_cntl |= RPTR_REARM;
2733
2734 #ifdef __BIG_ENDIAN
2735         ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT);
2736 #endif
2737         WREG32(IH_CNTL, ih_cntl);
2738
2739         /* force the active interrupt state to all disabled */
2740         if (rdev->family >= CHIP_CEDAR)
2741                 evergreen_disable_interrupt_state(rdev);
2742         else
2743                 r600_disable_interrupt_state(rdev);
2744
2745         /* enable irqs */
2746         r600_enable_interrupts(rdev);
2747
2748         return ret;
2749 }
2750
2751 void r600_irq_suspend(struct radeon_device *rdev)
2752 {
2753         r600_irq_disable(rdev);
2754         r600_rlc_stop(rdev);
2755 }
2756
2757 void r600_irq_fini(struct radeon_device *rdev)
2758 {
2759         r600_irq_suspend(rdev);
2760         r600_ih_ring_fini(rdev);
2761 }
2762
2763 int r600_irq_set(struct radeon_device *rdev)
2764 {
2765         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2766         u32 mode_int = 0;
2767         u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
2768         u32 grbm_int_cntl = 0;
2769         u32 hdmi1, hdmi2;
2770
2771         if (!rdev->irq.installed) {
2772                 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
2773                 return -EINVAL;
2774         }
2775         /* don't enable anything if the ih is disabled */
2776         if (!rdev->ih.enabled) {
2777                 r600_disable_interrupts(rdev);
2778                 /* force the active interrupt state to all disabled */
2779                 r600_disable_interrupt_state(rdev);
2780                 return 0;
2781         }
2782
2783         hdmi1 = RREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
2784         if (ASIC_IS_DCE3(rdev)) {
2785                 hdmi2 = RREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
2786                 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2787                 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2788                 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2789                 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2790                 if (ASIC_IS_DCE32(rdev)) {
2791                         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2792                         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2793                 }
2794         } else {
2795                 hdmi2 = RREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
2796                 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2797                 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2798                 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2799         }
2800
2801         if (rdev->irq.sw_int) {
2802                 DRM_DEBUG("r600_irq_set: sw int\n");
2803                 cp_int_cntl |= RB_INT_ENABLE;
2804         }
2805         if (rdev->irq.crtc_vblank_int[0]) {
2806                 DRM_DEBUG("r600_irq_set: vblank 0\n");
2807                 mode_int |= D1MODE_VBLANK_INT_MASK;
2808         }
2809         if (rdev->irq.crtc_vblank_int[1]) {
2810                 DRM_DEBUG("r600_irq_set: vblank 1\n");
2811                 mode_int |= D2MODE_VBLANK_INT_MASK;
2812         }
2813         if (rdev->irq.hpd[0]) {
2814                 DRM_DEBUG("r600_irq_set: hpd 1\n");
2815                 hpd1 |= DC_HPDx_INT_EN;
2816         }
2817         if (rdev->irq.hpd[1]) {
2818                 DRM_DEBUG("r600_irq_set: hpd 2\n");
2819                 hpd2 |= DC_HPDx_INT_EN;
2820         }
2821         if (rdev->irq.hpd[2]) {
2822                 DRM_DEBUG("r600_irq_set: hpd 3\n");
2823                 hpd3 |= DC_HPDx_INT_EN;
2824         }
2825         if (rdev->irq.hpd[3]) {
2826                 DRM_DEBUG("r600_irq_set: hpd 4\n");
2827                 hpd4 |= DC_HPDx_INT_EN;
2828         }
2829         if (rdev->irq.hpd[4]) {
2830                 DRM_DEBUG("r600_irq_set: hpd 5\n");
2831                 hpd5 |= DC_HPDx_INT_EN;
2832         }
2833         if (rdev->irq.hpd[5]) {
2834                 DRM_DEBUG("r600_irq_set: hpd 6\n");
2835                 hpd6 |= DC_HPDx_INT_EN;
2836         }
2837         if (rdev->irq.hdmi[0]) {
2838                 DRM_DEBUG("r600_irq_set: hdmi 1\n");
2839                 hdmi1 |= R600_HDMI_INT_EN;
2840         }
2841         if (rdev->irq.hdmi[1]) {
2842                 DRM_DEBUG("r600_irq_set: hdmi 2\n");
2843                 hdmi2 |= R600_HDMI_INT_EN;
2844         }
2845         if (rdev->irq.gui_idle) {
2846                 DRM_DEBUG("gui idle\n");
2847                 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
2848         }
2849
2850         WREG32(CP_INT_CNTL, cp_int_cntl);
2851         WREG32(DxMODE_INT_MASK, mode_int);
2852         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
2853         WREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, hdmi1);
2854         if (ASIC_IS_DCE3(rdev)) {
2855                 WREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, hdmi2);
2856                 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2857                 WREG32(DC_HPD2_INT_CONTROL, hpd2);
2858                 WREG32(DC_HPD3_INT_CONTROL, hpd3);
2859                 WREG32(DC_HPD4_INT_CONTROL, hpd4);
2860                 if (ASIC_IS_DCE32(rdev)) {
2861                         WREG32(DC_HPD5_INT_CONTROL, hpd5);
2862                         WREG32(DC_HPD6_INT_CONTROL, hpd6);
2863                 }
2864         } else {
2865                 WREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, hdmi2);
2866                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
2867                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
2868                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
2869         }
2870
2871         return 0;
2872 }
2873
2874 static inline void r600_irq_ack(struct radeon_device *rdev,
2875                                 u32 *disp_int,
2876                                 u32 *disp_int_cont,
2877                                 u32 *disp_int_cont2)
2878 {
2879         u32 tmp;
2880
2881         if (ASIC_IS_DCE3(rdev)) {
2882                 *disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
2883                 *disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
2884                 *disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
2885         } else {
2886                 *disp_int = RREG32(DISP_INTERRUPT_STATUS);
2887                 *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2888                 *disp_int_cont2 = 0;
2889         }
2890
2891         if (*disp_int & LB_D1_VBLANK_INTERRUPT)
2892                 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
2893         if (*disp_int & LB_D1_VLINE_INTERRUPT)
2894                 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
2895         if (*disp_int & LB_D2_VBLANK_INTERRUPT)
2896                 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
2897         if (*disp_int & LB_D2_VLINE_INTERRUPT)
2898                 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
2899         if (*disp_int & DC_HPD1_INTERRUPT) {
2900                 if (ASIC_IS_DCE3(rdev)) {
2901                         tmp = RREG32(DC_HPD1_INT_CONTROL);
2902                         tmp |= DC_HPDx_INT_ACK;
2903                         WREG32(DC_HPD1_INT_CONTROL, tmp);
2904                 } else {
2905                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
2906                         tmp |= DC_HPDx_INT_ACK;
2907                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
2908                 }
2909         }
2910         if (*disp_int & DC_HPD2_INTERRUPT) {
2911                 if (ASIC_IS_DCE3(rdev)) {
2912                         tmp = RREG32(DC_HPD2_INT_CONTROL);
2913                         tmp |= DC_HPDx_INT_ACK;
2914                         WREG32(DC_HPD2_INT_CONTROL, tmp);
2915                 } else {
2916                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
2917                         tmp |= DC_HPDx_INT_ACK;
2918                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
2919                 }
2920         }
2921         if (*disp_int_cont & DC_HPD3_INTERRUPT) {
2922                 if (ASIC_IS_DCE3(rdev)) {
2923                         tmp = RREG32(DC_HPD3_INT_CONTROL);
2924                         tmp |= DC_HPDx_INT_ACK;
2925                         WREG32(DC_HPD3_INT_CONTROL, tmp);
2926                 } else {
2927                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
2928                         tmp |= DC_HPDx_INT_ACK;
2929                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
2930                 }
2931         }
2932         if (*disp_int_cont & DC_HPD4_INTERRUPT) {
2933                 tmp = RREG32(DC_HPD4_INT_CONTROL);
2934                 tmp |= DC_HPDx_INT_ACK;
2935                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2936         }
2937         if (ASIC_IS_DCE32(rdev)) {
2938                 if (*disp_int_cont2 & DC_HPD5_INTERRUPT) {
2939                         tmp = RREG32(DC_HPD5_INT_CONTROL);
2940                         tmp |= DC_HPDx_INT_ACK;
2941                         WREG32(DC_HPD5_INT_CONTROL, tmp);
2942                 }
2943                 if (*disp_int_cont2 & DC_HPD6_INTERRUPT) {
2944                         tmp = RREG32(DC_HPD5_INT_CONTROL);
2945                         tmp |= DC_HPDx_INT_ACK;
2946                         WREG32(DC_HPD6_INT_CONTROL, tmp);
2947                 }
2948         }
2949         if (RREG32(R600_HDMI_BLOCK1 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
2950                 WREG32_P(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
2951         }
2952         if (ASIC_IS_DCE3(rdev)) {
2953                 if (RREG32(R600_HDMI_BLOCK3 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
2954                         WREG32_P(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
2955                 }
2956         } else {
2957                 if (RREG32(R600_HDMI_BLOCK2 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
2958                         WREG32_P(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
2959                 }
2960         }
2961 }
2962
2963 void r600_irq_disable(struct radeon_device *rdev)
2964 {
2965         u32 disp_int, disp_int_cont, disp_int_cont2;
2966
2967         r600_disable_interrupts(rdev);
2968         /* Wait and acknowledge irq */
2969         mdelay(1);
2970         r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
2971         r600_disable_interrupt_state(rdev);
2972 }
2973
2974 static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
2975 {
2976         u32 wptr, tmp;
2977
2978         /* XXX use writeback */
2979         wptr = RREG32(IH_RB_WPTR);
2980
2981         if (wptr & RB_OVERFLOW) {
2982                 /* When a ring buffer overflow happen start parsing interrupt
2983                  * from the last not overwritten vector (wptr + 16). Hopefully
2984                  * this should allow us to catchup.
2985                  */
2986                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2987                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2988                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2989                 tmp = RREG32(IH_RB_CNTL);
2990                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2991                 WREG32(IH_RB_CNTL, tmp);
2992         }
2993         return (wptr & rdev->ih.ptr_mask);
2994 }
2995
2996 /*        r600 IV Ring
2997  * Each IV ring entry is 128 bits:
2998  * [7:0]    - interrupt source id
2999  * [31:8]   - reserved
3000  * [59:32]  - interrupt source data
3001  * [127:60]  - reserved
3002  *
3003  * The basic interrupt vector entries
3004  * are decoded as follows:
3005  * src_id  src_data  description
3006  *      1         0  D1 Vblank
3007  *      1         1  D1 Vline
3008  *      5         0  D2 Vblank
3009  *      5         1  D2 Vline
3010  *     19         0  FP Hot plug detection A
3011  *     19         1  FP Hot plug detection B
3012  *     19         2  DAC A auto-detection
3013  *     19         3  DAC B auto-detection
3014  *     21         4  HDMI block A
3015  *     21         5  HDMI block B
3016  *    176         -  CP_INT RB
3017  *    177         -  CP_INT IB1
3018  *    178         -  CP_INT IB2
3019  *    181         -  EOP Interrupt
3020  *    233         -  GUI Idle
3021  *
3022  * Note, these are based on r600 and may need to be
3023  * adjusted or added to on newer asics
3024  */
3025
3026 int r600_irq_process(struct radeon_device *rdev)
3027 {
3028         u32 wptr = r600_get_ih_wptr(rdev);
3029         u32 rptr = rdev->ih.rptr;
3030         u32 src_id, src_data;
3031         u32 ring_index, disp_int, disp_int_cont, disp_int_cont2;
3032         unsigned long flags;
3033         bool queue_hotplug = false;
3034
3035         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3036         if (!rdev->ih.enabled)
3037                 return IRQ_NONE;
3038
3039         spin_lock_irqsave(&rdev->ih.lock, flags);
3040
3041         if (rptr == wptr) {
3042                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3043                 return IRQ_NONE;
3044         }
3045         if (rdev->shutdown) {
3046                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3047                 return IRQ_NONE;
3048         }
3049
3050 restart_ih:
3051         /* display interrupts */
3052         r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
3053
3054         rdev->ih.wptr = wptr;
3055         while (rptr != wptr) {
3056                 /* wptr/rptr are in bytes! */
3057                 ring_index = rptr / 4;
3058                 src_id =  rdev->ih.ring[ring_index] & 0xff;
3059                 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
3060
3061                 switch (src_id) {
3062                 case 1: /* D1 vblank/vline */
3063                         switch (src_data) {
3064                         case 0: /* D1 vblank */
3065                                 if (disp_int & LB_D1_VBLANK_INTERRUPT) {
3066                                         drm_handle_vblank(rdev->ddev, 0);
3067                                         rdev->pm.vblank_sync = true;
3068                                         wake_up(&rdev->irq.vblank_queue);
3069                                         disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3070                                         DRM_DEBUG("IH: D1 vblank\n");
3071                                 }
3072                                 break;
3073                         case 1: /* D1 vline */
3074                                 if (disp_int & LB_D1_VLINE_INTERRUPT) {
3075                                         disp_int &= ~LB_D1_VLINE_INTERRUPT;
3076                                         DRM_DEBUG("IH: D1 vline\n");
3077                                 }
3078                                 break;
3079                         default:
3080                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3081                                 break;
3082                         }
3083                         break;
3084                 case 5: /* D2 vblank/vline */
3085                         switch (src_data) {
3086                         case 0: /* D2 vblank */
3087                                 if (disp_int & LB_D2_VBLANK_INTERRUPT) {
3088                                         drm_handle_vblank(rdev->ddev, 1);
3089                                         rdev->pm.vblank_sync = true;
3090                                         wake_up(&rdev->irq.vblank_queue);
3091                                         disp_int &= ~LB_D2_VBLANK_INTERRUPT;
3092                                         DRM_DEBUG("IH: D2 vblank\n");
3093                                 }
3094                                 break;
3095                         case 1: /* D1 vline */
3096                                 if (disp_int & LB_D2_VLINE_INTERRUPT) {
3097                                         disp_int &= ~LB_D2_VLINE_INTERRUPT;
3098                                         DRM_DEBUG("IH: D2 vline\n");
3099                                 }
3100                                 break;
3101                         default:
3102                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3103                                 break;
3104                         }
3105                         break;
3106                 case 19: /* HPD/DAC hotplug */
3107                         switch (src_data) {
3108                         case 0:
3109                                 if (disp_int & DC_HPD1_INTERRUPT) {
3110                                         disp_int &= ~DC_HPD1_INTERRUPT;
3111                                         queue_hotplug = true;
3112                                         DRM_DEBUG("IH: HPD1\n");
3113                                 }
3114                                 break;
3115                         case 1:
3116                                 if (disp_int & DC_HPD2_INTERRUPT) {
3117                                         disp_int &= ~DC_HPD2_INTERRUPT;
3118                                         queue_hotplug = true;
3119                                         DRM_DEBUG("IH: HPD2\n");
3120                                 }
3121                                 break;
3122                         case 4:
3123                                 if (disp_int_cont & DC_HPD3_INTERRUPT) {
3124                                         disp_int_cont &= ~DC_HPD3_INTERRUPT;
3125                                         queue_hotplug = true;
3126                                         DRM_DEBUG("IH: HPD3\n");
3127                                 }
3128                                 break;
3129                         case 5:
3130                                 if (disp_int_cont & DC_HPD4_INTERRUPT) {
3131                                         disp_int_cont &= ~DC_HPD4_INTERRUPT;
3132                                         queue_hotplug = true;
3133                                         DRM_DEBUG("IH: HPD4\n");
3134                                 }
3135                                 break;
3136                         case 10:
3137                                 if (disp_int_cont2 & DC_HPD5_INTERRUPT) {
3138                                         disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
3139                                         queue_hotplug = true;
3140                                         DRM_DEBUG("IH: HPD5\n");
3141                                 }
3142                                 break;
3143                         case 12:
3144                                 if (disp_int_cont2 & DC_HPD6_INTERRUPT) {
3145                                         disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
3146                                         queue_hotplug = true;
3147                                         DRM_DEBUG("IH: HPD6\n");
3148                                 }
3149                                 break;
3150                         default:
3151                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3152                                 break;
3153                         }
3154                         break;
3155                 case 21: /* HDMI */
3156                         DRM_DEBUG("IH: HDMI: 0x%x\n", src_data);
3157                         r600_audio_schedule_polling(rdev);
3158                         break;
3159                 case 176: /* CP_INT in ring buffer */
3160                 case 177: /* CP_INT in IB1 */
3161                 case 178: /* CP_INT in IB2 */
3162                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3163                         radeon_fence_process(rdev);
3164                         break;
3165                 case 181: /* CP EOP event */
3166                         DRM_DEBUG("IH: CP EOP\n");
3167                         break;
3168                 case 233: /* GUI IDLE */
3169                         DRM_DEBUG("IH: CP EOP\n");
3170                         rdev->pm.gui_idle = true;
3171                         wake_up(&rdev->irq.idle_queue);
3172                         break;
3173                 default:
3174                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3175                         break;
3176                 }
3177
3178                 /* wptr/rptr are in bytes! */
3179                 rptr += 16;
3180                 rptr &= rdev->ih.ptr_mask;
3181         }
3182         /* make sure wptr hasn't changed while processing */
3183         wptr = r600_get_ih_wptr(rdev);
3184         if (wptr != rdev->ih.wptr)
3185                 goto restart_ih;
3186         if (queue_hotplug)
3187                 queue_work(rdev->wq, &rdev->hotplug_work);
3188         rdev->ih.rptr = rptr;
3189         WREG32(IH_RB_RPTR, rdev->ih.rptr);
3190         spin_unlock_irqrestore(&rdev->ih.lock, flags);
3191         return IRQ_HANDLED;
3192 }
3193
3194 /*
3195  * Debugfs info
3196  */
3197 #if defined(CONFIG_DEBUG_FS)
3198
3199 static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
3200 {
3201         struct drm_info_node *node = (struct drm_info_node *) m->private;
3202         struct drm_device *dev = node->minor->dev;
3203         struct radeon_device *rdev = dev->dev_private;
3204         unsigned count, i, j;
3205
3206         radeon_ring_free_size(rdev);
3207         count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
3208         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
3209         seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
3210         seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
3211         seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
3212         seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
3213         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
3214         seq_printf(m, "%u dwords in ring\n", count);
3215         i = rdev->cp.rptr;
3216         for (j = 0; j <= count; j++) {
3217                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
3218                 i = (i + 1) & rdev->cp.ptr_mask;
3219         }
3220         return 0;
3221 }
3222
3223 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
3224 {
3225         struct drm_info_node *node = (struct drm_info_node *) m->private;
3226         struct drm_device *dev = node->minor->dev;
3227         struct radeon_device *rdev = dev->dev_private;
3228
3229         DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
3230         DREG32_SYS(m, rdev, VM_L2_STATUS);
3231         return 0;
3232 }
3233
3234 static struct drm_info_list r600_mc_info_list[] = {
3235         {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
3236         {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
3237 };
3238 #endif
3239
3240 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
3241 {
3242 #if defined(CONFIG_DEBUG_FS)
3243         return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
3244 #else
3245         return 0;
3246 #endif
3247 }
3248
3249 /**
3250  * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
3251  * rdev: radeon device structure
3252  * bo: buffer object struct which userspace is waiting for idle
3253  *
3254  * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
3255  * through ring buffer, this leads to corruption in rendering, see
3256  * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
3257  * directly perform HDP flush by writing register through MMIO.
3258  */
3259 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
3260 {
3261         WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
3262 }