SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/r420.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include "drmP.h"
  30 #include "radeon_reg.h"
  31 #include "radeon.h"
  32 #include "atom.h"
  33 #include "r100d.h"
  34 #include "r420d.h"
  35 #include "r420_reg_safe.h"
  36
  37 static void r420_set_reg_safe(struct radeon_device *rdev)
  38 {
  39         rdev->config.r300.reg_safe_bm = r420_reg_safe_bm;
  40         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm);
  41 }
  42
  43 void r420_pipes_init(struct radeon_device *rdev)
  44 {
  45         unsigned tmp;
  46         unsigned gb_pipe_select;
  47         unsigned num_pipes;
  48
  49         /* GA_ENHANCE workaround TCL deadlock issue */
  50         WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL |
  51                (1 << 2) | (1 << 3));
  52         /* add idle wait as per freedesktop.org bug 24041 */
  53         if (r100_gui_wait_for_idle(rdev)) {
  54                 printk(KERN_WARNING "Failed to wait GUI idle while "
  55                        "programming pipes. Bad things might happen.\n");
  56         }
  57         /* get max number of pipes */
  58         gb_pipe_select = RREG32(0x402C);
  59         num_pipes = ((gb_pipe_select >> 12) & 3) + 1;
  60         rdev->num_gb_pipes = num_pipes;
  61         tmp = 0;
  62         switch (num_pipes) {
  63         default:
  64                 /* force to 1 pipe */
  65                 num_pipes = 1;
  66         case 1:
  67                 tmp = (0 << 1);
  68                 break;
  69         case 2:
  70                 tmp = (3 << 1);
  71                 break;
  72         case 3:
  73                 tmp = (6 << 1);
  74                 break;
  75         case 4:
  76                 tmp = (7 << 1);
  77                 break;
  78         }
  79         WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1);
  80         /* Sub pixel 1/12 so we can have 4K rendering according to doc */
  81         tmp |= R300_TILE_SIZE_16 | R300_ENABLE_TILING;
  82         WREG32(R300_GB_TILE_CONFIG, tmp);
  83         if (r100_gui_wait_for_idle(rdev)) {
  84                 printk(KERN_WARNING "Failed to wait GUI idle while "
  85                        "programming pipes. Bad things might happen.\n");
  86         }
  87
  88         tmp = RREG32(R300_DST_PIPE_CONFIG);
  89         WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
  90
  91         WREG32(R300_RB2D_DSTCACHE_MODE,
  92                RREG32(R300_RB2D_DSTCACHE_MODE) |
  93                R300_DC_AUTOFLUSH_ENABLE |
  94                R300_DC_DC_DISABLE_IGNORE_PE);
  95
  96         if (r100_gui_wait_for_idle(rdev)) {
  97                 printk(KERN_WARNING "Failed to wait GUI idle while "
  98                        "programming pipes. Bad things might happen.\n");
  99         }
 100
 101         if (rdev->family == CHIP_RV530) {
 102                 tmp = RREG32(RV530_GB_PIPE_SELECT2);
 103                 if ((tmp & 3) == 3)
 104                         rdev->num_z_pipes = 2;
 105                 else
 106                         rdev->num_z_pipes = 1;
 107         } else
 108                 rdev->num_z_pipes = 1;
 109
 110         DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n",
 111                  rdev->num_gb_pipes, rdev->num_z_pipes);
 112 }
 113
 114 u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
 115 {
 116         u32 r;
 117
 118         WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));
 119         r = RREG32(R_0001FC_MC_IND_DATA);
 120         return r;
 121 }
 122
 123 void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
 124 {
 125         WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) |
 126                 S_0001F8_MC_IND_WR_EN(1));
 127         WREG32(R_0001FC_MC_IND_DATA, v);
 128 }
 129
 130 static void r420_debugfs(struct radeon_device *rdev)
 131 {
 132         if (r100_debugfs_rbbm_init(rdev)) {
 133                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
 134         }
 135         if (r420_debugfs_pipes_info_init(rdev)) {
 136                 DRM_ERROR("Failed to register debugfs file for pipes !\n");
 137         }
 138 }
 139
 140 static void r420_clock_resume(struct radeon_device *rdev)
 141 {
 142         u32 sclk_cntl;
 143
 144         if (radeon_dynclks != -1 && radeon_dynclks)
 145                 radeon_atom_set_clock_gating(rdev, 1);
 146         sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL);
 147         sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
 148         if (rdev->family == CHIP_R420)
 149                 sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1);
 150         WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl);
 151 }
 152
 153 static void r420_cp_errata_init(struct radeon_device *rdev)
 154 {
 155         /* RV410 and R420 can lock up if CP DMA to host memory happens
 156          * while the 2D engine is busy.
 157          *
 158          * The proper workaround is to queue a RESYNC at the beginning
 159          * of the CP init, apparently.
 160          */
 161         radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch);
 162         radeon_ring_lock(rdev, 8);
 163         radeon_ring_write(rdev, PACKET0(R300_CP_RESYNC_ADDR, 1));
 164         radeon_ring_write(rdev, rdev->config.r300.resync_scratch);
 165         radeon_ring_write(rdev, 0xDEADBEEF);
 166         radeon_ring_unlock_commit(rdev);
 167 }
 168
 169 static void r420_cp_errata_fini(struct radeon_device *rdev)
 170 {
 171         /* Catch the RESYNC we dispatched all the way back,
 172          * at the very beginning of the CP init.
 173          */
 174         radeon_ring_lock(rdev, 8);
 175         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
 176         radeon_ring_write(rdev, R300_RB3D_DC_FINISH);
 177         radeon_ring_unlock_commit(rdev);
 178         radeon_scratch_free(rdev, rdev->config.r300.resync_scratch);
 179 }
 180
 181 static int r420_startup(struct radeon_device *rdev)
 182 {
 183         int r;
 184
 185         /* set common regs */
 186         r100_set_common_regs(rdev);
 187         /* program mc */
 188         r300_mc_program(rdev);
 189         /* Resume clock */
 190         r420_clock_resume(rdev);
 191         /* Initialize GART (initialize after TTM so we can allocate
 192          * memory through TTM but finalize after TTM) */
 193         if (rdev->flags & RADEON_IS_PCIE) {
 194                 r = rv370_pcie_gart_enable(rdev);
 195                 if (r)
 196                         return r;
 197         }
 198         if (rdev->flags & RADEON_IS_PCI) {
 199                 r = r100_pci_gart_enable(rdev);
 200                 if (r)
 201                         return r;
 202         }
 203         r420_pipes_init(rdev);
 204         /* Enable IRQ */
 205         r100_irq_set(rdev);
 206         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
 207         /* 1M ring buffer */
 208         r = r100_cp_init(rdev, 1024 * 1024);
 209         if (r) {
 210                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
 211                 return r;
 212         }
 213         r420_cp_errata_init(rdev);
 214         r = r100_wb_init(rdev);
 215         if (r) {
 216                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
 217         }
 218         r = r100_ib_init(rdev);
 219         if (r) {
 220                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
 221                 return r;
 222         }
 223         return 0;
 224 }
 225
 226 int r420_resume(struct radeon_device *rdev)
 227 {
 228         /* Make sur GART are not working */
 229         if (rdev->flags & RADEON_IS_PCIE)
 230                 rv370_pcie_gart_disable(rdev);
 231         if (rdev->flags & RADEON_IS_PCI)
 232                 r100_pci_gart_disable(rdev);
 233         /* Resume clock before doing reset */
 234         r420_clock_resume(rdev);
 235         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 236         if (radeon_gpu_reset(rdev)) {
 237                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 238                         RREG32(R_000E40_RBBM_STATUS),
 239                         RREG32(R_0007C0_CP_STAT));
 240         }
 241         /* check if cards are posted or not */
 242         if (rdev->is_atom_bios) {
 243                 atom_asic_init(rdev->mode_info.atom_context);
 244         } else {
 245                 radeon_combios_asic_init(rdev->ddev);
 246         }
 247         /* Resume clock after posting */
 248         r420_clock_resume(rdev);
 249         /* Initialize surface registers */
 250         radeon_surface_init(rdev);
 251         return r420_startup(rdev);
 252 }
 253
 254 int r420_suspend(struct radeon_device *rdev)
 255 {
 256         r420_cp_errata_fini(rdev);
 257         r100_cp_disable(rdev);
 258         r100_wb_disable(rdev);
 259         r100_irq_disable(rdev);
 260         if (rdev->flags & RADEON_IS_PCIE)
 261                 rv370_pcie_gart_disable(rdev);
 262         if (rdev->flags & RADEON_IS_PCI)
 263                 r100_pci_gart_disable(rdev);
 264         return 0;
 265 }
 266
 267 void r420_fini(struct radeon_device *rdev)
 268 {
 269         r100_cp_fini(rdev);
 270         r100_wb_fini(rdev);
 271         r100_ib_fini(rdev);
 272         radeon_gem_fini(rdev);
 273         if (rdev->flags & RADEON_IS_PCIE)
 274                 rv370_pcie_gart_fini(rdev);
 275         if (rdev->flags & RADEON_IS_PCI)
 276                 r100_pci_gart_fini(rdev);
 277         radeon_agp_fini(rdev);
 278         radeon_irq_kms_fini(rdev);
 279         radeon_fence_driver_fini(rdev);
 280         radeon_bo_fini(rdev);
 281         if (rdev->is_atom_bios) {
 282                 radeon_atombios_fini(rdev);
 283         } else {
 284                 radeon_combios_fini(rdev);
 285         }
 286         kfree(rdev->bios);
 287         rdev->bios = NULL;
 288 }
 289
 290 int r420_init(struct radeon_device *rdev)
 291 {
 292         int r;
 293
 294         /* Initialize scratch registers */
 295         radeon_scratch_init(rdev);
 296         /* Initialize surface registers */
 297         radeon_surface_init(rdev);
 298         /* TODO: disable VGA need to use VGA request */
 299         /* BIOS*/
 300         if (!radeon_get_bios(rdev)) {
 301                 if (ASIC_IS_AVIVO(rdev))
 302                         return -EINVAL;
 303         }
 304         if (rdev->is_atom_bios) {
 305                 r = radeon_atombios_init(rdev);
 306                 if (r) {
 307                         return r;
 308                 }
 309         } else {
 310                 r = radeon_combios_init(rdev);
 311                 if (r) {
 312                         return r;
 313                 }
 314         }
 315         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 316         if (radeon_gpu_reset(rdev)) {
 317                 dev_warn(rdev->dev,
 318                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 319                         RREG32(R_000E40_RBBM_STATUS),
 320                         RREG32(R_0007C0_CP_STAT));
 321         }
 322         /* check if cards are posted or not */
 323         if (radeon_boot_test_post_card(rdev) == false)
 324                 return -EINVAL;
 325
 326         /* Initialize clocks */
 327         radeon_get_clock_info(rdev->ddev);
 328         /* Initialize power management */
 329         radeon_pm_init(rdev);
 330         /* initialize AGP */
 331         if (rdev->flags & RADEON_IS_AGP) {
 332                 r = radeon_agp_init(rdev);
 333                 if (r) {
 334                         radeon_agp_disable(rdev);
 335                 }
 336         }
 337         /* initialize memory controller */
 338         r300_mc_init(rdev);
 339         r420_debugfs(rdev);
 340         /* Fence driver */
 341         r = radeon_fence_driver_init(rdev);
 342         if (r) {
 343                 return r;
 344         }
 345         r = radeon_irq_kms_init(rdev);
 346         if (r) {
 347                 return r;
 348         }
 349         /* Memory manager */
 350         r = radeon_bo_init(rdev);
 351         if (r) {
 352                 return r;
 353         }
 354         if (rdev->family == CHIP_R420)
 355                 r100_enable_bm(rdev);
 356
 357         if (rdev->flags & RADEON_IS_PCIE) {
 358                 r = rv370_pcie_gart_init(rdev);
 359                 if (r)
 360                         return r;
 361         }
 362         if (rdev->flags & RADEON_IS_PCI) {
 363                 r = r100_pci_gart_init(rdev);
 364                 if (r)
 365                         return r;
 366         }
 367         r420_set_reg_safe(rdev);
 368         rdev->accel_working = true;
 369         r = r420_startup(rdev);
 370         if (r) {
 371                 /* Somethings want wront with the accel init stop accel */
 372                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
 373                 r100_cp_fini(rdev);
 374                 r100_wb_fini(rdev);
 375                 r100_ib_fini(rdev);
 376                 radeon_irq_kms_fini(rdev);
 377                 if (rdev->flags & RADEON_IS_PCIE)
 378                         rv370_pcie_gart_fini(rdev);
 379                 if (rdev->flags & RADEON_IS_PCI)
 380                         r100_pci_gart_fini(rdev);
 381                 radeon_agp_fini(rdev);
 382                 rdev->accel_working = false;
 383         }
 384         return 0;
 385 }
 386
 387 /*
 388  * Debugfs info
 389  */
 390 #if defined(CONFIG_DEBUG_FS)
 391 static int r420_debugfs_pipes_info(struct seq_file *m, void *data)
 392 {
 393         struct drm_info_node *node = (struct drm_info_node *) m->private;
 394         struct drm_device *dev = node->minor->dev;
 395         struct radeon_device *rdev = dev->dev_private;
 396         uint32_t tmp;
 397
 398         tmp = RREG32(R400_GB_PIPE_SELECT);
 399         seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
 400         tmp = RREG32(R300_GB_TILE_CONFIG);
 401         seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
 402         tmp = RREG32(R300_DST_PIPE_CONFIG);
 403         seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
 404         return 0;
 405 }
 406
 407 static struct drm_info_list r420_pipes_info_list[] = {
 408         {"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL},
 409 };
 410 #endif
 411
 412 int r420_debugfs_pipes_info_init(struct radeon_device *rdev)
 413 {
 414 #if defined(CONFIG_DEBUG_FS)
 415         return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1);
 416 #else
 417         return 0;
 418 #endif
 419 }