SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/r420.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include <linux/slab.h>
  30 #include "drmP.h"
  31 #include "radeon_reg.h"
  32 #include "radeon.h"
  33 #include "radeon_asic.h"
  34 #include "atom.h"
  35 #include "r100d.h"
  36 #include "r420d.h"
  37 #include "r420_reg_safe.h"
  38
  39 void r420_pm_init_profile(struct radeon_device *rdev)
  40 {
  41         /* default */
  42         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
  43         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
  44         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
  45         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
  46         /* low sh */
  47         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
  48         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
  49         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
  50         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
  51         /* high sh */
  52         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
  53         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
  54         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
  55         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
  56         /* low mh */
  57         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
  58         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
  59         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
  60         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
  61         /* high mh */
  62         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
  63         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
  64         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
  65         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
  66 }
  67
  68 static void r420_set_reg_safe(struct radeon_device *rdev)
  69 {
  70         rdev->config.r300.reg_safe_bm = r420_reg_safe_bm;
  71         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm);
  72 }
  73
  74 void r420_pipes_init(struct radeon_device *rdev)
  75 {
  76         unsigned tmp;
  77         unsigned gb_pipe_select;
  78         unsigned num_pipes;
  79
  80         /* GA_ENHANCE workaround TCL deadlock issue */
  81         WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL |
  82                (1 << 2) | (1 << 3));
  83         /* add idle wait as per freedesktop.org bug 24041 */
  84         if (r100_gui_wait_for_idle(rdev)) {
  85                 printk(KERN_WARNING "Failed to wait GUI idle while "
  86                        "programming pipes. Bad things might happen.\n");
  87         }
  88         /* get max number of pipes */
  89         gb_pipe_select = RREG32(0x402C);
  90         num_pipes = ((gb_pipe_select >> 12) & 3) + 1;
  91
  92         /* SE chips have 1 pipe */
  93         if ((rdev->pdev->device == 0x5e4c) ||
  94             (rdev->pdev->device == 0x5e4f))
  95                 num_pipes = 1;
  96
  97         rdev->num_gb_pipes = num_pipes;
  98         tmp = 0;
  99         switch (num_pipes) {
 100         default:
 101                 /* force to 1 pipe */
 102                 num_pipes = 1;
 103         case 1:
 104                 tmp = (0 << 1);
 105                 break;
 106         case 2:
 107                 tmp = (3 << 1);
 108                 break;
 109         case 3:
 110                 tmp = (6 << 1);
 111                 break;
 112         case 4:
 113                 tmp = (7 << 1);
 114                 break;
 115         }
 116         WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1);
 117         /* Sub pixel 1/12 so we can have 4K rendering according to doc */
 118         tmp |= R300_TILE_SIZE_16 | R300_ENABLE_TILING;
 119         WREG32(R300_GB_TILE_CONFIG, tmp);
 120         if (r100_gui_wait_for_idle(rdev)) {
 121                 printk(KERN_WARNING "Failed to wait GUI idle while "
 122                        "programming pipes. Bad things might happen.\n");
 123         }
 124
 125         tmp = RREG32(R300_DST_PIPE_CONFIG);
 126         WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
 127
 128         WREG32(R300_RB2D_DSTCACHE_MODE,
 129                RREG32(R300_RB2D_DSTCACHE_MODE) |
 130                R300_DC_AUTOFLUSH_ENABLE |
 131                R300_DC_DC_DISABLE_IGNORE_PE);
 132
 133         if (r100_gui_wait_for_idle(rdev)) {
 134                 printk(KERN_WARNING "Failed to wait GUI idle while "
 135                        "programming pipes. Bad things might happen.\n");
 136         }
 137
 138         if (rdev->family == CHIP_RV530) {
 139                 tmp = RREG32(RV530_GB_PIPE_SELECT2);
 140                 if ((tmp & 3) == 3)
 141                         rdev->num_z_pipes = 2;
 142                 else
 143                         rdev->num_z_pipes = 1;
 144         } else
 145                 rdev->num_z_pipes = 1;
 146
 147         DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n",
 148                  rdev->num_gb_pipes, rdev->num_z_pipes);
 149 }
 150
 151 u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
 152 {
 153         u32 r;
 154
 155         WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));
 156         r = RREG32(R_0001FC_MC_IND_DATA);
 157         return r;
 158 }
 159
 160 void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
 161 {
 162         WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) |
 163                 S_0001F8_MC_IND_WR_EN(1));
 164         WREG32(R_0001FC_MC_IND_DATA, v);
 165 }
 166
 167 static void r420_debugfs(struct radeon_device *rdev)
 168 {
 169         if (r100_debugfs_rbbm_init(rdev)) {
 170                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
 171         }
 172         if (r420_debugfs_pipes_info_init(rdev)) {
 173                 DRM_ERROR("Failed to register debugfs file for pipes !\n");
 174         }
 175 }
 176
 177 static void r420_clock_resume(struct radeon_device *rdev)
 178 {
 179         u32 sclk_cntl;
 180
 181         if (radeon_dynclks != -1 && radeon_dynclks)
 182                 radeon_atom_set_clock_gating(rdev, 1);
 183         sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL);
 184         sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
 185         if (rdev->family == CHIP_R420)
 186                 sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1);
 187         WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl);
 188 }
 189
 190 static void r420_cp_errata_init(struct radeon_device *rdev)
 191 {
 192         /* RV410 and R420 can lock up if CP DMA to host memory happens
 193          * while the 2D engine is busy.
 194          *
 195          * The proper workaround is to queue a RESYNC at the beginning
 196          * of the CP init, apparently.
 197          */
 198         radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch);
 199         radeon_ring_lock(rdev, 8);
 200         radeon_ring_write(rdev, PACKET0(R300_CP_RESYNC_ADDR, 1));
 201         radeon_ring_write(rdev, rdev->config.r300.resync_scratch);
 202         radeon_ring_write(rdev, 0xDEADBEEF);
 203         radeon_ring_unlock_commit(rdev);
 204 }
 205
 206 static void r420_cp_errata_fini(struct radeon_device *rdev)
 207 {
 208         /* Catch the RESYNC we dispatched all the way back,
 209          * at the very beginning of the CP init.
 210          */
 211         radeon_ring_lock(rdev, 8);
 212         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
 213         radeon_ring_write(rdev, R300_RB3D_DC_FINISH);
 214         radeon_ring_unlock_commit(rdev);
 215         radeon_scratch_free(rdev, rdev->config.r300.resync_scratch);
 216 }
 217
 218 static int r420_startup(struct radeon_device *rdev)
 219 {
 220         int r;
 221
 222         /* set common regs */
 223         r100_set_common_regs(rdev);
 224         /* program mc */
 225         r300_mc_program(rdev);
 226         /* Resume clock */
 227         r420_clock_resume(rdev);
 228         /* Initialize GART (initialize after TTM so we can allocate
 229          * memory through TTM but finalize after TTM) */
 230         if (rdev->flags & RADEON_IS_PCIE) {
 231                 r = rv370_pcie_gart_enable(rdev);
 232                 if (r)
 233                         return r;
 234         }
 235         if (rdev->flags & RADEON_IS_PCI) {
 236                 r = r100_pci_gart_enable(rdev);
 237                 if (r)
 238                         return r;
 239         }
 240         r420_pipes_init(rdev);
 241         /* Enable IRQ */
 242         r100_irq_set(rdev);
 243         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
 244         /* 1M ring buffer */
 245         r = r100_cp_init(rdev, 1024 * 1024);
 246         if (r) {
 247                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
 248                 return r;
 249         }
 250         r420_cp_errata_init(rdev);
 251         r = r100_wb_init(rdev);
 252         if (r) {
 253                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
 254         }
 255         r = r100_ib_init(rdev);
 256         if (r) {
 257                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
 258                 return r;
 259         }
 260         return 0;
 261 }
 262
 263 int r420_resume(struct radeon_device *rdev)
 264 {
 265         /* Make sur GART are not working */
 266         if (rdev->flags & RADEON_IS_PCIE)
 267                 rv370_pcie_gart_disable(rdev);
 268         if (rdev->flags & RADEON_IS_PCI)
 269                 r100_pci_gart_disable(rdev);
 270         /* Resume clock before doing reset */
 271         r420_clock_resume(rdev);
 272         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 273         if (radeon_asic_reset(rdev)) {
 274                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 275                         RREG32(R_000E40_RBBM_STATUS),
 276                         RREG32(R_0007C0_CP_STAT));
 277         }
 278         /* check if cards are posted or not */
 279         if (rdev->is_atom_bios) {
 280                 atom_asic_init(rdev->mode_info.atom_context);
 281         } else {
 282                 radeon_combios_asic_init(rdev->ddev);
 283         }
 284         /* Resume clock after posting */
 285         r420_clock_resume(rdev);
 286         /* Initialize surface registers */
 287         radeon_surface_init(rdev);
 288         return r420_startup(rdev);
 289 }
 290
 291 int r420_suspend(struct radeon_device *rdev)
 292 {
 293         r420_cp_errata_fini(rdev);
 294         r100_cp_disable(rdev);
 295         r100_wb_disable(rdev);
 296         r100_irq_disable(rdev);
 297         if (rdev->flags & RADEON_IS_PCIE)
 298                 rv370_pcie_gart_disable(rdev);
 299         if (rdev->flags & RADEON_IS_PCI)
 300                 r100_pci_gart_disable(rdev);
 301         return 0;
 302 }
 303
 304 void r420_fini(struct radeon_device *rdev)
 305 {
 306         r100_cp_fini(rdev);
 307         r100_wb_fini(rdev);
 308         r100_ib_fini(rdev);
 309         radeon_gem_fini(rdev);
 310         if (rdev->flags & RADEON_IS_PCIE)
 311                 rv370_pcie_gart_fini(rdev);
 312         if (rdev->flags & RADEON_IS_PCI)
 313                 r100_pci_gart_fini(rdev);
 314         radeon_agp_fini(rdev);
 315         radeon_irq_kms_fini(rdev);
 316         radeon_fence_driver_fini(rdev);
 317         radeon_bo_fini(rdev);
 318         if (rdev->is_atom_bios) {
 319                 radeon_atombios_fini(rdev);
 320         } else {
 321                 radeon_combios_fini(rdev);
 322         }
 323         kfree(rdev->bios);
 324         rdev->bios = NULL;
 325 }
 326
 327 int r420_init(struct radeon_device *rdev)
 328 {
 329         int r;
 330
 331         /* Initialize scratch registers */
 332         radeon_scratch_init(rdev);
 333         /* Initialize surface registers */
 334         radeon_surface_init(rdev);
 335         /* TODO: disable VGA need to use VGA request */
 336         /* BIOS*/
 337         if (!radeon_get_bios(rdev)) {
 338                 if (ASIC_IS_AVIVO(rdev))
 339                         return -EINVAL;
 340         }
 341         if (rdev->is_atom_bios) {
 342                 r = radeon_atombios_init(rdev);
 343                 if (r) {
 344                         return r;
 345                 }
 346         } else {
 347                 r = radeon_combios_init(rdev);
 348                 if (r) {
 349                         return r;
 350                 }
 351         }
 352         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 353         if (radeon_asic_reset(rdev)) {
 354                 dev_warn(rdev->dev,
 355                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 356                         RREG32(R_000E40_RBBM_STATUS),
 357                         RREG32(R_0007C0_CP_STAT));
 358         }
 359         /* check if cards are posted or not */
 360         if (radeon_boot_test_post_card(rdev) == false)
 361                 return -EINVAL;
 362
 363         /* Initialize clocks */
 364         radeon_get_clock_info(rdev->ddev);
 365         /* initialize AGP */
 366         if (rdev->flags & RADEON_IS_AGP) {
 367                 r = radeon_agp_init(rdev);
 368                 if (r) {
 369                         radeon_agp_disable(rdev);
 370                 }
 371         }
 372         /* initialize memory controller */
 373         r300_mc_init(rdev);
 374         r420_debugfs(rdev);
 375         /* Fence driver */
 376         r = radeon_fence_driver_init(rdev);
 377         if (r) {
 378                 return r;
 379         }
 380         r = radeon_irq_kms_init(rdev);
 381         if (r) {
 382                 return r;
 383         }
 384         /* Memory manager */
 385         r = radeon_bo_init(rdev);
 386         if (r) {
 387                 return r;
 388         }
 389         if (rdev->family == CHIP_R420)
 390                 r100_enable_bm(rdev);
 391
 392         if (rdev->flags & RADEON_IS_PCIE) {
 393                 r = rv370_pcie_gart_init(rdev);
 394                 if (r)
 395                         return r;
 396         }
 397         if (rdev->flags & RADEON_IS_PCI) {
 398                 r = r100_pci_gart_init(rdev);
 399                 if (r)
 400                         return r;
 401         }
 402         r420_set_reg_safe(rdev);
 403         rdev->accel_working = true;
 404         r = r420_startup(rdev);
 405         if (r) {
 406                 /* Somethings want wront with the accel init stop accel */
 407                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
 408                 r100_cp_fini(rdev);
 409                 r100_wb_fini(rdev);
 410                 r100_ib_fini(rdev);
 411                 radeon_irq_kms_fini(rdev);
 412                 if (rdev->flags & RADEON_IS_PCIE)
 413                         rv370_pcie_gart_fini(rdev);
 414                 if (rdev->flags & RADEON_IS_PCI)
 415                         r100_pci_gart_fini(rdev);
 416                 radeon_agp_fini(rdev);
 417                 rdev->accel_working = false;
 418         }
 419         return 0;
 420 }
 421
 422 /*
 423  * Debugfs info
 424  */
 425 #if defined(CONFIG_DEBUG_FS)
 426 static int r420_debugfs_pipes_info(struct seq_file *m, void *data)
 427 {
 428         struct drm_info_node *node = (struct drm_info_node *) m->private;
 429         struct drm_device *dev = node->minor->dev;
 430         struct radeon_device *rdev = dev->dev_private;
 431         uint32_t tmp;
 432
 433         tmp = RREG32(R400_GB_PIPE_SELECT);
 434         seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
 435         tmp = RREG32(R300_GB_TILE_CONFIG);
 436         seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
 437         tmp = RREG32(R300_DST_PIPE_CONFIG);
 438         seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
 439         return 0;
 440 }
 441
 442 static struct drm_info_list r420_pipes_info_list[] = {
 443         {"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL},
 444 };
 445 #endif
 446
 447 int r420_debugfs_pipes_info_init(struct radeon_device *rdev)
 448 {
 449 #if defined(CONFIG_DEBUG_FS)
 450         return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1);
 451 #else
 452         return 0;
 453 #endif
 454 }