SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/r420.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include "drmP.h"
  30 #include "radeon_reg.h"
  31 #include "radeon.h"
  32 #include "atom.h"
  33 #include "r100d.h"
  34 #include "r420d.h"
  35 #include "r420_reg_safe.h"
  36
  37 static void r420_set_reg_safe(struct radeon_device *rdev)
  38 {
  39         rdev->config.r300.reg_safe_bm = r420_reg_safe_bm;
  40         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm);
  41 }
  42
  43 int r420_mc_init(struct radeon_device *rdev)
  44 {
  45         int r;
  46
  47         /* Setup GPU memory space */
  48         rdev->mc.vram_location = 0xFFFFFFFFUL;
  49         rdev->mc.gtt_location = 0xFFFFFFFFUL;
  50         if (rdev->flags & RADEON_IS_AGP) {
  51                 r = radeon_agp_init(rdev);
  52                 if (r) {
  53                         radeon_agp_disable(rdev);
  54                 } else {
  55                         rdev->mc.gtt_location = rdev->mc.agp_base;
  56                 }
  57         }
  58         r = radeon_mc_setup(rdev);
  59         if (r) {
  60                 return r;
  61         }
  62         return 0;
  63 }
  64
  65 void r420_pipes_init(struct radeon_device *rdev)
  66 {
  67         unsigned tmp;
  68         unsigned gb_pipe_select;
  69         unsigned num_pipes;
  70
  71         /* GA_ENHANCE workaround TCL deadlock issue */
  72         WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL |
  73                (1 << 2) | (1 << 3));
  74         /* add idle wait as per freedesktop.org bug 24041 */
  75         if (r100_gui_wait_for_idle(rdev)) {
  76                 printk(KERN_WARNING "Failed to wait GUI idle while "
  77                        "programming pipes. Bad things might happen.\n");
  78         }
  79         /* get max number of pipes */
  80         gb_pipe_select = RREG32(0x402C);
  81         num_pipes = ((gb_pipe_select >> 12) & 3) + 1;
  82         rdev->num_gb_pipes = num_pipes;
  83         tmp = 0;
  84         switch (num_pipes) {
  85         default:
  86                 /* force to 1 pipe */
  87                 num_pipes = 1;
  88         case 1:
  89                 tmp = (0 << 1);
  90                 break;
  91         case 2:
  92                 tmp = (3 << 1);
  93                 break;
  94         case 3:
  95                 tmp = (6 << 1);
  96                 break;
  97         case 4:
  98                 tmp = (7 << 1);
  99                 break;
 100         }
 101         WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1);
 102         /* Sub pixel 1/12 so we can have 4K rendering according to doc */
 103         tmp |= R300_TILE_SIZE_16 | R300_ENABLE_TILING;
 104         WREG32(R300_GB_TILE_CONFIG, tmp);
 105         if (r100_gui_wait_for_idle(rdev)) {
 106                 printk(KERN_WARNING "Failed to wait GUI idle while "
 107                        "programming pipes. Bad things might happen.\n");
 108         }
 109
 110         tmp = RREG32(R300_DST_PIPE_CONFIG);
 111         WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
 112
 113         WREG32(R300_RB2D_DSTCACHE_MODE,
 114                RREG32(R300_RB2D_DSTCACHE_MODE) |
 115                R300_DC_AUTOFLUSH_ENABLE |
 116                R300_DC_DC_DISABLE_IGNORE_PE);
 117
 118         if (r100_gui_wait_for_idle(rdev)) {
 119                 printk(KERN_WARNING "Failed to wait GUI idle while "
 120                        "programming pipes. Bad things might happen.\n");
 121         }
 122
 123         if (rdev->family == CHIP_RV530) {
 124                 tmp = RREG32(RV530_GB_PIPE_SELECT2);
 125                 if ((tmp & 3) == 3)
 126                         rdev->num_z_pipes = 2;
 127                 else
 128                         rdev->num_z_pipes = 1;
 129         } else
 130                 rdev->num_z_pipes = 1;
 131
 132         DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n",
 133                  rdev->num_gb_pipes, rdev->num_z_pipes);
 134 }
 135
 136 u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
 137 {
 138         u32 r;
 139
 140         WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));
 141         r = RREG32(R_0001FC_MC_IND_DATA);
 142         return r;
 143 }
 144
 145 void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
 146 {
 147         WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) |
 148                 S_0001F8_MC_IND_WR_EN(1));
 149         WREG32(R_0001FC_MC_IND_DATA, v);
 150 }
 151
 152 static void r420_debugfs(struct radeon_device *rdev)
 153 {
 154         if (r100_debugfs_rbbm_init(rdev)) {
 155                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
 156         }
 157         if (r420_debugfs_pipes_info_init(rdev)) {
 158                 DRM_ERROR("Failed to register debugfs file for pipes !\n");
 159         }
 160 }
 161
 162 static void r420_clock_resume(struct radeon_device *rdev)
 163 {
 164         u32 sclk_cntl;
 165
 166         if (radeon_dynclks != -1 && radeon_dynclks)
 167                 radeon_atom_set_clock_gating(rdev, 1);
 168         sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL);
 169         sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
 170         if (rdev->family == CHIP_R420)
 171                 sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1);
 172         WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl);
 173 }
 174
 175 static void r420_cp_errata_init(struct radeon_device *rdev)
 176 {
 177         /* RV410 and R420 can lock up if CP DMA to host memory happens
 178          * while the 2D engine is busy.
 179          *
 180          * The proper workaround is to queue a RESYNC at the beginning
 181          * of the CP init, apparently.
 182          */
 183         radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch);
 184         radeon_ring_lock(rdev, 8);
 185         radeon_ring_write(rdev, PACKET0(R300_CP_RESYNC_ADDR, 1));
 186         radeon_ring_write(rdev, rdev->config.r300.resync_scratch);
 187         radeon_ring_write(rdev, 0xDEADBEEF);
 188         radeon_ring_unlock_commit(rdev);
 189 }
 190
 191 static void r420_cp_errata_fini(struct radeon_device *rdev)
 192 {
 193         /* Catch the RESYNC we dispatched all the way back,
 194          * at the very beginning of the CP init.
 195          */
 196         radeon_ring_lock(rdev, 8);
 197         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
 198         radeon_ring_write(rdev, R300_RB3D_DC_FINISH);
 199         radeon_ring_unlock_commit(rdev);
 200         radeon_scratch_free(rdev, rdev->config.r300.resync_scratch);
 201 }
 202
 203 static int r420_startup(struct radeon_device *rdev)
 204 {
 205         int r;
 206
 207         /* set common regs */
 208         r100_set_common_regs(rdev);
 209         /* program mc */
 210         r300_mc_program(rdev);
 211         /* Resume clock */
 212         r420_clock_resume(rdev);
 213         /* Initialize GART (initialize after TTM so we can allocate
 214          * memory through TTM but finalize after TTM) */
 215         if (rdev->flags & RADEON_IS_PCIE) {
 216                 r = rv370_pcie_gart_enable(rdev);
 217                 if (r)
 218                         return r;
 219         }
 220         if (rdev->flags & RADEON_IS_PCI) {
 221                 r = r100_pci_gart_enable(rdev);
 222                 if (r)
 223                         return r;
 224         }
 225         r420_pipes_init(rdev);
 226         /* Enable IRQ */
 227         r100_irq_set(rdev);
 228         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
 229         /* 1M ring buffer */
 230         r = r100_cp_init(rdev, 1024 * 1024);
 231         if (r) {
 232                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
 233                 return r;
 234         }
 235         r420_cp_errata_init(rdev);
 236         r = r100_wb_init(rdev);
 237         if (r) {
 238                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
 239         }
 240         r = r100_ib_init(rdev);
 241         if (r) {
 242                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
 243                 return r;
 244         }
 245         return 0;
 246 }
 247
 248 int r420_resume(struct radeon_device *rdev)
 249 {
 250         /* Make sur GART are not working */
 251         if (rdev->flags & RADEON_IS_PCIE)
 252                 rv370_pcie_gart_disable(rdev);
 253         if (rdev->flags & RADEON_IS_PCI)
 254                 r100_pci_gart_disable(rdev);
 255         /* Resume clock before doing reset */
 256         r420_clock_resume(rdev);
 257         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 258         if (radeon_gpu_reset(rdev)) {
 259                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 260                         RREG32(R_000E40_RBBM_STATUS),
 261                         RREG32(R_0007C0_CP_STAT));
 262         }
 263         /* check if cards are posted or not */
 264         if (rdev->is_atom_bios) {
 265                 atom_asic_init(rdev->mode_info.atom_context);
 266         } else {
 267                 radeon_combios_asic_init(rdev->ddev);
 268         }
 269         /* Resume clock after posting */
 270         r420_clock_resume(rdev);
 271         /* Initialize surface registers */
 272         radeon_surface_init(rdev);
 273         return r420_startup(rdev);
 274 }
 275
 276 int r420_suspend(struct radeon_device *rdev)
 277 {
 278         r420_cp_errata_fini(rdev);
 279         r100_cp_disable(rdev);
 280         r100_wb_disable(rdev);
 281         r100_irq_disable(rdev);
 282         if (rdev->flags & RADEON_IS_PCIE)
 283                 rv370_pcie_gart_disable(rdev);
 284         if (rdev->flags & RADEON_IS_PCI)
 285                 r100_pci_gart_disable(rdev);
 286         return 0;
 287 }
 288
 289 void r420_fini(struct radeon_device *rdev)
 290 {
 291         r100_cp_fini(rdev);
 292         r100_wb_fini(rdev);
 293         r100_ib_fini(rdev);
 294         radeon_gem_fini(rdev);
 295         if (rdev->flags & RADEON_IS_PCIE)
 296                 rv370_pcie_gart_fini(rdev);
 297         if (rdev->flags & RADEON_IS_PCI)
 298                 r100_pci_gart_fini(rdev);
 299         radeon_agp_fini(rdev);
 300         radeon_irq_kms_fini(rdev);
 301         radeon_fence_driver_fini(rdev);
 302         radeon_bo_fini(rdev);
 303         if (rdev->is_atom_bios) {
 304                 radeon_atombios_fini(rdev);
 305         } else {
 306                 radeon_combios_fini(rdev);
 307         }
 308         kfree(rdev->bios);
 309         rdev->bios = NULL;
 310 }
 311
 312 int r420_init(struct radeon_device *rdev)
 313 {
 314         int r;
 315
 316         /* Initialize scratch registers */
 317         radeon_scratch_init(rdev);
 318         /* Initialize surface registers */
 319         radeon_surface_init(rdev);
 320         /* TODO: disable VGA need to use VGA request */
 321         /* BIOS*/
 322         if (!radeon_get_bios(rdev)) {
 323                 if (ASIC_IS_AVIVO(rdev))
 324                         return -EINVAL;
 325         }
 326         if (rdev->is_atom_bios) {
 327                 r = radeon_atombios_init(rdev);
 328                 if (r) {
 329                         return r;
 330                 }
 331         } else {
 332                 r = radeon_combios_init(rdev);
 333                 if (r) {
 334                         return r;
 335                 }
 336         }
 337         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 338         if (radeon_gpu_reset(rdev)) {
 339                 dev_warn(rdev->dev,
 340                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 341                         RREG32(R_000E40_RBBM_STATUS),
 342                         RREG32(R_0007C0_CP_STAT));
 343         }
 344         /* check if cards are posted or not */
 345         if (radeon_boot_test_post_card(rdev) == false)
 346                 return -EINVAL;
 347
 348         /* Initialize clocks */
 349         radeon_get_clock_info(rdev->ddev);
 350         /* Initialize power management */
 351         radeon_pm_init(rdev);
 352         /* Get vram informations */
 353         r300_vram_info(rdev);
 354         /* Initialize memory controller (also test AGP) */
 355         r = r420_mc_init(rdev);
 356         if (r) {
 357                 return r;
 358         }
 359         r420_debugfs(rdev);
 360         /* Fence driver */
 361         r = radeon_fence_driver_init(rdev);
 362         if (r) {
 363                 return r;
 364         }
 365         r = radeon_irq_kms_init(rdev);
 366         if (r) {
 367                 return r;
 368         }
 369         /* Memory manager */
 370         r = radeon_bo_init(rdev);
 371         if (r) {
 372                 return r;
 373         }
 374         if (rdev->family == CHIP_R420)
 375                 r100_enable_bm(rdev);
 376
 377         if (rdev->flags & RADEON_IS_PCIE) {
 378                 r = rv370_pcie_gart_init(rdev);
 379                 if (r)
 380                         return r;
 381         }
 382         if (rdev->flags & RADEON_IS_PCI) {
 383                 r = r100_pci_gart_init(rdev);
 384                 if (r)
 385                         return r;
 386         }
 387         r420_set_reg_safe(rdev);
 388         rdev->accel_working = true;
 389         r = r420_startup(rdev);
 390         if (r) {
 391                 /* Somethings want wront with the accel init stop accel */
 392                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
 393                 r100_cp_fini(rdev);
 394                 r100_wb_fini(rdev);
 395                 r100_ib_fini(rdev);
 396                 radeon_irq_kms_fini(rdev);
 397                 if (rdev->flags & RADEON_IS_PCIE)
 398                         rv370_pcie_gart_fini(rdev);
 399                 if (rdev->flags & RADEON_IS_PCI)
 400                         r100_pci_gart_fini(rdev);
 401                 radeon_agp_fini(rdev);
 402                 rdev->accel_working = false;
 403         }
 404         return 0;
 405 }
 406
 407 /*
 408  * Debugfs info
 409  */
 410 #if defined(CONFIG_DEBUG_FS)
 411 static int r420_debugfs_pipes_info(struct seq_file *m, void *data)
 412 {
 413         struct drm_info_node *node = (struct drm_info_node *) m->private;
 414         struct drm_device *dev = node->minor->dev;
 415         struct radeon_device *rdev = dev->dev_private;
 416         uint32_t tmp;
 417
 418         tmp = RREG32(R400_GB_PIPE_SELECT);
 419         seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
 420         tmp = RREG32(R300_GB_TILE_CONFIG);
 421         seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
 422         tmp = RREG32(R300_DST_PIPE_CONFIG);
 423         seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
 424         return 0;
 425 }
 426
 427 static struct drm_info_list r420_pipes_info_list[] = {
 428         {"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL},
 429 };
 430 #endif
 431
 432 int r420_debugfs_pipes_info_init(struct radeon_device *rdev)
 433 {
 434 #if defined(CONFIG_DEBUG_FS)
 435         return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1);
 436 #else
 437         return 0;
 438 #endif
 439 }