SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/r420.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include "drmP.h"
  30 #include "radeon_reg.h"
  31 #include "radeon.h"
  32 #include "radeon_asic.h"
  33 #include "atom.h"
  34 #include "r100d.h"
  35 #include "r420d.h"
  36 #include "r420_reg_safe.h"
  37
  38 static void r420_set_reg_safe(struct radeon_device *rdev)
  39 {
  40         rdev->config.r300.reg_safe_bm = r420_reg_safe_bm;
  41         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm);
  42 }
  43
  44 void r420_pipes_init(struct radeon_device *rdev)
  45 {
  46         unsigned tmp;
  47         unsigned gb_pipe_select;
  48         unsigned num_pipes;
  49
  50         /* GA_ENHANCE workaround TCL deadlock issue */
  51         WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL |
  52                (1 << 2) | (1 << 3));
  53         /* add idle wait as per freedesktop.org bug 24041 */
  54         if (r100_gui_wait_for_idle(rdev)) {
  55                 printk(KERN_WARNING "Failed to wait GUI idle while "
  56                        "programming pipes. Bad things might happen.\n");
  57         }
  58         /* get max number of pipes */
  59         gb_pipe_select = RREG32(0x402C);
  60         num_pipes = ((gb_pipe_select >> 12) & 3) + 1;
  61
  62         /* SE chips have 1 pipe */
  63         if ((rdev->pdev->device == 0x5e4c) ||
  64             (rdev->pdev->device == 0x5e4f))
  65                 num_pipes = 1;
  66
  67         rdev->num_gb_pipes = num_pipes;
  68         tmp = 0;
  69         switch (num_pipes) {
  70         default:
  71                 /* force to 1 pipe */
  72                 num_pipes = 1;
  73         case 1:
  74                 tmp = (0 << 1);
  75                 break;
  76         case 2:
  77                 tmp = (3 << 1);
  78                 break;
  79         case 3:
  80                 tmp = (6 << 1);
  81                 break;
  82         case 4:
  83                 tmp = (7 << 1);
  84                 break;
  85         }
  86         WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1);
  87         /* Sub pixel 1/12 so we can have 4K rendering according to doc */
  88         tmp |= R300_TILE_SIZE_16 | R300_ENABLE_TILING;
  89         WREG32(R300_GB_TILE_CONFIG, tmp);
  90         if (r100_gui_wait_for_idle(rdev)) {
  91                 printk(KERN_WARNING "Failed to wait GUI idle while "
  92                        "programming pipes. Bad things might happen.\n");
  93         }
  94
  95         tmp = RREG32(R300_DST_PIPE_CONFIG);
  96         WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
  97
  98         WREG32(R300_RB2D_DSTCACHE_MODE,
  99                RREG32(R300_RB2D_DSTCACHE_MODE) |
 100                R300_DC_AUTOFLUSH_ENABLE |
 101                R300_DC_DC_DISABLE_IGNORE_PE);
 102
 103         if (r100_gui_wait_for_idle(rdev)) {
 104                 printk(KERN_WARNING "Failed to wait GUI idle while "
 105                        "programming pipes. Bad things might happen.\n");
 106         }
 107
 108         if (rdev->family == CHIP_RV530) {
 109                 tmp = RREG32(RV530_GB_PIPE_SELECT2);
 110                 if ((tmp & 3) == 3)
 111                         rdev->num_z_pipes = 2;
 112                 else
 113                         rdev->num_z_pipes = 1;
 114         } else
 115                 rdev->num_z_pipes = 1;
 116
 117         DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n",
 118                  rdev->num_gb_pipes, rdev->num_z_pipes);
 119 }
 120
 121 u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
 122 {
 123         u32 r;
 124
 125         WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));
 126         r = RREG32(R_0001FC_MC_IND_DATA);
 127         return r;
 128 }
 129
 130 void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
 131 {
 132         WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) |
 133                 S_0001F8_MC_IND_WR_EN(1));
 134         WREG32(R_0001FC_MC_IND_DATA, v);
 135 }
 136
 137 static void r420_debugfs(struct radeon_device *rdev)
 138 {
 139         if (r100_debugfs_rbbm_init(rdev)) {
 140                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
 141         }
 142         if (r420_debugfs_pipes_info_init(rdev)) {
 143                 DRM_ERROR("Failed to register debugfs file for pipes !\n");
 144         }
 145 }
 146
 147 static void r420_clock_resume(struct radeon_device *rdev)
 148 {
 149         u32 sclk_cntl;
 150
 151         if (radeon_dynclks != -1 && radeon_dynclks)
 152                 radeon_atom_set_clock_gating(rdev, 1);
 153         sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL);
 154         sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
 155         if (rdev->family == CHIP_R420)
 156                 sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1);
 157         WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl);
 158 }
 159
 160 static void r420_cp_errata_init(struct radeon_device *rdev)
 161 {
 162         /* RV410 and R420 can lock up if CP DMA to host memory happens
 163          * while the 2D engine is busy.
 164          *
 165          * The proper workaround is to queue a RESYNC at the beginning
 166          * of the CP init, apparently.
 167          */
 168         radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch);
 169         radeon_ring_lock(rdev, 8);
 170         radeon_ring_write(rdev, PACKET0(R300_CP_RESYNC_ADDR, 1));
 171         radeon_ring_write(rdev, rdev->config.r300.resync_scratch);
 172         radeon_ring_write(rdev, 0xDEADBEEF);
 173         radeon_ring_unlock_commit(rdev);
 174 }
 175
 176 static void r420_cp_errata_fini(struct radeon_device *rdev)
 177 {
 178         /* Catch the RESYNC we dispatched all the way back,
 179          * at the very beginning of the CP init.
 180          */
 181         radeon_ring_lock(rdev, 8);
 182         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
 183         radeon_ring_write(rdev, R300_RB3D_DC_FINISH);
 184         radeon_ring_unlock_commit(rdev);
 185         radeon_scratch_free(rdev, rdev->config.r300.resync_scratch);
 186 }
 187
 188 static int r420_startup(struct radeon_device *rdev)
 189 {
 190         int r;
 191
 192         /* set common regs */
 193         r100_set_common_regs(rdev);
 194         /* program mc */
 195         r300_mc_program(rdev);
 196         /* Resume clock */
 197         r420_clock_resume(rdev);
 198         /* Initialize GART (initialize after TTM so we can allocate
 199          * memory through TTM but finalize after TTM) */
 200         if (rdev->flags & RADEON_IS_PCIE) {
 201                 r = rv370_pcie_gart_enable(rdev);
 202                 if (r)
 203                         return r;
 204         }
 205         if (rdev->flags & RADEON_IS_PCI) {
 206                 r = r100_pci_gart_enable(rdev);
 207                 if (r)
 208                         return r;
 209         }
 210         r420_pipes_init(rdev);
 211         /* Enable IRQ */
 212         r100_irq_set(rdev);
 213         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
 214         /* 1M ring buffer */
 215         r = r100_cp_init(rdev, 1024 * 1024);
 216         if (r) {
 217                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
 218                 return r;
 219         }
 220         r420_cp_errata_init(rdev);
 221         r = r100_wb_init(rdev);
 222         if (r) {
 223                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
 224         }
 225         r = r100_ib_init(rdev);
 226         if (r) {
 227                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
 228                 return r;
 229         }
 230         return 0;
 231 }
 232
 233 int r420_resume(struct radeon_device *rdev)
 234 {
 235         /* Make sur GART are not working */
 236         if (rdev->flags & RADEON_IS_PCIE)
 237                 rv370_pcie_gart_disable(rdev);
 238         if (rdev->flags & RADEON_IS_PCI)
 239                 r100_pci_gart_disable(rdev);
 240         /* Resume clock before doing reset */
 241         r420_clock_resume(rdev);
 242         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 243         if (radeon_gpu_reset(rdev)) {
 244                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 245                         RREG32(R_000E40_RBBM_STATUS),
 246                         RREG32(R_0007C0_CP_STAT));
 247         }
 248         /* check if cards are posted or not */
 249         if (rdev->is_atom_bios) {
 250                 atom_asic_init(rdev->mode_info.atom_context);
 251         } else {
 252                 radeon_combios_asic_init(rdev->ddev);
 253         }
 254         /* Resume clock after posting */
 255         r420_clock_resume(rdev);
 256         /* Initialize surface registers */
 257         radeon_surface_init(rdev);
 258         return r420_startup(rdev);
 259 }
 260
 261 int r420_suspend(struct radeon_device *rdev)
 262 {
 263         r420_cp_errata_fini(rdev);
 264         r100_cp_disable(rdev);
 265         r100_wb_disable(rdev);
 266         r100_irq_disable(rdev);
 267         if (rdev->flags & RADEON_IS_PCIE)
 268                 rv370_pcie_gart_disable(rdev);
 269         if (rdev->flags & RADEON_IS_PCI)
 270                 r100_pci_gart_disable(rdev);
 271         return 0;
 272 }
 273
 274 void r420_fini(struct radeon_device *rdev)
 275 {
 276         radeon_pm_fini(rdev);
 277         r100_cp_fini(rdev);
 278         r100_wb_fini(rdev);
 279         r100_ib_fini(rdev);
 280         radeon_gem_fini(rdev);
 281         if (rdev->flags & RADEON_IS_PCIE)
 282                 rv370_pcie_gart_fini(rdev);
 283         if (rdev->flags & RADEON_IS_PCI)
 284                 r100_pci_gart_fini(rdev);
 285         radeon_agp_fini(rdev);
 286         radeon_irq_kms_fini(rdev);
 287         radeon_fence_driver_fini(rdev);
 288         radeon_bo_fini(rdev);
 289         if (rdev->is_atom_bios) {
 290                 radeon_atombios_fini(rdev);
 291         } else {
 292                 radeon_combios_fini(rdev);
 293         }
 294         kfree(rdev->bios);
 295         rdev->bios = NULL;
 296 }
 297
 298 int r420_init(struct radeon_device *rdev)
 299 {
 300         int r;
 301
 302         /* Initialize scratch registers */
 303         radeon_scratch_init(rdev);
 304         /* Initialize surface registers */
 305         radeon_surface_init(rdev);
 306         /* TODO: disable VGA need to use VGA request */
 307         /* BIOS*/
 308         if (!radeon_get_bios(rdev)) {
 309                 if (ASIC_IS_AVIVO(rdev))
 310                         return -EINVAL;
 311         }
 312         if (rdev->is_atom_bios) {
 313                 r = radeon_atombios_init(rdev);
 314                 if (r) {
 315                         return r;
 316                 }
 317         } else {
 318                 r = radeon_combios_init(rdev);
 319                 if (r) {
 320                         return r;
 321                 }
 322         }
 323         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 324         if (radeon_gpu_reset(rdev)) {
 325                 dev_warn(rdev->dev,
 326                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 327                         RREG32(R_000E40_RBBM_STATUS),
 328                         RREG32(R_0007C0_CP_STAT));
 329         }
 330         /* check if cards are posted or not */
 331         if (radeon_boot_test_post_card(rdev) == false)
 332                 return -EINVAL;
 333
 334         /* Initialize clocks */
 335         radeon_get_clock_info(rdev->ddev);
 336         /* Initialize power management */
 337         radeon_pm_init(rdev);
 338         /* initialize AGP */
 339         if (rdev->flags & RADEON_IS_AGP) {
 340                 r = radeon_agp_init(rdev);
 341                 if (r) {
 342                         radeon_agp_disable(rdev);
 343                 }
 344         }
 345         /* initialize memory controller */
 346         r300_mc_init(rdev);
 347         r420_debugfs(rdev);
 348         /* Fence driver */
 349         r = radeon_fence_driver_init(rdev);
 350         if (r) {
 351                 return r;
 352         }
 353         r = radeon_irq_kms_init(rdev);
 354         if (r) {
 355                 return r;
 356         }
 357         /* Memory manager */
 358         r = radeon_bo_init(rdev);
 359         if (r) {
 360                 return r;
 361         }
 362         if (rdev->family == CHIP_R420)
 363                 r100_enable_bm(rdev);
 364
 365         if (rdev->flags & RADEON_IS_PCIE) {
 366                 r = rv370_pcie_gart_init(rdev);
 367                 if (r)
 368                         return r;
 369         }
 370         if (rdev->flags & RADEON_IS_PCI) {
 371                 r = r100_pci_gart_init(rdev);
 372                 if (r)
 373                         return r;
 374         }
 375         r420_set_reg_safe(rdev);
 376         rdev->accel_working = true;
 377         r = r420_startup(rdev);
 378         if (r) {
 379                 /* Somethings want wront with the accel init stop accel */
 380                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
 381                 r100_cp_fini(rdev);
 382                 r100_wb_fini(rdev);
 383                 r100_ib_fini(rdev);
 384                 radeon_irq_kms_fini(rdev);
 385                 if (rdev->flags & RADEON_IS_PCIE)
 386                         rv370_pcie_gart_fini(rdev);
 387                 if (rdev->flags & RADEON_IS_PCI)
 388                         r100_pci_gart_fini(rdev);
 389                 radeon_agp_fini(rdev);
 390                 rdev->accel_working = false;
 391         }
 392         return 0;
 393 }
 394
 395 /*
 396  * Debugfs info
 397  */
 398 #if defined(CONFIG_DEBUG_FS)
 399 static int r420_debugfs_pipes_info(struct seq_file *m, void *data)
 400 {
 401         struct drm_info_node *node = (struct drm_info_node *) m->private;
 402         struct drm_device *dev = node->minor->dev;
 403         struct radeon_device *rdev = dev->dev_private;
 404         uint32_t tmp;
 405
 406         tmp = RREG32(R400_GB_PIPE_SELECT);
 407         seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
 408         tmp = RREG32(R300_GB_TILE_CONFIG);
 409         seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
 410         tmp = RREG32(R300_DST_PIPE_CONFIG);
 411         seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
 412         return 0;
 413 }
 414
 415 static struct drm_info_list r420_pipes_info_list[] = {
 416         {"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL},
 417 };
 418 #endif
 419
 420 int r420_debugfs_pipes_info_init(struct radeon_device *rdev)
 421 {
 422 #if defined(CONFIG_DEBUG_FS)
 423         return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1);
 424 #else
 425         return 0;
 426 #endif
 427 }