drm/radeon/kms: fence cleanup + more reliable GPU lockup detection V4
[safe/jmp/linux-2.6] / drivers / gpu / drm / radeon / r300.c
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include <linux/seq_file.h>
29 #include <drm/drmP.h>
30 #include <drm/drm.h>
31 #include <drm/drm_crtc_helper.h>
32 #include "radeon_reg.h"
33 #include "radeon.h"
34 #include "radeon_asic.h"
35 #include "radeon_drm.h"
36 #include "r100_track.h"
37 #include "r300d.h"
38 #include "rv350d.h"
39 #include "r300_reg_safe.h"
40
41 /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380
42  *
43  * GPU Errata:
44  * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL
45  *   using MMIO to flush host path read cache, this lead to HARDLOCKUP.
46  *   However, scheduling such write to the ring seems harmless, i suspect
47  *   the CP read collide with the flush somehow, or maybe the MC, hard to
48  *   tell. (Jerome Glisse)
49  */
50
51 /*
52  * rv370,rv380 PCIE GART
53  */
54 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
55
56 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
57 {
58         uint32_t tmp;
59         int i;
60
61         /* Workaround HW bug do flush 2 times */
62         for (i = 0; i < 2; i++) {
63                 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
64                 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);
65                 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
66                 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
67         }
68         mb();
69 }
70
71 int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
72 {
73         void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
74
75         if (i < 0 || i > rdev->gart.num_gpu_pages) {
76                 return -EINVAL;
77         }
78         addr = (lower_32_bits(addr) >> 8) |
79                ((upper_32_bits(addr) & 0xff) << 24) |
80                0xc;
81         /* on x86 we want this to be CPU endian, on powerpc
82          * on powerpc without HW swappers, it'll get swapped on way
83          * into VRAM - so no need for cpu_to_le32 on VRAM tables */
84         writel(addr, ((void __iomem *)ptr) + (i * 4));
85         return 0;
86 }
87
88 int rv370_pcie_gart_init(struct radeon_device *rdev)
89 {
90         int r;
91
92         if (rdev->gart.table.vram.robj) {
93                 WARN(1, "RV370 PCIE GART already initialized.\n");
94                 return 0;
95         }
96         /* Initialize common gart structure */
97         r = radeon_gart_init(rdev);
98         if (r)
99                 return r;
100         r = rv370_debugfs_pcie_gart_info_init(rdev);
101         if (r)
102                 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
103         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
104         rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
105         rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
106         return radeon_gart_table_vram_alloc(rdev);
107 }
108
109 int rv370_pcie_gart_enable(struct radeon_device *rdev)
110 {
111         uint32_t table_addr;
112         uint32_t tmp;
113         int r;
114
115         if (rdev->gart.table.vram.robj == NULL) {
116                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
117                 return -EINVAL;
118         }
119         r = radeon_gart_table_vram_pin(rdev);
120         if (r)
121                 return r;
122         radeon_gart_restore(rdev);
123         /* discard memory request outside of configured range */
124         tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
125         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
126         WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start);
127         tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK;
128         WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
129         WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
130         WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
131         table_addr = rdev->gart.table_addr;
132         WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);
133         /* FIXME: setup default page */
134         WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start);
135         WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
136         /* Clear error */
137         WREG32_PCIE(0x18, 0);
138         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
139         tmp |= RADEON_PCIE_TX_GART_EN;
140         tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
141         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
142         rv370_pcie_gart_tlb_flush(rdev);
143         DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n",
144                  (unsigned)(rdev->mc.gtt_size >> 20), table_addr);
145         rdev->gart.ready = true;
146         return 0;
147 }
148
149 void rv370_pcie_gart_disable(struct radeon_device *rdev)
150 {
151         u32 tmp;
152         int r;
153
154         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
155         tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
156         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
157         if (rdev->gart.table.vram.robj) {
158                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
159                 if (likely(r == 0)) {
160                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
161                         radeon_bo_unpin(rdev->gart.table.vram.robj);
162                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
163                 }
164         }
165 }
166
167 void rv370_pcie_gart_fini(struct radeon_device *rdev)
168 {
169         radeon_gart_fini(rdev);
170         rv370_pcie_gart_disable(rdev);
171         radeon_gart_table_vram_free(rdev);
172 }
173
174 void r300_fence_ring_emit(struct radeon_device *rdev,
175                           struct radeon_fence *fence)
176 {
177         /* Who ever call radeon_fence_emit should call ring_lock and ask
178          * for enough space (today caller are ib schedule and buffer move) */
179         /* Write SC register so SC & US assert idle */
180         radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_TL, 0));
181         radeon_ring_write(rdev, 0);
182         radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_BR, 0));
183         radeon_ring_write(rdev, 0);
184         /* Flush 3D cache */
185         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
186         radeon_ring_write(rdev, R300_RB3D_DC_FLUSH);
187         radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
188         radeon_ring_write(rdev, R300_ZC_FLUSH);
189         /* Wait until IDLE & CLEAN */
190         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
191         radeon_ring_write(rdev, (RADEON_WAIT_3D_IDLECLEAN |
192                                  RADEON_WAIT_2D_IDLECLEAN |
193                                  RADEON_WAIT_DMA_GUI_IDLE));
194         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
195         radeon_ring_write(rdev, rdev->config.r300.hdp_cntl |
196                                 RADEON_HDP_READ_BUFFER_INVALIDATE);
197         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
198         radeon_ring_write(rdev, rdev->config.r300.hdp_cntl);
199         /* Emit fence sequence & fire IRQ */
200         radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
201         radeon_ring_write(rdev, fence->seq);
202         radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
203         radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
204 }
205
206 void r300_ring_start(struct radeon_device *rdev)
207 {
208         unsigned gb_tile_config;
209         int r;
210
211         /* Sub pixel 1/12 so we can have 4K rendering according to doc */
212         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
213         switch(rdev->num_gb_pipes) {
214         case 2:
215                 gb_tile_config |= R300_PIPE_COUNT_R300;
216                 break;
217         case 3:
218                 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
219                 break;
220         case 4:
221                 gb_tile_config |= R300_PIPE_COUNT_R420;
222                 break;
223         case 1:
224         default:
225                 gb_tile_config |= R300_PIPE_COUNT_RV350;
226                 break;
227         }
228
229         r = radeon_ring_lock(rdev, 64);
230         if (r) {
231                 return;
232         }
233         radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
234         radeon_ring_write(rdev,
235                           RADEON_ISYNC_ANY2D_IDLE3D |
236                           RADEON_ISYNC_ANY3D_IDLE2D |
237                           RADEON_ISYNC_WAIT_IDLEGUI |
238                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
239         radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0));
240         radeon_ring_write(rdev, gb_tile_config);
241         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
242         radeon_ring_write(rdev,
243                           RADEON_WAIT_2D_IDLECLEAN |
244                           RADEON_WAIT_3D_IDLECLEAN);
245         radeon_ring_write(rdev, PACKET0(R300_DST_PIPE_CONFIG, 0));
246         radeon_ring_write(rdev, R300_PIPE_AUTO_CONFIG);
247         radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0));
248         radeon_ring_write(rdev, 0);
249         radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0));
250         radeon_ring_write(rdev, 0);
251         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
252         radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
253         radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
254         radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
255         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
256         radeon_ring_write(rdev,
257                           RADEON_WAIT_2D_IDLECLEAN |
258                           RADEON_WAIT_3D_IDLECLEAN);
259         radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0));
260         radeon_ring_write(rdev, 0);
261         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
262         radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
263         radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
264         radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
265         radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0));
266         radeon_ring_write(rdev,
267                           ((6 << R300_MS_X0_SHIFT) |
268                            (6 << R300_MS_Y0_SHIFT) |
269                            (6 << R300_MS_X1_SHIFT) |
270                            (6 << R300_MS_Y1_SHIFT) |
271                            (6 << R300_MS_X2_SHIFT) |
272                            (6 << R300_MS_Y2_SHIFT) |
273                            (6 << R300_MSBD0_Y_SHIFT) |
274                            (6 << R300_MSBD0_X_SHIFT)));
275         radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0));
276         radeon_ring_write(rdev,
277                           ((6 << R300_MS_X3_SHIFT) |
278                            (6 << R300_MS_Y3_SHIFT) |
279                            (6 << R300_MS_X4_SHIFT) |
280                            (6 << R300_MS_Y4_SHIFT) |
281                            (6 << R300_MS_X5_SHIFT) |
282                            (6 << R300_MS_Y5_SHIFT) |
283                            (6 << R300_MSBD1_SHIFT)));
284         radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0));
285         radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
286         radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0));
287         radeon_ring_write(rdev,
288                           R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
289         radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0));
290         radeon_ring_write(rdev,
291                           R300_GEOMETRY_ROUND_NEAREST |
292                           R300_COLOR_ROUND_NEAREST);
293         radeon_ring_unlock_commit(rdev);
294 }
295
296 void r300_errata(struct radeon_device *rdev)
297 {
298         rdev->pll_errata = 0;
299
300         if (rdev->family == CHIP_R300 &&
301             (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) {
302                 rdev->pll_errata |= CHIP_ERRATA_R300_CG;
303         }
304 }
305
306 int r300_mc_wait_for_idle(struct radeon_device *rdev)
307 {
308         unsigned i;
309         uint32_t tmp;
310
311         for (i = 0; i < rdev->usec_timeout; i++) {
312                 /* read MC_STATUS */
313                 tmp = RREG32(RADEON_MC_STATUS);
314                 if (tmp & R300_MC_IDLE) {
315                         return 0;
316                 }
317                 DRM_UDELAY(1);
318         }
319         return -1;
320 }
321
322 void r300_gpu_init(struct radeon_device *rdev)
323 {
324         uint32_t gb_tile_config, tmp;
325
326         r100_hdp_reset(rdev);
327         /* FIXME: rv380 one pipes ? */
328         if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) ||
329             (rdev->family == CHIP_R350)) {
330                 /* r300,r350 */
331                 rdev->num_gb_pipes = 2;
332         } else {
333                 /* rv350,rv370,rv380,r300 AD */
334                 rdev->num_gb_pipes = 1;
335         }
336         rdev->num_z_pipes = 1;
337         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
338         switch (rdev->num_gb_pipes) {
339         case 2:
340                 gb_tile_config |= R300_PIPE_COUNT_R300;
341                 break;
342         case 3:
343                 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
344                 break;
345         case 4:
346                 gb_tile_config |= R300_PIPE_COUNT_R420;
347                 break;
348         default:
349         case 1:
350                 gb_tile_config |= R300_PIPE_COUNT_RV350;
351                 break;
352         }
353         WREG32(R300_GB_TILE_CONFIG, gb_tile_config);
354
355         if (r100_gui_wait_for_idle(rdev)) {
356                 printk(KERN_WARNING "Failed to wait GUI idle while "
357                        "programming pipes. Bad things might happen.\n");
358         }
359
360         tmp = RREG32(R300_DST_PIPE_CONFIG);
361         WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
362
363         WREG32(R300_RB2D_DSTCACHE_MODE,
364                R300_DC_AUTOFLUSH_ENABLE |
365                R300_DC_DC_DISABLE_IGNORE_PE);
366
367         if (r100_gui_wait_for_idle(rdev)) {
368                 printk(KERN_WARNING "Failed to wait GUI idle while "
369                        "programming pipes. Bad things might happen.\n");
370         }
371         if (r300_mc_wait_for_idle(rdev)) {
372                 printk(KERN_WARNING "Failed to wait MC idle while "
373                        "programming pipes. Bad things might happen.\n");
374         }
375         DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
376                  rdev->num_gb_pipes, rdev->num_z_pipes);
377 }
378
379 int r300_ga_reset(struct radeon_device *rdev)
380 {
381         uint32_t tmp;
382         bool reinit_cp;
383         int i;
384
385         reinit_cp = rdev->cp.ready;
386         rdev->cp.ready = false;
387         for (i = 0; i < rdev->usec_timeout; i++) {
388                 WREG32(RADEON_CP_CSQ_MODE, 0);
389                 WREG32(RADEON_CP_CSQ_CNTL, 0);
390                 WREG32(RADEON_RBBM_SOFT_RESET, 0x32005);
391                 (void)RREG32(RADEON_RBBM_SOFT_RESET);
392                 udelay(200);
393                 WREG32(RADEON_RBBM_SOFT_RESET, 0);
394                 /* Wait to prevent race in RBBM_STATUS */
395                 mdelay(1);
396                 tmp = RREG32(RADEON_RBBM_STATUS);
397                 if (tmp & ((1 << 20) | (1 << 26))) {
398                         DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)", tmp);
399                         /* GA still busy soft reset it */
400                         WREG32(0x429C, 0x200);
401                         WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0);
402                         WREG32(R300_RE_SCISSORS_TL, 0);
403                         WREG32(R300_RE_SCISSORS_BR, 0);
404                         WREG32(0x24AC, 0);
405                 }
406                 /* Wait to prevent race in RBBM_STATUS */
407                 mdelay(1);
408                 tmp = RREG32(RADEON_RBBM_STATUS);
409                 if (!(tmp & ((1 << 20) | (1 << 26)))) {
410                         break;
411                 }
412         }
413         for (i = 0; i < rdev->usec_timeout; i++) {
414                 tmp = RREG32(RADEON_RBBM_STATUS);
415                 if (!(tmp & ((1 << 20) | (1 << 26)))) {
416                         DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
417                                  tmp);
418                         if (reinit_cp) {
419                                 return r100_cp_init(rdev, rdev->cp.ring_size);
420                         }
421                         return 0;
422                 }
423                 DRM_UDELAY(1);
424         }
425         tmp = RREG32(RADEON_RBBM_STATUS);
426         DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
427         return -1;
428 }
429
430 bool r300_gpu_is_lockup(struct radeon_device *rdev)
431 {
432         u32 rbbm_status;
433         int r;
434
435         rbbm_status = RREG32(R_000E40_RBBM_STATUS);
436         if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
437                 r100_gpu_lockup_update(&rdev->config.r300.lockup, &rdev->cp);
438                 return false;
439         }
440         /* force CP activities */
441         r = radeon_ring_lock(rdev, 2);
442         if (!r) {
443                 /* PACKET2 NOP */
444                 radeon_ring_write(rdev, 0x80000000);
445                 radeon_ring_write(rdev, 0x80000000);
446                 radeon_ring_unlock_commit(rdev);
447         }
448         rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
449         return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, &rdev->cp);
450 }
451
452 int r300_gpu_reset(struct radeon_device *rdev)
453 {
454         uint32_t status;
455
456         /* reset order likely matter */
457         status = RREG32(RADEON_RBBM_STATUS);
458         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
459         /* reset HDP */
460         r100_hdp_reset(rdev);
461         /* reset rb2d */
462         if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
463                 r100_rb2d_reset(rdev);
464         }
465         /* reset GA */
466         if (status & ((1 << 20) | (1 << 26))) {
467                 r300_ga_reset(rdev);
468         }
469         /* reset CP */
470         status = RREG32(RADEON_RBBM_STATUS);
471         if (status & (1 << 16)) {
472                 r100_cp_reset(rdev);
473         }
474         /* Check if GPU is idle */
475         status = RREG32(RADEON_RBBM_STATUS);
476         if (status & RADEON_RBBM_ACTIVE) {
477                 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
478                 return -1;
479         }
480         DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
481         return 0;
482 }
483
484
485 /*
486  * r300,r350,rv350,rv380 VRAM info
487  */
488 void r300_mc_init(struct radeon_device *rdev)
489 {
490         u64 base;
491         u32 tmp;
492
493         /* DDR for all card after R300 & IGP */
494         rdev->mc.vram_is_ddr = true;
495         tmp = RREG32(RADEON_MEM_CNTL);
496         tmp &= R300_MEM_NUM_CHANNELS_MASK;
497         switch (tmp) {
498         case 0: rdev->mc.vram_width = 64; break;
499         case 1: rdev->mc.vram_width = 128; break;
500         case 2: rdev->mc.vram_width = 256; break;
501         default:  rdev->mc.vram_width = 128; break;
502         }
503         r100_vram_init_sizes(rdev);
504         base = rdev->mc.aper_base;
505         if (rdev->flags & RADEON_IS_IGP)
506                 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
507         radeon_vram_location(rdev, &rdev->mc, base);
508         if (!(rdev->flags & RADEON_IS_AGP))
509                 radeon_gtt_location(rdev, &rdev->mc);
510         radeon_update_bandwidth_info(rdev);
511 }
512
513 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
514 {
515         uint32_t link_width_cntl, mask;
516
517         if (rdev->flags & RADEON_IS_IGP)
518                 return;
519
520         if (!(rdev->flags & RADEON_IS_PCIE))
521                 return;
522
523         /* FIXME wait for idle */
524
525         switch (lanes) {
526         case 0:
527                 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
528                 break;
529         case 1:
530                 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
531                 break;
532         case 2:
533                 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
534                 break;
535         case 4:
536                 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
537                 break;
538         case 8:
539                 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
540                 break;
541         case 12:
542                 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
543                 break;
544         case 16:
545         default:
546                 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
547                 break;
548         }
549
550         link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
551
552         if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
553             (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
554                 return;
555
556         link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
557                              RADEON_PCIE_LC_RECONFIG_NOW |
558                              RADEON_PCIE_LC_RECONFIG_LATER |
559                              RADEON_PCIE_LC_SHORT_RECONFIG_EN);
560         link_width_cntl |= mask;
561         WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
562         WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
563                                                      RADEON_PCIE_LC_RECONFIG_NOW));
564
565         /* wait for lane set to complete */
566         link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
567         while (link_width_cntl == 0xffffffff)
568                 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
569
570 }
571
572 int rv370_get_pcie_lanes(struct radeon_device *rdev)
573 {
574         u32 link_width_cntl;
575
576         if (rdev->flags & RADEON_IS_IGP)
577                 return 0;
578
579         if (!(rdev->flags & RADEON_IS_PCIE))
580                 return 0;
581
582         /* FIXME wait for idle */
583
584         if (rdev->family < CHIP_R600)
585                 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
586         else
587                 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
588
589         switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
590         case RADEON_PCIE_LC_LINK_WIDTH_X0:
591                 return 0;
592         case RADEON_PCIE_LC_LINK_WIDTH_X1:
593                 return 1;
594         case RADEON_PCIE_LC_LINK_WIDTH_X2:
595                 return 2;
596         case RADEON_PCIE_LC_LINK_WIDTH_X4:
597                 return 4;
598         case RADEON_PCIE_LC_LINK_WIDTH_X8:
599                 return 8;
600         case RADEON_PCIE_LC_LINK_WIDTH_X16:
601         default:
602                 return 16;
603         }
604 }
605
606 #if defined(CONFIG_DEBUG_FS)
607 static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data)
608 {
609         struct drm_info_node *node = (struct drm_info_node *) m->private;
610         struct drm_device *dev = node->minor->dev;
611         struct radeon_device *rdev = dev->dev_private;
612         uint32_t tmp;
613
614         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
615         seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);
616         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);
617         seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);
618         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);
619         seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);
620         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);
621         seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);
622         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);
623         seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);
624         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);
625         seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);
626         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);
627         seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);
628         return 0;
629 }
630
631 static struct drm_info_list rv370_pcie_gart_info_list[] = {
632         {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL},
633 };
634 #endif
635
636 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
637 {
638 #if defined(CONFIG_DEBUG_FS)
639         return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1);
640 #else
641         return 0;
642 #endif
643 }
644
645 static int r300_packet0_check(struct radeon_cs_parser *p,
646                 struct radeon_cs_packet *pkt,
647                 unsigned idx, unsigned reg)
648 {
649         struct radeon_cs_reloc *reloc;
650         struct r100_cs_track *track;
651         volatile uint32_t *ib;
652         uint32_t tmp, tile_flags = 0;
653         unsigned i;
654         int r;
655         u32 idx_value;
656
657         ib = p->ib->ptr;
658         track = (struct r100_cs_track *)p->track;
659         idx_value = radeon_get_ib_value(p, idx);
660
661         switch(reg) {
662         case AVIVO_D1MODE_VLINE_START_END:
663         case RADEON_CRTC_GUI_TRIG_VLINE:
664                 r = r100_cs_packet_parse_vline(p);
665                 if (r) {
666                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
667                                         idx, reg);
668                         r100_cs_dump_packet(p, pkt);
669                         return r;
670                 }
671                 break;
672         case RADEON_DST_PITCH_OFFSET:
673         case RADEON_SRC_PITCH_OFFSET:
674                 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
675                 if (r)
676                         return r;
677                 break;
678         case R300_RB3D_COLOROFFSET0:
679         case R300_RB3D_COLOROFFSET1:
680         case R300_RB3D_COLOROFFSET2:
681         case R300_RB3D_COLOROFFSET3:
682                 i = (reg - R300_RB3D_COLOROFFSET0) >> 2;
683                 r = r100_cs_packet_next_reloc(p, &reloc);
684                 if (r) {
685                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
686                                         idx, reg);
687                         r100_cs_dump_packet(p, pkt);
688                         return r;
689                 }
690                 track->cb[i].robj = reloc->robj;
691                 track->cb[i].offset = idx_value;
692                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
693                 break;
694         case R300_ZB_DEPTHOFFSET:
695                 r = r100_cs_packet_next_reloc(p, &reloc);
696                 if (r) {
697                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
698                                         idx, reg);
699                         r100_cs_dump_packet(p, pkt);
700                         return r;
701                 }
702                 track->zb.robj = reloc->robj;
703                 track->zb.offset = idx_value;
704                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
705                 break;
706         case R300_TX_OFFSET_0:
707         case R300_TX_OFFSET_0+4:
708         case R300_TX_OFFSET_0+8:
709         case R300_TX_OFFSET_0+12:
710         case R300_TX_OFFSET_0+16:
711         case R300_TX_OFFSET_0+20:
712         case R300_TX_OFFSET_0+24:
713         case R300_TX_OFFSET_0+28:
714         case R300_TX_OFFSET_0+32:
715         case R300_TX_OFFSET_0+36:
716         case R300_TX_OFFSET_0+40:
717         case R300_TX_OFFSET_0+44:
718         case R300_TX_OFFSET_0+48:
719         case R300_TX_OFFSET_0+52:
720         case R300_TX_OFFSET_0+56:
721         case R300_TX_OFFSET_0+60:
722                 i = (reg - R300_TX_OFFSET_0) >> 2;
723                 r = r100_cs_packet_next_reloc(p, &reloc);
724                 if (r) {
725                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
726                                         idx, reg);
727                         r100_cs_dump_packet(p, pkt);
728                         return r;
729                 }
730
731                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
732                         tile_flags |= R300_TXO_MACRO_TILE;
733                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
734                         tile_flags |= R300_TXO_MICRO_TILE;
735                 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
736                         tile_flags |= R300_TXO_MICRO_TILE_SQUARE;
737
738                 tmp = idx_value + ((u32)reloc->lobj.gpu_offset);
739                 tmp |= tile_flags;
740                 ib[idx] = tmp;
741                 track->textures[i].robj = reloc->robj;
742                 break;
743         /* Tracked registers */
744         case 0x2084:
745                 /* VAP_VF_CNTL */
746                 track->vap_vf_cntl = idx_value;
747                 break;
748         case 0x20B4:
749                 /* VAP_VTX_SIZE */
750                 track->vtx_size = idx_value & 0x7F;
751                 break;
752         case 0x2134:
753                 /* VAP_VF_MAX_VTX_INDX */
754                 track->max_indx = idx_value & 0x00FFFFFFUL;
755                 break;
756         case 0x43E4:
757                 /* SC_SCISSOR1 */
758                 track->maxy = ((idx_value >> 13) & 0x1FFF) + 1;
759                 if (p->rdev->family < CHIP_RV515) {
760                         track->maxy -= 1440;
761                 }
762                 break;
763         case 0x4E00:
764                 /* RB3D_CCTL */
765                 track->num_cb = ((idx_value >> 5) & 0x3) + 1;
766                 break;
767         case 0x4E38:
768         case 0x4E3C:
769         case 0x4E40:
770         case 0x4E44:
771                 /* RB3D_COLORPITCH0 */
772                 /* RB3D_COLORPITCH1 */
773                 /* RB3D_COLORPITCH2 */
774                 /* RB3D_COLORPITCH3 */
775                 r = r100_cs_packet_next_reloc(p, &reloc);
776                 if (r) {
777                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
778                                   idx, reg);
779                         r100_cs_dump_packet(p, pkt);
780                         return r;
781                 }
782
783                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
784                         tile_flags |= R300_COLOR_TILE_ENABLE;
785                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
786                         tile_flags |= R300_COLOR_MICROTILE_ENABLE;
787                 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
788                         tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE;
789
790                 tmp = idx_value & ~(0x7 << 16);
791                 tmp |= tile_flags;
792                 ib[idx] = tmp;
793
794                 i = (reg - 0x4E38) >> 2;
795                 track->cb[i].pitch = idx_value & 0x3FFE;
796                 switch (((idx_value >> 21) & 0xF)) {
797                 case 9:
798                 case 11:
799                 case 12:
800                         track->cb[i].cpp = 1;
801                         break;
802                 case 3:
803                 case 4:
804                 case 13:
805                 case 15:
806                         track->cb[i].cpp = 2;
807                         break;
808                 case 6:
809                         track->cb[i].cpp = 4;
810                         break;
811                 case 10:
812                         track->cb[i].cpp = 8;
813                         break;
814                 case 7:
815                         track->cb[i].cpp = 16;
816                         break;
817                 default:
818                         DRM_ERROR("Invalid color buffer format (%d) !\n",
819                                   ((idx_value >> 21) & 0xF));
820                         return -EINVAL;
821                 }
822                 break;
823         case 0x4F00:
824                 /* ZB_CNTL */
825                 if (idx_value & 2) {
826                         track->z_enabled = true;
827                 } else {
828                         track->z_enabled = false;
829                 }
830                 break;
831         case 0x4F10:
832                 /* ZB_FORMAT */
833                 switch ((idx_value & 0xF)) {
834                 case 0:
835                 case 1:
836                         track->zb.cpp = 2;
837                         break;
838                 case 2:
839                         track->zb.cpp = 4;
840                         break;
841                 default:
842                         DRM_ERROR("Invalid z buffer format (%d) !\n",
843                                   (idx_value & 0xF));
844                         return -EINVAL;
845                 }
846                 break;
847         case 0x4F24:
848                 /* ZB_DEPTHPITCH */
849                 r = r100_cs_packet_next_reloc(p, &reloc);
850                 if (r) {
851                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
852                                   idx, reg);
853                         r100_cs_dump_packet(p, pkt);
854                         return r;
855                 }
856
857                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
858                         tile_flags |= R300_DEPTHMACROTILE_ENABLE;
859                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
860                         tile_flags |= R300_DEPTHMICROTILE_TILED;
861                 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
862                         tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE;
863
864                 tmp = idx_value & ~(0x7 << 16);
865                 tmp |= tile_flags;
866                 ib[idx] = tmp;
867
868                 track->zb.pitch = idx_value & 0x3FFC;
869                 break;
870         case 0x4104:
871                 for (i = 0; i < 16; i++) {
872                         bool enabled;
873
874                         enabled = !!(idx_value & (1 << i));
875                         track->textures[i].enabled = enabled;
876                 }
877                 break;
878         case 0x44C0:
879         case 0x44C4:
880         case 0x44C8:
881         case 0x44CC:
882         case 0x44D0:
883         case 0x44D4:
884         case 0x44D8:
885         case 0x44DC:
886         case 0x44E0:
887         case 0x44E4:
888         case 0x44E8:
889         case 0x44EC:
890         case 0x44F0:
891         case 0x44F4:
892         case 0x44F8:
893         case 0x44FC:
894                 /* TX_FORMAT1_[0-15] */
895                 i = (reg - 0x44C0) >> 2;
896                 tmp = (idx_value >> 25) & 0x3;
897                 track->textures[i].tex_coord_type = tmp;
898                 switch ((idx_value & 0x1F)) {
899                 case R300_TX_FORMAT_X8:
900                 case R300_TX_FORMAT_Y4X4:
901                 case R300_TX_FORMAT_Z3Y3X2:
902                         track->textures[i].cpp = 1;
903                         break;
904                 case R300_TX_FORMAT_X16:
905                 case R300_TX_FORMAT_Y8X8:
906                 case R300_TX_FORMAT_Z5Y6X5:
907                 case R300_TX_FORMAT_Z6Y5X5:
908                 case R300_TX_FORMAT_W4Z4Y4X4:
909                 case R300_TX_FORMAT_W1Z5Y5X5:
910                 case R300_TX_FORMAT_D3DMFT_CxV8U8:
911                 case R300_TX_FORMAT_B8G8_B8G8:
912                 case R300_TX_FORMAT_G8R8_G8B8:
913                         track->textures[i].cpp = 2;
914                         break;
915                 case R300_TX_FORMAT_Y16X16:
916                 case R300_TX_FORMAT_Z11Y11X10:
917                 case R300_TX_FORMAT_Z10Y11X11:
918                 case R300_TX_FORMAT_W8Z8Y8X8:
919                 case R300_TX_FORMAT_W2Z10Y10X10:
920                 case 0x17:
921                 case R300_TX_FORMAT_FL_I32:
922                 case 0x1e:
923                         track->textures[i].cpp = 4;
924                         break;
925                 case R300_TX_FORMAT_W16Z16Y16X16:
926                 case R300_TX_FORMAT_FL_R16G16B16A16:
927                 case R300_TX_FORMAT_FL_I32A32:
928                         track->textures[i].cpp = 8;
929                         break;
930                 case R300_TX_FORMAT_FL_R32G32B32A32:
931                         track->textures[i].cpp = 16;
932                         break;
933                 case R300_TX_FORMAT_DXT1:
934                         track->textures[i].cpp = 1;
935                         track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
936                         break;
937                 case R300_TX_FORMAT_ATI2N:
938                         if (p->rdev->family < CHIP_R420) {
939                                 DRM_ERROR("Invalid texture format %u\n",
940                                           (idx_value & 0x1F));
941                                 return -EINVAL;
942                         }
943                         /* The same rules apply as for DXT3/5. */
944                         /* Pass through. */
945                 case R300_TX_FORMAT_DXT3:
946                 case R300_TX_FORMAT_DXT5:
947                         track->textures[i].cpp = 1;
948                         track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
949                         break;
950                 default:
951                         DRM_ERROR("Invalid texture format %u\n",
952                                   (idx_value & 0x1F));
953                         return -EINVAL;
954                         break;
955                 }
956                 break;
957         case 0x4400:
958         case 0x4404:
959         case 0x4408:
960         case 0x440C:
961         case 0x4410:
962         case 0x4414:
963         case 0x4418:
964         case 0x441C:
965         case 0x4420:
966         case 0x4424:
967         case 0x4428:
968         case 0x442C:
969         case 0x4430:
970         case 0x4434:
971         case 0x4438:
972         case 0x443C:
973                 /* TX_FILTER0_[0-15] */
974                 i = (reg - 0x4400) >> 2;
975                 tmp = idx_value & 0x7;
976                 if (tmp == 2 || tmp == 4 || tmp == 6) {
977                         track->textures[i].roundup_w = false;
978                 }
979                 tmp = (idx_value >> 3) & 0x7;
980                 if (tmp == 2 || tmp == 4 || tmp == 6) {
981                         track->textures[i].roundup_h = false;
982                 }
983                 break;
984         case 0x4500:
985         case 0x4504:
986         case 0x4508:
987         case 0x450C:
988         case 0x4510:
989         case 0x4514:
990         case 0x4518:
991         case 0x451C:
992         case 0x4520:
993         case 0x4524:
994         case 0x4528:
995         case 0x452C:
996         case 0x4530:
997         case 0x4534:
998         case 0x4538:
999         case 0x453C:
1000                 /* TX_FORMAT2_[0-15] */
1001                 i = (reg - 0x4500) >> 2;
1002                 tmp = idx_value & 0x3FFF;
1003                 track->textures[i].pitch = tmp + 1;
1004                 if (p->rdev->family >= CHIP_RV515) {
1005                         tmp = ((idx_value >> 15) & 1) << 11;
1006                         track->textures[i].width_11 = tmp;
1007                         tmp = ((idx_value >> 16) & 1) << 11;
1008                         track->textures[i].height_11 = tmp;
1009
1010                         /* ATI1N */
1011                         if (idx_value & (1 << 14)) {
1012                                 /* The same rules apply as for DXT1. */
1013                                 track->textures[i].compress_format =
1014                                         R100_TRACK_COMP_DXT1;
1015                         }
1016                 } else if (idx_value & (1 << 14)) {
1017                         DRM_ERROR("Forbidden bit TXFORMAT_MSB\n");
1018                         return -EINVAL;
1019                 }
1020                 break;
1021         case 0x4480:
1022         case 0x4484:
1023         case 0x4488:
1024         case 0x448C:
1025         case 0x4490:
1026         case 0x4494:
1027         case 0x4498:
1028         case 0x449C:
1029         case 0x44A0:
1030         case 0x44A4:
1031         case 0x44A8:
1032         case 0x44AC:
1033         case 0x44B0:
1034         case 0x44B4:
1035         case 0x44B8:
1036         case 0x44BC:
1037                 /* TX_FORMAT0_[0-15] */
1038                 i = (reg - 0x4480) >> 2;
1039                 tmp = idx_value & 0x7FF;
1040                 track->textures[i].width = tmp + 1;
1041                 tmp = (idx_value >> 11) & 0x7FF;
1042                 track->textures[i].height = tmp + 1;
1043                 tmp = (idx_value >> 26) & 0xF;
1044                 track->textures[i].num_levels = tmp;
1045                 tmp = idx_value & (1 << 31);
1046                 track->textures[i].use_pitch = !!tmp;
1047                 tmp = (idx_value >> 22) & 0xF;
1048                 track->textures[i].txdepth = tmp;
1049                 break;
1050         case R300_ZB_ZPASS_ADDR:
1051                 r = r100_cs_packet_next_reloc(p, &reloc);
1052                 if (r) {
1053                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1054                                         idx, reg);
1055                         r100_cs_dump_packet(p, pkt);
1056                         return r;
1057                 }
1058                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1059                 break;
1060         case 0x4e0c:
1061                 /* RB3D_COLOR_CHANNEL_MASK */
1062                 track->color_channel_mask = idx_value;
1063                 break;
1064         case 0x4d1c:
1065                 /* ZB_BW_CNTL */
1066                 track->fastfill = !!(idx_value & (1 << 2));
1067                 break;
1068         case 0x4e04:
1069                 /* RB3D_BLENDCNTL */
1070                 track->blend_read_enable = !!(idx_value & (1 << 2));
1071                 break;
1072         case 0x4be8:
1073                 /* valid register only on RV530 */
1074                 if (p->rdev->family == CHIP_RV530)
1075                         break;
1076                 /* fallthrough do not move */
1077         default:
1078                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1079                        reg, idx);
1080                 return -EINVAL;
1081         }
1082         return 0;
1083 }
1084
1085 static int r300_packet3_check(struct radeon_cs_parser *p,
1086                               struct radeon_cs_packet *pkt)
1087 {
1088         struct radeon_cs_reloc *reloc;
1089         struct r100_cs_track *track;
1090         volatile uint32_t *ib;
1091         unsigned idx;
1092         int r;
1093
1094         ib = p->ib->ptr;
1095         idx = pkt->idx + 1;
1096         track = (struct r100_cs_track *)p->track;
1097         switch(pkt->opcode) {
1098         case PACKET3_3D_LOAD_VBPNTR:
1099                 r = r100_packet3_load_vbpntr(p, pkt, idx);
1100                 if (r)
1101                         return r;
1102                 break;
1103         case PACKET3_INDX_BUFFER:
1104                 r = r100_cs_packet_next_reloc(p, &reloc);
1105                 if (r) {
1106                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1107                         r100_cs_dump_packet(p, pkt);
1108                         return r;
1109                 }
1110                 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1111                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1112                 if (r) {
1113                         return r;
1114                 }
1115                 break;
1116         /* Draw packet */
1117         case PACKET3_3D_DRAW_IMMD:
1118                 /* Number of dwords is vtx_size * (num_vertices - 1)
1119                  * PRIM_WALK must be equal to 3 vertex data in embedded
1120                  * in cmd stream */
1121                 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1122                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1123                         return -EINVAL;
1124                 }
1125                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1126                 track->immd_dwords = pkt->count - 1;
1127                 r = r100_cs_track_check(p->rdev, track);
1128                 if (r) {
1129                         return r;
1130                 }
1131                 break;
1132         case PACKET3_3D_DRAW_IMMD_2:
1133                 /* Number of dwords is vtx_size * (num_vertices - 1)
1134                  * PRIM_WALK must be equal to 3 vertex data in embedded
1135                  * in cmd stream */
1136                 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1137                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1138                         return -EINVAL;
1139                 }
1140                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1141                 track->immd_dwords = pkt->count;
1142                 r = r100_cs_track_check(p->rdev, track);
1143                 if (r) {
1144                         return r;
1145                 }
1146                 break;
1147         case PACKET3_3D_DRAW_VBUF:
1148                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1149                 r = r100_cs_track_check(p->rdev, track);
1150                 if (r) {
1151                         return r;
1152                 }
1153                 break;
1154         case PACKET3_3D_DRAW_VBUF_2:
1155                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1156                 r = r100_cs_track_check(p->rdev, track);
1157                 if (r) {
1158                         return r;
1159                 }
1160                 break;
1161         case PACKET3_3D_DRAW_INDX:
1162                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1163                 r = r100_cs_track_check(p->rdev, track);
1164                 if (r) {
1165                         return r;
1166                 }
1167                 break;
1168         case PACKET3_3D_DRAW_INDX_2:
1169                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1170                 r = r100_cs_track_check(p->rdev, track);
1171                 if (r) {
1172                         return r;
1173                 }
1174                 break;
1175         case PACKET3_NOP:
1176                 break;
1177         default:
1178                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1179                 return -EINVAL;
1180         }
1181         return 0;
1182 }
1183
1184 int r300_cs_parse(struct radeon_cs_parser *p)
1185 {
1186         struct radeon_cs_packet pkt;
1187         struct r100_cs_track *track;
1188         int r;
1189
1190         track = kzalloc(sizeof(*track), GFP_KERNEL);
1191         r100_cs_track_clear(p->rdev, track);
1192         p->track = track;
1193         do {
1194                 r = r100_cs_packet_parse(p, &pkt, p->idx);
1195                 if (r) {
1196                         return r;
1197                 }
1198                 p->idx += pkt.count + 2;
1199                 switch (pkt.type) {
1200                 case PACKET_TYPE0:
1201                         r = r100_cs_parse_packet0(p, &pkt,
1202                                                   p->rdev->config.r300.reg_safe_bm,
1203                                                   p->rdev->config.r300.reg_safe_bm_size,
1204                                                   &r300_packet0_check);
1205                         break;
1206                 case PACKET_TYPE2:
1207                         break;
1208                 case PACKET_TYPE3:
1209                         r = r300_packet3_check(p, &pkt);
1210                         break;
1211                 default:
1212                         DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1213                         return -EINVAL;
1214                 }
1215                 if (r) {
1216                         return r;
1217                 }
1218         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1219         return 0;
1220 }
1221
1222 void r300_set_reg_safe(struct radeon_device *rdev)
1223 {
1224         rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
1225         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
1226 }
1227
1228 void r300_mc_program(struct radeon_device *rdev)
1229 {
1230         struct r100_mc_save save;
1231         int r;
1232
1233         r = r100_debugfs_mc_info_init(rdev);
1234         if (r) {
1235                 dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n");
1236         }
1237
1238         /* Stops all mc clients */
1239         r100_mc_stop(rdev, &save);
1240         if (rdev->flags & RADEON_IS_AGP) {
1241                 WREG32(R_00014C_MC_AGP_LOCATION,
1242                         S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
1243                         S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
1244                 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
1245                 WREG32(R_00015C_AGP_BASE_2,
1246                         upper_32_bits(rdev->mc.agp_base) & 0xff);
1247         } else {
1248                 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
1249                 WREG32(R_000170_AGP_BASE, 0);
1250                 WREG32(R_00015C_AGP_BASE_2, 0);
1251         }
1252         /* Wait for mc idle */
1253         if (r300_mc_wait_for_idle(rdev))
1254                 DRM_INFO("Failed to wait MC idle before programming MC.\n");
1255         /* Program MC, should be a 32bits limited address space */
1256         WREG32(R_000148_MC_FB_LOCATION,
1257                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
1258                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
1259         r100_mc_resume(rdev, &save);
1260 }
1261
1262 void r300_clock_startup(struct radeon_device *rdev)
1263 {
1264         u32 tmp;
1265
1266         if (radeon_dynclks != -1 && radeon_dynclks)
1267                 radeon_legacy_set_clock_gating(rdev, 1);
1268         /* We need to force on some of the block */
1269         tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
1270         tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
1271         if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380))
1272                 tmp |= S_00000D_FORCE_VAP(1);
1273         WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
1274 }
1275
1276 static int r300_startup(struct radeon_device *rdev)
1277 {
1278         int r;
1279
1280         /* set common regs */
1281         r100_set_common_regs(rdev);
1282         /* program mc */
1283         r300_mc_program(rdev);
1284         /* Resume clock */
1285         r300_clock_startup(rdev);
1286         /* Initialize GPU configuration (# pipes, ...) */
1287         r300_gpu_init(rdev);
1288         /* Initialize GART (initialize after TTM so we can allocate
1289          * memory through TTM but finalize after TTM) */
1290         if (rdev->flags & RADEON_IS_PCIE) {
1291                 r = rv370_pcie_gart_enable(rdev);
1292                 if (r)
1293                         return r;
1294         }
1295
1296         if (rdev->family == CHIP_R300 ||
1297             rdev->family == CHIP_R350 ||
1298             rdev->family == CHIP_RV350)
1299                 r100_enable_bm(rdev);
1300
1301         if (rdev->flags & RADEON_IS_PCI) {
1302                 r = r100_pci_gart_enable(rdev);
1303                 if (r)
1304                         return r;
1305         }
1306         /* Enable IRQ */
1307         r100_irq_set(rdev);
1308         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1309         /* 1M ring buffer */
1310         r = r100_cp_init(rdev, 1024 * 1024);
1311         if (r) {
1312                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
1313                 return r;
1314         }
1315         r = r100_wb_init(rdev);
1316         if (r)
1317                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
1318         r = r100_ib_init(rdev);
1319         if (r) {
1320                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
1321                 return r;
1322         }
1323         return 0;
1324 }
1325
1326 int r300_resume(struct radeon_device *rdev)
1327 {
1328         /* Make sur GART are not working */
1329         if (rdev->flags & RADEON_IS_PCIE)
1330                 rv370_pcie_gart_disable(rdev);
1331         if (rdev->flags & RADEON_IS_PCI)
1332                 r100_pci_gart_disable(rdev);
1333         /* Resume clock before doing reset */
1334         r300_clock_startup(rdev);
1335         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1336         if (radeon_gpu_reset(rdev)) {
1337                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1338                         RREG32(R_000E40_RBBM_STATUS),
1339                         RREG32(R_0007C0_CP_STAT));
1340         }
1341         /* post */
1342         radeon_combios_asic_init(rdev->ddev);
1343         /* Resume clock after posting */
1344         r300_clock_startup(rdev);
1345         /* Initialize surface registers */
1346         radeon_surface_init(rdev);
1347         return r300_startup(rdev);
1348 }
1349
1350 int r300_suspend(struct radeon_device *rdev)
1351 {
1352         r100_cp_disable(rdev);
1353         r100_wb_disable(rdev);
1354         r100_irq_disable(rdev);
1355         if (rdev->flags & RADEON_IS_PCIE)
1356                 rv370_pcie_gart_disable(rdev);
1357         if (rdev->flags & RADEON_IS_PCI)
1358                 r100_pci_gart_disable(rdev);
1359         return 0;
1360 }
1361
1362 void r300_fini(struct radeon_device *rdev)
1363 {
1364         radeon_pm_fini(rdev);
1365         r100_cp_fini(rdev);
1366         r100_wb_fini(rdev);
1367         r100_ib_fini(rdev);
1368         radeon_gem_fini(rdev);
1369         if (rdev->flags & RADEON_IS_PCIE)
1370                 rv370_pcie_gart_fini(rdev);
1371         if (rdev->flags & RADEON_IS_PCI)
1372                 r100_pci_gart_fini(rdev);
1373         radeon_agp_fini(rdev);
1374         radeon_irq_kms_fini(rdev);
1375         radeon_fence_driver_fini(rdev);
1376         radeon_bo_fini(rdev);
1377         radeon_atombios_fini(rdev);
1378         kfree(rdev->bios);
1379         rdev->bios = NULL;
1380 }
1381
1382 int r300_init(struct radeon_device *rdev)
1383 {
1384         int r;
1385
1386         /* Disable VGA */
1387         r100_vga_render_disable(rdev);
1388         /* Initialize scratch registers */
1389         radeon_scratch_init(rdev);
1390         /* Initialize surface registers */
1391         radeon_surface_init(rdev);
1392         /* TODO: disable VGA need to use VGA request */
1393         /* BIOS*/
1394         if (!radeon_get_bios(rdev)) {
1395                 if (ASIC_IS_AVIVO(rdev))
1396                         return -EINVAL;
1397         }
1398         if (rdev->is_atom_bios) {
1399                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
1400                 return -EINVAL;
1401         } else {
1402                 r = radeon_combios_init(rdev);
1403                 if (r)
1404                         return r;
1405         }
1406         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1407         if (radeon_gpu_reset(rdev)) {
1408                 dev_warn(rdev->dev,
1409                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1410                         RREG32(R_000E40_RBBM_STATUS),
1411                         RREG32(R_0007C0_CP_STAT));
1412         }
1413         /* check if cards are posted or not */
1414         if (radeon_boot_test_post_card(rdev) == false)
1415                 return -EINVAL;
1416         /* Set asic errata */
1417         r300_errata(rdev);
1418         /* Initialize clocks */
1419         radeon_get_clock_info(rdev->ddev);
1420         /* Initialize power management */
1421         radeon_pm_init(rdev);
1422         /* initialize AGP */
1423         if (rdev->flags & RADEON_IS_AGP) {
1424                 r = radeon_agp_init(rdev);
1425                 if (r) {
1426                         radeon_agp_disable(rdev);
1427                 }
1428         }
1429         /* initialize memory controller */
1430         r300_mc_init(rdev);
1431         /* Fence driver */
1432         r = radeon_fence_driver_init(rdev);
1433         if (r)
1434                 return r;
1435         r = radeon_irq_kms_init(rdev);
1436         if (r)
1437                 return r;
1438         /* Memory manager */
1439         r = radeon_bo_init(rdev);
1440         if (r)
1441                 return r;
1442         if (rdev->flags & RADEON_IS_PCIE) {
1443                 r = rv370_pcie_gart_init(rdev);
1444                 if (r)
1445                         return r;
1446         }
1447         if (rdev->flags & RADEON_IS_PCI) {
1448                 r = r100_pci_gart_init(rdev);
1449                 if (r)
1450                         return r;
1451         }
1452         r300_set_reg_safe(rdev);
1453         rdev->accel_working = true;
1454         r = r300_startup(rdev);
1455         if (r) {
1456                 /* Somethings want wront with the accel init stop accel */
1457                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
1458                 r100_cp_fini(rdev);
1459                 r100_wb_fini(rdev);
1460                 r100_ib_fini(rdev);
1461                 radeon_irq_kms_fini(rdev);
1462                 if (rdev->flags & RADEON_IS_PCIE)
1463                         rv370_pcie_gart_fini(rdev);
1464                 if (rdev->flags & RADEON_IS_PCI)
1465                         r100_pci_gart_fini(rdev);
1466                 radeon_agp_fini(rdev);
1467                 rdev->accel_working = false;
1468         }
1469         return 0;
1470 }