SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/r100.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "radeon_drm.h"
  32 #include "radeon_reg.h"
  33 #include "radeon.h"
  34 #include "radeon_asic.h"
  35 #include "r100d.h"
  36 #include "rs100d.h"
  37 #include "rv200d.h"
  38 #include "rv250d.h"
  39
  40 #include <linux/firmware.h>
  41 #include <linux/platform_device.h>
  42
  43 #include "r100_reg_safe.h"
  44 #include "rn50_reg_safe.h"
  45
  46 /* Firmware Names */
  47 #define FIRMWARE_R100           "radeon/R100_cp.bin"
  48 #define FIRMWARE_R200           "radeon/R200_cp.bin"
  49 #define FIRMWARE_R300           "radeon/R300_cp.bin"
  50 #define FIRMWARE_R420           "radeon/R420_cp.bin"
  51 #define FIRMWARE_RS690          "radeon/RS690_cp.bin"
  52 #define FIRMWARE_RS600          "radeon/RS600_cp.bin"
  53 #define FIRMWARE_R520           "radeon/R520_cp.bin"
  54
  55 MODULE_FIRMWARE(FIRMWARE_R100);
  56 MODULE_FIRMWARE(FIRMWARE_R200);
  57 MODULE_FIRMWARE(FIRMWARE_R300);
  58 MODULE_FIRMWARE(FIRMWARE_R420);
  59 MODULE_FIRMWARE(FIRMWARE_RS690);
  60 MODULE_FIRMWARE(FIRMWARE_RS600);
  61 MODULE_FIRMWARE(FIRMWARE_R520);
  62
  63 #include "r100_track.h"
  64
  65 /* This files gather functions specifics to:
  66  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
  67  */
  68
  69 /* hpd for digital panel detect/disconnect */
  70 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
  71 {
  72         bool connected = false;
  73
  74         switch (hpd) {
  75         case RADEON_HPD_1:
  76                 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
  77                         connected = true;
  78                 break;
  79         case RADEON_HPD_2:
  80                 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
  81                         connected = true;
  82                 break;
  83         default:
  84                 break;
  85         }
  86         return connected;
  87 }
  88
  89 void r100_hpd_set_polarity(struct radeon_device *rdev,
  90                            enum radeon_hpd_id hpd)
  91 {
  92         u32 tmp;
  93         bool connected = r100_hpd_sense(rdev, hpd);
  94
  95         switch (hpd) {
  96         case RADEON_HPD_1:
  97                 tmp = RREG32(RADEON_FP_GEN_CNTL);
  98                 if (connected)
  99                         tmp &= ~RADEON_FP_DETECT_INT_POL;
 100                 else
 101                         tmp |= RADEON_FP_DETECT_INT_POL;
 102                 WREG32(RADEON_FP_GEN_CNTL, tmp);
 103                 break;
 104         case RADEON_HPD_2:
 105                 tmp = RREG32(RADEON_FP2_GEN_CNTL);
 106                 if (connected)
 107                         tmp &= ~RADEON_FP2_DETECT_INT_POL;
 108                 else
 109                         tmp |= RADEON_FP2_DETECT_INT_POL;
 110                 WREG32(RADEON_FP2_GEN_CNTL, tmp);
 111                 break;
 112         default:
 113                 break;
 114         }
 115 }
 116
 117 void r100_hpd_init(struct radeon_device *rdev)
 118 {
 119         struct drm_device *dev = rdev->ddev;
 120         struct drm_connector *connector;
 121
 122         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 123                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 124                 switch (radeon_connector->hpd.hpd) {
 125                 case RADEON_HPD_1:
 126                         rdev->irq.hpd[0] = true;
 127                         break;
 128                 case RADEON_HPD_2:
 129                         rdev->irq.hpd[1] = true;
 130                         break;
 131                 default:
 132                         break;
 133                 }
 134         }
 135         if (rdev->irq.installed)
 136                 r100_irq_set(rdev);
 137 }
 138
 139 void r100_hpd_fini(struct radeon_device *rdev)
 140 {
 141         struct drm_device *dev = rdev->ddev;
 142         struct drm_connector *connector;
 143
 144         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 145                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 146                 switch (radeon_connector->hpd.hpd) {
 147                 case RADEON_HPD_1:
 148                         rdev->irq.hpd[0] = false;
 149                         break;
 150                 case RADEON_HPD_2:
 151                         rdev->irq.hpd[1] = false;
 152                         break;
 153                 default:
 154                         break;
 155                 }
 156         }
 157 }
 158
 159 /*
 160  * PCI GART
 161  */
 162 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
 163 {
 164         /* TODO: can we do somethings here ? */
 165         /* It seems hw only cache one entry so we should discard this
 166          * entry otherwise if first GPU GART read hit this entry it
 167          * could end up in wrong address. */
 168 }
 169
 170 int r100_pci_gart_init(struct radeon_device *rdev)
 171 {
 172         int r;
 173
 174         if (rdev->gart.table.ram.ptr) {
 175                 WARN(1, "R100 PCI GART already initialized.\n");
 176                 return 0;
 177         }
 178         /* Initialize common gart structure */
 179         r = radeon_gart_init(rdev);
 180         if (r)
 181                 return r;
 182         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
 183         rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
 184         rdev->asic->gart_set_page = &r100_pci_gart_set_page;
 185         return radeon_gart_table_ram_alloc(rdev);
 186 }
 187
 188 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
 189 void r100_enable_bm(struct radeon_device *rdev)
 190 {
 191         uint32_t tmp;
 192         /* Enable bus mastering */
 193         tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 194         WREG32(RADEON_BUS_CNTL, tmp);
 195 }
 196
 197 int r100_pci_gart_enable(struct radeon_device *rdev)
 198 {
 199         uint32_t tmp;
 200
 201         radeon_gart_restore(rdev);
 202         /* discard memory request outside of configured range */
 203         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 204         WREG32(RADEON_AIC_CNTL, tmp);
 205         /* set address range for PCI address translate */
 206         WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
 207         WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
 208         /* set PCI GART page-table base address */
 209         WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
 210         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
 211         WREG32(RADEON_AIC_CNTL, tmp);
 212         r100_pci_gart_tlb_flush(rdev);
 213         rdev->gart.ready = true;
 214         return 0;
 215 }
 216
 217 void r100_pci_gart_disable(struct radeon_device *rdev)
 218 {
 219         uint32_t tmp;
 220
 221         /* discard memory request outside of configured range */
 222         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 223         WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
 224         WREG32(RADEON_AIC_LO_ADDR, 0);
 225         WREG32(RADEON_AIC_HI_ADDR, 0);
 226 }
 227
 228 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
 229 {
 230         if (i < 0 || i > rdev->gart.num_gpu_pages) {
 231                 return -EINVAL;
 232         }
 233         rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
 234         return 0;
 235 }
 236
 237 void r100_pci_gart_fini(struct radeon_device *rdev)
 238 {
 239         r100_pci_gart_disable(rdev);
 240         radeon_gart_table_ram_free(rdev);
 241         radeon_gart_fini(rdev);
 242 }
 243
 244 int r100_irq_set(struct radeon_device *rdev)
 245 {
 246         uint32_t tmp = 0;
 247
 248         if (!rdev->irq.installed) {
 249                 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
 250                 WREG32(R_000040_GEN_INT_CNTL, 0);
 251                 return -EINVAL;
 252         }
 253         if (rdev->irq.sw_int) {
 254                 tmp |= RADEON_SW_INT_ENABLE;
 255         }
 256         if (rdev->irq.crtc_vblank_int[0]) {
 257                 tmp |= RADEON_CRTC_VBLANK_MASK;
 258         }
 259         if (rdev->irq.crtc_vblank_int[1]) {
 260                 tmp |= RADEON_CRTC2_VBLANK_MASK;
 261         }
 262         if (rdev->irq.hpd[0]) {
 263                 tmp |= RADEON_FP_DETECT_MASK;
 264         }
 265         if (rdev->irq.hpd[1]) {
 266                 tmp |= RADEON_FP2_DETECT_MASK;
 267         }
 268         WREG32(RADEON_GEN_INT_CNTL, tmp);
 269         return 0;
 270 }
 271
 272 void r100_irq_disable(struct radeon_device *rdev)
 273 {
 274         u32 tmp;
 275
 276         WREG32(R_000040_GEN_INT_CNTL, 0);
 277         /* Wait and acknowledge irq */
 278         mdelay(1);
 279         tmp = RREG32(R_000044_GEN_INT_STATUS);
 280         WREG32(R_000044_GEN_INT_STATUS, tmp);
 281 }
 282
 283 static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
 284 {
 285         uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
 286         uint32_t irq_mask = RADEON_SW_INT_TEST |
 287                 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
 288                 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
 289
 290         if (irqs) {
 291                 WREG32(RADEON_GEN_INT_STATUS, irqs);
 292         }
 293         return irqs & irq_mask;
 294 }
 295
 296 int r100_irq_process(struct radeon_device *rdev)
 297 {
 298         uint32_t status, msi_rearm;
 299         bool queue_hotplug = false;
 300
 301         status = r100_irq_ack(rdev);
 302         if (!status) {
 303                 return IRQ_NONE;
 304         }
 305         if (rdev->shutdown) {
 306                 return IRQ_NONE;
 307         }
 308         while (status) {
 309                 /* SW interrupt */
 310                 if (status & RADEON_SW_INT_TEST) {
 311                         radeon_fence_process(rdev);
 312                 }
 313                 /* Vertical blank interrupts */
 314                 if (status & RADEON_CRTC_VBLANK_STAT) {
 315                         drm_handle_vblank(rdev->ddev, 0);
 316                         rdev->pm.vblank_sync = true;
 317                         wake_up(&rdev->irq.vblank_queue);
 318                 }
 319                 if (status & RADEON_CRTC2_VBLANK_STAT) {
 320                         drm_handle_vblank(rdev->ddev, 1);
 321                         rdev->pm.vblank_sync = true;
 322                         wake_up(&rdev->irq.vblank_queue);
 323                 }
 324                 if (status & RADEON_FP_DETECT_STAT) {
 325                         queue_hotplug = true;
 326                         DRM_DEBUG("HPD1\n");
 327                 }
 328                 if (status & RADEON_FP2_DETECT_STAT) {
 329                         queue_hotplug = true;
 330                         DRM_DEBUG("HPD2\n");
 331                 }
 332                 status = r100_irq_ack(rdev);
 333         }
 334         if (queue_hotplug)
 335                 queue_work(rdev->wq, &rdev->hotplug_work);
 336         if (rdev->msi_enabled) {
 337                 switch (rdev->family) {
 338                 case CHIP_RS400:
 339                 case CHIP_RS480:
 340                         msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
 341                         WREG32(RADEON_AIC_CNTL, msi_rearm);
 342                         WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
 343                         break;
 344                 default:
 345                         msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
 346                         WREG32(RADEON_MSI_REARM_EN, msi_rearm);
 347                         WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
 348                         break;
 349                 }
 350         }
 351         return IRQ_HANDLED;
 352 }
 353
 354 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
 355 {
 356         if (crtc == 0)
 357                 return RREG32(RADEON_CRTC_CRNT_FRAME);
 358         else
 359                 return RREG32(RADEON_CRTC2_CRNT_FRAME);
 360 }
 361
 362 /* Who ever call radeon_fence_emit should call ring_lock and ask
 363  * for enough space (today caller are ib schedule and buffer move) */
 364 void r100_fence_ring_emit(struct radeon_device *rdev,
 365                           struct radeon_fence *fence)
 366 {
 367         /* We have to make sure that caches are flushed before
 368          * CPU might read something from VRAM. */
 369         radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
 370         radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
 371         radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
 372         radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
 373         /* Wait until IDLE & CLEAN */
 374         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 375         radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
 376         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 377         radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
 378                                 RADEON_HDP_READ_BUFFER_INVALIDATE);
 379         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 380         radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
 381         /* Emit fence sequence & fire IRQ */
 382         radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
 383         radeon_ring_write(rdev, fence->seq);
 384         radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
 385         radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
 386 }
 387
 388 int r100_wb_init(struct radeon_device *rdev)
 389 {
 390         int r;
 391
 392         if (rdev->wb.wb_obj == NULL) {
 393                 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
 394                                         RADEON_GEM_DOMAIN_GTT,
 395                                         &rdev->wb.wb_obj);
 396                 if (r) {
 397                         dev_err(rdev->dev, "(%d) create WB buffer failed\n", r);
 398                         return r;
 399                 }
 400                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
 401                 if (unlikely(r != 0))
 402                         return r;
 403                 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
 404                                         &rdev->wb.gpu_addr);
 405                 if (r) {
 406                         dev_err(rdev->dev, "(%d) pin WB buffer failed\n", r);
 407                         radeon_bo_unreserve(rdev->wb.wb_obj);
 408                         return r;
 409                 }
 410                 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
 411                 radeon_bo_unreserve(rdev->wb.wb_obj);
 412                 if (r) {
 413                         dev_err(rdev->dev, "(%d) map WB buffer failed\n", r);
 414                         return r;
 415                 }
 416         }
 417         WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
 418         WREG32(R_00070C_CP_RB_RPTR_ADDR,
 419                 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
 420         WREG32(R_000770_SCRATCH_UMSK, 0xff);
 421         return 0;
 422 }
 423
 424 void r100_wb_disable(struct radeon_device *rdev)
 425 {
 426         WREG32(R_000770_SCRATCH_UMSK, 0);
 427 }
 428
 429 void r100_wb_fini(struct radeon_device *rdev)
 430 {
 431         int r;
 432
 433         r100_wb_disable(rdev);
 434         if (rdev->wb.wb_obj) {
 435                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
 436                 if (unlikely(r != 0)) {
 437                         dev_err(rdev->dev, "(%d) can't finish WB\n", r);
 438                         return;
 439                 }
 440                 radeon_bo_kunmap(rdev->wb.wb_obj);
 441                 radeon_bo_unpin(rdev->wb.wb_obj);
 442                 radeon_bo_unreserve(rdev->wb.wb_obj);
 443                 radeon_bo_unref(&rdev->wb.wb_obj);
 444                 rdev->wb.wb = NULL;
 445                 rdev->wb.wb_obj = NULL;
 446         }
 447 }
 448
 449 int r100_copy_blit(struct radeon_device *rdev,
 450                    uint64_t src_offset,
 451                    uint64_t dst_offset,
 452                    unsigned num_pages,
 453                    struct radeon_fence *fence)
 454 {
 455         uint32_t cur_pages;
 456         uint32_t stride_bytes = PAGE_SIZE;
 457         uint32_t pitch;
 458         uint32_t stride_pixels;
 459         unsigned ndw;
 460         int num_loops;
 461         int r = 0;
 462
 463         /* radeon limited to 16k stride */
 464         stride_bytes &= 0x3fff;
 465         /* radeon pitch is /64 */
 466         pitch = stride_bytes / 64;
 467         stride_pixels = stride_bytes / 4;
 468         num_loops = DIV_ROUND_UP(num_pages, 8191);
 469
 470         /* Ask for enough room for blit + flush + fence */
 471         ndw = 64 + (10 * num_loops);
 472         r = radeon_ring_lock(rdev, ndw);
 473         if (r) {
 474                 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
 475                 return -EINVAL;
 476         }
 477         while (num_pages > 0) {
 478                 cur_pages = num_pages;
 479                 if (cur_pages > 8191) {
 480                         cur_pages = 8191;
 481                 }
 482                 num_pages -= cur_pages;
 483
 484                 /* pages are in Y direction - height
 485                    page width in X direction - width */
 486                 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
 487                 radeon_ring_write(rdev,
 488                                   RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
 489                                   RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 490                                   RADEON_GMC_SRC_CLIPPING |
 491                                   RADEON_GMC_DST_CLIPPING |
 492                                   RADEON_GMC_BRUSH_NONE |
 493                                   (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
 494                                   RADEON_GMC_SRC_DATATYPE_COLOR |
 495                                   RADEON_ROP3_S |
 496                                   RADEON_DP_SRC_SOURCE_MEMORY |
 497                                   RADEON_GMC_CLR_CMP_CNTL_DIS |
 498                                   RADEON_GMC_WR_MSK_DIS);
 499                 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
 500                 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
 501                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
 502                 radeon_ring_write(rdev, 0);
 503                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
 504                 radeon_ring_write(rdev, num_pages);
 505                 radeon_ring_write(rdev, num_pages);
 506                 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
 507         }
 508         radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
 509         radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
 510         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 511         radeon_ring_write(rdev,
 512                           RADEON_WAIT_2D_IDLECLEAN |
 513                           RADEON_WAIT_HOST_IDLECLEAN |
 514                           RADEON_WAIT_DMA_GUI_IDLE);
 515         if (fence) {
 516                 r = radeon_fence_emit(rdev, fence);
 517         }
 518         radeon_ring_unlock_commit(rdev);
 519         return r;
 520 }
 521
 522 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
 523 {
 524         unsigned i;
 525         u32 tmp;
 526
 527         for (i = 0; i < rdev->usec_timeout; i++) {
 528                 tmp = RREG32(R_000E40_RBBM_STATUS);
 529                 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
 530                         return 0;
 531                 }
 532                 udelay(1);
 533         }
 534         return -1;
 535 }
 536
 537 void r100_ring_start(struct radeon_device *rdev)
 538 {
 539         int r;
 540
 541         r = radeon_ring_lock(rdev, 2);
 542         if (r) {
 543                 return;
 544         }
 545         radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
 546         radeon_ring_write(rdev,
 547                           RADEON_ISYNC_ANY2D_IDLE3D |
 548                           RADEON_ISYNC_ANY3D_IDLE2D |
 549                           RADEON_ISYNC_WAIT_IDLEGUI |
 550                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 551         radeon_ring_unlock_commit(rdev);
 552 }
 553
 554
 555 /* Load the microcode for the CP */
 556 static int r100_cp_init_microcode(struct radeon_device *rdev)
 557 {
 558         struct platform_device *pdev;
 559         const char *fw_name = NULL;
 560         int err;
 561
 562         DRM_DEBUG("\n");
 563
 564         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
 565         err = IS_ERR(pdev);
 566         if (err) {
 567                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
 568                 return -EINVAL;
 569         }
 570         if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
 571             (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
 572             (rdev->family == CHIP_RS200)) {
 573                 DRM_INFO("Loading R100 Microcode\n");
 574                 fw_name = FIRMWARE_R100;
 575         } else if ((rdev->family == CHIP_R200) ||
 576                    (rdev->family == CHIP_RV250) ||
 577                    (rdev->family == CHIP_RV280) ||
 578                    (rdev->family == CHIP_RS300)) {
 579                 DRM_INFO("Loading R200 Microcode\n");
 580                 fw_name = FIRMWARE_R200;
 581         } else if ((rdev->family == CHIP_R300) ||
 582                    (rdev->family == CHIP_R350) ||
 583                    (rdev->family == CHIP_RV350) ||
 584                    (rdev->family == CHIP_RV380) ||
 585                    (rdev->family == CHIP_RS400) ||
 586                    (rdev->family == CHIP_RS480)) {
 587                 DRM_INFO("Loading R300 Microcode\n");
 588                 fw_name = FIRMWARE_R300;
 589         } else if ((rdev->family == CHIP_R420) ||
 590                    (rdev->family == CHIP_R423) ||
 591                    (rdev->family == CHIP_RV410)) {
 592                 DRM_INFO("Loading R400 Microcode\n");
 593                 fw_name = FIRMWARE_R420;
 594         } else if ((rdev->family == CHIP_RS690) ||
 595                    (rdev->family == CHIP_RS740)) {
 596                 DRM_INFO("Loading RS690/RS740 Microcode\n");
 597                 fw_name = FIRMWARE_RS690;
 598         } else if (rdev->family == CHIP_RS600) {
 599                 DRM_INFO("Loading RS600 Microcode\n");
 600                 fw_name = FIRMWARE_RS600;
 601         } else if ((rdev->family == CHIP_RV515) ||
 602                    (rdev->family == CHIP_R520) ||
 603                    (rdev->family == CHIP_RV530) ||
 604                    (rdev->family == CHIP_R580) ||
 605                    (rdev->family == CHIP_RV560) ||
 606                    (rdev->family == CHIP_RV570)) {
 607                 DRM_INFO("Loading R500 Microcode\n");
 608                 fw_name = FIRMWARE_R520;
 609         }
 610
 611         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
 612         platform_device_unregister(pdev);
 613         if (err) {
 614                 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
 615                        fw_name);
 616         } else if (rdev->me_fw->size % 8) {
 617                 printk(KERN_ERR
 618                        "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
 619                        rdev->me_fw->size, fw_name);
 620                 err = -EINVAL;
 621                 release_firmware(rdev->me_fw);
 622                 rdev->me_fw = NULL;
 623         }
 624         return err;
 625 }
 626
 627 static void r100_cp_load_microcode(struct radeon_device *rdev)
 628 {
 629         const __be32 *fw_data;
 630         int i, size;
 631
 632         if (r100_gui_wait_for_idle(rdev)) {
 633                 printk(KERN_WARNING "Failed to wait GUI idle while "
 634                        "programming pipes. Bad things might happen.\n");
 635         }
 636
 637         if (rdev->me_fw) {
 638                 size = rdev->me_fw->size / 4;
 639                 fw_data = (const __be32 *)&rdev->me_fw->data[0];
 640                 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
 641                 for (i = 0; i < size; i += 2) {
 642                         WREG32(RADEON_CP_ME_RAM_DATAH,
 643                                be32_to_cpup(&fw_data[i]));
 644                         WREG32(RADEON_CP_ME_RAM_DATAL,
 645                                be32_to_cpup(&fw_data[i + 1]));
 646                 }
 647         }
 648 }
 649
 650 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
 651 {
 652         unsigned rb_bufsz;
 653         unsigned rb_blksz;
 654         unsigned max_fetch;
 655         unsigned pre_write_timer;
 656         unsigned pre_write_limit;
 657         unsigned indirect2_start;
 658         unsigned indirect1_start;
 659         uint32_t tmp;
 660         int r;
 661
 662         if (r100_debugfs_cp_init(rdev)) {
 663                 DRM_ERROR("Failed to register debugfs file for CP !\n");
 664         }
 665         /* Reset CP */
 666         tmp = RREG32(RADEON_CP_CSQ_STAT);
 667         if ((tmp & (1 << 31))) {
 668                 DRM_INFO("radeon: cp busy (0x%08X) resetting\n", tmp);
 669                 WREG32(RADEON_CP_CSQ_MODE, 0);
 670                 WREG32(RADEON_CP_CSQ_CNTL, 0);
 671                 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
 672                 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
 673                 mdelay(2);
 674                 WREG32(RADEON_RBBM_SOFT_RESET, 0);
 675                 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
 676                 mdelay(2);
 677                 tmp = RREG32(RADEON_CP_CSQ_STAT);
 678                 if ((tmp & (1 << 31))) {
 679                         DRM_INFO("radeon: cp reset failed (0x%08X)\n", tmp);
 680                 }
 681         } else {
 682                 DRM_INFO("radeon: cp idle (0x%08X)\n", tmp);
 683         }
 684
 685         if (!rdev->me_fw) {
 686                 r = r100_cp_init_microcode(rdev);
 687                 if (r) {
 688                         DRM_ERROR("Failed to load firmware!\n");
 689                         return r;
 690                 }
 691         }
 692
 693         /* Align ring size */
 694         rb_bufsz = drm_order(ring_size / 8);
 695         ring_size = (1 << (rb_bufsz + 1)) * 4;
 696         r100_cp_load_microcode(rdev);
 697         r = radeon_ring_init(rdev, ring_size);
 698         if (r) {
 699                 return r;
 700         }
 701         /* Each time the cp read 1024 bytes (16 dword/quadword) update
 702          * the rptr copy in system ram */
 703         rb_blksz = 9;
 704         /* cp will read 128bytes at a time (4 dwords) */
 705         max_fetch = 1;
 706         rdev->cp.align_mask = 16 - 1;
 707         /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
 708         pre_write_timer = 64;
 709         /* Force CP_RB_WPTR write if written more than one time before the
 710          * delay expire
 711          */
 712         pre_write_limit = 0;
 713         /* Setup the cp cache like this (cache size is 96 dwords) :
 714          *      RING            0  to 15
 715          *      INDIRECT1       16 to 79
 716          *      INDIRECT2       80 to 95
 717          * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
 718          *    indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
 719          *    indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
 720          * Idea being that most of the gpu cmd will be through indirect1 buffer
 721          * so it gets the bigger cache.
 722          */
 723         indirect2_start = 80;
 724         indirect1_start = 16;
 725         /* cp setup */
 726         WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
 727         tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
 728                REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
 729                REG_SET(RADEON_MAX_FETCH, max_fetch) |
 730                RADEON_RB_NO_UPDATE);
 731 #ifdef __BIG_ENDIAN
 732         tmp |= RADEON_BUF_SWAP_32BIT;
 733 #endif
 734         WREG32(RADEON_CP_RB_CNTL, tmp);
 735
 736         /* Set ring address */
 737         DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
 738         WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
 739         /* Force read & write ptr to 0 */
 740         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
 741         WREG32(RADEON_CP_RB_RPTR_WR, 0);
 742         WREG32(RADEON_CP_RB_WPTR, 0);
 743         WREG32(RADEON_CP_RB_CNTL, tmp);
 744         udelay(10);
 745         rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
 746         rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
 747         /* Set cp mode to bus mastering & enable cp*/
 748         WREG32(RADEON_CP_CSQ_MODE,
 749                REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
 750                REG_SET(RADEON_INDIRECT1_START, indirect1_start));
 751         WREG32(0x718, 0);
 752         WREG32(0x744, 0x00004D4D);
 753         WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
 754         radeon_ring_start(rdev);
 755         r = radeon_ring_test(rdev);
 756         if (r) {
 757                 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
 758                 return r;
 759         }
 760         rdev->cp.ready = true;
 761         return 0;
 762 }
 763
 764 void r100_cp_fini(struct radeon_device *rdev)
 765 {
 766         if (r100_cp_wait_for_idle(rdev)) {
 767                 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
 768         }
 769         /* Disable ring */
 770         r100_cp_disable(rdev);
 771         radeon_ring_fini(rdev);
 772         DRM_INFO("radeon: cp finalized\n");
 773 }
 774
 775 void r100_cp_disable(struct radeon_device *rdev)
 776 {
 777         /* Disable ring */
 778         rdev->cp.ready = false;
 779         WREG32(RADEON_CP_CSQ_MODE, 0);
 780         WREG32(RADEON_CP_CSQ_CNTL, 0);
 781         if (r100_gui_wait_for_idle(rdev)) {
 782                 printk(KERN_WARNING "Failed to wait GUI idle while "
 783                        "programming pipes. Bad things might happen.\n");
 784         }
 785 }
 786
 787 int r100_cp_reset(struct radeon_device *rdev)
 788 {
 789         uint32_t tmp;
 790         bool reinit_cp;
 791         int i;
 792
 793         reinit_cp = rdev->cp.ready;
 794         rdev->cp.ready = false;
 795         WREG32(RADEON_CP_CSQ_MODE, 0);
 796         WREG32(RADEON_CP_CSQ_CNTL, 0);
 797         WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
 798         (void)RREG32(RADEON_RBBM_SOFT_RESET);
 799         udelay(200);
 800         WREG32(RADEON_RBBM_SOFT_RESET, 0);
 801         /* Wait to prevent race in RBBM_STATUS */
 802         mdelay(1);
 803         for (i = 0; i < rdev->usec_timeout; i++) {
 804                 tmp = RREG32(RADEON_RBBM_STATUS);
 805                 if (!(tmp & (1 << 16))) {
 806                         DRM_INFO("CP reset succeed (RBBM_STATUS=0x%08X)\n",
 807                                  tmp);
 808                         if (reinit_cp) {
 809                                 return r100_cp_init(rdev, rdev->cp.ring_size);
 810                         }
 811                         return 0;
 812                 }
 813                 DRM_UDELAY(1);
 814         }
 815         tmp = RREG32(RADEON_RBBM_STATUS);
 816         DRM_ERROR("Failed to reset CP (RBBM_STATUS=0x%08X)!\n", tmp);
 817         return -1;
 818 }
 819
 820 void r100_cp_commit(struct radeon_device *rdev)
 821 {
 822         WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
 823         (void)RREG32(RADEON_CP_RB_WPTR);
 824 }
 825
 826
 827 /*
 828  * CS functions
 829  */
 830 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
 831                           struct radeon_cs_packet *pkt,
 832                           const unsigned *auth, unsigned n,
 833                           radeon_packet0_check_t check)
 834 {
 835         unsigned reg;
 836         unsigned i, j, m;
 837         unsigned idx;
 838         int r;
 839
 840         idx = pkt->idx + 1;
 841         reg = pkt->reg;
 842         /* Check that register fall into register range
 843          * determined by the number of entry (n) in the
 844          * safe register bitmap.
 845          */
 846         if (pkt->one_reg_wr) {
 847                 if ((reg >> 7) > n) {
 848                         return -EINVAL;
 849                 }
 850         } else {
 851                 if (((reg + (pkt->count << 2)) >> 7) > n) {
 852                         return -EINVAL;
 853                 }
 854         }
 855         for (i = 0; i <= pkt->count; i++, idx++) {
 856                 j = (reg >> 7);
 857                 m = 1 << ((reg >> 2) & 31);
 858                 if (auth[j] & m) {
 859                         r = check(p, pkt, idx, reg);
 860                         if (r) {
 861                                 return r;
 862                         }
 863                 }
 864                 if (pkt->one_reg_wr) {
 865                         if (!(auth[j] & m)) {
 866                                 break;
 867                         }
 868                 } else {
 869                         reg += 4;
 870                 }
 871         }
 872         return 0;
 873 }
 874
 875 void r100_cs_dump_packet(struct radeon_cs_parser *p,
 876                          struct radeon_cs_packet *pkt)
 877 {
 878         volatile uint32_t *ib;
 879         unsigned i;
 880         unsigned idx;
 881
 882         ib = p->ib->ptr;
 883         idx = pkt->idx;
 884         for (i = 0; i <= (pkt->count + 1); i++, idx++) {
 885                 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
 886         }
 887 }
 888
 889 /**
 890  * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
 891  * @parser:     parser structure holding parsing context.
 892  * @pkt:        where to store packet informations
 893  *
 894  * Assume that chunk_ib_index is properly set. Will return -EINVAL
 895  * if packet is bigger than remaining ib size. or if packets is unknown.
 896  **/
 897 int r100_cs_packet_parse(struct radeon_cs_parser *p,
 898                          struct radeon_cs_packet *pkt,
 899                          unsigned idx)
 900 {
 901         struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
 902         uint32_t header;
 903
 904         if (idx >= ib_chunk->length_dw) {
 905                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
 906                           idx, ib_chunk->length_dw);
 907                 return -EINVAL;
 908         }
 909         header = radeon_get_ib_value(p, idx);
 910         pkt->idx = idx;
 911         pkt->type = CP_PACKET_GET_TYPE(header);
 912         pkt->count = CP_PACKET_GET_COUNT(header);
 913         switch (pkt->type) {
 914         case PACKET_TYPE0:
 915                 pkt->reg = CP_PACKET0_GET_REG(header);
 916                 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
 917                 break;
 918         case PACKET_TYPE3:
 919                 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
 920                 break;
 921         case PACKET_TYPE2:
 922                 pkt->count = -1;
 923                 break;
 924         default:
 925                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
 926                 return -EINVAL;
 927         }
 928         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
 929                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
 930                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
 931                 return -EINVAL;
 932         }
 933         return 0;
 934 }
 935
 936 /**
 937  * r100_cs_packet_next_vline() - parse userspace VLINE packet
 938  * @parser:             parser structure holding parsing context.
 939  *
 940  * Userspace sends a special sequence for VLINE waits.
 941  * PACKET0 - VLINE_START_END + value
 942  * PACKET0 - WAIT_UNTIL +_value
 943  * RELOC (P3) - crtc_id in reloc.
 944  *
 945  * This function parses this and relocates the VLINE START END
 946  * and WAIT UNTIL packets to the correct crtc.
 947  * It also detects a switched off crtc and nulls out the
 948  * wait in that case.
 949  */
 950 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
 951 {
 952         struct drm_mode_object *obj;
 953         struct drm_crtc *crtc;
 954         struct radeon_crtc *radeon_crtc;
 955         struct radeon_cs_packet p3reloc, waitreloc;
 956         int crtc_id;
 957         int r;
 958         uint32_t header, h_idx, reg;
 959         volatile uint32_t *ib;
 960
 961         ib = p->ib->ptr;
 962
 963         /* parse the wait until */
 964         r = r100_cs_packet_parse(p, &waitreloc, p->idx);
 965         if (r)
 966                 return r;
 967
 968         /* check its a wait until and only 1 count */
 969         if (waitreloc.reg != RADEON_WAIT_UNTIL ||
 970             waitreloc.count != 0) {
 971                 DRM_ERROR("vline wait had illegal wait until segment\n");
 972                 r = -EINVAL;
 973                 return r;
 974         }
 975
 976         if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
 977                 DRM_ERROR("vline wait had illegal wait until\n");
 978                 r = -EINVAL;
 979                 return r;
 980         }
 981
 982         /* jump over the NOP */
 983         r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
 984         if (r)
 985                 return r;
 986
 987         h_idx = p->idx - 2;
 988         p->idx += waitreloc.count + 2;
 989         p->idx += p3reloc.count + 2;
 990
 991         header = radeon_get_ib_value(p, h_idx);
 992         crtc_id = radeon_get_ib_value(p, h_idx + 5);
 993         reg = CP_PACKET0_GET_REG(header);
 994         mutex_lock(&p->rdev->ddev->mode_config.mutex);
 995         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
 996         if (!obj) {
 997                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
 998                 r = -EINVAL;
 999                 goto out;
1000         }
1001         crtc = obj_to_crtc(obj);
1002         radeon_crtc = to_radeon_crtc(crtc);
1003         crtc_id = radeon_crtc->crtc_id;
1004
1005         if (!crtc->enabled) {
1006                 /* if the CRTC isn't enabled - we need to nop out the wait until */
1007                 ib[h_idx + 2] = PACKET2(0);
1008                 ib[h_idx + 3] = PACKET2(0);
1009         } else if (crtc_id == 1) {
1010                 switch (reg) {
1011                 case AVIVO_D1MODE_VLINE_START_END:
1012                         header &= ~R300_CP_PACKET0_REG_MASK;
1013                         header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1014                         break;
1015                 case RADEON_CRTC_GUI_TRIG_VLINE:
1016                         header &= ~R300_CP_PACKET0_REG_MASK;
1017                         header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1018                         break;
1019                 default:
1020                         DRM_ERROR("unknown crtc reloc\n");
1021                         r = -EINVAL;
1022                         goto out;
1023                 }
1024                 ib[h_idx] = header;
1025                 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1026         }
1027 out:
1028         mutex_unlock(&p->rdev->ddev->mode_config.mutex);
1029         return r;
1030 }
1031
1032 /**
1033  * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1034  * @parser:             parser structure holding parsing context.
1035  * @data:               pointer to relocation data
1036  * @offset_start:       starting offset
1037  * @offset_mask:        offset mask (to align start offset on)
1038  * @reloc:              reloc informations
1039  *
1040  * Check next packet is relocation packet3, do bo validation and compute
1041  * GPU offset using the provided start.
1042  **/
1043 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1044                               struct radeon_cs_reloc **cs_reloc)
1045 {
1046         struct radeon_cs_chunk *relocs_chunk;
1047         struct radeon_cs_packet p3reloc;
1048         unsigned idx;
1049         int r;
1050
1051         if (p->chunk_relocs_idx == -1) {
1052                 DRM_ERROR("No relocation chunk !\n");
1053                 return -EINVAL;
1054         }
1055         *cs_reloc = NULL;
1056         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1057         r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1058         if (r) {
1059                 return r;
1060         }
1061         p->idx += p3reloc.count + 2;
1062         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1063                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1064                           p3reloc.idx);
1065                 r100_cs_dump_packet(p, &p3reloc);
1066                 return -EINVAL;
1067         }
1068         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1069         if (idx >= relocs_chunk->length_dw) {
1070                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1071                           idx, relocs_chunk->length_dw);
1072                 r100_cs_dump_packet(p, &p3reloc);
1073                 return -EINVAL;
1074         }
1075         /* FIXME: we assume reloc size is 4 dwords */
1076         *cs_reloc = p->relocs_ptr[(idx / 4)];
1077         return 0;
1078 }
1079
1080 static int r100_get_vtx_size(uint32_t vtx_fmt)
1081 {
1082         int vtx_size;
1083         vtx_size = 2;
1084         /* ordered according to bits in spec */
1085         if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1086                 vtx_size++;
1087         if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1088                 vtx_size += 3;
1089         if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1090                 vtx_size++;
1091         if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1092                 vtx_size++;
1093         if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1094                 vtx_size += 3;
1095         if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1096                 vtx_size++;
1097         if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1098                 vtx_size++;
1099         if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1100                 vtx_size += 2;
1101         if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1102                 vtx_size += 2;
1103         if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1104                 vtx_size++;
1105         if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1106                 vtx_size += 2;
1107         if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1108                 vtx_size++;
1109         if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1110                 vtx_size += 2;
1111         if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1112                 vtx_size++;
1113         if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1114                 vtx_size++;
1115         /* blend weight */
1116         if (vtx_fmt & (0x7 << 15))
1117                 vtx_size += (vtx_fmt >> 15) & 0x7;
1118         if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1119                 vtx_size += 3;
1120         if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1121                 vtx_size += 2;
1122         if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1123                 vtx_size++;
1124         if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1125                 vtx_size++;
1126         if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1127                 vtx_size++;
1128         if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1129                 vtx_size++;
1130         return vtx_size;
1131 }
1132
1133 static int r100_packet0_check(struct radeon_cs_parser *p,
1134                               struct radeon_cs_packet *pkt,
1135                               unsigned idx, unsigned reg)
1136 {
1137         struct radeon_cs_reloc *reloc;
1138         struct r100_cs_track *track;
1139         volatile uint32_t *ib;
1140         uint32_t tmp;
1141         int r;
1142         int i, face;
1143         u32 tile_flags = 0;
1144         u32 idx_value;
1145
1146         ib = p->ib->ptr;
1147         track = (struct r100_cs_track *)p->track;
1148
1149         idx_value = radeon_get_ib_value(p, idx);
1150
1151         switch (reg) {
1152         case RADEON_CRTC_GUI_TRIG_VLINE:
1153                 r = r100_cs_packet_parse_vline(p);
1154                 if (r) {
1155                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1156                                   idx, reg);
1157                         r100_cs_dump_packet(p, pkt);
1158                         return r;
1159                 }
1160                 break;
1161                 /* FIXME: only allow PACKET3 blit? easier to check for out of
1162                  * range access */
1163         case RADEON_DST_PITCH_OFFSET:
1164         case RADEON_SRC_PITCH_OFFSET:
1165                 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1166                 if (r)
1167                         return r;
1168                 break;
1169         case RADEON_RB3D_DEPTHOFFSET:
1170                 r = r100_cs_packet_next_reloc(p, &reloc);
1171                 if (r) {
1172                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1173                                   idx, reg);
1174                         r100_cs_dump_packet(p, pkt);
1175                         return r;
1176                 }
1177                 track->zb.robj = reloc->robj;
1178                 track->zb.offset = idx_value;
1179                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1180                 break;
1181         case RADEON_RB3D_COLOROFFSET:
1182                 r = r100_cs_packet_next_reloc(p, &reloc);
1183                 if (r) {
1184                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1185                                   idx, reg);
1186                         r100_cs_dump_packet(p, pkt);
1187                         return r;
1188                 }
1189                 track->cb[0].robj = reloc->robj;
1190                 track->cb[0].offset = idx_value;
1191                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1192                 break;
1193         case RADEON_PP_TXOFFSET_0:
1194         case RADEON_PP_TXOFFSET_1:
1195         case RADEON_PP_TXOFFSET_2:
1196                 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1197                 r = r100_cs_packet_next_reloc(p, &reloc);
1198                 if (r) {
1199                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1200                                   idx, reg);
1201                         r100_cs_dump_packet(p, pkt);
1202                         return r;
1203                 }
1204                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1205                 track->textures[i].robj = reloc->robj;
1206                 break;
1207         case RADEON_PP_CUBIC_OFFSET_T0_0:
1208         case RADEON_PP_CUBIC_OFFSET_T0_1:
1209         case RADEON_PP_CUBIC_OFFSET_T0_2:
1210         case RADEON_PP_CUBIC_OFFSET_T0_3:
1211         case RADEON_PP_CUBIC_OFFSET_T0_4:
1212                 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1213                 r = r100_cs_packet_next_reloc(p, &reloc);
1214                 if (r) {
1215                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1216                                   idx, reg);
1217                         r100_cs_dump_packet(p, pkt);
1218                         return r;
1219                 }
1220                 track->textures[0].cube_info[i].offset = idx_value;
1221                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1222                 track->textures[0].cube_info[i].robj = reloc->robj;
1223                 break;
1224         case RADEON_PP_CUBIC_OFFSET_T1_0:
1225         case RADEON_PP_CUBIC_OFFSET_T1_1:
1226         case RADEON_PP_CUBIC_OFFSET_T1_2:
1227         case RADEON_PP_CUBIC_OFFSET_T1_3:
1228         case RADEON_PP_CUBIC_OFFSET_T1_4:
1229                 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1230                 r = r100_cs_packet_next_reloc(p, &reloc);
1231                 if (r) {
1232                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1233                                   idx, reg);
1234                         r100_cs_dump_packet(p, pkt);
1235                         return r;
1236                 }
1237                 track->textures[1].cube_info[i].offset = idx_value;
1238                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1239                 track->textures[1].cube_info[i].robj = reloc->robj;
1240                 break;
1241         case RADEON_PP_CUBIC_OFFSET_T2_0:
1242         case RADEON_PP_CUBIC_OFFSET_T2_1:
1243         case RADEON_PP_CUBIC_OFFSET_T2_2:
1244         case RADEON_PP_CUBIC_OFFSET_T2_3:
1245         case RADEON_PP_CUBIC_OFFSET_T2_4:
1246                 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1247                 r = r100_cs_packet_next_reloc(p, &reloc);
1248                 if (r) {
1249                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1250                                   idx, reg);
1251                         r100_cs_dump_packet(p, pkt);
1252                         return r;
1253                 }
1254                 track->textures[2].cube_info[i].offset = idx_value;
1255                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1256                 track->textures[2].cube_info[i].robj = reloc->robj;
1257                 break;
1258         case RADEON_RE_WIDTH_HEIGHT:
1259                 track->maxy = ((idx_value >> 16) & 0x7FF);
1260                 break;
1261         case RADEON_RB3D_COLORPITCH:
1262                 r = r100_cs_packet_next_reloc(p, &reloc);
1263                 if (r) {
1264                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1265                                   idx, reg);
1266                         r100_cs_dump_packet(p, pkt);
1267                         return r;
1268                 }
1269
1270                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1271                         tile_flags |= RADEON_COLOR_TILE_ENABLE;
1272                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1273                         tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1274
1275                 tmp = idx_value & ~(0x7 << 16);
1276                 tmp |= tile_flags;
1277                 ib[idx] = tmp;
1278
1279                 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1280                 break;
1281         case RADEON_RB3D_DEPTHPITCH:
1282                 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1283                 break;
1284         case RADEON_RB3D_CNTL:
1285                 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1286                 case 7:
1287                 case 8:
1288                 case 9:
1289                 case 11:
1290                 case 12:
1291                         track->cb[0].cpp = 1;
1292                         break;
1293                 case 3:
1294                 case 4:
1295                 case 15:
1296                         track->cb[0].cpp = 2;
1297                         break;
1298                 case 6:
1299                         track->cb[0].cpp = 4;
1300                         break;
1301                 default:
1302                         DRM_ERROR("Invalid color buffer format (%d) !\n",
1303                                   ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1304                         return -EINVAL;
1305                 }
1306                 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1307                 break;
1308         case RADEON_RB3D_ZSTENCILCNTL:
1309                 switch (idx_value & 0xf) {
1310                 case 0:
1311                         track->zb.cpp = 2;
1312                         break;
1313                 case 2:
1314                 case 3:
1315                 case 4:
1316                 case 5:
1317                 case 9:
1318                 case 11:
1319                         track->zb.cpp = 4;
1320                         break;
1321                 default:
1322                         break;
1323                 }
1324                 break;
1325         case RADEON_RB3D_ZPASS_ADDR:
1326                 r = r100_cs_packet_next_reloc(p, &reloc);
1327                 if (r) {
1328                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1329                                   idx, reg);
1330                         r100_cs_dump_packet(p, pkt);
1331                         return r;
1332                 }
1333                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1334                 break;
1335         case RADEON_PP_CNTL:
1336                 {
1337                         uint32_t temp = idx_value >> 4;
1338                         for (i = 0; i < track->num_texture; i++)
1339                                 track->textures[i].enabled = !!(temp & (1 << i));
1340                 }
1341                 break;
1342         case RADEON_SE_VF_CNTL:
1343                 track->vap_vf_cntl = idx_value;
1344                 break;
1345         case RADEON_SE_VTX_FMT:
1346                 track->vtx_size = r100_get_vtx_size(idx_value);
1347                 break;
1348         case RADEON_PP_TEX_SIZE_0:
1349         case RADEON_PP_TEX_SIZE_1:
1350         case RADEON_PP_TEX_SIZE_2:
1351                 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1352                 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1353                 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1354                 break;
1355         case RADEON_PP_TEX_PITCH_0:
1356         case RADEON_PP_TEX_PITCH_1:
1357         case RADEON_PP_TEX_PITCH_2:
1358                 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1359                 track->textures[i].pitch = idx_value + 32;
1360                 break;
1361         case RADEON_PP_TXFILTER_0:
1362         case RADEON_PP_TXFILTER_1:
1363         case RADEON_PP_TXFILTER_2:
1364                 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1365                 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1366                                                  >> RADEON_MAX_MIP_LEVEL_SHIFT);
1367                 tmp = (idx_value >> 23) & 0x7;
1368                 if (tmp == 2 || tmp == 6)
1369                         track->textures[i].roundup_w = false;
1370                 tmp = (idx_value >> 27) & 0x7;
1371                 if (tmp == 2 || tmp == 6)
1372                         track->textures[i].roundup_h = false;
1373                 break;
1374         case RADEON_PP_TXFORMAT_0:
1375         case RADEON_PP_TXFORMAT_1:
1376         case RADEON_PP_TXFORMAT_2:
1377                 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1378                 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1379                         track->textures[i].use_pitch = 1;
1380                 } else {
1381                         track->textures[i].use_pitch = 0;
1382                         track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1383                         track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1384                 }
1385                 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1386                         track->textures[i].tex_coord_type = 2;
1387                 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1388                 case RADEON_TXFORMAT_I8:
1389                 case RADEON_TXFORMAT_RGB332:
1390                 case RADEON_TXFORMAT_Y8:
1391                         track->textures[i].cpp = 1;
1392                         break;
1393                 case RADEON_TXFORMAT_AI88:
1394                 case RADEON_TXFORMAT_ARGB1555:
1395                 case RADEON_TXFORMAT_RGB565:
1396                 case RADEON_TXFORMAT_ARGB4444:
1397                 case RADEON_TXFORMAT_VYUY422:
1398                 case RADEON_TXFORMAT_YVYU422:
1399                 case RADEON_TXFORMAT_SHADOW16:
1400                 case RADEON_TXFORMAT_LDUDV655:
1401                 case RADEON_TXFORMAT_DUDV88:
1402                         track->textures[i].cpp = 2;
1403                         break;
1404                 case RADEON_TXFORMAT_ARGB8888:
1405                 case RADEON_TXFORMAT_RGBA8888:
1406                 case RADEON_TXFORMAT_SHADOW32:
1407                 case RADEON_TXFORMAT_LDUDUV8888:
1408                         track->textures[i].cpp = 4;
1409                         break;
1410                 case RADEON_TXFORMAT_DXT1:
1411                         track->textures[i].cpp = 1;
1412                         track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1413                         break;
1414                 case RADEON_TXFORMAT_DXT23:
1415                 case RADEON_TXFORMAT_DXT45:
1416                         track->textures[i].cpp = 1;
1417                         track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1418                         break;
1419                 }
1420                 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1421                 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1422                 break;
1423         case RADEON_PP_CUBIC_FACES_0:
1424         case RADEON_PP_CUBIC_FACES_1:
1425         case RADEON_PP_CUBIC_FACES_2:
1426                 tmp = idx_value;
1427                 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1428                 for (face = 0; face < 4; face++) {
1429                         track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1430                         track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1431                 }
1432                 break;
1433         default:
1434                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1435                        reg, idx);
1436                 return -EINVAL;
1437         }
1438         return 0;
1439 }
1440
1441 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1442                                          struct radeon_cs_packet *pkt,
1443                                          struct radeon_bo *robj)
1444 {
1445         unsigned idx;
1446         u32 value;
1447         idx = pkt->idx + 1;
1448         value = radeon_get_ib_value(p, idx + 2);
1449         if ((value + 1) > radeon_bo_size(robj)) {
1450                 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1451                           "(need %u have %lu) !\n",
1452                           value + 1,
1453                           radeon_bo_size(robj));
1454                 return -EINVAL;
1455         }
1456         return 0;
1457 }
1458
1459 static int r100_packet3_check(struct radeon_cs_parser *p,
1460                               struct radeon_cs_packet *pkt)
1461 {
1462         struct radeon_cs_reloc *reloc;
1463         struct r100_cs_track *track;
1464         unsigned idx;
1465         volatile uint32_t *ib;
1466         int r;
1467
1468         ib = p->ib->ptr;
1469         idx = pkt->idx + 1;
1470         track = (struct r100_cs_track *)p->track;
1471         switch (pkt->opcode) {
1472         case PACKET3_3D_LOAD_VBPNTR:
1473                 r = r100_packet3_load_vbpntr(p, pkt, idx);
1474                 if (r)
1475                         return r;
1476                 break;
1477         case PACKET3_INDX_BUFFER:
1478                 r = r100_cs_packet_next_reloc(p, &reloc);
1479                 if (r) {
1480                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1481                         r100_cs_dump_packet(p, pkt);
1482                         return r;
1483                 }
1484                 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1485                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1486                 if (r) {
1487                         return r;
1488                 }
1489                 break;
1490         case 0x23:
1491                 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1492                 r = r100_cs_packet_next_reloc(p, &reloc);
1493                 if (r) {
1494                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1495                         r100_cs_dump_packet(p, pkt);
1496                         return r;
1497                 }
1498                 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1499                 track->num_arrays = 1;
1500                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1501
1502                 track->arrays[0].robj = reloc->robj;
1503                 track->arrays[0].esize = track->vtx_size;
1504
1505                 track->max_indx = radeon_get_ib_value(p, idx+1);
1506
1507                 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1508                 track->immd_dwords = pkt->count - 1;
1509                 r = r100_cs_track_check(p->rdev, track);
1510                 if (r)
1511                         return r;
1512                 break;
1513         case PACKET3_3D_DRAW_IMMD:
1514                 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1515                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1516                         return -EINVAL;
1517                 }
1518                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1519                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1520                 track->immd_dwords = pkt->count - 1;
1521                 r = r100_cs_track_check(p->rdev, track);
1522                 if (r)
1523                         return r;
1524                 break;
1525                 /* triggers drawing using in-packet vertex data */
1526         case PACKET3_3D_DRAW_IMMD_2:
1527                 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1528                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1529                         return -EINVAL;
1530                 }
1531                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1532                 track->immd_dwords = pkt->count;
1533                 r = r100_cs_track_check(p->rdev, track);
1534                 if (r)
1535                         return r;
1536                 break;
1537                 /* triggers drawing using in-packet vertex data */
1538         case PACKET3_3D_DRAW_VBUF_2:
1539                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1540                 r = r100_cs_track_check(p->rdev, track);
1541                 if (r)
1542                         return r;
1543                 break;
1544                 /* triggers drawing of vertex buffers setup elsewhere */
1545         case PACKET3_3D_DRAW_INDX_2:
1546                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1547                 r = r100_cs_track_check(p->rdev, track);
1548                 if (r)
1549                         return r;
1550                 break;
1551                 /* triggers drawing using indices to vertex buffer */
1552         case PACKET3_3D_DRAW_VBUF:
1553                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1554                 r = r100_cs_track_check(p->rdev, track);
1555                 if (r)
1556                         return r;
1557                 break;
1558                 /* triggers drawing of vertex buffers setup elsewhere */
1559         case PACKET3_3D_DRAW_INDX:
1560                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1561                 r = r100_cs_track_check(p->rdev, track);
1562                 if (r)
1563                         return r;
1564                 break;
1565                 /* triggers drawing using indices to vertex buffer */
1566         case PACKET3_NOP:
1567                 break;
1568         default:
1569                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1570                 return -EINVAL;
1571         }
1572         return 0;
1573 }
1574
1575 int r100_cs_parse(struct radeon_cs_parser *p)
1576 {
1577         struct radeon_cs_packet pkt;
1578         struct r100_cs_track *track;
1579         int r;
1580
1581         track = kzalloc(sizeof(*track), GFP_KERNEL);
1582         r100_cs_track_clear(p->rdev, track);
1583         p->track = track;
1584         do {
1585                 r = r100_cs_packet_parse(p, &pkt, p->idx);
1586                 if (r) {
1587                         return r;
1588                 }
1589                 p->idx += pkt.count + 2;
1590                 switch (pkt.type) {
1591                         case PACKET_TYPE0:
1592                                 if (p->rdev->family >= CHIP_R200)
1593                                         r = r100_cs_parse_packet0(p, &pkt,
1594                                                                   p->rdev->config.r100.reg_safe_bm,
1595                                                                   p->rdev->config.r100.reg_safe_bm_size,
1596                                                                   &r200_packet0_check);
1597                                 else
1598                                         r = r100_cs_parse_packet0(p, &pkt,
1599                                                                   p->rdev->config.r100.reg_safe_bm,
1600                                                                   p->rdev->config.r100.reg_safe_bm_size,
1601                                                                   &r100_packet0_check);
1602                                 break;
1603                         case PACKET_TYPE2:
1604                                 break;
1605                         case PACKET_TYPE3:
1606                                 r = r100_packet3_check(p, &pkt);
1607                                 break;
1608                         default:
1609                                 DRM_ERROR("Unknown packet type %d !\n",
1610                                           pkt.type);
1611                                 return -EINVAL;
1612                 }
1613                 if (r) {
1614                         return r;
1615                 }
1616         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1617         return 0;
1618 }
1619
1620
1621 /*
1622  * Global GPU functions
1623  */
1624 void r100_errata(struct radeon_device *rdev)
1625 {
1626         rdev->pll_errata = 0;
1627
1628         if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1629                 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1630         }
1631
1632         if (rdev->family == CHIP_RV100 ||
1633             rdev->family == CHIP_RS100 ||
1634             rdev->family == CHIP_RS200) {
1635                 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1636         }
1637 }
1638
1639 /* Wait for vertical sync on primary CRTC */
1640 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1641 {
1642         uint32_t crtc_gen_cntl, tmp;
1643         int i;
1644
1645         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1646         if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1647             !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1648                 return;
1649         }
1650         /* Clear the CRTC_VBLANK_SAVE bit */
1651         WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1652         for (i = 0; i < rdev->usec_timeout; i++) {
1653                 tmp = RREG32(RADEON_CRTC_STATUS);
1654                 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1655                         return;
1656                 }
1657                 DRM_UDELAY(1);
1658         }
1659 }
1660
1661 /* Wait for vertical sync on secondary CRTC */
1662 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1663 {
1664         uint32_t crtc2_gen_cntl, tmp;
1665         int i;
1666
1667         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1668         if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1669             !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1670                 return;
1671
1672         /* Clear the CRTC_VBLANK_SAVE bit */
1673         WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1674         for (i = 0; i < rdev->usec_timeout; i++) {
1675                 tmp = RREG32(RADEON_CRTC2_STATUS);
1676                 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1677                         return;
1678                 }
1679                 DRM_UDELAY(1);
1680         }
1681 }
1682
1683 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1684 {
1685         unsigned i;
1686         uint32_t tmp;
1687
1688         for (i = 0; i < rdev->usec_timeout; i++) {
1689                 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1690                 if (tmp >= n) {
1691                         return 0;
1692                 }
1693                 DRM_UDELAY(1);
1694         }
1695         return -1;
1696 }
1697
1698 int r100_gui_wait_for_idle(struct radeon_device *rdev)
1699 {
1700         unsigned i;
1701         uint32_t tmp;
1702
1703         if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1704                 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1705                        " Bad things might happen.\n");
1706         }
1707         for (i = 0; i < rdev->usec_timeout; i++) {
1708                 tmp = RREG32(RADEON_RBBM_STATUS);
1709                 if (!(tmp & RADEON_RBBM_ACTIVE)) {
1710                         return 0;
1711                 }
1712                 DRM_UDELAY(1);
1713         }
1714         return -1;
1715 }
1716
1717 int r100_mc_wait_for_idle(struct radeon_device *rdev)
1718 {
1719         unsigned i;
1720         uint32_t tmp;
1721
1722         for (i = 0; i < rdev->usec_timeout; i++) {
1723                 /* read MC_STATUS */
1724                 tmp = RREG32(RADEON_MC_STATUS);
1725                 if (tmp & RADEON_MC_IDLE) {
1726                         return 0;
1727                 }
1728                 DRM_UDELAY(1);
1729         }
1730         return -1;
1731 }
1732
1733 void r100_gpu_init(struct radeon_device *rdev)
1734 {
1735         /* TODO: anythings to do here ? pipes ? */
1736         r100_hdp_reset(rdev);
1737 }
1738
1739 void r100_hdp_reset(struct radeon_device *rdev)
1740 {
1741         uint32_t tmp;
1742
1743         tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
1744         tmp |= (7 << 28);
1745         WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
1746         (void)RREG32(RADEON_HOST_PATH_CNTL);
1747         udelay(200);
1748         WREG32(RADEON_RBBM_SOFT_RESET, 0);
1749         WREG32(RADEON_HOST_PATH_CNTL, tmp);
1750         (void)RREG32(RADEON_HOST_PATH_CNTL);
1751 }
1752
1753 int r100_rb2d_reset(struct radeon_device *rdev)
1754 {
1755         uint32_t tmp;
1756         int i;
1757
1758         WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_E2);
1759         (void)RREG32(RADEON_RBBM_SOFT_RESET);
1760         udelay(200);
1761         WREG32(RADEON_RBBM_SOFT_RESET, 0);
1762         /* Wait to prevent race in RBBM_STATUS */
1763         mdelay(1);
1764         for (i = 0; i < rdev->usec_timeout; i++) {
1765                 tmp = RREG32(RADEON_RBBM_STATUS);
1766                 if (!(tmp & (1 << 26))) {
1767                         DRM_INFO("RB2D reset succeed (RBBM_STATUS=0x%08X)\n",
1768                                  tmp);
1769                         return 0;
1770                 }
1771                 DRM_UDELAY(1);
1772         }
1773         tmp = RREG32(RADEON_RBBM_STATUS);
1774         DRM_ERROR("Failed to reset RB2D (RBBM_STATUS=0x%08X)!\n", tmp);
1775         return -1;
1776 }
1777
1778 int r100_gpu_reset(struct radeon_device *rdev)
1779 {
1780         uint32_t status;
1781
1782         /* reset order likely matter */
1783         status = RREG32(RADEON_RBBM_STATUS);
1784         /* reset HDP */
1785         r100_hdp_reset(rdev);
1786         /* reset rb2d */
1787         if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
1788                 r100_rb2d_reset(rdev);
1789         }
1790         /* TODO: reset 3D engine */
1791         /* reset CP */
1792         status = RREG32(RADEON_RBBM_STATUS);
1793         if (status & (1 << 16)) {
1794                 r100_cp_reset(rdev);
1795         }
1796         /* Check if GPU is idle */
1797         status = RREG32(RADEON_RBBM_STATUS);
1798         if (status & RADEON_RBBM_ACTIVE) {
1799                 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
1800                 return -1;
1801         }
1802         DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
1803         return 0;
1804 }
1805
1806 void r100_set_common_regs(struct radeon_device *rdev)
1807 {
1808         struct drm_device *dev = rdev->ddev;
1809         bool force_dac2 = false;
1810
1811         /* set these so they don't interfere with anything */
1812         WREG32(RADEON_OV0_SCALE_CNTL, 0);
1813         WREG32(RADEON_SUBPIC_CNTL, 0);
1814         WREG32(RADEON_VIPH_CONTROL, 0);
1815         WREG32(RADEON_I2C_CNTL_1, 0);
1816         WREG32(RADEON_DVI_I2C_CNTL_1, 0);
1817         WREG32(RADEON_CAP0_TRIG_CNTL, 0);
1818         WREG32(RADEON_CAP1_TRIG_CNTL, 0);
1819
1820         /* always set up dac2 on rn50 and some rv100 as lots
1821          * of servers seem to wire it up to a VGA port but
1822          * don't report it in the bios connector
1823          * table.
1824          */
1825         switch (dev->pdev->device) {
1826                 /* RN50 */
1827         case 0x515e:
1828         case 0x5969:
1829                 force_dac2 = true;
1830                 break;
1831                 /* RV100*/
1832         case 0x5159:
1833         case 0x515a:
1834                 /* DELL triple head servers */
1835                 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
1836                     ((dev->pdev->subsystem_device == 0x016c) ||
1837                      (dev->pdev->subsystem_device == 0x016d) ||
1838                      (dev->pdev->subsystem_device == 0x016e) ||
1839                      (dev->pdev->subsystem_device == 0x016f) ||
1840                      (dev->pdev->subsystem_device == 0x0170) ||
1841                      (dev->pdev->subsystem_device == 0x017d) ||
1842                      (dev->pdev->subsystem_device == 0x017e) ||
1843                      (dev->pdev->subsystem_device == 0x0183) ||
1844                      (dev->pdev->subsystem_device == 0x018a) ||
1845                      (dev->pdev->subsystem_device == 0x019a)))
1846                         force_dac2 = true;
1847                 break;
1848         }
1849
1850         if (force_dac2) {
1851                 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
1852                 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1853                 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
1854
1855                 /* For CRT on DAC2, don't turn it on if BIOS didn't
1856                    enable it, even it's detected.
1857                 */
1858
1859                 /* force it to crtc0 */
1860                 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
1861                 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
1862                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1863
1864                 /* set up the TV DAC */
1865                 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
1866                                  RADEON_TV_DAC_STD_MASK |
1867                                  RADEON_TV_DAC_RDACPD |
1868                                  RADEON_TV_DAC_GDACPD |
1869                                  RADEON_TV_DAC_BDACPD |
1870                                  RADEON_TV_DAC_BGADJ_MASK |
1871                                  RADEON_TV_DAC_DACADJ_MASK);
1872                 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
1873                                 RADEON_TV_DAC_NHOLD |
1874                                 RADEON_TV_DAC_STD_PS2 |
1875                                 (0x58 << 16));
1876
1877                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1878                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1879                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1880         }
1881 }
1882
1883 /*
1884  * VRAM info
1885  */
1886 static void r100_vram_get_type(struct radeon_device *rdev)
1887 {
1888         uint32_t tmp;
1889
1890         rdev->mc.vram_is_ddr = false;
1891         if (rdev->flags & RADEON_IS_IGP)
1892                 rdev->mc.vram_is_ddr = true;
1893         else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
1894                 rdev->mc.vram_is_ddr = true;
1895         if ((rdev->family == CHIP_RV100) ||
1896             (rdev->family == CHIP_RS100) ||
1897             (rdev->family == CHIP_RS200)) {
1898                 tmp = RREG32(RADEON_MEM_CNTL);
1899                 if (tmp & RV100_HALF_MODE) {
1900                         rdev->mc.vram_width = 32;
1901                 } else {
1902                         rdev->mc.vram_width = 64;
1903                 }
1904                 if (rdev->flags & RADEON_SINGLE_CRTC) {
1905                         rdev->mc.vram_width /= 4;
1906                         rdev->mc.vram_is_ddr = true;
1907                 }
1908         } else if (rdev->family <= CHIP_RV280) {
1909                 tmp = RREG32(RADEON_MEM_CNTL);
1910                 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
1911                         rdev->mc.vram_width = 128;
1912                 } else {
1913                         rdev->mc.vram_width = 64;
1914                 }
1915         } else {
1916                 /* newer IGPs */
1917                 rdev->mc.vram_width = 128;
1918         }
1919 }
1920
1921 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
1922 {
1923         u32 aper_size;
1924         u8 byte;
1925
1926         aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1927
1928         /* Set HDP_APER_CNTL only on cards that are known not to be broken,
1929          * that is has the 2nd generation multifunction PCI interface
1930          */
1931         if (rdev->family == CHIP_RV280 ||
1932             rdev->family >= CHIP_RV350) {
1933                 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
1934                        ~RADEON_HDP_APER_CNTL);
1935                 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
1936                 return aper_size * 2;
1937         }
1938
1939         /* Older cards have all sorts of funny issues to deal with. First
1940          * check if it's a multifunction card by reading the PCI config
1941          * header type... Limit those to one aperture size
1942          */
1943         pci_read_config_byte(rdev->pdev, 0xe, &byte);
1944         if (byte & 0x80) {
1945                 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
1946                 DRM_INFO("Limiting VRAM to one aperture\n");
1947                 return aper_size;
1948         }
1949
1950         /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
1951          * have set it up. We don't write this as it's broken on some ASICs but
1952          * we expect the BIOS to have done the right thing (might be too optimistic...)
1953          */
1954         if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
1955                 return aper_size * 2;
1956         return aper_size;
1957 }
1958
1959 void r100_vram_init_sizes(struct radeon_device *rdev)
1960 {
1961         u64 config_aper_size;
1962
1963         /* work out accessible VRAM */
1964         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1965         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
1966         rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
1967         /* FIXME we don't use the second aperture yet when we could use it */
1968         if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
1969                 rdev->mc.visible_vram_size = rdev->mc.aper_size;
1970         config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1971         if (rdev->flags & RADEON_IS_IGP) {
1972                 uint32_t tom;
1973                 /* read NB_TOM to get the amount of ram stolen for the GPU */
1974                 tom = RREG32(RADEON_NB_TOM);
1975                 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
1976                 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1977                 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1978         } else {
1979                 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
1980                 /* Some production boards of m6 will report 0
1981                  * if it's 8 MB
1982                  */
1983                 if (rdev->mc.real_vram_size == 0) {
1984                         rdev->mc.real_vram_size = 8192 * 1024;
1985                         WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1986                 }
1987                 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
1988                  * Novell bug 204882 + along with lots of ubuntu ones
1989                  */
1990                 if (config_aper_size > rdev->mc.real_vram_size)
1991                         rdev->mc.mc_vram_size = config_aper_size;
1992                 else
1993                         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1994         }
1995         /* FIXME remove this once we support unmappable VRAM */
1996         if (rdev->mc.mc_vram_size > rdev->mc.aper_size) {
1997                 rdev->mc.mc_vram_size = rdev->mc.aper_size;
1998                 rdev->mc.real_vram_size = rdev->mc.aper_size;
1999         }
2000 }
2001
2002 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2003 {
2004         uint32_t temp;
2005
2006         temp = RREG32(RADEON_CONFIG_CNTL);
2007         if (state == false) {
2008                 temp &= ~(1<<8);
2009                 temp |= (1<<9);
2010         } else {
2011                 temp &= ~(1<<9);
2012         }
2013         WREG32(RADEON_CONFIG_CNTL, temp);
2014 }
2015
2016 void r100_mc_init(struct radeon_device *rdev)
2017 {
2018         u64 base;
2019
2020         r100_vram_get_type(rdev);
2021         r100_vram_init_sizes(rdev);
2022         base = rdev->mc.aper_base;
2023         if (rdev->flags & RADEON_IS_IGP)
2024                 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2025         radeon_vram_location(rdev, &rdev->mc, base);
2026         if (!(rdev->flags & RADEON_IS_AGP))
2027                 radeon_gtt_location(rdev, &rdev->mc);
2028 }
2029
2030
2031 /*
2032  * Indirect registers accessor
2033  */
2034 void r100_pll_errata_after_index(struct radeon_device *rdev)
2035 {
2036         if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) {
2037                 return;
2038         }
2039         (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2040         (void)RREG32(RADEON_CRTC_GEN_CNTL);
2041 }
2042
2043 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2044 {
2045         /* This workarounds is necessary on RV100, RS100 and RS200 chips
2046          * or the chip could hang on a subsequent access
2047          */
2048         if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2049                 udelay(5000);
2050         }
2051
2052         /* This function is required to workaround a hardware bug in some (all?)
2053          * revisions of the R300.  This workaround should be called after every
2054          * CLOCK_CNTL_INDEX register access.  If not, register reads afterward
2055          * may not be correct.
2056          */
2057         if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2058                 uint32_t save, tmp;
2059
2060                 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2061                 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2062                 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2063                 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2064                 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2065         }
2066 }
2067
2068 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2069 {
2070         uint32_t data;
2071
2072         WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2073         r100_pll_errata_after_index(rdev);
2074         data = RREG32(RADEON_CLOCK_CNTL_DATA);
2075         r100_pll_errata_after_data(rdev);
2076         return data;
2077 }
2078
2079 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2080 {
2081         WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2082         r100_pll_errata_after_index(rdev);
2083         WREG32(RADEON_CLOCK_CNTL_DATA, v);
2084         r100_pll_errata_after_data(rdev);
2085 }
2086
2087 void r100_set_safe_registers(struct radeon_device *rdev)
2088 {
2089         if (ASIC_IS_RN50(rdev)) {
2090                 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2091                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2092         } else if (rdev->family < CHIP_R200) {
2093                 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2094                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2095         } else {
2096                 r200_set_safe_registers(rdev);
2097         }
2098 }
2099
2100 /*
2101  * Debugfs info
2102  */
2103 #if defined(CONFIG_DEBUG_FS)
2104 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2105 {
2106         struct drm_info_node *node = (struct drm_info_node *) m->private;
2107         struct drm_device *dev = node->minor->dev;
2108         struct radeon_device *rdev = dev->dev_private;
2109         uint32_t reg, value;
2110         unsigned i;
2111
2112         seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2113         seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2114         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2115         for (i = 0; i < 64; i++) {
2116                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2117                 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2118                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2119                 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2120                 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2121         }
2122         return 0;
2123 }
2124
2125 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2126 {
2127         struct drm_info_node *node = (struct drm_info_node *) m->private;
2128         struct drm_device *dev = node->minor->dev;
2129         struct radeon_device *rdev = dev->dev_private;
2130         uint32_t rdp, wdp;
2131         unsigned count, i, j;
2132
2133         radeon_ring_free_size(rdev);
2134         rdp = RREG32(RADEON_CP_RB_RPTR);
2135         wdp = RREG32(RADEON_CP_RB_WPTR);
2136         count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2137         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2138         seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2139         seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2140         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2141         seq_printf(m, "%u dwords in ring\n", count);
2142         for (j = 0; j <= count; j++) {
2143                 i = (rdp + j) & rdev->cp.ptr_mask;
2144                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2145         }
2146         return 0;
2147 }
2148
2149
2150 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2151 {
2152         struct drm_info_node *node = (struct drm_info_node *) m->private;
2153         struct drm_device *dev = node->minor->dev;
2154         struct radeon_device *rdev = dev->dev_private;
2155         uint32_t csq_stat, csq2_stat, tmp;
2156         unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2157         unsigned i;
2158
2159         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2160         seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2161         csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2162         csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2163         r_rptr = (csq_stat >> 0) & 0x3ff;
2164         r_wptr = (csq_stat >> 10) & 0x3ff;
2165         ib1_rptr = (csq_stat >> 20) & 0x3ff;
2166         ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2167         ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2168         ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2169         seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2170         seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2171         seq_printf(m, "Ring rptr %u\n", r_rptr);
2172         seq_printf(m, "Ring wptr %u\n", r_wptr);
2173         seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2174         seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2175         seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2176         seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2177         /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2178          * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2179         seq_printf(m, "Ring fifo:\n");
2180         for (i = 0; i < 256; i++) {
2181                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2182                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2183                 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2184         }
2185         seq_printf(m, "Indirect1 fifo:\n");
2186         for (i = 256; i <= 512; i++) {
2187                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2188                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2189                 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2190         }
2191         seq_printf(m, "Indirect2 fifo:\n");
2192         for (i = 640; i < ib1_wptr; i++) {
2193                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2194                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2195                 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2196         }
2197         return 0;
2198 }
2199
2200 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2201 {
2202         struct drm_info_node *node = (struct drm_info_node *) m->private;
2203         struct drm_device *dev = node->minor->dev;
2204         struct radeon_device *rdev = dev->dev_private;
2205         uint32_t tmp;
2206
2207         tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2208         seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2209         tmp = RREG32(RADEON_MC_FB_LOCATION);
2210         seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2211         tmp = RREG32(RADEON_BUS_CNTL);
2212         seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2213         tmp = RREG32(RADEON_MC_AGP_LOCATION);
2214         seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2215         tmp = RREG32(RADEON_AGP_BASE);
2216         seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2217         tmp = RREG32(RADEON_HOST_PATH_CNTL);
2218         seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2219         tmp = RREG32(0x01D0);
2220         seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2221         tmp = RREG32(RADEON_AIC_LO_ADDR);
2222         seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2223         tmp = RREG32(RADEON_AIC_HI_ADDR);
2224         seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2225         tmp = RREG32(0x01E4);
2226         seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2227         return 0;
2228 }
2229
2230 static struct drm_info_list r100_debugfs_rbbm_list[] = {
2231         {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2232 };
2233
2234 static struct drm_info_list r100_debugfs_cp_list[] = {
2235         {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2236         {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2237 };
2238
2239 static struct drm_info_list r100_debugfs_mc_info_list[] = {
2240         {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2241 };
2242 #endif
2243
2244 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2245 {
2246 #if defined(CONFIG_DEBUG_FS)
2247         return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2248 #else
2249         return 0;
2250 #endif
2251 }
2252
2253 int r100_debugfs_cp_init(struct radeon_device *rdev)
2254 {
2255 #if defined(CONFIG_DEBUG_FS)
2256         return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2257 #else
2258         return 0;
2259 #endif
2260 }
2261
2262 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2263 {
2264 #if defined(CONFIG_DEBUG_FS)
2265         return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2266 #else
2267         return 0;
2268 #endif
2269 }
2270
2271 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2272                          uint32_t tiling_flags, uint32_t pitch,
2273                          uint32_t offset, uint32_t obj_size)
2274 {
2275         int surf_index = reg * 16;
2276         int flags = 0;
2277
2278         /* r100/r200 divide by 16 */
2279         if (rdev->family < CHIP_R300)
2280                 flags = pitch / 16;
2281         else
2282                 flags = pitch / 8;
2283
2284         if (rdev->family <= CHIP_RS200) {
2285                 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2286                                  == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2287                         flags |= RADEON_SURF_TILE_COLOR_BOTH;
2288                 if (tiling_flags & RADEON_TILING_MACRO)
2289                         flags |= RADEON_SURF_TILE_COLOR_MACRO;
2290         } else if (rdev->family <= CHIP_RV280) {
2291                 if (tiling_flags & (RADEON_TILING_MACRO))
2292                         flags |= R200_SURF_TILE_COLOR_MACRO;
2293                 if (tiling_flags & RADEON_TILING_MICRO)
2294                         flags |= R200_SURF_TILE_COLOR_MICRO;
2295         } else {
2296                 if (tiling_flags & RADEON_TILING_MACRO)
2297                         flags |= R300_SURF_TILE_MACRO;
2298                 if (tiling_flags & RADEON_TILING_MICRO)
2299                         flags |= R300_SURF_TILE_MICRO;
2300         }
2301
2302         if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2303                 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2304         if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2305                 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2306
2307         DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2308         WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2309         WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2310         WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2311         return 0;
2312 }
2313
2314 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2315 {
2316         int surf_index = reg * 16;
2317         WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2318 }
2319
2320 void r100_bandwidth_update(struct radeon_device *rdev)
2321 {
2322         fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2323         fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2324         fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2325         uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2326         fixed20_12 memtcas_ff[8] = {
2327                 fixed_init(1),
2328                 fixed_init(2),
2329                 fixed_init(3),
2330                 fixed_init(0),
2331                 fixed_init_half(1),
2332                 fixed_init_half(2),
2333                 fixed_init(0),
2334         };
2335         fixed20_12 memtcas_rs480_ff[8] = {
2336                 fixed_init(0),
2337                 fixed_init(1),
2338                 fixed_init(2),
2339                 fixed_init(3),
2340                 fixed_init(0),
2341                 fixed_init_half(1),
2342                 fixed_init_half(2),
2343                 fixed_init_half(3),
2344         };
2345         fixed20_12 memtcas2_ff[8] = {
2346                 fixed_init(0),
2347                 fixed_init(1),
2348                 fixed_init(2),
2349                 fixed_init(3),
2350                 fixed_init(4),
2351                 fixed_init(5),
2352                 fixed_init(6),
2353                 fixed_init(7),
2354         };
2355         fixed20_12 memtrbs[8] = {
2356                 fixed_init(1),
2357                 fixed_init_half(1),
2358                 fixed_init(2),
2359                 fixed_init_half(2),
2360                 fixed_init(3),
2361                 fixed_init_half(3),
2362                 fixed_init(4),
2363                 fixed_init_half(4)
2364         };
2365         fixed20_12 memtrbs_r4xx[8] = {
2366                 fixed_init(4),
2367                 fixed_init(5),
2368                 fixed_init(6),
2369                 fixed_init(7),
2370                 fixed_init(8),
2371                 fixed_init(9),
2372                 fixed_init(10),
2373                 fixed_init(11)
2374         };
2375         fixed20_12 min_mem_eff;
2376         fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2377         fixed20_12 cur_latency_mclk, cur_latency_sclk;
2378         fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2379                 disp_drain_rate2, read_return_rate;
2380         fixed20_12 time_disp1_drop_priority;
2381         int c;
2382         int cur_size = 16;       /* in octawords */
2383         int critical_point = 0, critical_point2;
2384 /*      uint32_t read_return_rate, time_disp1_drop_priority; */
2385         int stop_req, max_stop_req;
2386         struct drm_display_mode *mode1 = NULL;
2387         struct drm_display_mode *mode2 = NULL;
2388         uint32_t pixel_bytes1 = 0;
2389         uint32_t pixel_bytes2 = 0;
2390
2391         if (rdev->mode_info.crtcs[0]->base.enabled) {
2392                 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2393                 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2394         }
2395         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2396                 if (rdev->mode_info.crtcs[1]->base.enabled) {
2397                         mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2398                         pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2399                 }
2400         }
2401
2402         min_mem_eff.full = rfixed_const_8(0);
2403         /* get modes */
2404         if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2405                 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2406                 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2407                 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2408                 /* check crtc enables */
2409                 if (mode2)
2410                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2411                 if (mode1)
2412                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2413                 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2414         }
2415
2416         /*
2417          * determine is there is enough bw for current mode
2418          */
2419         mclk_ff.full = rfixed_const(rdev->clock.default_mclk);
2420         temp_ff.full = rfixed_const(100);
2421         mclk_ff.full = rfixed_div(mclk_ff, temp_ff);
2422         sclk_ff.full = rfixed_const(rdev->clock.default_sclk);
2423         sclk_ff.full = rfixed_div(sclk_ff, temp_ff);
2424
2425         temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2426         temp_ff.full = rfixed_const(temp);
2427         mem_bw.full = rfixed_mul(mclk_ff, temp_ff);
2428
2429         pix_clk.full = 0;
2430         pix_clk2.full = 0;
2431         peak_disp_bw.full = 0;
2432         if (mode1) {
2433                 temp_ff.full = rfixed_const(1000);
2434                 pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */
2435                 pix_clk.full = rfixed_div(pix_clk, temp_ff);
2436                 temp_ff.full = rfixed_const(pixel_bytes1);
2437                 peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff);
2438         }
2439         if (mode2) {
2440                 temp_ff.full = rfixed_const(1000);
2441                 pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */
2442                 pix_clk2.full = rfixed_div(pix_clk2, temp_ff);
2443                 temp_ff.full = rfixed_const(pixel_bytes2);
2444                 peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff);
2445         }
2446
2447         mem_bw.full = rfixed_mul(mem_bw, min_mem_eff);
2448         if (peak_disp_bw.full >= mem_bw.full) {
2449                 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2450                           "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2451         }
2452
2453         /*  Get values from the EXT_MEM_CNTL register...converting its contents. */
2454         temp = RREG32(RADEON_MEM_TIMING_CNTL);
2455         if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2456                 mem_trcd = ((temp >> 2) & 0x3) + 1;
2457                 mem_trp  = ((temp & 0x3)) + 1;
2458                 mem_tras = ((temp & 0x70) >> 4) + 1;
2459         } else if (rdev->family == CHIP_R300 ||
2460                    rdev->family == CHIP_R350) { /* r300, r350 */
2461                 mem_trcd = (temp & 0x7) + 1;
2462                 mem_trp = ((temp >> 8) & 0x7) + 1;
2463                 mem_tras = ((temp >> 11) & 0xf) + 4;
2464         } else if (rdev->family == CHIP_RV350 ||
2465                    rdev->family <= CHIP_RV380) {
2466                 /* rv3x0 */
2467                 mem_trcd = (temp & 0x7) + 3;
2468                 mem_trp = ((temp >> 8) & 0x7) + 3;
2469                 mem_tras = ((temp >> 11) & 0xf) + 6;
2470         } else if (rdev->family == CHIP_R420 ||
2471                    rdev->family == CHIP_R423 ||
2472                    rdev->family == CHIP_RV410) {
2473                 /* r4xx */
2474                 mem_trcd = (temp & 0xf) + 3;
2475                 if (mem_trcd > 15)
2476                         mem_trcd = 15;
2477                 mem_trp = ((temp >> 8) & 0xf) + 3;
2478                 if (mem_trp > 15)
2479                         mem_trp = 15;
2480                 mem_tras = ((temp >> 12) & 0x1f) + 6;
2481                 if (mem_tras > 31)
2482                         mem_tras = 31;
2483         } else { /* RV200, R200 */
2484                 mem_trcd = (temp & 0x7) + 1;
2485                 mem_trp = ((temp >> 8) & 0x7) + 1;
2486                 mem_tras = ((temp >> 12) & 0xf) + 4;
2487         }
2488         /* convert to FF */
2489         trcd_ff.full = rfixed_const(mem_trcd);
2490         trp_ff.full = rfixed_const(mem_trp);
2491         tras_ff.full = rfixed_const(mem_tras);
2492
2493         /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2494         temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2495         data = (temp & (7 << 20)) >> 20;
2496         if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2497                 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2498                         tcas_ff = memtcas_rs480_ff[data];
2499                 else
2500                         tcas_ff = memtcas_ff[data];
2501         } else
2502                 tcas_ff = memtcas2_ff[data];
2503
2504         if (rdev->family == CHIP_RS400 ||
2505             rdev->family == CHIP_RS480) {
2506                 /* extra cas latency stored in bits 23-25 0-4 clocks */
2507                 data = (temp >> 23) & 0x7;
2508                 if (data < 5)
2509                         tcas_ff.full += rfixed_const(data);
2510         }
2511
2512         if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2513                 /* on the R300, Tcas is included in Trbs.
2514                  */
2515                 temp = RREG32(RADEON_MEM_CNTL);
2516                 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2517                 if (data == 1) {
2518                         if (R300_MEM_USE_CD_CH_ONLY & temp) {
2519                                 temp = RREG32(R300_MC_IND_INDEX);
2520                                 temp &= ~R300_MC_IND_ADDR_MASK;
2521                                 temp |= R300_MC_READ_CNTL_CD_mcind;
2522                                 WREG32(R300_MC_IND_INDEX, temp);
2523                                 temp = RREG32(R300_MC_IND_DATA);
2524                                 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2525                         } else {
2526                                 temp = RREG32(R300_MC_READ_CNTL_AB);
2527                                 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2528                         }
2529                 } else {
2530                         temp = RREG32(R300_MC_READ_CNTL_AB);
2531                         data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2532                 }
2533                 if (rdev->family == CHIP_RV410 ||
2534                     rdev->family == CHIP_R420 ||
2535                     rdev->family == CHIP_R423)
2536                         trbs_ff = memtrbs_r4xx[data];
2537                 else
2538                         trbs_ff = memtrbs[data];
2539                 tcas_ff.full += trbs_ff.full;
2540         }
2541
2542         sclk_eff_ff.full = sclk_ff.full;
2543
2544         if (rdev->flags & RADEON_IS_AGP) {
2545                 fixed20_12 agpmode_ff;
2546                 agpmode_ff.full = rfixed_const(radeon_agpmode);
2547                 temp_ff.full = rfixed_const_666(16);
2548                 sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff);
2549         }
2550         /* TODO PCIE lanes may affect this - agpmode == 16?? */
2551
2552         if (ASIC_IS_R300(rdev)) {
2553                 sclk_delay_ff.full = rfixed_const(250);
2554         } else {
2555                 if ((rdev->family == CHIP_RV100) ||
2556                     rdev->flags & RADEON_IS_IGP) {
2557                         if (rdev->mc.vram_is_ddr)
2558                                 sclk_delay_ff.full = rfixed_const(41);
2559                         else
2560                                 sclk_delay_ff.full = rfixed_const(33);
2561                 } else {
2562                         if (rdev->mc.vram_width == 128)
2563                                 sclk_delay_ff.full = rfixed_const(57);
2564                         else
2565                                 sclk_delay_ff.full = rfixed_const(41);
2566                 }
2567         }
2568
2569         mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff);
2570
2571         if (rdev->mc.vram_is_ddr) {
2572                 if (rdev->mc.vram_width == 32) {
2573                         k1.full = rfixed_const(40);
2574                         c  = 3;
2575                 } else {
2576                         k1.full = rfixed_const(20);
2577                         c  = 1;
2578                 }
2579         } else {
2580                 k1.full = rfixed_const(40);
2581                 c  = 3;
2582         }
2583
2584         temp_ff.full = rfixed_const(2);
2585         mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff);
2586         temp_ff.full = rfixed_const(c);
2587         mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff);
2588         temp_ff.full = rfixed_const(4);
2589         mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff);
2590         mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff);
2591         mc_latency_mclk.full += k1.full;
2592
2593         mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff);
2594         mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff);
2595
2596         /*
2597           HW cursor time assuming worst case of full size colour cursor.
2598         */
2599         temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
2600         temp_ff.full += trcd_ff.full;
2601         if (temp_ff.full < tras_ff.full)
2602                 temp_ff.full = tras_ff.full;
2603         cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff);
2604
2605         temp_ff.full = rfixed_const(cur_size);
2606         cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff);
2607         /*
2608           Find the total latency for the display data.
2609         */
2610         disp_latency_overhead.full = rfixed_const(8);
2611         disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff);
2612         mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2613         mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
2614
2615         if (mc_latency_mclk.full > mc_latency_sclk.full)
2616                 disp_latency.full = mc_latency_mclk.full;
2617         else
2618                 disp_latency.full = mc_latency_sclk.full;
2619
2620         /* setup Max GRPH_STOP_REQ default value */
2621         if (ASIC_IS_RV100(rdev))
2622                 max_stop_req = 0x5c;
2623         else
2624                 max_stop_req = 0x7c;
2625
2626         if (mode1) {
2627                 /*  CRTC1
2628                     Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2629                     GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2630                 */
2631                 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
2632
2633                 if (stop_req > max_stop_req)
2634                         stop_req = max_stop_req;
2635
2636                 /*
2637                   Find the drain rate of the display buffer.
2638                 */
2639                 temp_ff.full = rfixed_const((16/pixel_bytes1));
2640                 disp_drain_rate.full = rfixed_div(pix_clk, temp_ff);
2641
2642                 /*
2643                   Find the critical point of the display buffer.
2644                 */
2645                 crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency);
2646                 crit_point_ff.full += rfixed_const_half(0);
2647
2648                 critical_point = rfixed_trunc(crit_point_ff);
2649
2650                 if (rdev->disp_priority == 2) {
2651                         critical_point = 0;
2652                 }
2653
2654                 /*
2655                   The critical point should never be above max_stop_req-4.  Setting
2656                   GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
2657                 */
2658                 if (max_stop_req - critical_point < 4)
2659                         critical_point = 0;
2660
2661                 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
2662                         /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
2663                         critical_point = 0x10;
2664                 }
2665
2666                 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
2667                 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
2668                 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2669                 temp &= ~(RADEON_GRPH_START_REQ_MASK);
2670                 if ((rdev->family == CHIP_R350) &&
2671                     (stop_req > 0x15)) {
2672                         stop_req -= 0x10;
2673                 }
2674                 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2675                 temp |= RADEON_GRPH_BUFFER_SIZE;
2676                 temp &= ~(RADEON_GRPH_CRITICAL_CNTL   |
2677                           RADEON_GRPH_CRITICAL_AT_SOF |
2678                           RADEON_GRPH_STOP_CNTL);
2679                 /*
2680                   Write the result into the register.
2681                 */
2682                 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2683                                                        (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2684
2685 #if 0
2686                 if ((rdev->family == CHIP_RS400) ||
2687                     (rdev->family == CHIP_RS480)) {
2688                         /* attempt to program RS400 disp regs correctly ??? */
2689                         temp = RREG32(RS400_DISP1_REG_CNTL);
2690                         temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
2691                                   RS400_DISP1_STOP_REQ_LEVEL_MASK);
2692                         WREG32(RS400_DISP1_REQ_CNTL1, (temp |
2693                                                        (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2694                                                        (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2695                         temp = RREG32(RS400_DMIF_MEM_CNTL1);
2696                         temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
2697                                   RS400_DISP1_CRITICAL_POINT_STOP_MASK);
2698                         WREG32(RS400_DMIF_MEM_CNTL1, (temp |
2699                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
2700                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
2701                 }
2702 #endif
2703
2704                 DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
2705                           /*      (unsigned int)info->SavedReg->grph_buffer_cntl, */
2706                           (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
2707         }
2708
2709         if (mode2) {
2710                 u32 grph2_cntl;
2711                 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
2712
2713                 if (stop_req > max_stop_req)
2714                         stop_req = max_stop_req;
2715
2716                 /*
2717                   Find the drain rate of the display buffer.
2718                 */
2719                 temp_ff.full = rfixed_const((16/pixel_bytes2));
2720                 disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff);
2721
2722                 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
2723                 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
2724                 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2725                 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
2726                 if ((rdev->family == CHIP_R350) &&
2727                     (stop_req > 0x15)) {
2728                         stop_req -= 0x10;
2729                 }
2730                 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2731                 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
2732                 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL   |
2733                           RADEON_GRPH_CRITICAL_AT_SOF |
2734                           RADEON_GRPH_STOP_CNTL);
2735
2736                 if ((rdev->family == CHIP_RS100) ||
2737                     (rdev->family == CHIP_RS200))
2738                         critical_point2 = 0;
2739                 else {
2740                         temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
2741                         temp_ff.full = rfixed_const(temp);
2742                         temp_ff.full = rfixed_mul(mclk_ff, temp_ff);
2743                         if (sclk_ff.full < temp_ff.full)
2744                                 temp_ff.full = sclk_ff.full;
2745
2746                         read_return_rate.full = temp_ff.full;
2747
2748                         if (mode1) {
2749                                 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
2750                                 time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff);
2751                         } else {
2752                                 time_disp1_drop_priority.full = 0;
2753                         }
2754                         crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
2755                         crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2);
2756                         crit_point_ff.full += rfixed_const_half(0);
2757
2758                         critical_point2 = rfixed_trunc(crit_point_ff);
2759
2760                         if (rdev->disp_priority == 2) {
2761                                 critical_point2 = 0;
2762                         }
2763
2764                         if (max_stop_req - critical_point2 < 4)
2765                                 critical_point2 = 0;
2766
2767                 }
2768
2769                 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
2770                         /* some R300 cards have problem with this set to 0 */
2771                         critical_point2 = 0x10;
2772                 }
2773
2774                 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2775                                                   (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2776
2777                 if ((rdev->family == CHIP_RS400) ||
2778                     (rdev->family == CHIP_RS480)) {
2779 #if 0
2780                         /* attempt to program RS400 disp2 regs correctly ??? */
2781                         temp = RREG32(RS400_DISP2_REQ_CNTL1);
2782                         temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
2783                                   RS400_DISP2_STOP_REQ_LEVEL_MASK);
2784                         WREG32(RS400_DISP2_REQ_CNTL1, (temp |
2785                                                        (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2786                                                        (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2787                         temp = RREG32(RS400_DISP2_REQ_CNTL2);
2788                         temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
2789                                   RS400_DISP2_CRITICAL_POINT_STOP_MASK);
2790                         WREG32(RS400_DISP2_REQ_CNTL2, (temp |
2791                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
2792                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
2793 #endif
2794                         WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
2795                         WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
2796                         WREG32(RS400_DMIF_MEM_CNTL1,  0x29CA71DC);
2797                         WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
2798                 }
2799
2800                 DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
2801                           (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
2802         }
2803 }
2804
2805 static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2806 {
2807         DRM_ERROR("pitch                      %d\n", t->pitch);
2808         DRM_ERROR("use_pitch                  %d\n", t->use_pitch);
2809         DRM_ERROR("width                      %d\n", t->width);
2810         DRM_ERROR("width_11                   %d\n", t->width_11);
2811         DRM_ERROR("height                     %d\n", t->height);
2812         DRM_ERROR("height_11                  %d\n", t->height_11);
2813         DRM_ERROR("num levels                 %d\n", t->num_levels);
2814         DRM_ERROR("depth                      %d\n", t->txdepth);
2815         DRM_ERROR("bpp                        %d\n", t->cpp);
2816         DRM_ERROR("coordinate type            %d\n", t->tex_coord_type);
2817         DRM_ERROR("width round to power of 2  %d\n", t->roundup_w);
2818         DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2819         DRM_ERROR("compress format            %d\n", t->compress_format);
2820 }
2821
2822 static int r100_cs_track_cube(struct radeon_device *rdev,
2823                               struct r100_cs_track *track, unsigned idx)
2824 {
2825         unsigned face, w, h;
2826         struct radeon_bo *cube_robj;
2827         unsigned long size;
2828
2829         for (face = 0; face < 5; face++) {
2830                 cube_robj = track->textures[idx].cube_info[face].robj;
2831                 w = track->textures[idx].cube_info[face].width;
2832                 h = track->textures[idx].cube_info[face].height;
2833
2834                 size = w * h;
2835                 size *= track->textures[idx].cpp;
2836
2837                 size += track->textures[idx].cube_info[face].offset;
2838
2839                 if (size > radeon_bo_size(cube_robj)) {
2840                         DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2841                                   size, radeon_bo_size(cube_robj));
2842                         r100_cs_track_texture_print(&track->textures[idx]);
2843                         return -1;
2844                 }
2845         }
2846         return 0;
2847 }
2848
2849 static int r100_track_compress_size(int compress_format, int w, int h)
2850 {
2851         int block_width, block_height, block_bytes;
2852         int wblocks, hblocks;
2853         int min_wblocks;
2854         int sz;
2855
2856         block_width = 4;
2857         block_height = 4;
2858
2859         switch (compress_format) {
2860         case R100_TRACK_COMP_DXT1:
2861                 block_bytes = 8;
2862                 min_wblocks = 4;
2863                 break;
2864         default:
2865         case R100_TRACK_COMP_DXT35:
2866                 block_bytes = 16;
2867                 min_wblocks = 2;
2868                 break;
2869         }
2870
2871         hblocks = (h + block_height - 1) / block_height;
2872         wblocks = (w + block_width - 1) / block_width;
2873         if (wblocks < min_wblocks)
2874                 wblocks = min_wblocks;
2875         sz = wblocks * hblocks * block_bytes;
2876         return sz;
2877 }
2878
2879 static int r100_cs_track_texture_check(struct radeon_device *rdev,
2880                                        struct r100_cs_track *track)
2881 {
2882         struct radeon_bo *robj;
2883         unsigned long size;
2884         unsigned u, i, w, h;
2885         int ret;
2886
2887         for (u = 0; u < track->num_texture; u++) {
2888                 if (!track->textures[u].enabled)
2889                         continue;
2890                 robj = track->textures[u].robj;
2891                 if (robj == NULL) {
2892                         DRM_ERROR("No texture bound to unit %u\n", u);
2893                         return -EINVAL;
2894                 }
2895                 size = 0;
2896                 for (i = 0; i <= track->textures[u].num_levels; i++) {
2897                         if (track->textures[u].use_pitch) {
2898                                 if (rdev->family < CHIP_R300)
2899                                         w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2900                                 else
2901                                         w = track->textures[u].pitch / (1 << i);
2902                         } else {
2903                                 w = track->textures[u].width;
2904                                 if (rdev->family >= CHIP_RV515)
2905                                         w |= track->textures[u].width_11;
2906                                 w = w / (1 << i);
2907                                 if (track->textures[u].roundup_w)
2908                                         w = roundup_pow_of_two(w);
2909                         }
2910                         h = track->textures[u].height;
2911                         if (rdev->family >= CHIP_RV515)
2912                                 h |= track->textures[u].height_11;
2913                         h = h / (1 << i);
2914                         if (track->textures[u].roundup_h)
2915                                 h = roundup_pow_of_two(h);
2916                         if (track->textures[u].compress_format) {
2917
2918                                 size += r100_track_compress_size(track->textures[u].compress_format, w, h);
2919                                 /* compressed textures are block based */
2920                         } else
2921                                 size += w * h;
2922                 }
2923                 size *= track->textures[u].cpp;
2924
2925                 switch (track->textures[u].tex_coord_type) {
2926                 case 0:
2927                         break;
2928                 case 1:
2929                         size *= (1 << track->textures[u].txdepth);
2930                         break;
2931                 case 2:
2932                         if (track->separate_cube) {
2933                                 ret = r100_cs_track_cube(rdev, track, u);
2934                                 if (ret)
2935                                         return ret;
2936                         } else
2937                                 size *= 6;
2938                         break;
2939                 default:
2940                         DRM_ERROR("Invalid texture coordinate type %u for unit "
2941                                   "%u\n", track->textures[u].tex_coord_type, u);
2942                         return -EINVAL;
2943                 }
2944                 if (size > radeon_bo_size(robj)) {
2945                         DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2946                                   "%lu\n", u, size, radeon_bo_size(robj));
2947                         r100_cs_track_texture_print(&track->textures[u]);
2948                         return -EINVAL;
2949                 }
2950         }
2951         return 0;
2952 }
2953
2954 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2955 {
2956         unsigned i;
2957         unsigned long size;
2958         unsigned prim_walk;
2959         unsigned nverts;
2960
2961         for (i = 0; i < track->num_cb; i++) {
2962                 if (track->cb[i].robj == NULL) {
2963                         if (!(track->fastfill || track->color_channel_mask ||
2964                               track->blend_read_enable)) {
2965                                 continue;
2966                         }
2967                         DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2968                         return -EINVAL;
2969                 }
2970                 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2971                 size += track->cb[i].offset;
2972                 if (size > radeon_bo_size(track->cb[i].robj)) {
2973                         DRM_ERROR("[drm] Buffer too small for color buffer %d "
2974                                   "(need %lu have %lu) !\n", i, size,
2975                                   radeon_bo_size(track->cb[i].robj));
2976                         DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2977                                   i, track->cb[i].pitch, track->cb[i].cpp,
2978                                   track->cb[i].offset, track->maxy);
2979                         return -EINVAL;
2980                 }
2981         }
2982         if (track->z_enabled) {
2983                 if (track->zb.robj == NULL) {
2984                         DRM_ERROR("[drm] No buffer for z buffer !\n");
2985                         return -EINVAL;
2986                 }
2987                 size = track->zb.pitch * track->zb.cpp * track->maxy;
2988                 size += track->zb.offset;
2989                 if (size > radeon_bo_size(track->zb.robj)) {
2990                         DRM_ERROR("[drm] Buffer too small for z buffer "
2991                                   "(need %lu have %lu) !\n", size,
2992                                   radeon_bo_size(track->zb.robj));
2993                         DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2994                                   track->zb.pitch, track->zb.cpp,
2995                                   track->zb.offset, track->maxy);
2996                         return -EINVAL;
2997                 }
2998         }
2999         prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
3000         nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
3001         switch (prim_walk) {
3002         case 1:
3003                 for (i = 0; i < track->num_arrays; i++) {
3004                         size = track->arrays[i].esize * track->max_indx * 4;
3005                         if (track->arrays[i].robj == NULL) {
3006                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3007                                           "bound\n", prim_walk, i);
3008                                 return -EINVAL;
3009                         }
3010                         if (size > radeon_bo_size(track->arrays[i].robj)) {
3011                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3012                                         "need %lu dwords have %lu dwords\n",
3013                                         prim_walk, i, size >> 2,
3014                                         radeon_bo_size(track->arrays[i].robj)
3015                                         >> 2);
3016                                 DRM_ERROR("Max indices %u\n", track->max_indx);
3017                                 return -EINVAL;
3018                         }
3019                 }
3020                 break;
3021         case 2:
3022                 for (i = 0; i < track->num_arrays; i++) {
3023                         size = track->arrays[i].esize * (nverts - 1) * 4;
3024                         if (track->arrays[i].robj == NULL) {
3025                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3026                                           "bound\n", prim_walk, i);
3027                                 return -EINVAL;
3028                         }
3029                         if (size > radeon_bo_size(track->arrays[i].robj)) {
3030                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3031                                         "need %lu dwords have %lu dwords\n",
3032                                         prim_walk, i, size >> 2,
3033                                         radeon_bo_size(track->arrays[i].robj)
3034                                         >> 2);
3035                                 return -EINVAL;
3036                         }
3037                 }
3038                 break;
3039         case 3:
3040                 size = track->vtx_size * nverts;
3041                 if (size != track->immd_dwords) {
3042                         DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
3043                                   track->immd_dwords, size);
3044                         DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
3045                                   nverts, track->vtx_size);
3046                         return -EINVAL;
3047                 }
3048                 break;
3049         default:
3050                 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3051                           prim_walk);
3052                 return -EINVAL;
3053         }
3054         return r100_cs_track_texture_check(rdev, track);
3055 }
3056
3057 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
3058 {
3059         unsigned i, face;
3060
3061         if (rdev->family < CHIP_R300) {
3062                 track->num_cb = 1;
3063                 if (rdev->family <= CHIP_RS200)
3064                         track->num_texture = 3;
3065                 else
3066                         track->num_texture = 6;
3067                 track->maxy = 2048;
3068                 track->separate_cube = 1;
3069         } else {
3070                 track->num_cb = 4;
3071                 track->num_texture = 16;
3072                 track->maxy = 4096;
3073                 track->separate_cube = 0;
3074         }
3075
3076         for (i = 0; i < track->num_cb; i++) {
3077                 track->cb[i].robj = NULL;
3078                 track->cb[i].pitch = 8192;
3079                 track->cb[i].cpp = 16;
3080                 track->cb[i].offset = 0;
3081         }
3082         track->z_enabled = true;
3083         track->zb.robj = NULL;
3084         track->zb.pitch = 8192;
3085         track->zb.cpp = 4;
3086         track->zb.offset = 0;
3087         track->vtx_size = 0x7F;
3088         track->immd_dwords = 0xFFFFFFFFUL;
3089         track->num_arrays = 11;
3090         track->max_indx = 0x00FFFFFFUL;
3091         for (i = 0; i < track->num_arrays; i++) {
3092                 track->arrays[i].robj = NULL;
3093                 track->arrays[i].esize = 0x7F;
3094         }
3095         for (i = 0; i < track->num_texture; i++) {
3096                 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
3097                 track->textures[i].pitch = 16536;
3098                 track->textures[i].width = 16536;
3099                 track->textures[i].height = 16536;
3100                 track->textures[i].width_11 = 1 << 11;
3101                 track->textures[i].height_11 = 1 << 11;
3102                 track->textures[i].num_levels = 12;
3103                 if (rdev->family <= CHIP_RS200) {
3104                         track->textures[i].tex_coord_type = 0;
3105                         track->textures[i].txdepth = 0;
3106                 } else {
3107                         track->textures[i].txdepth = 16;
3108                         track->textures[i].tex_coord_type = 1;
3109                 }
3110                 track->textures[i].cpp = 64;
3111                 track->textures[i].robj = NULL;
3112                 /* CS IB emission code makes sure texture unit are disabled */
3113                 track->textures[i].enabled = false;
3114                 track->textures[i].roundup_w = true;
3115                 track->textures[i].roundup_h = true;
3116                 if (track->separate_cube)
3117                         for (face = 0; face < 5; face++) {
3118                                 track->textures[i].cube_info[face].robj = NULL;
3119                                 track->textures[i].cube_info[face].width = 16536;
3120                                 track->textures[i].cube_info[face].height = 16536;
3121                                 track->textures[i].cube_info[face].offset = 0;
3122                         }
3123         }
3124 }
3125
3126 int r100_ring_test(struct radeon_device *rdev)
3127 {
3128         uint32_t scratch;
3129         uint32_t tmp = 0;
3130         unsigned i;
3131         int r;
3132
3133         r = radeon_scratch_get(rdev, &scratch);
3134         if (r) {
3135                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3136                 return r;
3137         }
3138         WREG32(scratch, 0xCAFEDEAD);
3139         r = radeon_ring_lock(rdev, 2);
3140         if (r) {
3141                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3142                 radeon_scratch_free(rdev, scratch);
3143                 return r;
3144         }
3145         radeon_ring_write(rdev, PACKET0(scratch, 0));
3146         radeon_ring_write(rdev, 0xDEADBEEF);
3147         radeon_ring_unlock_commit(rdev);
3148         for (i = 0; i < rdev->usec_timeout; i++) {
3149                 tmp = RREG32(scratch);
3150                 if (tmp == 0xDEADBEEF) {
3151                         break;
3152                 }
3153                 DRM_UDELAY(1);
3154         }
3155         if (i < rdev->usec_timeout) {
3156                 DRM_INFO("ring test succeeded in %d usecs\n", i);
3157         } else {
3158                 DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
3159                           scratch, tmp);
3160                 r = -EINVAL;
3161         }
3162         radeon_scratch_free(rdev, scratch);
3163         return r;
3164 }
3165
3166 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3167 {
3168         radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3169         radeon_ring_write(rdev, ib->gpu_addr);
3170         radeon_ring_write(rdev, ib->length_dw);
3171 }
3172
3173 int r100_ib_test(struct radeon_device *rdev)
3174 {
3175         struct radeon_ib *ib;
3176         uint32_t scratch;
3177         uint32_t tmp = 0;
3178         unsigned i;
3179         int r;
3180
3181         r = radeon_scratch_get(rdev, &scratch);
3182         if (r) {
3183                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3184                 return r;
3185         }
3186         WREG32(scratch, 0xCAFEDEAD);
3187         r = radeon_ib_get(rdev, &ib);
3188         if (r) {
3189                 return r;
3190         }
3191         ib->ptr[0] = PACKET0(scratch, 0);
3192         ib->ptr[1] = 0xDEADBEEF;
3193         ib->ptr[2] = PACKET2(0);
3194         ib->ptr[3] = PACKET2(0);
3195         ib->ptr[4] = PACKET2(0);
3196         ib->ptr[5] = PACKET2(0);
3197         ib->ptr[6] = PACKET2(0);
3198         ib->ptr[7] = PACKET2(0);
3199         ib->length_dw = 8;
3200         r = radeon_ib_schedule(rdev, ib);
3201         if (r) {
3202                 radeon_scratch_free(rdev, scratch);
3203                 radeon_ib_free(rdev, &ib);
3204                 return r;
3205         }
3206         r = radeon_fence_wait(ib->fence, false);
3207         if (r) {
3208                 return r;
3209         }
3210         for (i = 0; i < rdev->usec_timeout; i++) {
3211                 tmp = RREG32(scratch);
3212                 if (tmp == 0xDEADBEEF) {
3213                         break;
3214                 }
3215                 DRM_UDELAY(1);
3216         }
3217         if (i < rdev->usec_timeout) {
3218                 DRM_INFO("ib test succeeded in %u usecs\n", i);
3219         } else {
3220                 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
3221                           scratch, tmp);
3222                 r = -EINVAL;
3223         }
3224         radeon_scratch_free(rdev, scratch);
3225         radeon_ib_free(rdev, &ib);
3226         return r;
3227 }
3228
3229 void r100_ib_fini(struct radeon_device *rdev)
3230 {
3231         radeon_ib_pool_fini(rdev);
3232 }
3233
3234 int r100_ib_init(struct radeon_device *rdev)
3235 {
3236         int r;
3237
3238         r = radeon_ib_pool_init(rdev);
3239         if (r) {
3240                 dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r);
3241                 r100_ib_fini(rdev);
3242                 return r;
3243         }
3244         r = r100_ib_test(rdev);
3245         if (r) {
3246                 dev_err(rdev->dev, "failled testing IB (%d).\n", r);
3247                 r100_ib_fini(rdev);
3248                 return r;
3249         }
3250         return 0;
3251 }
3252
3253 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3254 {
3255         /* Shutdown CP we shouldn't need to do that but better be safe than
3256          * sorry
3257          */
3258         rdev->cp.ready = false;
3259         WREG32(R_000740_CP_CSQ_CNTL, 0);
3260
3261         /* Save few CRTC registers */
3262         save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3263         save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3264         save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3265         save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3266         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3267                 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3268                 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3269         }
3270
3271         /* Disable VGA aperture access */
3272         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3273         /* Disable cursor, overlay, crtc */
3274         WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3275         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3276                                         S_000054_CRTC_DISPLAY_DIS(1));
3277         WREG32(R_000050_CRTC_GEN_CNTL,
3278                         (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3279                         S_000050_CRTC_DISP_REQ_EN_B(1));
3280         WREG32(R_000420_OV0_SCALE_CNTL,
3281                 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3282         WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3283         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3284                 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3285                                                 S_000360_CUR2_LOCK(1));
3286                 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3287                         (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3288                         S_0003F8_CRTC2_DISPLAY_DIS(1) |
3289                         S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3290                 WREG32(R_000360_CUR2_OFFSET,
3291                         C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3292         }
3293 }
3294
3295 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3296 {
3297         /* Update base address for crtc */
3298         WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3299         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3300                 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3301         }
3302         /* Restore CRTC registers */
3303         WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3304         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3305         WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3306         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3307                 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3308         }
3309 }
3310
3311 void r100_vga_render_disable(struct radeon_device *rdev)
3312 {
3313         u32 tmp;
3314
3315         tmp = RREG8(R_0003C2_GENMO_WT);
3316         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3317 }
3318
3319 static void r100_debugfs(struct radeon_device *rdev)
3320 {
3321         int r;
3322
3323         r = r100_debugfs_mc_info_init(rdev);
3324         if (r)
3325                 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3326 }
3327
3328 static void r100_mc_program(struct radeon_device *rdev)
3329 {
3330         struct r100_mc_save save;
3331
3332         /* Stops all mc clients */
3333         r100_mc_stop(rdev, &save);
3334         if (rdev->flags & RADEON_IS_AGP) {
3335                 WREG32(R_00014C_MC_AGP_LOCATION,
3336                         S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3337                         S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3338                 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3339                 if (rdev->family > CHIP_RV200)
3340                         WREG32(R_00015C_AGP_BASE_2,
3341                                 upper_32_bits(rdev->mc.agp_base) & 0xff);
3342         } else {
3343                 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3344                 WREG32(R_000170_AGP_BASE, 0);
3345                 if (rdev->family > CHIP_RV200)
3346                         WREG32(R_00015C_AGP_BASE_2, 0);
3347         }
3348         /* Wait for mc idle */
3349         if (r100_mc_wait_for_idle(rdev))
3350                 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3351         /* Program MC, should be a 32bits limited address space */
3352         WREG32(R_000148_MC_FB_LOCATION,
3353                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3354                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3355         r100_mc_resume(rdev, &save);
3356 }
3357
3358 void r100_clock_startup(struct radeon_device *rdev)
3359 {
3360         u32 tmp;
3361
3362         if (radeon_dynclks != -1 && radeon_dynclks)
3363                 radeon_legacy_set_clock_gating(rdev, 1);
3364         /* We need to force on some of the block */
3365         tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3366         tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3367         if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3368                 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3369         WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3370 }
3371
3372 static int r100_startup(struct radeon_device *rdev)
3373 {
3374         int r;
3375
3376         /* set common regs */
3377         r100_set_common_regs(rdev);
3378         /* program mc */
3379         r100_mc_program(rdev);
3380         /* Resume clock */
3381         r100_clock_startup(rdev);
3382         /* Initialize GPU configuration (# pipes, ...) */
3383         r100_gpu_init(rdev);
3384         /* Initialize GART (initialize after TTM so we can allocate
3385          * memory through TTM but finalize after TTM) */
3386         r100_enable_bm(rdev);
3387         if (rdev->flags & RADEON_IS_PCI) {
3388                 r = r100_pci_gart_enable(rdev);
3389                 if (r)
3390                         return r;
3391         }
3392         /* Enable IRQ */
3393         r100_irq_set(rdev);
3394         rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3395         /* 1M ring buffer */
3396         r = r100_cp_init(rdev, 1024 * 1024);
3397         if (r) {
3398                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
3399                 return r;
3400         }
3401         r = r100_wb_init(rdev);
3402         if (r)
3403                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
3404         r = r100_ib_init(rdev);
3405         if (r) {
3406                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
3407                 return r;
3408         }
3409         return 0;
3410 }
3411
3412 int r100_resume(struct radeon_device *rdev)
3413 {
3414         /* Make sur GART are not working */
3415         if (rdev->flags & RADEON_IS_PCI)
3416                 r100_pci_gart_disable(rdev);
3417         /* Resume clock before doing reset */
3418         r100_clock_startup(rdev);
3419         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3420         if (radeon_gpu_reset(rdev)) {
3421                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3422                         RREG32(R_000E40_RBBM_STATUS),
3423                         RREG32(R_0007C0_CP_STAT));
3424         }
3425         /* post */
3426         radeon_combios_asic_init(rdev->ddev);
3427         /* Resume clock after posting */
3428         r100_clock_startup(rdev);
3429         /* Initialize surface registers */
3430         radeon_surface_init(rdev);
3431         return r100_startup(rdev);
3432 }
3433
3434 int r100_suspend(struct radeon_device *rdev)
3435 {
3436         r100_cp_disable(rdev);
3437         r100_wb_disable(rdev);
3438         r100_irq_disable(rdev);
3439         if (rdev->flags & RADEON_IS_PCI)
3440                 r100_pci_gart_disable(rdev);
3441         return 0;
3442 }
3443
3444 void r100_fini(struct radeon_device *rdev)
3445 {
3446         radeon_pm_fini(rdev);
3447         r100_cp_fini(rdev);
3448         r100_wb_fini(rdev);
3449         r100_ib_fini(rdev);
3450         radeon_gem_fini(rdev);
3451         if (rdev->flags & RADEON_IS_PCI)
3452                 r100_pci_gart_fini(rdev);
3453         radeon_agp_fini(rdev);
3454         radeon_irq_kms_fini(rdev);
3455         radeon_fence_driver_fini(rdev);
3456         radeon_bo_fini(rdev);
3457         radeon_atombios_fini(rdev);
3458         kfree(rdev->bios);
3459         rdev->bios = NULL;
3460 }
3461
3462 int r100_init(struct radeon_device *rdev)
3463 {
3464         int r;
3465
3466         /* Register debugfs file specific to this group of asics */
3467         r100_debugfs(rdev);
3468         /* Disable VGA */
3469         r100_vga_render_disable(rdev);
3470         /* Initialize scratch registers */
3471         radeon_scratch_init(rdev);
3472         /* Initialize surface registers */
3473         radeon_surface_init(rdev);
3474         /* TODO: disable VGA need to use VGA request */
3475         /* BIOS*/
3476         if (!radeon_get_bios(rdev)) {
3477                 if (ASIC_IS_AVIVO(rdev))
3478                         return -EINVAL;
3479         }
3480         if (rdev->is_atom_bios) {
3481                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
3482                 return -EINVAL;
3483         } else {
3484                 r = radeon_combios_init(rdev);
3485                 if (r)
3486                         return r;
3487         }
3488         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3489         if (radeon_gpu_reset(rdev)) {
3490                 dev_warn(rdev->dev,
3491                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3492                         RREG32(R_000E40_RBBM_STATUS),
3493                         RREG32(R_0007C0_CP_STAT));
3494         }
3495         /* check if cards are posted or not */
3496         if (radeon_boot_test_post_card(rdev) == false)
3497                 return -EINVAL;
3498         /* Set asic errata */
3499         r100_errata(rdev);
3500         /* Initialize clocks */
3501         radeon_get_clock_info(rdev->ddev);
3502         /* Initialize power management */
3503         radeon_pm_init(rdev);
3504         /* initialize AGP */
3505         if (rdev->flags & RADEON_IS_AGP) {
3506                 r = radeon_agp_init(rdev);
3507                 if (r) {
3508                         radeon_agp_disable(rdev);
3509                 }
3510         }
3511         /* initialize VRAM */
3512         r100_mc_init(rdev);
3513         /* Fence driver */
3514         r = radeon_fence_driver_init(rdev);
3515         if (r)
3516                 return r;
3517         r = radeon_irq_kms_init(rdev);
3518         if (r)
3519                 return r;
3520         /* Memory manager */
3521         r = radeon_bo_init(rdev);
3522         if (r)
3523                 return r;
3524         if (rdev->flags & RADEON_IS_PCI) {
3525                 r = r100_pci_gart_init(rdev);
3526                 if (r)
3527                         return r;
3528         }
3529         r100_set_safe_registers(rdev);
3530         rdev->accel_working = true;
3531         r = r100_startup(rdev);
3532         if (r) {
3533                 /* Somethings want wront with the accel init stop accel */
3534                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
3535                 r100_cp_fini(rdev);
3536                 r100_wb_fini(rdev);
3537                 r100_ib_fini(rdev);
3538                 radeon_irq_kms_fini(rdev);
3539                 if (rdev->flags & RADEON_IS_PCI)
3540                         r100_pci_gart_fini(rdev);
3541                 rdev->accel_working = false;
3542         }
3543         return 0;
3544 }