SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/r100.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "radeon_drm.h"
  32 #include "radeon_microcode.h"
  33 #include "radeon_reg.h"
  34 #include "radeon.h"
  35
  36 /* This files gather functions specifics to:
  37  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
  38  *
  39  * Some of these functions might be used by newer ASICs.
  40  */
  41 void r100_hdp_reset(struct radeon_device *rdev);
  42 void r100_gpu_init(struct radeon_device *rdev);
  43 int r100_gui_wait_for_idle(struct radeon_device *rdev);
  44 int r100_mc_wait_for_idle(struct radeon_device *rdev);
  45 void r100_gpu_wait_for_vsync(struct radeon_device *rdev);
  46 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev);
  47 int r100_debugfs_mc_info_init(struct radeon_device *rdev);
  48
  49
  50 /*
  51  * PCI GART
  52  */
  53 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
  54 {
  55         /* TODO: can we do somethings here ? */
  56         /* It seems hw only cache one entry so we should discard this
  57          * entry otherwise if first GPU GART read hit this entry it
  58          * could end up in wrong address. */
  59 }
  60
  61 int r100_pci_gart_enable(struct radeon_device *rdev)
  62 {
  63         uint32_t tmp;
  64         int r;
  65
  66         /* Initialize common gart structure */
  67         r = radeon_gart_init(rdev);
  68         if (r) {
  69                 return r;
  70         }
  71         if (rdev->gart.table.ram.ptr == NULL) {
  72                 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
  73                 r = radeon_gart_table_ram_alloc(rdev);
  74                 if (r) {
  75                         return r;
  76                 }
  77         }
  78         /* discard memory request outside of configured range */
  79         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
  80         WREG32(RADEON_AIC_CNTL, tmp);
  81         /* set address range for PCI address translate */
  82         WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_location);
  83         tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
  84         WREG32(RADEON_AIC_HI_ADDR, tmp);
  85         /* Enable bus mastering */
  86         tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
  87         WREG32(RADEON_BUS_CNTL, tmp);
  88         /* set PCI GART page-table base address */
  89         WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
  90         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
  91         WREG32(RADEON_AIC_CNTL, tmp);
  92         r100_pci_gart_tlb_flush(rdev);
  93         rdev->gart.ready = true;
  94         return 0;
  95 }
  96
  97 void r100_pci_gart_disable(struct radeon_device *rdev)
  98 {
  99         uint32_t tmp;
 100
 101         /* discard memory request outside of configured range */
 102         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 103         WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
 104         WREG32(RADEON_AIC_LO_ADDR, 0);
 105         WREG32(RADEON_AIC_HI_ADDR, 0);
 106 }
 107
 108 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
 109 {
 110         if (i < 0 || i > rdev->gart.num_gpu_pages) {
 111                 return -EINVAL;
 112         }
 113         rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
 114         return 0;
 115 }
 116
 117 int r100_gart_enable(struct radeon_device *rdev)
 118 {
 119         if (rdev->flags & RADEON_IS_AGP) {
 120                 r100_pci_gart_disable(rdev);
 121                 return 0;
 122         }
 123         return r100_pci_gart_enable(rdev);
 124 }
 125
 126
 127 /*
 128  * MC
 129  */
 130 void r100_mc_disable_clients(struct radeon_device *rdev)
 131 {
 132         uint32_t ov0_scale_cntl, crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl;
 133
 134         /* FIXME: is this function correct for rs100,rs200,rs300 ? */
 135         if (r100_gui_wait_for_idle(rdev)) {
 136                 printk(KERN_WARNING "Failed to wait GUI idle while "
 137                        "programming pipes. Bad things might happen.\n");
 138         }
 139
 140         /* stop display and memory access */
 141         ov0_scale_cntl = RREG32(RADEON_OV0_SCALE_CNTL);
 142         WREG32(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl & ~RADEON_SCALER_ENABLE);
 143         crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
 144         WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl | RADEON_CRTC_DISPLAY_DIS);
 145         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
 146
 147         r100_gpu_wait_for_vsync(rdev);
 148
 149         WREG32(RADEON_CRTC_GEN_CNTL,
 150                (crtc_gen_cntl & ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_ICON_EN)) |
 151                RADEON_CRTC_DISP_REQ_EN_B | RADEON_CRTC_EXT_DISP_EN);
 152
 153         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
 154                 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
 155
 156                 r100_gpu_wait_for_vsync2(rdev);
 157                 WREG32(RADEON_CRTC2_GEN_CNTL,
 158                        (crtc2_gen_cntl &
 159                         ~(RADEON_CRTC2_CUR_EN | RADEON_CRTC2_ICON_EN)) |
 160                        RADEON_CRTC2_DISP_REQ_EN_B);
 161         }
 162
 163         udelay(500);
 164 }
 165
 166 void r100_mc_setup(struct radeon_device *rdev)
 167 {
 168         uint32_t tmp;
 169         int r;
 170
 171         r = r100_debugfs_mc_info_init(rdev);
 172         if (r) {
 173                 DRM_ERROR("Failed to register debugfs file for R100 MC !\n");
 174         }
 175         /* Write VRAM size in case we are limiting it */
 176         WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size);
 177         tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1;
 178         tmp = REG_SET(RADEON_MC_FB_TOP, tmp >> 16);
 179         tmp |= REG_SET(RADEON_MC_FB_START, rdev->mc.vram_location >> 16);
 180         WREG32(RADEON_MC_FB_LOCATION, tmp);
 181
 182         /* Enable bus mastering */
 183         tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 184         WREG32(RADEON_BUS_CNTL, tmp);
 185
 186         if (rdev->flags & RADEON_IS_AGP) {
 187                 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
 188                 tmp = REG_SET(RADEON_MC_AGP_TOP, tmp >> 16);
 189                 tmp |= REG_SET(RADEON_MC_AGP_START, rdev->mc.gtt_location >> 16);
 190                 WREG32(RADEON_MC_AGP_LOCATION, tmp);
 191                 WREG32(RADEON_AGP_BASE, rdev->mc.agp_base);
 192         } else {
 193                 WREG32(RADEON_MC_AGP_LOCATION, 0x0FFFFFFF);
 194                 WREG32(RADEON_AGP_BASE, 0);
 195         }
 196
 197         tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
 198         tmp |= (7 << 28);
 199         WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
 200         (void)RREG32(RADEON_HOST_PATH_CNTL);
 201         WREG32(RADEON_HOST_PATH_CNTL, tmp);
 202         (void)RREG32(RADEON_HOST_PATH_CNTL);
 203 }
 204
 205 int r100_mc_init(struct radeon_device *rdev)
 206 {
 207         int r;
 208
 209         if (r100_debugfs_rbbm_init(rdev)) {
 210                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
 211         }
 212
 213         r100_gpu_init(rdev);
 214         /* Disable gart which also disable out of gart access */
 215         r100_pci_gart_disable(rdev);
 216
 217         /* Setup GPU memory space */
 218         rdev->mc.gtt_location = 0xFFFFFFFFUL;
 219         if (rdev->flags & RADEON_IS_AGP) {
 220                 r = radeon_agp_init(rdev);
 221                 if (r) {
 222                         printk(KERN_WARNING "[drm] Disabling AGP\n");
 223                         rdev->flags &= ~RADEON_IS_AGP;
 224                         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 225                 } else {
 226                         rdev->mc.gtt_location = rdev->mc.agp_base;
 227                 }
 228         }
 229         r = radeon_mc_setup(rdev);
 230         if (r) {
 231                 return r;
 232         }
 233
 234         r100_mc_disable_clients(rdev);
 235         if (r100_mc_wait_for_idle(rdev)) {
 236                 printk(KERN_WARNING "Failed to wait MC idle while "
 237                        "programming pipes. Bad things might happen.\n");
 238         }
 239
 240         r100_mc_setup(rdev);
 241         return 0;
 242 }
 243
 244 void r100_mc_fini(struct radeon_device *rdev)
 245 {
 246         r100_pci_gart_disable(rdev);
 247         radeon_gart_table_ram_free(rdev);
 248         radeon_gart_fini(rdev);
 249 }
 250
 251
 252 /*
 253  * Fence emission
 254  */
 255 void r100_fence_ring_emit(struct radeon_device *rdev,
 256                           struct radeon_fence *fence)
 257 {
 258         /* Who ever call radeon_fence_emit should call ring_lock and ask
 259          * for enough space (today caller are ib schedule and buffer move) */
 260         /* Wait until IDLE & CLEAN */
 261         radeon_ring_write(rdev, PACKET0(0x1720, 0));
 262         radeon_ring_write(rdev, (1 << 16) | (1 << 17));
 263         /* Emit fence sequence & fire IRQ */
 264         radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
 265         radeon_ring_write(rdev, fence->seq);
 266         radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
 267         radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
 268 }
 269
 270
 271 /*
 272  * Writeback
 273  */
 274 int r100_wb_init(struct radeon_device *rdev)
 275 {
 276         int r;
 277
 278         if (rdev->wb.wb_obj == NULL) {
 279                 r = radeon_object_create(rdev, NULL, 4096,
 280                                          true,
 281                                          RADEON_GEM_DOMAIN_GTT,
 282                                          false, &rdev->wb.wb_obj);
 283                 if (r) {
 284                         DRM_ERROR("radeon: failed to create WB buffer (%d).\n", r);
 285                         return r;
 286                 }
 287                 r = radeon_object_pin(rdev->wb.wb_obj,
 288                                       RADEON_GEM_DOMAIN_GTT,
 289                                       &rdev->wb.gpu_addr);
 290                 if (r) {
 291                         DRM_ERROR("radeon: failed to pin WB buffer (%d).\n", r);
 292                         return r;
 293                 }
 294                 r = radeon_object_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
 295                 if (r) {
 296                         DRM_ERROR("radeon: failed to map WB buffer (%d).\n", r);
 297                         return r;
 298                 }
 299         }
 300         WREG32(0x774, rdev->wb.gpu_addr);
 301         WREG32(0x70C, rdev->wb.gpu_addr + 1024);
 302         WREG32(0x770, 0xff);
 303         return 0;
 304 }
 305
 306 void r100_wb_fini(struct radeon_device *rdev)
 307 {
 308         if (rdev->wb.wb_obj) {
 309                 radeon_object_kunmap(rdev->wb.wb_obj);
 310                 radeon_object_unpin(rdev->wb.wb_obj);
 311                 radeon_object_unref(&rdev->wb.wb_obj);
 312                 rdev->wb.wb = NULL;
 313                 rdev->wb.wb_obj = NULL;
 314         }
 315 }
 316
 317 int r100_copy_blit(struct radeon_device *rdev,
 318                    uint64_t src_offset,
 319                    uint64_t dst_offset,
 320                    unsigned num_pages,
 321                    struct radeon_fence *fence)
 322 {
 323         uint32_t cur_pages;
 324         uint32_t stride_bytes = PAGE_SIZE;
 325         uint32_t pitch;
 326         uint32_t stride_pixels;
 327         unsigned ndw;
 328         int num_loops;
 329         int r = 0;
 330
 331         /* radeon limited to 16k stride */
 332         stride_bytes &= 0x3fff;
 333         /* radeon pitch is /64 */
 334         pitch = stride_bytes / 64;
 335         stride_pixels = stride_bytes / 4;
 336         num_loops = DIV_ROUND_UP(num_pages, 8191);
 337
 338         /* Ask for enough room for blit + flush + fence */
 339         ndw = 64 + (10 * num_loops);
 340         r = radeon_ring_lock(rdev, ndw);
 341         if (r) {
 342                 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
 343                 return -EINVAL;
 344         }
 345         while (num_pages > 0) {
 346                 cur_pages = num_pages;
 347                 if (cur_pages > 8191) {
 348                         cur_pages = 8191;
 349                 }
 350                 num_pages -= cur_pages;
 351
 352                 /* pages are in Y direction - height
 353                    page width in X direction - width */
 354                 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
 355                 radeon_ring_write(rdev,
 356                                   RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
 357                                   RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 358                                   RADEON_GMC_SRC_CLIPPING |
 359                                   RADEON_GMC_DST_CLIPPING |
 360                                   RADEON_GMC_BRUSH_NONE |
 361                                   (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
 362                                   RADEON_GMC_SRC_DATATYPE_COLOR |
 363                                   RADEON_ROP3_S |
 364                                   RADEON_DP_SRC_SOURCE_MEMORY |
 365                                   RADEON_GMC_CLR_CMP_CNTL_DIS |
 366                                   RADEON_GMC_WR_MSK_DIS);
 367                 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
 368                 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
 369                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
 370                 radeon_ring_write(rdev, 0);
 371                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
 372                 radeon_ring_write(rdev, num_pages);
 373                 radeon_ring_write(rdev, num_pages);
 374                 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
 375         }
 376         radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
 377         radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
 378         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 379         radeon_ring_write(rdev,
 380                           RADEON_WAIT_2D_IDLECLEAN |
 381                           RADEON_WAIT_HOST_IDLECLEAN |
 382                           RADEON_WAIT_DMA_GUI_IDLE);
 383         if (fence) {
 384                 r = radeon_fence_emit(rdev, fence);
 385         }
 386         radeon_ring_unlock_commit(rdev);
 387         return r;
 388 }
 389
 390
 391 /*
 392  * CP
 393  */
 394 void r100_ring_start(struct radeon_device *rdev)
 395 {
 396         int r;
 397
 398         r = radeon_ring_lock(rdev, 2);
 399         if (r) {
 400                 return;
 401         }
 402         radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
 403         radeon_ring_write(rdev,
 404                           RADEON_ISYNC_ANY2D_IDLE3D |
 405                           RADEON_ISYNC_ANY3D_IDLE2D |
 406                           RADEON_ISYNC_WAIT_IDLEGUI |
 407                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 408         radeon_ring_unlock_commit(rdev);
 409 }
 410
 411 static void r100_cp_load_microcode(struct radeon_device *rdev)
 412 {
 413         int i;
 414
 415         if (r100_gui_wait_for_idle(rdev)) {
 416                 printk(KERN_WARNING "Failed to wait GUI idle while "
 417                        "programming pipes. Bad things might happen.\n");
 418         }
 419
 420         WREG32(RADEON_CP_ME_RAM_ADDR, 0);
 421         if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
 422             (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
 423             (rdev->family == CHIP_RS200)) {
 424                 DRM_INFO("Loading R100 Microcode\n");
 425                 for (i = 0; i < 256; i++) {
 426                         WREG32(RADEON_CP_ME_RAM_DATAH, R100_cp_microcode[i][1]);
 427                         WREG32(RADEON_CP_ME_RAM_DATAL, R100_cp_microcode[i][0]);
 428                 }
 429         } else if ((rdev->family == CHIP_R200) ||
 430                    (rdev->family == CHIP_RV250) ||
 431                    (rdev->family == CHIP_RV280) ||
 432                    (rdev->family == CHIP_RS300)) {
 433                 DRM_INFO("Loading R200 Microcode\n");
 434                 for (i = 0; i < 256; i++) {
 435                         WREG32(RADEON_CP_ME_RAM_DATAH, R200_cp_microcode[i][1]);
 436                         WREG32(RADEON_CP_ME_RAM_DATAL, R200_cp_microcode[i][0]);
 437                 }
 438         } else if ((rdev->family == CHIP_R300) ||
 439                    (rdev->family == CHIP_R350) ||
 440                    (rdev->family == CHIP_RV350) ||
 441                    (rdev->family == CHIP_RV380) ||
 442                    (rdev->family == CHIP_RS400) ||
 443                    (rdev->family == CHIP_RS480)) {
 444                 DRM_INFO("Loading R300 Microcode\n");
 445                 for (i = 0; i < 256; i++) {
 446                         WREG32(RADEON_CP_ME_RAM_DATAH, R300_cp_microcode[i][1]);
 447                         WREG32(RADEON_CP_ME_RAM_DATAL, R300_cp_microcode[i][0]);
 448                 }
 449         } else if ((rdev->family == CHIP_R420) ||
 450                    (rdev->family == CHIP_R423) ||
 451                    (rdev->family == CHIP_RV410)) {
 452                 DRM_INFO("Loading R400 Microcode\n");
 453                 for (i = 0; i < 256; i++) {
 454                         WREG32(RADEON_CP_ME_RAM_DATAH, R420_cp_microcode[i][1]);
 455                         WREG32(RADEON_CP_ME_RAM_DATAL, R420_cp_microcode[i][0]);
 456                 }
 457         } else if ((rdev->family == CHIP_RS690) ||
 458                    (rdev->family == CHIP_RS740)) {
 459                 DRM_INFO("Loading RS690/RS740 Microcode\n");
 460                 for (i = 0; i < 256; i++) {
 461                         WREG32(RADEON_CP_ME_RAM_DATAH, RS690_cp_microcode[i][1]);
 462                         WREG32(RADEON_CP_ME_RAM_DATAL, RS690_cp_microcode[i][0]);
 463                 }
 464         } else if (rdev->family == CHIP_RS600) {
 465                 DRM_INFO("Loading RS600 Microcode\n");
 466                 for (i = 0; i < 256; i++) {
 467                         WREG32(RADEON_CP_ME_RAM_DATAH, RS600_cp_microcode[i][1]);
 468                         WREG32(RADEON_CP_ME_RAM_DATAL, RS600_cp_microcode[i][0]);
 469                 }
 470         } else if ((rdev->family == CHIP_RV515) ||
 471                    (rdev->family == CHIP_R520) ||
 472                    (rdev->family == CHIP_RV530) ||
 473                    (rdev->family == CHIP_R580) ||
 474                    (rdev->family == CHIP_RV560) ||
 475                    (rdev->family == CHIP_RV570)) {
 476                 DRM_INFO("Loading R500 Microcode\n");
 477                 for (i = 0; i < 256; i++) {
 478                         WREG32(RADEON_CP_ME_RAM_DATAH, R520_cp_microcode[i][1]);
 479                         WREG32(RADEON_CP_ME_RAM_DATAL, R520_cp_microcode[i][0]);
 480                 }
 481         }
 482 }
 483
 484 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
 485 {
 486         unsigned rb_bufsz;
 487         unsigned rb_blksz;
 488         unsigned max_fetch;
 489         unsigned pre_write_timer;
 490         unsigned pre_write_limit;
 491         unsigned indirect2_start;
 492         unsigned indirect1_start;
 493         uint32_t tmp;
 494         int r;
 495
 496         if (r100_debugfs_cp_init(rdev)) {
 497                 DRM_ERROR("Failed to register debugfs file for CP !\n");
 498         }
 499         /* Reset CP */
 500         tmp = RREG32(RADEON_CP_CSQ_STAT);
 501         if ((tmp & (1 << 31))) {
 502                 DRM_INFO("radeon: cp busy (0x%08X) resetting\n", tmp);
 503                 WREG32(RADEON_CP_CSQ_MODE, 0);
 504                 WREG32(RADEON_CP_CSQ_CNTL, 0);
 505                 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
 506                 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
 507                 mdelay(2);
 508                 WREG32(RADEON_RBBM_SOFT_RESET, 0);
 509                 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
 510                 mdelay(2);
 511                 tmp = RREG32(RADEON_CP_CSQ_STAT);
 512                 if ((tmp & (1 << 31))) {
 513                         DRM_INFO("radeon: cp reset failed (0x%08X)\n", tmp);
 514                 }
 515         } else {
 516                 DRM_INFO("radeon: cp idle (0x%08X)\n", tmp);
 517         }
 518         /* Align ring size */
 519         rb_bufsz = drm_order(ring_size / 8);
 520         ring_size = (1 << (rb_bufsz + 1)) * 4;
 521         r100_cp_load_microcode(rdev);
 522         r = radeon_ring_init(rdev, ring_size);
 523         if (r) {
 524                 return r;
 525         }
 526         /* Each time the cp read 1024 bytes (16 dword/quadword) update
 527          * the rptr copy in system ram */
 528         rb_blksz = 9;
 529         /* cp will read 128bytes at a time (4 dwords) */
 530         max_fetch = 1;
 531         rdev->cp.align_mask = 16 - 1;
 532         /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
 533         pre_write_timer = 64;
 534         /* Force CP_RB_WPTR write if written more than one time before the
 535          * delay expire
 536          */
 537         pre_write_limit = 0;
 538         /* Setup the cp cache like this (cache size is 96 dwords) :
 539          *      RING            0  to 15
 540          *      INDIRECT1       16 to 79
 541          *      INDIRECT2       80 to 95
 542          * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
 543          *    indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
 544          *    indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
 545          * Idea being that most of the gpu cmd will be through indirect1 buffer
 546          * so it gets the bigger cache.
 547          */
 548         indirect2_start = 80;
 549         indirect1_start = 16;
 550         /* cp setup */
 551         WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
 552         WREG32(RADEON_CP_RB_CNTL,
 553 #ifdef __BIG_ENDIAN
 554                RADEON_BUF_SWAP_32BIT |
 555 #endif
 556                REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
 557                REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
 558                REG_SET(RADEON_MAX_FETCH, max_fetch) |
 559                RADEON_RB_NO_UPDATE);
 560         /* Set ring address */
 561         DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
 562         WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
 563         /* Force read & write ptr to 0 */
 564         tmp = RREG32(RADEON_CP_RB_CNTL);
 565         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
 566         WREG32(RADEON_CP_RB_RPTR_WR, 0);
 567         WREG32(RADEON_CP_RB_WPTR, 0);
 568         WREG32(RADEON_CP_RB_CNTL, tmp);
 569         udelay(10);
 570         rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
 571         rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
 572         /* Set cp mode to bus mastering & enable cp*/
 573         WREG32(RADEON_CP_CSQ_MODE,
 574                REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
 575                REG_SET(RADEON_INDIRECT1_START, indirect1_start));
 576         WREG32(0x718, 0);
 577         WREG32(0x744, 0x00004D4D);
 578         WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
 579         radeon_ring_start(rdev);
 580         r = radeon_ring_test(rdev);
 581         if (r) {
 582                 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
 583                 return r;
 584         }
 585         rdev->cp.ready = true;
 586         return 0;
 587 }
 588
 589 void r100_cp_fini(struct radeon_device *rdev)
 590 {
 591         /* Disable ring */
 592         rdev->cp.ready = false;
 593         WREG32(RADEON_CP_CSQ_CNTL, 0);
 594         radeon_ring_fini(rdev);
 595         DRM_INFO("radeon: cp finalized\n");
 596 }
 597
 598 void r100_cp_disable(struct radeon_device *rdev)
 599 {
 600         /* Disable ring */
 601         rdev->cp.ready = false;
 602         WREG32(RADEON_CP_CSQ_MODE, 0);
 603         WREG32(RADEON_CP_CSQ_CNTL, 0);
 604         if (r100_gui_wait_for_idle(rdev)) {
 605                 printk(KERN_WARNING "Failed to wait GUI idle while "
 606                        "programming pipes. Bad things might happen.\n");
 607         }
 608 }
 609
 610 int r100_cp_reset(struct radeon_device *rdev)
 611 {
 612         uint32_t tmp;
 613         bool reinit_cp;
 614         int i;
 615
 616         reinit_cp = rdev->cp.ready;
 617         rdev->cp.ready = false;
 618         WREG32(RADEON_CP_CSQ_MODE, 0);
 619         WREG32(RADEON_CP_CSQ_CNTL, 0);
 620         WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
 621         (void)RREG32(RADEON_RBBM_SOFT_RESET);
 622         udelay(200);
 623         WREG32(RADEON_RBBM_SOFT_RESET, 0);
 624         /* Wait to prevent race in RBBM_STATUS */
 625         mdelay(1);
 626         for (i = 0; i < rdev->usec_timeout; i++) {
 627                 tmp = RREG32(RADEON_RBBM_STATUS);
 628                 if (!(tmp & (1 << 16))) {
 629                         DRM_INFO("CP reset succeed (RBBM_STATUS=0x%08X)\n",
 630                                  tmp);
 631                         if (reinit_cp) {
 632                                 return r100_cp_init(rdev, rdev->cp.ring_size);
 633                         }
 634                         return 0;
 635                 }
 636                 DRM_UDELAY(1);
 637         }
 638         tmp = RREG32(RADEON_RBBM_STATUS);
 639         DRM_ERROR("Failed to reset CP (RBBM_STATUS=0x%08X)!\n", tmp);
 640         return -1;
 641 }
 642
 643
 644 /*
 645  * CS functions
 646  */
 647 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
 648                           struct radeon_cs_packet *pkt,
 649                           const unsigned *auth, unsigned n,
 650                           radeon_packet0_check_t check)
 651 {
 652         unsigned reg;
 653         unsigned i, j, m;
 654         unsigned idx;
 655         int r;
 656
 657         idx = pkt->idx + 1;
 658         reg = pkt->reg;
 659         /* Check that register fall into register range
 660          * determined by the number of entry (n) in the
 661          * safe register bitmap.
 662          */
 663         if (pkt->one_reg_wr) {
 664                 if ((reg >> 7) > n) {
 665                         return -EINVAL;
 666                 }
 667         } else {
 668                 if (((reg + (pkt->count << 2)) >> 7) > n) {
 669                         return -EINVAL;
 670                 }
 671         }
 672         for (i = 0; i <= pkt->count; i++, idx++) {
 673                 j = (reg >> 7);
 674                 m = 1 << ((reg >> 2) & 31);
 675                 if (auth[j] & m) {
 676                         r = check(p, pkt, idx, reg);
 677                         if (r) {
 678                                 return r;
 679                         }
 680                 }
 681                 if (pkt->one_reg_wr) {
 682                         if (!(auth[j] & m)) {
 683                                 break;
 684                         }
 685                 } else {
 686                         reg += 4;
 687                 }
 688         }
 689         return 0;
 690 }
 691
 692 void r100_cs_dump_packet(struct radeon_cs_parser *p,
 693                          struct radeon_cs_packet *pkt)
 694 {
 695         struct radeon_cs_chunk *ib_chunk;
 696         volatile uint32_t *ib;
 697         unsigned i;
 698         unsigned idx;
 699
 700         ib = p->ib->ptr;
 701         ib_chunk = &p->chunks[p->chunk_ib_idx];
 702         idx = pkt->idx;
 703         for (i = 0; i <= (pkt->count + 1); i++, idx++) {
 704                 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
 705         }
 706 }
 707
 708 /**
 709  * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
 710  * @parser:     parser structure holding parsing context.
 711  * @pkt:        where to store packet informations
 712  *
 713  * Assume that chunk_ib_index is properly set. Will return -EINVAL
 714  * if packet is bigger than remaining ib size. or if packets is unknown.
 715  **/
 716 int r100_cs_packet_parse(struct radeon_cs_parser *p,
 717                          struct radeon_cs_packet *pkt,
 718                          unsigned idx)
 719 {
 720         struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
 721         uint32_t header = ib_chunk->kdata[idx];
 722
 723         if (idx >= ib_chunk->length_dw) {
 724                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
 725                           idx, ib_chunk->length_dw);
 726                 return -EINVAL;
 727         }
 728         pkt->idx = idx;
 729         pkt->type = CP_PACKET_GET_TYPE(header);
 730         pkt->count = CP_PACKET_GET_COUNT(header);
 731         switch (pkt->type) {
 732         case PACKET_TYPE0:
 733                 pkt->reg = CP_PACKET0_GET_REG(header);
 734                 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
 735                 break;
 736         case PACKET_TYPE3:
 737                 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
 738                 break;
 739         case PACKET_TYPE2:
 740                 pkt->count = -1;
 741                 break;
 742         default:
 743                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
 744                 return -EINVAL;
 745         }
 746         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
 747                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
 748                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
 749                 return -EINVAL;
 750         }
 751         return 0;
 752 }
 753
 754 /**
 755  * r100_cs_packet_next_vline() - parse userspace VLINE packet
 756  * @parser:             parser structure holding parsing context.
 757  *
 758  * Userspace sends a special sequence for VLINE waits.
 759  * PACKET0 - VLINE_START_END + value
 760  * PACKET0 - WAIT_UNTIL +_value
 761  * RELOC (P3) - crtc_id in reloc.
 762  *
 763  * This function parses this and relocates the VLINE START END
 764  * and WAIT UNTIL packets to the correct crtc.
 765  * It also detects a switched off crtc and nulls out the
 766  * wait in that case.
 767  */
 768 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
 769 {
 770         struct radeon_cs_chunk *ib_chunk;
 771         struct drm_mode_object *obj;
 772         struct drm_crtc *crtc;
 773         struct radeon_crtc *radeon_crtc;
 774         struct radeon_cs_packet p3reloc, waitreloc;
 775         int crtc_id;
 776         int r;
 777         uint32_t header, h_idx, reg;
 778
 779         ib_chunk = &p->chunks[p->chunk_ib_idx];
 780
 781         /* parse the wait until */
 782         r = r100_cs_packet_parse(p, &waitreloc, p->idx);
 783         if (r)
 784                 return r;
 785
 786         /* check its a wait until and only 1 count */
 787         if (waitreloc.reg != RADEON_WAIT_UNTIL ||
 788             waitreloc.count != 0) {
 789                 DRM_ERROR("vline wait had illegal wait until segment\n");
 790                 r = -EINVAL;
 791                 return r;
 792         }
 793
 794         if (ib_chunk->kdata[waitreloc.idx + 1] != RADEON_WAIT_CRTC_VLINE) {
 795                 DRM_ERROR("vline wait had illegal wait until\n");
 796                 r = -EINVAL;
 797                 return r;
 798         }
 799
 800         /* jump over the NOP */
 801         r = r100_cs_packet_parse(p, &p3reloc, p->idx);
 802         if (r)
 803                 return r;
 804
 805         h_idx = p->idx - 2;
 806         p->idx += waitreloc.count;
 807         p->idx += p3reloc.count;
 808
 809         header = ib_chunk->kdata[h_idx];
 810         crtc_id = ib_chunk->kdata[h_idx + 5];
 811         reg = ib_chunk->kdata[h_idx] >> 2;
 812         mutex_lock(&p->rdev->ddev->mode_config.mutex);
 813         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
 814         if (!obj) {
 815                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
 816                 r = -EINVAL;
 817                 goto out;
 818         }
 819         crtc = obj_to_crtc(obj);
 820         radeon_crtc = to_radeon_crtc(crtc);
 821         crtc_id = radeon_crtc->crtc_id;
 822
 823         if (!crtc->enabled) {
 824                 /* if the CRTC isn't enabled - we need to nop out the wait until */
 825                 ib_chunk->kdata[h_idx + 2] = PACKET2(0);
 826                 ib_chunk->kdata[h_idx + 3] = PACKET2(0);
 827         } else if (crtc_id == 1) {
 828                 switch (reg) {
 829                 case AVIVO_D1MODE_VLINE_START_END:
 830                         header &= R300_CP_PACKET0_REG_MASK;
 831                         header |= AVIVO_D2MODE_VLINE_START_END >> 2;
 832                         break;
 833                 case RADEON_CRTC_GUI_TRIG_VLINE:
 834                         header &= R300_CP_PACKET0_REG_MASK;
 835                         header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
 836                         break;
 837                 default:
 838                         DRM_ERROR("unknown crtc reloc\n");
 839                         r = -EINVAL;
 840                         goto out;
 841                 }
 842                 ib_chunk->kdata[h_idx] = header;
 843                 ib_chunk->kdata[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
 844         }
 845 out:
 846         mutex_unlock(&p->rdev->ddev->mode_config.mutex);
 847         return r;
 848 }
 849
 850 /**
 851  * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
 852  * @parser:             parser structure holding parsing context.
 853  * @data:               pointer to relocation data
 854  * @offset_start:       starting offset
 855  * @offset_mask:        offset mask (to align start offset on)
 856  * @reloc:              reloc informations
 857  *
 858  * Check next packet is relocation packet3, do bo validation and compute
 859  * GPU offset using the provided start.
 860  **/
 861 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
 862                               struct radeon_cs_reloc **cs_reloc)
 863 {
 864         struct radeon_cs_chunk *ib_chunk;
 865         struct radeon_cs_chunk *relocs_chunk;
 866         struct radeon_cs_packet p3reloc;
 867         unsigned idx;
 868         int r;
 869
 870         if (p->chunk_relocs_idx == -1) {
 871                 DRM_ERROR("No relocation chunk !\n");
 872                 return -EINVAL;
 873         }
 874         *cs_reloc = NULL;
 875         ib_chunk = &p->chunks[p->chunk_ib_idx];
 876         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
 877         r = r100_cs_packet_parse(p, &p3reloc, p->idx);
 878         if (r) {
 879                 return r;
 880         }
 881         p->idx += p3reloc.count + 2;
 882         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
 883                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
 884                           p3reloc.idx);
 885                 r100_cs_dump_packet(p, &p3reloc);
 886                 return -EINVAL;
 887         }
 888         idx = ib_chunk->kdata[p3reloc.idx + 1];
 889         if (idx >= relocs_chunk->length_dw) {
 890                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
 891                           idx, relocs_chunk->length_dw);
 892                 r100_cs_dump_packet(p, &p3reloc);
 893                 return -EINVAL;
 894         }
 895         /* FIXME: we assume reloc size is 4 dwords */
 896         *cs_reloc = p->relocs_ptr[(idx / 4)];
 897         return 0;
 898 }
 899
 900 static int r100_packet0_check(struct radeon_cs_parser *p,
 901                               struct radeon_cs_packet *pkt)
 902 {
 903         struct radeon_cs_chunk *ib_chunk;
 904         struct radeon_cs_reloc *reloc;
 905         volatile uint32_t *ib;
 906         uint32_t tmp;
 907         unsigned reg;
 908         unsigned i;
 909         unsigned idx;
 910         bool onereg;
 911         int r;
 912
 913         ib = p->ib->ptr;
 914         ib_chunk = &p->chunks[p->chunk_ib_idx];
 915         idx = pkt->idx + 1;
 916         reg = pkt->reg;
 917         onereg = false;
 918         if (CP_PACKET0_GET_ONE_REG_WR(ib_chunk->kdata[pkt->idx])) {
 919                 onereg = true;
 920         }
 921         for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
 922                 switch (reg) {
 923                 case RADEON_CRTC_GUI_TRIG_VLINE:
 924                         r = r100_cs_packet_parse_vline(p);
 925                         if (r) {
 926                                 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 927                                                 idx, reg);
 928                                 r100_cs_dump_packet(p, pkt);
 929                                 return r;
 930                         }
 931                         break;
 932                 /* FIXME: only allow PACKET3 blit? easier to check for out of
 933                  * range access */
 934                 case RADEON_DST_PITCH_OFFSET:
 935                 case RADEON_SRC_PITCH_OFFSET:
 936                         r = r100_cs_packet_next_reloc(p, &reloc);
 937                         if (r) {
 938                                 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 939                                           idx, reg);
 940                                 r100_cs_dump_packet(p, pkt);
 941                                 return r;
 942                         }
 943                         tmp = ib_chunk->kdata[idx] & 0x003fffff;
 944                         tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
 945                         ib[idx] = (ib_chunk->kdata[idx] & 0xffc00000) | tmp;
 946                         break;
 947                 case RADEON_RB3D_DEPTHOFFSET:
 948                 case RADEON_RB3D_COLOROFFSET:
 949                 case R300_RB3D_COLOROFFSET0:
 950                 case R300_ZB_DEPTHOFFSET:
 951                 case R200_PP_TXOFFSET_0:
 952                 case R200_PP_TXOFFSET_1:
 953                 case R200_PP_TXOFFSET_2:
 954                 case R200_PP_TXOFFSET_3:
 955                 case R200_PP_TXOFFSET_4:
 956                 case R200_PP_TXOFFSET_5:
 957                 case RADEON_PP_TXOFFSET_0:
 958                 case RADEON_PP_TXOFFSET_1:
 959                 case RADEON_PP_TXOFFSET_2:
 960                 case R300_TX_OFFSET_0:
 961                 case R300_TX_OFFSET_0+4:
 962                 case R300_TX_OFFSET_0+8:
 963                 case R300_TX_OFFSET_0+12:
 964                 case R300_TX_OFFSET_0+16:
 965                 case R300_TX_OFFSET_0+20:
 966                 case R300_TX_OFFSET_0+24:
 967                 case R300_TX_OFFSET_0+28:
 968                 case R300_TX_OFFSET_0+32:
 969                 case R300_TX_OFFSET_0+36:
 970                 case R300_TX_OFFSET_0+40:
 971                 case R300_TX_OFFSET_0+44:
 972                 case R300_TX_OFFSET_0+48:
 973                 case R300_TX_OFFSET_0+52:
 974                 case R300_TX_OFFSET_0+56:
 975                 case R300_TX_OFFSET_0+60:
 976                         r = r100_cs_packet_next_reloc(p, &reloc);
 977                         if (r) {
 978                                 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 979                                           idx, reg);
 980                                 r100_cs_dump_packet(p, pkt);
 981                                 return r;
 982                         }
 983                         ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
 984                         break;
 985                 default:
 986                         /* FIXME: we don't want to allow anyothers packet */
 987                         break;
 988                 }
 989                 if (onereg) {
 990                         /* FIXME: forbid onereg write to register on relocate */
 991                         break;
 992                 }
 993         }
 994         return 0;
 995 }
 996
 997 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
 998                                          struct radeon_cs_packet *pkt,
 999                                          struct radeon_object *robj)
1000 {
1001         struct radeon_cs_chunk *ib_chunk;
1002         unsigned idx;
1003
1004         ib_chunk = &p->chunks[p->chunk_ib_idx];
1005         idx = pkt->idx + 1;
1006         if ((ib_chunk->kdata[idx+2] + 1) > radeon_object_size(robj)) {
1007                 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1008                           "(need %u have %lu) !\n",
1009                           ib_chunk->kdata[idx+2] + 1,
1010                           radeon_object_size(robj));
1011                 return -EINVAL;
1012         }
1013         return 0;
1014 }
1015
1016 static int r100_packet3_check(struct radeon_cs_parser *p,
1017                               struct radeon_cs_packet *pkt)
1018 {
1019         struct radeon_cs_chunk *ib_chunk;
1020         struct radeon_cs_reloc *reloc;
1021         unsigned idx;
1022         unsigned i, c;
1023         volatile uint32_t *ib;
1024         int r;
1025
1026         ib = p->ib->ptr;
1027         ib_chunk = &p->chunks[p->chunk_ib_idx];
1028         idx = pkt->idx + 1;
1029         switch (pkt->opcode) {
1030         case PACKET3_3D_LOAD_VBPNTR:
1031                 c = ib_chunk->kdata[idx++];
1032                 for (i = 0; i < (c - 1); i += 2, idx += 3) {
1033                         r = r100_cs_packet_next_reloc(p, &reloc);
1034                         if (r) {
1035                                 DRM_ERROR("No reloc for packet3 %d\n",
1036                                           pkt->opcode);
1037                                 r100_cs_dump_packet(p, pkt);
1038                                 return r;
1039                         }
1040                         ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
1041                         r = r100_cs_packet_next_reloc(p, &reloc);
1042                         if (r) {
1043                                 DRM_ERROR("No reloc for packet3 %d\n",
1044                                           pkt->opcode);
1045                                 r100_cs_dump_packet(p, pkt);
1046                                 return r;
1047                         }
1048                         ib[idx+2] = ib_chunk->kdata[idx+2] + ((u32)reloc->lobj.gpu_offset);
1049                 }
1050                 if (c & 1) {
1051                         r = r100_cs_packet_next_reloc(p, &reloc);
1052                         if (r) {
1053                                 DRM_ERROR("No reloc for packet3 %d\n",
1054                                           pkt->opcode);
1055                                 r100_cs_dump_packet(p, pkt);
1056                                 return r;
1057                         }
1058                         ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
1059                 }
1060                 break;
1061         case PACKET3_INDX_BUFFER:
1062                 r = r100_cs_packet_next_reloc(p, &reloc);
1063                 if (r) {
1064                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1065                         r100_cs_dump_packet(p, pkt);
1066                         return r;
1067                 }
1068                 ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
1069                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1070                 if (r) {
1071                         return r;
1072                 }
1073                 break;
1074         case 0x23:
1075                 /* FIXME: cleanup */
1076                 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1077                 r = r100_cs_packet_next_reloc(p, &reloc);
1078                 if (r) {
1079                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1080                         r100_cs_dump_packet(p, pkt);
1081                         return r;
1082                 }
1083                 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1084                 break;
1085         case PACKET3_3D_DRAW_IMMD:
1086                 /* triggers drawing using in-packet vertex data */
1087         case PACKET3_3D_DRAW_IMMD_2:
1088                 /* triggers drawing using in-packet vertex data */
1089         case PACKET3_3D_DRAW_VBUF_2:
1090                 /* triggers drawing of vertex buffers setup elsewhere */
1091         case PACKET3_3D_DRAW_INDX_2:
1092                 /* triggers drawing using indices to vertex buffer */
1093         case PACKET3_3D_DRAW_VBUF:
1094                 /* triggers drawing of vertex buffers setup elsewhere */
1095         case PACKET3_3D_DRAW_INDX:
1096                 /* triggers drawing using indices to vertex buffer */
1097         case PACKET3_NOP:
1098                 break;
1099         default:
1100                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1101                 return -EINVAL;
1102         }
1103         return 0;
1104 }
1105
1106 int r100_cs_parse(struct radeon_cs_parser *p)
1107 {
1108         struct radeon_cs_packet pkt;
1109         int r;
1110
1111         do {
1112                 r = r100_cs_packet_parse(p, &pkt, p->idx);
1113                 if (r) {
1114                         return r;
1115                 }
1116                 p->idx += pkt.count + 2;
1117                 switch (pkt.type) {
1118                         case PACKET_TYPE0:
1119                                 r = r100_packet0_check(p, &pkt);
1120                                 break;
1121                         case PACKET_TYPE2:
1122                                 break;
1123                         case PACKET_TYPE3:
1124                                 r = r100_packet3_check(p, &pkt);
1125                                 break;
1126                         default:
1127                                 DRM_ERROR("Unknown packet type %d !\n",
1128                                           pkt.type);
1129                                 return -EINVAL;
1130                 }
1131                 if (r) {
1132                         return r;
1133                 }
1134         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1135         return 0;
1136 }
1137
1138
1139 /*
1140  * Global GPU functions
1141  */
1142 void r100_errata(struct radeon_device *rdev)
1143 {
1144         rdev->pll_errata = 0;
1145
1146         if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1147                 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1148         }
1149
1150         if (rdev->family == CHIP_RV100 ||
1151             rdev->family == CHIP_RS100 ||
1152             rdev->family == CHIP_RS200) {
1153                 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1154         }
1155 }
1156
1157 /* Wait for vertical sync on primary CRTC */
1158 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1159 {
1160         uint32_t crtc_gen_cntl, tmp;
1161         int i;
1162
1163         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1164         if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1165             !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1166                 return;
1167         }
1168         /* Clear the CRTC_VBLANK_SAVE bit */
1169         WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1170         for (i = 0; i < rdev->usec_timeout; i++) {
1171                 tmp = RREG32(RADEON_CRTC_STATUS);
1172                 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1173                         return;
1174                 }
1175                 DRM_UDELAY(1);
1176         }
1177 }
1178
1179 /* Wait for vertical sync on secondary CRTC */
1180 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1181 {
1182         uint32_t crtc2_gen_cntl, tmp;
1183         int i;
1184
1185         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1186         if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1187             !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1188                 return;
1189
1190         /* Clear the CRTC_VBLANK_SAVE bit */
1191         WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1192         for (i = 0; i < rdev->usec_timeout; i++) {
1193                 tmp = RREG32(RADEON_CRTC2_STATUS);
1194                 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1195                         return;
1196                 }
1197                 DRM_UDELAY(1);
1198         }
1199 }
1200
1201 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1202 {
1203         unsigned i;
1204         uint32_t tmp;
1205
1206         for (i = 0; i < rdev->usec_timeout; i++) {
1207                 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1208                 if (tmp >= n) {
1209                         return 0;
1210                 }
1211                 DRM_UDELAY(1);
1212         }
1213         return -1;
1214 }
1215
1216 int r100_gui_wait_for_idle(struct radeon_device *rdev)
1217 {
1218         unsigned i;
1219         uint32_t tmp;
1220
1221         if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1222                 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1223                        " Bad things might happen.\n");
1224         }
1225         for (i = 0; i < rdev->usec_timeout; i++) {
1226                 tmp = RREG32(RADEON_RBBM_STATUS);
1227                 if (!(tmp & (1 << 31))) {
1228                         return 0;
1229                 }
1230                 DRM_UDELAY(1);
1231         }
1232         return -1;
1233 }
1234
1235 int r100_mc_wait_for_idle(struct radeon_device *rdev)
1236 {
1237         unsigned i;
1238         uint32_t tmp;
1239
1240         for (i = 0; i < rdev->usec_timeout; i++) {
1241                 /* read MC_STATUS */
1242                 tmp = RREG32(0x0150);
1243                 if (tmp & (1 << 2)) {
1244                         return 0;
1245                 }
1246                 DRM_UDELAY(1);
1247         }
1248         return -1;
1249 }
1250
1251 void r100_gpu_init(struct radeon_device *rdev)
1252 {
1253         /* TODO: anythings to do here ? pipes ? */
1254         r100_hdp_reset(rdev);
1255 }
1256
1257 void r100_hdp_reset(struct radeon_device *rdev)
1258 {
1259         uint32_t tmp;
1260
1261         tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
1262         tmp |= (7 << 28);
1263         WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
1264         (void)RREG32(RADEON_HOST_PATH_CNTL);
1265         udelay(200);
1266         WREG32(RADEON_RBBM_SOFT_RESET, 0);
1267         WREG32(RADEON_HOST_PATH_CNTL, tmp);
1268         (void)RREG32(RADEON_HOST_PATH_CNTL);
1269 }
1270
1271 int r100_rb2d_reset(struct radeon_device *rdev)
1272 {
1273         uint32_t tmp;
1274         int i;
1275
1276         WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_E2);
1277         (void)RREG32(RADEON_RBBM_SOFT_RESET);
1278         udelay(200);
1279         WREG32(RADEON_RBBM_SOFT_RESET, 0);
1280         /* Wait to prevent race in RBBM_STATUS */
1281         mdelay(1);
1282         for (i = 0; i < rdev->usec_timeout; i++) {
1283                 tmp = RREG32(RADEON_RBBM_STATUS);
1284                 if (!(tmp & (1 << 26))) {
1285                         DRM_INFO("RB2D reset succeed (RBBM_STATUS=0x%08X)\n",
1286                                  tmp);
1287                         return 0;
1288                 }
1289                 DRM_UDELAY(1);
1290         }
1291         tmp = RREG32(RADEON_RBBM_STATUS);
1292         DRM_ERROR("Failed to reset RB2D (RBBM_STATUS=0x%08X)!\n", tmp);
1293         return -1;
1294 }
1295
1296 int r100_gpu_reset(struct radeon_device *rdev)
1297 {
1298         uint32_t status;
1299
1300         /* reset order likely matter */
1301         status = RREG32(RADEON_RBBM_STATUS);
1302         /* reset HDP */
1303         r100_hdp_reset(rdev);
1304         /* reset rb2d */
1305         if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
1306                 r100_rb2d_reset(rdev);
1307         }
1308         /* TODO: reset 3D engine */
1309         /* reset CP */
1310         status = RREG32(RADEON_RBBM_STATUS);
1311         if (status & (1 << 16)) {
1312                 r100_cp_reset(rdev);
1313         }
1314         /* Check if GPU is idle */
1315         status = RREG32(RADEON_RBBM_STATUS);
1316         if (status & (1 << 31)) {
1317                 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
1318                 return -1;
1319         }
1320         DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
1321         return 0;
1322 }
1323
1324
1325 /*
1326  * VRAM info
1327  */
1328 static void r100_vram_get_type(struct radeon_device *rdev)
1329 {
1330         uint32_t tmp;
1331
1332         rdev->mc.vram_is_ddr = false;
1333         if (rdev->flags & RADEON_IS_IGP)
1334                 rdev->mc.vram_is_ddr = true;
1335         else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
1336                 rdev->mc.vram_is_ddr = true;
1337         if ((rdev->family == CHIP_RV100) ||
1338             (rdev->family == CHIP_RS100) ||
1339             (rdev->family == CHIP_RS200)) {
1340                 tmp = RREG32(RADEON_MEM_CNTL);
1341                 if (tmp & RV100_HALF_MODE) {
1342                         rdev->mc.vram_width = 32;
1343                 } else {
1344                         rdev->mc.vram_width = 64;
1345                 }
1346                 if (rdev->flags & RADEON_SINGLE_CRTC) {
1347                         rdev->mc.vram_width /= 4;
1348                         rdev->mc.vram_is_ddr = true;
1349                 }
1350         } else if (rdev->family <= CHIP_RV280) {
1351                 tmp = RREG32(RADEON_MEM_CNTL);
1352                 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
1353                         rdev->mc.vram_width = 128;
1354                 } else {
1355                         rdev->mc.vram_width = 64;
1356                 }
1357         } else {
1358                 /* newer IGPs */
1359                 rdev->mc.vram_width = 128;
1360         }
1361 }
1362
1363 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
1364 {
1365         u32 aper_size;
1366         u8 byte;
1367
1368         aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1369
1370         /* Set HDP_APER_CNTL only on cards that are known not to be broken,
1371          * that is has the 2nd generation multifunction PCI interface
1372          */
1373         if (rdev->family == CHIP_RV280 ||
1374             rdev->family >= CHIP_RV350) {
1375                 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
1376                        ~RADEON_HDP_APER_CNTL);
1377                 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
1378                 return aper_size * 2;
1379         }
1380
1381         /* Older cards have all sorts of funny issues to deal with. First
1382          * check if it's a multifunction card by reading the PCI config
1383          * header type... Limit those to one aperture size
1384          */
1385         pci_read_config_byte(rdev->pdev, 0xe, &byte);
1386         if (byte & 0x80) {
1387                 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
1388                 DRM_INFO("Limiting VRAM to one aperture\n");
1389                 return aper_size;
1390         }
1391
1392         /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
1393          * have set it up. We don't write this as it's broken on some ASICs but
1394          * we expect the BIOS to have done the right thing (might be too optimistic...)
1395          */
1396         if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
1397                 return aper_size * 2;
1398         return aper_size;
1399 }
1400
1401 void r100_vram_init_sizes(struct radeon_device *rdev)
1402 {
1403         u64 config_aper_size;
1404         u32 accessible;
1405
1406         config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1407
1408         if (rdev->flags & RADEON_IS_IGP) {
1409                 uint32_t tom;
1410                 /* read NB_TOM to get the amount of ram stolen for the GPU */
1411                 tom = RREG32(RADEON_NB_TOM);
1412                 rdev->mc.vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
1413                 /* for IGPs we need to keep VRAM where it was put by the BIOS */
1414                 rdev->mc.vram_location = (tom & 0xffff) << 16;
1415                 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size);
1416         } else {
1417                 rdev->mc.vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
1418                 /* Some production boards of m6 will report 0
1419                  * if it's 8 MB
1420                  */
1421                 if (rdev->mc.vram_size == 0) {
1422                         rdev->mc.vram_size = 8192 * 1024;
1423                         WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size);
1424                 }
1425                 /* let driver place VRAM */
1426                 rdev->mc.vram_location = 0xFFFFFFFFUL;
1427                  /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
1428                   * Novell bug 204882 + along with lots of ubuntu ones */
1429                 if (config_aper_size > rdev->mc.vram_size)
1430                         rdev->mc.vram_size = config_aper_size;
1431         }
1432
1433         /* work out accessible VRAM */
1434         accessible = r100_get_accessible_vram(rdev);
1435
1436         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1437         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
1438
1439         if (accessible > rdev->mc.aper_size)
1440                 accessible = rdev->mc.aper_size;
1441
1442         if (rdev->mc.vram_size > rdev->mc.aper_size)
1443                 rdev->mc.vram_size = rdev->mc.aper_size;
1444 }
1445
1446 void r100_vram_info(struct radeon_device *rdev)
1447 {
1448         r100_vram_get_type(rdev);
1449
1450         r100_vram_init_sizes(rdev);
1451 }
1452
1453
1454 /*
1455  * Indirect registers accessor
1456  */
1457 void r100_pll_errata_after_index(struct radeon_device *rdev)
1458 {
1459         if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) {
1460                 return;
1461         }
1462         (void)RREG32(RADEON_CLOCK_CNTL_DATA);
1463         (void)RREG32(RADEON_CRTC_GEN_CNTL);
1464 }
1465
1466 static void r100_pll_errata_after_data(struct radeon_device *rdev)
1467 {
1468         /* This workarounds is necessary on RV100, RS100 and RS200 chips
1469          * or the chip could hang on a subsequent access
1470          */
1471         if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
1472                 udelay(5000);
1473         }
1474
1475         /* This function is required to workaround a hardware bug in some (all?)
1476          * revisions of the R300.  This workaround should be called after every
1477          * CLOCK_CNTL_INDEX register access.  If not, register reads afterward
1478          * may not be correct.
1479          */
1480         if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
1481                 uint32_t save, tmp;
1482
1483                 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
1484                 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
1485                 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
1486                 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
1487                 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
1488         }
1489 }
1490
1491 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
1492 {
1493         uint32_t data;
1494
1495         WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
1496         r100_pll_errata_after_index(rdev);
1497         data = RREG32(RADEON_CLOCK_CNTL_DATA);
1498         r100_pll_errata_after_data(rdev);
1499         return data;
1500 }
1501
1502 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1503 {
1504         WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
1505         r100_pll_errata_after_index(rdev);
1506         WREG32(RADEON_CLOCK_CNTL_DATA, v);
1507         r100_pll_errata_after_data(rdev);
1508 }
1509
1510 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
1511 {
1512         if (reg < 0x10000)
1513                 return readl(((void __iomem *)rdev->rmmio) + reg);
1514         else {
1515                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1516                 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1517         }
1518 }
1519
1520 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1521 {
1522         if (reg < 0x10000)
1523                 writel(v, ((void __iomem *)rdev->rmmio) + reg);
1524         else {
1525                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1526                 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1527         }
1528 }
1529
1530 int r100_init(struct radeon_device *rdev)
1531 {
1532         return 0;
1533 }
1534
1535 /*
1536  * Debugfs info
1537  */
1538 #if defined(CONFIG_DEBUG_FS)
1539 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
1540 {
1541         struct drm_info_node *node = (struct drm_info_node *) m->private;
1542         struct drm_device *dev = node->minor->dev;
1543         struct radeon_device *rdev = dev->dev_private;
1544         uint32_t reg, value;
1545         unsigned i;
1546
1547         seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
1548         seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
1549         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
1550         for (i = 0; i < 64; i++) {
1551                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
1552                 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
1553                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
1554                 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
1555                 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
1556         }
1557         return 0;
1558 }
1559
1560 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
1561 {
1562         struct drm_info_node *node = (struct drm_info_node *) m->private;
1563         struct drm_device *dev = node->minor->dev;
1564         struct radeon_device *rdev = dev->dev_private;
1565         uint32_t rdp, wdp;
1566         unsigned count, i, j;
1567
1568         radeon_ring_free_size(rdev);
1569         rdp = RREG32(RADEON_CP_RB_RPTR);
1570         wdp = RREG32(RADEON_CP_RB_WPTR);
1571         count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
1572         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
1573         seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
1574         seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
1575         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
1576         seq_printf(m, "%u dwords in ring\n", count);
1577         for (j = 0; j <= count; j++) {
1578                 i = (rdp + j) & rdev->cp.ptr_mask;
1579                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
1580         }
1581         return 0;
1582 }
1583
1584
1585 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
1586 {
1587         struct drm_info_node *node = (struct drm_info_node *) m->private;
1588         struct drm_device *dev = node->minor->dev;
1589         struct radeon_device *rdev = dev->dev_private;
1590         uint32_t csq_stat, csq2_stat, tmp;
1591         unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
1592         unsigned i;
1593
1594         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
1595         seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
1596         csq_stat = RREG32(RADEON_CP_CSQ_STAT);
1597         csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
1598         r_rptr = (csq_stat >> 0) & 0x3ff;
1599         r_wptr = (csq_stat >> 10) & 0x3ff;
1600         ib1_rptr = (csq_stat >> 20) & 0x3ff;
1601         ib1_wptr = (csq2_stat >> 0) & 0x3ff;
1602         ib2_rptr = (csq2_stat >> 10) & 0x3ff;
1603         ib2_wptr = (csq2_stat >> 20) & 0x3ff;
1604         seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
1605         seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
1606         seq_printf(m, "Ring rptr %u\n", r_rptr);
1607         seq_printf(m, "Ring wptr %u\n", r_wptr);
1608         seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
1609         seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
1610         seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
1611         seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
1612         /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
1613          * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
1614         seq_printf(m, "Ring fifo:\n");
1615         for (i = 0; i < 256; i++) {
1616                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
1617                 tmp = RREG32(RADEON_CP_CSQ_DATA);
1618                 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
1619         }
1620         seq_printf(m, "Indirect1 fifo:\n");
1621         for (i = 256; i <= 512; i++) {
1622                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
1623                 tmp = RREG32(RADEON_CP_CSQ_DATA);
1624                 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
1625         }
1626         seq_printf(m, "Indirect2 fifo:\n");
1627         for (i = 640; i < ib1_wptr; i++) {
1628                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
1629                 tmp = RREG32(RADEON_CP_CSQ_DATA);
1630                 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
1631         }
1632         return 0;
1633 }
1634
1635 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
1636 {
1637         struct drm_info_node *node = (struct drm_info_node *) m->private;
1638         struct drm_device *dev = node->minor->dev;
1639         struct radeon_device *rdev = dev->dev_private;
1640         uint32_t tmp;
1641
1642         tmp = RREG32(RADEON_CONFIG_MEMSIZE);
1643         seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
1644         tmp = RREG32(RADEON_MC_FB_LOCATION);
1645         seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
1646         tmp = RREG32(RADEON_BUS_CNTL);
1647         seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
1648         tmp = RREG32(RADEON_MC_AGP_LOCATION);
1649         seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
1650         tmp = RREG32(RADEON_AGP_BASE);
1651         seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
1652         tmp = RREG32(RADEON_HOST_PATH_CNTL);
1653         seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
1654         tmp = RREG32(0x01D0);
1655         seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
1656         tmp = RREG32(RADEON_AIC_LO_ADDR);
1657         seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
1658         tmp = RREG32(RADEON_AIC_HI_ADDR);
1659         seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
1660         tmp = RREG32(0x01E4);
1661         seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
1662         return 0;
1663 }
1664
1665 static struct drm_info_list r100_debugfs_rbbm_list[] = {
1666         {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
1667 };
1668
1669 static struct drm_info_list r100_debugfs_cp_list[] = {
1670         {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
1671         {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
1672 };
1673
1674 static struct drm_info_list r100_debugfs_mc_info_list[] = {
1675         {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
1676 };
1677 #endif
1678
1679 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
1680 {
1681 #if defined(CONFIG_DEBUG_FS)
1682         return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
1683 #else
1684         return 0;
1685 #endif
1686 }
1687
1688 int r100_debugfs_cp_init(struct radeon_device *rdev)
1689 {
1690 #if defined(CONFIG_DEBUG_FS)
1691         return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
1692 #else
1693         return 0;
1694 #endif
1695 }
1696
1697 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
1698 {
1699 #if defined(CONFIG_DEBUG_FS)
1700         return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
1701 #else
1702         return 0;
1703 #endif
1704 }