SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/r100.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include <linux/slab.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "radeon_drm.h"
  33 #include "radeon_reg.h"
  34 #include "radeon.h"
  35 #include "radeon_asic.h"
  36 #include "r100d.h"
  37 #include "rs100d.h"
  38 #include "rv200d.h"
  39 #include "rv250d.h"
  40 #include "atom.h"
  41
  42 #include <linux/firmware.h>
  43 #include <linux/platform_device.h>
  44
  45 #include "r100_reg_safe.h"
  46 #include "rn50_reg_safe.h"
  47
  48 /* Firmware Names */
  49 #define FIRMWARE_R100           "radeon/R100_cp.bin"
  50 #define FIRMWARE_R200           "radeon/R200_cp.bin"
  51 #define FIRMWARE_R300           "radeon/R300_cp.bin"
  52 #define FIRMWARE_R420           "radeon/R420_cp.bin"
  53 #define FIRMWARE_RS690          "radeon/RS690_cp.bin"
  54 #define FIRMWARE_RS600          "radeon/RS600_cp.bin"
  55 #define FIRMWARE_R520           "radeon/R520_cp.bin"
  56
  57 MODULE_FIRMWARE(FIRMWARE_R100);
  58 MODULE_FIRMWARE(FIRMWARE_R200);
  59 MODULE_FIRMWARE(FIRMWARE_R300);
  60 MODULE_FIRMWARE(FIRMWARE_R420);
  61 MODULE_FIRMWARE(FIRMWARE_RS690);
  62 MODULE_FIRMWARE(FIRMWARE_RS600);
  63 MODULE_FIRMWARE(FIRMWARE_R520);
  64
  65 #include "r100_track.h"
  66
  67 /* This files gather functions specifics to:
  68  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
  69  */
  70
  71 void r100_get_power_state(struct radeon_device *rdev,
  72                           enum radeon_pm_action action)
  73 {
  74         int i;
  75         rdev->pm.can_upclock = true;
  76         rdev->pm.can_downclock = true;
  77
  78         switch (action) {
  79         case PM_ACTION_MINIMUM:
  80                 rdev->pm.requested_power_state_index = 0;
  81                 rdev->pm.can_downclock = false;
  82                 break;
  83         case PM_ACTION_DOWNCLOCK:
  84                 if (rdev->pm.current_power_state_index == 0) {
  85                         rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
  86                         rdev->pm.can_downclock = false;
  87                 } else {
  88                         if (rdev->pm.active_crtc_count > 1) {
  89                                 for (i = 0; i < rdev->pm.num_power_states; i++) {
  90                                         if (rdev->pm.power_state[i].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)
  91                                                 continue;
  92                                         else if (i >= rdev->pm.current_power_state_index) {
  93                                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
  94                                                 break;
  95                                         } else {
  96                                                 rdev->pm.requested_power_state_index = i;
  97                                                 break;
  98                                         }
  99                                 }
 100                         } else
 101                                 rdev->pm.requested_power_state_index =
 102                                         rdev->pm.current_power_state_index - 1;
 103                 }
 104                 break;
 105         case PM_ACTION_UPCLOCK:
 106                 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
 107                         rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 108                         rdev->pm.can_upclock = false;
 109                 } else {
 110                         if (rdev->pm.active_crtc_count > 1) {
 111                                 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
 112                                         if (rdev->pm.power_state[i].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)
 113                                                 continue;
 114                                         else if (i <= rdev->pm.current_power_state_index) {
 115                                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 116                                                 break;
 117                                         } else {
 118                                                 rdev->pm.requested_power_state_index = i;
 119                                                 break;
 120                                         }
 121                                 }
 122                         } else
 123                                 rdev->pm.requested_power_state_index =
 124                                         rdev->pm.current_power_state_index + 1;
 125                 }
 126                 break;
 127         case PM_ACTION_DEFAULT:
 128                 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 129                 rdev->pm.can_upclock = false;
 130                 break;
 131         case PM_ACTION_NONE:
 132         default:
 133                 DRM_ERROR("Requested mode for not defined action\n");
 134                 return;
 135         }
 136         /* only one clock mode per power state */
 137         rdev->pm.requested_clock_mode_index = 0;
 138
 139         DRM_INFO("Requested: e: %d m: %d p: %d\n",
 140                  rdev->pm.power_state[rdev->pm.requested_power_state_index].
 141                  clock_info[rdev->pm.requested_clock_mode_index].sclk,
 142                  rdev->pm.power_state[rdev->pm.requested_power_state_index].
 143                  clock_info[rdev->pm.requested_clock_mode_index].mclk,
 144                  rdev->pm.power_state[rdev->pm.requested_power_state_index].
 145                  pcie_lanes);
 146 }
 147
 148 void r100_set_power_state(struct radeon_device *rdev, bool static_switch)
 149 {
 150         u32 sclk, mclk;
 151
 152         if (rdev->pm.current_power_state_index == rdev->pm.requested_power_state_index)
 153                 return;
 154
 155         if (radeon_gui_idle(rdev)) {
 156
 157                 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 158                         clock_info[rdev->pm.requested_clock_mode_index].sclk;
 159                 if (sclk > rdev->clock.default_sclk)
 160                         sclk = rdev->clock.default_sclk;
 161
 162                 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 163                         clock_info[rdev->pm.requested_clock_mode_index].mclk;
 164                 if (mclk > rdev->clock.default_mclk)
 165                         mclk = rdev->clock.default_mclk;
 166                 /* don't change the mclk with multiple crtcs */
 167                 if (rdev->pm.active_crtc_count > 1)
 168                         mclk = rdev->clock.default_mclk;
 169
 170                 /* voltage, pcie lanes, etc.*/
 171                 radeon_pm_misc(rdev);
 172
 173                 if (static_switch) {
 174                         radeon_pm_prepare(rdev);
 175                         /* set engine clock */
 176                         if (sclk != rdev->pm.current_sclk) {
 177                                 radeon_set_engine_clock(rdev, sclk);
 178                                 rdev->pm.current_sclk = sclk;
 179                                 DRM_INFO("Setting: e: %d\n", sclk);
 180                         }
 181 #if 0
 182                         /* set memory clock */
 183                         if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
 184                                 radeon_set_memory_clock(rdev, mclk);
 185                                 rdev->pm.current_mclk = mclk;
 186                                 DRM_INFO("Setting: m: %d\n", mclk);
 187                         }
 188 #endif
 189                         radeon_pm_finish(rdev);
 190                 } else {
 191                         /* set engine clock */
 192                         if (sclk != rdev->pm.current_sclk) {
 193                                 radeon_sync_with_vblank(rdev);
 194                                 radeon_pm_debug_check_in_vbl(rdev, false);
 195                                 radeon_set_engine_clock(rdev, sclk);
 196                                 radeon_pm_debug_check_in_vbl(rdev, true);
 197                                 rdev->pm.current_sclk = sclk;
 198                                 DRM_INFO("Setting: e: %d\n", sclk);
 199                         }
 200
 201 #if 0
 202                         /* set memory clock */
 203                         if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
 204                                 radeon_sync_with_vblank(rdev);
 205                                 radeon_pm_debug_check_in_vbl(rdev, false);
 206                                 radeon_pm_prepare(rdev);
 207                                 radeon_set_memory_clock(rdev, mclk);
 208                                 radeon_pm_finish(rdev);
 209                                 radeon_pm_debug_check_in_vbl(rdev, true);
 210                                 rdev->pm.current_mclk = mclk;
 211                                 DRM_INFO("Setting: m: %d\n", mclk);
 212                         }
 213 #endif
 214                 }
 215
 216                 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
 217                 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
 218         } else
 219                 DRM_INFO("GUI not idle!!!\n");
 220 }
 221
 222 void r100_pm_misc(struct radeon_device *rdev)
 223 {
 224 #if 0
 225         int requested_index = rdev->pm.requested_power_state_index;
 226         struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
 227         struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
 228         u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
 229
 230         if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
 231                 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
 232                         tmp = RREG32(voltage->gpio.reg);
 233                         if (voltage->active_high)
 234                                 tmp |= voltage->gpio.mask;
 235                         else
 236                                 tmp &= ~(voltage->gpio.mask);
 237                         WREG32(voltage->gpio.reg, tmp);
 238                         if (voltage->delay)
 239                                 udelay(voltage->delay);
 240                 } else {
 241                         tmp = RREG32(voltage->gpio.reg);
 242                         if (voltage->active_high)
 243                                 tmp &= ~voltage->gpio.mask;
 244                         else
 245                                 tmp |= voltage->gpio.mask;
 246                         WREG32(voltage->gpio.reg, tmp);
 247                         if (voltage->delay)
 248                                 udelay(voltage->delay);
 249                 }
 250         }
 251
 252         sclk_cntl = RREG32_PLL(SCLK_CNTL);
 253         sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
 254         sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
 255         sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
 256         sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
 257         if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
 258                 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
 259                 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
 260                         sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
 261                 else
 262                         sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
 263                 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
 264                         sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
 265                 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
 266                         sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
 267         } else
 268                 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
 269
 270         if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
 271                 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
 272                 if (voltage->delay) {
 273                         sclk_more_cntl |= VOLTAGE_DROP_SYNC;
 274                         switch (voltage->delay) {
 275                         case 33:
 276                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
 277                                 break;
 278                         case 66:
 279                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
 280                                 break;
 281                         case 99:
 282                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
 283                                 break;
 284                         case 132:
 285                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
 286                                 break;
 287                         }
 288                 } else
 289                         sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
 290         } else
 291                 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
 292
 293         if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
 294                 sclk_cntl &= ~FORCE_HDP;
 295         else
 296                 sclk_cntl |= FORCE_HDP;
 297
 298         WREG32_PLL(SCLK_CNTL, sclk_cntl);
 299         WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
 300         WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
 301
 302         /* set pcie lanes */
 303         if ((rdev->flags & RADEON_IS_PCIE) &&
 304             !(rdev->flags & RADEON_IS_IGP) &&
 305             rdev->asic->set_pcie_lanes &&
 306             (ps->pcie_lanes !=
 307              rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
 308                 radeon_set_pcie_lanes(rdev,
 309                                       ps->pcie_lanes);
 310                 DRM_INFO("Setting: p: %d\n", ps->pcie_lanes);
 311         }
 312 #endif
 313 }
 314
 315 void r100_pm_prepare(struct radeon_device *rdev)
 316 {
 317         struct drm_device *ddev = rdev->ddev;
 318         struct drm_crtc *crtc;
 319         struct radeon_crtc *radeon_crtc;
 320         u32 tmp;
 321
 322         /* disable any active CRTCs */
 323         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 324                 radeon_crtc = to_radeon_crtc(crtc);
 325                 if (radeon_crtc->enabled) {
 326                         if (radeon_crtc->crtc_id) {
 327                                 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
 328                                 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
 329                                 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
 330                         } else {
 331                                 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
 332                                 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
 333                                 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
 334                         }
 335                 }
 336         }
 337 }
 338
 339 void r100_pm_finish(struct radeon_device *rdev)
 340 {
 341         struct drm_device *ddev = rdev->ddev;
 342         struct drm_crtc *crtc;
 343         struct radeon_crtc *radeon_crtc;
 344         u32 tmp;
 345
 346         /* enable any active CRTCs */
 347         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 348                 radeon_crtc = to_radeon_crtc(crtc);
 349                 if (radeon_crtc->enabled) {
 350                         if (radeon_crtc->crtc_id) {
 351                                 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
 352                                 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
 353                                 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
 354                         } else {
 355                                 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
 356                                 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
 357                                 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
 358                         }
 359                 }
 360         }
 361 }
 362
 363 bool r100_gui_idle(struct radeon_device *rdev)
 364 {
 365         if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
 366                 return false;
 367         else
 368                 return true;
 369 }
 370
 371 /* hpd for digital panel detect/disconnect */
 372 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 373 {
 374         bool connected = false;
 375
 376         switch (hpd) {
 377         case RADEON_HPD_1:
 378                 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
 379                         connected = true;
 380                 break;
 381         case RADEON_HPD_2:
 382                 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
 383                         connected = true;
 384                 break;
 385         default:
 386                 break;
 387         }
 388         return connected;
 389 }
 390
 391 void r100_hpd_set_polarity(struct radeon_device *rdev,
 392                            enum radeon_hpd_id hpd)
 393 {
 394         u32 tmp;
 395         bool connected = r100_hpd_sense(rdev, hpd);
 396
 397         switch (hpd) {
 398         case RADEON_HPD_1:
 399                 tmp = RREG32(RADEON_FP_GEN_CNTL);
 400                 if (connected)
 401                         tmp &= ~RADEON_FP_DETECT_INT_POL;
 402                 else
 403                         tmp |= RADEON_FP_DETECT_INT_POL;
 404                 WREG32(RADEON_FP_GEN_CNTL, tmp);
 405                 break;
 406         case RADEON_HPD_2:
 407                 tmp = RREG32(RADEON_FP2_GEN_CNTL);
 408                 if (connected)
 409                         tmp &= ~RADEON_FP2_DETECT_INT_POL;
 410                 else
 411                         tmp |= RADEON_FP2_DETECT_INT_POL;
 412                 WREG32(RADEON_FP2_GEN_CNTL, tmp);
 413                 break;
 414         default:
 415                 break;
 416         }
 417 }
 418
 419 void r100_hpd_init(struct radeon_device *rdev)
 420 {
 421         struct drm_device *dev = rdev->ddev;
 422         struct drm_connector *connector;
 423
 424         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 425                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 426                 switch (radeon_connector->hpd.hpd) {
 427                 case RADEON_HPD_1:
 428                         rdev->irq.hpd[0] = true;
 429                         break;
 430                 case RADEON_HPD_2:
 431                         rdev->irq.hpd[1] = true;
 432                         break;
 433                 default:
 434                         break;
 435                 }
 436         }
 437         if (rdev->irq.installed)
 438                 r100_irq_set(rdev);
 439 }
 440
 441 void r100_hpd_fini(struct radeon_device *rdev)
 442 {
 443         struct drm_device *dev = rdev->ddev;
 444         struct drm_connector *connector;
 445
 446         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 447                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 448                 switch (radeon_connector->hpd.hpd) {
 449                 case RADEON_HPD_1:
 450                         rdev->irq.hpd[0] = false;
 451                         break;
 452                 case RADEON_HPD_2:
 453                         rdev->irq.hpd[1] = false;
 454                         break;
 455                 default:
 456                         break;
 457                 }
 458         }
 459 }
 460
 461 /*
 462  * PCI GART
 463  */
 464 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
 465 {
 466         /* TODO: can we do somethings here ? */
 467         /* It seems hw only cache one entry so we should discard this
 468          * entry otherwise if first GPU GART read hit this entry it
 469          * could end up in wrong address. */
 470 }
 471
 472 int r100_pci_gart_init(struct radeon_device *rdev)
 473 {
 474         int r;
 475
 476         if (rdev->gart.table.ram.ptr) {
 477                 WARN(1, "R100 PCI GART already initialized.\n");
 478                 return 0;
 479         }
 480         /* Initialize common gart structure */
 481         r = radeon_gart_init(rdev);
 482         if (r)
 483                 return r;
 484         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
 485         rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
 486         rdev->asic->gart_set_page = &r100_pci_gart_set_page;
 487         return radeon_gart_table_ram_alloc(rdev);
 488 }
 489
 490 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
 491 void r100_enable_bm(struct radeon_device *rdev)
 492 {
 493         uint32_t tmp;
 494         /* Enable bus mastering */
 495         tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 496         WREG32(RADEON_BUS_CNTL, tmp);
 497 }
 498
 499 int r100_pci_gart_enable(struct radeon_device *rdev)
 500 {
 501         uint32_t tmp;
 502
 503         radeon_gart_restore(rdev);
 504         /* discard memory request outside of configured range */
 505         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 506         WREG32(RADEON_AIC_CNTL, tmp);
 507         /* set address range for PCI address translate */
 508         WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
 509         WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
 510         /* set PCI GART page-table base address */
 511         WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
 512         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
 513         WREG32(RADEON_AIC_CNTL, tmp);
 514         r100_pci_gart_tlb_flush(rdev);
 515         rdev->gart.ready = true;
 516         return 0;
 517 }
 518
 519 void r100_pci_gart_disable(struct radeon_device *rdev)
 520 {
 521         uint32_t tmp;
 522
 523         /* discard memory request outside of configured range */
 524         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 525         WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
 526         WREG32(RADEON_AIC_LO_ADDR, 0);
 527         WREG32(RADEON_AIC_HI_ADDR, 0);
 528 }
 529
 530 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
 531 {
 532         if (i < 0 || i > rdev->gart.num_gpu_pages) {
 533                 return -EINVAL;
 534         }
 535         rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
 536         return 0;
 537 }
 538
 539 void r100_pci_gart_fini(struct radeon_device *rdev)
 540 {
 541         radeon_gart_fini(rdev);
 542         r100_pci_gart_disable(rdev);
 543         radeon_gart_table_ram_free(rdev);
 544 }
 545
 546 int r100_irq_set(struct radeon_device *rdev)
 547 {
 548         uint32_t tmp = 0;
 549
 550         if (!rdev->irq.installed) {
 551                 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
 552                 WREG32(R_000040_GEN_INT_CNTL, 0);
 553                 return -EINVAL;
 554         }
 555         if (rdev->irq.sw_int) {
 556                 tmp |= RADEON_SW_INT_ENABLE;
 557         }
 558         if (rdev->irq.gui_idle) {
 559                 tmp |= RADEON_GUI_IDLE_MASK;
 560         }
 561         if (rdev->irq.crtc_vblank_int[0]) {
 562                 tmp |= RADEON_CRTC_VBLANK_MASK;
 563         }
 564         if (rdev->irq.crtc_vblank_int[1]) {
 565                 tmp |= RADEON_CRTC2_VBLANK_MASK;
 566         }
 567         if (rdev->irq.hpd[0]) {
 568                 tmp |= RADEON_FP_DETECT_MASK;
 569         }
 570         if (rdev->irq.hpd[1]) {
 571                 tmp |= RADEON_FP2_DETECT_MASK;
 572         }
 573         WREG32(RADEON_GEN_INT_CNTL, tmp);
 574         return 0;
 575 }
 576
 577 void r100_irq_disable(struct radeon_device *rdev)
 578 {
 579         u32 tmp;
 580
 581         WREG32(R_000040_GEN_INT_CNTL, 0);
 582         /* Wait and acknowledge irq */
 583         mdelay(1);
 584         tmp = RREG32(R_000044_GEN_INT_STATUS);
 585         WREG32(R_000044_GEN_INT_STATUS, tmp);
 586 }
 587
 588 static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
 589 {
 590         uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
 591         uint32_t irq_mask = RADEON_SW_INT_TEST |
 592                 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
 593                 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
 594
 595         /* the interrupt works, but the status bit is permanently asserted */
 596         if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
 597                 if (!rdev->irq.gui_idle_acked)
 598                         irq_mask |= RADEON_GUI_IDLE_STAT;
 599         }
 600
 601         if (irqs) {
 602                 WREG32(RADEON_GEN_INT_STATUS, irqs);
 603         }
 604         return irqs & irq_mask;
 605 }
 606
 607 int r100_irq_process(struct radeon_device *rdev)
 608 {
 609         uint32_t status, msi_rearm;
 610         bool queue_hotplug = false;
 611
 612         /* reset gui idle ack.  the status bit is broken */
 613         rdev->irq.gui_idle_acked = false;
 614
 615         status = r100_irq_ack(rdev);
 616         if (!status) {
 617                 return IRQ_NONE;
 618         }
 619         if (rdev->shutdown) {
 620                 return IRQ_NONE;
 621         }
 622         while (status) {
 623                 /* SW interrupt */
 624                 if (status & RADEON_SW_INT_TEST) {
 625                         radeon_fence_process(rdev);
 626                 }
 627                 /* gui idle interrupt */
 628                 if (status & RADEON_GUI_IDLE_STAT) {
 629                         rdev->irq.gui_idle_acked = true;
 630                         rdev->pm.gui_idle = true;
 631                         wake_up(&rdev->irq.idle_queue);
 632                 }
 633                 /* Vertical blank interrupts */
 634                 if (status & RADEON_CRTC_VBLANK_STAT) {
 635                         drm_handle_vblank(rdev->ddev, 0);
 636                         rdev->pm.vblank_sync = true;
 637                         wake_up(&rdev->irq.vblank_queue);
 638                 }
 639                 if (status & RADEON_CRTC2_VBLANK_STAT) {
 640                         drm_handle_vblank(rdev->ddev, 1);
 641                         rdev->pm.vblank_sync = true;
 642                         wake_up(&rdev->irq.vblank_queue);
 643                 }
 644                 if (status & RADEON_FP_DETECT_STAT) {
 645                         queue_hotplug = true;
 646                         DRM_DEBUG("HPD1\n");
 647                 }
 648                 if (status & RADEON_FP2_DETECT_STAT) {
 649                         queue_hotplug = true;
 650                         DRM_DEBUG("HPD2\n");
 651                 }
 652                 status = r100_irq_ack(rdev);
 653         }
 654         /* reset gui idle ack.  the status bit is broken */
 655         rdev->irq.gui_idle_acked = false;
 656         if (queue_hotplug)
 657                 queue_work(rdev->wq, &rdev->hotplug_work);
 658         if (rdev->msi_enabled) {
 659                 switch (rdev->family) {
 660                 case CHIP_RS400:
 661                 case CHIP_RS480:
 662                         msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
 663                         WREG32(RADEON_AIC_CNTL, msi_rearm);
 664                         WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
 665                         break;
 666                 default:
 667                         msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
 668                         WREG32(RADEON_MSI_REARM_EN, msi_rearm);
 669                         WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
 670                         break;
 671                 }
 672         }
 673         return IRQ_HANDLED;
 674 }
 675
 676 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
 677 {
 678         if (crtc == 0)
 679                 return RREG32(RADEON_CRTC_CRNT_FRAME);
 680         else
 681                 return RREG32(RADEON_CRTC2_CRNT_FRAME);
 682 }
 683
 684 /* Who ever call radeon_fence_emit should call ring_lock and ask
 685  * for enough space (today caller are ib schedule and buffer move) */
 686 void r100_fence_ring_emit(struct radeon_device *rdev,
 687                           struct radeon_fence *fence)
 688 {
 689         /* We have to make sure that caches are flushed before
 690          * CPU might read something from VRAM. */
 691         radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
 692         radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
 693         radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
 694         radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
 695         /* Wait until IDLE & CLEAN */
 696         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 697         radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
 698         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 699         radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
 700                                 RADEON_HDP_READ_BUFFER_INVALIDATE);
 701         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 702         radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
 703         /* Emit fence sequence & fire IRQ */
 704         radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
 705         radeon_ring_write(rdev, fence->seq);
 706         radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
 707         radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
 708 }
 709
 710 int r100_wb_init(struct radeon_device *rdev)
 711 {
 712         int r;
 713
 714         if (rdev->wb.wb_obj == NULL) {
 715                 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
 716                                         RADEON_GEM_DOMAIN_GTT,
 717                                         &rdev->wb.wb_obj);
 718                 if (r) {
 719                         dev_err(rdev->dev, "(%d) create WB buffer failed\n", r);
 720                         return r;
 721                 }
 722                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
 723                 if (unlikely(r != 0))
 724                         return r;
 725                 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
 726                                         &rdev->wb.gpu_addr);
 727                 if (r) {
 728                         dev_err(rdev->dev, "(%d) pin WB buffer failed\n", r);
 729                         radeon_bo_unreserve(rdev->wb.wb_obj);
 730                         return r;
 731                 }
 732                 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
 733                 radeon_bo_unreserve(rdev->wb.wb_obj);
 734                 if (r) {
 735                         dev_err(rdev->dev, "(%d) map WB buffer failed\n", r);
 736                         return r;
 737                 }
 738         }
 739         WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
 740         WREG32(R_00070C_CP_RB_RPTR_ADDR,
 741                 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
 742         WREG32(R_000770_SCRATCH_UMSK, 0xff);
 743         return 0;
 744 }
 745
 746 void r100_wb_disable(struct radeon_device *rdev)
 747 {
 748         WREG32(R_000770_SCRATCH_UMSK, 0);
 749 }
 750
 751 void r100_wb_fini(struct radeon_device *rdev)
 752 {
 753         int r;
 754
 755         r100_wb_disable(rdev);
 756         if (rdev->wb.wb_obj) {
 757                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
 758                 if (unlikely(r != 0)) {
 759                         dev_err(rdev->dev, "(%d) can't finish WB\n", r);
 760                         return;
 761                 }
 762                 radeon_bo_kunmap(rdev->wb.wb_obj);
 763                 radeon_bo_unpin(rdev->wb.wb_obj);
 764                 radeon_bo_unreserve(rdev->wb.wb_obj);
 765                 radeon_bo_unref(&rdev->wb.wb_obj);
 766                 rdev->wb.wb = NULL;
 767                 rdev->wb.wb_obj = NULL;
 768         }
 769 }
 770
 771 int r100_copy_blit(struct radeon_device *rdev,
 772                    uint64_t src_offset,
 773                    uint64_t dst_offset,
 774                    unsigned num_pages,
 775                    struct radeon_fence *fence)
 776 {
 777         uint32_t cur_pages;
 778         uint32_t stride_bytes = PAGE_SIZE;
 779         uint32_t pitch;
 780         uint32_t stride_pixels;
 781         unsigned ndw;
 782         int num_loops;
 783         int r = 0;
 784
 785         /* radeon limited to 16k stride */
 786         stride_bytes &= 0x3fff;
 787         /* radeon pitch is /64 */
 788         pitch = stride_bytes / 64;
 789         stride_pixels = stride_bytes / 4;
 790         num_loops = DIV_ROUND_UP(num_pages, 8191);
 791
 792         /* Ask for enough room for blit + flush + fence */
 793         ndw = 64 + (10 * num_loops);
 794         r = radeon_ring_lock(rdev, ndw);
 795         if (r) {
 796                 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
 797                 return -EINVAL;
 798         }
 799         while (num_pages > 0) {
 800                 cur_pages = num_pages;
 801                 if (cur_pages > 8191) {
 802                         cur_pages = 8191;
 803                 }
 804                 num_pages -= cur_pages;
 805
 806                 /* pages are in Y direction - height
 807                    page width in X direction - width */
 808                 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
 809                 radeon_ring_write(rdev,
 810                                   RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
 811                                   RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 812                                   RADEON_GMC_SRC_CLIPPING |
 813                                   RADEON_GMC_DST_CLIPPING |
 814                                   RADEON_GMC_BRUSH_NONE |
 815                                   (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
 816                                   RADEON_GMC_SRC_DATATYPE_COLOR |
 817                                   RADEON_ROP3_S |
 818                                   RADEON_DP_SRC_SOURCE_MEMORY |
 819                                   RADEON_GMC_CLR_CMP_CNTL_DIS |
 820                                   RADEON_GMC_WR_MSK_DIS);
 821                 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
 822                 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
 823                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
 824                 radeon_ring_write(rdev, 0);
 825                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
 826                 radeon_ring_write(rdev, num_pages);
 827                 radeon_ring_write(rdev, num_pages);
 828                 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
 829         }
 830         radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
 831         radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
 832         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 833         radeon_ring_write(rdev,
 834                           RADEON_WAIT_2D_IDLECLEAN |
 835                           RADEON_WAIT_HOST_IDLECLEAN |
 836                           RADEON_WAIT_DMA_GUI_IDLE);
 837         if (fence) {
 838                 r = radeon_fence_emit(rdev, fence);
 839         }
 840         radeon_ring_unlock_commit(rdev);
 841         return r;
 842 }
 843
 844 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
 845 {
 846         unsigned i;
 847         u32 tmp;
 848
 849         for (i = 0; i < rdev->usec_timeout; i++) {
 850                 tmp = RREG32(R_000E40_RBBM_STATUS);
 851                 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
 852                         return 0;
 853                 }
 854                 udelay(1);
 855         }
 856         return -1;
 857 }
 858
 859 void r100_ring_start(struct radeon_device *rdev)
 860 {
 861         int r;
 862
 863         r = radeon_ring_lock(rdev, 2);
 864         if (r) {
 865                 return;
 866         }
 867         radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
 868         radeon_ring_write(rdev,
 869                           RADEON_ISYNC_ANY2D_IDLE3D |
 870                           RADEON_ISYNC_ANY3D_IDLE2D |
 871                           RADEON_ISYNC_WAIT_IDLEGUI |
 872                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 873         radeon_ring_unlock_commit(rdev);
 874 }
 875
 876
 877 /* Load the microcode for the CP */
 878 static int r100_cp_init_microcode(struct radeon_device *rdev)
 879 {
 880         struct platform_device *pdev;
 881         const char *fw_name = NULL;
 882         int err;
 883
 884         DRM_DEBUG("\n");
 885
 886         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
 887         err = IS_ERR(pdev);
 888         if (err) {
 889                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
 890                 return -EINVAL;
 891         }
 892         if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
 893             (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
 894             (rdev->family == CHIP_RS200)) {
 895                 DRM_INFO("Loading R100 Microcode\n");
 896                 fw_name = FIRMWARE_R100;
 897         } else if ((rdev->family == CHIP_R200) ||
 898                    (rdev->family == CHIP_RV250) ||
 899                    (rdev->family == CHIP_RV280) ||
 900                    (rdev->family == CHIP_RS300)) {
 901                 DRM_INFO("Loading R200 Microcode\n");
 902                 fw_name = FIRMWARE_R200;
 903         } else if ((rdev->family == CHIP_R300) ||
 904                    (rdev->family == CHIP_R350) ||
 905                    (rdev->family == CHIP_RV350) ||
 906                    (rdev->family == CHIP_RV380) ||
 907                    (rdev->family == CHIP_RS400) ||
 908                    (rdev->family == CHIP_RS480)) {
 909                 DRM_INFO("Loading R300 Microcode\n");
 910                 fw_name = FIRMWARE_R300;
 911         } else if ((rdev->family == CHIP_R420) ||
 912                    (rdev->family == CHIP_R423) ||
 913                    (rdev->family == CHIP_RV410)) {
 914                 DRM_INFO("Loading R400 Microcode\n");
 915                 fw_name = FIRMWARE_R420;
 916         } else if ((rdev->family == CHIP_RS690) ||
 917                    (rdev->family == CHIP_RS740)) {
 918                 DRM_INFO("Loading RS690/RS740 Microcode\n");
 919                 fw_name = FIRMWARE_RS690;
 920         } else if (rdev->family == CHIP_RS600) {
 921                 DRM_INFO("Loading RS600 Microcode\n");
 922                 fw_name = FIRMWARE_RS600;
 923         } else if ((rdev->family == CHIP_RV515) ||
 924                    (rdev->family == CHIP_R520) ||
 925                    (rdev->family == CHIP_RV530) ||
 926                    (rdev->family == CHIP_R580) ||
 927                    (rdev->family == CHIP_RV560) ||
 928                    (rdev->family == CHIP_RV570)) {
 929                 DRM_INFO("Loading R500 Microcode\n");
 930                 fw_name = FIRMWARE_R520;
 931         }
 932
 933         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
 934         platform_device_unregister(pdev);
 935         if (err) {
 936                 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
 937                        fw_name);
 938         } else if (rdev->me_fw->size % 8) {
 939                 printk(KERN_ERR
 940                        "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
 941                        rdev->me_fw->size, fw_name);
 942                 err = -EINVAL;
 943                 release_firmware(rdev->me_fw);
 944                 rdev->me_fw = NULL;
 945         }
 946         return err;
 947 }
 948
 949 static void r100_cp_load_microcode(struct radeon_device *rdev)
 950 {
 951         const __be32 *fw_data;
 952         int i, size;
 953
 954         if (r100_gui_wait_for_idle(rdev)) {
 955                 printk(KERN_WARNING "Failed to wait GUI idle while "
 956                        "programming pipes. Bad things might happen.\n");
 957         }
 958
 959         if (rdev->me_fw) {
 960                 size = rdev->me_fw->size / 4;
 961                 fw_data = (const __be32 *)&rdev->me_fw->data[0];
 962                 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
 963                 for (i = 0; i < size; i += 2) {
 964                         WREG32(RADEON_CP_ME_RAM_DATAH,
 965                                be32_to_cpup(&fw_data[i]));
 966                         WREG32(RADEON_CP_ME_RAM_DATAL,
 967                                be32_to_cpup(&fw_data[i + 1]));
 968                 }
 969         }
 970 }
 971
 972 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
 973 {
 974         unsigned rb_bufsz;
 975         unsigned rb_blksz;
 976         unsigned max_fetch;
 977         unsigned pre_write_timer;
 978         unsigned pre_write_limit;
 979         unsigned indirect2_start;
 980         unsigned indirect1_start;
 981         uint32_t tmp;
 982         int r;
 983
 984         if (r100_debugfs_cp_init(rdev)) {
 985                 DRM_ERROR("Failed to register debugfs file for CP !\n");
 986         }
 987         if (!rdev->me_fw) {
 988                 r = r100_cp_init_microcode(rdev);
 989                 if (r) {
 990                         DRM_ERROR("Failed to load firmware!\n");
 991                         return r;
 992                 }
 993         }
 994
 995         /* Align ring size */
 996         rb_bufsz = drm_order(ring_size / 8);
 997         ring_size = (1 << (rb_bufsz + 1)) * 4;
 998         r100_cp_load_microcode(rdev);
 999         r = radeon_ring_init(rdev, ring_size);
1000         if (r) {
1001                 return r;
1002         }
1003         /* Each time the cp read 1024 bytes (16 dword/quadword) update
1004          * the rptr copy in system ram */
1005         rb_blksz = 9;
1006         /* cp will read 128bytes at a time (4 dwords) */
1007         max_fetch = 1;
1008         rdev->cp.align_mask = 16 - 1;
1009         /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
1010         pre_write_timer = 64;
1011         /* Force CP_RB_WPTR write if written more than one time before the
1012          * delay expire
1013          */
1014         pre_write_limit = 0;
1015         /* Setup the cp cache like this (cache size is 96 dwords) :
1016          *      RING            0  to 15
1017          *      INDIRECT1       16 to 79
1018          *      INDIRECT2       80 to 95
1019          * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1020          *    indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
1021          *    indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1022          * Idea being that most of the gpu cmd will be through indirect1 buffer
1023          * so it gets the bigger cache.
1024          */
1025         indirect2_start = 80;
1026         indirect1_start = 16;
1027         /* cp setup */
1028         WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
1029         tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
1030                REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
1031                REG_SET(RADEON_MAX_FETCH, max_fetch) |
1032                RADEON_RB_NO_UPDATE);
1033 #ifdef __BIG_ENDIAN
1034         tmp |= RADEON_BUF_SWAP_32BIT;
1035 #endif
1036         WREG32(RADEON_CP_RB_CNTL, tmp);
1037
1038         /* Set ring address */
1039         DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
1040         WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
1041         /* Force read & write ptr to 0 */
1042         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
1043         WREG32(RADEON_CP_RB_RPTR_WR, 0);
1044         WREG32(RADEON_CP_RB_WPTR, 0);
1045         WREG32(RADEON_CP_RB_CNTL, tmp);
1046         udelay(10);
1047         rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
1048         rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
1049         /* protect against crazy HW on resume */
1050         rdev->cp.wptr &= rdev->cp.ptr_mask;
1051         /* Set cp mode to bus mastering & enable cp*/
1052         WREG32(RADEON_CP_CSQ_MODE,
1053                REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1054                REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1055         WREG32(0x718, 0);
1056         WREG32(0x744, 0x00004D4D);
1057         WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1058         radeon_ring_start(rdev);
1059         r = radeon_ring_test(rdev);
1060         if (r) {
1061                 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1062                 return r;
1063         }
1064         rdev->cp.ready = true;
1065         return 0;
1066 }
1067
1068 void r100_cp_fini(struct radeon_device *rdev)
1069 {
1070         if (r100_cp_wait_for_idle(rdev)) {
1071                 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1072         }
1073         /* Disable ring */
1074         r100_cp_disable(rdev);
1075         radeon_ring_fini(rdev);
1076         DRM_INFO("radeon: cp finalized\n");
1077 }
1078
1079 void r100_cp_disable(struct radeon_device *rdev)
1080 {
1081         /* Disable ring */
1082         rdev->cp.ready = false;
1083         WREG32(RADEON_CP_CSQ_MODE, 0);
1084         WREG32(RADEON_CP_CSQ_CNTL, 0);
1085         if (r100_gui_wait_for_idle(rdev)) {
1086                 printk(KERN_WARNING "Failed to wait GUI idle while "
1087                        "programming pipes. Bad things might happen.\n");
1088         }
1089 }
1090
1091 void r100_cp_commit(struct radeon_device *rdev)
1092 {
1093         WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
1094         (void)RREG32(RADEON_CP_RB_WPTR);
1095 }
1096
1097
1098 /*
1099  * CS functions
1100  */
1101 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1102                           struct radeon_cs_packet *pkt,
1103                           const unsigned *auth, unsigned n,
1104                           radeon_packet0_check_t check)
1105 {
1106         unsigned reg;
1107         unsigned i, j, m;
1108         unsigned idx;
1109         int r;
1110
1111         idx = pkt->idx + 1;
1112         reg = pkt->reg;
1113         /* Check that register fall into register range
1114          * determined by the number of entry (n) in the
1115          * safe register bitmap.
1116          */
1117         if (pkt->one_reg_wr) {
1118                 if ((reg >> 7) > n) {
1119                         return -EINVAL;
1120                 }
1121         } else {
1122                 if (((reg + (pkt->count << 2)) >> 7) > n) {
1123                         return -EINVAL;
1124                 }
1125         }
1126         for (i = 0; i <= pkt->count; i++, idx++) {
1127                 j = (reg >> 7);
1128                 m = 1 << ((reg >> 2) & 31);
1129                 if (auth[j] & m) {
1130                         r = check(p, pkt, idx, reg);
1131                         if (r) {
1132                                 return r;
1133                         }
1134                 }
1135                 if (pkt->one_reg_wr) {
1136                         if (!(auth[j] & m)) {
1137                                 break;
1138                         }
1139                 } else {
1140                         reg += 4;
1141                 }
1142         }
1143         return 0;
1144 }
1145
1146 void r100_cs_dump_packet(struct radeon_cs_parser *p,
1147                          struct radeon_cs_packet *pkt)
1148 {
1149         volatile uint32_t *ib;
1150         unsigned i;
1151         unsigned idx;
1152
1153         ib = p->ib->ptr;
1154         idx = pkt->idx;
1155         for (i = 0; i <= (pkt->count + 1); i++, idx++) {
1156                 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
1157         }
1158 }
1159
1160 /**
1161  * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
1162  * @parser:     parser structure holding parsing context.
1163  * @pkt:        where to store packet informations
1164  *
1165  * Assume that chunk_ib_index is properly set. Will return -EINVAL
1166  * if packet is bigger than remaining ib size. or if packets is unknown.
1167  **/
1168 int r100_cs_packet_parse(struct radeon_cs_parser *p,
1169                          struct radeon_cs_packet *pkt,
1170                          unsigned idx)
1171 {
1172         struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
1173         uint32_t header;
1174
1175         if (idx >= ib_chunk->length_dw) {
1176                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
1177                           idx, ib_chunk->length_dw);
1178                 return -EINVAL;
1179         }
1180         header = radeon_get_ib_value(p, idx);
1181         pkt->idx = idx;
1182         pkt->type = CP_PACKET_GET_TYPE(header);
1183         pkt->count = CP_PACKET_GET_COUNT(header);
1184         switch (pkt->type) {
1185         case PACKET_TYPE0:
1186                 pkt->reg = CP_PACKET0_GET_REG(header);
1187                 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
1188                 break;
1189         case PACKET_TYPE3:
1190                 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
1191                 break;
1192         case PACKET_TYPE2:
1193                 pkt->count = -1;
1194                 break;
1195         default:
1196                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
1197                 return -EINVAL;
1198         }
1199         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
1200                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
1201                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
1202                 return -EINVAL;
1203         }
1204         return 0;
1205 }
1206
1207 /**
1208  * r100_cs_packet_next_vline() - parse userspace VLINE packet
1209  * @parser:             parser structure holding parsing context.
1210  *
1211  * Userspace sends a special sequence for VLINE waits.
1212  * PACKET0 - VLINE_START_END + value
1213  * PACKET0 - WAIT_UNTIL +_value
1214  * RELOC (P3) - crtc_id in reloc.
1215  *
1216  * This function parses this and relocates the VLINE START END
1217  * and WAIT UNTIL packets to the correct crtc.
1218  * It also detects a switched off crtc and nulls out the
1219  * wait in that case.
1220  */
1221 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1222 {
1223         struct drm_mode_object *obj;
1224         struct drm_crtc *crtc;
1225         struct radeon_crtc *radeon_crtc;
1226         struct radeon_cs_packet p3reloc, waitreloc;
1227         int crtc_id;
1228         int r;
1229         uint32_t header, h_idx, reg;
1230         volatile uint32_t *ib;
1231
1232         ib = p->ib->ptr;
1233
1234         /* parse the wait until */
1235         r = r100_cs_packet_parse(p, &waitreloc, p->idx);
1236         if (r)
1237                 return r;
1238
1239         /* check its a wait until and only 1 count */
1240         if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1241             waitreloc.count != 0) {
1242                 DRM_ERROR("vline wait had illegal wait until segment\n");
1243                 r = -EINVAL;
1244                 return r;
1245         }
1246
1247         if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1248                 DRM_ERROR("vline wait had illegal wait until\n");
1249                 r = -EINVAL;
1250                 return r;
1251         }
1252
1253         /* jump over the NOP */
1254         r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1255         if (r)
1256                 return r;
1257
1258         h_idx = p->idx - 2;
1259         p->idx += waitreloc.count + 2;
1260         p->idx += p3reloc.count + 2;
1261
1262         header = radeon_get_ib_value(p, h_idx);
1263         crtc_id = radeon_get_ib_value(p, h_idx + 5);
1264         reg = CP_PACKET0_GET_REG(header);
1265         mutex_lock(&p->rdev->ddev->mode_config.mutex);
1266         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1267         if (!obj) {
1268                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1269                 r = -EINVAL;
1270                 goto out;
1271         }
1272         crtc = obj_to_crtc(obj);
1273         radeon_crtc = to_radeon_crtc(crtc);
1274         crtc_id = radeon_crtc->crtc_id;
1275
1276         if (!crtc->enabled) {
1277                 /* if the CRTC isn't enabled - we need to nop out the wait until */
1278                 ib[h_idx + 2] = PACKET2(0);
1279                 ib[h_idx + 3] = PACKET2(0);
1280         } else if (crtc_id == 1) {
1281                 switch (reg) {
1282                 case AVIVO_D1MODE_VLINE_START_END:
1283                         header &= ~R300_CP_PACKET0_REG_MASK;
1284                         header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1285                         break;
1286                 case RADEON_CRTC_GUI_TRIG_VLINE:
1287                         header &= ~R300_CP_PACKET0_REG_MASK;
1288                         header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1289                         break;
1290                 default:
1291                         DRM_ERROR("unknown crtc reloc\n");
1292                         r = -EINVAL;
1293                         goto out;
1294                 }
1295                 ib[h_idx] = header;
1296                 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1297         }
1298 out:
1299         mutex_unlock(&p->rdev->ddev->mode_config.mutex);
1300         return r;
1301 }
1302
1303 /**
1304  * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1305  * @parser:             parser structure holding parsing context.
1306  * @data:               pointer to relocation data
1307  * @offset_start:       starting offset
1308  * @offset_mask:        offset mask (to align start offset on)
1309  * @reloc:              reloc informations
1310  *
1311  * Check next packet is relocation packet3, do bo validation and compute
1312  * GPU offset using the provided start.
1313  **/
1314 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1315                               struct radeon_cs_reloc **cs_reloc)
1316 {
1317         struct radeon_cs_chunk *relocs_chunk;
1318         struct radeon_cs_packet p3reloc;
1319         unsigned idx;
1320         int r;
1321
1322         if (p->chunk_relocs_idx == -1) {
1323                 DRM_ERROR("No relocation chunk !\n");
1324                 return -EINVAL;
1325         }
1326         *cs_reloc = NULL;
1327         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1328         r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1329         if (r) {
1330                 return r;
1331         }
1332         p->idx += p3reloc.count + 2;
1333         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1334                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1335                           p3reloc.idx);
1336                 r100_cs_dump_packet(p, &p3reloc);
1337                 return -EINVAL;
1338         }
1339         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1340         if (idx >= relocs_chunk->length_dw) {
1341                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1342                           idx, relocs_chunk->length_dw);
1343                 r100_cs_dump_packet(p, &p3reloc);
1344                 return -EINVAL;
1345         }
1346         /* FIXME: we assume reloc size is 4 dwords */
1347         *cs_reloc = p->relocs_ptr[(idx / 4)];
1348         return 0;
1349 }
1350
1351 static int r100_get_vtx_size(uint32_t vtx_fmt)
1352 {
1353         int vtx_size;
1354         vtx_size = 2;
1355         /* ordered according to bits in spec */
1356         if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1357                 vtx_size++;
1358         if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1359                 vtx_size += 3;
1360         if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1361                 vtx_size++;
1362         if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1363                 vtx_size++;
1364         if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1365                 vtx_size += 3;
1366         if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1367                 vtx_size++;
1368         if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1369                 vtx_size++;
1370         if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1371                 vtx_size += 2;
1372         if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1373                 vtx_size += 2;
1374         if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1375                 vtx_size++;
1376         if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1377                 vtx_size += 2;
1378         if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1379                 vtx_size++;
1380         if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1381                 vtx_size += 2;
1382         if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1383                 vtx_size++;
1384         if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1385                 vtx_size++;
1386         /* blend weight */
1387         if (vtx_fmt & (0x7 << 15))
1388                 vtx_size += (vtx_fmt >> 15) & 0x7;
1389         if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1390                 vtx_size += 3;
1391         if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1392                 vtx_size += 2;
1393         if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1394                 vtx_size++;
1395         if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1396                 vtx_size++;
1397         if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1398                 vtx_size++;
1399         if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1400                 vtx_size++;
1401         return vtx_size;
1402 }
1403
1404 static int r100_packet0_check(struct radeon_cs_parser *p,
1405                               struct radeon_cs_packet *pkt,
1406                               unsigned idx, unsigned reg)
1407 {
1408         struct radeon_cs_reloc *reloc;
1409         struct r100_cs_track *track;
1410         volatile uint32_t *ib;
1411         uint32_t tmp;
1412         int r;
1413         int i, face;
1414         u32 tile_flags = 0;
1415         u32 idx_value;
1416
1417         ib = p->ib->ptr;
1418         track = (struct r100_cs_track *)p->track;
1419
1420         idx_value = radeon_get_ib_value(p, idx);
1421
1422         switch (reg) {
1423         case RADEON_CRTC_GUI_TRIG_VLINE:
1424                 r = r100_cs_packet_parse_vline(p);
1425                 if (r) {
1426                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1427                                   idx, reg);
1428                         r100_cs_dump_packet(p, pkt);
1429                         return r;
1430                 }
1431                 break;
1432                 /* FIXME: only allow PACKET3 blit? easier to check for out of
1433                  * range access */
1434         case RADEON_DST_PITCH_OFFSET:
1435         case RADEON_SRC_PITCH_OFFSET:
1436                 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1437                 if (r)
1438                         return r;
1439                 break;
1440         case RADEON_RB3D_DEPTHOFFSET:
1441                 r = r100_cs_packet_next_reloc(p, &reloc);
1442                 if (r) {
1443                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1444                                   idx, reg);
1445                         r100_cs_dump_packet(p, pkt);
1446                         return r;
1447                 }
1448                 track->zb.robj = reloc->robj;
1449                 track->zb.offset = idx_value;
1450                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1451                 break;
1452         case RADEON_RB3D_COLOROFFSET:
1453                 r = r100_cs_packet_next_reloc(p, &reloc);
1454                 if (r) {
1455                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1456                                   idx, reg);
1457                         r100_cs_dump_packet(p, pkt);
1458                         return r;
1459                 }
1460                 track->cb[0].robj = reloc->robj;
1461                 track->cb[0].offset = idx_value;
1462                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1463                 break;
1464         case RADEON_PP_TXOFFSET_0:
1465         case RADEON_PP_TXOFFSET_1:
1466         case RADEON_PP_TXOFFSET_2:
1467                 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1468                 r = r100_cs_packet_next_reloc(p, &reloc);
1469                 if (r) {
1470                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1471                                   idx, reg);
1472                         r100_cs_dump_packet(p, pkt);
1473                         return r;
1474                 }
1475                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1476                 track->textures[i].robj = reloc->robj;
1477                 break;
1478         case RADEON_PP_CUBIC_OFFSET_T0_0:
1479         case RADEON_PP_CUBIC_OFFSET_T0_1:
1480         case RADEON_PP_CUBIC_OFFSET_T0_2:
1481         case RADEON_PP_CUBIC_OFFSET_T0_3:
1482         case RADEON_PP_CUBIC_OFFSET_T0_4:
1483                 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1484                 r = r100_cs_packet_next_reloc(p, &reloc);
1485                 if (r) {
1486                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1487                                   idx, reg);
1488                         r100_cs_dump_packet(p, pkt);
1489                         return r;
1490                 }
1491                 track->textures[0].cube_info[i].offset = idx_value;
1492                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1493                 track->textures[0].cube_info[i].robj = reloc->robj;
1494                 break;
1495         case RADEON_PP_CUBIC_OFFSET_T1_0:
1496         case RADEON_PP_CUBIC_OFFSET_T1_1:
1497         case RADEON_PP_CUBIC_OFFSET_T1_2:
1498         case RADEON_PP_CUBIC_OFFSET_T1_3:
1499         case RADEON_PP_CUBIC_OFFSET_T1_4:
1500                 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1501                 r = r100_cs_packet_next_reloc(p, &reloc);
1502                 if (r) {
1503                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1504                                   idx, reg);
1505                         r100_cs_dump_packet(p, pkt);
1506                         return r;
1507                 }
1508                 track->textures[1].cube_info[i].offset = idx_value;
1509                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1510                 track->textures[1].cube_info[i].robj = reloc->robj;
1511                 break;
1512         case RADEON_PP_CUBIC_OFFSET_T2_0:
1513         case RADEON_PP_CUBIC_OFFSET_T2_1:
1514         case RADEON_PP_CUBIC_OFFSET_T2_2:
1515         case RADEON_PP_CUBIC_OFFSET_T2_3:
1516         case RADEON_PP_CUBIC_OFFSET_T2_4:
1517                 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1518                 r = r100_cs_packet_next_reloc(p, &reloc);
1519                 if (r) {
1520                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1521                                   idx, reg);
1522                         r100_cs_dump_packet(p, pkt);
1523                         return r;
1524                 }
1525                 track->textures[2].cube_info[i].offset = idx_value;
1526                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1527                 track->textures[2].cube_info[i].robj = reloc->robj;
1528                 break;
1529         case RADEON_RE_WIDTH_HEIGHT:
1530                 track->maxy = ((idx_value >> 16) & 0x7FF);
1531                 break;
1532         case RADEON_RB3D_COLORPITCH:
1533                 r = r100_cs_packet_next_reloc(p, &reloc);
1534                 if (r) {
1535                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1536                                   idx, reg);
1537                         r100_cs_dump_packet(p, pkt);
1538                         return r;
1539                 }
1540
1541                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1542                         tile_flags |= RADEON_COLOR_TILE_ENABLE;
1543                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1544                         tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1545
1546                 tmp = idx_value & ~(0x7 << 16);
1547                 tmp |= tile_flags;
1548                 ib[idx] = tmp;
1549
1550                 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1551                 break;
1552         case RADEON_RB3D_DEPTHPITCH:
1553                 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1554                 break;
1555         case RADEON_RB3D_CNTL:
1556                 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1557                 case 7:
1558                 case 8:
1559                 case 9:
1560                 case 11:
1561                 case 12:
1562                         track->cb[0].cpp = 1;
1563                         break;
1564                 case 3:
1565                 case 4:
1566                 case 15:
1567                         track->cb[0].cpp = 2;
1568                         break;
1569                 case 6:
1570                         track->cb[0].cpp = 4;
1571                         break;
1572                 default:
1573                         DRM_ERROR("Invalid color buffer format (%d) !\n",
1574                                   ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1575                         return -EINVAL;
1576                 }
1577                 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1578                 break;
1579         case RADEON_RB3D_ZSTENCILCNTL:
1580                 switch (idx_value & 0xf) {
1581                 case 0:
1582                         track->zb.cpp = 2;
1583                         break;
1584                 case 2:
1585                 case 3:
1586                 case 4:
1587                 case 5:
1588                 case 9:
1589                 case 11:
1590                         track->zb.cpp = 4;
1591                         break;
1592                 default:
1593                         break;
1594                 }
1595                 break;
1596         case RADEON_RB3D_ZPASS_ADDR:
1597                 r = r100_cs_packet_next_reloc(p, &reloc);
1598                 if (r) {
1599                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1600                                   idx, reg);
1601                         r100_cs_dump_packet(p, pkt);
1602                         return r;
1603                 }
1604                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1605                 break;
1606         case RADEON_PP_CNTL:
1607                 {
1608                         uint32_t temp = idx_value >> 4;
1609                         for (i = 0; i < track->num_texture; i++)
1610                                 track->textures[i].enabled = !!(temp & (1 << i));
1611                 }
1612                 break;
1613         case RADEON_SE_VF_CNTL:
1614                 track->vap_vf_cntl = idx_value;
1615                 break;
1616         case RADEON_SE_VTX_FMT:
1617                 track->vtx_size = r100_get_vtx_size(idx_value);
1618                 break;
1619         case RADEON_PP_TEX_SIZE_0:
1620         case RADEON_PP_TEX_SIZE_1:
1621         case RADEON_PP_TEX_SIZE_2:
1622                 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1623                 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1624                 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1625                 break;
1626         case RADEON_PP_TEX_PITCH_0:
1627         case RADEON_PP_TEX_PITCH_1:
1628         case RADEON_PP_TEX_PITCH_2:
1629                 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1630                 track->textures[i].pitch = idx_value + 32;
1631                 break;
1632         case RADEON_PP_TXFILTER_0:
1633         case RADEON_PP_TXFILTER_1:
1634         case RADEON_PP_TXFILTER_2:
1635                 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1636                 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1637                                                  >> RADEON_MAX_MIP_LEVEL_SHIFT);
1638                 tmp = (idx_value >> 23) & 0x7;
1639                 if (tmp == 2 || tmp == 6)
1640                         track->textures[i].roundup_w = false;
1641                 tmp = (idx_value >> 27) & 0x7;
1642                 if (tmp == 2 || tmp == 6)
1643                         track->textures[i].roundup_h = false;
1644                 break;
1645         case RADEON_PP_TXFORMAT_0:
1646         case RADEON_PP_TXFORMAT_1:
1647         case RADEON_PP_TXFORMAT_2:
1648                 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1649                 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1650                         track->textures[i].use_pitch = 1;
1651                 } else {
1652                         track->textures[i].use_pitch = 0;
1653                         track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1654                         track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1655                 }
1656                 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1657                         track->textures[i].tex_coord_type = 2;
1658                 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1659                 case RADEON_TXFORMAT_I8:
1660                 case RADEON_TXFORMAT_RGB332:
1661                 case RADEON_TXFORMAT_Y8:
1662                         track->textures[i].cpp = 1;
1663                         break;
1664                 case RADEON_TXFORMAT_AI88:
1665                 case RADEON_TXFORMAT_ARGB1555:
1666                 case RADEON_TXFORMAT_RGB565:
1667                 case RADEON_TXFORMAT_ARGB4444:
1668                 case RADEON_TXFORMAT_VYUY422:
1669                 case RADEON_TXFORMAT_YVYU422:
1670                 case RADEON_TXFORMAT_SHADOW16:
1671                 case RADEON_TXFORMAT_LDUDV655:
1672                 case RADEON_TXFORMAT_DUDV88:
1673                         track->textures[i].cpp = 2;
1674                         break;
1675                 case RADEON_TXFORMAT_ARGB8888:
1676                 case RADEON_TXFORMAT_RGBA8888:
1677                 case RADEON_TXFORMAT_SHADOW32:
1678                 case RADEON_TXFORMAT_LDUDUV8888:
1679                         track->textures[i].cpp = 4;
1680                         break;
1681                 case RADEON_TXFORMAT_DXT1:
1682                         track->textures[i].cpp = 1;
1683                         track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1684                         break;
1685                 case RADEON_TXFORMAT_DXT23:
1686                 case RADEON_TXFORMAT_DXT45:
1687                         track->textures[i].cpp = 1;
1688                         track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1689                         break;
1690                 }
1691                 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1692                 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1693                 break;
1694         case RADEON_PP_CUBIC_FACES_0:
1695         case RADEON_PP_CUBIC_FACES_1:
1696         case RADEON_PP_CUBIC_FACES_2:
1697                 tmp = idx_value;
1698                 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1699                 for (face = 0; face < 4; face++) {
1700                         track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1701                         track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1702                 }
1703                 break;
1704         default:
1705                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1706                        reg, idx);
1707                 return -EINVAL;
1708         }
1709         return 0;
1710 }
1711
1712 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1713                                          struct radeon_cs_packet *pkt,
1714                                          struct radeon_bo *robj)
1715 {
1716         unsigned idx;
1717         u32 value;
1718         idx = pkt->idx + 1;
1719         value = radeon_get_ib_value(p, idx + 2);
1720         if ((value + 1) > radeon_bo_size(robj)) {
1721                 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1722                           "(need %u have %lu) !\n",
1723                           value + 1,
1724                           radeon_bo_size(robj));
1725                 return -EINVAL;
1726         }
1727         return 0;
1728 }
1729
1730 static int r100_packet3_check(struct radeon_cs_parser *p,
1731                               struct radeon_cs_packet *pkt)
1732 {
1733         struct radeon_cs_reloc *reloc;
1734         struct r100_cs_track *track;
1735         unsigned idx;
1736         volatile uint32_t *ib;
1737         int r;
1738
1739         ib = p->ib->ptr;
1740         idx = pkt->idx + 1;
1741         track = (struct r100_cs_track *)p->track;
1742         switch (pkt->opcode) {
1743         case PACKET3_3D_LOAD_VBPNTR:
1744                 r = r100_packet3_load_vbpntr(p, pkt, idx);
1745                 if (r)
1746                         return r;
1747                 break;
1748         case PACKET3_INDX_BUFFER:
1749                 r = r100_cs_packet_next_reloc(p, &reloc);
1750                 if (r) {
1751                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1752                         r100_cs_dump_packet(p, pkt);
1753                         return r;
1754                 }
1755                 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1756                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1757                 if (r) {
1758                         return r;
1759                 }
1760                 break;
1761         case 0x23:
1762                 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1763                 r = r100_cs_packet_next_reloc(p, &reloc);
1764                 if (r) {
1765                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1766                         r100_cs_dump_packet(p, pkt);
1767                         return r;
1768                 }
1769                 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1770                 track->num_arrays = 1;
1771                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1772
1773                 track->arrays[0].robj = reloc->robj;
1774                 track->arrays[0].esize = track->vtx_size;
1775
1776                 track->max_indx = radeon_get_ib_value(p, idx+1);
1777
1778                 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1779                 track->immd_dwords = pkt->count - 1;
1780                 r = r100_cs_track_check(p->rdev, track);
1781                 if (r)
1782                         return r;
1783                 break;
1784         case PACKET3_3D_DRAW_IMMD:
1785                 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1786                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1787                         return -EINVAL;
1788                 }
1789                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1790                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1791                 track->immd_dwords = pkt->count - 1;
1792                 r = r100_cs_track_check(p->rdev, track);
1793                 if (r)
1794                         return r;
1795                 break;
1796                 /* triggers drawing using in-packet vertex data */
1797         case PACKET3_3D_DRAW_IMMD_2:
1798                 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1799                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1800                         return -EINVAL;
1801                 }
1802                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1803                 track->immd_dwords = pkt->count;
1804                 r = r100_cs_track_check(p->rdev, track);
1805                 if (r)
1806                         return r;
1807                 break;
1808                 /* triggers drawing using in-packet vertex data */
1809         case PACKET3_3D_DRAW_VBUF_2:
1810                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1811                 r = r100_cs_track_check(p->rdev, track);
1812                 if (r)
1813                         return r;
1814                 break;
1815                 /* triggers drawing of vertex buffers setup elsewhere */
1816         case PACKET3_3D_DRAW_INDX_2:
1817                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1818                 r = r100_cs_track_check(p->rdev, track);
1819                 if (r)
1820                         return r;
1821                 break;
1822                 /* triggers drawing using indices to vertex buffer */
1823         case PACKET3_3D_DRAW_VBUF:
1824                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1825                 r = r100_cs_track_check(p->rdev, track);
1826                 if (r)
1827                         return r;
1828                 break;
1829                 /* triggers drawing of vertex buffers setup elsewhere */
1830         case PACKET3_3D_DRAW_INDX:
1831                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1832                 r = r100_cs_track_check(p->rdev, track);
1833                 if (r)
1834                         return r;
1835                 break;
1836                 /* triggers drawing using indices to vertex buffer */
1837         case PACKET3_NOP:
1838                 break;
1839         default:
1840                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1841                 return -EINVAL;
1842         }
1843         return 0;
1844 }
1845
1846 int r100_cs_parse(struct radeon_cs_parser *p)
1847 {
1848         struct radeon_cs_packet pkt;
1849         struct r100_cs_track *track;
1850         int r;
1851
1852         track = kzalloc(sizeof(*track), GFP_KERNEL);
1853         r100_cs_track_clear(p->rdev, track);
1854         p->track = track;
1855         do {
1856                 r = r100_cs_packet_parse(p, &pkt, p->idx);
1857                 if (r) {
1858                         return r;
1859                 }
1860                 p->idx += pkt.count + 2;
1861                 switch (pkt.type) {
1862                         case PACKET_TYPE0:
1863                                 if (p->rdev->family >= CHIP_R200)
1864                                         r = r100_cs_parse_packet0(p, &pkt,
1865                                                                   p->rdev->config.r100.reg_safe_bm,
1866                                                                   p->rdev->config.r100.reg_safe_bm_size,
1867                                                                   &r200_packet0_check);
1868                                 else
1869                                         r = r100_cs_parse_packet0(p, &pkt,
1870                                                                   p->rdev->config.r100.reg_safe_bm,
1871                                                                   p->rdev->config.r100.reg_safe_bm_size,
1872                                                                   &r100_packet0_check);
1873                                 break;
1874                         case PACKET_TYPE2:
1875                                 break;
1876                         case PACKET_TYPE3:
1877                                 r = r100_packet3_check(p, &pkt);
1878                                 break;
1879                         default:
1880                                 DRM_ERROR("Unknown packet type %d !\n",
1881                                           pkt.type);
1882                                 return -EINVAL;
1883                 }
1884                 if (r) {
1885                         return r;
1886                 }
1887         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1888         return 0;
1889 }
1890
1891
1892 /*
1893  * Global GPU functions
1894  */
1895 void r100_errata(struct radeon_device *rdev)
1896 {
1897         rdev->pll_errata = 0;
1898
1899         if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1900                 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1901         }
1902
1903         if (rdev->family == CHIP_RV100 ||
1904             rdev->family == CHIP_RS100 ||
1905             rdev->family == CHIP_RS200) {
1906                 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1907         }
1908 }
1909
1910 /* Wait for vertical sync on primary CRTC */
1911 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1912 {
1913         uint32_t crtc_gen_cntl, tmp;
1914         int i;
1915
1916         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1917         if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1918             !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1919                 return;
1920         }
1921         /* Clear the CRTC_VBLANK_SAVE bit */
1922         WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1923         for (i = 0; i < rdev->usec_timeout; i++) {
1924                 tmp = RREG32(RADEON_CRTC_STATUS);
1925                 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1926                         return;
1927                 }
1928                 DRM_UDELAY(1);
1929         }
1930 }
1931
1932 /* Wait for vertical sync on secondary CRTC */
1933 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1934 {
1935         uint32_t crtc2_gen_cntl, tmp;
1936         int i;
1937
1938         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1939         if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1940             !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1941                 return;
1942
1943         /* Clear the CRTC_VBLANK_SAVE bit */
1944         WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1945         for (i = 0; i < rdev->usec_timeout; i++) {
1946                 tmp = RREG32(RADEON_CRTC2_STATUS);
1947                 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1948                         return;
1949                 }
1950                 DRM_UDELAY(1);
1951         }
1952 }
1953
1954 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1955 {
1956         unsigned i;
1957         uint32_t tmp;
1958
1959         for (i = 0; i < rdev->usec_timeout; i++) {
1960                 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1961                 if (tmp >= n) {
1962                         return 0;
1963                 }
1964                 DRM_UDELAY(1);
1965         }
1966         return -1;
1967 }
1968
1969 int r100_gui_wait_for_idle(struct radeon_device *rdev)
1970 {
1971         unsigned i;
1972         uint32_t tmp;
1973
1974         if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1975                 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1976                        " Bad things might happen.\n");
1977         }
1978         for (i = 0; i < rdev->usec_timeout; i++) {
1979                 tmp = RREG32(RADEON_RBBM_STATUS);
1980                 if (!(tmp & RADEON_RBBM_ACTIVE)) {
1981                         return 0;
1982                 }
1983                 DRM_UDELAY(1);
1984         }
1985         return -1;
1986 }
1987
1988 int r100_mc_wait_for_idle(struct radeon_device *rdev)
1989 {
1990         unsigned i;
1991         uint32_t tmp;
1992
1993         for (i = 0; i < rdev->usec_timeout; i++) {
1994                 /* read MC_STATUS */
1995                 tmp = RREG32(RADEON_MC_STATUS);
1996                 if (tmp & RADEON_MC_IDLE) {
1997                         return 0;
1998                 }
1999                 DRM_UDELAY(1);
2000         }
2001         return -1;
2002 }
2003
2004 void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
2005 {
2006         lockup->last_cp_rptr = cp->rptr;
2007         lockup->last_jiffies = jiffies;
2008 }
2009
2010 /**
2011  * r100_gpu_cp_is_lockup() - check if CP is lockup by recording information
2012  * @rdev:       radeon device structure
2013  * @lockup:     r100_gpu_lockup structure holding CP lockup tracking informations
2014  * @cp:         radeon_cp structure holding CP information
2015  *
2016  * We don't need to initialize the lockup tracking information as we will either
2017  * have CP rptr to a different value of jiffies wrap around which will force
2018  * initialization of the lockup tracking informations.
2019  *
2020  * A possible false positivie is if we get call after while and last_cp_rptr ==
2021  * the current CP rptr, even if it's unlikely it might happen. To avoid this
2022  * if the elapsed time since last call is bigger than 2 second than we return
2023  * false and update the tracking information. Due to this the caller must call
2024  * r100_gpu_cp_is_lockup several time in less than 2sec for lockup to be reported
2025  * the fencing code should be cautious about that.
2026  *
2027  * Caller should write to the ring to force CP to do something so we don't get
2028  * false positive when CP is just gived nothing to do.
2029  *
2030  **/
2031 bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
2032 {
2033         unsigned long cjiffies, elapsed;
2034
2035         cjiffies = jiffies;
2036         if (!time_after(cjiffies, lockup->last_jiffies)) {
2037                 /* likely a wrap around */
2038                 lockup->last_cp_rptr = cp->rptr;
2039                 lockup->last_jiffies = jiffies;
2040                 return false;
2041         }
2042         if (cp->rptr != lockup->last_cp_rptr) {
2043                 /* CP is still working no lockup */
2044                 lockup->last_cp_rptr = cp->rptr;
2045                 lockup->last_jiffies = jiffies;
2046                 return false;
2047         }
2048         elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies);
2049         if (elapsed >= 3000) {
2050                 /* very likely the improbable case where current
2051                  * rptr is equal to last recorded, a while ago, rptr
2052                  * this is more likely a false positive update tracking
2053                  * information which should force us to be recall at
2054                  * latter point
2055                  */
2056                 lockup->last_cp_rptr = cp->rptr;
2057                 lockup->last_jiffies = jiffies;
2058                 return false;
2059         }
2060         if (elapsed >= 1000) {
2061                 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
2062                 return true;
2063         }
2064         /* give a chance to the GPU ... */
2065         return false;
2066 }
2067
2068 bool r100_gpu_is_lockup(struct radeon_device *rdev)
2069 {
2070         u32 rbbm_status;
2071         int r;
2072
2073         rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2074         if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2075                 r100_gpu_lockup_update(&rdev->config.r100.lockup, &rdev->cp);
2076                 return false;
2077         }
2078         /* force CP activities */
2079         r = radeon_ring_lock(rdev, 2);
2080         if (!r) {
2081                 /* PACKET2 NOP */
2082                 radeon_ring_write(rdev, 0x80000000);
2083                 radeon_ring_write(rdev, 0x80000000);
2084                 radeon_ring_unlock_commit(rdev);
2085         }
2086         rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
2087         return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, &rdev->cp);
2088 }
2089
2090 void r100_bm_disable(struct radeon_device *rdev)
2091 {
2092         u32 tmp;
2093
2094         /* disable bus mastering */
2095         tmp = RREG32(R_000030_BUS_CNTL);
2096         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2097         mdelay(1);
2098         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2099         mdelay(1);
2100         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2101         tmp = RREG32(RADEON_BUS_CNTL);
2102         mdelay(1);
2103         pci_read_config_word(rdev->pdev, 0x4, (u16*)&tmp);
2104         pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB);
2105         mdelay(1);
2106 }
2107
2108 int r100_asic_reset(struct radeon_device *rdev)
2109 {
2110         struct r100_mc_save save;
2111         u32 status, tmp;
2112
2113         r100_mc_stop(rdev, &save);
2114         status = RREG32(R_000E40_RBBM_STATUS);
2115         if (!G_000E40_GUI_ACTIVE(status)) {
2116                 return 0;
2117         }
2118         status = RREG32(R_000E40_RBBM_STATUS);
2119         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2120         /* stop CP */
2121         WREG32(RADEON_CP_CSQ_CNTL, 0);
2122         tmp = RREG32(RADEON_CP_RB_CNTL);
2123         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2124         WREG32(RADEON_CP_RB_RPTR_WR, 0);
2125         WREG32(RADEON_CP_RB_WPTR, 0);
2126         WREG32(RADEON_CP_RB_CNTL, tmp);
2127         /* save PCI state */
2128         pci_save_state(rdev->pdev);
2129         /* disable bus mastering */
2130         r100_bm_disable(rdev);
2131         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2132                                         S_0000F0_SOFT_RESET_RE(1) |
2133                                         S_0000F0_SOFT_RESET_PP(1) |
2134                                         S_0000F0_SOFT_RESET_RB(1));
2135         RREG32(R_0000F0_RBBM_SOFT_RESET);
2136         mdelay(500);
2137         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2138         mdelay(1);
2139         status = RREG32(R_000E40_RBBM_STATUS);
2140         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2141         /* reset CP */
2142         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2143         RREG32(R_0000F0_RBBM_SOFT_RESET);
2144         mdelay(500);
2145         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2146         mdelay(1);
2147         status = RREG32(R_000E40_RBBM_STATUS);
2148         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2149         /* restore PCI & busmastering */
2150         pci_restore_state(rdev->pdev);
2151         r100_enable_bm(rdev);
2152         /* Check if GPU is idle */
2153         if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2154                 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2155                 dev_err(rdev->dev, "failed to reset GPU\n");
2156                 rdev->gpu_lockup = true;
2157                 return -1;
2158         }
2159         r100_mc_resume(rdev, &save);
2160         dev_info(rdev->dev, "GPU reset succeed\n");
2161         return 0;
2162 }
2163
2164 void r100_set_common_regs(struct radeon_device *rdev)
2165 {
2166         struct drm_device *dev = rdev->ddev;
2167         bool force_dac2 = false;
2168         u32 tmp;
2169
2170         /* set these so they don't interfere with anything */
2171         WREG32(RADEON_OV0_SCALE_CNTL, 0);
2172         WREG32(RADEON_SUBPIC_CNTL, 0);
2173         WREG32(RADEON_VIPH_CONTROL, 0);
2174         WREG32(RADEON_I2C_CNTL_1, 0);
2175         WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2176         WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2177         WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2178
2179         /* always set up dac2 on rn50 and some rv100 as lots
2180          * of servers seem to wire it up to a VGA port but
2181          * don't report it in the bios connector
2182          * table.
2183          */
2184         switch (dev->pdev->device) {
2185                 /* RN50 */
2186         case 0x515e:
2187         case 0x5969:
2188                 force_dac2 = true;
2189                 break;
2190                 /* RV100*/
2191         case 0x5159:
2192         case 0x515a:
2193                 /* DELL triple head servers */
2194                 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2195                     ((dev->pdev->subsystem_device == 0x016c) ||
2196                      (dev->pdev->subsystem_device == 0x016d) ||
2197                      (dev->pdev->subsystem_device == 0x016e) ||
2198                      (dev->pdev->subsystem_device == 0x016f) ||
2199                      (dev->pdev->subsystem_device == 0x0170) ||
2200                      (dev->pdev->subsystem_device == 0x017d) ||
2201                      (dev->pdev->subsystem_device == 0x017e) ||
2202                      (dev->pdev->subsystem_device == 0x0183) ||
2203                      (dev->pdev->subsystem_device == 0x018a) ||
2204                      (dev->pdev->subsystem_device == 0x019a)))
2205                         force_dac2 = true;
2206                 break;
2207         }
2208
2209         if (force_dac2) {
2210                 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2211                 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2212                 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2213
2214                 /* For CRT on DAC2, don't turn it on if BIOS didn't
2215                    enable it, even it's detected.
2216                 */
2217
2218                 /* force it to crtc0 */
2219                 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2220                 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2221                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2222
2223                 /* set up the TV DAC */
2224                 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2225                                  RADEON_TV_DAC_STD_MASK |
2226                                  RADEON_TV_DAC_RDACPD |
2227                                  RADEON_TV_DAC_GDACPD |
2228                                  RADEON_TV_DAC_BDACPD |
2229                                  RADEON_TV_DAC_BGADJ_MASK |
2230                                  RADEON_TV_DAC_DACADJ_MASK);
2231                 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2232                                 RADEON_TV_DAC_NHOLD |
2233                                 RADEON_TV_DAC_STD_PS2 |
2234                                 (0x58 << 16));
2235
2236                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2237                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2238                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2239         }
2240
2241         /* switch PM block to ACPI mode */
2242         tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2243         tmp &= ~RADEON_PM_MODE_SEL;
2244         WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2245
2246 }
2247
2248 /*
2249  * VRAM info
2250  */
2251 static void r100_vram_get_type(struct radeon_device *rdev)
2252 {
2253         uint32_t tmp;
2254
2255         rdev->mc.vram_is_ddr = false;
2256         if (rdev->flags & RADEON_IS_IGP)
2257                 rdev->mc.vram_is_ddr = true;
2258         else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2259                 rdev->mc.vram_is_ddr = true;
2260         if ((rdev->family == CHIP_RV100) ||
2261             (rdev->family == CHIP_RS100) ||
2262             (rdev->family == CHIP_RS200)) {
2263                 tmp = RREG32(RADEON_MEM_CNTL);
2264                 if (tmp & RV100_HALF_MODE) {
2265                         rdev->mc.vram_width = 32;
2266                 } else {
2267                         rdev->mc.vram_width = 64;
2268                 }
2269                 if (rdev->flags & RADEON_SINGLE_CRTC) {
2270                         rdev->mc.vram_width /= 4;
2271                         rdev->mc.vram_is_ddr = true;
2272                 }
2273         } else if (rdev->family <= CHIP_RV280) {
2274                 tmp = RREG32(RADEON_MEM_CNTL);
2275                 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2276                         rdev->mc.vram_width = 128;
2277                 } else {
2278                         rdev->mc.vram_width = 64;
2279                 }
2280         } else {
2281                 /* newer IGPs */
2282                 rdev->mc.vram_width = 128;
2283         }
2284 }
2285
2286 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2287 {
2288         u32 aper_size;
2289         u8 byte;
2290
2291         aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2292
2293         /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2294          * that is has the 2nd generation multifunction PCI interface
2295          */
2296         if (rdev->family == CHIP_RV280 ||
2297             rdev->family >= CHIP_RV350) {
2298                 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2299                        ~RADEON_HDP_APER_CNTL);
2300                 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2301                 return aper_size * 2;
2302         }
2303
2304         /* Older cards have all sorts of funny issues to deal with. First
2305          * check if it's a multifunction card by reading the PCI config
2306          * header type... Limit those to one aperture size
2307          */
2308         pci_read_config_byte(rdev->pdev, 0xe, &byte);
2309         if (byte & 0x80) {
2310                 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2311                 DRM_INFO("Limiting VRAM to one aperture\n");
2312                 return aper_size;
2313         }
2314
2315         /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2316          * have set it up. We don't write this as it's broken on some ASICs but
2317          * we expect the BIOS to have done the right thing (might be too optimistic...)
2318          */
2319         if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2320                 return aper_size * 2;
2321         return aper_size;
2322 }
2323
2324 void r100_vram_init_sizes(struct radeon_device *rdev)
2325 {
2326         u64 config_aper_size;
2327
2328         /* work out accessible VRAM */
2329         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
2330         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
2331         rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2332         /* FIXME we don't use the second aperture yet when we could use it */
2333         if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2334                 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2335         config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2336         if (rdev->flags & RADEON_IS_IGP) {
2337                 uint32_t tom;
2338                 /* read NB_TOM to get the amount of ram stolen for the GPU */
2339                 tom = RREG32(RADEON_NB_TOM);
2340                 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2341                 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2342                 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2343         } else {
2344                 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2345                 /* Some production boards of m6 will report 0
2346                  * if it's 8 MB
2347                  */
2348                 if (rdev->mc.real_vram_size == 0) {
2349                         rdev->mc.real_vram_size = 8192 * 1024;
2350                         WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2351                 }
2352                 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2353                  * Novell bug 204882 + along with lots of ubuntu ones
2354                  */
2355                 if (config_aper_size > rdev->mc.real_vram_size)
2356                         rdev->mc.mc_vram_size = config_aper_size;
2357                 else
2358                         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2359         }
2360 }
2361
2362 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2363 {
2364         uint32_t temp;
2365
2366         temp = RREG32(RADEON_CONFIG_CNTL);
2367         if (state == false) {
2368                 temp &= ~(1<<8);
2369                 temp |= (1<<9);
2370         } else {
2371                 temp &= ~(1<<9);
2372         }
2373         WREG32(RADEON_CONFIG_CNTL, temp);
2374 }
2375
2376 void r100_mc_init(struct radeon_device *rdev)
2377 {
2378         u64 base;
2379
2380         r100_vram_get_type(rdev);
2381         r100_vram_init_sizes(rdev);
2382         base = rdev->mc.aper_base;
2383         if (rdev->flags & RADEON_IS_IGP)
2384                 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2385         radeon_vram_location(rdev, &rdev->mc, base);
2386         if (!(rdev->flags & RADEON_IS_AGP))
2387                 radeon_gtt_location(rdev, &rdev->mc);
2388         radeon_update_bandwidth_info(rdev);
2389 }
2390
2391
2392 /*
2393  * Indirect registers accessor
2394  */
2395 void r100_pll_errata_after_index(struct radeon_device *rdev)
2396 {
2397         if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) {
2398                 return;
2399         }
2400         (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2401         (void)RREG32(RADEON_CRTC_GEN_CNTL);
2402 }
2403
2404 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2405 {
2406         /* This workarounds is necessary on RV100, RS100 and RS200 chips
2407          * or the chip could hang on a subsequent access
2408          */
2409         if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2410                 udelay(5000);
2411         }
2412
2413         /* This function is required to workaround a hardware bug in some (all?)
2414          * revisions of the R300.  This workaround should be called after every
2415          * CLOCK_CNTL_INDEX register access.  If not, register reads afterward
2416          * may not be correct.
2417          */
2418         if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2419                 uint32_t save, tmp;
2420
2421                 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2422                 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2423                 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2424                 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2425                 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2426         }
2427 }
2428
2429 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2430 {
2431         uint32_t data;
2432
2433         WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2434         r100_pll_errata_after_index(rdev);
2435         data = RREG32(RADEON_CLOCK_CNTL_DATA);
2436         r100_pll_errata_after_data(rdev);
2437         return data;
2438 }
2439
2440 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2441 {
2442         WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2443         r100_pll_errata_after_index(rdev);
2444         WREG32(RADEON_CLOCK_CNTL_DATA, v);
2445         r100_pll_errata_after_data(rdev);
2446 }
2447
2448 void r100_set_safe_registers(struct radeon_device *rdev)
2449 {
2450         if (ASIC_IS_RN50(rdev)) {
2451                 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2452                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2453         } else if (rdev->family < CHIP_R200) {
2454                 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2455                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2456         } else {
2457                 r200_set_safe_registers(rdev);
2458         }
2459 }
2460
2461 /*
2462  * Debugfs info
2463  */
2464 #if defined(CONFIG_DEBUG_FS)
2465 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2466 {
2467         struct drm_info_node *node = (struct drm_info_node *) m->private;
2468         struct drm_device *dev = node->minor->dev;
2469         struct radeon_device *rdev = dev->dev_private;
2470         uint32_t reg, value;
2471         unsigned i;
2472
2473         seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2474         seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2475         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2476         for (i = 0; i < 64; i++) {
2477                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2478                 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2479                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2480                 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2481                 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2482         }
2483         return 0;
2484 }
2485
2486 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2487 {
2488         struct drm_info_node *node = (struct drm_info_node *) m->private;
2489         struct drm_device *dev = node->minor->dev;
2490         struct radeon_device *rdev = dev->dev_private;
2491         uint32_t rdp, wdp;
2492         unsigned count, i, j;
2493
2494         radeon_ring_free_size(rdev);
2495         rdp = RREG32(RADEON_CP_RB_RPTR);
2496         wdp = RREG32(RADEON_CP_RB_WPTR);
2497         count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2498         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2499         seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2500         seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2501         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2502         seq_printf(m, "%u dwords in ring\n", count);
2503         for (j = 0; j <= count; j++) {
2504                 i = (rdp + j) & rdev->cp.ptr_mask;
2505                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2506         }
2507         return 0;
2508 }
2509
2510
2511 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2512 {
2513         struct drm_info_node *node = (struct drm_info_node *) m->private;
2514         struct drm_device *dev = node->minor->dev;
2515         struct radeon_device *rdev = dev->dev_private;
2516         uint32_t csq_stat, csq2_stat, tmp;
2517         unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2518         unsigned i;
2519
2520         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2521         seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2522         csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2523         csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2524         r_rptr = (csq_stat >> 0) & 0x3ff;
2525         r_wptr = (csq_stat >> 10) & 0x3ff;
2526         ib1_rptr = (csq_stat >> 20) & 0x3ff;
2527         ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2528         ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2529         ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2530         seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2531         seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2532         seq_printf(m, "Ring rptr %u\n", r_rptr);
2533         seq_printf(m, "Ring wptr %u\n", r_wptr);
2534         seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2535         seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2536         seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2537         seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2538         /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2539          * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2540         seq_printf(m, "Ring fifo:\n");
2541         for (i = 0; i < 256; i++) {
2542                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2543                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2544                 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2545         }
2546         seq_printf(m, "Indirect1 fifo:\n");
2547         for (i = 256; i <= 512; i++) {
2548                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2549                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2550                 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2551         }
2552         seq_printf(m, "Indirect2 fifo:\n");
2553         for (i = 640; i < ib1_wptr; i++) {
2554                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2555                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2556                 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2557         }
2558         return 0;
2559 }
2560
2561 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2562 {
2563         struct drm_info_node *node = (struct drm_info_node *) m->private;
2564         struct drm_device *dev = node->minor->dev;
2565         struct radeon_device *rdev = dev->dev_private;
2566         uint32_t tmp;
2567
2568         tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2569         seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2570         tmp = RREG32(RADEON_MC_FB_LOCATION);
2571         seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2572         tmp = RREG32(RADEON_BUS_CNTL);
2573         seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2574         tmp = RREG32(RADEON_MC_AGP_LOCATION);
2575         seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2576         tmp = RREG32(RADEON_AGP_BASE);
2577         seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2578         tmp = RREG32(RADEON_HOST_PATH_CNTL);
2579         seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2580         tmp = RREG32(0x01D0);
2581         seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2582         tmp = RREG32(RADEON_AIC_LO_ADDR);
2583         seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2584         tmp = RREG32(RADEON_AIC_HI_ADDR);
2585         seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2586         tmp = RREG32(0x01E4);
2587         seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2588         return 0;
2589 }
2590
2591 static struct drm_info_list r100_debugfs_rbbm_list[] = {
2592         {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2593 };
2594
2595 static struct drm_info_list r100_debugfs_cp_list[] = {
2596         {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2597         {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2598 };
2599
2600 static struct drm_info_list r100_debugfs_mc_info_list[] = {
2601         {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2602 };
2603 #endif
2604
2605 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2606 {
2607 #if defined(CONFIG_DEBUG_FS)
2608         return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2609 #else
2610         return 0;
2611 #endif
2612 }
2613
2614 int r100_debugfs_cp_init(struct radeon_device *rdev)
2615 {
2616 #if defined(CONFIG_DEBUG_FS)
2617         return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2618 #else
2619         return 0;
2620 #endif
2621 }
2622
2623 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2624 {
2625 #if defined(CONFIG_DEBUG_FS)
2626         return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2627 #else
2628         return 0;
2629 #endif
2630 }
2631
2632 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2633                          uint32_t tiling_flags, uint32_t pitch,
2634                          uint32_t offset, uint32_t obj_size)
2635 {
2636         int surf_index = reg * 16;
2637         int flags = 0;
2638
2639         /* r100/r200 divide by 16 */
2640         if (rdev->family < CHIP_R300)
2641                 flags = pitch / 16;
2642         else
2643                 flags = pitch / 8;
2644
2645         if (rdev->family <= CHIP_RS200) {
2646                 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2647                                  == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2648                         flags |= RADEON_SURF_TILE_COLOR_BOTH;
2649                 if (tiling_flags & RADEON_TILING_MACRO)
2650                         flags |= RADEON_SURF_TILE_COLOR_MACRO;
2651         } else if (rdev->family <= CHIP_RV280) {
2652                 if (tiling_flags & (RADEON_TILING_MACRO))
2653                         flags |= R200_SURF_TILE_COLOR_MACRO;
2654                 if (tiling_flags & RADEON_TILING_MICRO)
2655                         flags |= R200_SURF_TILE_COLOR_MICRO;
2656         } else {
2657                 if (tiling_flags & RADEON_TILING_MACRO)
2658                         flags |= R300_SURF_TILE_MACRO;
2659                 if (tiling_flags & RADEON_TILING_MICRO)
2660                         flags |= R300_SURF_TILE_MICRO;
2661         }
2662
2663         if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2664                 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2665         if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2666                 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2667
2668         DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2669         WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2670         WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2671         WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2672         return 0;
2673 }
2674
2675 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2676 {
2677         int surf_index = reg * 16;
2678         WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2679 }
2680
2681 void r100_bandwidth_update(struct radeon_device *rdev)
2682 {
2683         fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2684         fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2685         fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2686         uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2687         fixed20_12 memtcas_ff[8] = {
2688                 fixed_init(1),
2689                 fixed_init(2),
2690                 fixed_init(3),
2691                 fixed_init(0),
2692                 fixed_init_half(1),
2693                 fixed_init_half(2),
2694                 fixed_init(0),
2695         };
2696         fixed20_12 memtcas_rs480_ff[8] = {
2697                 fixed_init(0),
2698                 fixed_init(1),
2699                 fixed_init(2),
2700                 fixed_init(3),
2701                 fixed_init(0),
2702                 fixed_init_half(1),
2703                 fixed_init_half(2),
2704                 fixed_init_half(3),
2705         };
2706         fixed20_12 memtcas2_ff[8] = {
2707                 fixed_init(0),
2708                 fixed_init(1),
2709                 fixed_init(2),
2710                 fixed_init(3),
2711                 fixed_init(4),
2712                 fixed_init(5),
2713                 fixed_init(6),
2714                 fixed_init(7),
2715         };
2716         fixed20_12 memtrbs[8] = {
2717                 fixed_init(1),
2718                 fixed_init_half(1),
2719                 fixed_init(2),
2720                 fixed_init_half(2),
2721                 fixed_init(3),
2722                 fixed_init_half(3),
2723                 fixed_init(4),
2724                 fixed_init_half(4)
2725         };
2726         fixed20_12 memtrbs_r4xx[8] = {
2727                 fixed_init(4),
2728                 fixed_init(5),
2729                 fixed_init(6),
2730                 fixed_init(7),
2731                 fixed_init(8),
2732                 fixed_init(9),
2733                 fixed_init(10),
2734                 fixed_init(11)
2735         };
2736         fixed20_12 min_mem_eff;
2737         fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2738         fixed20_12 cur_latency_mclk, cur_latency_sclk;
2739         fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2740                 disp_drain_rate2, read_return_rate;
2741         fixed20_12 time_disp1_drop_priority;
2742         int c;
2743         int cur_size = 16;       /* in octawords */
2744         int critical_point = 0, critical_point2;
2745 /*      uint32_t read_return_rate, time_disp1_drop_priority; */
2746         int stop_req, max_stop_req;
2747         struct drm_display_mode *mode1 = NULL;
2748         struct drm_display_mode *mode2 = NULL;
2749         uint32_t pixel_bytes1 = 0;
2750         uint32_t pixel_bytes2 = 0;
2751
2752         radeon_update_display_priority(rdev);
2753
2754         if (rdev->mode_info.crtcs[0]->base.enabled) {
2755                 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2756                 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2757         }
2758         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2759                 if (rdev->mode_info.crtcs[1]->base.enabled) {
2760                         mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2761                         pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2762                 }
2763         }
2764
2765         min_mem_eff.full = rfixed_const_8(0);
2766         /* get modes */
2767         if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2768                 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2769                 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2770                 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2771                 /* check crtc enables */
2772                 if (mode2)
2773                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2774                 if (mode1)
2775                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2776                 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2777         }
2778
2779         /*
2780          * determine is there is enough bw for current mode
2781          */
2782         sclk_ff = rdev->pm.sclk;
2783         mclk_ff = rdev->pm.mclk;
2784
2785         temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2786         temp_ff.full = rfixed_const(temp);
2787         mem_bw.full = rfixed_mul(mclk_ff, temp_ff);
2788
2789         pix_clk.full = 0;
2790         pix_clk2.full = 0;
2791         peak_disp_bw.full = 0;
2792         if (mode1) {
2793                 temp_ff.full = rfixed_const(1000);
2794                 pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */
2795                 pix_clk.full = rfixed_div(pix_clk, temp_ff);
2796                 temp_ff.full = rfixed_const(pixel_bytes1);
2797                 peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff);
2798         }
2799         if (mode2) {
2800                 temp_ff.full = rfixed_const(1000);
2801                 pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */
2802                 pix_clk2.full = rfixed_div(pix_clk2, temp_ff);
2803                 temp_ff.full = rfixed_const(pixel_bytes2);
2804                 peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff);
2805         }
2806
2807         mem_bw.full = rfixed_mul(mem_bw, min_mem_eff);
2808         if (peak_disp_bw.full >= mem_bw.full) {
2809                 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2810                           "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2811         }
2812
2813         /*  Get values from the EXT_MEM_CNTL register...converting its contents. */
2814         temp = RREG32(RADEON_MEM_TIMING_CNTL);
2815         if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2816                 mem_trcd = ((temp >> 2) & 0x3) + 1;
2817                 mem_trp  = ((temp & 0x3)) + 1;
2818                 mem_tras = ((temp & 0x70) >> 4) + 1;
2819         } else if (rdev->family == CHIP_R300 ||
2820                    rdev->family == CHIP_R350) { /* r300, r350 */
2821                 mem_trcd = (temp & 0x7) + 1;
2822                 mem_trp = ((temp >> 8) & 0x7) + 1;
2823                 mem_tras = ((temp >> 11) & 0xf) + 4;
2824         } else if (rdev->family == CHIP_RV350 ||
2825                    rdev->family <= CHIP_RV380) {
2826                 /* rv3x0 */
2827                 mem_trcd = (temp & 0x7) + 3;
2828                 mem_trp = ((temp >> 8) & 0x7) + 3;
2829                 mem_tras = ((temp >> 11) & 0xf) + 6;
2830         } else if (rdev->family == CHIP_R420 ||
2831                    rdev->family == CHIP_R423 ||
2832                    rdev->family == CHIP_RV410) {
2833                 /* r4xx */
2834                 mem_trcd = (temp & 0xf) + 3;
2835                 if (mem_trcd > 15)
2836                         mem_trcd = 15;
2837                 mem_trp = ((temp >> 8) & 0xf) + 3;
2838                 if (mem_trp > 15)
2839                         mem_trp = 15;
2840                 mem_tras = ((temp >> 12) & 0x1f) + 6;
2841                 if (mem_tras > 31)
2842                         mem_tras = 31;
2843         } else { /* RV200, R200 */
2844                 mem_trcd = (temp & 0x7) + 1;
2845                 mem_trp = ((temp >> 8) & 0x7) + 1;
2846                 mem_tras = ((temp >> 12) & 0xf) + 4;
2847         }
2848         /* convert to FF */
2849         trcd_ff.full = rfixed_const(mem_trcd);
2850         trp_ff.full = rfixed_const(mem_trp);
2851         tras_ff.full = rfixed_const(mem_tras);
2852
2853         /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2854         temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2855         data = (temp & (7 << 20)) >> 20;
2856         if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2857                 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2858                         tcas_ff = memtcas_rs480_ff[data];
2859                 else
2860                         tcas_ff = memtcas_ff[data];
2861         } else
2862                 tcas_ff = memtcas2_ff[data];
2863
2864         if (rdev->family == CHIP_RS400 ||
2865             rdev->family == CHIP_RS480) {
2866                 /* extra cas latency stored in bits 23-25 0-4 clocks */
2867                 data = (temp >> 23) & 0x7;
2868                 if (data < 5)
2869                         tcas_ff.full += rfixed_const(data);
2870         }
2871
2872         if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2873                 /* on the R300, Tcas is included in Trbs.
2874                  */
2875                 temp = RREG32(RADEON_MEM_CNTL);
2876                 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2877                 if (data == 1) {
2878                         if (R300_MEM_USE_CD_CH_ONLY & temp) {
2879                                 temp = RREG32(R300_MC_IND_INDEX);
2880                                 temp &= ~R300_MC_IND_ADDR_MASK;
2881                                 temp |= R300_MC_READ_CNTL_CD_mcind;
2882                                 WREG32(R300_MC_IND_INDEX, temp);
2883                                 temp = RREG32(R300_MC_IND_DATA);
2884                                 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2885                         } else {
2886                                 temp = RREG32(R300_MC_READ_CNTL_AB);
2887                                 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2888                         }
2889                 } else {
2890                         temp = RREG32(R300_MC_READ_CNTL_AB);
2891                         data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2892                 }
2893                 if (rdev->family == CHIP_RV410 ||
2894                     rdev->family == CHIP_R420 ||
2895                     rdev->family == CHIP_R423)
2896                         trbs_ff = memtrbs_r4xx[data];
2897                 else
2898                         trbs_ff = memtrbs[data];
2899                 tcas_ff.full += trbs_ff.full;
2900         }
2901
2902         sclk_eff_ff.full = sclk_ff.full;
2903
2904         if (rdev->flags & RADEON_IS_AGP) {
2905                 fixed20_12 agpmode_ff;
2906                 agpmode_ff.full = rfixed_const(radeon_agpmode);
2907                 temp_ff.full = rfixed_const_666(16);
2908                 sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff);
2909         }
2910         /* TODO PCIE lanes may affect this - agpmode == 16?? */
2911
2912         if (ASIC_IS_R300(rdev)) {
2913                 sclk_delay_ff.full = rfixed_const(250);
2914         } else {
2915                 if ((rdev->family == CHIP_RV100) ||
2916                     rdev->flags & RADEON_IS_IGP) {
2917                         if (rdev->mc.vram_is_ddr)
2918                                 sclk_delay_ff.full = rfixed_const(41);
2919                         else
2920                                 sclk_delay_ff.full = rfixed_const(33);
2921                 } else {
2922                         if (rdev->mc.vram_width == 128)
2923                                 sclk_delay_ff.full = rfixed_const(57);
2924                         else
2925                                 sclk_delay_ff.full = rfixed_const(41);
2926                 }
2927         }
2928
2929         mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff);
2930
2931         if (rdev->mc.vram_is_ddr) {
2932                 if (rdev->mc.vram_width == 32) {
2933                         k1.full = rfixed_const(40);
2934                         c  = 3;
2935                 } else {
2936                         k1.full = rfixed_const(20);
2937                         c  = 1;
2938                 }
2939         } else {
2940                 k1.full = rfixed_const(40);
2941                 c  = 3;
2942         }
2943
2944         temp_ff.full = rfixed_const(2);
2945         mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff);
2946         temp_ff.full = rfixed_const(c);
2947         mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff);
2948         temp_ff.full = rfixed_const(4);
2949         mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff);
2950         mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff);
2951         mc_latency_mclk.full += k1.full;
2952
2953         mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff);
2954         mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff);
2955
2956         /*
2957           HW cursor time assuming worst case of full size colour cursor.
2958         */
2959         temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
2960         temp_ff.full += trcd_ff.full;
2961         if (temp_ff.full < tras_ff.full)
2962                 temp_ff.full = tras_ff.full;
2963         cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff);
2964
2965         temp_ff.full = rfixed_const(cur_size);
2966         cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff);
2967         /*
2968           Find the total latency for the display data.
2969         */
2970         disp_latency_overhead.full = rfixed_const(8);
2971         disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff);
2972         mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2973         mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
2974
2975         if (mc_latency_mclk.full > mc_latency_sclk.full)
2976                 disp_latency.full = mc_latency_mclk.full;
2977         else
2978                 disp_latency.full = mc_latency_sclk.full;
2979
2980         /* setup Max GRPH_STOP_REQ default value */
2981         if (ASIC_IS_RV100(rdev))
2982                 max_stop_req = 0x5c;
2983         else
2984                 max_stop_req = 0x7c;
2985
2986         if (mode1) {
2987                 /*  CRTC1
2988                     Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2989                     GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2990                 */
2991                 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
2992
2993                 if (stop_req > max_stop_req)
2994                         stop_req = max_stop_req;
2995
2996                 /*
2997                   Find the drain rate of the display buffer.
2998                 */
2999                 temp_ff.full = rfixed_const((16/pixel_bytes1));
3000                 disp_drain_rate.full = rfixed_div(pix_clk, temp_ff);
3001
3002                 /*
3003                   Find the critical point of the display buffer.
3004                 */
3005                 crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency);
3006                 crit_point_ff.full += rfixed_const_half(0);
3007
3008                 critical_point = rfixed_trunc(crit_point_ff);
3009
3010                 if (rdev->disp_priority == 2) {
3011                         critical_point = 0;
3012                 }
3013
3014                 /*
3015                   The critical point should never be above max_stop_req-4.  Setting
3016                   GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3017                 */
3018                 if (max_stop_req - critical_point < 4)
3019                         critical_point = 0;
3020
3021                 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3022                         /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3023                         critical_point = 0x10;
3024                 }
3025
3026                 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3027                 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3028                 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3029                 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3030                 if ((rdev->family == CHIP_R350) &&
3031                     (stop_req > 0x15)) {
3032                         stop_req -= 0x10;
3033                 }
3034                 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3035                 temp |= RADEON_GRPH_BUFFER_SIZE;
3036                 temp &= ~(RADEON_GRPH_CRITICAL_CNTL   |
3037                           RADEON_GRPH_CRITICAL_AT_SOF |
3038                           RADEON_GRPH_STOP_CNTL);
3039                 /*
3040                   Write the result into the register.
3041                 */
3042                 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3043                                                        (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3044
3045 #if 0
3046                 if ((rdev->family == CHIP_RS400) ||
3047                     (rdev->family == CHIP_RS480)) {
3048                         /* attempt to program RS400 disp regs correctly ??? */
3049                         temp = RREG32(RS400_DISP1_REG_CNTL);
3050                         temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3051                                   RS400_DISP1_STOP_REQ_LEVEL_MASK);
3052                         WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3053                                                        (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3054                                                        (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3055                         temp = RREG32(RS400_DMIF_MEM_CNTL1);
3056                         temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3057                                   RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3058                         WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3059                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3060                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3061                 }
3062 #endif
3063
3064                 DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
3065                           /*      (unsigned int)info->SavedReg->grph_buffer_cntl, */
3066                           (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3067         }
3068
3069         if (mode2) {
3070                 u32 grph2_cntl;
3071                 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3072
3073                 if (stop_req > max_stop_req)
3074                         stop_req = max_stop_req;
3075
3076                 /*
3077                   Find the drain rate of the display buffer.
3078                 */
3079                 temp_ff.full = rfixed_const((16/pixel_bytes2));
3080                 disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff);
3081
3082                 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3083                 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3084                 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3085                 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3086                 if ((rdev->family == CHIP_R350) &&
3087                     (stop_req > 0x15)) {
3088                         stop_req -= 0x10;
3089                 }
3090                 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3091                 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3092                 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL   |
3093                           RADEON_GRPH_CRITICAL_AT_SOF |
3094                           RADEON_GRPH_STOP_CNTL);
3095
3096                 if ((rdev->family == CHIP_RS100) ||
3097                     (rdev->family == CHIP_RS200))
3098                         critical_point2 = 0;
3099                 else {
3100                         temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3101                         temp_ff.full = rfixed_const(temp);
3102                         temp_ff.full = rfixed_mul(mclk_ff, temp_ff);
3103                         if (sclk_ff.full < temp_ff.full)
3104                                 temp_ff.full = sclk_ff.full;
3105
3106                         read_return_rate.full = temp_ff.full;
3107
3108                         if (mode1) {
3109                                 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3110                                 time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff);
3111                         } else {
3112                                 time_disp1_drop_priority.full = 0;
3113                         }
3114                         crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3115                         crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2);
3116                         crit_point_ff.full += rfixed_const_half(0);
3117
3118                         critical_point2 = rfixed_trunc(crit_point_ff);
3119
3120                         if (rdev->disp_priority == 2) {
3121                                 critical_point2 = 0;
3122                         }
3123
3124                         if (max_stop_req - critical_point2 < 4)
3125                                 critical_point2 = 0;
3126
3127                 }
3128
3129                 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3130                         /* some R300 cards have problem with this set to 0 */
3131                         critical_point2 = 0x10;
3132                 }
3133
3134                 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3135                                                   (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3136
3137                 if ((rdev->family == CHIP_RS400) ||
3138                     (rdev->family == CHIP_RS480)) {
3139 #if 0
3140                         /* attempt to program RS400 disp2 regs correctly ??? */
3141                         temp = RREG32(RS400_DISP2_REQ_CNTL1);
3142                         temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3143                                   RS400_DISP2_STOP_REQ_LEVEL_MASK);
3144                         WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3145                                                        (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3146                                                        (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3147                         temp = RREG32(RS400_DISP2_REQ_CNTL2);
3148                         temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3149                                   RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3150                         WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3151                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3152                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3153 #endif
3154                         WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3155                         WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3156                         WREG32(RS400_DMIF_MEM_CNTL1,  0x29CA71DC);
3157                         WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3158                 }
3159
3160                 DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
3161                           (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3162         }
3163 }
3164
3165 static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
3166 {
3167         DRM_ERROR("pitch                      %d\n", t->pitch);
3168         DRM_ERROR("use_pitch                  %d\n", t->use_pitch);
3169         DRM_ERROR("width                      %d\n", t->width);
3170         DRM_ERROR("width_11                   %d\n", t->width_11);
3171         DRM_ERROR("height                     %d\n", t->height);
3172         DRM_ERROR("height_11                  %d\n", t->height_11);
3173         DRM_ERROR("num levels                 %d\n", t->num_levels);
3174         DRM_ERROR("depth                      %d\n", t->txdepth);
3175         DRM_ERROR("bpp                        %d\n", t->cpp);
3176         DRM_ERROR("coordinate type            %d\n", t->tex_coord_type);
3177         DRM_ERROR("width round to power of 2  %d\n", t->roundup_w);
3178         DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
3179         DRM_ERROR("compress format            %d\n", t->compress_format);
3180 }
3181
3182 static int r100_cs_track_cube(struct radeon_device *rdev,
3183                               struct r100_cs_track *track, unsigned idx)
3184 {
3185         unsigned face, w, h;
3186         struct radeon_bo *cube_robj;
3187         unsigned long size;
3188
3189         for (face = 0; face < 5; face++) {
3190                 cube_robj = track->textures[idx].cube_info[face].robj;
3191                 w = track->textures[idx].cube_info[face].width;
3192                 h = track->textures[idx].cube_info[face].height;
3193
3194                 size = w * h;
3195                 size *= track->textures[idx].cpp;
3196
3197                 size += track->textures[idx].cube_info[face].offset;
3198
3199                 if (size > radeon_bo_size(cube_robj)) {
3200                         DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
3201                                   size, radeon_bo_size(cube_robj));
3202                         r100_cs_track_texture_print(&track->textures[idx]);
3203                         return -1;
3204                 }
3205         }
3206         return 0;
3207 }
3208
3209 static int r100_track_compress_size(int compress_format, int w, int h)
3210 {
3211         int block_width, block_height, block_bytes;
3212         int wblocks, hblocks;
3213         int min_wblocks;
3214         int sz;
3215
3216         block_width = 4;
3217         block_height = 4;
3218
3219         switch (compress_format) {
3220         case R100_TRACK_COMP_DXT1:
3221                 block_bytes = 8;
3222                 min_wblocks = 4;
3223                 break;
3224         default:
3225         case R100_TRACK_COMP_DXT35:
3226                 block_bytes = 16;
3227                 min_wblocks = 2;
3228                 break;
3229         }
3230
3231         hblocks = (h + block_height - 1) / block_height;
3232         wblocks = (w + block_width - 1) / block_width;
3233         if (wblocks < min_wblocks)
3234                 wblocks = min_wblocks;
3235         sz = wblocks * hblocks * block_bytes;
3236         return sz;
3237 }
3238
3239 static int r100_cs_track_texture_check(struct radeon_device *rdev,
3240                                        struct r100_cs_track *track)
3241 {
3242         struct radeon_bo *robj;
3243         unsigned long size;
3244         unsigned u, i, w, h, d;
3245         int ret;
3246
3247         for (u = 0; u < track->num_texture; u++) {
3248                 if (!track->textures[u].enabled)
3249                         continue;
3250                 robj = track->textures[u].robj;
3251                 if (robj == NULL) {
3252                         DRM_ERROR("No texture bound to unit %u\n", u);
3253                         return -EINVAL;
3254                 }
3255                 size = 0;
3256                 for (i = 0; i <= track->textures[u].num_levels; i++) {
3257                         if (track->textures[u].use_pitch) {
3258                                 if (rdev->family < CHIP_R300)
3259                                         w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
3260                                 else
3261                                         w = track->textures[u].pitch / (1 << i);
3262                         } else {
3263                                 w = track->textures[u].width;
3264                                 if (rdev->family >= CHIP_RV515)
3265                                         w |= track->textures[u].width_11;
3266                                 w = w / (1 << i);
3267                                 if (track->textures[u].roundup_w)
3268                                         w = roundup_pow_of_two(w);
3269                         }
3270                         h = track->textures[u].height;
3271                         if (rdev->family >= CHIP_RV515)
3272                                 h |= track->textures[u].height_11;
3273                         h = h / (1 << i);
3274                         if (track->textures[u].roundup_h)
3275                                 h = roundup_pow_of_two(h);
3276                         if (track->textures[u].tex_coord_type == 1) {
3277                                 d = (1 << track->textures[u].txdepth) / (1 << i);
3278                                 if (!d)
3279                                         d = 1;
3280                         } else {
3281                                 d = 1;
3282                         }
3283                         if (track->textures[u].compress_format) {
3284
3285                                 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
3286                                 /* compressed textures are block based */
3287                         } else
3288                                 size += w * h * d;
3289                 }
3290                 size *= track->textures[u].cpp;
3291
3292                 switch (track->textures[u].tex_coord_type) {
3293                 case 0:
3294                 case 1:
3295                         break;
3296                 case 2:
3297                         if (track->separate_cube) {
3298                                 ret = r100_cs_track_cube(rdev, track, u);
3299                                 if (ret)
3300                                         return ret;
3301                         } else
3302                                 size *= 6;
3303                         break;
3304                 default:
3305                         DRM_ERROR("Invalid texture coordinate type %u for unit "
3306                                   "%u\n", track->textures[u].tex_coord_type, u);
3307                         return -EINVAL;
3308                 }
3309                 if (size > radeon_bo_size(robj)) {
3310                         DRM_ERROR("Texture of unit %u needs %lu bytes but is "
3311                                   "%lu\n", u, size, radeon_bo_size(robj));
3312                         r100_cs_track_texture_print(&track->textures[u]);
3313                         return -EINVAL;
3314                 }
3315         }
3316         return 0;
3317 }
3318
3319 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
3320 {
3321         unsigned i;
3322         unsigned long size;
3323         unsigned prim_walk;
3324         unsigned nverts;
3325
3326         for (i = 0; i < track->num_cb; i++) {
3327                 if (track->cb[i].robj == NULL) {
3328                         if (!(track->fastfill || track->color_channel_mask ||
3329                               track->blend_read_enable)) {
3330                                 continue;
3331                         }
3332                         DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
3333                         return -EINVAL;
3334                 }
3335                 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
3336                 size += track->cb[i].offset;
3337                 if (size > radeon_bo_size(track->cb[i].robj)) {
3338                         DRM_ERROR("[drm] Buffer too small for color buffer %d "
3339                                   "(need %lu have %lu) !\n", i, size,
3340                                   radeon_bo_size(track->cb[i].robj));
3341                         DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
3342                                   i, track->cb[i].pitch, track->cb[i].cpp,
3343                                   track->cb[i].offset, track->maxy);
3344                         return -EINVAL;
3345                 }
3346         }
3347         if (track->z_enabled) {
3348                 if (track->zb.robj == NULL) {
3349                         DRM_ERROR("[drm] No buffer for z buffer !\n");
3350                         return -EINVAL;
3351                 }
3352                 size = track->zb.pitch * track->zb.cpp * track->maxy;
3353                 size += track->zb.offset;
3354                 if (size > radeon_bo_size(track->zb.robj)) {
3355                         DRM_ERROR("[drm] Buffer too small for z buffer "
3356                                   "(need %lu have %lu) !\n", size,
3357                                   radeon_bo_size(track->zb.robj));
3358                         DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
3359                                   track->zb.pitch, track->zb.cpp,
3360                                   track->zb.offset, track->maxy);
3361                         return -EINVAL;
3362                 }
3363         }
3364         prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
3365         if (track->vap_vf_cntl & (1 << 14)) {
3366                 nverts = track->vap_alt_nverts;
3367         } else {
3368                 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
3369         }
3370         switch (prim_walk) {
3371         case 1:
3372                 for (i = 0; i < track->num_arrays; i++) {
3373                         size = track->arrays[i].esize * track->max_indx * 4;
3374                         if (track->arrays[i].robj == NULL) {
3375                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3376                                           "bound\n", prim_walk, i);
3377                                 return -EINVAL;
3378                         }
3379                         if (size > radeon_bo_size(track->arrays[i].robj)) {
3380                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3381                                         "need %lu dwords have %lu dwords\n",
3382                                         prim_walk, i, size >> 2,
3383                                         radeon_bo_size(track->arrays[i].robj)
3384                                         >> 2);
3385                                 DRM_ERROR("Max indices %u\n", track->max_indx);
3386                                 return -EINVAL;
3387                         }
3388                 }
3389                 break;
3390         case 2:
3391                 for (i = 0; i < track->num_arrays; i++) {
3392                         size = track->arrays[i].esize * (nverts - 1) * 4;
3393                         if (track->arrays[i].robj == NULL) {
3394                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3395                                           "bound\n", prim_walk, i);
3396                                 return -EINVAL;
3397                         }
3398                         if (size > radeon_bo_size(track->arrays[i].robj)) {
3399                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3400                                         "need %lu dwords have %lu dwords\n",
3401                                         prim_walk, i, size >> 2,
3402                                         radeon_bo_size(track->arrays[i].robj)
3403                                         >> 2);
3404                                 return -EINVAL;
3405                         }
3406                 }
3407                 break;
3408         case 3:
3409                 size = track->vtx_size * nverts;
3410                 if (size != track->immd_dwords) {
3411                         DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
3412                                   track->immd_dwords, size);
3413                         DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
3414                                   nverts, track->vtx_size);
3415                         return -EINVAL;
3416                 }
3417                 break;
3418         default:
3419                 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3420                           prim_walk);
3421                 return -EINVAL;
3422         }
3423         return r100_cs_track_texture_check(rdev, track);
3424 }
3425
3426 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
3427 {
3428         unsigned i, face;
3429
3430         if (rdev->family < CHIP_R300) {
3431                 track->num_cb = 1;
3432                 if (rdev->family <= CHIP_RS200)
3433                         track->num_texture = 3;
3434                 else
3435                         track->num_texture = 6;
3436                 track->maxy = 2048;
3437                 track->separate_cube = 1;
3438         } else {
3439                 track->num_cb = 4;
3440                 track->num_texture = 16;
3441                 track->maxy = 4096;
3442                 track->separate_cube = 0;
3443         }
3444
3445         for (i = 0; i < track->num_cb; i++) {
3446                 track->cb[i].robj = NULL;
3447                 track->cb[i].pitch = 8192;
3448                 track->cb[i].cpp = 16;
3449                 track->cb[i].offset = 0;
3450         }
3451         track->z_enabled = true;
3452         track->zb.robj = NULL;
3453         track->zb.pitch = 8192;
3454         track->zb.cpp = 4;
3455         track->zb.offset = 0;
3456         track->vtx_size = 0x7F;
3457         track->immd_dwords = 0xFFFFFFFFUL;
3458         track->num_arrays = 11;
3459         track->max_indx = 0x00FFFFFFUL;
3460         for (i = 0; i < track->num_arrays; i++) {
3461                 track->arrays[i].robj = NULL;
3462                 track->arrays[i].esize = 0x7F;
3463         }
3464         for (i = 0; i < track->num_texture; i++) {
3465                 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
3466                 track->textures[i].pitch = 16536;
3467                 track->textures[i].width = 16536;
3468                 track->textures[i].height = 16536;
3469                 track->textures[i].width_11 = 1 << 11;
3470                 track->textures[i].height_11 = 1 << 11;
3471                 track->textures[i].num_levels = 12;
3472                 if (rdev->family <= CHIP_RS200) {
3473                         track->textures[i].tex_coord_type = 0;
3474                         track->textures[i].txdepth = 0;
3475                 } else {
3476                         track->textures[i].txdepth = 16;
3477                         track->textures[i].tex_coord_type = 1;
3478                 }
3479                 track->textures[i].cpp = 64;
3480                 track->textures[i].robj = NULL;
3481                 /* CS IB emission code makes sure texture unit are disabled */
3482                 track->textures[i].enabled = false;
3483                 track->textures[i].roundup_w = true;
3484                 track->textures[i].roundup_h = true;
3485                 if (track->separate_cube)
3486                         for (face = 0; face < 5; face++) {
3487                                 track->textures[i].cube_info[face].robj = NULL;
3488                                 track->textures[i].cube_info[face].width = 16536;
3489                                 track->textures[i].cube_info[face].height = 16536;
3490                                 track->textures[i].cube_info[face].offset = 0;
3491                         }
3492         }
3493 }
3494
3495 int r100_ring_test(struct radeon_device *rdev)
3496 {
3497         uint32_t scratch;
3498         uint32_t tmp = 0;
3499         unsigned i;
3500         int r;
3501
3502         r = radeon_scratch_get(rdev, &scratch);
3503         if (r) {
3504                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3505                 return r;
3506         }
3507         WREG32(scratch, 0xCAFEDEAD);
3508         r = radeon_ring_lock(rdev, 2);
3509         if (r) {
3510                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3511                 radeon_scratch_free(rdev, scratch);
3512                 return r;
3513         }
3514         radeon_ring_write(rdev, PACKET0(scratch, 0));
3515         radeon_ring_write(rdev, 0xDEADBEEF);
3516         radeon_ring_unlock_commit(rdev);
3517         for (i = 0; i < rdev->usec_timeout; i++) {
3518                 tmp = RREG32(scratch);
3519                 if (tmp == 0xDEADBEEF) {
3520                         break;
3521                 }
3522                 DRM_UDELAY(1);
3523         }
3524         if (i < rdev->usec_timeout) {
3525                 DRM_INFO("ring test succeeded in %d usecs\n", i);
3526         } else {
3527                 DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
3528                           scratch, tmp);
3529                 r = -EINVAL;
3530         }
3531         radeon_scratch_free(rdev, scratch);
3532         return r;
3533 }
3534
3535 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3536 {
3537         radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3538         radeon_ring_write(rdev, ib->gpu_addr);
3539         radeon_ring_write(rdev, ib->length_dw);
3540 }
3541
3542 int r100_ib_test(struct radeon_device *rdev)
3543 {
3544         struct radeon_ib *ib;
3545         uint32_t scratch;
3546         uint32_t tmp = 0;
3547         unsigned i;
3548         int r;
3549
3550         r = radeon_scratch_get(rdev, &scratch);
3551         if (r) {
3552                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3553                 return r;
3554         }
3555         WREG32(scratch, 0xCAFEDEAD);
3556         r = radeon_ib_get(rdev, &ib);
3557         if (r) {
3558                 return r;
3559         }
3560         ib->ptr[0] = PACKET0(scratch, 0);
3561         ib->ptr[1] = 0xDEADBEEF;
3562         ib->ptr[2] = PACKET2(0);
3563         ib->ptr[3] = PACKET2(0);
3564         ib->ptr[4] = PACKET2(0);
3565         ib->ptr[5] = PACKET2(0);
3566         ib->ptr[6] = PACKET2(0);
3567         ib->ptr[7] = PACKET2(0);
3568         ib->length_dw = 8;
3569         r = radeon_ib_schedule(rdev, ib);
3570         if (r) {
3571                 radeon_scratch_free(rdev, scratch);
3572                 radeon_ib_free(rdev, &ib);
3573                 return r;
3574         }
3575         r = radeon_fence_wait(ib->fence, false);
3576         if (r) {
3577                 return r;
3578         }
3579         for (i = 0; i < rdev->usec_timeout; i++) {
3580                 tmp = RREG32(scratch);
3581                 if (tmp == 0xDEADBEEF) {
3582                         break;
3583                 }
3584                 DRM_UDELAY(1);
3585         }
3586         if (i < rdev->usec_timeout) {
3587                 DRM_INFO("ib test succeeded in %u usecs\n", i);
3588         } else {
3589                 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
3590                           scratch, tmp);
3591                 r = -EINVAL;
3592         }
3593         radeon_scratch_free(rdev, scratch);
3594         radeon_ib_free(rdev, &ib);
3595         return r;
3596 }
3597
3598 void r100_ib_fini(struct radeon_device *rdev)
3599 {
3600         radeon_ib_pool_fini(rdev);
3601 }
3602
3603 int r100_ib_init(struct radeon_device *rdev)
3604 {
3605         int r;
3606
3607         r = radeon_ib_pool_init(rdev);
3608         if (r) {
3609                 dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r);
3610                 r100_ib_fini(rdev);
3611                 return r;
3612         }
3613         r = r100_ib_test(rdev);
3614         if (r) {
3615                 dev_err(rdev->dev, "failled testing IB (%d).\n", r);
3616                 r100_ib_fini(rdev);
3617                 return r;
3618         }
3619         return 0;
3620 }
3621
3622 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3623 {
3624         /* Shutdown CP we shouldn't need to do that but better be safe than
3625          * sorry
3626          */
3627         rdev->cp.ready = false;
3628         WREG32(R_000740_CP_CSQ_CNTL, 0);
3629
3630         /* Save few CRTC registers */
3631         save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3632         save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3633         save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3634         save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3635         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3636                 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3637                 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3638         }
3639
3640         /* Disable VGA aperture access */
3641         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3642         /* Disable cursor, overlay, crtc */
3643         WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3644         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3645                                         S_000054_CRTC_DISPLAY_DIS(1));
3646         WREG32(R_000050_CRTC_GEN_CNTL,
3647                         (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3648                         S_000050_CRTC_DISP_REQ_EN_B(1));
3649         WREG32(R_000420_OV0_SCALE_CNTL,
3650                 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3651         WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3652         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3653                 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3654                                                 S_000360_CUR2_LOCK(1));
3655                 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3656                         (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3657                         S_0003F8_CRTC2_DISPLAY_DIS(1) |
3658                         S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3659                 WREG32(R_000360_CUR2_OFFSET,
3660                         C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3661         }
3662 }
3663
3664 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3665 {
3666         /* Update base address for crtc */
3667         WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3668         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3669                 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3670         }
3671         /* Restore CRTC registers */
3672         WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3673         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3674         WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3675         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3676                 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3677         }
3678 }
3679
3680 void r100_vga_render_disable(struct radeon_device *rdev)
3681 {
3682         u32 tmp;
3683
3684         tmp = RREG8(R_0003C2_GENMO_WT);
3685         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3686 }
3687
3688 static void r100_debugfs(struct radeon_device *rdev)
3689 {
3690         int r;
3691
3692         r = r100_debugfs_mc_info_init(rdev);
3693         if (r)
3694                 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3695 }
3696
3697 static void r100_mc_program(struct radeon_device *rdev)
3698 {
3699         struct r100_mc_save save;
3700
3701         /* Stops all mc clients */
3702         r100_mc_stop(rdev, &save);
3703         if (rdev->flags & RADEON_IS_AGP) {
3704                 WREG32(R_00014C_MC_AGP_LOCATION,
3705                         S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3706                         S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3707                 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3708                 if (rdev->family > CHIP_RV200)
3709                         WREG32(R_00015C_AGP_BASE_2,
3710                                 upper_32_bits(rdev->mc.agp_base) & 0xff);
3711         } else {
3712                 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3713                 WREG32(R_000170_AGP_BASE, 0);
3714                 if (rdev->family > CHIP_RV200)
3715                         WREG32(R_00015C_AGP_BASE_2, 0);
3716         }
3717         /* Wait for mc idle */
3718         if (r100_mc_wait_for_idle(rdev))
3719                 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3720         /* Program MC, should be a 32bits limited address space */
3721         WREG32(R_000148_MC_FB_LOCATION,
3722                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3723                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3724         r100_mc_resume(rdev, &save);
3725 }
3726
3727 void r100_clock_startup(struct radeon_device *rdev)
3728 {
3729         u32 tmp;
3730
3731         if (radeon_dynclks != -1 && radeon_dynclks)
3732                 radeon_legacy_set_clock_gating(rdev, 1);
3733         /* We need to force on some of the block */
3734         tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3735         tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3736         if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3737                 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3738         WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3739 }
3740
3741 static int r100_startup(struct radeon_device *rdev)
3742 {
3743         int r;
3744
3745         /* set common regs */
3746         r100_set_common_regs(rdev);
3747         /* program mc */
3748         r100_mc_program(rdev);
3749         /* Resume clock */
3750         r100_clock_startup(rdev);
3751         /* Initialize GPU configuration (# pipes, ...) */
3752 //      r100_gpu_init(rdev);
3753         /* Initialize GART (initialize after TTM so we can allocate
3754          * memory through TTM but finalize after TTM) */
3755         r100_enable_bm(rdev);
3756         if (rdev->flags & RADEON_IS_PCI) {
3757                 r = r100_pci_gart_enable(rdev);
3758                 if (r)
3759                         return r;
3760         }
3761         /* Enable IRQ */
3762         r100_irq_set(rdev);
3763         rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3764         /* 1M ring buffer */
3765         r = r100_cp_init(rdev, 1024 * 1024);
3766         if (r) {
3767                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
3768                 return r;
3769         }
3770         r = r100_wb_init(rdev);
3771         if (r)
3772                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
3773         r = r100_ib_init(rdev);
3774         if (r) {
3775                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
3776                 return r;
3777         }
3778         return 0;
3779 }
3780
3781 int r100_resume(struct radeon_device *rdev)
3782 {
3783         /* Make sur GART are not working */
3784         if (rdev->flags & RADEON_IS_PCI)
3785                 r100_pci_gart_disable(rdev);
3786         /* Resume clock before doing reset */
3787         r100_clock_startup(rdev);
3788         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3789         if (radeon_asic_reset(rdev)) {
3790                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3791                         RREG32(R_000E40_RBBM_STATUS),
3792                         RREG32(R_0007C0_CP_STAT));
3793         }
3794         /* post */
3795         radeon_combios_asic_init(rdev->ddev);
3796         /* Resume clock after posting */
3797         r100_clock_startup(rdev);
3798         /* Initialize surface registers */
3799         radeon_surface_init(rdev);
3800         return r100_startup(rdev);
3801 }
3802
3803 int r100_suspend(struct radeon_device *rdev)
3804 {
3805         r100_cp_disable(rdev);
3806         r100_wb_disable(rdev);
3807         r100_irq_disable(rdev);
3808         if (rdev->flags & RADEON_IS_PCI)
3809                 r100_pci_gart_disable(rdev);
3810         return 0;
3811 }
3812
3813 void r100_fini(struct radeon_device *rdev)
3814 {
3815         radeon_pm_fini(rdev);
3816         r100_cp_fini(rdev);
3817         r100_wb_fini(rdev);
3818         r100_ib_fini(rdev);
3819         radeon_gem_fini(rdev);
3820         if (rdev->flags & RADEON_IS_PCI)
3821                 r100_pci_gart_fini(rdev);
3822         radeon_agp_fini(rdev);
3823         radeon_irq_kms_fini(rdev);
3824         radeon_fence_driver_fini(rdev);
3825         radeon_bo_fini(rdev);
3826         radeon_atombios_fini(rdev);
3827         kfree(rdev->bios);
3828         rdev->bios = NULL;
3829 }
3830
3831 int r100_init(struct radeon_device *rdev)
3832 {
3833         int r;
3834
3835         /* Register debugfs file specific to this group of asics */
3836         r100_debugfs(rdev);
3837         /* Disable VGA */
3838         r100_vga_render_disable(rdev);
3839         /* Initialize scratch registers */
3840         radeon_scratch_init(rdev);
3841         /* Initialize surface registers */
3842         radeon_surface_init(rdev);
3843         /* TODO: disable VGA need to use VGA request */
3844         /* BIOS*/
3845         if (!radeon_get_bios(rdev)) {
3846                 if (ASIC_IS_AVIVO(rdev))
3847                         return -EINVAL;
3848         }
3849         if (rdev->is_atom_bios) {
3850                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
3851                 return -EINVAL;
3852         } else {
3853                 r = radeon_combios_init(rdev);
3854                 if (r)
3855                         return r;
3856         }
3857         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3858         if (radeon_asic_reset(rdev)) {
3859                 dev_warn(rdev->dev,
3860                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3861                         RREG32(R_000E40_RBBM_STATUS),
3862                         RREG32(R_0007C0_CP_STAT));
3863         }
3864         /* check if cards are posted or not */
3865         if (radeon_boot_test_post_card(rdev) == false)
3866                 return -EINVAL;
3867         /* Set asic errata */
3868         r100_errata(rdev);
3869         /* Initialize clocks */
3870         radeon_get_clock_info(rdev->ddev);
3871         /* Initialize power management */
3872         radeon_pm_init(rdev);
3873         /* initialize AGP */
3874         if (rdev->flags & RADEON_IS_AGP) {
3875                 r = radeon_agp_init(rdev);
3876                 if (r) {
3877                         radeon_agp_disable(rdev);
3878                 }
3879         }
3880         /* initialize VRAM */
3881         r100_mc_init(rdev);
3882         /* Fence driver */
3883         r = radeon_fence_driver_init(rdev);
3884         if (r)
3885                 return r;
3886         r = radeon_irq_kms_init(rdev);
3887         if (r)
3888                 return r;
3889         /* Memory manager */
3890         r = radeon_bo_init(rdev);
3891         if (r)
3892                 return r;
3893         if (rdev->flags & RADEON_IS_PCI) {
3894                 r = r100_pci_gart_init(rdev);
3895                 if (r)
3896                         return r;
3897         }
3898         r100_set_safe_registers(rdev);
3899         rdev->accel_working = true;
3900         r = r100_startup(rdev);
3901         if (r) {
3902                 /* Somethings want wront with the accel init stop accel */
3903                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
3904                 r100_cp_fini(rdev);
3905                 r100_wb_fini(rdev);
3906                 r100_ib_fini(rdev);
3907                 radeon_irq_kms_fini(rdev);
3908                 if (rdev->flags & RADEON_IS_PCI)
3909                         r100_pci_gart_fini(rdev);
3910                 rdev->accel_working = false;
3911         }
3912         return 0;
3913 }