2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
32 #include "radeon_drm.h"
33 #include "radeon_reg.h"
35 #include "radeon_asic.h"
42 #include <linux/firmware.h>
43 #include <linux/platform_device.h>
45 #include "r100_reg_safe.h"
46 #include "rn50_reg_safe.h"
49 #define FIRMWARE_R100 "radeon/R100_cp.bin"
50 #define FIRMWARE_R200 "radeon/R200_cp.bin"
51 #define FIRMWARE_R300 "radeon/R300_cp.bin"
52 #define FIRMWARE_R420 "radeon/R420_cp.bin"
53 #define FIRMWARE_RS690 "radeon/RS690_cp.bin"
54 #define FIRMWARE_RS600 "radeon/RS600_cp.bin"
55 #define FIRMWARE_R520 "radeon/R520_cp.bin"
57 MODULE_FIRMWARE(FIRMWARE_R100);
58 MODULE_FIRMWARE(FIRMWARE_R200);
59 MODULE_FIRMWARE(FIRMWARE_R300);
60 MODULE_FIRMWARE(FIRMWARE_R420);
61 MODULE_FIRMWARE(FIRMWARE_RS690);
62 MODULE_FIRMWARE(FIRMWARE_RS600);
63 MODULE_FIRMWARE(FIRMWARE_R520);
65 #include "r100_track.h"
67 /* This files gather functions specifics to:
68 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
71 void r100_get_power_state(struct radeon_device *rdev,
72 enum radeon_pm_action action)
75 rdev->pm.can_upclock = true;
76 rdev->pm.can_downclock = true;
79 case PM_ACTION_MINIMUM:
80 rdev->pm.requested_power_state_index = 0;
81 rdev->pm.can_downclock = false;
83 case PM_ACTION_DOWNCLOCK:
84 if (rdev->pm.current_power_state_index == 0) {
85 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
86 rdev->pm.can_downclock = false;
88 if (rdev->pm.active_crtc_count > 1) {
89 for (i = 0; i < rdev->pm.num_power_states; i++) {
90 if (rdev->pm.power_state[i].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)
92 else if (i >= rdev->pm.current_power_state_index) {
93 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
96 rdev->pm.requested_power_state_index = i;
101 rdev->pm.requested_power_state_index =
102 rdev->pm.current_power_state_index - 1;
105 case PM_ACTION_UPCLOCK:
106 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
107 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
108 rdev->pm.can_upclock = false;
110 if (rdev->pm.active_crtc_count > 1) {
111 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
112 if (rdev->pm.power_state[i].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)
114 else if (i <= rdev->pm.current_power_state_index) {
115 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
118 rdev->pm.requested_power_state_index = i;
123 rdev->pm.requested_power_state_index =
124 rdev->pm.current_power_state_index + 1;
127 case PM_ACTION_DEFAULT:
128 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
129 rdev->pm.can_upclock = false;
133 DRM_ERROR("Requested mode for not defined action\n");
136 /* only one clock mode per power state */
137 rdev->pm.requested_clock_mode_index = 0;
139 DRM_INFO("Requested: e: %d m: %d p: %d\n",
140 rdev->pm.power_state[rdev->pm.requested_power_state_index].
141 clock_info[rdev->pm.requested_clock_mode_index].sclk,
142 rdev->pm.power_state[rdev->pm.requested_power_state_index].
143 clock_info[rdev->pm.requested_clock_mode_index].mclk,
144 rdev->pm.power_state[rdev->pm.requested_power_state_index].
148 void r100_set_power_state(struct radeon_device *rdev, bool static_switch)
152 if (rdev->pm.current_power_state_index == rdev->pm.requested_power_state_index)
155 if (radeon_gui_idle(rdev)) {
157 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
158 clock_info[rdev->pm.requested_clock_mode_index].sclk;
159 if (sclk > rdev->clock.default_sclk)
160 sclk = rdev->clock.default_sclk;
162 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
163 clock_info[rdev->pm.requested_clock_mode_index].mclk;
164 if (mclk > rdev->clock.default_mclk)
165 mclk = rdev->clock.default_mclk;
166 /* don't change the mclk with multiple crtcs */
167 if (rdev->pm.active_crtc_count > 1)
168 mclk = rdev->clock.default_mclk;
170 /* voltage, pcie lanes, etc.*/
171 radeon_pm_misc(rdev);
174 radeon_pm_prepare(rdev);
175 /* set engine clock */
176 if (sclk != rdev->pm.current_sclk) {
177 radeon_set_engine_clock(rdev, sclk);
178 rdev->pm.current_sclk = sclk;
179 DRM_INFO("Setting: e: %d\n", sclk);
181 /* set memory clock */
182 if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
183 radeon_set_memory_clock(rdev, mclk);
184 rdev->pm.current_mclk = mclk;
185 DRM_INFO("Setting: m: %d\n", mclk);
187 radeon_pm_finish(rdev);
189 radeon_sync_with_vblank(rdev);
191 if (!radeon_pm_in_vbl(rdev))
194 radeon_pm_prepare(rdev);
195 /* set engine clock */
196 if (sclk != rdev->pm.current_sclk) {
197 radeon_pm_debug_check_in_vbl(rdev, false);
198 radeon_set_engine_clock(rdev, sclk);
199 radeon_pm_debug_check_in_vbl(rdev, true);
200 rdev->pm.current_sclk = sclk;
201 DRM_INFO("Setting: e: %d\n", sclk);
204 /* set memory clock */
205 if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
206 radeon_pm_debug_check_in_vbl(rdev, false);
207 radeon_set_memory_clock(rdev, mclk);
208 radeon_pm_debug_check_in_vbl(rdev, true);
209 rdev->pm.current_mclk = mclk;
210 DRM_INFO("Setting: m: %d\n", mclk);
212 radeon_pm_finish(rdev);
215 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
216 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
218 DRM_INFO("GUI not idle!!!\n");
221 void r100_pm_misc(struct radeon_device *rdev)
224 int requested_index = rdev->pm.requested_power_state_index;
225 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
226 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
227 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
229 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
230 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
231 tmp = RREG32(voltage->gpio.reg);
232 if (voltage->active_high)
233 tmp |= voltage->gpio.mask;
235 tmp &= ~(voltage->gpio.mask);
236 WREG32(voltage->gpio.reg, tmp);
238 udelay(voltage->delay);
240 tmp = RREG32(voltage->gpio.reg);
241 if (voltage->active_high)
242 tmp &= ~voltage->gpio.mask;
244 tmp |= voltage->gpio.mask;
245 WREG32(voltage->gpio.reg, tmp);
247 udelay(voltage->delay);
251 sclk_cntl = RREG32_PLL(SCLK_CNTL);
252 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
253 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
254 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
255 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
256 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
257 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
258 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
259 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
261 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
262 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
263 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
264 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
265 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
267 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
269 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
270 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
271 if (voltage->delay) {
272 sclk_more_cntl |= VOLTAGE_DROP_SYNC;
273 switch (voltage->delay) {
275 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
278 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
281 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
284 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
288 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
290 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
292 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
293 sclk_cntl &= ~FORCE_HDP;
295 sclk_cntl |= FORCE_HDP;
297 WREG32_PLL(SCLK_CNTL, sclk_cntl);
298 WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
299 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
302 if ((rdev->flags & RADEON_IS_PCIE) &&
303 !(rdev->flags & RADEON_IS_IGP) &&
304 rdev->asic->set_pcie_lanes &&
306 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
307 radeon_set_pcie_lanes(rdev,
309 DRM_INFO("Setting: p: %d\n", ps->pcie_lanes);
314 void r100_pm_prepare(struct radeon_device *rdev)
316 struct drm_device *ddev = rdev->ddev;
317 struct drm_crtc *crtc;
318 struct radeon_crtc *radeon_crtc;
321 /* disable any active CRTCs */
322 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
323 radeon_crtc = to_radeon_crtc(crtc);
324 if (radeon_crtc->enabled) {
325 if (radeon_crtc->crtc_id) {
326 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
327 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
328 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
330 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
331 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
332 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
338 void r100_pm_finish(struct radeon_device *rdev)
340 struct drm_device *ddev = rdev->ddev;
341 struct drm_crtc *crtc;
342 struct radeon_crtc *radeon_crtc;
345 /* enable any active CRTCs */
346 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
347 radeon_crtc = to_radeon_crtc(crtc);
348 if (radeon_crtc->enabled) {
349 if (radeon_crtc->crtc_id) {
350 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
351 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
352 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
354 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
355 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
356 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
362 bool r100_gui_idle(struct radeon_device *rdev)
364 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
370 /* hpd for digital panel detect/disconnect */
371 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
373 bool connected = false;
377 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
381 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
390 void r100_hpd_set_polarity(struct radeon_device *rdev,
391 enum radeon_hpd_id hpd)
394 bool connected = r100_hpd_sense(rdev, hpd);
398 tmp = RREG32(RADEON_FP_GEN_CNTL);
400 tmp &= ~RADEON_FP_DETECT_INT_POL;
402 tmp |= RADEON_FP_DETECT_INT_POL;
403 WREG32(RADEON_FP_GEN_CNTL, tmp);
406 tmp = RREG32(RADEON_FP2_GEN_CNTL);
408 tmp &= ~RADEON_FP2_DETECT_INT_POL;
410 tmp |= RADEON_FP2_DETECT_INT_POL;
411 WREG32(RADEON_FP2_GEN_CNTL, tmp);
418 void r100_hpd_init(struct radeon_device *rdev)
420 struct drm_device *dev = rdev->ddev;
421 struct drm_connector *connector;
423 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
424 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
425 switch (radeon_connector->hpd.hpd) {
427 rdev->irq.hpd[0] = true;
430 rdev->irq.hpd[1] = true;
436 if (rdev->irq.installed)
440 void r100_hpd_fini(struct radeon_device *rdev)
442 struct drm_device *dev = rdev->ddev;
443 struct drm_connector *connector;
445 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
446 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
447 switch (radeon_connector->hpd.hpd) {
449 rdev->irq.hpd[0] = false;
452 rdev->irq.hpd[1] = false;
463 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
465 /* TODO: can we do somethings here ? */
466 /* It seems hw only cache one entry so we should discard this
467 * entry otherwise if first GPU GART read hit this entry it
468 * could end up in wrong address. */
471 int r100_pci_gart_init(struct radeon_device *rdev)
475 if (rdev->gart.table.ram.ptr) {
476 WARN(1, "R100 PCI GART already initialized.\n");
479 /* Initialize common gart structure */
480 r = radeon_gart_init(rdev);
483 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
484 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
485 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
486 return radeon_gart_table_ram_alloc(rdev);
489 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
490 void r100_enable_bm(struct radeon_device *rdev)
493 /* Enable bus mastering */
494 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
495 WREG32(RADEON_BUS_CNTL, tmp);
498 int r100_pci_gart_enable(struct radeon_device *rdev)
502 radeon_gart_restore(rdev);
503 /* discard memory request outside of configured range */
504 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
505 WREG32(RADEON_AIC_CNTL, tmp);
506 /* set address range for PCI address translate */
507 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
508 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
509 /* set PCI GART page-table base address */
510 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
511 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
512 WREG32(RADEON_AIC_CNTL, tmp);
513 r100_pci_gart_tlb_flush(rdev);
514 rdev->gart.ready = true;
518 void r100_pci_gart_disable(struct radeon_device *rdev)
522 /* discard memory request outside of configured range */
523 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
524 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
525 WREG32(RADEON_AIC_LO_ADDR, 0);
526 WREG32(RADEON_AIC_HI_ADDR, 0);
529 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
531 if (i < 0 || i > rdev->gart.num_gpu_pages) {
534 rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
538 void r100_pci_gart_fini(struct radeon_device *rdev)
540 radeon_gart_fini(rdev);
541 r100_pci_gart_disable(rdev);
542 radeon_gart_table_ram_free(rdev);
545 int r100_irq_set(struct radeon_device *rdev)
549 if (!rdev->irq.installed) {
550 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
551 WREG32(R_000040_GEN_INT_CNTL, 0);
554 if (rdev->irq.sw_int) {
555 tmp |= RADEON_SW_INT_ENABLE;
557 if (rdev->irq.gui_idle) {
558 tmp |= RADEON_GUI_IDLE_MASK;
560 if (rdev->irq.crtc_vblank_int[0]) {
561 tmp |= RADEON_CRTC_VBLANK_MASK;
563 if (rdev->irq.crtc_vblank_int[1]) {
564 tmp |= RADEON_CRTC2_VBLANK_MASK;
566 if (rdev->irq.hpd[0]) {
567 tmp |= RADEON_FP_DETECT_MASK;
569 if (rdev->irq.hpd[1]) {
570 tmp |= RADEON_FP2_DETECT_MASK;
572 WREG32(RADEON_GEN_INT_CNTL, tmp);
576 void r100_irq_disable(struct radeon_device *rdev)
580 WREG32(R_000040_GEN_INT_CNTL, 0);
581 /* Wait and acknowledge irq */
583 tmp = RREG32(R_000044_GEN_INT_STATUS);
584 WREG32(R_000044_GEN_INT_STATUS, tmp);
587 static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
589 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
590 uint32_t irq_mask = RADEON_SW_INT_TEST |
591 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
592 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
594 /* the interrupt works, but the status bit is permanently asserted */
595 if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
596 if (!rdev->irq.gui_idle_acked)
597 irq_mask |= RADEON_GUI_IDLE_STAT;
601 WREG32(RADEON_GEN_INT_STATUS, irqs);
603 return irqs & irq_mask;
606 int r100_irq_process(struct radeon_device *rdev)
608 uint32_t status, msi_rearm;
609 bool queue_hotplug = false;
611 /* reset gui idle ack. the status bit is broken */
612 rdev->irq.gui_idle_acked = false;
614 status = r100_irq_ack(rdev);
618 if (rdev->shutdown) {
623 if (status & RADEON_SW_INT_TEST) {
624 radeon_fence_process(rdev);
626 /* gui idle interrupt */
627 if (status & RADEON_GUI_IDLE_STAT) {
628 rdev->irq.gui_idle_acked = true;
629 rdev->pm.gui_idle = true;
630 wake_up(&rdev->irq.idle_queue);
632 /* Vertical blank interrupts */
633 if (status & RADEON_CRTC_VBLANK_STAT) {
634 drm_handle_vblank(rdev->ddev, 0);
635 rdev->pm.vblank_sync = true;
636 wake_up(&rdev->irq.vblank_queue);
638 if (status & RADEON_CRTC2_VBLANK_STAT) {
639 drm_handle_vblank(rdev->ddev, 1);
640 rdev->pm.vblank_sync = true;
641 wake_up(&rdev->irq.vblank_queue);
643 if (status & RADEON_FP_DETECT_STAT) {
644 queue_hotplug = true;
647 if (status & RADEON_FP2_DETECT_STAT) {
648 queue_hotplug = true;
651 status = r100_irq_ack(rdev);
653 /* reset gui idle ack. the status bit is broken */
654 rdev->irq.gui_idle_acked = false;
656 queue_work(rdev->wq, &rdev->hotplug_work);
657 if (rdev->msi_enabled) {
658 switch (rdev->family) {
661 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
662 WREG32(RADEON_AIC_CNTL, msi_rearm);
663 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
666 msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
667 WREG32(RADEON_MSI_REARM_EN, msi_rearm);
668 WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
675 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
678 return RREG32(RADEON_CRTC_CRNT_FRAME);
680 return RREG32(RADEON_CRTC2_CRNT_FRAME);
683 /* Who ever call radeon_fence_emit should call ring_lock and ask
684 * for enough space (today caller are ib schedule and buffer move) */
685 void r100_fence_ring_emit(struct radeon_device *rdev,
686 struct radeon_fence *fence)
688 /* We have to make sure that caches are flushed before
689 * CPU might read something from VRAM. */
690 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
691 radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
692 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
693 radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
694 /* Wait until IDLE & CLEAN */
695 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
696 radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
697 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
698 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
699 RADEON_HDP_READ_BUFFER_INVALIDATE);
700 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
701 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
702 /* Emit fence sequence & fire IRQ */
703 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
704 radeon_ring_write(rdev, fence->seq);
705 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
706 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
709 int r100_wb_init(struct radeon_device *rdev)
713 if (rdev->wb.wb_obj == NULL) {
714 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
715 RADEON_GEM_DOMAIN_GTT,
718 dev_err(rdev->dev, "(%d) create WB buffer failed\n", r);
721 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
722 if (unlikely(r != 0))
724 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
727 dev_err(rdev->dev, "(%d) pin WB buffer failed\n", r);
728 radeon_bo_unreserve(rdev->wb.wb_obj);
731 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
732 radeon_bo_unreserve(rdev->wb.wb_obj);
734 dev_err(rdev->dev, "(%d) map WB buffer failed\n", r);
738 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
739 WREG32(R_00070C_CP_RB_RPTR_ADDR,
740 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
741 WREG32(R_000770_SCRATCH_UMSK, 0xff);
745 void r100_wb_disable(struct radeon_device *rdev)
747 WREG32(R_000770_SCRATCH_UMSK, 0);
750 void r100_wb_fini(struct radeon_device *rdev)
754 r100_wb_disable(rdev);
755 if (rdev->wb.wb_obj) {
756 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
757 if (unlikely(r != 0)) {
758 dev_err(rdev->dev, "(%d) can't finish WB\n", r);
761 radeon_bo_kunmap(rdev->wb.wb_obj);
762 radeon_bo_unpin(rdev->wb.wb_obj);
763 radeon_bo_unreserve(rdev->wb.wb_obj);
764 radeon_bo_unref(&rdev->wb.wb_obj);
766 rdev->wb.wb_obj = NULL;
770 int r100_copy_blit(struct radeon_device *rdev,
774 struct radeon_fence *fence)
777 uint32_t stride_bytes = PAGE_SIZE;
779 uint32_t stride_pixels;
784 /* radeon limited to 16k stride */
785 stride_bytes &= 0x3fff;
786 /* radeon pitch is /64 */
787 pitch = stride_bytes / 64;
788 stride_pixels = stride_bytes / 4;
789 num_loops = DIV_ROUND_UP(num_pages, 8191);
791 /* Ask for enough room for blit + flush + fence */
792 ndw = 64 + (10 * num_loops);
793 r = radeon_ring_lock(rdev, ndw);
795 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
798 while (num_pages > 0) {
799 cur_pages = num_pages;
800 if (cur_pages > 8191) {
803 num_pages -= cur_pages;
805 /* pages are in Y direction - height
806 page width in X direction - width */
807 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
808 radeon_ring_write(rdev,
809 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
810 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
811 RADEON_GMC_SRC_CLIPPING |
812 RADEON_GMC_DST_CLIPPING |
813 RADEON_GMC_BRUSH_NONE |
814 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
815 RADEON_GMC_SRC_DATATYPE_COLOR |
817 RADEON_DP_SRC_SOURCE_MEMORY |
818 RADEON_GMC_CLR_CMP_CNTL_DIS |
819 RADEON_GMC_WR_MSK_DIS);
820 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
821 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
822 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
823 radeon_ring_write(rdev, 0);
824 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
825 radeon_ring_write(rdev, num_pages);
826 radeon_ring_write(rdev, num_pages);
827 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
829 radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
830 radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
831 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
832 radeon_ring_write(rdev,
833 RADEON_WAIT_2D_IDLECLEAN |
834 RADEON_WAIT_HOST_IDLECLEAN |
835 RADEON_WAIT_DMA_GUI_IDLE);
837 r = radeon_fence_emit(rdev, fence);
839 radeon_ring_unlock_commit(rdev);
843 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
848 for (i = 0; i < rdev->usec_timeout; i++) {
849 tmp = RREG32(R_000E40_RBBM_STATUS);
850 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
858 void r100_ring_start(struct radeon_device *rdev)
862 r = radeon_ring_lock(rdev, 2);
866 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
867 radeon_ring_write(rdev,
868 RADEON_ISYNC_ANY2D_IDLE3D |
869 RADEON_ISYNC_ANY3D_IDLE2D |
870 RADEON_ISYNC_WAIT_IDLEGUI |
871 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
872 radeon_ring_unlock_commit(rdev);
876 /* Load the microcode for the CP */
877 static int r100_cp_init_microcode(struct radeon_device *rdev)
879 struct platform_device *pdev;
880 const char *fw_name = NULL;
885 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
888 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
891 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
892 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
893 (rdev->family == CHIP_RS200)) {
894 DRM_INFO("Loading R100 Microcode\n");
895 fw_name = FIRMWARE_R100;
896 } else if ((rdev->family == CHIP_R200) ||
897 (rdev->family == CHIP_RV250) ||
898 (rdev->family == CHIP_RV280) ||
899 (rdev->family == CHIP_RS300)) {
900 DRM_INFO("Loading R200 Microcode\n");
901 fw_name = FIRMWARE_R200;
902 } else if ((rdev->family == CHIP_R300) ||
903 (rdev->family == CHIP_R350) ||
904 (rdev->family == CHIP_RV350) ||
905 (rdev->family == CHIP_RV380) ||
906 (rdev->family == CHIP_RS400) ||
907 (rdev->family == CHIP_RS480)) {
908 DRM_INFO("Loading R300 Microcode\n");
909 fw_name = FIRMWARE_R300;
910 } else if ((rdev->family == CHIP_R420) ||
911 (rdev->family == CHIP_R423) ||
912 (rdev->family == CHIP_RV410)) {
913 DRM_INFO("Loading R400 Microcode\n");
914 fw_name = FIRMWARE_R420;
915 } else if ((rdev->family == CHIP_RS690) ||
916 (rdev->family == CHIP_RS740)) {
917 DRM_INFO("Loading RS690/RS740 Microcode\n");
918 fw_name = FIRMWARE_RS690;
919 } else if (rdev->family == CHIP_RS600) {
920 DRM_INFO("Loading RS600 Microcode\n");
921 fw_name = FIRMWARE_RS600;
922 } else if ((rdev->family == CHIP_RV515) ||
923 (rdev->family == CHIP_R520) ||
924 (rdev->family == CHIP_RV530) ||
925 (rdev->family == CHIP_R580) ||
926 (rdev->family == CHIP_RV560) ||
927 (rdev->family == CHIP_RV570)) {
928 DRM_INFO("Loading R500 Microcode\n");
929 fw_name = FIRMWARE_R520;
932 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
933 platform_device_unregister(pdev);
935 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
937 } else if (rdev->me_fw->size % 8) {
939 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
940 rdev->me_fw->size, fw_name);
942 release_firmware(rdev->me_fw);
948 static void r100_cp_load_microcode(struct radeon_device *rdev)
950 const __be32 *fw_data;
953 if (r100_gui_wait_for_idle(rdev)) {
954 printk(KERN_WARNING "Failed to wait GUI idle while "
955 "programming pipes. Bad things might happen.\n");
959 size = rdev->me_fw->size / 4;
960 fw_data = (const __be32 *)&rdev->me_fw->data[0];
961 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
962 for (i = 0; i < size; i += 2) {
963 WREG32(RADEON_CP_ME_RAM_DATAH,
964 be32_to_cpup(&fw_data[i]));
965 WREG32(RADEON_CP_ME_RAM_DATAL,
966 be32_to_cpup(&fw_data[i + 1]));
971 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
976 unsigned pre_write_timer;
977 unsigned pre_write_limit;
978 unsigned indirect2_start;
979 unsigned indirect1_start;
983 if (r100_debugfs_cp_init(rdev)) {
984 DRM_ERROR("Failed to register debugfs file for CP !\n");
987 r = r100_cp_init_microcode(rdev);
989 DRM_ERROR("Failed to load firmware!\n");
994 /* Align ring size */
995 rb_bufsz = drm_order(ring_size / 8);
996 ring_size = (1 << (rb_bufsz + 1)) * 4;
997 r100_cp_load_microcode(rdev);
998 r = radeon_ring_init(rdev, ring_size);
1002 /* Each time the cp read 1024 bytes (16 dword/quadword) update
1003 * the rptr copy in system ram */
1005 /* cp will read 128bytes at a time (4 dwords) */
1007 rdev->cp.align_mask = 16 - 1;
1008 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
1009 pre_write_timer = 64;
1010 /* Force CP_RB_WPTR write if written more than one time before the
1013 pre_write_limit = 0;
1014 /* Setup the cp cache like this (cache size is 96 dwords) :
1016 * INDIRECT1 16 to 79
1017 * INDIRECT2 80 to 95
1018 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1019 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
1020 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1021 * Idea being that most of the gpu cmd will be through indirect1 buffer
1022 * so it gets the bigger cache.
1024 indirect2_start = 80;
1025 indirect1_start = 16;
1027 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
1028 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
1029 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
1030 REG_SET(RADEON_MAX_FETCH, max_fetch) |
1031 RADEON_RB_NO_UPDATE);
1033 tmp |= RADEON_BUF_SWAP_32BIT;
1035 WREG32(RADEON_CP_RB_CNTL, tmp);
1037 /* Set ring address */
1038 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
1039 WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
1040 /* Force read & write ptr to 0 */
1041 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
1042 WREG32(RADEON_CP_RB_RPTR_WR, 0);
1043 WREG32(RADEON_CP_RB_WPTR, 0);
1044 WREG32(RADEON_CP_RB_CNTL, tmp);
1046 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
1047 rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
1048 /* protect against crazy HW on resume */
1049 rdev->cp.wptr &= rdev->cp.ptr_mask;
1050 /* Set cp mode to bus mastering & enable cp*/
1051 WREG32(RADEON_CP_CSQ_MODE,
1052 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1053 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1055 WREG32(0x744, 0x00004D4D);
1056 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1057 radeon_ring_start(rdev);
1058 r = radeon_ring_test(rdev);
1060 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1063 rdev->cp.ready = true;
1067 void r100_cp_fini(struct radeon_device *rdev)
1069 if (r100_cp_wait_for_idle(rdev)) {
1070 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1073 r100_cp_disable(rdev);
1074 radeon_ring_fini(rdev);
1075 DRM_INFO("radeon: cp finalized\n");
1078 void r100_cp_disable(struct radeon_device *rdev)
1081 rdev->cp.ready = false;
1082 WREG32(RADEON_CP_CSQ_MODE, 0);
1083 WREG32(RADEON_CP_CSQ_CNTL, 0);
1084 if (r100_gui_wait_for_idle(rdev)) {
1085 printk(KERN_WARNING "Failed to wait GUI idle while "
1086 "programming pipes. Bad things might happen.\n");
1090 void r100_cp_commit(struct radeon_device *rdev)
1092 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
1093 (void)RREG32(RADEON_CP_RB_WPTR);
1100 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1101 struct radeon_cs_packet *pkt,
1102 const unsigned *auth, unsigned n,
1103 radeon_packet0_check_t check)
1112 /* Check that register fall into register range
1113 * determined by the number of entry (n) in the
1114 * safe register bitmap.
1116 if (pkt->one_reg_wr) {
1117 if ((reg >> 7) > n) {
1121 if (((reg + (pkt->count << 2)) >> 7) > n) {
1125 for (i = 0; i <= pkt->count; i++, idx++) {
1127 m = 1 << ((reg >> 2) & 31);
1129 r = check(p, pkt, idx, reg);
1134 if (pkt->one_reg_wr) {
1135 if (!(auth[j] & m)) {
1145 void r100_cs_dump_packet(struct radeon_cs_parser *p,
1146 struct radeon_cs_packet *pkt)
1148 volatile uint32_t *ib;
1154 for (i = 0; i <= (pkt->count + 1); i++, idx++) {
1155 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
1160 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
1161 * @parser: parser structure holding parsing context.
1162 * @pkt: where to store packet informations
1164 * Assume that chunk_ib_index is properly set. Will return -EINVAL
1165 * if packet is bigger than remaining ib size. or if packets is unknown.
1167 int r100_cs_packet_parse(struct radeon_cs_parser *p,
1168 struct radeon_cs_packet *pkt,
1171 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
1174 if (idx >= ib_chunk->length_dw) {
1175 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
1176 idx, ib_chunk->length_dw);
1179 header = radeon_get_ib_value(p, idx);
1181 pkt->type = CP_PACKET_GET_TYPE(header);
1182 pkt->count = CP_PACKET_GET_COUNT(header);
1183 switch (pkt->type) {
1185 pkt->reg = CP_PACKET0_GET_REG(header);
1186 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
1189 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
1195 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
1198 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
1199 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
1200 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
1207 * r100_cs_packet_next_vline() - parse userspace VLINE packet
1208 * @parser: parser structure holding parsing context.
1210 * Userspace sends a special sequence for VLINE waits.
1211 * PACKET0 - VLINE_START_END + value
1212 * PACKET0 - WAIT_UNTIL +_value
1213 * RELOC (P3) - crtc_id in reloc.
1215 * This function parses this and relocates the VLINE START END
1216 * and WAIT UNTIL packets to the correct crtc.
1217 * It also detects a switched off crtc and nulls out the
1218 * wait in that case.
1220 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1222 struct drm_mode_object *obj;
1223 struct drm_crtc *crtc;
1224 struct radeon_crtc *radeon_crtc;
1225 struct radeon_cs_packet p3reloc, waitreloc;
1228 uint32_t header, h_idx, reg;
1229 volatile uint32_t *ib;
1233 /* parse the wait until */
1234 r = r100_cs_packet_parse(p, &waitreloc, p->idx);
1238 /* check its a wait until and only 1 count */
1239 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1240 waitreloc.count != 0) {
1241 DRM_ERROR("vline wait had illegal wait until segment\n");
1246 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1247 DRM_ERROR("vline wait had illegal wait until\n");
1252 /* jump over the NOP */
1253 r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1258 p->idx += waitreloc.count + 2;
1259 p->idx += p3reloc.count + 2;
1261 header = radeon_get_ib_value(p, h_idx);
1262 crtc_id = radeon_get_ib_value(p, h_idx + 5);
1263 reg = CP_PACKET0_GET_REG(header);
1264 mutex_lock(&p->rdev->ddev->mode_config.mutex);
1265 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1267 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1271 crtc = obj_to_crtc(obj);
1272 radeon_crtc = to_radeon_crtc(crtc);
1273 crtc_id = radeon_crtc->crtc_id;
1275 if (!crtc->enabled) {
1276 /* if the CRTC isn't enabled - we need to nop out the wait until */
1277 ib[h_idx + 2] = PACKET2(0);
1278 ib[h_idx + 3] = PACKET2(0);
1279 } else if (crtc_id == 1) {
1281 case AVIVO_D1MODE_VLINE_START_END:
1282 header &= ~R300_CP_PACKET0_REG_MASK;
1283 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1285 case RADEON_CRTC_GUI_TRIG_VLINE:
1286 header &= ~R300_CP_PACKET0_REG_MASK;
1287 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1290 DRM_ERROR("unknown crtc reloc\n");
1295 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1298 mutex_unlock(&p->rdev->ddev->mode_config.mutex);
1303 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1304 * @parser: parser structure holding parsing context.
1305 * @data: pointer to relocation data
1306 * @offset_start: starting offset
1307 * @offset_mask: offset mask (to align start offset on)
1308 * @reloc: reloc informations
1310 * Check next packet is relocation packet3, do bo validation and compute
1311 * GPU offset using the provided start.
1313 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1314 struct radeon_cs_reloc **cs_reloc)
1316 struct radeon_cs_chunk *relocs_chunk;
1317 struct radeon_cs_packet p3reloc;
1321 if (p->chunk_relocs_idx == -1) {
1322 DRM_ERROR("No relocation chunk !\n");
1326 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1327 r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1331 p->idx += p3reloc.count + 2;
1332 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1333 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1335 r100_cs_dump_packet(p, &p3reloc);
1338 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1339 if (idx >= relocs_chunk->length_dw) {
1340 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1341 idx, relocs_chunk->length_dw);
1342 r100_cs_dump_packet(p, &p3reloc);
1345 /* FIXME: we assume reloc size is 4 dwords */
1346 *cs_reloc = p->relocs_ptr[(idx / 4)];
1350 static int r100_get_vtx_size(uint32_t vtx_fmt)
1354 /* ordered according to bits in spec */
1355 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1357 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1359 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1361 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1363 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1365 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1367 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1369 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1371 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1373 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1375 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1377 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1379 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1381 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1383 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1386 if (vtx_fmt & (0x7 << 15))
1387 vtx_size += (vtx_fmt >> 15) & 0x7;
1388 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1390 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1392 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1394 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1396 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1398 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1403 static int r100_packet0_check(struct radeon_cs_parser *p,
1404 struct radeon_cs_packet *pkt,
1405 unsigned idx, unsigned reg)
1407 struct radeon_cs_reloc *reloc;
1408 struct r100_cs_track *track;
1409 volatile uint32_t *ib;
1417 track = (struct r100_cs_track *)p->track;
1419 idx_value = radeon_get_ib_value(p, idx);
1422 case RADEON_CRTC_GUI_TRIG_VLINE:
1423 r = r100_cs_packet_parse_vline(p);
1425 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1427 r100_cs_dump_packet(p, pkt);
1431 /* FIXME: only allow PACKET3 blit? easier to check for out of
1433 case RADEON_DST_PITCH_OFFSET:
1434 case RADEON_SRC_PITCH_OFFSET:
1435 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1439 case RADEON_RB3D_DEPTHOFFSET:
1440 r = r100_cs_packet_next_reloc(p, &reloc);
1442 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1444 r100_cs_dump_packet(p, pkt);
1447 track->zb.robj = reloc->robj;
1448 track->zb.offset = idx_value;
1449 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1451 case RADEON_RB3D_COLOROFFSET:
1452 r = r100_cs_packet_next_reloc(p, &reloc);
1454 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1456 r100_cs_dump_packet(p, pkt);
1459 track->cb[0].robj = reloc->robj;
1460 track->cb[0].offset = idx_value;
1461 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1463 case RADEON_PP_TXOFFSET_0:
1464 case RADEON_PP_TXOFFSET_1:
1465 case RADEON_PP_TXOFFSET_2:
1466 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1467 r = r100_cs_packet_next_reloc(p, &reloc);
1469 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1471 r100_cs_dump_packet(p, pkt);
1474 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1475 track->textures[i].robj = reloc->robj;
1477 case RADEON_PP_CUBIC_OFFSET_T0_0:
1478 case RADEON_PP_CUBIC_OFFSET_T0_1:
1479 case RADEON_PP_CUBIC_OFFSET_T0_2:
1480 case RADEON_PP_CUBIC_OFFSET_T0_3:
1481 case RADEON_PP_CUBIC_OFFSET_T0_4:
1482 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1483 r = r100_cs_packet_next_reloc(p, &reloc);
1485 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1487 r100_cs_dump_packet(p, pkt);
1490 track->textures[0].cube_info[i].offset = idx_value;
1491 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1492 track->textures[0].cube_info[i].robj = reloc->robj;
1494 case RADEON_PP_CUBIC_OFFSET_T1_0:
1495 case RADEON_PP_CUBIC_OFFSET_T1_1:
1496 case RADEON_PP_CUBIC_OFFSET_T1_2:
1497 case RADEON_PP_CUBIC_OFFSET_T1_3:
1498 case RADEON_PP_CUBIC_OFFSET_T1_4:
1499 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1500 r = r100_cs_packet_next_reloc(p, &reloc);
1502 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1504 r100_cs_dump_packet(p, pkt);
1507 track->textures[1].cube_info[i].offset = idx_value;
1508 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1509 track->textures[1].cube_info[i].robj = reloc->robj;
1511 case RADEON_PP_CUBIC_OFFSET_T2_0:
1512 case RADEON_PP_CUBIC_OFFSET_T2_1:
1513 case RADEON_PP_CUBIC_OFFSET_T2_2:
1514 case RADEON_PP_CUBIC_OFFSET_T2_3:
1515 case RADEON_PP_CUBIC_OFFSET_T2_4:
1516 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1517 r = r100_cs_packet_next_reloc(p, &reloc);
1519 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1521 r100_cs_dump_packet(p, pkt);
1524 track->textures[2].cube_info[i].offset = idx_value;
1525 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1526 track->textures[2].cube_info[i].robj = reloc->robj;
1528 case RADEON_RE_WIDTH_HEIGHT:
1529 track->maxy = ((idx_value >> 16) & 0x7FF);
1531 case RADEON_RB3D_COLORPITCH:
1532 r = r100_cs_packet_next_reloc(p, &reloc);
1534 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1536 r100_cs_dump_packet(p, pkt);
1540 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1541 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1542 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1543 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1545 tmp = idx_value & ~(0x7 << 16);
1549 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1551 case RADEON_RB3D_DEPTHPITCH:
1552 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1554 case RADEON_RB3D_CNTL:
1555 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1561 track->cb[0].cpp = 1;
1566 track->cb[0].cpp = 2;
1569 track->cb[0].cpp = 4;
1572 DRM_ERROR("Invalid color buffer format (%d) !\n",
1573 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1576 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1578 case RADEON_RB3D_ZSTENCILCNTL:
1579 switch (idx_value & 0xf) {
1595 case RADEON_RB3D_ZPASS_ADDR:
1596 r = r100_cs_packet_next_reloc(p, &reloc);
1598 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1600 r100_cs_dump_packet(p, pkt);
1603 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1605 case RADEON_PP_CNTL:
1607 uint32_t temp = idx_value >> 4;
1608 for (i = 0; i < track->num_texture; i++)
1609 track->textures[i].enabled = !!(temp & (1 << i));
1612 case RADEON_SE_VF_CNTL:
1613 track->vap_vf_cntl = idx_value;
1615 case RADEON_SE_VTX_FMT:
1616 track->vtx_size = r100_get_vtx_size(idx_value);
1618 case RADEON_PP_TEX_SIZE_0:
1619 case RADEON_PP_TEX_SIZE_1:
1620 case RADEON_PP_TEX_SIZE_2:
1621 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1622 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1623 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1625 case RADEON_PP_TEX_PITCH_0:
1626 case RADEON_PP_TEX_PITCH_1:
1627 case RADEON_PP_TEX_PITCH_2:
1628 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1629 track->textures[i].pitch = idx_value + 32;
1631 case RADEON_PP_TXFILTER_0:
1632 case RADEON_PP_TXFILTER_1:
1633 case RADEON_PP_TXFILTER_2:
1634 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1635 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1636 >> RADEON_MAX_MIP_LEVEL_SHIFT);
1637 tmp = (idx_value >> 23) & 0x7;
1638 if (tmp == 2 || tmp == 6)
1639 track->textures[i].roundup_w = false;
1640 tmp = (idx_value >> 27) & 0x7;
1641 if (tmp == 2 || tmp == 6)
1642 track->textures[i].roundup_h = false;
1644 case RADEON_PP_TXFORMAT_0:
1645 case RADEON_PP_TXFORMAT_1:
1646 case RADEON_PP_TXFORMAT_2:
1647 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1648 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1649 track->textures[i].use_pitch = 1;
1651 track->textures[i].use_pitch = 0;
1652 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1653 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1655 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1656 track->textures[i].tex_coord_type = 2;
1657 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1658 case RADEON_TXFORMAT_I8:
1659 case RADEON_TXFORMAT_RGB332:
1660 case RADEON_TXFORMAT_Y8:
1661 track->textures[i].cpp = 1;
1663 case RADEON_TXFORMAT_AI88:
1664 case RADEON_TXFORMAT_ARGB1555:
1665 case RADEON_TXFORMAT_RGB565:
1666 case RADEON_TXFORMAT_ARGB4444:
1667 case RADEON_TXFORMAT_VYUY422:
1668 case RADEON_TXFORMAT_YVYU422:
1669 case RADEON_TXFORMAT_SHADOW16:
1670 case RADEON_TXFORMAT_LDUDV655:
1671 case RADEON_TXFORMAT_DUDV88:
1672 track->textures[i].cpp = 2;
1674 case RADEON_TXFORMAT_ARGB8888:
1675 case RADEON_TXFORMAT_RGBA8888:
1676 case RADEON_TXFORMAT_SHADOW32:
1677 case RADEON_TXFORMAT_LDUDUV8888:
1678 track->textures[i].cpp = 4;
1680 case RADEON_TXFORMAT_DXT1:
1681 track->textures[i].cpp = 1;
1682 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1684 case RADEON_TXFORMAT_DXT23:
1685 case RADEON_TXFORMAT_DXT45:
1686 track->textures[i].cpp = 1;
1687 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1690 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1691 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1693 case RADEON_PP_CUBIC_FACES_0:
1694 case RADEON_PP_CUBIC_FACES_1:
1695 case RADEON_PP_CUBIC_FACES_2:
1697 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1698 for (face = 0; face < 4; face++) {
1699 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1700 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1704 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1711 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1712 struct radeon_cs_packet *pkt,
1713 struct radeon_bo *robj)
1718 value = radeon_get_ib_value(p, idx + 2);
1719 if ((value + 1) > radeon_bo_size(robj)) {
1720 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1721 "(need %u have %lu) !\n",
1723 radeon_bo_size(robj));
1729 static int r100_packet3_check(struct radeon_cs_parser *p,
1730 struct radeon_cs_packet *pkt)
1732 struct radeon_cs_reloc *reloc;
1733 struct r100_cs_track *track;
1735 volatile uint32_t *ib;
1740 track = (struct r100_cs_track *)p->track;
1741 switch (pkt->opcode) {
1742 case PACKET3_3D_LOAD_VBPNTR:
1743 r = r100_packet3_load_vbpntr(p, pkt, idx);
1747 case PACKET3_INDX_BUFFER:
1748 r = r100_cs_packet_next_reloc(p, &reloc);
1750 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1751 r100_cs_dump_packet(p, pkt);
1754 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1755 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1761 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1762 r = r100_cs_packet_next_reloc(p, &reloc);
1764 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1765 r100_cs_dump_packet(p, pkt);
1768 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1769 track->num_arrays = 1;
1770 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1772 track->arrays[0].robj = reloc->robj;
1773 track->arrays[0].esize = track->vtx_size;
1775 track->max_indx = radeon_get_ib_value(p, idx+1);
1777 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1778 track->immd_dwords = pkt->count - 1;
1779 r = r100_cs_track_check(p->rdev, track);
1783 case PACKET3_3D_DRAW_IMMD:
1784 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1785 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1788 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1789 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1790 track->immd_dwords = pkt->count - 1;
1791 r = r100_cs_track_check(p->rdev, track);
1795 /* triggers drawing using in-packet vertex data */
1796 case PACKET3_3D_DRAW_IMMD_2:
1797 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1798 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1801 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1802 track->immd_dwords = pkt->count;
1803 r = r100_cs_track_check(p->rdev, track);
1807 /* triggers drawing using in-packet vertex data */
1808 case PACKET3_3D_DRAW_VBUF_2:
1809 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1810 r = r100_cs_track_check(p->rdev, track);
1814 /* triggers drawing of vertex buffers setup elsewhere */
1815 case PACKET3_3D_DRAW_INDX_2:
1816 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1817 r = r100_cs_track_check(p->rdev, track);
1821 /* triggers drawing using indices to vertex buffer */
1822 case PACKET3_3D_DRAW_VBUF:
1823 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1824 r = r100_cs_track_check(p->rdev, track);
1828 /* triggers drawing of vertex buffers setup elsewhere */
1829 case PACKET3_3D_DRAW_INDX:
1830 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1831 r = r100_cs_track_check(p->rdev, track);
1835 /* triggers drawing using indices to vertex buffer */
1839 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1845 int r100_cs_parse(struct radeon_cs_parser *p)
1847 struct radeon_cs_packet pkt;
1848 struct r100_cs_track *track;
1851 track = kzalloc(sizeof(*track), GFP_KERNEL);
1852 r100_cs_track_clear(p->rdev, track);
1855 r = r100_cs_packet_parse(p, &pkt, p->idx);
1859 p->idx += pkt.count + 2;
1862 if (p->rdev->family >= CHIP_R200)
1863 r = r100_cs_parse_packet0(p, &pkt,
1864 p->rdev->config.r100.reg_safe_bm,
1865 p->rdev->config.r100.reg_safe_bm_size,
1866 &r200_packet0_check);
1868 r = r100_cs_parse_packet0(p, &pkt,
1869 p->rdev->config.r100.reg_safe_bm,
1870 p->rdev->config.r100.reg_safe_bm_size,
1871 &r100_packet0_check);
1876 r = r100_packet3_check(p, &pkt);
1879 DRM_ERROR("Unknown packet type %d !\n",
1886 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1892 * Global GPU functions
1894 void r100_errata(struct radeon_device *rdev)
1896 rdev->pll_errata = 0;
1898 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1899 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1902 if (rdev->family == CHIP_RV100 ||
1903 rdev->family == CHIP_RS100 ||
1904 rdev->family == CHIP_RS200) {
1905 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1909 /* Wait for vertical sync on primary CRTC */
1910 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1912 uint32_t crtc_gen_cntl, tmp;
1915 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1916 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1917 !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1920 /* Clear the CRTC_VBLANK_SAVE bit */
1921 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1922 for (i = 0; i < rdev->usec_timeout; i++) {
1923 tmp = RREG32(RADEON_CRTC_STATUS);
1924 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1931 /* Wait for vertical sync on secondary CRTC */
1932 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1934 uint32_t crtc2_gen_cntl, tmp;
1937 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1938 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1939 !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1942 /* Clear the CRTC_VBLANK_SAVE bit */
1943 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1944 for (i = 0; i < rdev->usec_timeout; i++) {
1945 tmp = RREG32(RADEON_CRTC2_STATUS);
1946 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1953 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1958 for (i = 0; i < rdev->usec_timeout; i++) {
1959 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1968 int r100_gui_wait_for_idle(struct radeon_device *rdev)
1973 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1974 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1975 " Bad things might happen.\n");
1977 for (i = 0; i < rdev->usec_timeout; i++) {
1978 tmp = RREG32(RADEON_RBBM_STATUS);
1979 if (!(tmp & RADEON_RBBM_ACTIVE)) {
1987 int r100_mc_wait_for_idle(struct radeon_device *rdev)
1992 for (i = 0; i < rdev->usec_timeout; i++) {
1993 /* read MC_STATUS */
1994 tmp = RREG32(RADEON_MC_STATUS);
1995 if (tmp & RADEON_MC_IDLE) {
2003 void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
2005 lockup->last_cp_rptr = cp->rptr;
2006 lockup->last_jiffies = jiffies;
2010 * r100_gpu_cp_is_lockup() - check if CP is lockup by recording information
2011 * @rdev: radeon device structure
2012 * @lockup: r100_gpu_lockup structure holding CP lockup tracking informations
2013 * @cp: radeon_cp structure holding CP information
2015 * We don't need to initialize the lockup tracking information as we will either
2016 * have CP rptr to a different value of jiffies wrap around which will force
2017 * initialization of the lockup tracking informations.
2019 * A possible false positivie is if we get call after while and last_cp_rptr ==
2020 * the current CP rptr, even if it's unlikely it might happen. To avoid this
2021 * if the elapsed time since last call is bigger than 2 second than we return
2022 * false and update the tracking information. Due to this the caller must call
2023 * r100_gpu_cp_is_lockup several time in less than 2sec for lockup to be reported
2024 * the fencing code should be cautious about that.
2026 * Caller should write to the ring to force CP to do something so we don't get
2027 * false positive when CP is just gived nothing to do.
2030 bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
2032 unsigned long cjiffies, elapsed;
2035 if (!time_after(cjiffies, lockup->last_jiffies)) {
2036 /* likely a wrap around */
2037 lockup->last_cp_rptr = cp->rptr;
2038 lockup->last_jiffies = jiffies;
2041 if (cp->rptr != lockup->last_cp_rptr) {
2042 /* CP is still working no lockup */
2043 lockup->last_cp_rptr = cp->rptr;
2044 lockup->last_jiffies = jiffies;
2047 elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies);
2048 if (elapsed >= 3000) {
2049 /* very likely the improbable case where current
2050 * rptr is equal to last recorded, a while ago, rptr
2051 * this is more likely a false positive update tracking
2052 * information which should force us to be recall at
2055 lockup->last_cp_rptr = cp->rptr;
2056 lockup->last_jiffies = jiffies;
2059 if (elapsed >= 1000) {
2060 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
2063 /* give a chance to the GPU ... */
2067 bool r100_gpu_is_lockup(struct radeon_device *rdev)
2072 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2073 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2074 r100_gpu_lockup_update(&rdev->config.r100.lockup, &rdev->cp);
2077 /* force CP activities */
2078 r = radeon_ring_lock(rdev, 2);
2081 radeon_ring_write(rdev, 0x80000000);
2082 radeon_ring_write(rdev, 0x80000000);
2083 radeon_ring_unlock_commit(rdev);
2085 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
2086 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, &rdev->cp);
2089 void r100_bm_disable(struct radeon_device *rdev)
2093 /* disable bus mastering */
2094 tmp = RREG32(R_000030_BUS_CNTL);
2095 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2097 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2099 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2100 tmp = RREG32(RADEON_BUS_CNTL);
2102 pci_read_config_word(rdev->pdev, 0x4, (u16*)&tmp);
2103 pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB);
2107 int r100_asic_reset(struct radeon_device *rdev)
2109 struct r100_mc_save save;
2112 r100_mc_stop(rdev, &save);
2113 status = RREG32(R_000E40_RBBM_STATUS);
2114 if (!G_000E40_GUI_ACTIVE(status)) {
2117 status = RREG32(R_000E40_RBBM_STATUS);
2118 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2120 WREG32(RADEON_CP_CSQ_CNTL, 0);
2121 tmp = RREG32(RADEON_CP_RB_CNTL);
2122 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2123 WREG32(RADEON_CP_RB_RPTR_WR, 0);
2124 WREG32(RADEON_CP_RB_WPTR, 0);
2125 WREG32(RADEON_CP_RB_CNTL, tmp);
2126 /* save PCI state */
2127 pci_save_state(rdev->pdev);
2128 /* disable bus mastering */
2129 r100_bm_disable(rdev);
2130 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2131 S_0000F0_SOFT_RESET_RE(1) |
2132 S_0000F0_SOFT_RESET_PP(1) |
2133 S_0000F0_SOFT_RESET_RB(1));
2134 RREG32(R_0000F0_RBBM_SOFT_RESET);
2136 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2138 status = RREG32(R_000E40_RBBM_STATUS);
2139 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2141 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2142 RREG32(R_0000F0_RBBM_SOFT_RESET);
2144 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2146 status = RREG32(R_000E40_RBBM_STATUS);
2147 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2148 /* restore PCI & busmastering */
2149 pci_restore_state(rdev->pdev);
2150 r100_enable_bm(rdev);
2151 /* Check if GPU is idle */
2152 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2153 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2154 dev_err(rdev->dev, "failed to reset GPU\n");
2155 rdev->gpu_lockup = true;
2158 r100_mc_resume(rdev, &save);
2159 dev_info(rdev->dev, "GPU reset succeed\n");
2163 void r100_set_common_regs(struct radeon_device *rdev)
2165 struct drm_device *dev = rdev->ddev;
2166 bool force_dac2 = false;
2169 /* set these so they don't interfere with anything */
2170 WREG32(RADEON_OV0_SCALE_CNTL, 0);
2171 WREG32(RADEON_SUBPIC_CNTL, 0);
2172 WREG32(RADEON_VIPH_CONTROL, 0);
2173 WREG32(RADEON_I2C_CNTL_1, 0);
2174 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2175 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2176 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2178 /* always set up dac2 on rn50 and some rv100 as lots
2179 * of servers seem to wire it up to a VGA port but
2180 * don't report it in the bios connector
2183 switch (dev->pdev->device) {
2192 /* DELL triple head servers */
2193 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2194 ((dev->pdev->subsystem_device == 0x016c) ||
2195 (dev->pdev->subsystem_device == 0x016d) ||
2196 (dev->pdev->subsystem_device == 0x016e) ||
2197 (dev->pdev->subsystem_device == 0x016f) ||
2198 (dev->pdev->subsystem_device == 0x0170) ||
2199 (dev->pdev->subsystem_device == 0x017d) ||
2200 (dev->pdev->subsystem_device == 0x017e) ||
2201 (dev->pdev->subsystem_device == 0x0183) ||
2202 (dev->pdev->subsystem_device == 0x018a) ||
2203 (dev->pdev->subsystem_device == 0x019a)))
2209 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2210 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2211 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2213 /* For CRT on DAC2, don't turn it on if BIOS didn't
2214 enable it, even it's detected.
2217 /* force it to crtc0 */
2218 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2219 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2220 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2222 /* set up the TV DAC */
2223 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2224 RADEON_TV_DAC_STD_MASK |
2225 RADEON_TV_DAC_RDACPD |
2226 RADEON_TV_DAC_GDACPD |
2227 RADEON_TV_DAC_BDACPD |
2228 RADEON_TV_DAC_BGADJ_MASK |
2229 RADEON_TV_DAC_DACADJ_MASK);
2230 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2231 RADEON_TV_DAC_NHOLD |
2232 RADEON_TV_DAC_STD_PS2 |
2235 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2236 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2237 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2240 /* switch PM block to ACPI mode */
2241 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2242 tmp &= ~RADEON_PM_MODE_SEL;
2243 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2250 static void r100_vram_get_type(struct radeon_device *rdev)
2254 rdev->mc.vram_is_ddr = false;
2255 if (rdev->flags & RADEON_IS_IGP)
2256 rdev->mc.vram_is_ddr = true;
2257 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2258 rdev->mc.vram_is_ddr = true;
2259 if ((rdev->family == CHIP_RV100) ||
2260 (rdev->family == CHIP_RS100) ||
2261 (rdev->family == CHIP_RS200)) {
2262 tmp = RREG32(RADEON_MEM_CNTL);
2263 if (tmp & RV100_HALF_MODE) {
2264 rdev->mc.vram_width = 32;
2266 rdev->mc.vram_width = 64;
2268 if (rdev->flags & RADEON_SINGLE_CRTC) {
2269 rdev->mc.vram_width /= 4;
2270 rdev->mc.vram_is_ddr = true;
2272 } else if (rdev->family <= CHIP_RV280) {
2273 tmp = RREG32(RADEON_MEM_CNTL);
2274 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2275 rdev->mc.vram_width = 128;
2277 rdev->mc.vram_width = 64;
2281 rdev->mc.vram_width = 128;
2285 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2290 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2292 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2293 * that is has the 2nd generation multifunction PCI interface
2295 if (rdev->family == CHIP_RV280 ||
2296 rdev->family >= CHIP_RV350) {
2297 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2298 ~RADEON_HDP_APER_CNTL);
2299 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2300 return aper_size * 2;
2303 /* Older cards have all sorts of funny issues to deal with. First
2304 * check if it's a multifunction card by reading the PCI config
2305 * header type... Limit those to one aperture size
2307 pci_read_config_byte(rdev->pdev, 0xe, &byte);
2309 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2310 DRM_INFO("Limiting VRAM to one aperture\n");
2314 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2315 * have set it up. We don't write this as it's broken on some ASICs but
2316 * we expect the BIOS to have done the right thing (might be too optimistic...)
2318 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2319 return aper_size * 2;
2323 void r100_vram_init_sizes(struct radeon_device *rdev)
2325 u64 config_aper_size;
2327 /* work out accessible VRAM */
2328 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
2329 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
2330 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2331 /* FIXME we don't use the second aperture yet when we could use it */
2332 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2333 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2334 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2335 if (rdev->flags & RADEON_IS_IGP) {
2337 /* read NB_TOM to get the amount of ram stolen for the GPU */
2338 tom = RREG32(RADEON_NB_TOM);
2339 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2340 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2341 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2343 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2344 /* Some production boards of m6 will report 0
2347 if (rdev->mc.real_vram_size == 0) {
2348 rdev->mc.real_vram_size = 8192 * 1024;
2349 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2351 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2352 * Novell bug 204882 + along with lots of ubuntu ones
2354 if (config_aper_size > rdev->mc.real_vram_size)
2355 rdev->mc.mc_vram_size = config_aper_size;
2357 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2361 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2365 temp = RREG32(RADEON_CONFIG_CNTL);
2366 if (state == false) {
2372 WREG32(RADEON_CONFIG_CNTL, temp);
2375 void r100_mc_init(struct radeon_device *rdev)
2379 r100_vram_get_type(rdev);
2380 r100_vram_init_sizes(rdev);
2381 base = rdev->mc.aper_base;
2382 if (rdev->flags & RADEON_IS_IGP)
2383 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2384 radeon_vram_location(rdev, &rdev->mc, base);
2385 if (!(rdev->flags & RADEON_IS_AGP))
2386 radeon_gtt_location(rdev, &rdev->mc);
2387 radeon_update_bandwidth_info(rdev);
2392 * Indirect registers accessor
2394 void r100_pll_errata_after_index(struct radeon_device *rdev)
2396 if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) {
2399 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2400 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2403 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2405 /* This workarounds is necessary on RV100, RS100 and RS200 chips
2406 * or the chip could hang on a subsequent access
2408 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2412 /* This function is required to workaround a hardware bug in some (all?)
2413 * revisions of the R300. This workaround should be called after every
2414 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
2415 * may not be correct.
2417 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2420 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2421 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2422 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2423 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2424 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2428 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2432 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2433 r100_pll_errata_after_index(rdev);
2434 data = RREG32(RADEON_CLOCK_CNTL_DATA);
2435 r100_pll_errata_after_data(rdev);
2439 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2441 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2442 r100_pll_errata_after_index(rdev);
2443 WREG32(RADEON_CLOCK_CNTL_DATA, v);
2444 r100_pll_errata_after_data(rdev);
2447 void r100_set_safe_registers(struct radeon_device *rdev)
2449 if (ASIC_IS_RN50(rdev)) {
2450 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2451 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2452 } else if (rdev->family < CHIP_R200) {
2453 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2454 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2456 r200_set_safe_registers(rdev);
2463 #if defined(CONFIG_DEBUG_FS)
2464 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2466 struct drm_info_node *node = (struct drm_info_node *) m->private;
2467 struct drm_device *dev = node->minor->dev;
2468 struct radeon_device *rdev = dev->dev_private;
2469 uint32_t reg, value;
2472 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2473 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2474 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2475 for (i = 0; i < 64; i++) {
2476 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2477 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2478 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2479 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2480 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2485 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2487 struct drm_info_node *node = (struct drm_info_node *) m->private;
2488 struct drm_device *dev = node->minor->dev;
2489 struct radeon_device *rdev = dev->dev_private;
2491 unsigned count, i, j;
2493 radeon_ring_free_size(rdev);
2494 rdp = RREG32(RADEON_CP_RB_RPTR);
2495 wdp = RREG32(RADEON_CP_RB_WPTR);
2496 count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2497 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2498 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2499 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2500 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2501 seq_printf(m, "%u dwords in ring\n", count);
2502 for (j = 0; j <= count; j++) {
2503 i = (rdp + j) & rdev->cp.ptr_mask;
2504 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2510 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2512 struct drm_info_node *node = (struct drm_info_node *) m->private;
2513 struct drm_device *dev = node->minor->dev;
2514 struct radeon_device *rdev = dev->dev_private;
2515 uint32_t csq_stat, csq2_stat, tmp;
2516 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2519 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2520 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2521 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2522 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2523 r_rptr = (csq_stat >> 0) & 0x3ff;
2524 r_wptr = (csq_stat >> 10) & 0x3ff;
2525 ib1_rptr = (csq_stat >> 20) & 0x3ff;
2526 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2527 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2528 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2529 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2530 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2531 seq_printf(m, "Ring rptr %u\n", r_rptr);
2532 seq_printf(m, "Ring wptr %u\n", r_wptr);
2533 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2534 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2535 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2536 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2537 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2538 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2539 seq_printf(m, "Ring fifo:\n");
2540 for (i = 0; i < 256; i++) {
2541 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2542 tmp = RREG32(RADEON_CP_CSQ_DATA);
2543 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2545 seq_printf(m, "Indirect1 fifo:\n");
2546 for (i = 256; i <= 512; i++) {
2547 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2548 tmp = RREG32(RADEON_CP_CSQ_DATA);
2549 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2551 seq_printf(m, "Indirect2 fifo:\n");
2552 for (i = 640; i < ib1_wptr; i++) {
2553 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2554 tmp = RREG32(RADEON_CP_CSQ_DATA);
2555 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2560 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2562 struct drm_info_node *node = (struct drm_info_node *) m->private;
2563 struct drm_device *dev = node->minor->dev;
2564 struct radeon_device *rdev = dev->dev_private;
2567 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2568 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2569 tmp = RREG32(RADEON_MC_FB_LOCATION);
2570 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2571 tmp = RREG32(RADEON_BUS_CNTL);
2572 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2573 tmp = RREG32(RADEON_MC_AGP_LOCATION);
2574 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2575 tmp = RREG32(RADEON_AGP_BASE);
2576 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2577 tmp = RREG32(RADEON_HOST_PATH_CNTL);
2578 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2579 tmp = RREG32(0x01D0);
2580 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2581 tmp = RREG32(RADEON_AIC_LO_ADDR);
2582 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2583 tmp = RREG32(RADEON_AIC_HI_ADDR);
2584 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2585 tmp = RREG32(0x01E4);
2586 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2590 static struct drm_info_list r100_debugfs_rbbm_list[] = {
2591 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2594 static struct drm_info_list r100_debugfs_cp_list[] = {
2595 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2596 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2599 static struct drm_info_list r100_debugfs_mc_info_list[] = {
2600 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2604 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2606 #if defined(CONFIG_DEBUG_FS)
2607 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2613 int r100_debugfs_cp_init(struct radeon_device *rdev)
2615 #if defined(CONFIG_DEBUG_FS)
2616 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2622 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2624 #if defined(CONFIG_DEBUG_FS)
2625 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2631 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2632 uint32_t tiling_flags, uint32_t pitch,
2633 uint32_t offset, uint32_t obj_size)
2635 int surf_index = reg * 16;
2638 /* r100/r200 divide by 16 */
2639 if (rdev->family < CHIP_R300)
2644 if (rdev->family <= CHIP_RS200) {
2645 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2646 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2647 flags |= RADEON_SURF_TILE_COLOR_BOTH;
2648 if (tiling_flags & RADEON_TILING_MACRO)
2649 flags |= RADEON_SURF_TILE_COLOR_MACRO;
2650 } else if (rdev->family <= CHIP_RV280) {
2651 if (tiling_flags & (RADEON_TILING_MACRO))
2652 flags |= R200_SURF_TILE_COLOR_MACRO;
2653 if (tiling_flags & RADEON_TILING_MICRO)
2654 flags |= R200_SURF_TILE_COLOR_MICRO;
2656 if (tiling_flags & RADEON_TILING_MACRO)
2657 flags |= R300_SURF_TILE_MACRO;
2658 if (tiling_flags & RADEON_TILING_MICRO)
2659 flags |= R300_SURF_TILE_MICRO;
2662 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2663 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2664 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2665 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2667 DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2668 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2669 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2670 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2674 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2676 int surf_index = reg * 16;
2677 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2680 void r100_bandwidth_update(struct radeon_device *rdev)
2682 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2683 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2684 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2685 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2686 fixed20_12 memtcas_ff[8] = {
2691 dfixed_init_half(1),
2692 dfixed_init_half(2),
2695 fixed20_12 memtcas_rs480_ff[8] = {
2701 dfixed_init_half(1),
2702 dfixed_init_half(2),
2703 dfixed_init_half(3),
2705 fixed20_12 memtcas2_ff[8] = {
2715 fixed20_12 memtrbs[8] = {
2717 dfixed_init_half(1),
2719 dfixed_init_half(2),
2721 dfixed_init_half(3),
2725 fixed20_12 memtrbs_r4xx[8] = {
2735 fixed20_12 min_mem_eff;
2736 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2737 fixed20_12 cur_latency_mclk, cur_latency_sclk;
2738 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2739 disp_drain_rate2, read_return_rate;
2740 fixed20_12 time_disp1_drop_priority;
2742 int cur_size = 16; /* in octawords */
2743 int critical_point = 0, critical_point2;
2744 /* uint32_t read_return_rate, time_disp1_drop_priority; */
2745 int stop_req, max_stop_req;
2746 struct drm_display_mode *mode1 = NULL;
2747 struct drm_display_mode *mode2 = NULL;
2748 uint32_t pixel_bytes1 = 0;
2749 uint32_t pixel_bytes2 = 0;
2751 radeon_update_display_priority(rdev);
2753 if (rdev->mode_info.crtcs[0]->base.enabled) {
2754 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2755 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2757 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2758 if (rdev->mode_info.crtcs[1]->base.enabled) {
2759 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2760 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2764 min_mem_eff.full = dfixed_const_8(0);
2766 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2767 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2768 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2769 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2770 /* check crtc enables */
2772 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2774 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2775 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2779 * determine is there is enough bw for current mode
2781 sclk_ff = rdev->pm.sclk;
2782 mclk_ff = rdev->pm.mclk;
2784 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2785 temp_ff.full = dfixed_const(temp);
2786 mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
2790 peak_disp_bw.full = 0;
2792 temp_ff.full = dfixed_const(1000);
2793 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
2794 pix_clk.full = dfixed_div(pix_clk, temp_ff);
2795 temp_ff.full = dfixed_const(pixel_bytes1);
2796 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
2799 temp_ff.full = dfixed_const(1000);
2800 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
2801 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
2802 temp_ff.full = dfixed_const(pixel_bytes2);
2803 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
2806 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
2807 if (peak_disp_bw.full >= mem_bw.full) {
2808 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2809 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2812 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
2813 temp = RREG32(RADEON_MEM_TIMING_CNTL);
2814 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2815 mem_trcd = ((temp >> 2) & 0x3) + 1;
2816 mem_trp = ((temp & 0x3)) + 1;
2817 mem_tras = ((temp & 0x70) >> 4) + 1;
2818 } else if (rdev->family == CHIP_R300 ||
2819 rdev->family == CHIP_R350) { /* r300, r350 */
2820 mem_trcd = (temp & 0x7) + 1;
2821 mem_trp = ((temp >> 8) & 0x7) + 1;
2822 mem_tras = ((temp >> 11) & 0xf) + 4;
2823 } else if (rdev->family == CHIP_RV350 ||
2824 rdev->family <= CHIP_RV380) {
2826 mem_trcd = (temp & 0x7) + 3;
2827 mem_trp = ((temp >> 8) & 0x7) + 3;
2828 mem_tras = ((temp >> 11) & 0xf) + 6;
2829 } else if (rdev->family == CHIP_R420 ||
2830 rdev->family == CHIP_R423 ||
2831 rdev->family == CHIP_RV410) {
2833 mem_trcd = (temp & 0xf) + 3;
2836 mem_trp = ((temp >> 8) & 0xf) + 3;
2839 mem_tras = ((temp >> 12) & 0x1f) + 6;
2842 } else { /* RV200, R200 */
2843 mem_trcd = (temp & 0x7) + 1;
2844 mem_trp = ((temp >> 8) & 0x7) + 1;
2845 mem_tras = ((temp >> 12) & 0xf) + 4;
2848 trcd_ff.full = dfixed_const(mem_trcd);
2849 trp_ff.full = dfixed_const(mem_trp);
2850 tras_ff.full = dfixed_const(mem_tras);
2852 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2853 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2854 data = (temp & (7 << 20)) >> 20;
2855 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2856 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2857 tcas_ff = memtcas_rs480_ff[data];
2859 tcas_ff = memtcas_ff[data];
2861 tcas_ff = memtcas2_ff[data];
2863 if (rdev->family == CHIP_RS400 ||
2864 rdev->family == CHIP_RS480) {
2865 /* extra cas latency stored in bits 23-25 0-4 clocks */
2866 data = (temp >> 23) & 0x7;
2868 tcas_ff.full += dfixed_const(data);
2871 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2872 /* on the R300, Tcas is included in Trbs.
2874 temp = RREG32(RADEON_MEM_CNTL);
2875 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2877 if (R300_MEM_USE_CD_CH_ONLY & temp) {
2878 temp = RREG32(R300_MC_IND_INDEX);
2879 temp &= ~R300_MC_IND_ADDR_MASK;
2880 temp |= R300_MC_READ_CNTL_CD_mcind;
2881 WREG32(R300_MC_IND_INDEX, temp);
2882 temp = RREG32(R300_MC_IND_DATA);
2883 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2885 temp = RREG32(R300_MC_READ_CNTL_AB);
2886 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2889 temp = RREG32(R300_MC_READ_CNTL_AB);
2890 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2892 if (rdev->family == CHIP_RV410 ||
2893 rdev->family == CHIP_R420 ||
2894 rdev->family == CHIP_R423)
2895 trbs_ff = memtrbs_r4xx[data];
2897 trbs_ff = memtrbs[data];
2898 tcas_ff.full += trbs_ff.full;
2901 sclk_eff_ff.full = sclk_ff.full;
2903 if (rdev->flags & RADEON_IS_AGP) {
2904 fixed20_12 agpmode_ff;
2905 agpmode_ff.full = dfixed_const(radeon_agpmode);
2906 temp_ff.full = dfixed_const_666(16);
2907 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
2909 /* TODO PCIE lanes may affect this - agpmode == 16?? */
2911 if (ASIC_IS_R300(rdev)) {
2912 sclk_delay_ff.full = dfixed_const(250);
2914 if ((rdev->family == CHIP_RV100) ||
2915 rdev->flags & RADEON_IS_IGP) {
2916 if (rdev->mc.vram_is_ddr)
2917 sclk_delay_ff.full = dfixed_const(41);
2919 sclk_delay_ff.full = dfixed_const(33);
2921 if (rdev->mc.vram_width == 128)
2922 sclk_delay_ff.full = dfixed_const(57);
2924 sclk_delay_ff.full = dfixed_const(41);
2928 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
2930 if (rdev->mc.vram_is_ddr) {
2931 if (rdev->mc.vram_width == 32) {
2932 k1.full = dfixed_const(40);
2935 k1.full = dfixed_const(20);
2939 k1.full = dfixed_const(40);
2943 temp_ff.full = dfixed_const(2);
2944 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
2945 temp_ff.full = dfixed_const(c);
2946 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
2947 temp_ff.full = dfixed_const(4);
2948 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
2949 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
2950 mc_latency_mclk.full += k1.full;
2952 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
2953 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
2956 HW cursor time assuming worst case of full size colour cursor.
2958 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
2959 temp_ff.full += trcd_ff.full;
2960 if (temp_ff.full < tras_ff.full)
2961 temp_ff.full = tras_ff.full;
2962 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
2964 temp_ff.full = dfixed_const(cur_size);
2965 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
2967 Find the total latency for the display data.
2969 disp_latency_overhead.full = dfixed_const(8);
2970 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
2971 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2972 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
2974 if (mc_latency_mclk.full > mc_latency_sclk.full)
2975 disp_latency.full = mc_latency_mclk.full;
2977 disp_latency.full = mc_latency_sclk.full;
2979 /* setup Max GRPH_STOP_REQ default value */
2980 if (ASIC_IS_RV100(rdev))
2981 max_stop_req = 0x5c;
2983 max_stop_req = 0x7c;
2987 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2988 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2990 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
2992 if (stop_req > max_stop_req)
2993 stop_req = max_stop_req;
2996 Find the drain rate of the display buffer.
2998 temp_ff.full = dfixed_const((16/pixel_bytes1));
2999 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
3002 Find the critical point of the display buffer.
3004 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
3005 crit_point_ff.full += dfixed_const_half(0);
3007 critical_point = dfixed_trunc(crit_point_ff);
3009 if (rdev->disp_priority == 2) {
3014 The critical point should never be above max_stop_req-4. Setting
3015 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3017 if (max_stop_req - critical_point < 4)
3020 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3021 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3022 critical_point = 0x10;
3025 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3026 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3027 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3028 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3029 if ((rdev->family == CHIP_R350) &&
3030 (stop_req > 0x15)) {
3033 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3034 temp |= RADEON_GRPH_BUFFER_SIZE;
3035 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
3036 RADEON_GRPH_CRITICAL_AT_SOF |
3037 RADEON_GRPH_STOP_CNTL);
3039 Write the result into the register.
3041 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3042 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3045 if ((rdev->family == CHIP_RS400) ||
3046 (rdev->family == CHIP_RS480)) {
3047 /* attempt to program RS400 disp regs correctly ??? */
3048 temp = RREG32(RS400_DISP1_REG_CNTL);
3049 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3050 RS400_DISP1_STOP_REQ_LEVEL_MASK);
3051 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3052 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3053 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3054 temp = RREG32(RS400_DMIF_MEM_CNTL1);
3055 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3056 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3057 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3058 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3059 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3063 DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
3064 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
3065 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3070 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3072 if (stop_req > max_stop_req)
3073 stop_req = max_stop_req;
3076 Find the drain rate of the display buffer.
3078 temp_ff.full = dfixed_const((16/pixel_bytes2));
3079 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3081 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3082 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3083 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3084 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3085 if ((rdev->family == CHIP_R350) &&
3086 (stop_req > 0x15)) {
3089 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3090 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3091 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
3092 RADEON_GRPH_CRITICAL_AT_SOF |
3093 RADEON_GRPH_STOP_CNTL);
3095 if ((rdev->family == CHIP_RS100) ||
3096 (rdev->family == CHIP_RS200))
3097 critical_point2 = 0;
3099 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3100 temp_ff.full = dfixed_const(temp);
3101 temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3102 if (sclk_ff.full < temp_ff.full)
3103 temp_ff.full = sclk_ff.full;
3105 read_return_rate.full = temp_ff.full;
3108 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3109 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3111 time_disp1_drop_priority.full = 0;
3113 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3114 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3115 crit_point_ff.full += dfixed_const_half(0);
3117 critical_point2 = dfixed_trunc(crit_point_ff);
3119 if (rdev->disp_priority == 2) {
3120 critical_point2 = 0;
3123 if (max_stop_req - critical_point2 < 4)
3124 critical_point2 = 0;
3128 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3129 /* some R300 cards have problem with this set to 0 */
3130 critical_point2 = 0x10;
3133 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3134 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3136 if ((rdev->family == CHIP_RS400) ||
3137 (rdev->family == CHIP_RS480)) {
3139 /* attempt to program RS400 disp2 regs correctly ??? */
3140 temp = RREG32(RS400_DISP2_REQ_CNTL1);
3141 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3142 RS400_DISP2_STOP_REQ_LEVEL_MASK);
3143 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3144 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3145 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3146 temp = RREG32(RS400_DISP2_REQ_CNTL2);
3147 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3148 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3149 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3150 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3151 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3153 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3154 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3155 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
3156 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3159 DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
3160 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3164 static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
3166 DRM_ERROR("pitch %d\n", t->pitch);
3167 DRM_ERROR("use_pitch %d\n", t->use_pitch);
3168 DRM_ERROR("width %d\n", t->width);
3169 DRM_ERROR("width_11 %d\n", t->width_11);
3170 DRM_ERROR("height %d\n", t->height);
3171 DRM_ERROR("height_11 %d\n", t->height_11);
3172 DRM_ERROR("num levels %d\n", t->num_levels);
3173 DRM_ERROR("depth %d\n", t->txdepth);
3174 DRM_ERROR("bpp %d\n", t->cpp);
3175 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
3176 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
3177 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
3178 DRM_ERROR("compress format %d\n", t->compress_format);
3181 static int r100_cs_track_cube(struct radeon_device *rdev,
3182 struct r100_cs_track *track, unsigned idx)
3184 unsigned face, w, h;
3185 struct radeon_bo *cube_robj;
3188 for (face = 0; face < 5; face++) {
3189 cube_robj = track->textures[idx].cube_info[face].robj;
3190 w = track->textures[idx].cube_info[face].width;
3191 h = track->textures[idx].cube_info[face].height;
3194 size *= track->textures[idx].cpp;
3196 size += track->textures[idx].cube_info[face].offset;
3198 if (size > radeon_bo_size(cube_robj)) {
3199 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
3200 size, radeon_bo_size(cube_robj));
3201 r100_cs_track_texture_print(&track->textures[idx]);
3208 static int r100_track_compress_size(int compress_format, int w, int h)
3210 int block_width, block_height, block_bytes;
3211 int wblocks, hblocks;
3218 switch (compress_format) {
3219 case R100_TRACK_COMP_DXT1:
3224 case R100_TRACK_COMP_DXT35:
3230 hblocks = (h + block_height - 1) / block_height;
3231 wblocks = (w + block_width - 1) / block_width;
3232 if (wblocks < min_wblocks)
3233 wblocks = min_wblocks;
3234 sz = wblocks * hblocks * block_bytes;
3238 static int r100_cs_track_texture_check(struct radeon_device *rdev,
3239 struct r100_cs_track *track)
3241 struct radeon_bo *robj;
3243 unsigned u, i, w, h, d;
3246 for (u = 0; u < track->num_texture; u++) {
3247 if (!track->textures[u].enabled)
3249 robj = track->textures[u].robj;
3251 DRM_ERROR("No texture bound to unit %u\n", u);
3255 for (i = 0; i <= track->textures[u].num_levels; i++) {
3256 if (track->textures[u].use_pitch) {
3257 if (rdev->family < CHIP_R300)
3258 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
3260 w = track->textures[u].pitch / (1 << i);
3262 w = track->textures[u].width;
3263 if (rdev->family >= CHIP_RV515)
3264 w |= track->textures[u].width_11;
3266 if (track->textures[u].roundup_w)
3267 w = roundup_pow_of_two(w);
3269 h = track->textures[u].height;
3270 if (rdev->family >= CHIP_RV515)
3271 h |= track->textures[u].height_11;
3273 if (track->textures[u].roundup_h)
3274 h = roundup_pow_of_two(h);
3275 if (track->textures[u].tex_coord_type == 1) {
3276 d = (1 << track->textures[u].txdepth) / (1 << i);
3282 if (track->textures[u].compress_format) {
3284 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
3285 /* compressed textures are block based */
3289 size *= track->textures[u].cpp;
3291 switch (track->textures[u].tex_coord_type) {
3296 if (track->separate_cube) {
3297 ret = r100_cs_track_cube(rdev, track, u);
3304 DRM_ERROR("Invalid texture coordinate type %u for unit "
3305 "%u\n", track->textures[u].tex_coord_type, u);
3308 if (size > radeon_bo_size(robj)) {
3309 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
3310 "%lu\n", u, size, radeon_bo_size(robj));
3311 r100_cs_track_texture_print(&track->textures[u]);
3318 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
3325 for (i = 0; i < track->num_cb; i++) {
3326 if (track->cb[i].robj == NULL) {
3327 if (!(track->fastfill || track->color_channel_mask ||
3328 track->blend_read_enable)) {
3331 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
3334 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
3335 size += track->cb[i].offset;
3336 if (size > radeon_bo_size(track->cb[i].robj)) {
3337 DRM_ERROR("[drm] Buffer too small for color buffer %d "
3338 "(need %lu have %lu) !\n", i, size,
3339 radeon_bo_size(track->cb[i].robj));
3340 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
3341 i, track->cb[i].pitch, track->cb[i].cpp,
3342 track->cb[i].offset, track->maxy);
3346 if (track->z_enabled) {
3347 if (track->zb.robj == NULL) {
3348 DRM_ERROR("[drm] No buffer for z buffer !\n");
3351 size = track->zb.pitch * track->zb.cpp * track->maxy;
3352 size += track->zb.offset;
3353 if (size > radeon_bo_size(track->zb.robj)) {
3354 DRM_ERROR("[drm] Buffer too small for z buffer "
3355 "(need %lu have %lu) !\n", size,
3356 radeon_bo_size(track->zb.robj));
3357 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
3358 track->zb.pitch, track->zb.cpp,
3359 track->zb.offset, track->maxy);
3363 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
3364 if (track->vap_vf_cntl & (1 << 14)) {
3365 nverts = track->vap_alt_nverts;
3367 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
3369 switch (prim_walk) {
3371 for (i = 0; i < track->num_arrays; i++) {
3372 size = track->arrays[i].esize * track->max_indx * 4;
3373 if (track->arrays[i].robj == NULL) {
3374 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3375 "bound\n", prim_walk, i);
3378 if (size > radeon_bo_size(track->arrays[i].robj)) {
3379 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3380 "need %lu dwords have %lu dwords\n",
3381 prim_walk, i, size >> 2,
3382 radeon_bo_size(track->arrays[i].robj)
3384 DRM_ERROR("Max indices %u\n", track->max_indx);
3390 for (i = 0; i < track->num_arrays; i++) {
3391 size = track->arrays[i].esize * (nverts - 1) * 4;
3392 if (track->arrays[i].robj == NULL) {
3393 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3394 "bound\n", prim_walk, i);
3397 if (size > radeon_bo_size(track->arrays[i].robj)) {
3398 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3399 "need %lu dwords have %lu dwords\n",
3400 prim_walk, i, size >> 2,
3401 radeon_bo_size(track->arrays[i].robj)
3408 size = track->vtx_size * nverts;
3409 if (size != track->immd_dwords) {
3410 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
3411 track->immd_dwords, size);
3412 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
3413 nverts, track->vtx_size);
3418 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3422 return r100_cs_track_texture_check(rdev, track);
3425 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
3429 if (rdev->family < CHIP_R300) {
3431 if (rdev->family <= CHIP_RS200)
3432 track->num_texture = 3;
3434 track->num_texture = 6;
3436 track->separate_cube = 1;
3439 track->num_texture = 16;
3441 track->separate_cube = 0;
3444 for (i = 0; i < track->num_cb; i++) {
3445 track->cb[i].robj = NULL;
3446 track->cb[i].pitch = 8192;
3447 track->cb[i].cpp = 16;
3448 track->cb[i].offset = 0;
3450 track->z_enabled = true;
3451 track->zb.robj = NULL;
3452 track->zb.pitch = 8192;
3454 track->zb.offset = 0;
3455 track->vtx_size = 0x7F;
3456 track->immd_dwords = 0xFFFFFFFFUL;
3457 track->num_arrays = 11;
3458 track->max_indx = 0x00FFFFFFUL;
3459 for (i = 0; i < track->num_arrays; i++) {
3460 track->arrays[i].robj = NULL;
3461 track->arrays[i].esize = 0x7F;
3463 for (i = 0; i < track->num_texture; i++) {
3464 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
3465 track->textures[i].pitch = 16536;
3466 track->textures[i].width = 16536;
3467 track->textures[i].height = 16536;
3468 track->textures[i].width_11 = 1 << 11;
3469 track->textures[i].height_11 = 1 << 11;
3470 track->textures[i].num_levels = 12;
3471 if (rdev->family <= CHIP_RS200) {
3472 track->textures[i].tex_coord_type = 0;
3473 track->textures[i].txdepth = 0;
3475 track->textures[i].txdepth = 16;
3476 track->textures[i].tex_coord_type = 1;
3478 track->textures[i].cpp = 64;
3479 track->textures[i].robj = NULL;
3480 /* CS IB emission code makes sure texture unit are disabled */
3481 track->textures[i].enabled = false;
3482 track->textures[i].roundup_w = true;
3483 track->textures[i].roundup_h = true;
3484 if (track->separate_cube)
3485 for (face = 0; face < 5; face++) {
3486 track->textures[i].cube_info[face].robj = NULL;
3487 track->textures[i].cube_info[face].width = 16536;
3488 track->textures[i].cube_info[face].height = 16536;
3489 track->textures[i].cube_info[face].offset = 0;
3494 int r100_ring_test(struct radeon_device *rdev)
3501 r = radeon_scratch_get(rdev, &scratch);
3503 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3506 WREG32(scratch, 0xCAFEDEAD);
3507 r = radeon_ring_lock(rdev, 2);
3509 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3510 radeon_scratch_free(rdev, scratch);
3513 radeon_ring_write(rdev, PACKET0(scratch, 0));
3514 radeon_ring_write(rdev, 0xDEADBEEF);
3515 radeon_ring_unlock_commit(rdev);
3516 for (i = 0; i < rdev->usec_timeout; i++) {
3517 tmp = RREG32(scratch);
3518 if (tmp == 0xDEADBEEF) {
3523 if (i < rdev->usec_timeout) {
3524 DRM_INFO("ring test succeeded in %d usecs\n", i);
3526 DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
3530 radeon_scratch_free(rdev, scratch);
3534 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3536 radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3537 radeon_ring_write(rdev, ib->gpu_addr);
3538 radeon_ring_write(rdev, ib->length_dw);
3541 int r100_ib_test(struct radeon_device *rdev)
3543 struct radeon_ib *ib;
3549 r = radeon_scratch_get(rdev, &scratch);
3551 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3554 WREG32(scratch, 0xCAFEDEAD);
3555 r = radeon_ib_get(rdev, &ib);
3559 ib->ptr[0] = PACKET0(scratch, 0);
3560 ib->ptr[1] = 0xDEADBEEF;
3561 ib->ptr[2] = PACKET2(0);
3562 ib->ptr[3] = PACKET2(0);
3563 ib->ptr[4] = PACKET2(0);
3564 ib->ptr[5] = PACKET2(0);
3565 ib->ptr[6] = PACKET2(0);
3566 ib->ptr[7] = PACKET2(0);
3568 r = radeon_ib_schedule(rdev, ib);
3570 radeon_scratch_free(rdev, scratch);
3571 radeon_ib_free(rdev, &ib);
3574 r = radeon_fence_wait(ib->fence, false);
3578 for (i = 0; i < rdev->usec_timeout; i++) {
3579 tmp = RREG32(scratch);
3580 if (tmp == 0xDEADBEEF) {
3585 if (i < rdev->usec_timeout) {
3586 DRM_INFO("ib test succeeded in %u usecs\n", i);
3588 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
3592 radeon_scratch_free(rdev, scratch);
3593 radeon_ib_free(rdev, &ib);
3597 void r100_ib_fini(struct radeon_device *rdev)
3599 radeon_ib_pool_fini(rdev);
3602 int r100_ib_init(struct radeon_device *rdev)
3606 r = radeon_ib_pool_init(rdev);
3608 dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r);
3612 r = r100_ib_test(rdev);
3614 dev_err(rdev->dev, "failled testing IB (%d).\n", r);
3621 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3623 /* Shutdown CP we shouldn't need to do that but better be safe than
3626 rdev->cp.ready = false;
3627 WREG32(R_000740_CP_CSQ_CNTL, 0);
3629 /* Save few CRTC registers */
3630 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3631 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3632 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3633 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3634 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3635 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3636 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3639 /* Disable VGA aperture access */
3640 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3641 /* Disable cursor, overlay, crtc */
3642 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3643 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3644 S_000054_CRTC_DISPLAY_DIS(1));
3645 WREG32(R_000050_CRTC_GEN_CNTL,
3646 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3647 S_000050_CRTC_DISP_REQ_EN_B(1));
3648 WREG32(R_000420_OV0_SCALE_CNTL,
3649 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3650 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3651 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3652 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3653 S_000360_CUR2_LOCK(1));
3654 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3655 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3656 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3657 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3658 WREG32(R_000360_CUR2_OFFSET,
3659 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3663 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3665 /* Update base address for crtc */
3666 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3667 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3668 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3670 /* Restore CRTC registers */
3671 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3672 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3673 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3674 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3675 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3679 void r100_vga_render_disable(struct radeon_device *rdev)
3683 tmp = RREG8(R_0003C2_GENMO_WT);
3684 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3687 static void r100_debugfs(struct radeon_device *rdev)
3691 r = r100_debugfs_mc_info_init(rdev);
3693 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3696 static void r100_mc_program(struct radeon_device *rdev)
3698 struct r100_mc_save save;
3700 /* Stops all mc clients */
3701 r100_mc_stop(rdev, &save);
3702 if (rdev->flags & RADEON_IS_AGP) {
3703 WREG32(R_00014C_MC_AGP_LOCATION,
3704 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3705 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3706 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3707 if (rdev->family > CHIP_RV200)
3708 WREG32(R_00015C_AGP_BASE_2,
3709 upper_32_bits(rdev->mc.agp_base) & 0xff);
3711 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3712 WREG32(R_000170_AGP_BASE, 0);
3713 if (rdev->family > CHIP_RV200)
3714 WREG32(R_00015C_AGP_BASE_2, 0);
3716 /* Wait for mc idle */
3717 if (r100_mc_wait_for_idle(rdev))
3718 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3719 /* Program MC, should be a 32bits limited address space */
3720 WREG32(R_000148_MC_FB_LOCATION,
3721 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3722 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3723 r100_mc_resume(rdev, &save);
3726 void r100_clock_startup(struct radeon_device *rdev)
3730 if (radeon_dynclks != -1 && radeon_dynclks)
3731 radeon_legacy_set_clock_gating(rdev, 1);
3732 /* We need to force on some of the block */
3733 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3734 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3735 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3736 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3737 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3740 static int r100_startup(struct radeon_device *rdev)
3744 /* set common regs */
3745 r100_set_common_regs(rdev);
3747 r100_mc_program(rdev);
3749 r100_clock_startup(rdev);
3750 /* Initialize GPU configuration (# pipes, ...) */
3751 // r100_gpu_init(rdev);
3752 /* Initialize GART (initialize after TTM so we can allocate
3753 * memory through TTM but finalize after TTM) */
3754 r100_enable_bm(rdev);
3755 if (rdev->flags & RADEON_IS_PCI) {
3756 r = r100_pci_gart_enable(rdev);
3762 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3763 /* 1M ring buffer */
3764 r = r100_cp_init(rdev, 1024 * 1024);
3766 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
3769 r = r100_wb_init(rdev);
3771 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
3772 r = r100_ib_init(rdev);
3774 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
3780 int r100_resume(struct radeon_device *rdev)
3782 /* Make sur GART are not working */
3783 if (rdev->flags & RADEON_IS_PCI)
3784 r100_pci_gart_disable(rdev);
3785 /* Resume clock before doing reset */
3786 r100_clock_startup(rdev);
3787 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3788 if (radeon_asic_reset(rdev)) {
3789 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3790 RREG32(R_000E40_RBBM_STATUS),
3791 RREG32(R_0007C0_CP_STAT));
3794 radeon_combios_asic_init(rdev->ddev);
3795 /* Resume clock after posting */
3796 r100_clock_startup(rdev);
3797 /* Initialize surface registers */
3798 radeon_surface_init(rdev);
3799 return r100_startup(rdev);
3802 int r100_suspend(struct radeon_device *rdev)
3804 r100_cp_disable(rdev);
3805 r100_wb_disable(rdev);
3806 r100_irq_disable(rdev);
3807 if (rdev->flags & RADEON_IS_PCI)
3808 r100_pci_gart_disable(rdev);
3812 void r100_fini(struct radeon_device *rdev)
3814 radeon_pm_fini(rdev);
3818 radeon_gem_fini(rdev);
3819 if (rdev->flags & RADEON_IS_PCI)
3820 r100_pci_gart_fini(rdev);
3821 radeon_agp_fini(rdev);
3822 radeon_irq_kms_fini(rdev);
3823 radeon_fence_driver_fini(rdev);
3824 radeon_bo_fini(rdev);
3825 radeon_atombios_fini(rdev);
3830 int r100_init(struct radeon_device *rdev)
3834 /* Register debugfs file specific to this group of asics */
3837 r100_vga_render_disable(rdev);
3838 /* Initialize scratch registers */
3839 radeon_scratch_init(rdev);
3840 /* Initialize surface registers */
3841 radeon_surface_init(rdev);
3842 /* TODO: disable VGA need to use VGA request */
3844 if (!radeon_get_bios(rdev)) {
3845 if (ASIC_IS_AVIVO(rdev))
3848 if (rdev->is_atom_bios) {
3849 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
3852 r = radeon_combios_init(rdev);
3856 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3857 if (radeon_asic_reset(rdev)) {
3859 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3860 RREG32(R_000E40_RBBM_STATUS),
3861 RREG32(R_0007C0_CP_STAT));
3863 /* check if cards are posted or not */
3864 if (radeon_boot_test_post_card(rdev) == false)
3866 /* Set asic errata */
3868 /* Initialize clocks */
3869 radeon_get_clock_info(rdev->ddev);
3870 /* Initialize power management */
3871 radeon_pm_init(rdev);
3872 /* initialize AGP */
3873 if (rdev->flags & RADEON_IS_AGP) {
3874 r = radeon_agp_init(rdev);
3876 radeon_agp_disable(rdev);
3879 /* initialize VRAM */
3882 r = radeon_fence_driver_init(rdev);
3885 r = radeon_irq_kms_init(rdev);
3888 /* Memory manager */
3889 r = radeon_bo_init(rdev);
3892 if (rdev->flags & RADEON_IS_PCI) {
3893 r = r100_pci_gart_init(rdev);
3897 r100_set_safe_registers(rdev);
3898 rdev->accel_working = true;
3899 r = r100_startup(rdev);
3901 /* Somethings want wront with the accel init stop accel */
3902 dev_err(rdev->dev, "Disabling GPU acceleration\n");
3906 radeon_irq_kms_fini(rdev);
3907 if (rdev->flags & RADEON_IS_PCI)
3908 r100_pci_gart_fini(rdev);
3909 rdev->accel_working = false;