SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/nouveau/nv50_display.c

   1 /*
   2  * Copyright (C) 2008 Maarten Maathuis.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include "nv50_display.h"
  28 #include "nouveau_crtc.h"
  29 #include "nouveau_encoder.h"
  30 #include "nouveau_connector.h"
  31 #include "nouveau_fb.h"
  32 #include "nouveau_fbcon.h"
  33 #include "drm_crtc_helper.h"
  34
  35 static void
  36 nv50_evo_channel_del(struct nouveau_channel **pchan)
  37 {
  38         struct nouveau_channel *chan = *pchan;
  39
  40         if (!chan)
  41                 return;
  42         *pchan = NULL;
  43
  44         nouveau_gpuobj_channel_takedown(chan);
  45         nouveau_bo_ref(NULL, &chan->pushbuf_bo);
  46
  47         if (chan->user)
  48                 iounmap(chan->user);
  49
  50         kfree(chan);
  51 }
  52
  53 static int
  54 nv50_evo_dmaobj_new(struct nouveau_channel *evo, uint32_t class, uint32_t name,
  55                     uint32_t tile_flags, uint32_t magic_flags,
  56                     uint32_t offset, uint32_t limit)
  57 {
  58         struct drm_nouveau_private *dev_priv = evo->dev->dev_private;
  59         struct drm_device *dev = evo->dev;
  60         struct nouveau_gpuobj *obj = NULL;
  61         int ret;
  62
  63         ret = nouveau_gpuobj_new(dev, evo, 6*4, 32, 0, &obj);
  64         if (ret)
  65                 return ret;
  66         obj->engine = NVOBJ_ENGINE_DISPLAY;
  67
  68         ret = nouveau_gpuobj_ref_add(dev, evo, name, obj, NULL);
  69         if (ret) {
  70                 nouveau_gpuobj_del(dev, &obj);
  71                 return ret;
  72         }
  73
  74         dev_priv->engine.instmem.prepare_access(dev, true);
  75         nv_wo32(dev, obj, 0, (tile_flags << 22) | (magic_flags << 16) | class);
  76         nv_wo32(dev, obj, 1, limit);
  77         nv_wo32(dev, obj, 2, offset);
  78         nv_wo32(dev, obj, 3, 0x00000000);
  79         nv_wo32(dev, obj, 4, 0x00000000);
  80         nv_wo32(dev, obj, 5, 0x00010000);
  81         dev_priv->engine.instmem.finish_access(dev);
  82
  83         return 0;
  84 }
  85
  86 static int
  87 nv50_evo_channel_new(struct drm_device *dev, struct nouveau_channel **pchan)
  88 {
  89         struct drm_nouveau_private *dev_priv = dev->dev_private;
  90         struct nouveau_channel *chan;
  91         int ret;
  92
  93         chan = kzalloc(sizeof(struct nouveau_channel), GFP_KERNEL);
  94         if (!chan)
  95                 return -ENOMEM;
  96         *pchan = chan;
  97
  98         chan->id = -1;
  99         chan->dev = dev;
 100         chan->user_get = 4;
 101         chan->user_put = 0;
 102
 103         INIT_LIST_HEAD(&chan->ramht_refs);
 104
 105         ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, 32768, 0x1000,
 106                                      NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin);
 107         if (ret) {
 108                 NV_ERROR(dev, "Error allocating EVO channel memory: %d\n", ret);
 109                 nv50_evo_channel_del(pchan);
 110                 return ret;
 111         }
 112
 113         ret = nouveau_mem_init_heap(&chan->ramin_heap, chan->ramin->gpuobj->
 114                                     im_pramin->start, 32768);
 115         if (ret) {
 116                 NV_ERROR(dev, "Error initialising EVO PRAMIN heap: %d\n", ret);
 117                 nv50_evo_channel_del(pchan);
 118                 return ret;
 119         }
 120
 121         ret = nouveau_gpuobj_new_ref(dev, chan, chan, 0, 4096, 16,
 122                                      0, &chan->ramht);
 123         if (ret) {
 124                 NV_ERROR(dev, "Unable to allocate EVO RAMHT: %d\n", ret);
 125                 nv50_evo_channel_del(pchan);
 126                 return ret;
 127         }
 128
 129         if (dev_priv->chipset != 0x50) {
 130                 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoFB16, 0x70, 0x19,
 131                                           0, 0xffffffff);
 132                 if (ret) {
 133                         nv50_evo_channel_del(pchan);
 134                         return ret;
 135                 }
 136
 137
 138                 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoFB32, 0x7a, 0x19,
 139                                           0, 0xffffffff);
 140                 if (ret) {
 141                         nv50_evo_channel_del(pchan);
 142                         return ret;
 143                 }
 144         }
 145
 146         ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoVRAM, 0, 0x19,
 147                                   0, dev_priv->vram_size);
 148         if (ret) {
 149                 nv50_evo_channel_del(pchan);
 150                 return ret;
 151         }
 152
 153         ret = nouveau_bo_new(dev, NULL, 4096, 0, TTM_PL_FLAG_VRAM, 0, 0,
 154                              false, true, &chan->pushbuf_bo);
 155         if (ret == 0)
 156                 ret = nouveau_bo_pin(chan->pushbuf_bo, TTM_PL_FLAG_VRAM);
 157         if (ret) {
 158                 NV_ERROR(dev, "Error creating EVO DMA push buffer: %d\n", ret);
 159                 nv50_evo_channel_del(pchan);
 160                 return ret;
 161         }
 162
 163         ret = nouveau_bo_map(chan->pushbuf_bo);
 164         if (ret) {
 165                 NV_ERROR(dev, "Error mapping EVO DMA push buffer: %d\n", ret);
 166                 nv50_evo_channel_del(pchan);
 167                 return ret;
 168         }
 169
 170         chan->user = ioremap(pci_resource_start(dev->pdev, 0) +
 171                                         NV50_PDISPLAY_USER(0), PAGE_SIZE);
 172         if (!chan->user) {
 173                 NV_ERROR(dev, "Error mapping EVO control regs.\n");
 174                 nv50_evo_channel_del(pchan);
 175                 return -ENOMEM;
 176         }
 177
 178         return 0;
 179 }
 180
 181 int
 182 nv50_display_init(struct drm_device *dev)
 183 {
 184         struct drm_nouveau_private *dev_priv = dev->dev_private;
 185         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
 186         struct nouveau_channel *evo = dev_priv->evo;
 187         struct drm_connector *connector;
 188         uint32_t val, ram_amount, hpd_en[2];
 189         uint64_t start;
 190         int ret, i;
 191
 192         NV_DEBUG_KMS(dev, "\n");
 193
 194         nv_wr32(dev, 0x00610184, nv_rd32(dev, 0x00614004));
 195         /*
 196          * I think the 0x006101XX range is some kind of main control area
 197          * that enables things.
 198          */
 199         /* CRTC? */
 200         for (i = 0; i < 2; i++) {
 201                 val = nv_rd32(dev, 0x00616100 + (i * 0x800));
 202                 nv_wr32(dev, 0x00610190 + (i * 0x10), val);
 203                 val = nv_rd32(dev, 0x00616104 + (i * 0x800));
 204                 nv_wr32(dev, 0x00610194 + (i * 0x10), val);
 205                 val = nv_rd32(dev, 0x00616108 + (i * 0x800));
 206                 nv_wr32(dev, 0x00610198 + (i * 0x10), val);
 207                 val = nv_rd32(dev, 0x0061610c + (i * 0x800));
 208                 nv_wr32(dev, 0x0061019c + (i * 0x10), val);
 209         }
 210         /* DAC */
 211         for (i = 0; i < 3; i++) {
 212                 val = nv_rd32(dev, 0x0061a000 + (i * 0x800));
 213                 nv_wr32(dev, 0x006101d0 + (i * 0x04), val);
 214         }
 215         /* SOR */
 216         for (i = 0; i < 4; i++) {
 217                 val = nv_rd32(dev, 0x0061c000 + (i * 0x800));
 218                 nv_wr32(dev, 0x006101e0 + (i * 0x04), val);
 219         }
 220         /* Something not yet in use, tv-out maybe. */
 221         for (i = 0; i < 3; i++) {
 222                 val = nv_rd32(dev, 0x0061e000 + (i * 0x800));
 223                 nv_wr32(dev, 0x006101f0 + (i * 0x04), val);
 224         }
 225
 226         for (i = 0; i < 3; i++) {
 227                 nv_wr32(dev, NV50_PDISPLAY_DAC_DPMS_CTRL(i), 0x00550000 |
 228                         NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING);
 229                 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL1(i), 0x00000001);
 230         }
 231
 232         /* This used to be in crtc unblank, but seems out of place there. */
 233         nv_wr32(dev, NV50_PDISPLAY_UNK_380, 0);
 234         /* RAM is clamped to 256 MiB. */
 235         ram_amount = dev_priv->vram_size;
 236         NV_DEBUG_KMS(dev, "ram_amount %d\n", ram_amount);
 237         if (ram_amount > 256*1024*1024)
 238                 ram_amount = 256*1024*1024;
 239         nv_wr32(dev, NV50_PDISPLAY_RAM_AMOUNT, ram_amount - 1);
 240         nv_wr32(dev, NV50_PDISPLAY_UNK_388, 0x150000);
 241         nv_wr32(dev, NV50_PDISPLAY_UNK_38C, 0);
 242
 243         /* The precise purpose is unknown, i suspect it has something to do
 244          * with text mode.
 245          */
 246         if (nv_rd32(dev, NV50_PDISPLAY_INTR_1) & 0x100) {
 247                 nv_wr32(dev, NV50_PDISPLAY_INTR_1, 0x100);
 248                 nv_wr32(dev, 0x006194e8, nv_rd32(dev, 0x006194e8) & ~1);
 249                 if (!nv_wait(0x006194e8, 2, 0)) {
 250                         NV_ERROR(dev, "timeout: (0x6194e8 & 2) != 0\n");
 251                         NV_ERROR(dev, "0x6194e8 = 0x%08x\n",
 252                                                 nv_rd32(dev, 0x6194e8));
 253                         return -EBUSY;
 254                 }
 255         }
 256
 257         /* taken from nv bug #12637, attempts to un-wedge the hw if it's
 258          * stuck in some unspecified state
 259          */
 260         start = ptimer->read(dev);
 261         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x2b00);
 262         while ((val = nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0))) & 0x1e0000) {
 263                 if ((val & 0x9f0000) == 0x20000)
 264                         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
 265                                                         val | 0x800000);
 266
 267                 if ((val & 0x3f0000) == 0x30000)
 268                         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
 269                                                         val | 0x200000);
 270
 271                 if (ptimer->read(dev) - start > 1000000000ULL) {
 272                         NV_ERROR(dev, "timeout: (0x610200 & 0x1e0000) != 0\n");
 273                         NV_ERROR(dev, "0x610200 = 0x%08x\n", val);
 274                         return -EBUSY;
 275                 }
 276         }
 277
 278         nv_wr32(dev, NV50_PDISPLAY_CTRL_STATE, NV50_PDISPLAY_CTRL_STATE_ENABLE);
 279         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x1000b03);
 280         if (!nv_wait(NV50_PDISPLAY_CHANNEL_STAT(0), 0x40000000, 0x40000000)) {
 281                 NV_ERROR(dev, "timeout: (0x610200 & 0x40000000) == 0x40000000\n");
 282                 NV_ERROR(dev, "0x610200 = 0x%08x\n",
 283                           nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)));
 284                 return -EBUSY;
 285         }
 286
 287         for (i = 0; i < 2; i++) {
 288                 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0x2000);
 289                 if (!nv_wait(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
 290                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) {
 291                         NV_ERROR(dev, "timeout: CURSOR_CTRL2_STATUS == 0\n");
 292                         NV_ERROR(dev, "CURSOR_CTRL2 = 0x%08x\n",
 293                                  nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
 294                         return -EBUSY;
 295                 }
 296
 297                 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
 298                         NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_ON);
 299                 if (!nv_wait(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
 300                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS,
 301                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_ACTIVE)) {
 302                         NV_ERROR(dev, "timeout: "
 303                                       "CURSOR_CTRL2_STATUS_ACTIVE(%d)\n", i);
 304                         NV_ERROR(dev, "CURSOR_CTRL2(%d) = 0x%08x\n", i,
 305                                  nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
 306                         return -EBUSY;
 307                 }
 308         }
 309
 310         nv_wr32(dev, NV50_PDISPLAY_OBJECTS, (evo->ramin->instance >> 8) | 9);
 311
 312         /* initialise fifo */
 313         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_DMA_CB(0),
 314                 ((evo->pushbuf_bo->bo.mem.mm_node->start << PAGE_SHIFT) >> 8) |
 315                 NV50_PDISPLAY_CHANNEL_DMA_CB_LOCATION_VRAM |
 316                 NV50_PDISPLAY_CHANNEL_DMA_CB_VALID);
 317         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_UNK2(0), 0x00010000);
 318         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_UNK3(0), 0x00000002);
 319         if (!nv_wait(0x610200, 0x80000000, 0x00000000)) {
 320                 NV_ERROR(dev, "timeout: (0x610200 & 0x80000000) == 0\n");
 321                 NV_ERROR(dev, "0x610200 = 0x%08x\n", nv_rd32(dev, 0x610200));
 322                 return -EBUSY;
 323         }
 324         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
 325                 (nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)) & ~0x00000003) |
 326                  NV50_PDISPLAY_CHANNEL_STAT_DMA_ENABLED);
 327         nv_wr32(dev, NV50_PDISPLAY_USER_PUT(0), 0);
 328         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x01000003 |
 329                 NV50_PDISPLAY_CHANNEL_STAT_DMA_ENABLED);
 330         nv_wr32(dev, 0x610300, nv_rd32(dev, 0x610300) & ~1);
 331
 332         evo->dma.max = (4096/4) - 2;
 333         evo->dma.put = 0;
 334         evo->dma.cur = evo->dma.put;
 335         evo->dma.free = evo->dma.max - evo->dma.cur;
 336
 337         ret = RING_SPACE(evo, NOUVEAU_DMA_SKIPS);
 338         if (ret)
 339                 return ret;
 340
 341         for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
 342                 OUT_RING(evo, 0);
 343
 344         ret = RING_SPACE(evo, 11);
 345         if (ret)
 346                 return ret;
 347         BEGIN_RING(evo, 0, NV50_EVO_UNK84, 2);
 348         OUT_RING(evo, NV50_EVO_UNK84_NOTIFY_DISABLED);
 349         OUT_RING(evo, NV50_EVO_DMA_NOTIFY_HANDLE_NONE);
 350         BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, FB_DMA), 1);
 351         OUT_RING(evo, NV50_EVO_CRTC_FB_DMA_HANDLE_NONE);
 352         BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK0800), 1);
 353         OUT_RING(evo, 0);
 354         BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, DISPLAY_START), 1);
 355         OUT_RING(evo, 0);
 356         BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK082C), 1);
 357         OUT_RING(evo, 0);
 358         FIRE_RING(evo);
 359         if (!nv_wait(0x640004, 0xffffffff, evo->dma.put << 2))
 360                 NV_ERROR(dev, "evo pushbuf stalled\n");
 361
 362         /* enable clock change interrupts. */
 363         nv_wr32(dev, 0x610028, 0x00010001);
 364         nv_wr32(dev, NV50_PDISPLAY_INTR_EN, (NV50_PDISPLAY_INTR_EN_CLK_UNK10 |
 365                                              NV50_PDISPLAY_INTR_EN_CLK_UNK20 |
 366                                              NV50_PDISPLAY_INTR_EN_CLK_UNK40));
 367
 368         /* enable hotplug interrupts */
 369         hpd_en[0] = hpd_en[1] = 0;
 370         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 371                 struct nouveau_connector *conn = nouveau_connector(connector);
 372                 struct dcb_gpio_entry *gpio;
 373
 374                 if (conn->dcb->gpio_tag == 0xff)
 375                         continue;
 376
 377                 gpio = nouveau_bios_gpio_entry(dev, conn->dcb->gpio_tag);
 378                 if (!gpio)
 379                         continue;
 380
 381                 hpd_en[gpio->line >> 4] |= (0x00010001 << (gpio->line & 0xf));
 382         }
 383
 384         nv_wr32(dev, 0xe054, 0xffffffff);
 385         nv_wr32(dev, 0xe050, hpd_en[0]);
 386         if (dev_priv->chipset >= 0x90) {
 387                 nv_wr32(dev, 0xe074, 0xffffffff);
 388                 nv_wr32(dev, 0xe070, hpd_en[1]);
 389         }
 390
 391         return 0;
 392 }
 393
 394 static int nv50_display_disable(struct drm_device *dev)
 395 {
 396         struct drm_nouveau_private *dev_priv = dev->dev_private;
 397         struct drm_crtc *drm_crtc;
 398         int ret, i;
 399
 400         NV_DEBUG_KMS(dev, "\n");
 401
 402         list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
 403                 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
 404
 405                 nv50_crtc_blank(crtc, true);
 406         }
 407
 408         ret = RING_SPACE(dev_priv->evo, 2);
 409         if (ret == 0) {
 410                 BEGIN_RING(dev_priv->evo, 0, NV50_EVO_UPDATE, 1);
 411                 OUT_RING(dev_priv->evo, 0);
 412         }
 413         FIRE_RING(dev_priv->evo);
 414
 415         /* Almost like ack'ing a vblank interrupt, maybe in the spirit of
 416          * cleaning up?
 417          */
 418         list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
 419                 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
 420                 uint32_t mask = NV50_PDISPLAY_INTR_1_VBLANK_CRTC_(crtc->index);
 421
 422                 if (!crtc->base.enabled)
 423                         continue;
 424
 425                 nv_wr32(dev, NV50_PDISPLAY_INTR_1, mask);
 426                 if (!nv_wait(NV50_PDISPLAY_INTR_1, mask, mask)) {
 427                         NV_ERROR(dev, "timeout: (0x610024 & 0x%08x) == "
 428                                       "0x%08x\n", mask, mask);
 429                         NV_ERROR(dev, "0x610024 = 0x%08x\n",
 430                                  nv_rd32(dev, NV50_PDISPLAY_INTR_1));
 431                 }
 432         }
 433
 434         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0);
 435         nv_wr32(dev, NV50_PDISPLAY_CTRL_STATE, 0);
 436         if (!nv_wait(NV50_PDISPLAY_CHANNEL_STAT(0), 0x1e0000, 0)) {
 437                 NV_ERROR(dev, "timeout: (0x610200 & 0x1e0000) == 0\n");
 438                 NV_ERROR(dev, "0x610200 = 0x%08x\n",
 439                           nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)));
 440         }
 441
 442         for (i = 0; i < 3; i++) {
 443                 if (!nv_wait(NV50_PDISPLAY_SOR_DPMS_STATE(i),
 444                              NV50_PDISPLAY_SOR_DPMS_STATE_WAIT, 0)) {
 445                         NV_ERROR(dev, "timeout: SOR_DPMS_STATE_WAIT(%d) == 0\n", i);
 446                         NV_ERROR(dev, "SOR_DPMS_STATE(%d) = 0x%08x\n", i,
 447                                   nv_rd32(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i)));
 448                 }
 449         }
 450
 451         /* disable interrupts. */
 452         nv_wr32(dev, NV50_PDISPLAY_INTR_EN, 0x00000000);
 453
 454         /* disable hotplug interrupts */
 455         nv_wr32(dev, 0xe054, 0xffffffff);
 456         nv_wr32(dev, 0xe050, 0x00000000);
 457         if (dev_priv->chipset >= 0x90) {
 458                 nv_wr32(dev, 0xe074, 0xffffffff);
 459                 nv_wr32(dev, 0xe070, 0x00000000);
 460         }
 461         return 0;
 462 }
 463
 464 int nv50_display_create(struct drm_device *dev)
 465 {
 466         struct drm_nouveau_private *dev_priv = dev->dev_private;
 467         struct dcb_table *dcb = &dev_priv->vbios.dcb;
 468         int ret, i;
 469
 470         NV_DEBUG_KMS(dev, "\n");
 471
 472         /* init basic kernel modesetting */
 473         drm_mode_config_init(dev);
 474
 475         /* Initialise some optional connector properties. */
 476         drm_mode_create_scaling_mode_property(dev);
 477         drm_mode_create_dithering_property(dev);
 478
 479         dev->mode_config.min_width = 0;
 480         dev->mode_config.min_height = 0;
 481
 482         dev->mode_config.funcs = (void *)&nouveau_mode_config_funcs;
 483
 484         dev->mode_config.max_width = 8192;
 485         dev->mode_config.max_height = 8192;
 486
 487         dev->mode_config.fb_base = dev_priv->fb_phys;
 488
 489         /* Create EVO channel */
 490         ret = nv50_evo_channel_new(dev, &dev_priv->evo);
 491         if (ret) {
 492                 NV_ERROR(dev, "Error creating EVO channel: %d\n", ret);
 493                 return ret;
 494         }
 495
 496         /* Create CRTC objects */
 497         for (i = 0; i < 2; i++)
 498                 nv50_crtc_create(dev, i);
 499
 500         /* We setup the encoders from the BIOS table */
 501         for (i = 0 ; i < dcb->entries; i++) {
 502                 struct dcb_entry *entry = &dcb->entry[i];
 503
 504                 if (entry->location != DCB_LOC_ON_CHIP) {
 505                         NV_WARN(dev, "Off-chip encoder %d/%d unsupported\n",
 506                                 entry->type, ffs(entry->or) - 1);
 507                         continue;
 508                 }
 509
 510                 switch (entry->type) {
 511                 case OUTPUT_TMDS:
 512                 case OUTPUT_LVDS:
 513                 case OUTPUT_DP:
 514                         nv50_sor_create(dev, entry);
 515                         break;
 516                 case OUTPUT_ANALOG:
 517                         nv50_dac_create(dev, entry);
 518                         break;
 519                 default:
 520                         NV_WARN(dev, "DCB encoder %d unknown\n", entry->type);
 521                         continue;
 522                 }
 523         }
 524
 525         for (i = 0 ; i < dcb->connector.entries; i++) {
 526                 if (i != 0 && dcb->connector.entry[i].index2 ==
 527                               dcb->connector.entry[i - 1].index2)
 528                         continue;
 529                 nouveau_connector_create(dev, &dcb->connector.entry[i]);
 530         }
 531
 532         ret = nv50_display_init(dev);
 533         if (ret) {
 534                 nv50_display_destroy(dev);
 535                 return ret;
 536         }
 537
 538         return 0;
 539 }
 540
 541 int nv50_display_destroy(struct drm_device *dev)
 542 {
 543         struct drm_nouveau_private *dev_priv = dev->dev_private;
 544
 545         NV_DEBUG_KMS(dev, "\n");
 546
 547         drm_mode_config_cleanup(dev);
 548
 549         nv50_display_disable(dev);
 550         nv50_evo_channel_del(&dev_priv->evo);
 551
 552         return 0;
 553 }
 554
 555 static inline uint32_t
 556 nv50_display_mode_ctrl(struct drm_device *dev, bool sor, int or)
 557 {
 558         struct drm_nouveau_private *dev_priv = dev->dev_private;
 559         uint32_t mc;
 560
 561         if (sor) {
 562                 if (dev_priv->chipset < 0x90 ||
 563                     dev_priv->chipset == 0x92 || dev_priv->chipset == 0xa0)
 564                         mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_P(or));
 565                 else
 566                         mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_P(or));
 567         } else {
 568                 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_P(or));
 569         }
 570
 571         return mc;
 572 }
 573
 574 static int
 575 nv50_display_irq_head(struct drm_device *dev, int *phead,
 576                       struct dcb_entry **pdcbent)
 577 {
 578         struct drm_nouveau_private *dev_priv = dev->dev_private;
 579         uint32_t unk30 = nv_rd32(dev, NV50_PDISPLAY_UNK30_CTRL);
 580         uint32_t dac = 0, sor = 0;
 581         int head, i, or = 0, type = OUTPUT_ANY;
 582
 583         /* We're assuming that head 0 *or* head 1 will be active here,
 584          * and not both.  I'm not sure if the hw will even signal both
 585          * ever, but it definitely shouldn't for us as we commit each
 586          * CRTC separately, and submission will be blocked by the GPU
 587          * until we handle each in turn.
 588          */
 589         NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
 590         head = ffs((unk30 >> 9) & 3) - 1;
 591         if (head < 0)
 592                 return -EINVAL;
 593
 594         /* This assumes CRTCs are never bound to multiple encoders, which
 595          * should be the case.
 596          */
 597         for (i = 0; i < 3 && type == OUTPUT_ANY; i++) {
 598                 uint32_t mc = nv50_display_mode_ctrl(dev, false, i);
 599                 if (!(mc & (1 << head)))
 600                         continue;
 601
 602                 switch ((mc >> 8) & 0xf) {
 603                 case 0: type = OUTPUT_ANALOG; break;
 604                 case 1: type = OUTPUT_TV; break;
 605                 default:
 606                         NV_ERROR(dev, "unknown dac mode_ctrl: 0x%08x\n", dac);
 607                         return -1;
 608                 }
 609
 610                 or = i;
 611         }
 612
 613         for (i = 0; i < 4 && type == OUTPUT_ANY; i++) {
 614                 uint32_t mc = nv50_display_mode_ctrl(dev, true, i);
 615                 if (!(mc & (1 << head)))
 616                         continue;
 617
 618                 switch ((mc >> 8) & 0xf) {
 619                 case 0: type = OUTPUT_LVDS; break;
 620                 case 1: type = OUTPUT_TMDS; break;
 621                 case 2: type = OUTPUT_TMDS; break;
 622                 case 5: type = OUTPUT_TMDS; break;
 623                 case 8: type = OUTPUT_DP; break;
 624                 case 9: type = OUTPUT_DP; break;
 625                 default:
 626                         NV_ERROR(dev, "unknown sor mode_ctrl: 0x%08x\n", sor);
 627                         return -1;
 628                 }
 629
 630                 or = i;
 631         }
 632
 633         NV_DEBUG_KMS(dev, "type %d, or %d\n", type, or);
 634         if (type == OUTPUT_ANY) {
 635                 NV_ERROR(dev, "unknown encoder!!\n");
 636                 return -1;
 637         }
 638
 639         for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
 640                 struct dcb_entry *dcbent = &dev_priv->vbios.dcb.entry[i];
 641
 642                 if (dcbent->type != type)
 643                         continue;
 644
 645                 if (!(dcbent->or & (1 << or)))
 646                         continue;
 647
 648                 *phead = head;
 649                 *pdcbent = dcbent;
 650                 return 0;
 651         }
 652
 653         NV_ERROR(dev, "no DCB entry for %d %d\n", dac != 0, or);
 654         return 0;
 655 }
 656
 657 static uint32_t
 658 nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcbent,
 659                            int pxclk)
 660 {
 661         struct drm_nouveau_private *dev_priv = dev->dev_private;
 662         struct nouveau_connector *nv_connector = NULL;
 663         struct drm_encoder *encoder;
 664         struct nvbios *bios = &dev_priv->vbios;
 665         uint32_t mc, script = 0, or;
 666
 667         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 668                 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 669
 670                 if (nv_encoder->dcb != dcbent)
 671                         continue;
 672
 673                 nv_connector = nouveau_encoder_connector_get(nv_encoder);
 674                 break;
 675         }
 676
 677         or = ffs(dcbent->or) - 1;
 678         mc = nv50_display_mode_ctrl(dev, dcbent->type != OUTPUT_ANALOG, or);
 679         switch (dcbent->type) {
 680         case OUTPUT_LVDS:
 681                 script = (mc >> 8) & 0xf;
 682                 if (bios->fp_no_ddc) {
 683                         if (bios->fp.dual_link)
 684                                 script |= 0x0100;
 685                         if (bios->fp.if_is_24bit)
 686                                 script |= 0x0200;
 687                 } else {
 688                         if (pxclk >= bios->fp.duallink_transition_clk) {
 689                                 script |= 0x0100;
 690                                 if (bios->fp.strapless_is_24bit & 2)
 691                                         script |= 0x0200;
 692                         } else
 693                         if (bios->fp.strapless_is_24bit & 1)
 694                                 script |= 0x0200;
 695
 696                         if (nv_connector && nv_connector->edid &&
 697                             (nv_connector->edid->revision >= 4) &&
 698                             (nv_connector->edid->input & 0x70) >= 0x20)
 699                                 script |= 0x0200;
 700                 }
 701
 702                 if (nouveau_uscript_lvds >= 0) {
 703                         NV_INFO(dev, "override script 0x%04x with 0x%04x "
 704                                      "for output LVDS-%d\n", script,
 705                                      nouveau_uscript_lvds, or);
 706                         script = nouveau_uscript_lvds;
 707                 }
 708                 break;
 709         case OUTPUT_TMDS:
 710                 script = (mc >> 8) & 0xf;
 711                 if (pxclk >= 165000)
 712                         script |= 0x0100;
 713
 714                 if (nouveau_uscript_tmds >= 0) {
 715                         NV_INFO(dev, "override script 0x%04x with 0x%04x "
 716                                      "for output TMDS-%d\n", script,
 717                                      nouveau_uscript_tmds, or);
 718                         script = nouveau_uscript_tmds;
 719                 }
 720                 break;
 721         case OUTPUT_DP:
 722                 script = (mc >> 8) & 0xf;
 723                 break;
 724         case OUTPUT_ANALOG:
 725                 script = 0xff;
 726                 break;
 727         default:
 728                 NV_ERROR(dev, "modeset on unsupported output type!\n");
 729                 break;
 730         }
 731
 732         return script;
 733 }
 734
 735 static void
 736 nv50_display_vblank_crtc_handler(struct drm_device *dev, int crtc)
 737 {
 738         struct drm_nouveau_private *dev_priv = dev->dev_private;
 739         struct nouveau_channel *chan;
 740         struct list_head *entry, *tmp;
 741
 742         list_for_each_safe(entry, tmp, &dev_priv->vbl_waiting) {
 743                 chan = list_entry(entry, struct nouveau_channel, nvsw.vbl_wait);
 744
 745                 nouveau_bo_wr32(chan->notifier_bo, chan->nvsw.vblsem_offset,
 746                                                 chan->nvsw.vblsem_rval);
 747                 list_del(&chan->nvsw.vbl_wait);
 748         }
 749 }
 750
 751 static void
 752 nv50_display_vblank_handler(struct drm_device *dev, uint32_t intr)
 753 {
 754         intr &= NV50_PDISPLAY_INTR_1_VBLANK_CRTC;
 755
 756         if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_0)
 757                 nv50_display_vblank_crtc_handler(dev, 0);
 758
 759         if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_1)
 760                 nv50_display_vblank_crtc_handler(dev, 1);
 761
 762         nv_wr32(dev, NV50_PDISPLAY_INTR_EN, nv_rd32(dev,
 763                      NV50_PDISPLAY_INTR_EN) & ~intr);
 764         nv_wr32(dev, NV50_PDISPLAY_INTR_1, intr);
 765 }
 766
 767 static void
 768 nv50_display_unk10_handler(struct drm_device *dev)
 769 {
 770         struct dcb_entry *dcbent;
 771         int head, ret;
 772
 773         ret = nv50_display_irq_head(dev, &head, &dcbent);
 774         if (ret)
 775                 goto ack;
 776
 777         nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) & ~8);
 778
 779         nouveau_bios_run_display_table(dev, dcbent, 0, -1);
 780
 781 ack:
 782         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK10);
 783         nv_wr32(dev, 0x610030, 0x80000000);
 784 }
 785
 786 static void
 787 nv50_display_unk20_dp_hack(struct drm_device *dev, struct dcb_entry *dcb)
 788 {
 789         int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1);
 790         struct drm_encoder *encoder;
 791         uint32_t tmp, unk0 = 0, unk1 = 0;
 792
 793         if (dcb->type != OUTPUT_DP)
 794                 return;
 795
 796         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 797                 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 798
 799                 if (nv_encoder->dcb == dcb) {
 800                         unk0 = nv_encoder->dp.unk0;
 801                         unk1 = nv_encoder->dp.unk1;
 802                         break;
 803                 }
 804         }
 805
 806         if (unk0 || unk1) {
 807                 tmp  = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
 808                 tmp &= 0xfffffe03;
 809                 nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp | unk0);
 810
 811                 tmp  = nv_rd32(dev, NV50_SOR_DP_UNK128(or, link));
 812                 tmp &= 0xfef080c0;
 813                 nv_wr32(dev, NV50_SOR_DP_UNK128(or, link), tmp | unk1);
 814         }
 815 }
 816
 817 static void
 818 nv50_display_unk20_handler(struct drm_device *dev)
 819 {
 820         struct dcb_entry *dcbent;
 821         uint32_t tmp, pclk, script;
 822         int head, or, ret;
 823
 824         ret = nv50_display_irq_head(dev, &head, &dcbent);
 825         if (ret)
 826                 goto ack;
 827         or = ffs(dcbent->or) - 1;
 828         pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(head, CLOCK)) & 0x3fffff;
 829         script = nv50_display_script_select(dev, dcbent, pclk);
 830
 831         NV_DEBUG_KMS(dev, "head %d pxclk: %dKHz\n", head, pclk);
 832
 833         if (dcbent->type != OUTPUT_DP)
 834                 nouveau_bios_run_display_table(dev, dcbent, 0, -2);
 835
 836         nv50_crtc_set_clock(dev, head, pclk);
 837
 838         nouveau_bios_run_display_table(dev, dcbent, script, pclk);
 839
 840         nv50_display_unk20_dp_hack(dev, dcbent);
 841
 842         tmp = nv_rd32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(head));
 843         tmp &= ~0x000000f;
 844         nv_wr32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(head), tmp);
 845
 846         if (dcbent->type != OUTPUT_ANALOG) {
 847                 tmp = nv_rd32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or));
 848                 tmp &= ~0x00000f0f;
 849                 if (script & 0x0100)
 850                         tmp |= 0x00000101;
 851                 nv_wr32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or), tmp);
 852         } else {
 853                 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL2(or), 0);
 854         }
 855
 856 ack:
 857         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK20);
 858         nv_wr32(dev, 0x610030, 0x80000000);
 859 }
 860
 861 static void
 862 nv50_display_unk40_handler(struct drm_device *dev)
 863 {
 864         struct dcb_entry *dcbent;
 865         int head, pclk, script, ret;
 866
 867         ret = nv50_display_irq_head(dev, &head, &dcbent);
 868         if (ret)
 869                 goto ack;
 870         pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(head, CLOCK)) & 0x3fffff;
 871         script = nv50_display_script_select(dev, dcbent, pclk);
 872
 873         nouveau_bios_run_display_table(dev, dcbent, script, -pclk);
 874
 875 ack:
 876         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK40);
 877         nv_wr32(dev, 0x610030, 0x80000000);
 878         nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) | 8);
 879 }
 880
 881 void
 882 nv50_display_irq_handler_bh(struct work_struct *work)
 883 {
 884         struct drm_nouveau_private *dev_priv =
 885                 container_of(work, struct drm_nouveau_private, irq_work);
 886         struct drm_device *dev = dev_priv->dev;
 887
 888         for (;;) {
 889                 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
 890                 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
 891
 892                 NV_DEBUG_KMS(dev, "PDISPLAY_INTR_BH 0x%08x 0x%08x\n", intr0, intr1);
 893
 894                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK10)
 895                         nv50_display_unk10_handler(dev);
 896                 else
 897                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK20)
 898                         nv50_display_unk20_handler(dev);
 899                 else
 900                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK40)
 901                         nv50_display_unk40_handler(dev);
 902                 else
 903                         break;
 904         }
 905
 906         nv_wr32(dev, NV03_PMC_INTR_EN_0, 1);
 907 }
 908
 909 static void
 910 nv50_display_error_handler(struct drm_device *dev)
 911 {
 912         uint32_t addr, data;
 913
 914         nv_wr32(dev, NV50_PDISPLAY_INTR_0, 0x00010000);
 915         addr = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_ADDR);
 916         data = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_DATA);
 917
 918         NV_ERROR(dev, "EvoCh %d Mthd 0x%04x Data 0x%08x (0x%04x 0x%02x)\n",
 919                  0, addr & 0xffc, data, addr >> 16, (addr >> 12) & 0xf);
 920
 921         nv_wr32(dev, NV50_PDISPLAY_TRAPPED_ADDR, 0x90000000);
 922 }
 923
 924 void
 925 nv50_display_irq_hotplug_bh(struct work_struct *work)
 926 {
 927         struct drm_nouveau_private *dev_priv =
 928                 container_of(work, struct drm_nouveau_private, hpd_work);
 929         struct drm_device *dev = dev_priv->dev;
 930         struct drm_connector *connector;
 931         const uint32_t gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 };
 932         uint32_t unplug_mask, plug_mask, change_mask;
 933         uint32_t hpd0, hpd1 = 0;
 934
 935         hpd0 = nv_rd32(dev, 0xe054) & nv_rd32(dev, 0xe050);
 936         if (dev_priv->chipset >= 0x90)
 937                 hpd1 = nv_rd32(dev, 0xe074) & nv_rd32(dev, 0xe070);
 938
 939         plug_mask   = (hpd0 & 0x0000ffff) | (hpd1 << 16);
 940         unplug_mask = (hpd0 >> 16) | (hpd1 & 0xffff0000);
 941         change_mask = plug_mask | unplug_mask;
 942
 943         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 944                 struct drm_encoder_helper_funcs *helper;
 945                 struct nouveau_connector *nv_connector =
 946                         nouveau_connector(connector);
 947                 struct nouveau_encoder *nv_encoder;
 948                 struct dcb_gpio_entry *gpio;
 949                 uint32_t reg;
 950                 bool plugged;
 951
 952                 if (!nv_connector->dcb)
 953                         continue;
 954
 955                 gpio = nouveau_bios_gpio_entry(dev, nv_connector->dcb->gpio_tag);
 956                 if (!gpio || !(change_mask & (1 << gpio->line)))
 957                         continue;
 958
 959                 reg = nv_rd32(dev, gpio_reg[gpio->line >> 3]);
 960                 plugged = !!(reg & (4 << ((gpio->line & 7) << 2)));
 961                 NV_INFO(dev, "%splugged %s\n", plugged ? "" : "un",
 962                         drm_get_connector_name(connector)) ;
 963
 964                 if (!connector->encoder || !connector->encoder->crtc ||
 965                     !connector->encoder->crtc->enabled)
 966                         continue;
 967                 nv_encoder = nouveau_encoder(connector->encoder);
 968                 helper = connector->encoder->helper_private;
 969
 970                 if (nv_encoder->dcb->type != OUTPUT_DP)
 971                         continue;
 972
 973                 if (plugged)
 974                         helper->dpms(connector->encoder, DRM_MODE_DPMS_ON);
 975                 else
 976                         helper->dpms(connector->encoder, DRM_MODE_DPMS_OFF);
 977         }
 978
 979         nv_wr32(dev, 0xe054, nv_rd32(dev, 0xe054));
 980         if (dev_priv->chipset >= 0x90)
 981                 nv_wr32(dev, 0xe074, nv_rd32(dev, 0xe074));
 982
 983         drm_helper_hpd_irq_event(dev);
 984 }
 985
 986 void
 987 nv50_display_irq_handler(struct drm_device *dev)
 988 {
 989         struct drm_nouveau_private *dev_priv = dev->dev_private;
 990         uint32_t delayed = 0;
 991
 992         if (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_HOTPLUG) {
 993                 if (!work_pending(&dev_priv->hpd_work))
 994                         queue_work(dev_priv->wq, &dev_priv->hpd_work);
 995         }
 996
 997         while (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_DISPLAY) {
 998                 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
 999                 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
1000                 uint32_t clock;
1001
1002                 NV_DEBUG_KMS(dev, "PDISPLAY_INTR 0x%08x 0x%08x\n", intr0, intr1);
1003
1004                 if (!intr0 && !(intr1 & ~delayed))
1005                         break;
1006
1007                 if (intr0 & 0x00010000) {
1008                         nv50_display_error_handler(dev);
1009                         intr0 &= ~0x00010000;
1010                 }
1011
1012                 if (intr1 & NV50_PDISPLAY_INTR_1_VBLANK_CRTC) {
1013                         nv50_display_vblank_handler(dev, intr1);
1014                         intr1 &= ~NV50_PDISPLAY_INTR_1_VBLANK_CRTC;
1015                 }
1016
1017                 clock = (intr1 & (NV50_PDISPLAY_INTR_1_CLK_UNK10 |
1018                                   NV50_PDISPLAY_INTR_1_CLK_UNK20 |
1019                                   NV50_PDISPLAY_INTR_1_CLK_UNK40));
1020                 if (clock) {
1021                         nv_wr32(dev, NV03_PMC_INTR_EN_0, 0);
1022                         if (!work_pending(&dev_priv->irq_work))
1023                                 queue_work(dev_priv->wq, &dev_priv->irq_work);
1024                         delayed |= clock;
1025                         intr1 &= ~clock;
1026                 }
1027
1028                 if (intr0) {
1029                         NV_ERROR(dev, "unknown PDISPLAY_INTR_0: 0x%08x\n", intr0);
1030                         nv_wr32(dev, NV50_PDISPLAY_INTR_0, intr0);
1031                 }
1032
1033                 if (intr1) {
1034                         NV_ERROR(dev,
1035                                  "unknown PDISPLAY_INTR_1: 0x%08x\n", intr1);
1036                         nv_wr32(dev, NV50_PDISPLAY_INTR_1, intr1);
1037                 }
1038         }
1039 }
1040