SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/nouveau/nouveau_state.c

   1 /*
   2  * Copyright 2005 Stephane Marchesin
   3  * Copyright 2008 Stuart Bennett
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  21  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #include <linux/swab.h>
  27 #include "drmP.h"
  28 #include "drm.h"
  29 #include "drm_sarea.h"
  30 #include "drm_crtc_helper.h"
  31 #include <linux/vgaarb.h>
  32
  33 #include "nouveau_drv.h"
  34 #include "nouveau_drm.h"
  35 #include "nv50_display.h"
  36
  37 static int nouveau_stub_init(struct drm_device *dev) { return 0; }
  38 static void nouveau_stub_takedown(struct drm_device *dev) {}
  39
  40 static int nouveau_init_engine_ptrs(struct drm_device *dev)
  41 {
  42         struct drm_nouveau_private *dev_priv = dev->dev_private;
  43         struct nouveau_engine *engine = &dev_priv->engine;
  44
  45         switch (dev_priv->chipset & 0xf0) {
  46         case 0x00:
  47                 engine->instmem.init            = nv04_instmem_init;
  48                 engine->instmem.takedown        = nv04_instmem_takedown;
  49                 engine->instmem.suspend         = nv04_instmem_suspend;
  50                 engine->instmem.resume          = nv04_instmem_resume;
  51                 engine->instmem.populate        = nv04_instmem_populate;
  52                 engine->instmem.clear           = nv04_instmem_clear;
  53                 engine->instmem.bind            = nv04_instmem_bind;
  54                 engine->instmem.unbind          = nv04_instmem_unbind;
  55                 engine->instmem.prepare_access  = nv04_instmem_prepare_access;
  56                 engine->instmem.finish_access   = nv04_instmem_finish_access;
  57                 engine->mc.init                 = nv04_mc_init;
  58                 engine->mc.takedown             = nv04_mc_takedown;
  59                 engine->timer.init              = nv04_timer_init;
  60                 engine->timer.read              = nv04_timer_read;
  61                 engine->timer.takedown          = nv04_timer_takedown;
  62                 engine->fb.init                 = nv04_fb_init;
  63                 engine->fb.takedown             = nv04_fb_takedown;
  64                 engine->graph.grclass           = nv04_graph_grclass;
  65                 engine->graph.init              = nv04_graph_init;
  66                 engine->graph.takedown          = nv04_graph_takedown;
  67                 engine->graph.fifo_access       = nv04_graph_fifo_access;
  68                 engine->graph.channel           = nv04_graph_channel;
  69                 engine->graph.create_context    = nv04_graph_create_context;
  70                 engine->graph.destroy_context   = nv04_graph_destroy_context;
  71                 engine->graph.load_context      = nv04_graph_load_context;
  72                 engine->graph.unload_context    = nv04_graph_unload_context;
  73                 engine->fifo.channels           = 16;
  74                 engine->fifo.init               = nv04_fifo_init;
  75                 engine->fifo.takedown           = nouveau_stub_takedown;
  76                 engine->fifo.disable            = nv04_fifo_disable;
  77                 engine->fifo.enable             = nv04_fifo_enable;
  78                 engine->fifo.reassign           = nv04_fifo_reassign;
  79                 engine->fifo.cache_flush        = nv04_fifo_cache_flush;
  80                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
  81                 engine->fifo.channel_id         = nv04_fifo_channel_id;
  82                 engine->fifo.create_context     = nv04_fifo_create_context;
  83                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
  84                 engine->fifo.load_context       = nv04_fifo_load_context;
  85                 engine->fifo.unload_context     = nv04_fifo_unload_context;
  86                 break;
  87         case 0x10:
  88                 engine->instmem.init            = nv04_instmem_init;
  89                 engine->instmem.takedown        = nv04_instmem_takedown;
  90                 engine->instmem.suspend         = nv04_instmem_suspend;
  91                 engine->instmem.resume          = nv04_instmem_resume;
  92                 engine->instmem.populate        = nv04_instmem_populate;
  93                 engine->instmem.clear           = nv04_instmem_clear;
  94                 engine->instmem.bind            = nv04_instmem_bind;
  95                 engine->instmem.unbind          = nv04_instmem_unbind;
  96                 engine->instmem.prepare_access  = nv04_instmem_prepare_access;
  97                 engine->instmem.finish_access   = nv04_instmem_finish_access;
  98                 engine->mc.init                 = nv04_mc_init;
  99                 engine->mc.takedown             = nv04_mc_takedown;
 100                 engine->timer.init              = nv04_timer_init;
 101                 engine->timer.read              = nv04_timer_read;
 102                 engine->timer.takedown          = nv04_timer_takedown;
 103                 engine->fb.init                 = nv10_fb_init;
 104                 engine->fb.takedown             = nv10_fb_takedown;
 105                 engine->graph.grclass           = nv10_graph_grclass;
 106                 engine->graph.init              = nv10_graph_init;
 107                 engine->graph.takedown          = nv10_graph_takedown;
 108                 engine->graph.channel           = nv10_graph_channel;
 109                 engine->graph.create_context    = nv10_graph_create_context;
 110                 engine->graph.destroy_context   = nv10_graph_destroy_context;
 111                 engine->graph.fifo_access       = nv04_graph_fifo_access;
 112                 engine->graph.load_context      = nv10_graph_load_context;
 113                 engine->graph.unload_context    = nv10_graph_unload_context;
 114                 engine->fifo.channels           = 32;
 115                 engine->fifo.init               = nv10_fifo_init;
 116                 engine->fifo.takedown           = nouveau_stub_takedown;
 117                 engine->fifo.disable            = nv04_fifo_disable;
 118                 engine->fifo.enable             = nv04_fifo_enable;
 119                 engine->fifo.reassign           = nv04_fifo_reassign;
 120                 engine->fifo.cache_flush        = nv04_fifo_cache_flush;
 121                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 122                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 123                 engine->fifo.create_context     = nv10_fifo_create_context;
 124                 engine->fifo.destroy_context    = nv10_fifo_destroy_context;
 125                 engine->fifo.load_context       = nv10_fifo_load_context;
 126                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 127                 break;
 128         case 0x20:
 129                 engine->instmem.init            = nv04_instmem_init;
 130                 engine->instmem.takedown        = nv04_instmem_takedown;
 131                 engine->instmem.suspend         = nv04_instmem_suspend;
 132                 engine->instmem.resume          = nv04_instmem_resume;
 133                 engine->instmem.populate        = nv04_instmem_populate;
 134                 engine->instmem.clear           = nv04_instmem_clear;
 135                 engine->instmem.bind            = nv04_instmem_bind;
 136                 engine->instmem.unbind          = nv04_instmem_unbind;
 137                 engine->instmem.prepare_access  = nv04_instmem_prepare_access;
 138                 engine->instmem.finish_access   = nv04_instmem_finish_access;
 139                 engine->mc.init                 = nv04_mc_init;
 140                 engine->mc.takedown             = nv04_mc_takedown;
 141                 engine->timer.init              = nv04_timer_init;
 142                 engine->timer.read              = nv04_timer_read;
 143                 engine->timer.takedown          = nv04_timer_takedown;
 144                 engine->fb.init                 = nv10_fb_init;
 145                 engine->fb.takedown             = nv10_fb_takedown;
 146                 engine->graph.grclass           = nv20_graph_grclass;
 147                 engine->graph.init              = nv20_graph_init;
 148                 engine->graph.takedown          = nv20_graph_takedown;
 149                 engine->graph.channel           = nv10_graph_channel;
 150                 engine->graph.create_context    = nv20_graph_create_context;
 151                 engine->graph.destroy_context   = nv20_graph_destroy_context;
 152                 engine->graph.fifo_access       = nv04_graph_fifo_access;
 153                 engine->graph.load_context      = nv20_graph_load_context;
 154                 engine->graph.unload_context    = nv20_graph_unload_context;
 155                 engine->fifo.channels           = 32;
 156                 engine->fifo.init               = nv10_fifo_init;
 157                 engine->fifo.takedown           = nouveau_stub_takedown;
 158                 engine->fifo.disable            = nv04_fifo_disable;
 159                 engine->fifo.enable             = nv04_fifo_enable;
 160                 engine->fifo.reassign           = nv04_fifo_reassign;
 161                 engine->fifo.cache_flush        = nv04_fifo_cache_flush;
 162                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 163                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 164                 engine->fifo.create_context     = nv10_fifo_create_context;
 165                 engine->fifo.destroy_context    = nv10_fifo_destroy_context;
 166                 engine->fifo.load_context       = nv10_fifo_load_context;
 167                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 168                 break;
 169         case 0x30:
 170                 engine->instmem.init            = nv04_instmem_init;
 171                 engine->instmem.takedown        = nv04_instmem_takedown;
 172                 engine->instmem.suspend         = nv04_instmem_suspend;
 173                 engine->instmem.resume          = nv04_instmem_resume;
 174                 engine->instmem.populate        = nv04_instmem_populate;
 175                 engine->instmem.clear           = nv04_instmem_clear;
 176                 engine->instmem.bind            = nv04_instmem_bind;
 177                 engine->instmem.unbind          = nv04_instmem_unbind;
 178                 engine->instmem.prepare_access  = nv04_instmem_prepare_access;
 179                 engine->instmem.finish_access   = nv04_instmem_finish_access;
 180                 engine->mc.init                 = nv04_mc_init;
 181                 engine->mc.takedown             = nv04_mc_takedown;
 182                 engine->timer.init              = nv04_timer_init;
 183                 engine->timer.read              = nv04_timer_read;
 184                 engine->timer.takedown          = nv04_timer_takedown;
 185                 engine->fb.init                 = nv10_fb_init;
 186                 engine->fb.takedown             = nv10_fb_takedown;
 187                 engine->graph.grclass           = nv30_graph_grclass;
 188                 engine->graph.init              = nv30_graph_init;
 189                 engine->graph.takedown          = nv20_graph_takedown;
 190                 engine->graph.fifo_access       = nv04_graph_fifo_access;
 191                 engine->graph.channel           = nv10_graph_channel;
 192                 engine->graph.create_context    = nv20_graph_create_context;
 193                 engine->graph.destroy_context   = nv20_graph_destroy_context;
 194                 engine->graph.load_context      = nv20_graph_load_context;
 195                 engine->graph.unload_context    = nv20_graph_unload_context;
 196                 engine->fifo.channels           = 32;
 197                 engine->fifo.init               = nv10_fifo_init;
 198                 engine->fifo.takedown           = nouveau_stub_takedown;
 199                 engine->fifo.disable            = nv04_fifo_disable;
 200                 engine->fifo.enable             = nv04_fifo_enable;
 201                 engine->fifo.reassign           = nv04_fifo_reassign;
 202                 engine->fifo.cache_flush        = nv04_fifo_cache_flush;
 203                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 204                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 205                 engine->fifo.create_context     = nv10_fifo_create_context;
 206                 engine->fifo.destroy_context    = nv10_fifo_destroy_context;
 207                 engine->fifo.load_context       = nv10_fifo_load_context;
 208                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 209                 break;
 210         case 0x40:
 211         case 0x60:
 212                 engine->instmem.init            = nv04_instmem_init;
 213                 engine->instmem.takedown        = nv04_instmem_takedown;
 214                 engine->instmem.suspend         = nv04_instmem_suspend;
 215                 engine->instmem.resume          = nv04_instmem_resume;
 216                 engine->instmem.populate        = nv04_instmem_populate;
 217                 engine->instmem.clear           = nv04_instmem_clear;
 218                 engine->instmem.bind            = nv04_instmem_bind;
 219                 engine->instmem.unbind          = nv04_instmem_unbind;
 220                 engine->instmem.prepare_access  = nv04_instmem_prepare_access;
 221                 engine->instmem.finish_access   = nv04_instmem_finish_access;
 222                 engine->mc.init                 = nv40_mc_init;
 223                 engine->mc.takedown             = nv40_mc_takedown;
 224                 engine->timer.init              = nv04_timer_init;
 225                 engine->timer.read              = nv04_timer_read;
 226                 engine->timer.takedown          = nv04_timer_takedown;
 227                 engine->fb.init                 = nv40_fb_init;
 228                 engine->fb.takedown             = nv40_fb_takedown;
 229                 engine->graph.grclass           = nv40_graph_grclass;
 230                 engine->graph.init              = nv40_graph_init;
 231                 engine->graph.takedown          = nv40_graph_takedown;
 232                 engine->graph.fifo_access       = nv04_graph_fifo_access;
 233                 engine->graph.channel           = nv40_graph_channel;
 234                 engine->graph.create_context    = nv40_graph_create_context;
 235                 engine->graph.destroy_context   = nv40_graph_destroy_context;
 236                 engine->graph.load_context      = nv40_graph_load_context;
 237                 engine->graph.unload_context    = nv40_graph_unload_context;
 238                 engine->fifo.channels           = 32;
 239                 engine->fifo.init               = nv40_fifo_init;
 240                 engine->fifo.takedown           = nouveau_stub_takedown;
 241                 engine->fifo.disable            = nv04_fifo_disable;
 242                 engine->fifo.enable             = nv04_fifo_enable;
 243                 engine->fifo.reassign           = nv04_fifo_reassign;
 244                 engine->fifo.cache_flush        = nv04_fifo_cache_flush;
 245                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 246                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 247                 engine->fifo.create_context     = nv40_fifo_create_context;
 248                 engine->fifo.destroy_context    = nv40_fifo_destroy_context;
 249                 engine->fifo.load_context       = nv40_fifo_load_context;
 250                 engine->fifo.unload_context     = nv40_fifo_unload_context;
 251                 break;
 252         case 0x50:
 253         case 0x80: /* gotta love NVIDIA's consistency.. */
 254         case 0x90:
 255         case 0xA0:
 256                 engine->instmem.init            = nv50_instmem_init;
 257                 engine->instmem.takedown        = nv50_instmem_takedown;
 258                 engine->instmem.suspend         = nv50_instmem_suspend;
 259                 engine->instmem.resume          = nv50_instmem_resume;
 260                 engine->instmem.populate        = nv50_instmem_populate;
 261                 engine->instmem.clear           = nv50_instmem_clear;
 262                 engine->instmem.bind            = nv50_instmem_bind;
 263                 engine->instmem.unbind          = nv50_instmem_unbind;
 264                 engine->instmem.prepare_access  = nv50_instmem_prepare_access;
 265                 engine->instmem.finish_access   = nv50_instmem_finish_access;
 266                 engine->mc.init                 = nv50_mc_init;
 267                 engine->mc.takedown             = nv50_mc_takedown;
 268                 engine->timer.init              = nv04_timer_init;
 269                 engine->timer.read              = nv04_timer_read;
 270                 engine->timer.takedown          = nv04_timer_takedown;
 271                 engine->fb.init                 = nouveau_stub_init;
 272                 engine->fb.takedown             = nouveau_stub_takedown;
 273                 engine->graph.grclass           = nv50_graph_grclass;
 274                 engine->graph.init              = nv50_graph_init;
 275                 engine->graph.takedown          = nv50_graph_takedown;
 276                 engine->graph.fifo_access       = nv50_graph_fifo_access;
 277                 engine->graph.channel           = nv50_graph_channel;
 278                 engine->graph.create_context    = nv50_graph_create_context;
 279                 engine->graph.destroy_context   = nv50_graph_destroy_context;
 280                 engine->graph.load_context      = nv50_graph_load_context;
 281                 engine->graph.unload_context    = nv50_graph_unload_context;
 282                 engine->fifo.channels           = 128;
 283                 engine->fifo.init               = nv50_fifo_init;
 284                 engine->fifo.takedown           = nv50_fifo_takedown;
 285                 engine->fifo.disable            = nv04_fifo_disable;
 286                 engine->fifo.enable             = nv04_fifo_enable;
 287                 engine->fifo.reassign           = nv04_fifo_reassign;
 288                 engine->fifo.channel_id         = nv50_fifo_channel_id;
 289                 engine->fifo.create_context     = nv50_fifo_create_context;
 290                 engine->fifo.destroy_context    = nv50_fifo_destroy_context;
 291                 engine->fifo.load_context       = nv50_fifo_load_context;
 292                 engine->fifo.unload_context     = nv50_fifo_unload_context;
 293                 break;
 294         default:
 295                 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
 296                 return 1;
 297         }
 298
 299         return 0;
 300 }
 301
 302 static unsigned int
 303 nouveau_vga_set_decode(void *priv, bool state)
 304 {
 305         if (state)
 306                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 307                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 308         else
 309                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 310 }
 311
 312 static int
 313 nouveau_card_init_channel(struct drm_device *dev)
 314 {
 315         struct drm_nouveau_private *dev_priv = dev->dev_private;
 316         struct nouveau_gpuobj *gpuobj;
 317         int ret;
 318
 319         ret = nouveau_channel_alloc(dev, &dev_priv->channel,
 320                                     (struct drm_file *)-2,
 321                                     NvDmaFB, NvDmaTT);
 322         if (ret)
 323                 return ret;
 324
 325         gpuobj = NULL;
 326         ret = nouveau_gpuobj_dma_new(dev_priv->channel, NV_CLASS_DMA_IN_MEMORY,
 327                                      0, nouveau_mem_fb_amount(dev),
 328                                      NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM,
 329                                      &gpuobj);
 330         if (ret)
 331                 goto out_err;
 332
 333         ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, NvDmaVRAM,
 334                                      gpuobj, NULL);
 335         if (ret)
 336                 goto out_err;
 337
 338         gpuobj = NULL;
 339         ret = nouveau_gpuobj_gart_dma_new(dev_priv->channel, 0,
 340                                           dev_priv->gart_info.aper_size,
 341                                           NV_DMA_ACCESS_RW, &gpuobj, NULL);
 342         if (ret)
 343                 goto out_err;
 344
 345         ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, NvDmaGART,
 346                                      gpuobj, NULL);
 347         if (ret)
 348                 goto out_err;
 349
 350         return 0;
 351 out_err:
 352         nouveau_gpuobj_del(dev, &gpuobj);
 353         nouveau_channel_free(dev_priv->channel);
 354         dev_priv->channel = NULL;
 355         return ret;
 356 }
 357
 358 int
 359 nouveau_card_init(struct drm_device *dev)
 360 {
 361         struct drm_nouveau_private *dev_priv = dev->dev_private;
 362         struct nouveau_engine *engine;
 363         int ret;
 364
 365         NV_DEBUG(dev, "prev state = %d\n", dev_priv->init_state);
 366
 367         if (dev_priv->init_state == NOUVEAU_CARD_INIT_DONE)
 368                 return 0;
 369
 370         vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
 371
 372         /* Initialise internal driver API hooks */
 373         ret = nouveau_init_engine_ptrs(dev);
 374         if (ret)
 375                 goto out;
 376         engine = &dev_priv->engine;
 377         dev_priv->init_state = NOUVEAU_CARD_INIT_FAILED;
 378
 379         /* Parse BIOS tables / Run init tables if card not POSTed */
 380         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 381                 ret = nouveau_bios_init(dev);
 382                 if (ret)
 383                         goto out;
 384         }
 385
 386         ret = nouveau_gpuobj_early_init(dev);
 387         if (ret)
 388                 goto out_bios;
 389
 390         /* Initialise instance memory, must happen before mem_init so we
 391          * know exactly how much VRAM we're able to use for "normal"
 392          * purposes.
 393          */
 394         ret = engine->instmem.init(dev);
 395         if (ret)
 396                 goto out_gpuobj_early;
 397
 398         /* Setup the memory manager */
 399         ret = nouveau_mem_init(dev);
 400         if (ret)
 401                 goto out_instmem;
 402
 403         ret = nouveau_gpuobj_init(dev);
 404         if (ret)
 405                 goto out_mem;
 406
 407         /* PMC */
 408         ret = engine->mc.init(dev);
 409         if (ret)
 410                 goto out_gpuobj;
 411
 412         /* PTIMER */
 413         ret = engine->timer.init(dev);
 414         if (ret)
 415                 goto out_mc;
 416
 417         /* PFB */
 418         ret = engine->fb.init(dev);
 419         if (ret)
 420                 goto out_timer;
 421
 422         /* PGRAPH */
 423         ret = engine->graph.init(dev);
 424         if (ret)
 425                 goto out_fb;
 426
 427         /* PFIFO */
 428         ret = engine->fifo.init(dev);
 429         if (ret)
 430                 goto out_graph;
 431
 432         /* this call irq_preinstall, register irq handler and
 433          * call irq_postinstall
 434          */
 435         ret = drm_irq_install(dev);
 436         if (ret)
 437                 goto out_fifo;
 438
 439         ret = drm_vblank_init(dev, 0);
 440         if (ret)
 441                 goto out_irq;
 442
 443         /* what about PVIDEO/PCRTC/PRAMDAC etc? */
 444
 445         if (!engine->graph.accel_blocked) {
 446                 ret = nouveau_card_init_channel(dev);
 447                 if (ret)
 448                         goto out_irq;
 449         }
 450
 451         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 452                 if (dev_priv->card_type >= NV_50)
 453                         ret = nv50_display_create(dev);
 454                 else
 455                         ret = nv04_display_create(dev);
 456                 if (ret)
 457                         goto out_irq;
 458         }
 459
 460         ret = nouveau_backlight_init(dev);
 461         if (ret)
 462                 NV_ERROR(dev, "Error %d registering backlight\n", ret);
 463
 464         dev_priv->init_state = NOUVEAU_CARD_INIT_DONE;
 465
 466         if (drm_core_check_feature(dev, DRIVER_MODESET))
 467                 drm_helper_initial_config(dev);
 468
 469         return 0;
 470
 471 out_irq:
 472         drm_irq_uninstall(dev);
 473 out_fifo:
 474         engine->fifo.takedown(dev);
 475 out_graph:
 476         engine->graph.takedown(dev);
 477 out_fb:
 478         engine->fb.takedown(dev);
 479 out_timer:
 480         engine->timer.takedown(dev);
 481 out_mc:
 482         engine->mc.takedown(dev);
 483 out_gpuobj:
 484         nouveau_gpuobj_takedown(dev);
 485 out_mem:
 486         nouveau_mem_close(dev);
 487 out_instmem:
 488         engine->instmem.takedown(dev);
 489 out_gpuobj_early:
 490         nouveau_gpuobj_late_takedown(dev);
 491 out_bios:
 492         nouveau_bios_takedown(dev);
 493 out:
 494         vga_client_register(dev->pdev, NULL, NULL, NULL);
 495         return ret;
 496 }
 497
 498 static void nouveau_card_takedown(struct drm_device *dev)
 499 {
 500         struct drm_nouveau_private *dev_priv = dev->dev_private;
 501         struct nouveau_engine *engine = &dev_priv->engine;
 502
 503         NV_DEBUG(dev, "prev state = %d\n", dev_priv->init_state);
 504
 505         if (dev_priv->init_state != NOUVEAU_CARD_INIT_DOWN) {
 506                 nouveau_backlight_exit(dev);
 507
 508                 if (dev_priv->channel) {
 509                         nouveau_channel_free(dev_priv->channel);
 510                         dev_priv->channel = NULL;
 511                 }
 512
 513                 engine->fifo.takedown(dev);
 514                 engine->graph.takedown(dev);
 515                 engine->fb.takedown(dev);
 516                 engine->timer.takedown(dev);
 517                 engine->mc.takedown(dev);
 518
 519                 mutex_lock(&dev->struct_mutex);
 520                 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
 521                 mutex_unlock(&dev->struct_mutex);
 522                 nouveau_sgdma_takedown(dev);
 523
 524                 nouveau_gpuobj_takedown(dev);
 525                 nouveau_mem_close(dev);
 526                 engine->instmem.takedown(dev);
 527
 528                 if (drm_core_check_feature(dev, DRIVER_MODESET))
 529                         drm_irq_uninstall(dev);
 530
 531                 nouveau_gpuobj_late_takedown(dev);
 532                 nouveau_bios_takedown(dev);
 533
 534                 vga_client_register(dev->pdev, NULL, NULL, NULL);
 535
 536                 dev_priv->init_state = NOUVEAU_CARD_INIT_DOWN;
 537         }
 538 }
 539
 540 /* here a client dies, release the stuff that was allocated for its
 541  * file_priv */
 542 void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
 543 {
 544         nouveau_channel_cleanup(dev, file_priv);
 545 }
 546
 547 /* first module load, setup the mmio/fb mapping */
 548 /* KMS: we need mmio at load time, not when the first drm client opens. */
 549 int nouveau_firstopen(struct drm_device *dev)
 550 {
 551         return 0;
 552 }
 553
 554 /* if we have an OF card, copy vbios to RAMIN */
 555 static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
 556 {
 557 #if defined(__powerpc__)
 558         int size, i;
 559         const uint32_t *bios;
 560         struct device_node *dn = pci_device_to_OF_node(dev->pdev);
 561         if (!dn) {
 562                 NV_INFO(dev, "Unable to get the OF node\n");
 563                 return;
 564         }
 565
 566         bios = of_get_property(dn, "NVDA,BMP", &size);
 567         if (bios) {
 568                 for (i = 0; i < size; i += 4)
 569                         nv_wi32(dev, i, bios[i/4]);
 570                 NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
 571         } else {
 572                 NV_INFO(dev, "Unable to get the OF bios\n");
 573         }
 574 #endif
 575 }
 576
 577 int nouveau_load(struct drm_device *dev, unsigned long flags)
 578 {
 579         struct drm_nouveau_private *dev_priv;
 580         uint32_t reg0;
 581         resource_size_t mmio_start_offs;
 582
 583         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
 584         if (!dev_priv)
 585                 return -ENOMEM;
 586         dev->dev_private = dev_priv;
 587         dev_priv->dev = dev;
 588
 589         dev_priv->flags = flags & NOUVEAU_FLAGS;
 590         dev_priv->init_state = NOUVEAU_CARD_INIT_DOWN;
 591
 592         NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
 593                  dev->pci_vendor, dev->pci_device, dev->pdev->class);
 594
 595         dev_priv->acpi_dsm = nouveau_dsm_probe(dev);
 596
 597         if (dev_priv->acpi_dsm)
 598                 nouveau_hybrid_setup(dev);
 599
 600         dev_priv->wq = create_workqueue("nouveau");
 601         if (!dev_priv->wq)
 602                 return -EINVAL;
 603
 604         /* resource 0 is mmio regs */
 605         /* resource 1 is linear FB */
 606         /* resource 2 is RAMIN (mmio regs + 0x1000000) */
 607         /* resource 6 is bios */
 608
 609         /* map the mmio regs */
 610         mmio_start_offs = pci_resource_start(dev->pdev, 0);
 611         dev_priv->mmio = ioremap(mmio_start_offs, 0x00800000);
 612         if (!dev_priv->mmio) {
 613                 NV_ERROR(dev, "Unable to initialize the mmio mapping. "
 614                          "Please report your setup to " DRIVER_EMAIL "\n");
 615                 return -EINVAL;
 616         }
 617         NV_DEBUG(dev, "regs mapped ok at 0x%llx\n",
 618                                         (unsigned long long)mmio_start_offs);
 619
 620 #ifdef __BIG_ENDIAN
 621         /* Put the card in BE mode if it's not */
 622         if (nv_rd32(dev, NV03_PMC_BOOT_1))
 623                 nv_wr32(dev, NV03_PMC_BOOT_1, 0x00000001);
 624
 625         DRM_MEMORYBARRIER();
 626 #endif
 627
 628         /* Time to determine the card architecture */
 629         reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
 630
 631         /* We're dealing with >=NV10 */
 632         if ((reg0 & 0x0f000000) > 0) {
 633                 /* Bit 27-20 contain the architecture in hex */
 634                 dev_priv->chipset = (reg0 & 0xff00000) >> 20;
 635         /* NV04 or NV05 */
 636         } else if ((reg0 & 0xff00fff0) == 0x20004000) {
 637                 dev_priv->chipset = 0x04;
 638         } else
 639                 dev_priv->chipset = 0xff;
 640
 641         switch (dev_priv->chipset & 0xf0) {
 642         case 0x00:
 643         case 0x10:
 644         case 0x20:
 645         case 0x30:
 646                 dev_priv->card_type = dev_priv->chipset & 0xf0;
 647                 break;
 648         case 0x40:
 649         case 0x60:
 650                 dev_priv->card_type = NV_40;
 651                 break;
 652         case 0x50:
 653         case 0x80:
 654         case 0x90:
 655         case 0xa0:
 656                 dev_priv->card_type = NV_50;
 657                 break;
 658         default:
 659                 NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0);
 660                 return -EINVAL;
 661         }
 662
 663         NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
 664                 dev_priv->card_type, reg0);
 665
 666         /* map larger RAMIN aperture on NV40 cards */
 667         dev_priv->ramin  = NULL;
 668         if (dev_priv->card_type >= NV_40) {
 669                 int ramin_bar = 2;
 670                 if (pci_resource_len(dev->pdev, ramin_bar) == 0)
 671                         ramin_bar = 3;
 672
 673                 dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
 674                 dev_priv->ramin = ioremap(
 675                                 pci_resource_start(dev->pdev, ramin_bar),
 676                                 dev_priv->ramin_size);
 677                 if (!dev_priv->ramin) {
 678                         NV_ERROR(dev, "Failed to init RAMIN mapping, "
 679                                       "limited instance memory available\n");
 680                 }
 681         }
 682
 683         /* On older cards (or if the above failed), create a map covering
 684          * the BAR0 PRAMIN aperture */
 685         if (!dev_priv->ramin) {
 686                 dev_priv->ramin_size = 1 * 1024 * 1024;
 687                 dev_priv->ramin = ioremap(mmio_start_offs + NV_RAMIN,
 688                                                         dev_priv->ramin_size);
 689                 if (!dev_priv->ramin) {
 690                         NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
 691                         return -ENOMEM;
 692                 }
 693         }
 694
 695         nouveau_OF_copy_vbios_to_ramin(dev);
 696
 697         /* Special flags */
 698         if (dev->pci_device == 0x01a0)
 699                 dev_priv->flags |= NV_NFORCE;
 700         else if (dev->pci_device == 0x01f0)
 701                 dev_priv->flags |= NV_NFORCE2;
 702
 703         /* For kernel modesetting, init card now and bring up fbcon */
 704         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 705                 int ret = nouveau_card_init(dev);
 706                 if (ret)
 707                         return ret;
 708         }
 709
 710         return 0;
 711 }
 712
 713 static void nouveau_close(struct drm_device *dev)
 714 {
 715         struct drm_nouveau_private *dev_priv = dev->dev_private;
 716
 717         /* In the case of an error dev_priv may not be be allocated yet */
 718         if (dev_priv && dev_priv->card_type)
 719                 nouveau_card_takedown(dev);
 720 }
 721
 722 /* KMS: we need mmio at load time, not when the first drm client opens. */
 723 void nouveau_lastclose(struct drm_device *dev)
 724 {
 725         if (drm_core_check_feature(dev, DRIVER_MODESET))
 726                 return;
 727
 728         nouveau_close(dev);
 729 }
 730
 731 int nouveau_unload(struct drm_device *dev)
 732 {
 733         struct drm_nouveau_private *dev_priv = dev->dev_private;
 734
 735         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 736                 if (dev_priv->card_type >= NV_50)
 737                         nv50_display_destroy(dev);
 738                 else
 739                         nv04_display_destroy(dev);
 740                 nouveau_close(dev);
 741         }
 742
 743         iounmap(dev_priv->mmio);
 744         iounmap(dev_priv->ramin);
 745
 746         kfree(dev_priv);
 747         dev->dev_private = NULL;
 748         return 0;
 749 }
 750
 751 int
 752 nouveau_ioctl_card_init(struct drm_device *dev, void *data,
 753                         struct drm_file *file_priv)
 754 {
 755         return nouveau_card_init(dev);
 756 }
 757
 758 int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
 759                                                 struct drm_file *file_priv)
 760 {
 761         struct drm_nouveau_private *dev_priv = dev->dev_private;
 762         struct drm_nouveau_getparam *getparam = data;
 763
 764         NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
 765
 766         switch (getparam->param) {
 767         case NOUVEAU_GETPARAM_CHIPSET_ID:
 768                 getparam->value = dev_priv->chipset;
 769                 break;
 770         case NOUVEAU_GETPARAM_PCI_VENDOR:
 771                 getparam->value = dev->pci_vendor;
 772                 break;
 773         case NOUVEAU_GETPARAM_PCI_DEVICE:
 774                 getparam->value = dev->pci_device;
 775                 break;
 776         case NOUVEAU_GETPARAM_BUS_TYPE:
 777                 if (drm_device_is_agp(dev))
 778                         getparam->value = NV_AGP;
 779                 else if (drm_device_is_pcie(dev))
 780                         getparam->value = NV_PCIE;
 781                 else
 782                         getparam->value = NV_PCI;
 783                 break;
 784         case NOUVEAU_GETPARAM_FB_PHYSICAL:
 785                 getparam->value = dev_priv->fb_phys;
 786                 break;
 787         case NOUVEAU_GETPARAM_AGP_PHYSICAL:
 788                 getparam->value = dev_priv->gart_info.aper_base;
 789                 break;
 790         case NOUVEAU_GETPARAM_PCI_PHYSICAL:
 791                 if (dev->sg) {
 792                         getparam->value = (unsigned long)dev->sg->virtual;
 793                 } else {
 794                         NV_ERROR(dev, "Requested PCIGART address, "
 795                                         "while no PCIGART was created\n");
 796                         return -EINVAL;
 797                 }
 798                 break;
 799         case NOUVEAU_GETPARAM_FB_SIZE:
 800                 getparam->value = dev_priv->fb_available_size;
 801                 break;
 802         case NOUVEAU_GETPARAM_AGP_SIZE:
 803                 getparam->value = dev_priv->gart_info.aper_size;
 804                 break;
 805         case NOUVEAU_GETPARAM_VM_VRAM_BASE:
 806                 getparam->value = dev_priv->vm_vram_base;
 807                 break;
 808         default:
 809                 NV_ERROR(dev, "unknown parameter %lld\n", getparam->param);
 810                 return -EINVAL;
 811         }
 812
 813         return 0;
 814 }
 815
 816 int
 817 nouveau_ioctl_setparam(struct drm_device *dev, void *data,
 818                        struct drm_file *file_priv)
 819 {
 820         struct drm_nouveau_setparam *setparam = data;
 821
 822         NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
 823
 824         switch (setparam->param) {
 825         default:
 826                 NV_ERROR(dev, "unknown parameter %lld\n", setparam->param);
 827                 return -EINVAL;
 828         }
 829
 830         return 0;
 831 }
 832
 833 /* Wait until (value(reg) & mask) == val, up until timeout has hit */
 834 bool nouveau_wait_until(struct drm_device *dev, uint64_t timeout,
 835                         uint32_t reg, uint32_t mask, uint32_t val)
 836 {
 837         struct drm_nouveau_private *dev_priv = dev->dev_private;
 838         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
 839         uint64_t start = ptimer->read(dev);
 840
 841         do {
 842                 if ((nv_rd32(dev, reg) & mask) == val)
 843                         return true;
 844         } while (ptimer->read(dev) - start < timeout);
 845
 846         return false;
 847 }
 848
 849 /* Waits for PGRAPH to go completely idle */
 850 bool nouveau_wait_for_idle(struct drm_device *dev)
 851 {
 852         if (!nv_wait(NV04_PGRAPH_STATUS, 0xffffffff, 0x00000000)) {
 853                 NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n",
 854                          nv_rd32(dev, NV04_PGRAPH_STATUS));
 855                 return false;
 856         }
 857
 858         return true;
 859 }
 860