SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/i915/intel_sdvo.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2007 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  *
  25  * Authors:
  26  *      Eric Anholt <eric@anholt.net>
  27  */
  28 #include <linux/i2c.h>
  29 #include <linux/delay.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "drm_crtc.h"
  33 #include "intel_drv.h"
  34 #include "i915_drm.h"
  35 #include "i915_drv.h"
  36 #include "intel_sdvo_regs.h"
  37
  38 #undef SDVO_DEBUG
  39 #define I915_SDVO       "i915_sdvo"
  40 struct intel_sdvo_priv {
  41         u8 slave_addr;
  42
  43         /* Register for the SDVO device: SDVOB or SDVOC */
  44         int output_device;
  45
  46         /* Active outputs controlled by this SDVO output */
  47         uint16_t controlled_output;
  48
  49         /*
  50          * Capabilities of the SDVO device returned by
  51          * i830_sdvo_get_capabilities()
  52          */
  53         struct intel_sdvo_caps caps;
  54
  55         /* Pixel clock limitations reported by the SDVO device, in kHz */
  56         int pixel_clock_min, pixel_clock_max;
  57
  58         /*
  59         * For multiple function SDVO device,
  60         * this is for current attached outputs.
  61         */
  62         uint16_t attached_output;
  63
  64         /**
  65          * This is set if we're going to treat the device as TV-out.
  66          *
  67          * While we have these nice friendly flags for output types that ought
  68          * to decide this for us, the S-Video output on our HDMI+S-Video card
  69          * shows up as RGB1 (VGA).
  70          */
  71         bool is_tv;
  72
  73         /**
  74          * This is set if we treat the device as HDMI, instead of DVI.
  75          */
  76         bool is_hdmi;
  77
  78         /**
  79          * This is set if we detect output of sdvo device as LVDS.
  80          */
  81         bool is_lvds;
  82
  83         /**
  84          * This is sdvo flags for input timing.
  85          */
  86         uint8_t sdvo_flags;
  87
  88         /**
  89          * This is sdvo fixed pannel mode pointer
  90          */
  91         struct drm_display_mode *sdvo_lvds_fixed_mode;
  92
  93         /**
  94          * Returned SDTV resolutions allowed for the current format, if the
  95          * device reported it.
  96          */
  97         struct intel_sdvo_sdtv_resolution_reply sdtv_resolutions;
  98
  99         /**
 100          * Current selected TV format.
 101          *
 102          * This is stored in the same structure that's passed to the device, for
 103          * convenience.
 104          */
 105         struct intel_sdvo_tv_format tv_format;
 106
 107         /*
 108          * supported encoding mode, used to determine whether HDMI is
 109          * supported
 110          */
 111         struct intel_sdvo_encode encode;
 112
 113         /* DDC bus used by this SDVO output */
 114         uint8_t ddc_bus;
 115
 116         int save_sdvo_mult;
 117         u16 save_active_outputs;
 118         struct intel_sdvo_dtd save_input_dtd_1, save_input_dtd_2;
 119         struct intel_sdvo_dtd save_output_dtd[16];
 120         u32 save_SDVOX;
 121 };
 122
 123 static bool
 124 intel_sdvo_output_setup(struct intel_output *intel_output, uint16_t flags);
 125
 126 /**
 127  * Writes the SDVOB or SDVOC with the given value, but always writes both
 128  * SDVOB and SDVOC to work around apparent hardware issues (according to
 129  * comments in the BIOS).
 130  */
 131 static void intel_sdvo_write_sdvox(struct intel_output *intel_output, u32 val)
 132 {
 133         struct drm_device *dev = intel_output->base.dev;
 134         struct drm_i915_private *dev_priv = dev->dev_private;
 135         struct intel_sdvo_priv   *sdvo_priv = intel_output->dev_priv;
 136         u32 bval = val, cval = val;
 137         int i;
 138
 139         if (sdvo_priv->output_device == SDVOB) {
 140                 cval = I915_READ(SDVOC);
 141         } else {
 142                 bval = I915_READ(SDVOB);
 143         }
 144         /*
 145          * Write the registers twice for luck. Sometimes,
 146          * writing them only once doesn't appear to 'stick'.
 147          * The BIOS does this too. Yay, magic
 148          */
 149         for (i = 0; i < 2; i++)
 150         {
 151                 I915_WRITE(SDVOB, bval);
 152                 I915_READ(SDVOB);
 153                 I915_WRITE(SDVOC, cval);
 154                 I915_READ(SDVOC);
 155         }
 156 }
 157
 158 static bool intel_sdvo_read_byte(struct intel_output *intel_output, u8 addr,
 159                                  u8 *ch)
 160 {
 161         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
 162         u8 out_buf[2];
 163         u8 buf[2];
 164         int ret;
 165
 166         struct i2c_msg msgs[] = {
 167                 {
 168                         .addr = sdvo_priv->slave_addr >> 1,
 169                         .flags = 0,
 170                         .len = 1,
 171                         .buf = out_buf,
 172                 },
 173                 {
 174                         .addr = sdvo_priv->slave_addr >> 1,
 175                         .flags = I2C_M_RD,
 176                         .len = 1,
 177                         .buf = buf,
 178                 }
 179         };
 180
 181         out_buf[0] = addr;
 182         out_buf[1] = 0;
 183
 184         if ((ret = i2c_transfer(intel_output->i2c_bus, msgs, 2)) == 2)
 185         {
 186                 *ch = buf[0];
 187                 return true;
 188         }
 189
 190         DRM_DEBUG("i2c transfer returned %d\n", ret);
 191         return false;
 192 }
 193
 194 static bool intel_sdvo_write_byte(struct intel_output *intel_output, int addr,
 195                                   u8 ch)
 196 {
 197         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
 198         u8 out_buf[2];
 199         struct i2c_msg msgs[] = {
 200                 {
 201                         .addr = sdvo_priv->slave_addr >> 1,
 202                         .flags = 0,
 203                         .len = 2,
 204                         .buf = out_buf,
 205                 }
 206         };
 207
 208         out_buf[0] = addr;
 209         out_buf[1] = ch;
 210
 211         if (i2c_transfer(intel_output->i2c_bus, msgs, 1) == 1)
 212         {
 213                 return true;
 214         }
 215         return false;
 216 }
 217
 218 #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
 219 /** Mapping of command numbers to names, for debug output */
 220 static const struct _sdvo_cmd_name {
 221         u8 cmd;
 222         char *name;
 223 } sdvo_cmd_names[] = {
 224     SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
 225     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
 226     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
 227     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
 228     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
 229     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
 230     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
 231     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
 232     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
 233     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
 234     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
 235     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
 236     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
 237     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
 238     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
 239     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
 240     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
 241     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
 242     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
 243     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
 244     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
 245     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
 246     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
 247     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
 248     SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
 249     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
 250     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
 251     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
 252     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
 253     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
 254     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
 255     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
 256     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
 257     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
 258     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
 259     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
 260     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
 261     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
 262     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
 263     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
 264     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
 265     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
 266     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
 267     /* HDMI op code */
 268     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
 269     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
 270     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
 271     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
 272     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
 273     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
 274     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
 275     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
 276     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
 277     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
 278     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
 279     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
 280     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
 281     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
 282     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
 283     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
 284     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
 285     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
 286     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
 287     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
 288 };
 289
 290 #define SDVO_NAME(dev_priv) ((dev_priv)->output_device == SDVOB ? "SDVOB" : "SDVOC")
 291 #define SDVO_PRIV(output)   ((struct intel_sdvo_priv *) (output)->dev_priv)
 292
 293 #ifdef SDVO_DEBUG
 294 static void intel_sdvo_debug_write(struct intel_output *intel_output, u8 cmd,
 295                                    void *args, int args_len)
 296 {
 297         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
 298         int i;
 299
 300         DRM_DEBUG_KMS(I915_SDVO, "%s: W: %02X ",
 301                                 SDVO_NAME(sdvo_priv), cmd);
 302         for (i = 0; i < args_len; i++)
 303                 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
 304         for (; i < 8; i++)
 305                 DRM_LOG_KMS("   ");
 306         for (i = 0; i < sizeof(sdvo_cmd_names) / sizeof(sdvo_cmd_names[0]); i++) {
 307                 if (cmd == sdvo_cmd_names[i].cmd) {
 308                         DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
 309                         break;
 310                 }
 311         }
 312         if (i == sizeof(sdvo_cmd_names)/ sizeof(sdvo_cmd_names[0]))
 313                 DRM_LOG_KMS("(%02X)", cmd);
 314         DRM_LOG_KMS("\n");
 315 }
 316 #else
 317 #define intel_sdvo_debug_write(o, c, a, l)
 318 #endif
 319
 320 static void intel_sdvo_write_cmd(struct intel_output *intel_output, u8 cmd,
 321                                  void *args, int args_len)
 322 {
 323         int i;
 324
 325         intel_sdvo_debug_write(intel_output, cmd, args, args_len);
 326
 327         for (i = 0; i < args_len; i++) {
 328                 intel_sdvo_write_byte(intel_output, SDVO_I2C_ARG_0 - i,
 329                                       ((u8*)args)[i]);
 330         }
 331
 332         intel_sdvo_write_byte(intel_output, SDVO_I2C_OPCODE, cmd);
 333 }
 334
 335 #ifdef SDVO_DEBUG
 336 static const char *cmd_status_names[] = {
 337         "Power on",
 338         "Success",
 339         "Not supported",
 340         "Invalid arg",
 341         "Pending",
 342         "Target not specified",
 343         "Scaling not supported"
 344 };
 345
 346 static void intel_sdvo_debug_response(struct intel_output *intel_output,
 347                                       void *response, int response_len,
 348                                       u8 status)
 349 {
 350         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
 351         int i;
 352
 353         DRM_DEBUG_KMS(I915_SDVO, "%s: R: ", SDVO_NAME(sdvo_priv));
 354         for (i = 0; i < response_len; i++)
 355                 DRM_LOG_KMS("%02X ", ((u8 *)response)[i]);
 356         for (; i < 8; i++)
 357                 DRM_LOG_KMS("   ");
 358         if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
 359                 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
 360         else
 361                 DRM_LOG_KMS("(??? %d)", status);
 362         DRM_LOG_KMS("\n");
 363 }
 364 #else
 365 #define intel_sdvo_debug_response(o, r, l, s)
 366 #endif
 367
 368 static u8 intel_sdvo_read_response(struct intel_output *intel_output,
 369                                    void *response, int response_len)
 370 {
 371         int i;
 372         u8 status;
 373         u8 retry = 50;
 374
 375         while (retry--) {
 376                 /* Read the command response */
 377                 for (i = 0; i < response_len; i++) {
 378                         intel_sdvo_read_byte(intel_output,
 379                                              SDVO_I2C_RETURN_0 + i,
 380                                              &((u8 *)response)[i]);
 381                 }
 382
 383                 /* read the return status */
 384                 intel_sdvo_read_byte(intel_output, SDVO_I2C_CMD_STATUS,
 385                                      &status);
 386
 387                 intel_sdvo_debug_response(intel_output, response, response_len,
 388                                           status);
 389                 if (status != SDVO_CMD_STATUS_PENDING)
 390                         return status;
 391
 392                 mdelay(50);
 393         }
 394
 395         return status;
 396 }
 397
 398 static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
 399 {
 400         if (mode->clock >= 100000)
 401                 return 1;
 402         else if (mode->clock >= 50000)
 403                 return 2;
 404         else
 405                 return 4;
 406 }
 407
 408 /**
 409  * Don't check status code from this as it switches the bus back to the
 410  * SDVO chips which defeats the purpose of doing a bus switch in the first
 411  * place.
 412  */
 413 static void intel_sdvo_set_control_bus_switch(struct intel_output *intel_output,
 414                                               u8 target)
 415 {
 416         intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_CONTROL_BUS_SWITCH, &target, 1);
 417 }
 418
 419 static bool intel_sdvo_set_target_input(struct intel_output *intel_output, bool target_0, bool target_1)
 420 {
 421         struct intel_sdvo_set_target_input_args targets = {0};
 422         u8 status;
 423
 424         if (target_0 && target_1)
 425                 return SDVO_CMD_STATUS_NOTSUPP;
 426
 427         if (target_1)
 428                 targets.target_1 = 1;
 429
 430         intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_TARGET_INPUT, &targets,
 431                              sizeof(targets));
 432
 433         status = intel_sdvo_read_response(intel_output, NULL, 0);
 434
 435         return (status == SDVO_CMD_STATUS_SUCCESS);
 436 }
 437
 438 /**
 439  * Return whether each input is trained.
 440  *
 441  * This function is making an assumption about the layout of the response,
 442  * which should be checked against the docs.
 443  */
 444 static bool intel_sdvo_get_trained_inputs(struct intel_output *intel_output, bool *input_1, bool *input_2)
 445 {
 446         struct intel_sdvo_get_trained_inputs_response response;
 447         u8 status;
 448
 449         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_TRAINED_INPUTS, NULL, 0);
 450         status = intel_sdvo_read_response(intel_output, &response, sizeof(response));
 451         if (status != SDVO_CMD_STATUS_SUCCESS)
 452                 return false;
 453
 454         *input_1 = response.input0_trained;
 455         *input_2 = response.input1_trained;
 456         return true;
 457 }
 458
 459 static bool intel_sdvo_get_active_outputs(struct intel_output *intel_output,
 460                                           u16 *outputs)
 461 {
 462         u8 status;
 463
 464         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_OUTPUTS, NULL, 0);
 465         status = intel_sdvo_read_response(intel_output, outputs, sizeof(*outputs));
 466
 467         return (status == SDVO_CMD_STATUS_SUCCESS);
 468 }
 469
 470 static bool intel_sdvo_set_active_outputs(struct intel_output *intel_output,
 471                                           u16 outputs)
 472 {
 473         u8 status;
 474
 475         intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_OUTPUTS, &outputs,
 476                              sizeof(outputs));
 477         status = intel_sdvo_read_response(intel_output, NULL, 0);
 478         return (status == SDVO_CMD_STATUS_SUCCESS);
 479 }
 480
 481 static bool intel_sdvo_set_encoder_power_state(struct intel_output *intel_output,
 482                                                int mode)
 483 {
 484         u8 status, state = SDVO_ENCODER_STATE_ON;
 485
 486         switch (mode) {
 487         case DRM_MODE_DPMS_ON:
 488                 state = SDVO_ENCODER_STATE_ON;
 489                 break;
 490         case DRM_MODE_DPMS_STANDBY:
 491                 state = SDVO_ENCODER_STATE_STANDBY;
 492                 break;
 493         case DRM_MODE_DPMS_SUSPEND:
 494                 state = SDVO_ENCODER_STATE_SUSPEND;
 495                 break;
 496         case DRM_MODE_DPMS_OFF:
 497                 state = SDVO_ENCODER_STATE_OFF;
 498                 break;
 499         }
 500
 501         intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ENCODER_POWER_STATE, &state,
 502                              sizeof(state));
 503         status = intel_sdvo_read_response(intel_output, NULL, 0);
 504
 505         return (status == SDVO_CMD_STATUS_SUCCESS);
 506 }
 507
 508 static bool intel_sdvo_get_input_pixel_clock_range(struct intel_output *intel_output,
 509                                                    int *clock_min,
 510                                                    int *clock_max)
 511 {
 512         struct intel_sdvo_pixel_clock_range clocks;
 513         u8 status;
 514
 515         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
 516                              NULL, 0);
 517
 518         status = intel_sdvo_read_response(intel_output, &clocks, sizeof(clocks));
 519
 520         if (status != SDVO_CMD_STATUS_SUCCESS)
 521                 return false;
 522
 523         /* Convert the values from units of 10 kHz to kHz. */
 524         *clock_min = clocks.min * 10;
 525         *clock_max = clocks.max * 10;
 526
 527         return true;
 528 }
 529
 530 static bool intel_sdvo_set_target_output(struct intel_output *intel_output,
 531                                          u16 outputs)
 532 {
 533         u8 status;
 534
 535         intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_TARGET_OUTPUT, &outputs,
 536                              sizeof(outputs));
 537
 538         status = intel_sdvo_read_response(intel_output, NULL, 0);
 539         return (status == SDVO_CMD_STATUS_SUCCESS);
 540 }
 541
 542 static bool intel_sdvo_get_timing(struct intel_output *intel_output, u8 cmd,
 543                                   struct intel_sdvo_dtd *dtd)
 544 {
 545         u8 status;
 546
 547         intel_sdvo_write_cmd(intel_output, cmd, NULL, 0);
 548         status = intel_sdvo_read_response(intel_output, &dtd->part1,
 549                                           sizeof(dtd->part1));
 550         if (status != SDVO_CMD_STATUS_SUCCESS)
 551                 return false;
 552
 553         intel_sdvo_write_cmd(intel_output, cmd + 1, NULL, 0);
 554         status = intel_sdvo_read_response(intel_output, &dtd->part2,
 555                                           sizeof(dtd->part2));
 556         if (status != SDVO_CMD_STATUS_SUCCESS)
 557                 return false;
 558
 559         return true;
 560 }
 561
 562 static bool intel_sdvo_get_input_timing(struct intel_output *intel_output,
 563                                          struct intel_sdvo_dtd *dtd)
 564 {
 565         return intel_sdvo_get_timing(intel_output,
 566                                      SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
 567 }
 568
 569 static bool intel_sdvo_get_output_timing(struct intel_output *intel_output,
 570                                          struct intel_sdvo_dtd *dtd)
 571 {
 572         return intel_sdvo_get_timing(intel_output,
 573                                      SDVO_CMD_GET_OUTPUT_TIMINGS_PART1, dtd);
 574 }
 575
 576 static bool intel_sdvo_set_timing(struct intel_output *intel_output, u8 cmd,
 577                                   struct intel_sdvo_dtd *dtd)
 578 {
 579         u8 status;
 580
 581         intel_sdvo_write_cmd(intel_output, cmd, &dtd->part1, sizeof(dtd->part1));
 582         status = intel_sdvo_read_response(intel_output, NULL, 0);
 583         if (status != SDVO_CMD_STATUS_SUCCESS)
 584                 return false;
 585
 586         intel_sdvo_write_cmd(intel_output, cmd + 1, &dtd->part2, sizeof(dtd->part2));
 587         status = intel_sdvo_read_response(intel_output, NULL, 0);
 588         if (status != SDVO_CMD_STATUS_SUCCESS)
 589                 return false;
 590
 591         return true;
 592 }
 593
 594 static bool intel_sdvo_set_input_timing(struct intel_output *intel_output,
 595                                          struct intel_sdvo_dtd *dtd)
 596 {
 597         return intel_sdvo_set_timing(intel_output,
 598                                      SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
 599 }
 600
 601 static bool intel_sdvo_set_output_timing(struct intel_output *intel_output,
 602                                          struct intel_sdvo_dtd *dtd)
 603 {
 604         return intel_sdvo_set_timing(intel_output,
 605                                      SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
 606 }
 607
 608 static bool
 609 intel_sdvo_create_preferred_input_timing(struct intel_output *output,
 610                                          uint16_t clock,
 611                                          uint16_t width,
 612                                          uint16_t height)
 613 {
 614         struct intel_sdvo_preferred_input_timing_args args;
 615         struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
 616         uint8_t status;
 617
 618         memset(&args, 0, sizeof(args));
 619         args.clock = clock;
 620         args.width = width;
 621         args.height = height;
 622         args.interlace = 0;
 623
 624         if (sdvo_priv->is_lvds &&
 625            (sdvo_priv->sdvo_lvds_fixed_mode->hdisplay != width ||
 626             sdvo_priv->sdvo_lvds_fixed_mode->vdisplay != height))
 627                 args.scaled = 1;
 628
 629         intel_sdvo_write_cmd(output, SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
 630                              &args, sizeof(args));
 631         status = intel_sdvo_read_response(output, NULL, 0);
 632         if (status != SDVO_CMD_STATUS_SUCCESS)
 633                 return false;
 634
 635         return true;
 636 }
 637
 638 static bool intel_sdvo_get_preferred_input_timing(struct intel_output *output,
 639                                                   struct intel_sdvo_dtd *dtd)
 640 {
 641         bool status;
 642
 643         intel_sdvo_write_cmd(output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
 644                              NULL, 0);
 645
 646         status = intel_sdvo_read_response(output, &dtd->part1,
 647                                           sizeof(dtd->part1));
 648         if (status != SDVO_CMD_STATUS_SUCCESS)
 649                 return false;
 650
 651         intel_sdvo_write_cmd(output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
 652                              NULL, 0);
 653
 654         status = intel_sdvo_read_response(output, &dtd->part2,
 655                                           sizeof(dtd->part2));
 656         if (status != SDVO_CMD_STATUS_SUCCESS)
 657                 return false;
 658
 659         return false;
 660 }
 661
 662 static int intel_sdvo_get_clock_rate_mult(struct intel_output *intel_output)
 663 {
 664         u8 response, status;
 665
 666         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_CLOCK_RATE_MULT, NULL, 0);
 667         status = intel_sdvo_read_response(intel_output, &response, 1);
 668
 669         if (status != SDVO_CMD_STATUS_SUCCESS) {
 670                 DRM_DEBUG("Couldn't get SDVO clock rate multiplier\n");
 671                 return SDVO_CLOCK_RATE_MULT_1X;
 672         } else {
 673                 DRM_DEBUG("Current clock rate multiplier: %d\n", response);
 674         }
 675
 676         return response;
 677 }
 678
 679 static bool intel_sdvo_set_clock_rate_mult(struct intel_output *intel_output, u8 val)
 680 {
 681         u8 status;
 682
 683         intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
 684         status = intel_sdvo_read_response(intel_output, NULL, 0);
 685         if (status != SDVO_CMD_STATUS_SUCCESS)
 686                 return false;
 687
 688         return true;
 689 }
 690
 691 static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
 692                                          struct drm_display_mode *mode)
 693 {
 694         uint16_t width, height;
 695         uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
 696         uint16_t h_sync_offset, v_sync_offset;
 697
 698         width = mode->crtc_hdisplay;
 699         height = mode->crtc_vdisplay;
 700
 701         /* do some mode translations */
 702         h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
 703         h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
 704
 705         v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
 706         v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
 707
 708         h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
 709         v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
 710
 711         dtd->part1.clock = mode->clock / 10;
 712         dtd->part1.h_active = width & 0xff;
 713         dtd->part1.h_blank = h_blank_len & 0xff;
 714         dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
 715                 ((h_blank_len >> 8) & 0xf);
 716         dtd->part1.v_active = height & 0xff;
 717         dtd->part1.v_blank = v_blank_len & 0xff;
 718         dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
 719                 ((v_blank_len >> 8) & 0xf);
 720
 721         dtd->part2.h_sync_off = h_sync_offset & 0xff;
 722         dtd->part2.h_sync_width = h_sync_len & 0xff;
 723         dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
 724                 (v_sync_len & 0xf);
 725         dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
 726                 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
 727                 ((v_sync_len & 0x30) >> 4);
 728
 729         dtd->part2.dtd_flags = 0x18;
 730         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
 731                 dtd->part2.dtd_flags |= 0x2;
 732         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
 733                 dtd->part2.dtd_flags |= 0x4;
 734
 735         dtd->part2.sdvo_flags = 0;
 736         dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
 737         dtd->part2.reserved = 0;
 738 }
 739
 740 static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
 741                                          struct intel_sdvo_dtd *dtd)
 742 {
 743         mode->hdisplay = dtd->part1.h_active;
 744         mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
 745         mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
 746         mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
 747         mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
 748         mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
 749         mode->htotal = mode->hdisplay + dtd->part1.h_blank;
 750         mode->htotal += (dtd->part1.h_high & 0xf) << 8;
 751
 752         mode->vdisplay = dtd->part1.v_active;
 753         mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
 754         mode->vsync_start = mode->vdisplay;
 755         mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
 756         mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
 757         mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
 758         mode->vsync_end = mode->vsync_start +
 759                 (dtd->part2.v_sync_off_width & 0xf);
 760         mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
 761         mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
 762         mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
 763
 764         mode->clock = dtd->part1.clock * 10;
 765
 766         mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
 767         if (dtd->part2.dtd_flags & 0x2)
 768                 mode->flags |= DRM_MODE_FLAG_PHSYNC;
 769         if (dtd->part2.dtd_flags & 0x4)
 770                 mode->flags |= DRM_MODE_FLAG_PVSYNC;
 771 }
 772
 773 static bool intel_sdvo_get_supp_encode(struct intel_output *output,
 774                                        struct intel_sdvo_encode *encode)
 775 {
 776         uint8_t status;
 777
 778         intel_sdvo_write_cmd(output, SDVO_CMD_GET_SUPP_ENCODE, NULL, 0);
 779         status = intel_sdvo_read_response(output, encode, sizeof(*encode));
 780         if (status != SDVO_CMD_STATUS_SUCCESS) { /* non-support means DVI */
 781                 memset(encode, 0, sizeof(*encode));
 782                 return false;
 783         }
 784
 785         return true;
 786 }
 787
 788 static bool intel_sdvo_set_encode(struct intel_output *output, uint8_t mode)
 789 {
 790         uint8_t status;
 791
 792         intel_sdvo_write_cmd(output, SDVO_CMD_SET_ENCODE, &mode, 1);
 793         status = intel_sdvo_read_response(output, NULL, 0);
 794
 795         return (status == SDVO_CMD_STATUS_SUCCESS);
 796 }
 797
 798 static bool intel_sdvo_set_colorimetry(struct intel_output *output,
 799                                        uint8_t mode)
 800 {
 801         uint8_t status;
 802
 803         intel_sdvo_write_cmd(output, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
 804         status = intel_sdvo_read_response(output, NULL, 0);
 805
 806         return (status == SDVO_CMD_STATUS_SUCCESS);
 807 }
 808
 809 #if 0
 810 static void intel_sdvo_dump_hdmi_buf(struct intel_output *output)
 811 {
 812         int i, j;
 813         uint8_t set_buf_index[2];
 814         uint8_t av_split;
 815         uint8_t buf_size;
 816         uint8_t buf[48];
 817         uint8_t *pos;
 818
 819         intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_AV_SPLIT, NULL, 0);
 820         intel_sdvo_read_response(output, &av_split, 1);
 821
 822         for (i = 0; i <= av_split; i++) {
 823                 set_buf_index[0] = i; set_buf_index[1] = 0;
 824                 intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_INDEX,
 825                                      set_buf_index, 2);
 826                 intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
 827                 intel_sdvo_read_response(output, &buf_size, 1);
 828
 829                 pos = buf;
 830                 for (j = 0; j <= buf_size; j += 8) {
 831                         intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_DATA,
 832                                              NULL, 0);
 833                         intel_sdvo_read_response(output, pos, 8);
 834                         pos += 8;
 835                 }
 836         }
 837 }
 838 #endif
 839
 840 static void intel_sdvo_set_hdmi_buf(struct intel_output *output, int index,
 841                                 uint8_t *data, int8_t size, uint8_t tx_rate)
 842 {
 843     uint8_t set_buf_index[2];
 844
 845     set_buf_index[0] = index;
 846     set_buf_index[1] = 0;
 847
 848     intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_INDEX, set_buf_index, 2);
 849
 850     for (; size > 0; size -= 8) {
 851         intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_DATA, data, 8);
 852         data += 8;
 853     }
 854
 855     intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1);
 856 }
 857
 858 static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size)
 859 {
 860         uint8_t csum = 0;
 861         int i;
 862
 863         for (i = 0; i < size; i++)
 864                 csum += data[i];
 865
 866         return 0x100 - csum;
 867 }
 868
 869 #define DIP_TYPE_AVI    0x82
 870 #define DIP_VERSION_AVI 0x2
 871 #define DIP_LEN_AVI     13
 872
 873 struct dip_infoframe {
 874         uint8_t type;
 875         uint8_t version;
 876         uint8_t len;
 877         uint8_t checksum;
 878         union {
 879                 struct {
 880                         /* Packet Byte #1 */
 881                         uint8_t S:2;
 882                         uint8_t B:2;
 883                         uint8_t A:1;
 884                         uint8_t Y:2;
 885                         uint8_t rsvd1:1;
 886                         /* Packet Byte #2 */
 887                         uint8_t R:4;
 888                         uint8_t M:2;
 889                         uint8_t C:2;
 890                         /* Packet Byte #3 */
 891                         uint8_t SC:2;
 892                         uint8_t Q:2;
 893                         uint8_t EC:3;
 894                         uint8_t ITC:1;
 895                         /* Packet Byte #4 */
 896                         uint8_t VIC:7;
 897                         uint8_t rsvd2:1;
 898                         /* Packet Byte #5 */
 899                         uint8_t PR:4;
 900                         uint8_t rsvd3:4;
 901                         /* Packet Byte #6~13 */
 902                         uint16_t top_bar_end;
 903                         uint16_t bottom_bar_start;
 904                         uint16_t left_bar_end;
 905                         uint16_t right_bar_start;
 906                 } avi;
 907                 struct {
 908                         /* Packet Byte #1 */
 909                         uint8_t channel_count:3;
 910                         uint8_t rsvd1:1;
 911                         uint8_t coding_type:4;
 912                         /* Packet Byte #2 */
 913                         uint8_t sample_size:2; /* SS0, SS1 */
 914                         uint8_t sample_frequency:3;
 915                         uint8_t rsvd2:3;
 916                         /* Packet Byte #3 */
 917                         uint8_t coding_type_private:5;
 918                         uint8_t rsvd3:3;
 919                         /* Packet Byte #4 */
 920                         uint8_t channel_allocation;
 921                         /* Packet Byte #5 */
 922                         uint8_t rsvd4:3;
 923                         uint8_t level_shift:4;
 924                         uint8_t downmix_inhibit:1;
 925                 } audio;
 926                 uint8_t payload[28];
 927         } __attribute__ ((packed)) u;
 928 } __attribute__((packed));
 929
 930 static void intel_sdvo_set_avi_infoframe(struct intel_output *output,
 931                                          struct drm_display_mode * mode)
 932 {
 933         struct dip_infoframe avi_if = {
 934                 .type = DIP_TYPE_AVI,
 935                 .version = DIP_VERSION_AVI,
 936                 .len = DIP_LEN_AVI,
 937         };
 938
 939         avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if,
 940                                                     4 + avi_if.len);
 941         intel_sdvo_set_hdmi_buf(output, 1, (uint8_t *)&avi_if, 4 + avi_if.len,
 942                                 SDVO_HBUF_TX_VSYNC);
 943 }
 944
 945 static void intel_sdvo_set_tv_format(struct intel_output *output)
 946 {
 947         struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
 948         struct intel_sdvo_tv_format *format, unset;
 949         u8 status;
 950
 951         format = &sdvo_priv->tv_format;
 952         memset(&unset, 0, sizeof(unset));
 953         if (memcmp(format, &unset, sizeof(*format))) {
 954                 DRM_DEBUG("%s: Choosing default TV format of NTSC-M\n",
 955                                 SDVO_NAME(sdvo_priv));
 956                 format->ntsc_m = 1;
 957                 intel_sdvo_write_cmd(output, SDVO_CMD_SET_TV_FORMAT, format,
 958                                 sizeof(*format));
 959                 status = intel_sdvo_read_response(output, NULL, 0);
 960                 if (status != SDVO_CMD_STATUS_SUCCESS)
 961                         DRM_DEBUG("%s: Failed to set TV format\n",
 962                                         SDVO_NAME(sdvo_priv));
 963         }
 964 }
 965
 966 static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
 967                                   struct drm_display_mode *mode,
 968                                   struct drm_display_mode *adjusted_mode)
 969 {
 970         struct intel_output *output = enc_to_intel_output(encoder);
 971         struct intel_sdvo_priv *dev_priv = output->dev_priv;
 972
 973         if (dev_priv->is_tv) {
 974                 struct intel_sdvo_dtd output_dtd;
 975                 bool success;
 976
 977                 /* We need to construct preferred input timings based on our
 978                  * output timings.  To do that, we have to set the output
 979                  * timings, even though this isn't really the right place in
 980                  * the sequence to do it. Oh well.
 981                  */
 982
 983
 984                 /* Set output timings */
 985                 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
 986                 intel_sdvo_set_target_output(output,
 987                                              dev_priv->controlled_output);
 988                 intel_sdvo_set_output_timing(output, &output_dtd);
 989
 990                 /* Set the input timing to the screen. Assume always input 0. */
 991                 intel_sdvo_set_target_input(output, true, false);
 992
 993
 994                 success = intel_sdvo_create_preferred_input_timing(output,
 995                                                                    mode->clock / 10,
 996                                                                    mode->hdisplay,
 997                                                                    mode->vdisplay);
 998                 if (success) {
 999                         struct intel_sdvo_dtd input_dtd;
1000
1001                         intel_sdvo_get_preferred_input_timing(output,
1002                                                              &input_dtd);
1003                         intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
1004                         dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags;
1005
1006                         drm_mode_set_crtcinfo(adjusted_mode, 0);
1007
1008                         mode->clock = adjusted_mode->clock;
1009
1010                         adjusted_mode->clock *=
1011                                 intel_sdvo_get_pixel_multiplier(mode);
1012                 } else {
1013                         return false;
1014                 }
1015         } else if (dev_priv->is_lvds) {
1016                 struct intel_sdvo_dtd output_dtd;
1017                 bool success;
1018
1019                 drm_mode_set_crtcinfo(dev_priv->sdvo_lvds_fixed_mode, 0);
1020                 /* Set output timings */
1021                 intel_sdvo_get_dtd_from_mode(&output_dtd,
1022                                 dev_priv->sdvo_lvds_fixed_mode);
1023
1024                 intel_sdvo_set_target_output(output,
1025                                              dev_priv->controlled_output);
1026                 intel_sdvo_set_output_timing(output, &output_dtd);
1027
1028                 /* Set the input timing to the screen. Assume always input 0. */
1029                 intel_sdvo_set_target_input(output, true, false);
1030
1031
1032                 success = intel_sdvo_create_preferred_input_timing(
1033                                 output,
1034                                 mode->clock / 10,
1035                                 mode->hdisplay,
1036                                 mode->vdisplay);
1037
1038                 if (success) {
1039                         struct intel_sdvo_dtd input_dtd;
1040
1041                         intel_sdvo_get_preferred_input_timing(output,
1042                                                              &input_dtd);
1043                         intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
1044                         dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags;
1045
1046                         drm_mode_set_crtcinfo(adjusted_mode, 0);
1047
1048                         mode->clock = adjusted_mode->clock;
1049
1050                         adjusted_mode->clock *=
1051                                 intel_sdvo_get_pixel_multiplier(mode);
1052                 } else {
1053                         return false;
1054                 }
1055
1056         } else {
1057                 /* Make the CRTC code factor in the SDVO pixel multiplier.  The
1058                  * SDVO device will be told of the multiplier during mode_set.
1059                  */
1060                 adjusted_mode->clock *= intel_sdvo_get_pixel_multiplier(mode);
1061         }
1062         return true;
1063 }
1064
1065 static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1066                                 struct drm_display_mode *mode,
1067                                 struct drm_display_mode *adjusted_mode)
1068 {
1069         struct drm_device *dev = encoder->dev;
1070         struct drm_i915_private *dev_priv = dev->dev_private;
1071         struct drm_crtc *crtc = encoder->crtc;
1072         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1073         struct intel_output *output = enc_to_intel_output(encoder);
1074         struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1075         u32 sdvox = 0;
1076         int sdvo_pixel_multiply;
1077         struct intel_sdvo_in_out_map in_out;
1078         struct intel_sdvo_dtd input_dtd;
1079         u8 status;
1080
1081         if (!mode)
1082                 return;
1083
1084         /* First, set the input mapping for the first input to our controlled
1085          * output. This is only correct if we're a single-input device, in
1086          * which case the first input is the output from the appropriate SDVO
1087          * channel on the motherboard.  In a two-input device, the first input
1088          * will be SDVOB and the second SDVOC.
1089          */
1090         in_out.in0 = sdvo_priv->controlled_output;
1091         in_out.in1 = 0;
1092
1093         intel_sdvo_write_cmd(output, SDVO_CMD_SET_IN_OUT_MAP,
1094                              &in_out, sizeof(in_out));
1095         status = intel_sdvo_read_response(output, NULL, 0);
1096
1097         if (sdvo_priv->is_hdmi) {
1098                 intel_sdvo_set_avi_infoframe(output, mode);
1099                 sdvox |= SDVO_AUDIO_ENABLE;
1100         }
1101
1102         /* We have tried to get input timing in mode_fixup, and filled into
1103            adjusted_mode */
1104         if (sdvo_priv->is_tv || sdvo_priv->is_lvds) {
1105                 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
1106                 input_dtd.part2.sdvo_flags = sdvo_priv->sdvo_flags;
1107         } else
1108                 intel_sdvo_get_dtd_from_mode(&input_dtd, mode);
1109
1110         /* If it's a TV, we already set the output timing in mode_fixup.
1111          * Otherwise, the output timing is equal to the input timing.
1112          */
1113         if (!sdvo_priv->is_tv && !sdvo_priv->is_lvds) {
1114                 /* Set the output timing to the screen */
1115                 intel_sdvo_set_target_output(output,
1116                                              sdvo_priv->controlled_output);
1117                 intel_sdvo_set_output_timing(output, &input_dtd);
1118         }
1119
1120         /* Set the input timing to the screen. Assume always input 0. */
1121         intel_sdvo_set_target_input(output, true, false);
1122
1123         if (sdvo_priv->is_tv)
1124                 intel_sdvo_set_tv_format(output);
1125
1126         /* We would like to use intel_sdvo_create_preferred_input_timing() to
1127          * provide the device with a timing it can support, if it supports that
1128          * feature.  However, presumably we would need to adjust the CRTC to
1129          * output the preferred timing, and we don't support that currently.
1130          */
1131 #if 0
1132         success = intel_sdvo_create_preferred_input_timing(output, clock,
1133                                                            width, height);
1134         if (success) {
1135                 struct intel_sdvo_dtd *input_dtd;
1136
1137                 intel_sdvo_get_preferred_input_timing(output, &input_dtd);
1138                 intel_sdvo_set_input_timing(output, &input_dtd);
1139         }
1140 #else
1141         intel_sdvo_set_input_timing(output, &input_dtd);
1142 #endif
1143
1144         switch (intel_sdvo_get_pixel_multiplier(mode)) {
1145         case 1:
1146                 intel_sdvo_set_clock_rate_mult(output,
1147                                                SDVO_CLOCK_RATE_MULT_1X);
1148                 break;
1149         case 2:
1150                 intel_sdvo_set_clock_rate_mult(output,
1151                                                SDVO_CLOCK_RATE_MULT_2X);
1152                 break;
1153         case 4:
1154                 intel_sdvo_set_clock_rate_mult(output,
1155                                                SDVO_CLOCK_RATE_MULT_4X);
1156                 break;
1157         }
1158
1159         /* Set the SDVO control regs. */
1160         if (IS_I965G(dev)) {
1161                 sdvox |= SDVO_BORDER_ENABLE |
1162                         SDVO_VSYNC_ACTIVE_HIGH |
1163                         SDVO_HSYNC_ACTIVE_HIGH;
1164         } else {
1165                 sdvox |= I915_READ(sdvo_priv->output_device);
1166                 switch (sdvo_priv->output_device) {
1167                 case SDVOB:
1168                         sdvox &= SDVOB_PRESERVE_MASK;
1169                         break;
1170                 case SDVOC:
1171                         sdvox &= SDVOC_PRESERVE_MASK;
1172                         break;
1173                 }
1174                 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1175         }
1176         if (intel_crtc->pipe == 1)
1177                 sdvox |= SDVO_PIPE_B_SELECT;
1178
1179         sdvo_pixel_multiply = intel_sdvo_get_pixel_multiplier(mode);
1180         if (IS_I965G(dev)) {
1181                 /* done in crtc_mode_set as the dpll_md reg must be written early */
1182         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1183                 /* done in crtc_mode_set as it lives inside the dpll register */
1184         } else {
1185                 sdvox |= (sdvo_pixel_multiply - 1) << SDVO_PORT_MULTIPLY_SHIFT;
1186         }
1187
1188         if (sdvo_priv->sdvo_flags & SDVO_NEED_TO_STALL)
1189                 sdvox |= SDVO_STALL_SELECT;
1190         intel_sdvo_write_sdvox(output, sdvox);
1191 }
1192
1193 static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1194 {
1195         struct drm_device *dev = encoder->dev;
1196         struct drm_i915_private *dev_priv = dev->dev_private;
1197         struct intel_output *intel_output = enc_to_intel_output(encoder);
1198         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1199         u32 temp;
1200
1201         if (mode != DRM_MODE_DPMS_ON) {
1202                 intel_sdvo_set_active_outputs(intel_output, 0);
1203                 if (0)
1204                         intel_sdvo_set_encoder_power_state(intel_output, mode);
1205
1206                 if (mode == DRM_MODE_DPMS_OFF) {
1207                         temp = I915_READ(sdvo_priv->output_device);
1208                         if ((temp & SDVO_ENABLE) != 0) {
1209                                 intel_sdvo_write_sdvox(intel_output, temp & ~SDVO_ENABLE);
1210                         }
1211                 }
1212         } else {
1213                 bool input1, input2;
1214                 int i;
1215                 u8 status;
1216
1217                 temp = I915_READ(sdvo_priv->output_device);
1218                 if ((temp & SDVO_ENABLE) == 0)
1219                         intel_sdvo_write_sdvox(intel_output, temp | SDVO_ENABLE);
1220                 for (i = 0; i < 2; i++)
1221                   intel_wait_for_vblank(dev);
1222
1223                 status = intel_sdvo_get_trained_inputs(intel_output, &input1,
1224                                                        &input2);
1225
1226
1227                 /* Warn if the device reported failure to sync.
1228                  * A lot of SDVO devices fail to notify of sync, but it's
1229                  * a given it the status is a success, we succeeded.
1230                  */
1231                 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
1232                         DRM_DEBUG("First %s output reported failure to sync\n",
1233                                    SDVO_NAME(sdvo_priv));
1234                 }
1235
1236                 if (0)
1237                         intel_sdvo_set_encoder_power_state(intel_output, mode);
1238                 intel_sdvo_set_active_outputs(intel_output, sdvo_priv->controlled_output);
1239         }
1240         return;
1241 }
1242
1243 static void intel_sdvo_save(struct drm_connector *connector)
1244 {
1245         struct drm_device *dev = connector->dev;
1246         struct drm_i915_private *dev_priv = dev->dev_private;
1247         struct intel_output *intel_output = to_intel_output(connector);
1248         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1249         int o;
1250
1251         sdvo_priv->save_sdvo_mult = intel_sdvo_get_clock_rate_mult(intel_output);
1252         intel_sdvo_get_active_outputs(intel_output, &sdvo_priv->save_active_outputs);
1253
1254         if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
1255                 intel_sdvo_set_target_input(intel_output, true, false);
1256                 intel_sdvo_get_input_timing(intel_output,
1257                                             &sdvo_priv->save_input_dtd_1);
1258         }
1259
1260         if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
1261                 intel_sdvo_set_target_input(intel_output, false, true);
1262                 intel_sdvo_get_input_timing(intel_output,
1263                                             &sdvo_priv->save_input_dtd_2);
1264         }
1265
1266         for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++)
1267         {
1268                 u16  this_output = (1 << o);
1269                 if (sdvo_priv->caps.output_flags & this_output)
1270                 {
1271                         intel_sdvo_set_target_output(intel_output, this_output);
1272                         intel_sdvo_get_output_timing(intel_output,
1273                                                      &sdvo_priv->save_output_dtd[o]);
1274                 }
1275         }
1276         if (sdvo_priv->is_tv) {
1277                 /* XXX: Save TV format/enhancements. */
1278         }
1279
1280         sdvo_priv->save_SDVOX = I915_READ(sdvo_priv->output_device);
1281 }
1282
1283 static void intel_sdvo_restore(struct drm_connector *connector)
1284 {
1285         struct drm_device *dev = connector->dev;
1286         struct intel_output *intel_output = to_intel_output(connector);
1287         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1288         int o;
1289         int i;
1290         bool input1, input2;
1291         u8 status;
1292
1293         intel_sdvo_set_active_outputs(intel_output, 0);
1294
1295         for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++)
1296         {
1297                 u16  this_output = (1 << o);
1298                 if (sdvo_priv->caps.output_flags & this_output) {
1299                         intel_sdvo_set_target_output(intel_output, this_output);
1300                         intel_sdvo_set_output_timing(intel_output, &sdvo_priv->save_output_dtd[o]);
1301                 }
1302         }
1303
1304         if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
1305                 intel_sdvo_set_target_input(intel_output, true, false);
1306                 intel_sdvo_set_input_timing(intel_output, &sdvo_priv->save_input_dtd_1);
1307         }
1308
1309         if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
1310                 intel_sdvo_set_target_input(intel_output, false, true);
1311                 intel_sdvo_set_input_timing(intel_output, &sdvo_priv->save_input_dtd_2);
1312         }
1313
1314         intel_sdvo_set_clock_rate_mult(intel_output, sdvo_priv->save_sdvo_mult);
1315
1316         if (sdvo_priv->is_tv) {
1317                 /* XXX: Restore TV format/enhancements. */
1318         }
1319
1320         intel_sdvo_write_sdvox(intel_output, sdvo_priv->save_SDVOX);
1321
1322         if (sdvo_priv->save_SDVOX & SDVO_ENABLE)
1323         {
1324                 for (i = 0; i < 2; i++)
1325                         intel_wait_for_vblank(dev);
1326                 status = intel_sdvo_get_trained_inputs(intel_output, &input1, &input2);
1327                 if (status == SDVO_CMD_STATUS_SUCCESS && !input1)
1328                         DRM_DEBUG("First %s output reported failure to sync\n",
1329                                    SDVO_NAME(sdvo_priv));
1330         }
1331
1332         intel_sdvo_set_active_outputs(intel_output, sdvo_priv->save_active_outputs);
1333 }
1334
1335 static int intel_sdvo_mode_valid(struct drm_connector *connector,
1336                                  struct drm_display_mode *mode)
1337 {
1338         struct intel_output *intel_output = to_intel_output(connector);
1339         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1340
1341         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1342                 return MODE_NO_DBLESCAN;
1343
1344         if (sdvo_priv->pixel_clock_min > mode->clock)
1345                 return MODE_CLOCK_LOW;
1346
1347         if (sdvo_priv->pixel_clock_max < mode->clock)
1348                 return MODE_CLOCK_HIGH;
1349
1350         if (sdvo_priv->is_lvds == true) {
1351                 if (sdvo_priv->sdvo_lvds_fixed_mode == NULL)
1352                         return MODE_PANEL;
1353
1354                 if (mode->hdisplay > sdvo_priv->sdvo_lvds_fixed_mode->hdisplay)
1355                         return MODE_PANEL;
1356
1357                 if (mode->vdisplay > sdvo_priv->sdvo_lvds_fixed_mode->vdisplay)
1358                         return MODE_PANEL;
1359         }
1360
1361         return MODE_OK;
1362 }
1363
1364 static bool intel_sdvo_get_capabilities(struct intel_output *intel_output, struct intel_sdvo_caps *caps)
1365 {
1366         u8 status;
1367
1368         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_DEVICE_CAPS, NULL, 0);
1369         status = intel_sdvo_read_response(intel_output, caps, sizeof(*caps));
1370         if (status != SDVO_CMD_STATUS_SUCCESS)
1371                 return false;
1372
1373         return true;
1374 }
1375
1376 struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB)
1377 {
1378         struct drm_connector *connector = NULL;
1379         struct intel_output *iout = NULL;
1380         struct intel_sdvo_priv *sdvo;
1381
1382         /* find the sdvo connector */
1383         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1384                 iout = to_intel_output(connector);
1385
1386                 if (iout->type != INTEL_OUTPUT_SDVO)
1387                         continue;
1388
1389                 sdvo = iout->dev_priv;
1390
1391                 if (sdvo->output_device == SDVOB && sdvoB)
1392                         return connector;
1393
1394                 if (sdvo->output_device == SDVOC && !sdvoB)
1395                         return connector;
1396
1397         }
1398
1399         return NULL;
1400 }
1401
1402 int intel_sdvo_supports_hotplug(struct drm_connector *connector)
1403 {
1404         u8 response[2];
1405         u8 status;
1406         struct intel_output *intel_output;
1407         DRM_DEBUG("\n");
1408
1409         if (!connector)
1410                 return 0;
1411
1412         intel_output = to_intel_output(connector);
1413
1414         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1415         status = intel_sdvo_read_response(intel_output, &response, 2);
1416
1417         if (response[0] !=0)
1418                 return 1;
1419
1420         return 0;
1421 }
1422
1423 void intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
1424 {
1425         u8 response[2];
1426         u8 status;
1427         struct intel_output *intel_output = to_intel_output(connector);
1428
1429         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1430         intel_sdvo_read_response(intel_output, &response, 2);
1431
1432         if (on) {
1433                 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1434                 status = intel_sdvo_read_response(intel_output, &response, 2);
1435
1436                 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
1437         } else {
1438                 response[0] = 0;
1439                 response[1] = 0;
1440                 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
1441         }
1442
1443         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1444         intel_sdvo_read_response(intel_output, &response, 2);
1445 }
1446
1447 static bool
1448 intel_sdvo_multifunc_encoder(struct intel_output *intel_output)
1449 {
1450         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1451         int caps = 0;
1452
1453         if (sdvo_priv->caps.output_flags &
1454                 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1))
1455                 caps++;
1456         if (sdvo_priv->caps.output_flags &
1457                 (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1))
1458                 caps++;
1459         if (sdvo_priv->caps.output_flags &
1460                 (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_SVID0))
1461                 caps++;
1462         if (sdvo_priv->caps.output_flags &
1463                 (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_CVBS1))
1464                 caps++;
1465         if (sdvo_priv->caps.output_flags &
1466                 (SDVO_OUTPUT_YPRPB0 | SDVO_OUTPUT_YPRPB1))
1467                 caps++;
1468
1469         if (sdvo_priv->caps.output_flags &
1470                 (SDVO_OUTPUT_SCART0 | SDVO_OUTPUT_SCART1))
1471                 caps++;
1472
1473         if (sdvo_priv->caps.output_flags &
1474                 (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1))
1475                 caps++;
1476
1477         return (caps > 1);
1478 }
1479
1480 static void
1481 intel_sdvo_hdmi_sink_detect(struct drm_connector *connector)
1482 {
1483         struct intel_output *intel_output = to_intel_output(connector);
1484         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1485         struct edid *edid = NULL;
1486
1487         edid = drm_get_edid(&intel_output->base,
1488                             intel_output->ddc_bus);
1489         if (edid != NULL) {
1490                 sdvo_priv->is_hdmi = drm_detect_hdmi_monitor(edid);
1491                 kfree(edid);
1492                 intel_output->base.display_info.raw_edid = NULL;
1493         }
1494 }
1495
1496 static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector)
1497 {
1498         uint16_t response;
1499         u8 status;
1500         struct intel_output *intel_output = to_intel_output(connector);
1501         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1502
1503         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0);
1504         status = intel_sdvo_read_response(intel_output, &response, 2);
1505
1506         DRM_DEBUG("SDVO response %d %d\n", response & 0xff, response >> 8);
1507
1508         if (status != SDVO_CMD_STATUS_SUCCESS)
1509                 return connector_status_unknown;
1510
1511         if (response == 0)
1512                 return connector_status_disconnected;
1513
1514         if (intel_sdvo_multifunc_encoder(intel_output) &&
1515                 sdvo_priv->attached_output != response) {
1516                 if (sdvo_priv->controlled_output != response &&
1517                         intel_sdvo_output_setup(intel_output, response) != true)
1518                         return connector_status_unknown;
1519                 sdvo_priv->attached_output = response;
1520         }
1521         intel_sdvo_hdmi_sink_detect(connector);
1522         return connector_status_connected;
1523 }
1524
1525 static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
1526 {
1527         struct intel_output *intel_output = to_intel_output(connector);
1528
1529         /* set the bus switch and get the modes */
1530         intel_ddc_get_modes(intel_output);
1531
1532 #if 0
1533         struct drm_device *dev = encoder->dev;
1534         struct drm_i915_private *dev_priv = dev->dev_private;
1535         /* Mac mini hack.  On this device, I get DDC through the analog, which
1536          * load-detects as disconnected.  I fail to DDC through the SDVO DDC,
1537          * but it does load-detect as connected.  So, just steal the DDC bits
1538          * from analog when we fail at finding it the right way.
1539          */
1540         crt = xf86_config->output[0];
1541         intel_output = crt->driver_private;
1542         if (intel_output->type == I830_OUTPUT_ANALOG &&
1543             crt->funcs->detect(crt) == XF86OutputStatusDisconnected) {
1544                 I830I2CInit(pScrn, &intel_output->pDDCBus, GPIOA, "CRTDDC_A");
1545                 edid_mon = xf86OutputGetEDID(crt, intel_output->pDDCBus);
1546                 xf86DestroyI2CBusRec(intel_output->pDDCBus, true, true);
1547         }
1548         if (edid_mon) {
1549                 xf86OutputSetEDID(output, edid_mon);
1550                 modes = xf86OutputGetEDIDModes(output);
1551         }
1552 #endif
1553 }
1554
1555 /**
1556  * This function checks the current TV format, and chooses a default if
1557  * it hasn't been set.
1558  */
1559 static void
1560 intel_sdvo_check_tv_format(struct intel_output *output)
1561 {
1562         struct intel_sdvo_priv *dev_priv = output->dev_priv;
1563         struct intel_sdvo_tv_format format;
1564         uint8_t status;
1565
1566         intel_sdvo_write_cmd(output, SDVO_CMD_GET_TV_FORMAT, NULL, 0);
1567         status = intel_sdvo_read_response(output, &format, sizeof(format));
1568         if (status != SDVO_CMD_STATUS_SUCCESS)
1569                 return;
1570
1571         memcpy(&dev_priv->tv_format, &format, sizeof(format));
1572 }
1573
1574 /*
1575  * Set of SDVO TV modes.
1576  * Note!  This is in reply order (see loop in get_tv_modes).
1577  * XXX: all 60Hz refresh?
1578  */
1579 struct drm_display_mode sdvo_tv_modes[] = {
1580         { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1581                    416, 0, 200, 201, 232, 233, 0,
1582                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1583         { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1584                    416, 0, 240, 241, 272, 273, 0,
1585                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1586         { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1587                    496, 0, 300, 301, 332, 333, 0,
1588                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1589         { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1590                    736, 0, 350, 351, 382, 383, 0,
1591                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1592         { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1593                    736, 0, 400, 401, 432, 433, 0,
1594                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1595         { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1596                    736, 0, 480, 481, 512, 513, 0,
1597                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1598         { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1599                    800, 0, 480, 481, 512, 513, 0,
1600                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1601         { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1602                    800, 0, 576, 577, 608, 609, 0,
1603                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1604         { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1605                    816, 0, 350, 351, 382, 383, 0,
1606                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1607         { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1608                    816, 0, 400, 401, 432, 433, 0,
1609                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1610         { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1611                    816, 0, 480, 481, 512, 513, 0,
1612                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1613         { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1614                    816, 0, 540, 541, 572, 573, 0,
1615                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1616         { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1617                    816, 0, 576, 577, 608, 609, 0,
1618                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1619         { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1620                    864, 0, 576, 577, 608, 609, 0,
1621                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1622         { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1623                    896, 0, 600, 601, 632, 633, 0,
1624                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1625         { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1626                    928, 0, 624, 625, 656, 657, 0,
1627                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1628         { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1629                    1016, 0, 766, 767, 798, 799, 0,
1630                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1631         { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1632                    1120, 0, 768, 769, 800, 801, 0,
1633                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1634         { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1635                    1376, 0, 1024, 1025, 1056, 1057, 0,
1636                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1637 };
1638
1639 static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1640 {
1641         struct intel_output *output = to_intel_output(connector);
1642         struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1643         struct intel_sdvo_sdtv_resolution_request tv_res;
1644         uint32_t reply = 0;
1645         uint8_t status;
1646         int i = 0;
1647
1648         intel_sdvo_check_tv_format(output);
1649
1650         /* Read the list of supported input resolutions for the selected TV
1651          * format.
1652          */
1653         memset(&tv_res, 0, sizeof(tv_res));
1654         memcpy(&tv_res, &sdvo_priv->tv_format, sizeof(tv_res));
1655         intel_sdvo_write_cmd(output, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
1656                              &tv_res, sizeof(tv_res));
1657         status = intel_sdvo_read_response(output, &reply, 3);
1658         if (status != SDVO_CMD_STATUS_SUCCESS)
1659                 return;
1660
1661         for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
1662                 if (reply & (1 << i)) {
1663                         struct drm_display_mode *nmode;
1664                         nmode = drm_mode_duplicate(connector->dev,
1665                                         &sdvo_tv_modes[i]);
1666                         if (nmode)
1667                                 drm_mode_probed_add(connector, nmode);
1668                 }
1669 }
1670
1671 static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1672 {
1673         struct intel_output *intel_output = to_intel_output(connector);
1674         struct drm_i915_private *dev_priv = connector->dev->dev_private;
1675         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1676         struct drm_display_mode *newmode;
1677
1678         /*
1679          * Attempt to get the mode list from DDC.
1680          * Assume that the preferred modes are
1681          * arranged in priority order.
1682          */
1683         intel_ddc_get_modes(intel_output);
1684         if (list_empty(&connector->probed_modes) == false)
1685                 goto end;
1686
1687         /* Fetch modes from VBT */
1688         if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
1689                 newmode = drm_mode_duplicate(connector->dev,
1690                                              dev_priv->sdvo_lvds_vbt_mode);
1691                 if (newmode != NULL) {
1692                         /* Guarantee the mode is preferred */
1693                         newmode->type = (DRM_MODE_TYPE_PREFERRED |
1694                                          DRM_MODE_TYPE_DRIVER);
1695                         drm_mode_probed_add(connector, newmode);
1696                 }
1697         }
1698
1699 end:
1700         list_for_each_entry(newmode, &connector->probed_modes, head) {
1701                 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1702                         sdvo_priv->sdvo_lvds_fixed_mode =
1703                                 drm_mode_duplicate(connector->dev, newmode);
1704                         break;
1705                 }
1706         }
1707
1708 }
1709
1710 static int intel_sdvo_get_modes(struct drm_connector *connector)
1711 {
1712         struct intel_output *output = to_intel_output(connector);
1713         struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1714
1715         if (sdvo_priv->is_tv)
1716                 intel_sdvo_get_tv_modes(connector);
1717         else if (sdvo_priv->is_lvds == true)
1718                 intel_sdvo_get_lvds_modes(connector);
1719         else
1720                 intel_sdvo_get_ddc_modes(connector);
1721
1722         if (list_empty(&connector->probed_modes))
1723                 return 0;
1724         return 1;
1725 }
1726
1727 static void intel_sdvo_destroy(struct drm_connector *connector)
1728 {
1729         struct intel_output *intel_output = to_intel_output(connector);
1730         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1731
1732         if (intel_output->i2c_bus)
1733                 intel_i2c_destroy(intel_output->i2c_bus);
1734         if (intel_output->ddc_bus)
1735                 intel_i2c_destroy(intel_output->ddc_bus);
1736
1737         if (sdvo_priv->sdvo_lvds_fixed_mode != NULL)
1738                 drm_mode_destroy(connector->dev,
1739                                  sdvo_priv->sdvo_lvds_fixed_mode);
1740
1741         drm_sysfs_connector_remove(connector);
1742         drm_connector_cleanup(connector);
1743
1744         kfree(intel_output);
1745 }
1746
1747 static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
1748         .dpms = intel_sdvo_dpms,
1749         .mode_fixup = intel_sdvo_mode_fixup,
1750         .prepare = intel_encoder_prepare,
1751         .mode_set = intel_sdvo_mode_set,
1752         .commit = intel_encoder_commit,
1753 };
1754
1755 static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
1756         .dpms = drm_helper_connector_dpms,
1757         .save = intel_sdvo_save,
1758         .restore = intel_sdvo_restore,
1759         .detect = intel_sdvo_detect,
1760         .fill_modes = drm_helper_probe_single_connector_modes,
1761         .destroy = intel_sdvo_destroy,
1762 };
1763
1764 static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
1765         .get_modes = intel_sdvo_get_modes,
1766         .mode_valid = intel_sdvo_mode_valid,
1767         .best_encoder = intel_best_encoder,
1768 };
1769
1770 static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
1771 {
1772         drm_encoder_cleanup(encoder);
1773 }
1774
1775 static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
1776         .destroy = intel_sdvo_enc_destroy,
1777 };
1778
1779
1780 /**
1781  * Choose the appropriate DDC bus for control bus switch command for this
1782  * SDVO output based on the controlled output.
1783  *
1784  * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
1785  * outputs, then LVDS outputs.
1786  */
1787 static void
1788 intel_sdvo_select_ddc_bus(struct intel_sdvo_priv *dev_priv)
1789 {
1790         uint16_t mask = 0;
1791         unsigned int num_bits;
1792
1793         /* Make a mask of outputs less than or equal to our own priority in the
1794          * list.
1795          */
1796         switch (dev_priv->controlled_output) {
1797         case SDVO_OUTPUT_LVDS1:
1798                 mask |= SDVO_OUTPUT_LVDS1;
1799         case SDVO_OUTPUT_LVDS0:
1800                 mask |= SDVO_OUTPUT_LVDS0;
1801         case SDVO_OUTPUT_TMDS1:
1802                 mask |= SDVO_OUTPUT_TMDS1;
1803         case SDVO_OUTPUT_TMDS0:
1804                 mask |= SDVO_OUTPUT_TMDS0;
1805         case SDVO_OUTPUT_RGB1:
1806                 mask |= SDVO_OUTPUT_RGB1;
1807         case SDVO_OUTPUT_RGB0:
1808                 mask |= SDVO_OUTPUT_RGB0;
1809                 break;
1810         }
1811
1812         /* Count bits to find what number we are in the priority list. */
1813         mask &= dev_priv->caps.output_flags;
1814         num_bits = hweight16(mask);
1815         if (num_bits > 3) {
1816                 /* if more than 3 outputs, default to DDC bus 3 for now */
1817                 num_bits = 3;
1818         }
1819
1820         /* Corresponds to SDVO_CONTROL_BUS_DDCx */
1821         dev_priv->ddc_bus = 1 << num_bits;
1822 }
1823
1824 static bool
1825 intel_sdvo_get_digital_encoding_mode(struct intel_output *output)
1826 {
1827         struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1828         uint8_t status;
1829
1830         intel_sdvo_set_target_output(output, sdvo_priv->controlled_output);
1831
1832         intel_sdvo_write_cmd(output, SDVO_CMD_GET_ENCODE, NULL, 0);
1833         status = intel_sdvo_read_response(output, &sdvo_priv->is_hdmi, 1);
1834         if (status != SDVO_CMD_STATUS_SUCCESS)
1835                 return false;
1836         return true;
1837 }
1838
1839 static struct intel_output *
1840 intel_sdvo_chan_to_intel_output(struct intel_i2c_chan *chan)
1841 {
1842         struct drm_device *dev = chan->drm_dev;
1843         struct drm_connector *connector;
1844         struct intel_output *intel_output = NULL;
1845
1846         list_for_each_entry(connector,
1847                         &dev->mode_config.connector_list, head) {
1848                 if (to_intel_output(connector)->ddc_bus == &chan->adapter) {
1849                         intel_output = to_intel_output(connector);
1850                         break;
1851                 }
1852         }
1853         return intel_output;
1854 }
1855
1856 static int intel_sdvo_master_xfer(struct i2c_adapter *i2c_adap,
1857                                   struct i2c_msg msgs[], int num)
1858 {
1859         struct intel_output *intel_output;
1860         struct intel_sdvo_priv *sdvo_priv;
1861         struct i2c_algo_bit_data *algo_data;
1862         const struct i2c_algorithm *algo;
1863
1864         algo_data = (struct i2c_algo_bit_data *)i2c_adap->algo_data;
1865         intel_output =
1866                 intel_sdvo_chan_to_intel_output(
1867                                 (struct intel_i2c_chan *)(algo_data->data));
1868         if (intel_output == NULL)
1869                 return -EINVAL;
1870
1871         sdvo_priv = intel_output->dev_priv;
1872         algo = intel_output->i2c_bus->algo;
1873
1874         intel_sdvo_set_control_bus_switch(intel_output, sdvo_priv->ddc_bus);
1875         return algo->master_xfer(i2c_adap, msgs, num);
1876 }
1877
1878 static struct i2c_algorithm intel_sdvo_i2c_bit_algo = {
1879         .master_xfer    = intel_sdvo_master_xfer,
1880 };
1881
1882 static u8
1883 intel_sdvo_get_slave_addr(struct drm_device *dev, int output_device)
1884 {
1885         struct drm_i915_private *dev_priv = dev->dev_private;
1886         struct sdvo_device_mapping *my_mapping, *other_mapping;
1887
1888         if (output_device == SDVOB) {
1889                 my_mapping = &dev_priv->sdvo_mappings[0];
1890                 other_mapping = &dev_priv->sdvo_mappings[1];
1891         } else {
1892                 my_mapping = &dev_priv->sdvo_mappings[1];
1893                 other_mapping = &dev_priv->sdvo_mappings[0];
1894         }
1895
1896         /* If the BIOS described our SDVO device, take advantage of it. */
1897         if (my_mapping->slave_addr)
1898                 return my_mapping->slave_addr;
1899
1900         /* If the BIOS only described a different SDVO device, use the
1901          * address that it isn't using.
1902          */
1903         if (other_mapping->slave_addr) {
1904                 if (other_mapping->slave_addr == 0x70)
1905                         return 0x72;
1906                 else
1907                         return 0x70;
1908         }
1909
1910         /* No SDVO device info is found for another DVO port,
1911          * so use mapping assumption we had before BIOS parsing.
1912          */
1913         if (output_device == SDVOB)
1914                 return 0x70;
1915         else
1916                 return 0x72;
1917 }
1918
1919 static bool
1920 intel_sdvo_output_setup(struct intel_output *intel_output, uint16_t flags)
1921 {
1922         struct drm_connector *connector = &intel_output->base;
1923         struct drm_encoder *encoder = &intel_output->enc;
1924         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1925         bool ret = true, registered = false;
1926
1927         sdvo_priv->is_tv = false;
1928         intel_output->needs_tv_clock = false;
1929         sdvo_priv->is_lvds = false;
1930
1931         if (device_is_registered(&connector->kdev)) {
1932                 drm_sysfs_connector_remove(connector);
1933                 registered = true;
1934         }
1935
1936         if (flags &
1937             (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) {
1938                 if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_TMDS0)
1939                         sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS0;
1940                 else
1941                         sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS1;
1942
1943                 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
1944                 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
1945
1946                 if (intel_sdvo_get_supp_encode(intel_output,
1947                                                &sdvo_priv->encode) &&
1948                     intel_sdvo_get_digital_encoding_mode(intel_output) &&
1949                     sdvo_priv->is_hdmi) {
1950                         /* enable hdmi encoding mode if supported */
1951                         intel_sdvo_set_encode(intel_output, SDVO_ENCODE_HDMI);
1952                         intel_sdvo_set_colorimetry(intel_output,
1953                                                    SDVO_COLORIMETRY_RGB256);
1954                         connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
1955                 }
1956         } else if (flags & SDVO_OUTPUT_SVID0) {
1957
1958                 sdvo_priv->controlled_output = SDVO_OUTPUT_SVID0;
1959                 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
1960                 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
1961                 sdvo_priv->is_tv = true;
1962                 intel_output->needs_tv_clock = true;
1963         } else if (flags & SDVO_OUTPUT_RGB0) {
1964
1965                 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB0;
1966                 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
1967                 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
1968         } else if (flags & SDVO_OUTPUT_RGB1) {
1969
1970                 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB1;
1971                 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
1972                 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
1973         } else if (flags & SDVO_OUTPUT_LVDS0) {
1974
1975                 sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS0;
1976                 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
1977                 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
1978                 sdvo_priv->is_lvds = true;
1979         } else if (flags & SDVO_OUTPUT_LVDS1) {
1980
1981                 sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS1;
1982                 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
1983                 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
1984                 sdvo_priv->is_lvds = true;
1985         } else {
1986
1987                 unsigned char bytes[2];
1988
1989                 sdvo_priv->controlled_output = 0;
1990                 memcpy(bytes, &sdvo_priv->caps.output_flags, 2);
1991                 DRM_DEBUG_KMS(I915_SDVO,
1992                                 "%s: Unknown SDVO output type (0x%02x%02x)\n",
1993                                   SDVO_NAME(sdvo_priv),
1994                                   bytes[0], bytes[1]);
1995                 ret = false;
1996         }
1997
1998         if (ret && registered)
1999                 ret = drm_sysfs_connector_add(connector) == 0 ? true : false;
2000
2001
2002         return ret;
2003
2004 }
2005
2006 bool intel_sdvo_init(struct drm_device *dev, int output_device)
2007 {
2008         struct drm_connector *connector;
2009         struct intel_output *intel_output;
2010         struct intel_sdvo_priv *sdvo_priv;
2011
2012         u8 ch[0x40];
2013         int i;
2014
2015         intel_output = kcalloc(sizeof(struct intel_output)+sizeof(struct intel_sdvo_priv), 1, GFP_KERNEL);
2016         if (!intel_output) {
2017                 return false;
2018         }
2019
2020         sdvo_priv = (struct intel_sdvo_priv *)(intel_output + 1);
2021         sdvo_priv->output_device = output_device;
2022
2023         intel_output->dev_priv = sdvo_priv;
2024         intel_output->type = INTEL_OUTPUT_SDVO;
2025
2026         /* setup the DDC bus. */
2027         if (output_device == SDVOB)
2028                 intel_output->i2c_bus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOB");
2029         else
2030                 intel_output->i2c_bus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOC");
2031
2032         if (!intel_output->i2c_bus)
2033                 goto err_inteloutput;
2034
2035         sdvo_priv->slave_addr = intel_sdvo_get_slave_addr(dev, output_device);
2036
2037         /* Save the bit-banging i2c functionality for use by the DDC wrapper */
2038         intel_sdvo_i2c_bit_algo.functionality = intel_output->i2c_bus->algo->functionality;
2039
2040         /* Read the regs to test if we can talk to the device */
2041         for (i = 0; i < 0x40; i++) {
2042                 if (!intel_sdvo_read_byte(intel_output, i, &ch[i])) {
2043                         DRM_DEBUG_KMS(I915_SDVO,
2044                                         "No SDVO device found on SDVO%c\n",
2045                                         output_device == SDVOB ? 'B' : 'C');
2046                         goto err_i2c;
2047                 }
2048         }
2049
2050         /* setup the DDC bus. */
2051         if (output_device == SDVOB)
2052                 intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOB DDC BUS");
2053         else
2054                 intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOC DDC BUS");
2055
2056         if (intel_output->ddc_bus == NULL)
2057                 goto err_i2c;
2058
2059         /* Wrap with our custom algo which switches to DDC mode */
2060         intel_output->ddc_bus->algo = &intel_sdvo_i2c_bit_algo;
2061
2062         /* In defaut case sdvo lvds is false */
2063         intel_sdvo_get_capabilities(intel_output, &sdvo_priv->caps);
2064
2065         if (intel_sdvo_output_setup(intel_output,
2066                                     sdvo_priv->caps.output_flags) != true) {
2067                 DRM_DEBUG("SDVO output failed to setup on SDVO%c\n",
2068                           output_device == SDVOB ? 'B' : 'C');
2069                 goto err_i2c;
2070         }
2071
2072
2073         connector = &intel_output->base;
2074         drm_connector_init(dev, connector, &intel_sdvo_connector_funcs,
2075                            connector->connector_type);
2076
2077         drm_connector_helper_add(connector, &intel_sdvo_connector_helper_funcs);
2078         connector->interlace_allowed = 0;
2079         connector->doublescan_allowed = 0;
2080         connector->display_info.subpixel_order = SubPixelHorizontalRGB;
2081
2082         drm_encoder_init(dev, &intel_output->enc,
2083                         &intel_sdvo_enc_funcs, intel_output->enc.encoder_type);
2084
2085         drm_encoder_helper_add(&intel_output->enc, &intel_sdvo_helper_funcs);
2086
2087         drm_mode_connector_attach_encoder(&intel_output->base, &intel_output->enc);
2088         drm_sysfs_connector_add(connector);
2089
2090         intel_sdvo_select_ddc_bus(sdvo_priv);
2091
2092         /* Set the input timing to the screen. Assume always input 0. */
2093         intel_sdvo_set_target_input(intel_output, true, false);
2094
2095         intel_sdvo_get_input_pixel_clock_range(intel_output,
2096                                                &sdvo_priv->pixel_clock_min,
2097                                                &sdvo_priv->pixel_clock_max);
2098
2099
2100         DRM_DEBUG_KMS(I915_SDVO, "%s device VID/DID: %02X:%02X.%02X, "
2101                         "clock range %dMHz - %dMHz, "
2102                         "input 1: %c, input 2: %c, "
2103                         "output 1: %c, output 2: %c\n",
2104                         SDVO_NAME(sdvo_priv),
2105                         sdvo_priv->caps.vendor_id, sdvo_priv->caps.device_id,
2106                         sdvo_priv->caps.device_rev_id,
2107                         sdvo_priv->pixel_clock_min / 1000,
2108                         sdvo_priv->pixel_clock_max / 1000,
2109                         (sdvo_priv->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2110                         (sdvo_priv->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
2111                         /* check currently supported outputs */
2112                         sdvo_priv->caps.output_flags &
2113                         (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
2114                         sdvo_priv->caps.output_flags &
2115                         (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
2116
2117         return true;
2118
2119 err_i2c:
2120         if (intel_output->ddc_bus != NULL)
2121                 intel_i2c_destroy(intel_output->ddc_bus);
2122         if (intel_output->i2c_bus != NULL)
2123                 intel_i2c_destroy(intel_output->i2c_bus);
2124 err_inteloutput:
2125         kfree(intel_output);
2126
2127         return false;
2128 }