SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/i915/intel_sdvo.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2007 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  *
  25  * Authors:
  26  *      Eric Anholt <eric@anholt.net>
  27  */
  28 #include <linux/i2c.h>
  29 #include <linux/delay.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "drm_crtc.h"
  33 #include "intel_drv.h"
  34 #include "i915_drm.h"
  35 #include "i915_drv.h"
  36 #include "intel_sdvo_regs.h"
  37
  38 #undef SDVO_DEBUG
  39 struct intel_sdvo_priv {
  40         u8 slave_addr;
  41
  42         /* Register for the SDVO device: SDVOB or SDVOC */
  43         int output_device;
  44
  45         /* Active outputs controlled by this SDVO output */
  46         uint16_t controlled_output;
  47
  48         /*
  49          * Capabilities of the SDVO device returned by
  50          * i830_sdvo_get_capabilities()
  51          */
  52         struct intel_sdvo_caps caps;
  53
  54         /* Pixel clock limitations reported by the SDVO device, in kHz */
  55         int pixel_clock_min, pixel_clock_max;
  56
  57         /**
  58          * This is set if we're going to treat the device as TV-out.
  59          *
  60          * While we have these nice friendly flags for output types that ought
  61          * to decide this for us, the S-Video output on our HDMI+S-Video card
  62          * shows up as RGB1 (VGA).
  63          */
  64         bool is_tv;
  65
  66         /**
  67          * This is set if we treat the device as HDMI, instead of DVI.
  68          */
  69         bool is_hdmi;
  70
  71         /**
  72          * This is set if we detect output of sdvo device as LVDS.
  73          */
  74         bool is_lvds;
  75
  76         /**
  77          * This is sdvo flags for input timing.
  78          */
  79         uint8_t sdvo_flags;
  80
  81         /**
  82          * This is sdvo fixed pannel mode pointer
  83          */
  84         struct drm_display_mode *sdvo_lvds_fixed_mode;
  85
  86         /**
  87          * Returned SDTV resolutions allowed for the current format, if the
  88          * device reported it.
  89          */
  90         struct intel_sdvo_sdtv_resolution_reply sdtv_resolutions;
  91
  92         /**
  93          * Current selected TV format.
  94          *
  95          * This is stored in the same structure that's passed to the device, for
  96          * convenience.
  97          */
  98         struct intel_sdvo_tv_format tv_format;
  99
 100         /*
 101          * supported encoding mode, used to determine whether HDMI is
 102          * supported
 103          */
 104         struct intel_sdvo_encode encode;
 105
 106         /* DDC bus used by this SDVO output */
 107         uint8_t ddc_bus;
 108
 109         int save_sdvo_mult;
 110         u16 save_active_outputs;
 111         struct intel_sdvo_dtd save_input_dtd_1, save_input_dtd_2;
 112         struct intel_sdvo_dtd save_output_dtd[16];
 113         u32 save_SDVOX;
 114 };
 115
 116 /**
 117  * Writes the SDVOB or SDVOC with the given value, but always writes both
 118  * SDVOB and SDVOC to work around apparent hardware issues (according to
 119  * comments in the BIOS).
 120  */
 121 static void intel_sdvo_write_sdvox(struct intel_output *intel_output, u32 val)
 122 {
 123         struct drm_device *dev = intel_output->base.dev;
 124         struct drm_i915_private *dev_priv = dev->dev_private;
 125         struct intel_sdvo_priv   *sdvo_priv = intel_output->dev_priv;
 126         u32 bval = val, cval = val;
 127         int i;
 128
 129         if (sdvo_priv->output_device == SDVOB) {
 130                 cval = I915_READ(SDVOC);
 131         } else {
 132                 bval = I915_READ(SDVOB);
 133         }
 134         /*
 135          * Write the registers twice for luck. Sometimes,
 136          * writing them only once doesn't appear to 'stick'.
 137          * The BIOS does this too. Yay, magic
 138          */
 139         for (i = 0; i < 2; i++)
 140         {
 141                 I915_WRITE(SDVOB, bval);
 142                 I915_READ(SDVOB);
 143                 I915_WRITE(SDVOC, cval);
 144                 I915_READ(SDVOC);
 145         }
 146 }
 147
 148 static bool intel_sdvo_read_byte(struct intel_output *intel_output, u8 addr,
 149                                  u8 *ch)
 150 {
 151         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
 152         u8 out_buf[2];
 153         u8 buf[2];
 154         int ret;
 155
 156         struct i2c_msg msgs[] = {
 157                 {
 158                         .addr = sdvo_priv->slave_addr >> 1,
 159                         .flags = 0,
 160                         .len = 1,
 161                         .buf = out_buf,
 162                 },
 163                 {
 164                         .addr = sdvo_priv->slave_addr >> 1,
 165                         .flags = I2C_M_RD,
 166                         .len = 1,
 167                         .buf = buf,
 168                 }
 169         };
 170
 171         out_buf[0] = addr;
 172         out_buf[1] = 0;
 173
 174         if ((ret = i2c_transfer(intel_output->i2c_bus, msgs, 2)) == 2)
 175         {
 176                 *ch = buf[0];
 177                 return true;
 178         }
 179
 180         DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
 181         return false;
 182 }
 183
 184 static bool intel_sdvo_write_byte(struct intel_output *intel_output, int addr,
 185                                   u8 ch)
 186 {
 187         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
 188         u8 out_buf[2];
 189         struct i2c_msg msgs[] = {
 190                 {
 191                         .addr = sdvo_priv->slave_addr >> 1,
 192                         .flags = 0,
 193                         .len = 2,
 194                         .buf = out_buf,
 195                 }
 196         };
 197
 198         out_buf[0] = addr;
 199         out_buf[1] = ch;
 200
 201         if (i2c_transfer(intel_output->i2c_bus, msgs, 1) == 1)
 202         {
 203                 return true;
 204         }
 205         return false;
 206 }
 207
 208 #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
 209 /** Mapping of command numbers to names, for debug output */
 210 static const struct _sdvo_cmd_name {
 211         u8 cmd;
 212         char *name;
 213 } sdvo_cmd_names[] = {
 214     SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
 215     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
 216     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
 217     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
 218     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
 219     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
 220     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
 221     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
 222     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
 223     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
 224     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
 225     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
 226     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
 227     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
 228     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
 229     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
 230     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
 231     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
 232     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
 233     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
 234     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
 235     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
 236     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
 237     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
 238     SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
 239     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
 240     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
 241     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
 242     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
 243     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
 244     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
 245     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
 246     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
 247     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
 248     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
 249     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
 250     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
 251     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
 252     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
 253     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
 254     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
 255     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
 256     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
 257     /* HDMI op code */
 258     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
 259     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
 260     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
 261     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
 262     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
 263     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
 264     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
 265     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
 266     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
 267     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
 268     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
 269     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
 270     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
 271     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
 272     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
 273     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
 274     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
 275     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
 276     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
 277     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
 278 };
 279
 280 #define SDVO_NAME(dev_priv) ((dev_priv)->output_device == SDVOB ? "SDVOB" : "SDVOC")
 281 #define SDVO_PRIV(output)   ((struct intel_sdvo_priv *) (output)->dev_priv)
 282
 283 #ifdef SDVO_DEBUG
 284 static void intel_sdvo_debug_write(struct intel_output *intel_output, u8 cmd,
 285                                    void *args, int args_len)
 286 {
 287         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
 288         int i;
 289
 290         DRM_DEBUG_KMS("%s: W: %02X ",
 291                                 SDVO_NAME(sdvo_priv), cmd);
 292         for (i = 0; i < args_len; i++)
 293                 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
 294         for (; i < 8; i++)
 295                 DRM_LOG_KMS("   ");
 296         for (i = 0; i < sizeof(sdvo_cmd_names) / sizeof(sdvo_cmd_names[0]); i++) {
 297                 if (cmd == sdvo_cmd_names[i].cmd) {
 298                         DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
 299                         break;
 300                 }
 301         }
 302         if (i == sizeof(sdvo_cmd_names)/ sizeof(sdvo_cmd_names[0]))
 303                 DRM_LOG_KMS("(%02X)", cmd);
 304         DRM_LOG_KMS("\n");
 305 }
 306 #else
 307 #define intel_sdvo_debug_write(o, c, a, l)
 308 #endif
 309
 310 static void intel_sdvo_write_cmd(struct intel_output *intel_output, u8 cmd,
 311                                  void *args, int args_len)
 312 {
 313         int i;
 314
 315         intel_sdvo_debug_write(intel_output, cmd, args, args_len);
 316
 317         for (i = 0; i < args_len; i++) {
 318                 intel_sdvo_write_byte(intel_output, SDVO_I2C_ARG_0 - i,
 319                                       ((u8*)args)[i]);
 320         }
 321
 322         intel_sdvo_write_byte(intel_output, SDVO_I2C_OPCODE, cmd);
 323 }
 324
 325 #ifdef SDVO_DEBUG
 326 static const char *cmd_status_names[] = {
 327         "Power on",
 328         "Success",
 329         "Not supported",
 330         "Invalid arg",
 331         "Pending",
 332         "Target not specified",
 333         "Scaling not supported"
 334 };
 335
 336 static void intel_sdvo_debug_response(struct intel_output *intel_output,
 337                                       void *response, int response_len,
 338                                       u8 status)
 339 {
 340         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
 341         int i;
 342
 343         DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(sdvo_priv));
 344         for (i = 0; i < response_len; i++)
 345                 DRM_LOG_KMS("%02X ", ((u8 *)response)[i]);
 346         for (; i < 8; i++)
 347                 DRM_LOG_KMS("   ");
 348         if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
 349                 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
 350         else
 351                 DRM_LOG_KMS("(??? %d)", status);
 352         DRM_LOG_KMS("\n");
 353 }
 354 #else
 355 #define intel_sdvo_debug_response(o, r, l, s)
 356 #endif
 357
 358 static u8 intel_sdvo_read_response(struct intel_output *intel_output,
 359                                    void *response, int response_len)
 360 {
 361         int i;
 362         u8 status;
 363         u8 retry = 50;
 364
 365         while (retry--) {
 366                 /* Read the command response */
 367                 for (i = 0; i < response_len; i++) {
 368                         intel_sdvo_read_byte(intel_output,
 369                                              SDVO_I2C_RETURN_0 + i,
 370                                              &((u8 *)response)[i]);
 371                 }
 372
 373                 /* read the return status */
 374                 intel_sdvo_read_byte(intel_output, SDVO_I2C_CMD_STATUS,
 375                                      &status);
 376
 377                 intel_sdvo_debug_response(intel_output, response, response_len,
 378                                           status);
 379                 if (status != SDVO_CMD_STATUS_PENDING)
 380                         return status;
 381
 382                 mdelay(50);
 383         }
 384
 385         return status;
 386 }
 387
 388 static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
 389 {
 390         if (mode->clock >= 100000)
 391                 return 1;
 392         else if (mode->clock >= 50000)
 393                 return 2;
 394         else
 395                 return 4;
 396 }
 397
 398 /**
 399  * Don't check status code from this as it switches the bus back to the
 400  * SDVO chips which defeats the purpose of doing a bus switch in the first
 401  * place.
 402  */
 403 static void intel_sdvo_set_control_bus_switch(struct intel_output *intel_output,
 404                                               u8 target)
 405 {
 406         intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_CONTROL_BUS_SWITCH, &target, 1);
 407 }
 408
 409 static bool intel_sdvo_set_target_input(struct intel_output *intel_output, bool target_0, bool target_1)
 410 {
 411         struct intel_sdvo_set_target_input_args targets = {0};
 412         u8 status;
 413
 414         if (target_0 && target_1)
 415                 return SDVO_CMD_STATUS_NOTSUPP;
 416
 417         if (target_1)
 418                 targets.target_1 = 1;
 419
 420         intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_TARGET_INPUT, &targets,
 421                              sizeof(targets));
 422
 423         status = intel_sdvo_read_response(intel_output, NULL, 0);
 424
 425         return (status == SDVO_CMD_STATUS_SUCCESS);
 426 }
 427
 428 /**
 429  * Return whether each input is trained.
 430  *
 431  * This function is making an assumption about the layout of the response,
 432  * which should be checked against the docs.
 433  */
 434 static bool intel_sdvo_get_trained_inputs(struct intel_output *intel_output, bool *input_1, bool *input_2)
 435 {
 436         struct intel_sdvo_get_trained_inputs_response response;
 437         u8 status;
 438
 439         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_TRAINED_INPUTS, NULL, 0);
 440         status = intel_sdvo_read_response(intel_output, &response, sizeof(response));
 441         if (status != SDVO_CMD_STATUS_SUCCESS)
 442                 return false;
 443
 444         *input_1 = response.input0_trained;
 445         *input_2 = response.input1_trained;
 446         return true;
 447 }
 448
 449 static bool intel_sdvo_get_active_outputs(struct intel_output *intel_output,
 450                                           u16 *outputs)
 451 {
 452         u8 status;
 453
 454         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_OUTPUTS, NULL, 0);
 455         status = intel_sdvo_read_response(intel_output, outputs, sizeof(*outputs));
 456
 457         return (status == SDVO_CMD_STATUS_SUCCESS);
 458 }
 459
 460 static bool intel_sdvo_set_active_outputs(struct intel_output *intel_output,
 461                                           u16 outputs)
 462 {
 463         u8 status;
 464
 465         intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_OUTPUTS, &outputs,
 466                              sizeof(outputs));
 467         status = intel_sdvo_read_response(intel_output, NULL, 0);
 468         return (status == SDVO_CMD_STATUS_SUCCESS);
 469 }
 470
 471 static bool intel_sdvo_set_encoder_power_state(struct intel_output *intel_output,
 472                                                int mode)
 473 {
 474         u8 status, state = SDVO_ENCODER_STATE_ON;
 475
 476         switch (mode) {
 477         case DRM_MODE_DPMS_ON:
 478                 state = SDVO_ENCODER_STATE_ON;
 479                 break;
 480         case DRM_MODE_DPMS_STANDBY:
 481                 state = SDVO_ENCODER_STATE_STANDBY;
 482                 break;
 483         case DRM_MODE_DPMS_SUSPEND:
 484                 state = SDVO_ENCODER_STATE_SUSPEND;
 485                 break;
 486         case DRM_MODE_DPMS_OFF:
 487                 state = SDVO_ENCODER_STATE_OFF;
 488                 break;
 489         }
 490
 491         intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ENCODER_POWER_STATE, &state,
 492                              sizeof(state));
 493         status = intel_sdvo_read_response(intel_output, NULL, 0);
 494
 495         return (status == SDVO_CMD_STATUS_SUCCESS);
 496 }
 497
 498 static bool intel_sdvo_get_input_pixel_clock_range(struct intel_output *intel_output,
 499                                                    int *clock_min,
 500                                                    int *clock_max)
 501 {
 502         struct intel_sdvo_pixel_clock_range clocks;
 503         u8 status;
 504
 505         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
 506                              NULL, 0);
 507
 508         status = intel_sdvo_read_response(intel_output, &clocks, sizeof(clocks));
 509
 510         if (status != SDVO_CMD_STATUS_SUCCESS)
 511                 return false;
 512
 513         /* Convert the values from units of 10 kHz to kHz. */
 514         *clock_min = clocks.min * 10;
 515         *clock_max = clocks.max * 10;
 516
 517         return true;
 518 }
 519
 520 static bool intel_sdvo_set_target_output(struct intel_output *intel_output,
 521                                          u16 outputs)
 522 {
 523         u8 status;
 524
 525         intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_TARGET_OUTPUT, &outputs,
 526                              sizeof(outputs));
 527
 528         status = intel_sdvo_read_response(intel_output, NULL, 0);
 529         return (status == SDVO_CMD_STATUS_SUCCESS);
 530 }
 531
 532 static bool intel_sdvo_get_timing(struct intel_output *intel_output, u8 cmd,
 533                                   struct intel_sdvo_dtd *dtd)
 534 {
 535         u8 status;
 536
 537         intel_sdvo_write_cmd(intel_output, cmd, NULL, 0);
 538         status = intel_sdvo_read_response(intel_output, &dtd->part1,
 539                                           sizeof(dtd->part1));
 540         if (status != SDVO_CMD_STATUS_SUCCESS)
 541                 return false;
 542
 543         intel_sdvo_write_cmd(intel_output, cmd + 1, NULL, 0);
 544         status = intel_sdvo_read_response(intel_output, &dtd->part2,
 545                                           sizeof(dtd->part2));
 546         if (status != SDVO_CMD_STATUS_SUCCESS)
 547                 return false;
 548
 549         return true;
 550 }
 551
 552 static bool intel_sdvo_get_input_timing(struct intel_output *intel_output,
 553                                          struct intel_sdvo_dtd *dtd)
 554 {
 555         return intel_sdvo_get_timing(intel_output,
 556                                      SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
 557 }
 558
 559 static bool intel_sdvo_get_output_timing(struct intel_output *intel_output,
 560                                          struct intel_sdvo_dtd *dtd)
 561 {
 562         return intel_sdvo_get_timing(intel_output,
 563                                      SDVO_CMD_GET_OUTPUT_TIMINGS_PART1, dtd);
 564 }
 565
 566 static bool intel_sdvo_set_timing(struct intel_output *intel_output, u8 cmd,
 567                                   struct intel_sdvo_dtd *dtd)
 568 {
 569         u8 status;
 570
 571         intel_sdvo_write_cmd(intel_output, cmd, &dtd->part1, sizeof(dtd->part1));
 572         status = intel_sdvo_read_response(intel_output, NULL, 0);
 573         if (status != SDVO_CMD_STATUS_SUCCESS)
 574                 return false;
 575
 576         intel_sdvo_write_cmd(intel_output, cmd + 1, &dtd->part2, sizeof(dtd->part2));
 577         status = intel_sdvo_read_response(intel_output, NULL, 0);
 578         if (status != SDVO_CMD_STATUS_SUCCESS)
 579                 return false;
 580
 581         return true;
 582 }
 583
 584 static bool intel_sdvo_set_input_timing(struct intel_output *intel_output,
 585                                          struct intel_sdvo_dtd *dtd)
 586 {
 587         return intel_sdvo_set_timing(intel_output,
 588                                      SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
 589 }
 590
 591 static bool intel_sdvo_set_output_timing(struct intel_output *intel_output,
 592                                          struct intel_sdvo_dtd *dtd)
 593 {
 594         return intel_sdvo_set_timing(intel_output,
 595                                      SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
 596 }
 597
 598 static bool
 599 intel_sdvo_create_preferred_input_timing(struct intel_output *output,
 600                                          uint16_t clock,
 601                                          uint16_t width,
 602                                          uint16_t height)
 603 {
 604         struct intel_sdvo_preferred_input_timing_args args;
 605         struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
 606         uint8_t status;
 607
 608         memset(&args, 0, sizeof(args));
 609         args.clock = clock;
 610         args.width = width;
 611         args.height = height;
 612         args.interlace = 0;
 613
 614         if (sdvo_priv->is_lvds &&
 615            (sdvo_priv->sdvo_lvds_fixed_mode->hdisplay != width ||
 616             sdvo_priv->sdvo_lvds_fixed_mode->vdisplay != height))
 617                 args.scaled = 1;
 618
 619         intel_sdvo_write_cmd(output, SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
 620                              &args, sizeof(args));
 621         status = intel_sdvo_read_response(output, NULL, 0);
 622         if (status != SDVO_CMD_STATUS_SUCCESS)
 623                 return false;
 624
 625         return true;
 626 }
 627
 628 static bool intel_sdvo_get_preferred_input_timing(struct intel_output *output,
 629                                                   struct intel_sdvo_dtd *dtd)
 630 {
 631         bool status;
 632
 633         intel_sdvo_write_cmd(output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
 634                              NULL, 0);
 635
 636         status = intel_sdvo_read_response(output, &dtd->part1,
 637                                           sizeof(dtd->part1));
 638         if (status != SDVO_CMD_STATUS_SUCCESS)
 639                 return false;
 640
 641         intel_sdvo_write_cmd(output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
 642                              NULL, 0);
 643
 644         status = intel_sdvo_read_response(output, &dtd->part2,
 645                                           sizeof(dtd->part2));
 646         if (status != SDVO_CMD_STATUS_SUCCESS)
 647                 return false;
 648
 649         return false;
 650 }
 651
 652 static int intel_sdvo_get_clock_rate_mult(struct intel_output *intel_output)
 653 {
 654         u8 response, status;
 655
 656         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_CLOCK_RATE_MULT, NULL, 0);
 657         status = intel_sdvo_read_response(intel_output, &response, 1);
 658
 659         if (status != SDVO_CMD_STATUS_SUCCESS) {
 660                 DRM_DEBUG_KMS("Couldn't get SDVO clock rate multiplier\n");
 661                 return SDVO_CLOCK_RATE_MULT_1X;
 662         } else {
 663                 DRM_DEBUG_KMS("Current clock rate multiplier: %d\n", response);
 664         }
 665
 666         return response;
 667 }
 668
 669 static bool intel_sdvo_set_clock_rate_mult(struct intel_output *intel_output, u8 val)
 670 {
 671         u8 status;
 672
 673         intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
 674         status = intel_sdvo_read_response(intel_output, NULL, 0);
 675         if (status != SDVO_CMD_STATUS_SUCCESS)
 676                 return false;
 677
 678         return true;
 679 }
 680
 681 static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
 682                                          struct drm_display_mode *mode)
 683 {
 684         uint16_t width, height;
 685         uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
 686         uint16_t h_sync_offset, v_sync_offset;
 687
 688         width = mode->crtc_hdisplay;
 689         height = mode->crtc_vdisplay;
 690
 691         /* do some mode translations */
 692         h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
 693         h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
 694
 695         v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
 696         v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
 697
 698         h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
 699         v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
 700
 701         dtd->part1.clock = mode->clock / 10;
 702         dtd->part1.h_active = width & 0xff;
 703         dtd->part1.h_blank = h_blank_len & 0xff;
 704         dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
 705                 ((h_blank_len >> 8) & 0xf);
 706         dtd->part1.v_active = height & 0xff;
 707         dtd->part1.v_blank = v_blank_len & 0xff;
 708         dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
 709                 ((v_blank_len >> 8) & 0xf);
 710
 711         dtd->part2.h_sync_off = h_sync_offset & 0xff;
 712         dtd->part2.h_sync_width = h_sync_len & 0xff;
 713         dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
 714                 (v_sync_len & 0xf);
 715         dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
 716                 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
 717                 ((v_sync_len & 0x30) >> 4);
 718
 719         dtd->part2.dtd_flags = 0x18;
 720         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
 721                 dtd->part2.dtd_flags |= 0x2;
 722         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
 723                 dtd->part2.dtd_flags |= 0x4;
 724
 725         dtd->part2.sdvo_flags = 0;
 726         dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
 727         dtd->part2.reserved = 0;
 728 }
 729
 730 static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
 731                                          struct intel_sdvo_dtd *dtd)
 732 {
 733         mode->hdisplay = dtd->part1.h_active;
 734         mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
 735         mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
 736         mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
 737         mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
 738         mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
 739         mode->htotal = mode->hdisplay + dtd->part1.h_blank;
 740         mode->htotal += (dtd->part1.h_high & 0xf) << 8;
 741
 742         mode->vdisplay = dtd->part1.v_active;
 743         mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
 744         mode->vsync_start = mode->vdisplay;
 745         mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
 746         mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
 747         mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
 748         mode->vsync_end = mode->vsync_start +
 749                 (dtd->part2.v_sync_off_width & 0xf);
 750         mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
 751         mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
 752         mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
 753
 754         mode->clock = dtd->part1.clock * 10;
 755
 756         mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
 757         if (dtd->part2.dtd_flags & 0x2)
 758                 mode->flags |= DRM_MODE_FLAG_PHSYNC;
 759         if (dtd->part2.dtd_flags & 0x4)
 760                 mode->flags |= DRM_MODE_FLAG_PVSYNC;
 761 }
 762
 763 static bool intel_sdvo_get_supp_encode(struct intel_output *output,
 764                                        struct intel_sdvo_encode *encode)
 765 {
 766         uint8_t status;
 767
 768         intel_sdvo_write_cmd(output, SDVO_CMD_GET_SUPP_ENCODE, NULL, 0);
 769         status = intel_sdvo_read_response(output, encode, sizeof(*encode));
 770         if (status != SDVO_CMD_STATUS_SUCCESS) { /* non-support means DVI */
 771                 memset(encode, 0, sizeof(*encode));
 772                 return false;
 773         }
 774
 775         return true;
 776 }
 777
 778 static bool intel_sdvo_set_encode(struct intel_output *output, uint8_t mode)
 779 {
 780         uint8_t status;
 781
 782         intel_sdvo_write_cmd(output, SDVO_CMD_SET_ENCODE, &mode, 1);
 783         status = intel_sdvo_read_response(output, NULL, 0);
 784
 785         return (status == SDVO_CMD_STATUS_SUCCESS);
 786 }
 787
 788 static bool intel_sdvo_set_colorimetry(struct intel_output *output,
 789                                        uint8_t mode)
 790 {
 791         uint8_t status;
 792
 793         intel_sdvo_write_cmd(output, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
 794         status = intel_sdvo_read_response(output, NULL, 0);
 795
 796         return (status == SDVO_CMD_STATUS_SUCCESS);
 797 }
 798
 799 #if 0
 800 static void intel_sdvo_dump_hdmi_buf(struct intel_output *output)
 801 {
 802         int i, j;
 803         uint8_t set_buf_index[2];
 804         uint8_t av_split;
 805         uint8_t buf_size;
 806         uint8_t buf[48];
 807         uint8_t *pos;
 808
 809         intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_AV_SPLIT, NULL, 0);
 810         intel_sdvo_read_response(output, &av_split, 1);
 811
 812         for (i = 0; i <= av_split; i++) {
 813                 set_buf_index[0] = i; set_buf_index[1] = 0;
 814                 intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_INDEX,
 815                                      set_buf_index, 2);
 816                 intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
 817                 intel_sdvo_read_response(output, &buf_size, 1);
 818
 819                 pos = buf;
 820                 for (j = 0; j <= buf_size; j += 8) {
 821                         intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_DATA,
 822                                              NULL, 0);
 823                         intel_sdvo_read_response(output, pos, 8);
 824                         pos += 8;
 825                 }
 826         }
 827 }
 828 #endif
 829
 830 static void intel_sdvo_set_hdmi_buf(struct intel_output *output, int index,
 831                                 uint8_t *data, int8_t size, uint8_t tx_rate)
 832 {
 833     uint8_t set_buf_index[2];
 834
 835     set_buf_index[0] = index;
 836     set_buf_index[1] = 0;
 837
 838     intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_INDEX, set_buf_index, 2);
 839
 840     for (; size > 0; size -= 8) {
 841         intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_DATA, data, 8);
 842         data += 8;
 843     }
 844
 845     intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1);
 846 }
 847
 848 static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size)
 849 {
 850         uint8_t csum = 0;
 851         int i;
 852
 853         for (i = 0; i < size; i++)
 854                 csum += data[i];
 855
 856         return 0x100 - csum;
 857 }
 858
 859 #define DIP_TYPE_AVI    0x82
 860 #define DIP_VERSION_AVI 0x2
 861 #define DIP_LEN_AVI     13
 862
 863 struct dip_infoframe {
 864         uint8_t type;
 865         uint8_t version;
 866         uint8_t len;
 867         uint8_t checksum;
 868         union {
 869                 struct {
 870                         /* Packet Byte #1 */
 871                         uint8_t S:2;
 872                         uint8_t B:2;
 873                         uint8_t A:1;
 874                         uint8_t Y:2;
 875                         uint8_t rsvd1:1;
 876                         /* Packet Byte #2 */
 877                         uint8_t R:4;
 878                         uint8_t M:2;
 879                         uint8_t C:2;
 880                         /* Packet Byte #3 */
 881                         uint8_t SC:2;
 882                         uint8_t Q:2;
 883                         uint8_t EC:3;
 884                         uint8_t ITC:1;
 885                         /* Packet Byte #4 */
 886                         uint8_t VIC:7;
 887                         uint8_t rsvd2:1;
 888                         /* Packet Byte #5 */
 889                         uint8_t PR:4;
 890                         uint8_t rsvd3:4;
 891                         /* Packet Byte #6~13 */
 892                         uint16_t top_bar_end;
 893                         uint16_t bottom_bar_start;
 894                         uint16_t left_bar_end;
 895                         uint16_t right_bar_start;
 896                 } avi;
 897                 struct {
 898                         /* Packet Byte #1 */
 899                         uint8_t channel_count:3;
 900                         uint8_t rsvd1:1;
 901                         uint8_t coding_type:4;
 902                         /* Packet Byte #2 */
 903                         uint8_t sample_size:2; /* SS0, SS1 */
 904                         uint8_t sample_frequency:3;
 905                         uint8_t rsvd2:3;
 906                         /* Packet Byte #3 */
 907                         uint8_t coding_type_private:5;
 908                         uint8_t rsvd3:3;
 909                         /* Packet Byte #4 */
 910                         uint8_t channel_allocation;
 911                         /* Packet Byte #5 */
 912                         uint8_t rsvd4:3;
 913                         uint8_t level_shift:4;
 914                         uint8_t downmix_inhibit:1;
 915                 } audio;
 916                 uint8_t payload[28];
 917         } __attribute__ ((packed)) u;
 918 } __attribute__((packed));
 919
 920 static void intel_sdvo_set_avi_infoframe(struct intel_output *output,
 921                                          struct drm_display_mode * mode)
 922 {
 923         struct dip_infoframe avi_if = {
 924                 .type = DIP_TYPE_AVI,
 925                 .version = DIP_VERSION_AVI,
 926                 .len = DIP_LEN_AVI,
 927         };
 928
 929         avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if,
 930                                                     4 + avi_if.len);
 931         intel_sdvo_set_hdmi_buf(output, 1, (uint8_t *)&avi_if, 4 + avi_if.len,
 932                                 SDVO_HBUF_TX_VSYNC);
 933 }
 934
 935 static void intel_sdvo_set_tv_format(struct intel_output *output)
 936 {
 937         struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
 938         struct intel_sdvo_tv_format *format, unset;
 939         u8 status;
 940
 941         format = &sdvo_priv->tv_format;
 942         memset(&unset, 0, sizeof(unset));
 943         if (memcmp(format, &unset, sizeof(*format))) {
 944                 DRM_DEBUG_KMS("%s: Choosing default TV format of NTSC-M\n",
 945                                 SDVO_NAME(sdvo_priv));
 946                 format->ntsc_m = 1;
 947                 intel_sdvo_write_cmd(output, SDVO_CMD_SET_TV_FORMAT, format,
 948                                 sizeof(*format));
 949                 status = intel_sdvo_read_response(output, NULL, 0);
 950                 if (status != SDVO_CMD_STATUS_SUCCESS)
 951                         DRM_DEBUG_KMS("%s: Failed to set TV format\n",
 952                                         SDVO_NAME(sdvo_priv));
 953         }
 954 }
 955
 956 static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
 957                                   struct drm_display_mode *mode,
 958                                   struct drm_display_mode *adjusted_mode)
 959 {
 960         struct intel_output *output = enc_to_intel_output(encoder);
 961         struct intel_sdvo_priv *dev_priv = output->dev_priv;
 962
 963         if (dev_priv->is_tv) {
 964                 struct intel_sdvo_dtd output_dtd;
 965                 bool success;
 966
 967                 /* We need to construct preferred input timings based on our
 968                  * output timings.  To do that, we have to set the output
 969                  * timings, even though this isn't really the right place in
 970                  * the sequence to do it. Oh well.
 971                  */
 972
 973
 974                 /* Set output timings */
 975                 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
 976                 intel_sdvo_set_target_output(output,
 977                                              dev_priv->controlled_output);
 978                 intel_sdvo_set_output_timing(output, &output_dtd);
 979
 980                 /* Set the input timing to the screen. Assume always input 0. */
 981                 intel_sdvo_set_target_input(output, true, false);
 982
 983
 984                 success = intel_sdvo_create_preferred_input_timing(output,
 985                                                                    mode->clock / 10,
 986                                                                    mode->hdisplay,
 987                                                                    mode->vdisplay);
 988                 if (success) {
 989                         struct intel_sdvo_dtd input_dtd;
 990
 991                         intel_sdvo_get_preferred_input_timing(output,
 992                                                              &input_dtd);
 993                         intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
 994                         dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags;
 995
 996                         drm_mode_set_crtcinfo(adjusted_mode, 0);
 997
 998                         mode->clock = adjusted_mode->clock;
 999
1000                         adjusted_mode->clock *=
1001                                 intel_sdvo_get_pixel_multiplier(mode);
1002                 } else {
1003                         return false;
1004                 }
1005         } else if (dev_priv->is_lvds) {
1006                 struct intel_sdvo_dtd output_dtd;
1007                 bool success;
1008
1009                 drm_mode_set_crtcinfo(dev_priv->sdvo_lvds_fixed_mode, 0);
1010                 /* Set output timings */
1011                 intel_sdvo_get_dtd_from_mode(&output_dtd,
1012                                 dev_priv->sdvo_lvds_fixed_mode);
1013
1014                 intel_sdvo_set_target_output(output,
1015                                              dev_priv->controlled_output);
1016                 intel_sdvo_set_output_timing(output, &output_dtd);
1017
1018                 /* Set the input timing to the screen. Assume always input 0. */
1019                 intel_sdvo_set_target_input(output, true, false);
1020
1021
1022                 success = intel_sdvo_create_preferred_input_timing(
1023                                 output,
1024                                 mode->clock / 10,
1025                                 mode->hdisplay,
1026                                 mode->vdisplay);
1027
1028                 if (success) {
1029                         struct intel_sdvo_dtd input_dtd;
1030
1031                         intel_sdvo_get_preferred_input_timing(output,
1032                                                              &input_dtd);
1033                         intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
1034                         dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags;
1035
1036                         drm_mode_set_crtcinfo(adjusted_mode, 0);
1037
1038                         mode->clock = adjusted_mode->clock;
1039
1040                         adjusted_mode->clock *=
1041                                 intel_sdvo_get_pixel_multiplier(mode);
1042                 } else {
1043                         return false;
1044                 }
1045
1046         } else {
1047                 /* Make the CRTC code factor in the SDVO pixel multiplier.  The
1048                  * SDVO device will be told of the multiplier during mode_set.
1049                  */
1050                 adjusted_mode->clock *= intel_sdvo_get_pixel_multiplier(mode);
1051         }
1052         return true;
1053 }
1054
1055 static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1056                                 struct drm_display_mode *mode,
1057                                 struct drm_display_mode *adjusted_mode)
1058 {
1059         struct drm_device *dev = encoder->dev;
1060         struct drm_i915_private *dev_priv = dev->dev_private;
1061         struct drm_crtc *crtc = encoder->crtc;
1062         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1063         struct intel_output *output = enc_to_intel_output(encoder);
1064         struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1065         u32 sdvox = 0;
1066         int sdvo_pixel_multiply;
1067         struct intel_sdvo_in_out_map in_out;
1068         struct intel_sdvo_dtd input_dtd;
1069         u8 status;
1070
1071         if (!mode)
1072                 return;
1073
1074         /* First, set the input mapping for the first input to our controlled
1075          * output. This is only correct if we're a single-input device, in
1076          * which case the first input is the output from the appropriate SDVO
1077          * channel on the motherboard.  In a two-input device, the first input
1078          * will be SDVOB and the second SDVOC.
1079          */
1080         in_out.in0 = sdvo_priv->controlled_output;
1081         in_out.in1 = 0;
1082
1083         intel_sdvo_write_cmd(output, SDVO_CMD_SET_IN_OUT_MAP,
1084                              &in_out, sizeof(in_out));
1085         status = intel_sdvo_read_response(output, NULL, 0);
1086
1087         if (sdvo_priv->is_hdmi) {
1088                 intel_sdvo_set_avi_infoframe(output, mode);
1089                 sdvox |= SDVO_AUDIO_ENABLE;
1090         }
1091
1092         /* We have tried to get input timing in mode_fixup, and filled into
1093            adjusted_mode */
1094         if (sdvo_priv->is_tv || sdvo_priv->is_lvds) {
1095                 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
1096                 input_dtd.part2.sdvo_flags = sdvo_priv->sdvo_flags;
1097         } else
1098                 intel_sdvo_get_dtd_from_mode(&input_dtd, mode);
1099
1100         /* If it's a TV, we already set the output timing in mode_fixup.
1101          * Otherwise, the output timing is equal to the input timing.
1102          */
1103         if (!sdvo_priv->is_tv && !sdvo_priv->is_lvds) {
1104                 /* Set the output timing to the screen */
1105                 intel_sdvo_set_target_output(output,
1106                                              sdvo_priv->controlled_output);
1107                 intel_sdvo_set_output_timing(output, &input_dtd);
1108         }
1109
1110         /* Set the input timing to the screen. Assume always input 0. */
1111         intel_sdvo_set_target_input(output, true, false);
1112
1113         if (sdvo_priv->is_tv)
1114                 intel_sdvo_set_tv_format(output);
1115
1116         /* We would like to use intel_sdvo_create_preferred_input_timing() to
1117          * provide the device with a timing it can support, if it supports that
1118          * feature.  However, presumably we would need to adjust the CRTC to
1119          * output the preferred timing, and we don't support that currently.
1120          */
1121 #if 0
1122         success = intel_sdvo_create_preferred_input_timing(output, clock,
1123                                                            width, height);
1124         if (success) {
1125                 struct intel_sdvo_dtd *input_dtd;
1126
1127                 intel_sdvo_get_preferred_input_timing(output, &input_dtd);
1128                 intel_sdvo_set_input_timing(output, &input_dtd);
1129         }
1130 #else
1131         intel_sdvo_set_input_timing(output, &input_dtd);
1132 #endif
1133
1134         switch (intel_sdvo_get_pixel_multiplier(mode)) {
1135         case 1:
1136                 intel_sdvo_set_clock_rate_mult(output,
1137                                                SDVO_CLOCK_RATE_MULT_1X);
1138                 break;
1139         case 2:
1140                 intel_sdvo_set_clock_rate_mult(output,
1141                                                SDVO_CLOCK_RATE_MULT_2X);
1142                 break;
1143         case 4:
1144                 intel_sdvo_set_clock_rate_mult(output,
1145                                                SDVO_CLOCK_RATE_MULT_4X);
1146                 break;
1147         }
1148
1149         /* Set the SDVO control regs. */
1150         if (IS_I965G(dev)) {
1151                 sdvox |= SDVO_BORDER_ENABLE |
1152                         SDVO_VSYNC_ACTIVE_HIGH |
1153                         SDVO_HSYNC_ACTIVE_HIGH;
1154         } else {
1155                 sdvox |= I915_READ(sdvo_priv->output_device);
1156                 switch (sdvo_priv->output_device) {
1157                 case SDVOB:
1158                         sdvox &= SDVOB_PRESERVE_MASK;
1159                         break;
1160                 case SDVOC:
1161                         sdvox &= SDVOC_PRESERVE_MASK;
1162                         break;
1163                 }
1164                 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1165         }
1166         if (intel_crtc->pipe == 1)
1167                 sdvox |= SDVO_PIPE_B_SELECT;
1168
1169         sdvo_pixel_multiply = intel_sdvo_get_pixel_multiplier(mode);
1170         if (IS_I965G(dev)) {
1171                 /* done in crtc_mode_set as the dpll_md reg must be written early */
1172         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1173                 /* done in crtc_mode_set as it lives inside the dpll register */
1174         } else {
1175                 sdvox |= (sdvo_pixel_multiply - 1) << SDVO_PORT_MULTIPLY_SHIFT;
1176         }
1177
1178         if (sdvo_priv->sdvo_flags & SDVO_NEED_TO_STALL)
1179                 sdvox |= SDVO_STALL_SELECT;
1180         intel_sdvo_write_sdvox(output, sdvox);
1181 }
1182
1183 static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1184 {
1185         struct drm_device *dev = encoder->dev;
1186         struct drm_i915_private *dev_priv = dev->dev_private;
1187         struct intel_output *intel_output = enc_to_intel_output(encoder);
1188         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1189         u32 temp;
1190
1191         if (mode != DRM_MODE_DPMS_ON) {
1192                 intel_sdvo_set_active_outputs(intel_output, 0);
1193                 if (0)
1194                         intel_sdvo_set_encoder_power_state(intel_output, mode);
1195
1196                 if (mode == DRM_MODE_DPMS_OFF) {
1197                         temp = I915_READ(sdvo_priv->output_device);
1198                         if ((temp & SDVO_ENABLE) != 0) {
1199                                 intel_sdvo_write_sdvox(intel_output, temp & ~SDVO_ENABLE);
1200                         }
1201                 }
1202         } else {
1203                 bool input1, input2;
1204                 int i;
1205                 u8 status;
1206
1207                 temp = I915_READ(sdvo_priv->output_device);
1208                 if ((temp & SDVO_ENABLE) == 0)
1209                         intel_sdvo_write_sdvox(intel_output, temp | SDVO_ENABLE);
1210                 for (i = 0; i < 2; i++)
1211                   intel_wait_for_vblank(dev);
1212
1213                 status = intel_sdvo_get_trained_inputs(intel_output, &input1,
1214                                                        &input2);
1215
1216
1217                 /* Warn if the device reported failure to sync.
1218                  * A lot of SDVO devices fail to notify of sync, but it's
1219                  * a given it the status is a success, we succeeded.
1220                  */
1221                 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
1222                         DRM_DEBUG_KMS("First %s output reported failure to "
1223                                         "sync\n", SDVO_NAME(sdvo_priv));
1224                 }
1225
1226                 if (0)
1227                         intel_sdvo_set_encoder_power_state(intel_output, mode);
1228                 intel_sdvo_set_active_outputs(intel_output, sdvo_priv->controlled_output);
1229         }
1230         return;
1231 }
1232
1233 static void intel_sdvo_save(struct drm_connector *connector)
1234 {
1235         struct drm_device *dev = connector->dev;
1236         struct drm_i915_private *dev_priv = dev->dev_private;
1237         struct intel_output *intel_output = to_intel_output(connector);
1238         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1239         int o;
1240
1241         sdvo_priv->save_sdvo_mult = intel_sdvo_get_clock_rate_mult(intel_output);
1242         intel_sdvo_get_active_outputs(intel_output, &sdvo_priv->save_active_outputs);
1243
1244         if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
1245                 intel_sdvo_set_target_input(intel_output, true, false);
1246                 intel_sdvo_get_input_timing(intel_output,
1247                                             &sdvo_priv->save_input_dtd_1);
1248         }
1249
1250         if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
1251                 intel_sdvo_set_target_input(intel_output, false, true);
1252                 intel_sdvo_get_input_timing(intel_output,
1253                                             &sdvo_priv->save_input_dtd_2);
1254         }
1255
1256         for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++)
1257         {
1258                 u16  this_output = (1 << o);
1259                 if (sdvo_priv->caps.output_flags & this_output)
1260                 {
1261                         intel_sdvo_set_target_output(intel_output, this_output);
1262                         intel_sdvo_get_output_timing(intel_output,
1263                                                      &sdvo_priv->save_output_dtd[o]);
1264                 }
1265         }
1266         if (sdvo_priv->is_tv) {
1267                 /* XXX: Save TV format/enhancements. */
1268         }
1269
1270         sdvo_priv->save_SDVOX = I915_READ(sdvo_priv->output_device);
1271 }
1272
1273 static void intel_sdvo_restore(struct drm_connector *connector)
1274 {
1275         struct drm_device *dev = connector->dev;
1276         struct intel_output *intel_output = to_intel_output(connector);
1277         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1278         int o;
1279         int i;
1280         bool input1, input2;
1281         u8 status;
1282
1283         intel_sdvo_set_active_outputs(intel_output, 0);
1284
1285         for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++)
1286         {
1287                 u16  this_output = (1 << o);
1288                 if (sdvo_priv->caps.output_flags & this_output) {
1289                         intel_sdvo_set_target_output(intel_output, this_output);
1290                         intel_sdvo_set_output_timing(intel_output, &sdvo_priv->save_output_dtd[o]);
1291                 }
1292         }
1293
1294         if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
1295                 intel_sdvo_set_target_input(intel_output, true, false);
1296                 intel_sdvo_set_input_timing(intel_output, &sdvo_priv->save_input_dtd_1);
1297         }
1298
1299         if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
1300                 intel_sdvo_set_target_input(intel_output, false, true);
1301                 intel_sdvo_set_input_timing(intel_output, &sdvo_priv->save_input_dtd_2);
1302         }
1303
1304         intel_sdvo_set_clock_rate_mult(intel_output, sdvo_priv->save_sdvo_mult);
1305
1306         if (sdvo_priv->is_tv) {
1307                 /* XXX: Restore TV format/enhancements. */
1308         }
1309
1310         intel_sdvo_write_sdvox(intel_output, sdvo_priv->save_SDVOX);
1311
1312         if (sdvo_priv->save_SDVOX & SDVO_ENABLE)
1313         {
1314                 for (i = 0; i < 2; i++)
1315                         intel_wait_for_vblank(dev);
1316                 status = intel_sdvo_get_trained_inputs(intel_output, &input1, &input2);
1317                 if (status == SDVO_CMD_STATUS_SUCCESS && !input1)
1318                         DRM_DEBUG_KMS("First %s output reported failure to "
1319                                         "sync\n", SDVO_NAME(sdvo_priv));
1320         }
1321
1322         intel_sdvo_set_active_outputs(intel_output, sdvo_priv->save_active_outputs);
1323 }
1324
1325 static int intel_sdvo_mode_valid(struct drm_connector *connector,
1326                                  struct drm_display_mode *mode)
1327 {
1328         struct intel_output *intel_output = to_intel_output(connector);
1329         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1330
1331         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1332                 return MODE_NO_DBLESCAN;
1333
1334         if (sdvo_priv->pixel_clock_min > mode->clock)
1335                 return MODE_CLOCK_LOW;
1336
1337         if (sdvo_priv->pixel_clock_max < mode->clock)
1338                 return MODE_CLOCK_HIGH;
1339
1340         if (sdvo_priv->is_lvds == true) {
1341                 if (sdvo_priv->sdvo_lvds_fixed_mode == NULL)
1342                         return MODE_PANEL;
1343
1344                 if (mode->hdisplay > sdvo_priv->sdvo_lvds_fixed_mode->hdisplay)
1345                         return MODE_PANEL;
1346
1347                 if (mode->vdisplay > sdvo_priv->sdvo_lvds_fixed_mode->vdisplay)
1348                         return MODE_PANEL;
1349         }
1350
1351         return MODE_OK;
1352 }
1353
1354 static bool intel_sdvo_get_capabilities(struct intel_output *intel_output, struct intel_sdvo_caps *caps)
1355 {
1356         u8 status;
1357
1358         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_DEVICE_CAPS, NULL, 0);
1359         status = intel_sdvo_read_response(intel_output, caps, sizeof(*caps));
1360         if (status != SDVO_CMD_STATUS_SUCCESS)
1361                 return false;
1362
1363         return true;
1364 }
1365
1366 struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB)
1367 {
1368         struct drm_connector *connector = NULL;
1369         struct intel_output *iout = NULL;
1370         struct intel_sdvo_priv *sdvo;
1371
1372         /* find the sdvo connector */
1373         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1374                 iout = to_intel_output(connector);
1375
1376                 if (iout->type != INTEL_OUTPUT_SDVO)
1377                         continue;
1378
1379                 sdvo = iout->dev_priv;
1380
1381                 if (sdvo->output_device == SDVOB && sdvoB)
1382                         return connector;
1383
1384                 if (sdvo->output_device == SDVOC && !sdvoB)
1385                         return connector;
1386
1387         }
1388
1389         return NULL;
1390 }
1391
1392 int intel_sdvo_supports_hotplug(struct drm_connector *connector)
1393 {
1394         u8 response[2];
1395         u8 status;
1396         struct intel_output *intel_output;
1397         DRM_DEBUG_KMS("\n");
1398
1399         if (!connector)
1400                 return 0;
1401
1402         intel_output = to_intel_output(connector);
1403
1404         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1405         status = intel_sdvo_read_response(intel_output, &response, 2);
1406
1407         if (response[0] !=0)
1408                 return 1;
1409
1410         return 0;
1411 }
1412
1413 void intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
1414 {
1415         u8 response[2];
1416         u8 status;
1417         struct intel_output *intel_output = to_intel_output(connector);
1418
1419         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1420         intel_sdvo_read_response(intel_output, &response, 2);
1421
1422         if (on) {
1423                 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1424                 status = intel_sdvo_read_response(intel_output, &response, 2);
1425
1426                 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
1427         } else {
1428                 response[0] = 0;
1429                 response[1] = 0;
1430                 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
1431         }
1432
1433         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1434         intel_sdvo_read_response(intel_output, &response, 2);
1435 }
1436
1437 static void
1438 intel_sdvo_hdmi_sink_detect(struct drm_connector *connector)
1439 {
1440         struct intel_output *intel_output = to_intel_output(connector);
1441         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1442         struct edid *edid = NULL;
1443
1444         edid = drm_get_edid(&intel_output->base,
1445                             intel_output->ddc_bus);
1446         if (edid != NULL) {
1447                 sdvo_priv->is_hdmi = drm_detect_hdmi_monitor(edid);
1448                 kfree(edid);
1449                 intel_output->base.display_info.raw_edid = NULL;
1450         }
1451 }
1452
1453 static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector)
1454 {
1455         u8 response[2];
1456         u8 status;
1457         struct intel_output *intel_output = to_intel_output(connector);
1458
1459         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0);
1460         status = intel_sdvo_read_response(intel_output, &response, 2);
1461
1462         DRM_DEBUG_KMS("SDVO response %d %d\n", response[0], response[1]);
1463
1464         if (status != SDVO_CMD_STATUS_SUCCESS)
1465                 return connector_status_unknown;
1466
1467         if ((response[0] != 0) || (response[1] != 0)) {
1468                 intel_sdvo_hdmi_sink_detect(connector);
1469                 return connector_status_connected;
1470         } else
1471                 return connector_status_disconnected;
1472 }
1473
1474 static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
1475 {
1476         struct intel_output *intel_output = to_intel_output(connector);
1477
1478         /* set the bus switch and get the modes */
1479         intel_ddc_get_modes(intel_output);
1480
1481 #if 0
1482         struct drm_device *dev = encoder->dev;
1483         struct drm_i915_private *dev_priv = dev->dev_private;
1484         /* Mac mini hack.  On this device, I get DDC through the analog, which
1485          * load-detects as disconnected.  I fail to DDC through the SDVO DDC,
1486          * but it does load-detect as connected.  So, just steal the DDC bits
1487          * from analog when we fail at finding it the right way.
1488          */
1489         crt = xf86_config->output[0];
1490         intel_output = crt->driver_private;
1491         if (intel_output->type == I830_OUTPUT_ANALOG &&
1492             crt->funcs->detect(crt) == XF86OutputStatusDisconnected) {
1493                 I830I2CInit(pScrn, &intel_output->pDDCBus, GPIOA, "CRTDDC_A");
1494                 edid_mon = xf86OutputGetEDID(crt, intel_output->pDDCBus);
1495                 xf86DestroyI2CBusRec(intel_output->pDDCBus, true, true);
1496         }
1497         if (edid_mon) {
1498                 xf86OutputSetEDID(output, edid_mon);
1499                 modes = xf86OutputGetEDIDModes(output);
1500         }
1501 #endif
1502 }
1503
1504 /**
1505  * This function checks the current TV format, and chooses a default if
1506  * it hasn't been set.
1507  */
1508 static void
1509 intel_sdvo_check_tv_format(struct intel_output *output)
1510 {
1511         struct intel_sdvo_priv *dev_priv = output->dev_priv;
1512         struct intel_sdvo_tv_format format;
1513         uint8_t status;
1514
1515         intel_sdvo_write_cmd(output, SDVO_CMD_GET_TV_FORMAT, NULL, 0);
1516         status = intel_sdvo_read_response(output, &format, sizeof(format));
1517         if (status != SDVO_CMD_STATUS_SUCCESS)
1518                 return;
1519
1520         memcpy(&dev_priv->tv_format, &format, sizeof(format));
1521 }
1522
1523 /*
1524  * Set of SDVO TV modes.
1525  * Note!  This is in reply order (see loop in get_tv_modes).
1526  * XXX: all 60Hz refresh?
1527  */
1528 struct drm_display_mode sdvo_tv_modes[] = {
1529         { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1530                    416, 0, 200, 201, 232, 233, 0,
1531                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1532         { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1533                    416, 0, 240, 241, 272, 273, 0,
1534                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1535         { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1536                    496, 0, 300, 301, 332, 333, 0,
1537                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1538         { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1539                    736, 0, 350, 351, 382, 383, 0,
1540                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1541         { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1542                    736, 0, 400, 401, 432, 433, 0,
1543                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1544         { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1545                    736, 0, 480, 481, 512, 513, 0,
1546                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1547         { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1548                    800, 0, 480, 481, 512, 513, 0,
1549                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1550         { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1551                    800, 0, 576, 577, 608, 609, 0,
1552                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1553         { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1554                    816, 0, 350, 351, 382, 383, 0,
1555                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1556         { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1557                    816, 0, 400, 401, 432, 433, 0,
1558                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1559         { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1560                    816, 0, 480, 481, 512, 513, 0,
1561                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1562         { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1563                    816, 0, 540, 541, 572, 573, 0,
1564                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1565         { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1566                    816, 0, 576, 577, 608, 609, 0,
1567                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1568         { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1569                    864, 0, 576, 577, 608, 609, 0,
1570                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1571         { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1572                    896, 0, 600, 601, 632, 633, 0,
1573                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1574         { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1575                    928, 0, 624, 625, 656, 657, 0,
1576                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1577         { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1578                    1016, 0, 766, 767, 798, 799, 0,
1579                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1580         { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1581                    1120, 0, 768, 769, 800, 801, 0,
1582                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1583         { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1584                    1376, 0, 1024, 1025, 1056, 1057, 0,
1585                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1586 };
1587
1588 static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1589 {
1590         struct intel_output *output = to_intel_output(connector);
1591         struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1592         struct intel_sdvo_sdtv_resolution_request tv_res;
1593         uint32_t reply = 0;
1594         uint8_t status;
1595         int i = 0;
1596
1597         intel_sdvo_check_tv_format(output);
1598
1599         /* Read the list of supported input resolutions for the selected TV
1600          * format.
1601          */
1602         memset(&tv_res, 0, sizeof(tv_res));
1603         memcpy(&tv_res, &sdvo_priv->tv_format, sizeof(tv_res));
1604         intel_sdvo_write_cmd(output, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
1605                              &tv_res, sizeof(tv_res));
1606         status = intel_sdvo_read_response(output, &reply, 3);
1607         if (status != SDVO_CMD_STATUS_SUCCESS)
1608                 return;
1609
1610         for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
1611                 if (reply & (1 << i)) {
1612                         struct drm_display_mode *nmode;
1613                         nmode = drm_mode_duplicate(connector->dev,
1614                                         &sdvo_tv_modes[i]);
1615                         if (nmode)
1616                                 drm_mode_probed_add(connector, nmode);
1617                 }
1618 }
1619
1620 static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1621 {
1622         struct intel_output *intel_output = to_intel_output(connector);
1623         struct drm_i915_private *dev_priv = connector->dev->dev_private;
1624         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1625         struct drm_display_mode *newmode;
1626
1627         /*
1628          * Attempt to get the mode list from DDC.
1629          * Assume that the preferred modes are
1630          * arranged in priority order.
1631          */
1632         intel_ddc_get_modes(intel_output);
1633         if (list_empty(&connector->probed_modes) == false)
1634                 goto end;
1635
1636         /* Fetch modes from VBT */
1637         if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
1638                 newmode = drm_mode_duplicate(connector->dev,
1639                                              dev_priv->sdvo_lvds_vbt_mode);
1640                 if (newmode != NULL) {
1641                         /* Guarantee the mode is preferred */
1642                         newmode->type = (DRM_MODE_TYPE_PREFERRED |
1643                                          DRM_MODE_TYPE_DRIVER);
1644                         drm_mode_probed_add(connector, newmode);
1645                 }
1646         }
1647
1648 end:
1649         list_for_each_entry(newmode, &connector->probed_modes, head) {
1650                 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1651                         sdvo_priv->sdvo_lvds_fixed_mode =
1652                                 drm_mode_duplicate(connector->dev, newmode);
1653                         break;
1654                 }
1655         }
1656
1657 }
1658
1659 static int intel_sdvo_get_modes(struct drm_connector *connector)
1660 {
1661         struct intel_output *output = to_intel_output(connector);
1662         struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1663
1664         if (sdvo_priv->is_tv)
1665                 intel_sdvo_get_tv_modes(connector);
1666         else if (sdvo_priv->is_lvds == true)
1667                 intel_sdvo_get_lvds_modes(connector);
1668         else
1669                 intel_sdvo_get_ddc_modes(connector);
1670
1671         if (list_empty(&connector->probed_modes))
1672                 return 0;
1673         return 1;
1674 }
1675
1676 static void intel_sdvo_destroy(struct drm_connector *connector)
1677 {
1678         struct intel_output *intel_output = to_intel_output(connector);
1679         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1680
1681         if (intel_output->i2c_bus)
1682                 intel_i2c_destroy(intel_output->i2c_bus);
1683         if (intel_output->ddc_bus)
1684                 intel_i2c_destroy(intel_output->ddc_bus);
1685
1686         if (sdvo_priv->sdvo_lvds_fixed_mode != NULL)
1687                 drm_mode_destroy(connector->dev,
1688                                  sdvo_priv->sdvo_lvds_fixed_mode);
1689
1690         drm_sysfs_connector_remove(connector);
1691         drm_connector_cleanup(connector);
1692
1693         kfree(intel_output);
1694 }
1695
1696 static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
1697         .dpms = intel_sdvo_dpms,
1698         .mode_fixup = intel_sdvo_mode_fixup,
1699         .prepare = intel_encoder_prepare,
1700         .mode_set = intel_sdvo_mode_set,
1701         .commit = intel_encoder_commit,
1702 };
1703
1704 static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
1705         .dpms = drm_helper_connector_dpms,
1706         .save = intel_sdvo_save,
1707         .restore = intel_sdvo_restore,
1708         .detect = intel_sdvo_detect,
1709         .fill_modes = drm_helper_probe_single_connector_modes,
1710         .destroy = intel_sdvo_destroy,
1711 };
1712
1713 static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
1714         .get_modes = intel_sdvo_get_modes,
1715         .mode_valid = intel_sdvo_mode_valid,
1716         .best_encoder = intel_best_encoder,
1717 };
1718
1719 static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
1720 {
1721         drm_encoder_cleanup(encoder);
1722 }
1723
1724 static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
1725         .destroy = intel_sdvo_enc_destroy,
1726 };
1727
1728
1729 /**
1730  * Choose the appropriate DDC bus for control bus switch command for this
1731  * SDVO output based on the controlled output.
1732  *
1733  * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
1734  * outputs, then LVDS outputs.
1735  */
1736 static void
1737 intel_sdvo_select_ddc_bus(struct intel_sdvo_priv *dev_priv)
1738 {
1739         uint16_t mask = 0;
1740         unsigned int num_bits;
1741
1742         /* Make a mask of outputs less than or equal to our own priority in the
1743          * list.
1744          */
1745         switch (dev_priv->controlled_output) {
1746         case SDVO_OUTPUT_LVDS1:
1747                 mask |= SDVO_OUTPUT_LVDS1;
1748         case SDVO_OUTPUT_LVDS0:
1749                 mask |= SDVO_OUTPUT_LVDS0;
1750         case SDVO_OUTPUT_TMDS1:
1751                 mask |= SDVO_OUTPUT_TMDS1;
1752         case SDVO_OUTPUT_TMDS0:
1753                 mask |= SDVO_OUTPUT_TMDS0;
1754         case SDVO_OUTPUT_RGB1:
1755                 mask |= SDVO_OUTPUT_RGB1;
1756         case SDVO_OUTPUT_RGB0:
1757                 mask |= SDVO_OUTPUT_RGB0;
1758                 break;
1759         }
1760
1761         /* Count bits to find what number we are in the priority list. */
1762         mask &= dev_priv->caps.output_flags;
1763         num_bits = hweight16(mask);
1764         if (num_bits > 3) {
1765                 /* if more than 3 outputs, default to DDC bus 3 for now */
1766                 num_bits = 3;
1767         }
1768
1769         /* Corresponds to SDVO_CONTROL_BUS_DDCx */
1770         dev_priv->ddc_bus = 1 << num_bits;
1771 }
1772
1773 static bool
1774 intel_sdvo_get_digital_encoding_mode(struct intel_output *output)
1775 {
1776         struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1777         uint8_t status;
1778
1779         intel_sdvo_set_target_output(output, sdvo_priv->controlled_output);
1780
1781         intel_sdvo_write_cmd(output, SDVO_CMD_GET_ENCODE, NULL, 0);
1782         status = intel_sdvo_read_response(output, &sdvo_priv->is_hdmi, 1);
1783         if (status != SDVO_CMD_STATUS_SUCCESS)
1784                 return false;
1785         return true;
1786 }
1787
1788 static struct intel_output *
1789 intel_sdvo_chan_to_intel_output(struct intel_i2c_chan *chan)
1790 {
1791         struct drm_device *dev = chan->drm_dev;
1792         struct drm_connector *connector;
1793         struct intel_output *intel_output = NULL;
1794
1795         list_for_each_entry(connector,
1796                         &dev->mode_config.connector_list, head) {
1797                 if (to_intel_output(connector)->ddc_bus == &chan->adapter) {
1798                         intel_output = to_intel_output(connector);
1799                         break;
1800                 }
1801         }
1802         return intel_output;
1803 }
1804
1805 static int intel_sdvo_master_xfer(struct i2c_adapter *i2c_adap,
1806                                   struct i2c_msg msgs[], int num)
1807 {
1808         struct intel_output *intel_output;
1809         struct intel_sdvo_priv *sdvo_priv;
1810         struct i2c_algo_bit_data *algo_data;
1811         const struct i2c_algorithm *algo;
1812
1813         algo_data = (struct i2c_algo_bit_data *)i2c_adap->algo_data;
1814         intel_output =
1815                 intel_sdvo_chan_to_intel_output(
1816                                 (struct intel_i2c_chan *)(algo_data->data));
1817         if (intel_output == NULL)
1818                 return -EINVAL;
1819
1820         sdvo_priv = intel_output->dev_priv;
1821         algo = intel_output->i2c_bus->algo;
1822
1823         intel_sdvo_set_control_bus_switch(intel_output, sdvo_priv->ddc_bus);
1824         return algo->master_xfer(i2c_adap, msgs, num);
1825 }
1826
1827 static struct i2c_algorithm intel_sdvo_i2c_bit_algo = {
1828         .master_xfer    = intel_sdvo_master_xfer,
1829 };
1830
1831 static u8
1832 intel_sdvo_get_slave_addr(struct drm_device *dev, int output_device)
1833 {
1834         struct drm_i915_private *dev_priv = dev->dev_private;
1835         struct sdvo_device_mapping *my_mapping, *other_mapping;
1836
1837         if (output_device == SDVOB) {
1838                 my_mapping = &dev_priv->sdvo_mappings[0];
1839                 other_mapping = &dev_priv->sdvo_mappings[1];
1840         } else {
1841                 my_mapping = &dev_priv->sdvo_mappings[1];
1842                 other_mapping = &dev_priv->sdvo_mappings[0];
1843         }
1844
1845         /* If the BIOS described our SDVO device, take advantage of it. */
1846         if (my_mapping->slave_addr)
1847                 return my_mapping->slave_addr;
1848
1849         /* If the BIOS only described a different SDVO device, use the
1850          * address that it isn't using.
1851          */
1852         if (other_mapping->slave_addr) {
1853                 if (other_mapping->slave_addr == 0x70)
1854                         return 0x72;
1855                 else
1856                         return 0x70;
1857         }
1858
1859         /* No SDVO device info is found for another DVO port,
1860          * so use mapping assumption we had before BIOS parsing.
1861          */
1862         if (output_device == SDVOB)
1863                 return 0x70;
1864         else
1865                 return 0x72;
1866 }
1867
1868 bool intel_sdvo_init(struct drm_device *dev, int output_device)
1869 {
1870         struct drm_connector *connector;
1871         struct intel_output *intel_output;
1872         struct intel_sdvo_priv *sdvo_priv;
1873
1874         int connector_type;
1875         u8 ch[0x40];
1876         int i;
1877         int encoder_type;
1878
1879         intel_output = kcalloc(sizeof(struct intel_output)+sizeof(struct intel_sdvo_priv), 1, GFP_KERNEL);
1880         if (!intel_output) {
1881                 return false;
1882         }
1883
1884         sdvo_priv = (struct intel_sdvo_priv *)(intel_output + 1);
1885         sdvo_priv->output_device = output_device;
1886
1887         intel_output->dev_priv = sdvo_priv;
1888         intel_output->type = INTEL_OUTPUT_SDVO;
1889
1890         /* setup the DDC bus. */
1891         if (output_device == SDVOB)
1892                 intel_output->i2c_bus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOB");
1893         else
1894                 intel_output->i2c_bus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOC");
1895
1896         if (!intel_output->i2c_bus)
1897                 goto err_inteloutput;
1898
1899         sdvo_priv->slave_addr = intel_sdvo_get_slave_addr(dev, output_device);
1900
1901         /* Save the bit-banging i2c functionality for use by the DDC wrapper */
1902         intel_sdvo_i2c_bit_algo.functionality = intel_output->i2c_bus->algo->functionality;
1903
1904         /* Read the regs to test if we can talk to the device */
1905         for (i = 0; i < 0x40; i++) {
1906                 if (!intel_sdvo_read_byte(intel_output, i, &ch[i])) {
1907                         DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n",
1908                                         output_device == SDVOB ? 'B' : 'C');
1909                         goto err_i2c;
1910                 }
1911         }
1912
1913         /* setup the DDC bus. */
1914         if (output_device == SDVOB)
1915                 intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOB DDC BUS");
1916         else
1917                 intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOC DDC BUS");
1918
1919         if (intel_output->ddc_bus == NULL)
1920                 goto err_i2c;
1921
1922         /* Wrap with our custom algo which switches to DDC mode */
1923         intel_output->ddc_bus->algo = &intel_sdvo_i2c_bit_algo;
1924
1925         /* In defaut case sdvo lvds is false */
1926         sdvo_priv->is_lvds = false;
1927         intel_sdvo_get_capabilities(intel_output, &sdvo_priv->caps);
1928
1929         if (sdvo_priv->caps.output_flags &
1930             (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) {
1931                 if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_TMDS0)
1932                         sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS0;
1933                 else
1934                         sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS1;
1935
1936                 encoder_type = DRM_MODE_ENCODER_TMDS;
1937                 connector_type = DRM_MODE_CONNECTOR_DVID;
1938
1939                 if (intel_sdvo_get_supp_encode(intel_output,
1940                                                &sdvo_priv->encode) &&
1941                     intel_sdvo_get_digital_encoding_mode(intel_output) &&
1942                     sdvo_priv->is_hdmi) {
1943                         /* enable hdmi encoding mode if supported */
1944                         intel_sdvo_set_encode(intel_output, SDVO_ENCODE_HDMI);
1945                         intel_sdvo_set_colorimetry(intel_output,
1946                                                    SDVO_COLORIMETRY_RGB256);
1947                         connector_type = DRM_MODE_CONNECTOR_HDMIA;
1948                 }
1949         }
1950         else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_SVID0)
1951         {
1952                 sdvo_priv->controlled_output = SDVO_OUTPUT_SVID0;
1953                 encoder_type = DRM_MODE_ENCODER_TVDAC;
1954                 connector_type = DRM_MODE_CONNECTOR_SVIDEO;
1955                 sdvo_priv->is_tv = true;
1956                 intel_output->needs_tv_clock = true;
1957         }
1958         else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_RGB0)
1959         {
1960                 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB0;
1961                 encoder_type = DRM_MODE_ENCODER_DAC;
1962                 connector_type = DRM_MODE_CONNECTOR_VGA;
1963         }
1964         else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_RGB1)
1965         {
1966                 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB1;
1967                 encoder_type = DRM_MODE_ENCODER_DAC;
1968                 connector_type = DRM_MODE_CONNECTOR_VGA;
1969         }
1970         else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_LVDS0)
1971         {
1972                 sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS0;
1973                 encoder_type = DRM_MODE_ENCODER_LVDS;
1974                 connector_type = DRM_MODE_CONNECTOR_LVDS;
1975                 sdvo_priv->is_lvds = true;
1976         }
1977         else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_LVDS1)
1978         {
1979                 sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS1;
1980                 encoder_type = DRM_MODE_ENCODER_LVDS;
1981                 connector_type = DRM_MODE_CONNECTOR_LVDS;
1982                 sdvo_priv->is_lvds = true;
1983         }
1984         else
1985         {
1986                 unsigned char bytes[2];
1987
1988                 sdvo_priv->controlled_output = 0;
1989                 memcpy (bytes, &sdvo_priv->caps.output_flags, 2);
1990                 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
1991                                   SDVO_NAME(sdvo_priv),
1992                                   bytes[0], bytes[1]);
1993                 encoder_type = DRM_MODE_ENCODER_NONE;
1994                 connector_type = DRM_MODE_CONNECTOR_Unknown;
1995                 goto err_i2c;
1996         }
1997
1998         connector = &intel_output->base;
1999         drm_connector_init(dev, connector, &intel_sdvo_connector_funcs,
2000                            connector_type);
2001         drm_connector_helper_add(connector, &intel_sdvo_connector_helper_funcs);
2002         connector->interlace_allowed = 0;
2003         connector->doublescan_allowed = 0;
2004         connector->display_info.subpixel_order = SubPixelHorizontalRGB;
2005
2006         drm_encoder_init(dev, &intel_output->enc, &intel_sdvo_enc_funcs, encoder_type);
2007         drm_encoder_helper_add(&intel_output->enc, &intel_sdvo_helper_funcs);
2008
2009         drm_mode_connector_attach_encoder(&intel_output->base, &intel_output->enc);
2010         drm_sysfs_connector_add(connector);
2011
2012         intel_sdvo_select_ddc_bus(sdvo_priv);
2013
2014         /* Set the input timing to the screen. Assume always input 0. */
2015         intel_sdvo_set_target_input(intel_output, true, false);
2016
2017         intel_sdvo_get_input_pixel_clock_range(intel_output,
2018                                                &sdvo_priv->pixel_clock_min,
2019                                                &sdvo_priv->pixel_clock_max);
2020
2021
2022         DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
2023                         "clock range %dMHz - %dMHz, "
2024                         "input 1: %c, input 2: %c, "
2025                         "output 1: %c, output 2: %c\n",
2026                         SDVO_NAME(sdvo_priv),
2027                         sdvo_priv->caps.vendor_id, sdvo_priv->caps.device_id,
2028                         sdvo_priv->caps.device_rev_id,
2029                         sdvo_priv->pixel_clock_min / 1000,
2030                         sdvo_priv->pixel_clock_max / 1000,
2031                         (sdvo_priv->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2032                         (sdvo_priv->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
2033                         /* check currently supported outputs */
2034                         sdvo_priv->caps.output_flags &
2035                         (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
2036                         sdvo_priv->caps.output_flags &
2037                         (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
2038
2039         return true;
2040
2041 err_i2c:
2042         if (intel_output->ddc_bus != NULL)
2043                 intel_i2c_destroy(intel_output->ddc_bus);
2044         if (intel_output->i2c_bus != NULL)
2045                 intel_i2c_destroy(intel_output->i2c_bus);
2046 err_inteloutput:
2047         kfree(intel_output);
2048
2049         return false;
2050 }