SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/i915/intel_sdvo.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2007 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  *
  25  * Authors:
  26  *      Eric Anholt <eric@anholt.net>
  27  */
  28 #include <linux/i2c.h>
  29 #include <linux/delay.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "drm_crtc.h"
  33 #include "intel_drv.h"
  34 #include "drm_edid.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "intel_sdvo_regs.h"
  38 #include <linux/dmi.h>
  39
  40 static char *tv_format_names[] = {
  41         "NTSC_M"   , "NTSC_J"  , "NTSC_443",
  42         "PAL_B"    , "PAL_D"   , "PAL_G"   ,
  43         "PAL_H"    , "PAL_I"   , "PAL_M"   ,
  44         "PAL_N"    , "PAL_NC"  , "PAL_60"  ,
  45         "SECAM_B"  , "SECAM_D" , "SECAM_G" ,
  46         "SECAM_K"  , "SECAM_K1", "SECAM_L" ,
  47         "SECAM_60"
  48 };
  49
  50 #define TV_FORMAT_NUM  (sizeof(tv_format_names) / sizeof(*tv_format_names))
  51
  52 struct intel_sdvo_priv {
  53         u8 slave_addr;
  54
  55         /* Register for the SDVO device: SDVOB or SDVOC */
  56         int sdvo_reg;
  57
  58         /* Active outputs controlled by this SDVO output */
  59         uint16_t controlled_output;
  60
  61         /*
  62          * Capabilities of the SDVO device returned by
  63          * i830_sdvo_get_capabilities()
  64          */
  65         struct intel_sdvo_caps caps;
  66
  67         /* Pixel clock limitations reported by the SDVO device, in kHz */
  68         int pixel_clock_min, pixel_clock_max;
  69
  70         /*
  71         * For multiple function SDVO device,
  72         * this is for current attached outputs.
  73         */
  74         uint16_t attached_output;
  75
  76         /**
  77          * This is set if we're going to treat the device as TV-out.
  78          *
  79          * While we have these nice friendly flags for output types that ought
  80          * to decide this for us, the S-Video output on our HDMI+S-Video card
  81          * shows up as RGB1 (VGA).
  82          */
  83         bool is_tv;
  84
  85         /* This is for current tv format name */
  86         char *tv_format_name;
  87
  88         /* This contains all current supported TV format */
  89         char *tv_format_supported[TV_FORMAT_NUM];
  90         int   format_supported_num;
  91         struct drm_property *tv_format_property;
  92         struct drm_property *tv_format_name_property[TV_FORMAT_NUM];
  93
  94         /**
  95          * This is set if we treat the device as HDMI, instead of DVI.
  96          */
  97         bool is_hdmi;
  98
  99         /**
 100          * This is set if we detect output of sdvo device as LVDS.
 101          */
 102         bool is_lvds;
 103
 104         /**
 105          * This is sdvo flags for input timing.
 106          */
 107         uint8_t sdvo_flags;
 108
 109         /**
 110          * This is sdvo fixed pannel mode pointer
 111          */
 112         struct drm_display_mode *sdvo_lvds_fixed_mode;
 113
 114         /**
 115          * Returned SDTV resolutions allowed for the current format, if the
 116          * device reported it.
 117          */
 118         struct intel_sdvo_sdtv_resolution_reply sdtv_resolutions;
 119
 120         /*
 121          * supported encoding mode, used to determine whether HDMI is
 122          * supported
 123          */
 124         struct intel_sdvo_encode encode;
 125
 126         /* DDC bus used by this SDVO encoder */
 127         uint8_t ddc_bus;
 128
 129         /* Mac mini hack -- use the same DDC as the analog connector */
 130         struct i2c_adapter *analog_ddc_bus;
 131
 132         int save_sdvo_mult;
 133         u16 save_active_outputs;
 134         struct intel_sdvo_dtd save_input_dtd_1, save_input_dtd_2;
 135         struct intel_sdvo_dtd save_output_dtd[16];
 136         u32 save_SDVOX;
 137         /* add the property for the SDVO-TV */
 138         struct drm_property *left_property;
 139         struct drm_property *right_property;
 140         struct drm_property *top_property;
 141         struct drm_property *bottom_property;
 142         struct drm_property *hpos_property;
 143         struct drm_property *vpos_property;
 144
 145         /* add the property for the SDVO-TV/LVDS */
 146         struct drm_property *brightness_property;
 147         struct drm_property *contrast_property;
 148         struct drm_property *saturation_property;
 149         struct drm_property *hue_property;
 150
 151         /* Add variable to record current setting for the above property */
 152         u32     left_margin, right_margin, top_margin, bottom_margin;
 153         /* this is to get the range of margin.*/
 154         u32     max_hscan,  max_vscan;
 155         u32     max_hpos, cur_hpos;
 156         u32     max_vpos, cur_vpos;
 157         u32     cur_brightness, max_brightness;
 158         u32     cur_contrast,   max_contrast;
 159         u32     cur_saturation, max_saturation;
 160         u32     cur_hue,        max_hue;
 161 };
 162
 163 static bool
 164 intel_sdvo_output_setup(struct intel_encoder *intel_encoder, uint16_t flags);
 165
 166 /**
 167  * Writes the SDVOB or SDVOC with the given value, but always writes both
 168  * SDVOB and SDVOC to work around apparent hardware issues (according to
 169  * comments in the BIOS).
 170  */
 171 static void intel_sdvo_write_sdvox(struct intel_encoder *intel_encoder, u32 val)
 172 {
 173         struct drm_device *dev = intel_encoder->base.dev;
 174         struct drm_i915_private *dev_priv = dev->dev_private;
 175         struct intel_sdvo_priv   *sdvo_priv = intel_encoder->dev_priv;
 176         u32 bval = val, cval = val;
 177         int i;
 178
 179         if (sdvo_priv->sdvo_reg == SDVOB) {
 180                 cval = I915_READ(SDVOC);
 181         } else {
 182                 bval = I915_READ(SDVOB);
 183         }
 184         /*
 185          * Write the registers twice for luck. Sometimes,
 186          * writing them only once doesn't appear to 'stick'.
 187          * The BIOS does this too. Yay, magic
 188          */
 189         for (i = 0; i < 2; i++)
 190         {
 191                 I915_WRITE(SDVOB, bval);
 192                 I915_READ(SDVOB);
 193                 I915_WRITE(SDVOC, cval);
 194                 I915_READ(SDVOC);
 195         }
 196 }
 197
 198 static bool intel_sdvo_read_byte(struct intel_encoder *intel_encoder, u8 addr,
 199                                  u8 *ch)
 200 {
 201         struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
 202         u8 out_buf[2];
 203         u8 buf[2];
 204         int ret;
 205
 206         struct i2c_msg msgs[] = {
 207                 {
 208                         .addr = sdvo_priv->slave_addr >> 1,
 209                         .flags = 0,
 210                         .len = 1,
 211                         .buf = out_buf,
 212                 },
 213                 {
 214                         .addr = sdvo_priv->slave_addr >> 1,
 215                         .flags = I2C_M_RD,
 216                         .len = 1,
 217                         .buf = buf,
 218                 }
 219         };
 220
 221         out_buf[0] = addr;
 222         out_buf[1] = 0;
 223
 224         if ((ret = i2c_transfer(intel_encoder->i2c_bus, msgs, 2)) == 2)
 225         {
 226                 *ch = buf[0];
 227                 return true;
 228         }
 229
 230         DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
 231         return false;
 232 }
 233
 234 static bool intel_sdvo_write_byte(struct intel_encoder *intel_encoder, int addr,
 235                                   u8 ch)
 236 {
 237         struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
 238         u8 out_buf[2];
 239         struct i2c_msg msgs[] = {
 240                 {
 241                         .addr = sdvo_priv->slave_addr >> 1,
 242                         .flags = 0,
 243                         .len = 2,
 244                         .buf = out_buf,
 245                 }
 246         };
 247
 248         out_buf[0] = addr;
 249         out_buf[1] = ch;
 250
 251         if (i2c_transfer(intel_encoder->i2c_bus, msgs, 1) == 1)
 252         {
 253                 return true;
 254         }
 255         return false;
 256 }
 257
 258 #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
 259 /** Mapping of command numbers to names, for debug output */
 260 static const struct _sdvo_cmd_name {
 261         u8 cmd;
 262         char *name;
 263 } sdvo_cmd_names[] = {
 264     SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
 265     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
 266     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
 267     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
 268     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
 269     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
 270     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
 271     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
 272     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
 273     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
 274     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
 275     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
 276     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
 277     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
 278     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
 279     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
 280     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
 281     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
 282     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
 283     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
 284     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
 285     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
 286     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
 287     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
 288     SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
 289     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
 290     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
 291     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
 292     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
 293     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
 294     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
 295     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
 296     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
 297     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
 298     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
 299     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
 300     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
 301     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
 302     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
 303     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
 304     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
 305     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
 306     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
 307     /* Add the op code for SDVO enhancements */
 308     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_POSITION_H),
 309     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POSITION_H),
 310     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_POSITION_H),
 311     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_POSITION_V),
 312     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POSITION_V),
 313     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_POSITION_V),
 314     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
 315     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
 316     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
 317     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
 318     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
 319     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
 320     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
 321     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
 322     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
 323     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
 324     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
 325     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
 326     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
 327     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
 328     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
 329     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
 330     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
 331     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
 332     /* HDMI op code */
 333     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
 334     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
 335     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
 336     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
 337     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
 338     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
 339     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
 340     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
 341     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
 342     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
 343     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
 344     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
 345     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
 346     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
 347     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
 348     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
 349     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
 350     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
 351     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
 352     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
 353 };
 354
 355 #define SDVO_NAME(dev_priv) ((dev_priv)->sdvo_reg == SDVOB ? "SDVOB" : "SDVOC")
 356 #define SDVO_PRIV(encoder)   ((struct intel_sdvo_priv *) (encoder)->dev_priv)
 357
 358 static void intel_sdvo_debug_write(struct intel_encoder *intel_encoder, u8 cmd,
 359                                    void *args, int args_len)
 360 {
 361         struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
 362         int i;
 363
 364         DRM_DEBUG_KMS("%s: W: %02X ",
 365                                 SDVO_NAME(sdvo_priv), cmd);
 366         for (i = 0; i < args_len; i++)
 367                 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
 368         for (; i < 8; i++)
 369                 DRM_LOG_KMS("   ");
 370         for (i = 0; i < sizeof(sdvo_cmd_names) / sizeof(sdvo_cmd_names[0]); i++) {
 371                 if (cmd == sdvo_cmd_names[i].cmd) {
 372                         DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
 373                         break;
 374                 }
 375         }
 376         if (i == sizeof(sdvo_cmd_names)/ sizeof(sdvo_cmd_names[0]))
 377                 DRM_LOG_KMS("(%02X)", cmd);
 378         DRM_LOG_KMS("\n");
 379 }
 380
 381 static void intel_sdvo_write_cmd(struct intel_encoder *intel_encoder, u8 cmd,
 382                                  void *args, int args_len)
 383 {
 384         int i;
 385
 386         intel_sdvo_debug_write(intel_encoder, cmd, args, args_len);
 387
 388         for (i = 0; i < args_len; i++) {
 389                 intel_sdvo_write_byte(intel_encoder, SDVO_I2C_ARG_0 - i,
 390                                       ((u8*)args)[i]);
 391         }
 392
 393         intel_sdvo_write_byte(intel_encoder, SDVO_I2C_OPCODE, cmd);
 394 }
 395
 396 static const char *cmd_status_names[] = {
 397         "Power on",
 398         "Success",
 399         "Not supported",
 400         "Invalid arg",
 401         "Pending",
 402         "Target not specified",
 403         "Scaling not supported"
 404 };
 405
 406 static void intel_sdvo_debug_response(struct intel_encoder *intel_encoder,
 407                                       void *response, int response_len,
 408                                       u8 status)
 409 {
 410         struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
 411         int i;
 412
 413         DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(sdvo_priv));
 414         for (i = 0; i < response_len; i++)
 415                 DRM_LOG_KMS("%02X ", ((u8 *)response)[i]);
 416         for (; i < 8; i++)
 417                 DRM_LOG_KMS("   ");
 418         if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
 419                 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
 420         else
 421                 DRM_LOG_KMS("(??? %d)", status);
 422         DRM_LOG_KMS("\n");
 423 }
 424
 425 static u8 intel_sdvo_read_response(struct intel_encoder *intel_encoder,
 426                                    void *response, int response_len)
 427 {
 428         int i;
 429         u8 status;
 430         u8 retry = 50;
 431
 432         while (retry--) {
 433                 /* Read the command response */
 434                 for (i = 0; i < response_len; i++) {
 435                         intel_sdvo_read_byte(intel_encoder,
 436                                              SDVO_I2C_RETURN_0 + i,
 437                                              &((u8 *)response)[i]);
 438                 }
 439
 440                 /* read the return status */
 441                 intel_sdvo_read_byte(intel_encoder, SDVO_I2C_CMD_STATUS,
 442                                      &status);
 443
 444                 intel_sdvo_debug_response(intel_encoder, response, response_len,
 445                                           status);
 446                 if (status != SDVO_CMD_STATUS_PENDING)
 447                         return status;
 448
 449                 mdelay(50);
 450         }
 451
 452         return status;
 453 }
 454
 455 static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
 456 {
 457         if (mode->clock >= 100000)
 458                 return 1;
 459         else if (mode->clock >= 50000)
 460                 return 2;
 461         else
 462                 return 4;
 463 }
 464
 465 /**
 466  * Try to read the response after issuie the DDC switch command. But it
 467  * is noted that we must do the action of reading response and issuing DDC
 468  * switch command in one I2C transaction. Otherwise when we try to start
 469  * another I2C transaction after issuing the DDC bus switch, it will be
 470  * switched to the internal SDVO register.
 471  */
 472 static void intel_sdvo_set_control_bus_switch(struct intel_encoder *intel_encoder,
 473                                               u8 target)
 474 {
 475         struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
 476         u8 out_buf[2], cmd_buf[2], ret_value[2], ret;
 477         struct i2c_msg msgs[] = {
 478                 {
 479                         .addr = sdvo_priv->slave_addr >> 1,
 480                         .flags = 0,
 481                         .len = 2,
 482                         .buf = out_buf,
 483                 },
 484                 /* the following two are to read the response */
 485                 {
 486                         .addr = sdvo_priv->slave_addr >> 1,
 487                         .flags = 0,
 488                         .len = 1,
 489                         .buf = cmd_buf,
 490                 },
 491                 {
 492                         .addr = sdvo_priv->slave_addr >> 1,
 493                         .flags = I2C_M_RD,
 494                         .len = 1,
 495                         .buf = ret_value,
 496                 },
 497         };
 498
 499         intel_sdvo_debug_write(intel_encoder, SDVO_CMD_SET_CONTROL_BUS_SWITCH,
 500                                         &target, 1);
 501         /* write the DDC switch command argument */
 502         intel_sdvo_write_byte(intel_encoder, SDVO_I2C_ARG_0, target);
 503
 504         out_buf[0] = SDVO_I2C_OPCODE;
 505         out_buf[1] = SDVO_CMD_SET_CONTROL_BUS_SWITCH;
 506         cmd_buf[0] = SDVO_I2C_CMD_STATUS;
 507         cmd_buf[1] = 0;
 508         ret_value[0] = 0;
 509         ret_value[1] = 0;
 510
 511         ret = i2c_transfer(intel_encoder->i2c_bus, msgs, 3);
 512         if (ret != 3) {
 513                 /* failure in I2C transfer */
 514                 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
 515                 return;
 516         }
 517         if (ret_value[0] != SDVO_CMD_STATUS_SUCCESS) {
 518                 DRM_DEBUG_KMS("DDC switch command returns response %d\n",
 519                                         ret_value[0]);
 520                 return;
 521         }
 522         return;
 523 }
 524
 525 static bool intel_sdvo_set_target_input(struct intel_encoder *intel_encoder, bool target_0, bool target_1)
 526 {
 527         struct intel_sdvo_set_target_input_args targets = {0};
 528         u8 status;
 529
 530         if (target_0 && target_1)
 531                 return SDVO_CMD_STATUS_NOTSUPP;
 532
 533         if (target_1)
 534                 targets.target_1 = 1;
 535
 536         intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_TARGET_INPUT, &targets,
 537                              sizeof(targets));
 538
 539         status = intel_sdvo_read_response(intel_encoder, NULL, 0);
 540
 541         return (status == SDVO_CMD_STATUS_SUCCESS);
 542 }
 543
 544 /**
 545  * Return whether each input is trained.
 546  *
 547  * This function is making an assumption about the layout of the response,
 548  * which should be checked against the docs.
 549  */
 550 static bool intel_sdvo_get_trained_inputs(struct intel_encoder *intel_encoder, bool *input_1, bool *input_2)
 551 {
 552         struct intel_sdvo_get_trained_inputs_response response;
 553         u8 status;
 554
 555         intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_TRAINED_INPUTS, NULL, 0);
 556         status = intel_sdvo_read_response(intel_encoder, &response, sizeof(response));
 557         if (status != SDVO_CMD_STATUS_SUCCESS)
 558                 return false;
 559
 560         *input_1 = response.input0_trained;
 561         *input_2 = response.input1_trained;
 562         return true;
 563 }
 564
 565 static bool intel_sdvo_get_active_outputs(struct intel_encoder *intel_encoder,
 566                                           u16 *outputs)
 567 {
 568         u8 status;
 569
 570         intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_ACTIVE_OUTPUTS, NULL, 0);
 571         status = intel_sdvo_read_response(intel_encoder, outputs, sizeof(*outputs));
 572
 573         return (status == SDVO_CMD_STATUS_SUCCESS);
 574 }
 575
 576 static bool intel_sdvo_set_active_outputs(struct intel_encoder *intel_encoder,
 577                                           u16 outputs)
 578 {
 579         u8 status;
 580
 581         intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ACTIVE_OUTPUTS, &outputs,
 582                              sizeof(outputs));
 583         status = intel_sdvo_read_response(intel_encoder, NULL, 0);
 584         return (status == SDVO_CMD_STATUS_SUCCESS);
 585 }
 586
 587 static bool intel_sdvo_set_encoder_power_state(struct intel_encoder *intel_encoder,
 588                                                int mode)
 589 {
 590         u8 status, state = SDVO_ENCODER_STATE_ON;
 591
 592         switch (mode) {
 593         case DRM_MODE_DPMS_ON:
 594                 state = SDVO_ENCODER_STATE_ON;
 595                 break;
 596         case DRM_MODE_DPMS_STANDBY:
 597                 state = SDVO_ENCODER_STATE_STANDBY;
 598                 break;
 599         case DRM_MODE_DPMS_SUSPEND:
 600                 state = SDVO_ENCODER_STATE_SUSPEND;
 601                 break;
 602         case DRM_MODE_DPMS_OFF:
 603                 state = SDVO_ENCODER_STATE_OFF;
 604                 break;
 605         }
 606
 607         intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ENCODER_POWER_STATE, &state,
 608                              sizeof(state));
 609         status = intel_sdvo_read_response(intel_encoder, NULL, 0);
 610
 611         return (status == SDVO_CMD_STATUS_SUCCESS);
 612 }
 613
 614 static bool intel_sdvo_get_input_pixel_clock_range(struct intel_encoder *intel_encoder,
 615                                                    int *clock_min,
 616                                                    int *clock_max)
 617 {
 618         struct intel_sdvo_pixel_clock_range clocks;
 619         u8 status;
 620
 621         intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
 622                              NULL, 0);
 623
 624         status = intel_sdvo_read_response(intel_encoder, &clocks, sizeof(clocks));
 625
 626         if (status != SDVO_CMD_STATUS_SUCCESS)
 627                 return false;
 628
 629         /* Convert the values from units of 10 kHz to kHz. */
 630         *clock_min = clocks.min * 10;
 631         *clock_max = clocks.max * 10;
 632
 633         return true;
 634 }
 635
 636 static bool intel_sdvo_set_target_output(struct intel_encoder *intel_encoder,
 637                                          u16 outputs)
 638 {
 639         u8 status;
 640
 641         intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_TARGET_OUTPUT, &outputs,
 642                              sizeof(outputs));
 643
 644         status = intel_sdvo_read_response(intel_encoder, NULL, 0);
 645         return (status == SDVO_CMD_STATUS_SUCCESS);
 646 }
 647
 648 static bool intel_sdvo_get_timing(struct intel_encoder *intel_encoder, u8 cmd,
 649                                   struct intel_sdvo_dtd *dtd)
 650 {
 651         u8 status;
 652
 653         intel_sdvo_write_cmd(intel_encoder, cmd, NULL, 0);
 654         status = intel_sdvo_read_response(intel_encoder, &dtd->part1,
 655                                           sizeof(dtd->part1));
 656         if (status != SDVO_CMD_STATUS_SUCCESS)
 657                 return false;
 658
 659         intel_sdvo_write_cmd(intel_encoder, cmd + 1, NULL, 0);
 660         status = intel_sdvo_read_response(intel_encoder, &dtd->part2,
 661                                           sizeof(dtd->part2));
 662         if (status != SDVO_CMD_STATUS_SUCCESS)
 663                 return false;
 664
 665         return true;
 666 }
 667
 668 static bool intel_sdvo_get_input_timing(struct intel_encoder *intel_encoder,
 669                                          struct intel_sdvo_dtd *dtd)
 670 {
 671         return intel_sdvo_get_timing(intel_encoder,
 672                                      SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
 673 }
 674
 675 static bool intel_sdvo_get_output_timing(struct intel_encoder *intel_encoder,
 676                                          struct intel_sdvo_dtd *dtd)
 677 {
 678         return intel_sdvo_get_timing(intel_encoder,
 679                                      SDVO_CMD_GET_OUTPUT_TIMINGS_PART1, dtd);
 680 }
 681
 682 static bool intel_sdvo_set_timing(struct intel_encoder *intel_encoder, u8 cmd,
 683                                   struct intel_sdvo_dtd *dtd)
 684 {
 685         u8 status;
 686
 687         intel_sdvo_write_cmd(intel_encoder, cmd, &dtd->part1, sizeof(dtd->part1));
 688         status = intel_sdvo_read_response(intel_encoder, NULL, 0);
 689         if (status != SDVO_CMD_STATUS_SUCCESS)
 690                 return false;
 691
 692         intel_sdvo_write_cmd(intel_encoder, cmd + 1, &dtd->part2, sizeof(dtd->part2));
 693         status = intel_sdvo_read_response(intel_encoder, NULL, 0);
 694         if (status != SDVO_CMD_STATUS_SUCCESS)
 695                 return false;
 696
 697         return true;
 698 }
 699
 700 static bool intel_sdvo_set_input_timing(struct intel_encoder *intel_encoder,
 701                                          struct intel_sdvo_dtd *dtd)
 702 {
 703         return intel_sdvo_set_timing(intel_encoder,
 704                                      SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
 705 }
 706
 707 static bool intel_sdvo_set_output_timing(struct intel_encoder *intel_encoder,
 708                                          struct intel_sdvo_dtd *dtd)
 709 {
 710         return intel_sdvo_set_timing(intel_encoder,
 711                                      SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
 712 }
 713
 714 static bool
 715 intel_sdvo_create_preferred_input_timing(struct intel_encoder *intel_encoder,
 716                                          uint16_t clock,
 717                                          uint16_t width,
 718                                          uint16_t height)
 719 {
 720         struct intel_sdvo_preferred_input_timing_args args;
 721         struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
 722         uint8_t status;
 723
 724         memset(&args, 0, sizeof(args));
 725         args.clock = clock;
 726         args.width = width;
 727         args.height = height;
 728         args.interlace = 0;
 729
 730         if (sdvo_priv->is_lvds &&
 731            (sdvo_priv->sdvo_lvds_fixed_mode->hdisplay != width ||
 732             sdvo_priv->sdvo_lvds_fixed_mode->vdisplay != height))
 733                 args.scaled = 1;
 734
 735         intel_sdvo_write_cmd(intel_encoder,
 736                              SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
 737                              &args, sizeof(args));
 738         status = intel_sdvo_read_response(intel_encoder, NULL, 0);
 739         if (status != SDVO_CMD_STATUS_SUCCESS)
 740                 return false;
 741
 742         return true;
 743 }
 744
 745 static bool intel_sdvo_get_preferred_input_timing(struct intel_encoder *intel_encoder,
 746                                                   struct intel_sdvo_dtd *dtd)
 747 {
 748         bool status;
 749
 750         intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
 751                              NULL, 0);
 752
 753         status = intel_sdvo_read_response(intel_encoder, &dtd->part1,
 754                                           sizeof(dtd->part1));
 755         if (status != SDVO_CMD_STATUS_SUCCESS)
 756                 return false;
 757
 758         intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
 759                              NULL, 0);
 760
 761         status = intel_sdvo_read_response(intel_encoder, &dtd->part2,
 762                                           sizeof(dtd->part2));
 763         if (status != SDVO_CMD_STATUS_SUCCESS)
 764                 return false;
 765
 766         return false;
 767 }
 768
 769 static int intel_sdvo_get_clock_rate_mult(struct intel_encoder *intel_encoder)
 770 {
 771         u8 response, status;
 772
 773         intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_CLOCK_RATE_MULT, NULL, 0);
 774         status = intel_sdvo_read_response(intel_encoder, &response, 1);
 775
 776         if (status != SDVO_CMD_STATUS_SUCCESS) {
 777                 DRM_DEBUG_KMS("Couldn't get SDVO clock rate multiplier\n");
 778                 return SDVO_CLOCK_RATE_MULT_1X;
 779         } else {
 780                 DRM_DEBUG_KMS("Current clock rate multiplier: %d\n", response);
 781         }
 782
 783         return response;
 784 }
 785
 786 static bool intel_sdvo_set_clock_rate_mult(struct intel_encoder *intel_encoder, u8 val)
 787 {
 788         u8 status;
 789
 790         intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
 791         status = intel_sdvo_read_response(intel_encoder, NULL, 0);
 792         if (status != SDVO_CMD_STATUS_SUCCESS)
 793                 return false;
 794
 795         return true;
 796 }
 797
 798 static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
 799                                          struct drm_display_mode *mode)
 800 {
 801         uint16_t width, height;
 802         uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
 803         uint16_t h_sync_offset, v_sync_offset;
 804
 805         width = mode->crtc_hdisplay;
 806         height = mode->crtc_vdisplay;
 807
 808         /* do some mode translations */
 809         h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
 810         h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
 811
 812         v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
 813         v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
 814
 815         h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
 816         v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
 817
 818         dtd->part1.clock = mode->clock / 10;
 819         dtd->part1.h_active = width & 0xff;
 820         dtd->part1.h_blank = h_blank_len & 0xff;
 821         dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
 822                 ((h_blank_len >> 8) & 0xf);
 823         dtd->part1.v_active = height & 0xff;
 824         dtd->part1.v_blank = v_blank_len & 0xff;
 825         dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
 826                 ((v_blank_len >> 8) & 0xf);
 827
 828         dtd->part2.h_sync_off = h_sync_offset & 0xff;
 829         dtd->part2.h_sync_width = h_sync_len & 0xff;
 830         dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
 831                 (v_sync_len & 0xf);
 832         dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
 833                 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
 834                 ((v_sync_len & 0x30) >> 4);
 835
 836         dtd->part2.dtd_flags = 0x18;
 837         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
 838                 dtd->part2.dtd_flags |= 0x2;
 839         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
 840                 dtd->part2.dtd_flags |= 0x4;
 841
 842         dtd->part2.sdvo_flags = 0;
 843         dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
 844         dtd->part2.reserved = 0;
 845 }
 846
 847 static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
 848                                          struct intel_sdvo_dtd *dtd)
 849 {
 850         mode->hdisplay = dtd->part1.h_active;
 851         mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
 852         mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
 853         mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
 854         mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
 855         mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
 856         mode->htotal = mode->hdisplay + dtd->part1.h_blank;
 857         mode->htotal += (dtd->part1.h_high & 0xf) << 8;
 858
 859         mode->vdisplay = dtd->part1.v_active;
 860         mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
 861         mode->vsync_start = mode->vdisplay;
 862         mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
 863         mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
 864         mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
 865         mode->vsync_end = mode->vsync_start +
 866                 (dtd->part2.v_sync_off_width & 0xf);
 867         mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
 868         mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
 869         mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
 870
 871         mode->clock = dtd->part1.clock * 10;
 872
 873         mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
 874         if (dtd->part2.dtd_flags & 0x2)
 875                 mode->flags |= DRM_MODE_FLAG_PHSYNC;
 876         if (dtd->part2.dtd_flags & 0x4)
 877                 mode->flags |= DRM_MODE_FLAG_PVSYNC;
 878 }
 879
 880 static bool intel_sdvo_get_supp_encode(struct intel_encoder *intel_encoder,
 881                                        struct intel_sdvo_encode *encode)
 882 {
 883         uint8_t status;
 884
 885         intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_SUPP_ENCODE, NULL, 0);
 886         status = intel_sdvo_read_response(intel_encoder, encode, sizeof(*encode));
 887         if (status != SDVO_CMD_STATUS_SUCCESS) { /* non-support means DVI */
 888                 memset(encode, 0, sizeof(*encode));
 889                 return false;
 890         }
 891
 892         return true;
 893 }
 894
 895 static bool intel_sdvo_set_encode(struct intel_encoder *intel_encoder,
 896                                   uint8_t mode)
 897 {
 898         uint8_t status;
 899
 900         intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ENCODE, &mode, 1);
 901         status = intel_sdvo_read_response(intel_encoder, NULL, 0);
 902
 903         return (status == SDVO_CMD_STATUS_SUCCESS);
 904 }
 905
 906 static bool intel_sdvo_set_colorimetry(struct intel_encoder *intel_encoder,
 907                                        uint8_t mode)
 908 {
 909         uint8_t status;
 910
 911         intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
 912         status = intel_sdvo_read_response(intel_encoder, NULL, 0);
 913
 914         return (status == SDVO_CMD_STATUS_SUCCESS);
 915 }
 916
 917 #if 0
 918 static void intel_sdvo_dump_hdmi_buf(struct intel_encoder *intel_encoder)
 919 {
 920         int i, j;
 921         uint8_t set_buf_index[2];
 922         uint8_t av_split;
 923         uint8_t buf_size;
 924         uint8_t buf[48];
 925         uint8_t *pos;
 926
 927         intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, NULL, 0);
 928         intel_sdvo_read_response(encoder, &av_split, 1);
 929
 930         for (i = 0; i <= av_split; i++) {
 931                 set_buf_index[0] = i; set_buf_index[1] = 0;
 932                 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
 933                                      set_buf_index, 2);
 934                 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
 935                 intel_sdvo_read_response(encoder, &buf_size, 1);
 936
 937                 pos = buf;
 938                 for (j = 0; j <= buf_size; j += 8) {
 939                         intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
 940                                              NULL, 0);
 941                         intel_sdvo_read_response(encoder, pos, 8);
 942                         pos += 8;
 943                 }
 944         }
 945 }
 946 #endif
 947
 948 static void intel_sdvo_set_hdmi_buf(struct intel_encoder *intel_encoder,
 949                                     int index,
 950                                     uint8_t *data, int8_t size, uint8_t tx_rate)
 951 {
 952     uint8_t set_buf_index[2];
 953
 954     set_buf_index[0] = index;
 955     set_buf_index[1] = 0;
 956
 957     intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_HBUF_INDEX,
 958                          set_buf_index, 2);
 959
 960     for (; size > 0; size -= 8) {
 961         intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_HBUF_DATA, data, 8);
 962         data += 8;
 963     }
 964
 965     intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1);
 966 }
 967
 968 static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size)
 969 {
 970         uint8_t csum = 0;
 971         int i;
 972
 973         for (i = 0; i < size; i++)
 974                 csum += data[i];
 975
 976         return 0x100 - csum;
 977 }
 978
 979 #define DIP_TYPE_AVI    0x82
 980 #define DIP_VERSION_AVI 0x2
 981 #define DIP_LEN_AVI     13
 982
 983 struct dip_infoframe {
 984         uint8_t type;
 985         uint8_t version;
 986         uint8_t len;
 987         uint8_t checksum;
 988         union {
 989                 struct {
 990                         /* Packet Byte #1 */
 991                         uint8_t S:2;
 992                         uint8_t B:2;
 993                         uint8_t A:1;
 994                         uint8_t Y:2;
 995                         uint8_t rsvd1:1;
 996                         /* Packet Byte #2 */
 997                         uint8_t R:4;
 998                         uint8_t M:2;
 999                         uint8_t C:2;
1000                         /* Packet Byte #3 */
1001                         uint8_t SC:2;
1002                         uint8_t Q:2;
1003                         uint8_t EC:3;
1004                         uint8_t ITC:1;
1005                         /* Packet Byte #4 */
1006                         uint8_t VIC:7;
1007                         uint8_t rsvd2:1;
1008                         /* Packet Byte #5 */
1009                         uint8_t PR:4;
1010                         uint8_t rsvd3:4;
1011                         /* Packet Byte #6~13 */
1012                         uint16_t top_bar_end;
1013                         uint16_t bottom_bar_start;
1014                         uint16_t left_bar_end;
1015                         uint16_t right_bar_start;
1016                 } avi;
1017                 struct {
1018                         /* Packet Byte #1 */
1019                         uint8_t channel_count:3;
1020                         uint8_t rsvd1:1;
1021                         uint8_t coding_type:4;
1022                         /* Packet Byte #2 */
1023                         uint8_t sample_size:2; /* SS0, SS1 */
1024                         uint8_t sample_frequency:3;
1025                         uint8_t rsvd2:3;
1026                         /* Packet Byte #3 */
1027                         uint8_t coding_type_private:5;
1028                         uint8_t rsvd3:3;
1029                         /* Packet Byte #4 */
1030                         uint8_t channel_allocation;
1031                         /* Packet Byte #5 */
1032                         uint8_t rsvd4:3;
1033                         uint8_t level_shift:4;
1034                         uint8_t downmix_inhibit:1;
1035                 } audio;
1036                 uint8_t payload[28];
1037         } __attribute__ ((packed)) u;
1038 } __attribute__((packed));
1039
1040 static void intel_sdvo_set_avi_infoframe(struct intel_encoder *intel_encoder,
1041                                          struct drm_display_mode * mode)
1042 {
1043         struct dip_infoframe avi_if = {
1044                 .type = DIP_TYPE_AVI,
1045                 .version = DIP_VERSION_AVI,
1046                 .len = DIP_LEN_AVI,
1047         };
1048
1049         avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if,
1050                                                     4 + avi_if.len);
1051         intel_sdvo_set_hdmi_buf(intel_encoder, 1, (uint8_t *)&avi_if,
1052                                 4 + avi_if.len,
1053                                 SDVO_HBUF_TX_VSYNC);
1054 }
1055
1056 static void intel_sdvo_set_tv_format(struct intel_encoder *intel_encoder)
1057 {
1058
1059         struct intel_sdvo_tv_format format;
1060         struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1061         uint32_t format_map, i;
1062         uint8_t status;
1063
1064         for (i = 0; i < TV_FORMAT_NUM; i++)
1065                 if (tv_format_names[i] == sdvo_priv->tv_format_name)
1066                         break;
1067
1068         format_map = 1 << i;
1069         memset(&format, 0, sizeof(format));
1070         memcpy(&format, &format_map, sizeof(format_map) > sizeof(format) ?
1071                         sizeof(format) : sizeof(format_map));
1072
1073         intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_TV_FORMAT, &format_map,
1074                              sizeof(format));
1075
1076         status = intel_sdvo_read_response(intel_encoder, NULL, 0);
1077         if (status != SDVO_CMD_STATUS_SUCCESS)
1078                 DRM_DEBUG_KMS("%s: Failed to set TV format\n",
1079                           SDVO_NAME(sdvo_priv));
1080 }
1081
1082 static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
1083                                   struct drm_display_mode *mode,
1084                                   struct drm_display_mode *adjusted_mode)
1085 {
1086         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1087         struct intel_sdvo_priv *dev_priv = intel_encoder->dev_priv;
1088
1089         if (dev_priv->is_tv) {
1090                 struct intel_sdvo_dtd output_dtd;
1091                 bool success;
1092
1093                 /* We need to construct preferred input timings based on our
1094                  * output timings.  To do that, we have to set the output
1095                  * timings, even though this isn't really the right place in
1096                  * the sequence to do it. Oh well.
1097                  */
1098
1099
1100                 /* Set output timings */
1101                 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1102                 intel_sdvo_set_target_output(intel_encoder,
1103                                              dev_priv->controlled_output);
1104                 intel_sdvo_set_output_timing(intel_encoder, &output_dtd);
1105
1106                 /* Set the input timing to the screen. Assume always input 0. */
1107                 intel_sdvo_set_target_input(intel_encoder, true, false);
1108
1109
1110                 success = intel_sdvo_create_preferred_input_timing(intel_encoder,
1111                                                                    mode->clock / 10,
1112                                                                    mode->hdisplay,
1113                                                                    mode->vdisplay);
1114                 if (success) {
1115                         struct intel_sdvo_dtd input_dtd;
1116
1117                         intel_sdvo_get_preferred_input_timing(intel_encoder,
1118                                                              &input_dtd);
1119                         intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
1120                         dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags;
1121
1122                         drm_mode_set_crtcinfo(adjusted_mode, 0);
1123
1124                         mode->clock = adjusted_mode->clock;
1125
1126                         adjusted_mode->clock *=
1127                                 intel_sdvo_get_pixel_multiplier(mode);
1128                 } else {
1129                         return false;
1130                 }
1131         } else if (dev_priv->is_lvds) {
1132                 struct intel_sdvo_dtd output_dtd;
1133                 bool success;
1134
1135                 drm_mode_set_crtcinfo(dev_priv->sdvo_lvds_fixed_mode, 0);
1136                 /* Set output timings */
1137                 intel_sdvo_get_dtd_from_mode(&output_dtd,
1138                                 dev_priv->sdvo_lvds_fixed_mode);
1139
1140                 intel_sdvo_set_target_output(intel_encoder,
1141                                              dev_priv->controlled_output);
1142                 intel_sdvo_set_output_timing(intel_encoder, &output_dtd);
1143
1144                 /* Set the input timing to the screen. Assume always input 0. */
1145                 intel_sdvo_set_target_input(intel_encoder, true, false);
1146
1147
1148                 success = intel_sdvo_create_preferred_input_timing(
1149                                 intel_encoder,
1150                                 mode->clock / 10,
1151                                 mode->hdisplay,
1152                                 mode->vdisplay);
1153
1154                 if (success) {
1155                         struct intel_sdvo_dtd input_dtd;
1156
1157                         intel_sdvo_get_preferred_input_timing(intel_encoder,
1158                                                              &input_dtd);
1159                         intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
1160                         dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags;
1161
1162                         drm_mode_set_crtcinfo(adjusted_mode, 0);
1163
1164                         mode->clock = adjusted_mode->clock;
1165
1166                         adjusted_mode->clock *=
1167                                 intel_sdvo_get_pixel_multiplier(mode);
1168                 } else {
1169                         return false;
1170                 }
1171
1172         } else {
1173                 /* Make the CRTC code factor in the SDVO pixel multiplier.  The
1174                  * SDVO device will be told of the multiplier during mode_set.
1175                  */
1176                 adjusted_mode->clock *= intel_sdvo_get_pixel_multiplier(mode);
1177         }
1178         return true;
1179 }
1180
1181 static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1182                                 struct drm_display_mode *mode,
1183                                 struct drm_display_mode *adjusted_mode)
1184 {
1185         struct drm_device *dev = encoder->dev;
1186         struct drm_i915_private *dev_priv = dev->dev_private;
1187         struct drm_crtc *crtc = encoder->crtc;
1188         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1189         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1190         struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1191         u32 sdvox = 0;
1192         int sdvo_pixel_multiply;
1193         struct intel_sdvo_in_out_map in_out;
1194         struct intel_sdvo_dtd input_dtd;
1195         u8 status;
1196
1197         if (!mode)
1198                 return;
1199
1200         /* First, set the input mapping for the first input to our controlled
1201          * output. This is only correct if we're a single-input device, in
1202          * which case the first input is the output from the appropriate SDVO
1203          * channel on the motherboard.  In a two-input device, the first input
1204          * will be SDVOB and the second SDVOC.
1205          */
1206         in_out.in0 = sdvo_priv->controlled_output;
1207         in_out.in1 = 0;
1208
1209         intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_IN_OUT_MAP,
1210                              &in_out, sizeof(in_out));
1211         status = intel_sdvo_read_response(intel_encoder, NULL, 0);
1212
1213         if (sdvo_priv->is_hdmi) {
1214                 intel_sdvo_set_avi_infoframe(intel_encoder, mode);
1215                 sdvox |= SDVO_AUDIO_ENABLE;
1216         }
1217
1218         /* We have tried to get input timing in mode_fixup, and filled into
1219            adjusted_mode */
1220         if (sdvo_priv->is_tv || sdvo_priv->is_lvds) {
1221                 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
1222                 input_dtd.part2.sdvo_flags = sdvo_priv->sdvo_flags;
1223         } else
1224                 intel_sdvo_get_dtd_from_mode(&input_dtd, mode);
1225
1226         /* If it's a TV, we already set the output timing in mode_fixup.
1227          * Otherwise, the output timing is equal to the input timing.
1228          */
1229         if (!sdvo_priv->is_tv && !sdvo_priv->is_lvds) {
1230                 /* Set the output timing to the screen */
1231                 intel_sdvo_set_target_output(intel_encoder,
1232                                              sdvo_priv->controlled_output);
1233                 intel_sdvo_set_output_timing(intel_encoder, &input_dtd);
1234         }
1235
1236         /* Set the input timing to the screen. Assume always input 0. */
1237         intel_sdvo_set_target_input(intel_encoder, true, false);
1238
1239         if (sdvo_priv->is_tv)
1240                 intel_sdvo_set_tv_format(intel_encoder);
1241
1242         /* We would like to use intel_sdvo_create_preferred_input_timing() to
1243          * provide the device with a timing it can support, if it supports that
1244          * feature.  However, presumably we would need to adjust the CRTC to
1245          * output the preferred timing, and we don't support that currently.
1246          */
1247 #if 0
1248         success = intel_sdvo_create_preferred_input_timing(encoder, clock,
1249                                                            width, height);
1250         if (success) {
1251                 struct intel_sdvo_dtd *input_dtd;
1252
1253                 intel_sdvo_get_preferred_input_timing(encoder, &input_dtd);
1254                 intel_sdvo_set_input_timing(encoder, &input_dtd);
1255         }
1256 #else
1257         intel_sdvo_set_input_timing(intel_encoder, &input_dtd);
1258 #endif
1259
1260         switch (intel_sdvo_get_pixel_multiplier(mode)) {
1261         case 1:
1262                 intel_sdvo_set_clock_rate_mult(intel_encoder,
1263                                                SDVO_CLOCK_RATE_MULT_1X);
1264                 break;
1265         case 2:
1266                 intel_sdvo_set_clock_rate_mult(intel_encoder,
1267                                                SDVO_CLOCK_RATE_MULT_2X);
1268                 break;
1269         case 4:
1270                 intel_sdvo_set_clock_rate_mult(intel_encoder,
1271                                                SDVO_CLOCK_RATE_MULT_4X);
1272                 break;
1273         }
1274
1275         /* Set the SDVO control regs. */
1276         if (IS_I965G(dev)) {
1277                 sdvox |= SDVO_BORDER_ENABLE |
1278                         SDVO_VSYNC_ACTIVE_HIGH |
1279                         SDVO_HSYNC_ACTIVE_HIGH;
1280         } else {
1281                 sdvox |= I915_READ(sdvo_priv->sdvo_reg);
1282                 switch (sdvo_priv->sdvo_reg) {
1283                 case SDVOB:
1284                         sdvox &= SDVOB_PRESERVE_MASK;
1285                         break;
1286                 case SDVOC:
1287                         sdvox &= SDVOC_PRESERVE_MASK;
1288                         break;
1289                 }
1290                 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1291         }
1292         if (intel_crtc->pipe == 1)
1293                 sdvox |= SDVO_PIPE_B_SELECT;
1294
1295         sdvo_pixel_multiply = intel_sdvo_get_pixel_multiplier(mode);
1296         if (IS_I965G(dev)) {
1297                 /* done in crtc_mode_set as the dpll_md reg must be written early */
1298         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1299                 /* done in crtc_mode_set as it lives inside the dpll register */
1300         } else {
1301                 sdvox |= (sdvo_pixel_multiply - 1) << SDVO_PORT_MULTIPLY_SHIFT;
1302         }
1303
1304         if (sdvo_priv->sdvo_flags & SDVO_NEED_TO_STALL)
1305                 sdvox |= SDVO_STALL_SELECT;
1306         intel_sdvo_write_sdvox(intel_encoder, sdvox);
1307 }
1308
1309 static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1310 {
1311         struct drm_device *dev = encoder->dev;
1312         struct drm_i915_private *dev_priv = dev->dev_private;
1313         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1314         struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1315         u32 temp;
1316
1317         if (mode != DRM_MODE_DPMS_ON) {
1318                 intel_sdvo_set_active_outputs(intel_encoder, 0);
1319                 if (0)
1320                         intel_sdvo_set_encoder_power_state(intel_encoder, mode);
1321
1322                 if (mode == DRM_MODE_DPMS_OFF) {
1323                         temp = I915_READ(sdvo_priv->sdvo_reg);
1324                         if ((temp & SDVO_ENABLE) != 0) {
1325                                 intel_sdvo_write_sdvox(intel_encoder, temp & ~SDVO_ENABLE);
1326                         }
1327                 }
1328         } else {
1329                 bool input1, input2;
1330                 int i;
1331                 u8 status;
1332
1333                 temp = I915_READ(sdvo_priv->sdvo_reg);
1334                 if ((temp & SDVO_ENABLE) == 0)
1335                         intel_sdvo_write_sdvox(intel_encoder, temp | SDVO_ENABLE);
1336                 for (i = 0; i < 2; i++)
1337                   intel_wait_for_vblank(dev);
1338
1339                 status = intel_sdvo_get_trained_inputs(intel_encoder, &input1,
1340                                                        &input2);
1341
1342
1343                 /* Warn if the device reported failure to sync.
1344                  * A lot of SDVO devices fail to notify of sync, but it's
1345                  * a given it the status is a success, we succeeded.
1346                  */
1347                 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
1348                         DRM_DEBUG_KMS("First %s output reported failure to "
1349                                         "sync\n", SDVO_NAME(sdvo_priv));
1350                 }
1351
1352                 if (0)
1353                         intel_sdvo_set_encoder_power_state(intel_encoder, mode);
1354                 intel_sdvo_set_active_outputs(intel_encoder, sdvo_priv->controlled_output);
1355         }
1356         return;
1357 }
1358
1359 static void intel_sdvo_save(struct drm_connector *connector)
1360 {
1361         struct drm_device *dev = connector->dev;
1362         struct drm_i915_private *dev_priv = dev->dev_private;
1363         struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1364         struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1365         int o;
1366
1367         sdvo_priv->save_sdvo_mult = intel_sdvo_get_clock_rate_mult(intel_encoder);
1368         intel_sdvo_get_active_outputs(intel_encoder, &sdvo_priv->save_active_outputs);
1369
1370         if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
1371                 intel_sdvo_set_target_input(intel_encoder, true, false);
1372                 intel_sdvo_get_input_timing(intel_encoder,
1373                                             &sdvo_priv->save_input_dtd_1);
1374         }
1375
1376         if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
1377                 intel_sdvo_set_target_input(intel_encoder, false, true);
1378                 intel_sdvo_get_input_timing(intel_encoder,
1379                                             &sdvo_priv->save_input_dtd_2);
1380         }
1381
1382         for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++)
1383         {
1384                 u16  this_output = (1 << o);
1385                 if (sdvo_priv->caps.output_flags & this_output)
1386                 {
1387                         intel_sdvo_set_target_output(intel_encoder, this_output);
1388                         intel_sdvo_get_output_timing(intel_encoder,
1389                                                      &sdvo_priv->save_output_dtd[o]);
1390                 }
1391         }
1392         if (sdvo_priv->is_tv) {
1393                 /* XXX: Save TV format/enhancements. */
1394         }
1395
1396         sdvo_priv->save_SDVOX = I915_READ(sdvo_priv->sdvo_reg);
1397 }
1398
1399 static void intel_sdvo_restore(struct drm_connector *connector)
1400 {
1401         struct drm_device *dev = connector->dev;
1402         struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1403         struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1404         int o;
1405         int i;
1406         bool input1, input2;
1407         u8 status;
1408
1409         intel_sdvo_set_active_outputs(intel_encoder, 0);
1410
1411         for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++)
1412         {
1413                 u16  this_output = (1 << o);
1414                 if (sdvo_priv->caps.output_flags & this_output) {
1415                         intel_sdvo_set_target_output(intel_encoder, this_output);
1416                         intel_sdvo_set_output_timing(intel_encoder, &sdvo_priv->save_output_dtd[o]);
1417                 }
1418         }
1419
1420         if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
1421                 intel_sdvo_set_target_input(intel_encoder, true, false);
1422                 intel_sdvo_set_input_timing(intel_encoder, &sdvo_priv->save_input_dtd_1);
1423         }
1424
1425         if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
1426                 intel_sdvo_set_target_input(intel_encoder, false, true);
1427                 intel_sdvo_set_input_timing(intel_encoder, &sdvo_priv->save_input_dtd_2);
1428         }
1429
1430         intel_sdvo_set_clock_rate_mult(intel_encoder, sdvo_priv->save_sdvo_mult);
1431
1432         if (sdvo_priv->is_tv) {
1433                 /* XXX: Restore TV format/enhancements. */
1434         }
1435
1436         intel_sdvo_write_sdvox(intel_encoder, sdvo_priv->save_SDVOX);
1437
1438         if (sdvo_priv->save_SDVOX & SDVO_ENABLE)
1439         {
1440                 for (i = 0; i < 2; i++)
1441                         intel_wait_for_vblank(dev);
1442                 status = intel_sdvo_get_trained_inputs(intel_encoder, &input1, &input2);
1443                 if (status == SDVO_CMD_STATUS_SUCCESS && !input1)
1444                         DRM_DEBUG_KMS("First %s output reported failure to "
1445                                         "sync\n", SDVO_NAME(sdvo_priv));
1446         }
1447
1448         intel_sdvo_set_active_outputs(intel_encoder, sdvo_priv->save_active_outputs);
1449 }
1450
1451 static int intel_sdvo_mode_valid(struct drm_connector *connector,
1452                                  struct drm_display_mode *mode)
1453 {
1454         struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1455         struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1456
1457         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1458                 return MODE_NO_DBLESCAN;
1459
1460         if (sdvo_priv->pixel_clock_min > mode->clock)
1461                 return MODE_CLOCK_LOW;
1462
1463         if (sdvo_priv->pixel_clock_max < mode->clock)
1464                 return MODE_CLOCK_HIGH;
1465
1466         if (sdvo_priv->is_lvds == true) {
1467                 if (sdvo_priv->sdvo_lvds_fixed_mode == NULL)
1468                         return MODE_PANEL;
1469
1470                 if (mode->hdisplay > sdvo_priv->sdvo_lvds_fixed_mode->hdisplay)
1471                         return MODE_PANEL;
1472
1473                 if (mode->vdisplay > sdvo_priv->sdvo_lvds_fixed_mode->vdisplay)
1474                         return MODE_PANEL;
1475         }
1476
1477         return MODE_OK;
1478 }
1479
1480 static bool intel_sdvo_get_capabilities(struct intel_encoder *intel_encoder, struct intel_sdvo_caps *caps)
1481 {
1482         u8 status;
1483
1484         intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_DEVICE_CAPS, NULL, 0);
1485         status = intel_sdvo_read_response(intel_encoder, caps, sizeof(*caps));
1486         if (status != SDVO_CMD_STATUS_SUCCESS)
1487                 return false;
1488
1489         return true;
1490 }
1491
1492 struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB)
1493 {
1494         struct drm_connector *connector = NULL;
1495         struct intel_encoder *iout = NULL;
1496         struct intel_sdvo_priv *sdvo;
1497
1498         /* find the sdvo connector */
1499         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1500                 iout = to_intel_encoder(connector);
1501
1502                 if (iout->type != INTEL_OUTPUT_SDVO)
1503                         continue;
1504
1505                 sdvo = iout->dev_priv;
1506
1507                 if (sdvo->sdvo_reg == SDVOB && sdvoB)
1508                         return connector;
1509
1510                 if (sdvo->sdvo_reg == SDVOC && !sdvoB)
1511                         return connector;
1512
1513         }
1514
1515         return NULL;
1516 }
1517
1518 int intel_sdvo_supports_hotplug(struct drm_connector *connector)
1519 {
1520         u8 response[2];
1521         u8 status;
1522         struct intel_encoder *intel_encoder;
1523         DRM_DEBUG_KMS("\n");
1524
1525         if (!connector)
1526                 return 0;
1527
1528         intel_encoder = to_intel_encoder(connector);
1529
1530         intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1531         status = intel_sdvo_read_response(intel_encoder, &response, 2);
1532
1533         if (response[0] !=0)
1534                 return 1;
1535
1536         return 0;
1537 }
1538
1539 void intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
1540 {
1541         u8 response[2];
1542         u8 status;
1543         struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1544
1545         intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1546         intel_sdvo_read_response(intel_encoder, &response, 2);
1547
1548         if (on) {
1549                 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1550                 status = intel_sdvo_read_response(intel_encoder, &response, 2);
1551
1552                 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
1553         } else {
1554                 response[0] = 0;
1555                 response[1] = 0;
1556                 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
1557         }
1558
1559         intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1560         intel_sdvo_read_response(intel_encoder, &response, 2);
1561 }
1562
1563 static bool
1564 intel_sdvo_multifunc_encoder(struct intel_encoder *intel_encoder)
1565 {
1566         struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1567         int caps = 0;
1568
1569         if (sdvo_priv->caps.output_flags &
1570                 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1))
1571                 caps++;
1572         if (sdvo_priv->caps.output_flags &
1573                 (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1))
1574                 caps++;
1575         if (sdvo_priv->caps.output_flags &
1576                 (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_SVID1))
1577                 caps++;
1578         if (sdvo_priv->caps.output_flags &
1579                 (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_CVBS1))
1580                 caps++;
1581         if (sdvo_priv->caps.output_flags &
1582                 (SDVO_OUTPUT_YPRPB0 | SDVO_OUTPUT_YPRPB1))
1583                 caps++;
1584
1585         if (sdvo_priv->caps.output_flags &
1586                 (SDVO_OUTPUT_SCART0 | SDVO_OUTPUT_SCART1))
1587                 caps++;
1588
1589         if (sdvo_priv->caps.output_flags &
1590                 (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1))
1591                 caps++;
1592
1593         return (caps > 1);
1594 }
1595
1596 static struct drm_connector *
1597 intel_find_analog_connector(struct drm_device *dev)
1598 {
1599         struct drm_connector *connector;
1600         struct intel_encoder *intel_encoder;
1601
1602         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1603                 intel_encoder = to_intel_encoder(connector);
1604                 if (intel_encoder->type == INTEL_OUTPUT_ANALOG)
1605                         return connector;
1606         }
1607         return NULL;
1608 }
1609
1610 static int
1611 intel_analog_is_connected(struct drm_device *dev)
1612 {
1613         struct drm_connector *analog_connector;
1614         analog_connector = intel_find_analog_connector(dev);
1615
1616         if (!analog_connector)
1617                 return false;
1618
1619         if (analog_connector->funcs->detect(analog_connector) ==
1620                         connector_status_disconnected)
1621                 return false;
1622
1623         return true;
1624 }
1625
1626 enum drm_connector_status
1627 intel_sdvo_hdmi_sink_detect(struct drm_connector *connector, u16 response)
1628 {
1629         struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1630         struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1631         enum drm_connector_status status = connector_status_connected;
1632         struct edid *edid = NULL;
1633
1634         edid = drm_get_edid(&intel_encoder->base,
1635                             intel_encoder->ddc_bus);
1636
1637         /* This is only applied to SDVO cards with multiple outputs */
1638         if (edid == NULL && intel_sdvo_multifunc_encoder(intel_encoder)) {
1639                 uint8_t saved_ddc, temp_ddc;
1640                 saved_ddc = sdvo_priv->ddc_bus;
1641                 temp_ddc = sdvo_priv->ddc_bus >> 1;
1642                 /*
1643                  * Don't use the 1 as the argument of DDC bus switch to get
1644                  * the EDID. It is used for SDVO SPD ROM.
1645                  */
1646                 while(temp_ddc > 1) {
1647                         sdvo_priv->ddc_bus = temp_ddc;
1648                         edid = drm_get_edid(&intel_encoder->base,
1649                                 intel_encoder->ddc_bus);
1650                         if (edid) {
1651                                 /*
1652                                  * When we can get the EDID, maybe it is the
1653                                  * correct DDC bus. Update it.
1654                                  */
1655                                 sdvo_priv->ddc_bus = temp_ddc;
1656                                 break;
1657                         }
1658                         temp_ddc >>= 1;
1659                 }
1660                 if (edid == NULL)
1661                         sdvo_priv->ddc_bus = saved_ddc;
1662         }
1663         /* when there is no edid and no monitor is connected with VGA
1664          * port, try to use the CRT ddc to read the EDID for DVI-connector
1665          */
1666         if (edid == NULL &&
1667             sdvo_priv->analog_ddc_bus &&
1668             !intel_analog_is_connected(intel_encoder->base.dev))
1669                 edid = drm_get_edid(&intel_encoder->base,
1670                                     sdvo_priv->analog_ddc_bus);
1671         if (edid != NULL) {
1672                 /* Don't report the output as connected if it's a DVI-I
1673                  * connector with a non-digital EDID coming out.
1674                  */
1675                 if (response & (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) {
1676                         if (edid->input & DRM_EDID_INPUT_DIGITAL)
1677                                 sdvo_priv->is_hdmi =
1678                                         drm_detect_hdmi_monitor(edid);
1679                         else
1680                                 status = connector_status_disconnected;
1681                 }
1682
1683                 kfree(edid);
1684                 intel_encoder->base.display_info.raw_edid = NULL;
1685
1686         } else if (response & (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1))
1687                 status = connector_status_disconnected;
1688
1689         return status;
1690 }
1691
1692 static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector)
1693 {
1694         uint16_t response;
1695         u8 status;
1696         struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1697         struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1698
1699         intel_sdvo_write_cmd(intel_encoder,
1700                              SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0);
1701         if (sdvo_priv->is_tv) {
1702                 /* add 30ms delay when the output type is SDVO-TV */
1703                 mdelay(30);
1704         }
1705         status = intel_sdvo_read_response(intel_encoder, &response, 2);
1706
1707         DRM_DEBUG_KMS("SDVO response %d %d\n", response & 0xff, response >> 8);
1708
1709         if (status != SDVO_CMD_STATUS_SUCCESS)
1710                 return connector_status_unknown;
1711
1712         if (response == 0)
1713                 return connector_status_disconnected;
1714
1715         if (intel_sdvo_multifunc_encoder(intel_encoder) &&
1716                 sdvo_priv->attached_output != response) {
1717                 if (sdvo_priv->controlled_output != response &&
1718                         intel_sdvo_output_setup(intel_encoder, response) != true)
1719                         return connector_status_unknown;
1720                 sdvo_priv->attached_output = response;
1721         }
1722         return intel_sdvo_hdmi_sink_detect(connector, response);
1723 }
1724
1725 static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
1726 {
1727         struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1728         struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1729         int num_modes;
1730
1731         /* set the bus switch and get the modes */
1732         num_modes = intel_ddc_get_modes(intel_encoder);
1733
1734         /*
1735          * Mac mini hack.  On this device, the DVI-I connector shares one DDC
1736          * link between analog and digital outputs. So, if the regular SDVO
1737          * DDC fails, check to see if the analog output is disconnected, in
1738          * which case we'll look there for the digital DDC data.
1739          */
1740         if (num_modes == 0 &&
1741             sdvo_priv->analog_ddc_bus &&
1742             !intel_analog_is_connected(intel_encoder->base.dev)) {
1743                 struct i2c_adapter *digital_ddc_bus;
1744
1745                 /* Switch to the analog ddc bus and try that
1746                  */
1747                 digital_ddc_bus = intel_encoder->ddc_bus;
1748                 intel_encoder->ddc_bus = sdvo_priv->analog_ddc_bus;
1749
1750                 (void) intel_ddc_get_modes(intel_encoder);
1751
1752                 intel_encoder->ddc_bus = digital_ddc_bus;
1753         }
1754 }
1755
1756 /*
1757  * Set of SDVO TV modes.
1758  * Note!  This is in reply order (see loop in get_tv_modes).
1759  * XXX: all 60Hz refresh?
1760  */
1761 struct drm_display_mode sdvo_tv_modes[] = {
1762         { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1763                    416, 0, 200, 201, 232, 233, 0,
1764                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1765         { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1766                    416, 0, 240, 241, 272, 273, 0,
1767                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1768         { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1769                    496, 0, 300, 301, 332, 333, 0,
1770                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1771         { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1772                    736, 0, 350, 351, 382, 383, 0,
1773                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1774         { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1775                    736, 0, 400, 401, 432, 433, 0,
1776                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1777         { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1778                    736, 0, 480, 481, 512, 513, 0,
1779                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1780         { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1781                    800, 0, 480, 481, 512, 513, 0,
1782                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1783         { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1784                    800, 0, 576, 577, 608, 609, 0,
1785                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1786         { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1787                    816, 0, 350, 351, 382, 383, 0,
1788                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1789         { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1790                    816, 0, 400, 401, 432, 433, 0,
1791                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1792         { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1793                    816, 0, 480, 481, 512, 513, 0,
1794                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1795         { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1796                    816, 0, 540, 541, 572, 573, 0,
1797                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1798         { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1799                    816, 0, 576, 577, 608, 609, 0,
1800                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1801         { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1802                    864, 0, 576, 577, 608, 609, 0,
1803                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1804         { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1805                    896, 0, 600, 601, 632, 633, 0,
1806                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1807         { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1808                    928, 0, 624, 625, 656, 657, 0,
1809                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1810         { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1811                    1016, 0, 766, 767, 798, 799, 0,
1812                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1813         { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1814                    1120, 0, 768, 769, 800, 801, 0,
1815                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1816         { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1817                    1376, 0, 1024, 1025, 1056, 1057, 0,
1818                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1819 };
1820
1821 static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1822 {
1823         struct intel_encoder *output = to_intel_encoder(connector);
1824         struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1825         struct intel_sdvo_sdtv_resolution_request tv_res;
1826         uint32_t reply = 0, format_map = 0;
1827         int i;
1828         uint8_t status;
1829
1830
1831         /* Read the list of supported input resolutions for the selected TV
1832          * format.
1833          */
1834         for (i = 0; i < TV_FORMAT_NUM; i++)
1835                 if (tv_format_names[i] ==  sdvo_priv->tv_format_name)
1836                         break;
1837
1838         format_map = (1 << i);
1839         memcpy(&tv_res, &format_map,
1840                sizeof(struct intel_sdvo_sdtv_resolution_request) >
1841                sizeof(format_map) ? sizeof(format_map) :
1842                sizeof(struct intel_sdvo_sdtv_resolution_request));
1843
1844         intel_sdvo_set_target_output(output, sdvo_priv->controlled_output);
1845
1846         intel_sdvo_write_cmd(output, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
1847                              &tv_res, sizeof(tv_res));
1848         status = intel_sdvo_read_response(output, &reply, 3);
1849         if (status != SDVO_CMD_STATUS_SUCCESS)
1850                 return;
1851
1852         for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
1853                 if (reply & (1 << i)) {
1854                         struct drm_display_mode *nmode;
1855                         nmode = drm_mode_duplicate(connector->dev,
1856                                         &sdvo_tv_modes[i]);
1857                         if (nmode)
1858                                 drm_mode_probed_add(connector, nmode);
1859                 }
1860
1861 }
1862
1863 static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1864 {
1865         struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1866         struct drm_i915_private *dev_priv = connector->dev->dev_private;
1867         struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1868         struct drm_display_mode *newmode;
1869
1870         /*
1871          * Attempt to get the mode list from DDC.
1872          * Assume that the preferred modes are
1873          * arranged in priority order.
1874          */
1875         intel_ddc_get_modes(intel_encoder);
1876         if (list_empty(&connector->probed_modes) == false)
1877                 goto end;
1878
1879         /* Fetch modes from VBT */
1880         if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
1881                 newmode = drm_mode_duplicate(connector->dev,
1882                                              dev_priv->sdvo_lvds_vbt_mode);
1883                 if (newmode != NULL) {
1884                         /* Guarantee the mode is preferred */
1885                         newmode->type = (DRM_MODE_TYPE_PREFERRED |
1886                                          DRM_MODE_TYPE_DRIVER);
1887                         drm_mode_probed_add(connector, newmode);
1888                 }
1889         }
1890
1891 end:
1892         list_for_each_entry(newmode, &connector->probed_modes, head) {
1893                 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1894                         sdvo_priv->sdvo_lvds_fixed_mode =
1895                                 drm_mode_duplicate(connector->dev, newmode);
1896                         break;
1897                 }
1898         }
1899
1900 }
1901
1902 static int intel_sdvo_get_modes(struct drm_connector *connector)
1903 {
1904         struct intel_encoder *output = to_intel_encoder(connector);
1905         struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1906
1907         if (sdvo_priv->is_tv)
1908                 intel_sdvo_get_tv_modes(connector);
1909         else if (sdvo_priv->is_lvds == true)
1910                 intel_sdvo_get_lvds_modes(connector);
1911         else
1912                 intel_sdvo_get_ddc_modes(connector);
1913
1914         if (list_empty(&connector->probed_modes))
1915                 return 0;
1916         return 1;
1917 }
1918
1919 static
1920 void intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
1921 {
1922         struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1923         struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1924         struct drm_device *dev = connector->dev;
1925
1926         if (sdvo_priv->is_tv) {
1927                 if (sdvo_priv->left_property)
1928                         drm_property_destroy(dev, sdvo_priv->left_property);
1929                 if (sdvo_priv->right_property)
1930                         drm_property_destroy(dev, sdvo_priv->right_property);
1931                 if (sdvo_priv->top_property)
1932                         drm_property_destroy(dev, sdvo_priv->top_property);
1933                 if (sdvo_priv->bottom_property)
1934                         drm_property_destroy(dev, sdvo_priv->bottom_property);
1935                 if (sdvo_priv->hpos_property)
1936                         drm_property_destroy(dev, sdvo_priv->hpos_property);
1937                 if (sdvo_priv->vpos_property)
1938                         drm_property_destroy(dev, sdvo_priv->vpos_property);
1939         }
1940         if (sdvo_priv->is_tv) {
1941                 if (sdvo_priv->saturation_property)
1942                         drm_property_destroy(dev,
1943                                         sdvo_priv->saturation_property);
1944                 if (sdvo_priv->contrast_property)
1945                         drm_property_destroy(dev,
1946                                         sdvo_priv->contrast_property);
1947                 if (sdvo_priv->hue_property)
1948                         drm_property_destroy(dev, sdvo_priv->hue_property);
1949         }
1950         if (sdvo_priv->is_tv || sdvo_priv->is_lvds) {
1951                 if (sdvo_priv->brightness_property)
1952                         drm_property_destroy(dev,
1953                                         sdvo_priv->brightness_property);
1954         }
1955         return;
1956 }
1957
1958 static void intel_sdvo_destroy(struct drm_connector *connector)
1959 {
1960         struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1961         struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1962
1963         if (intel_encoder->i2c_bus)
1964                 intel_i2c_destroy(intel_encoder->i2c_bus);
1965         if (intel_encoder->ddc_bus)
1966                 intel_i2c_destroy(intel_encoder->ddc_bus);
1967         if (sdvo_priv->analog_ddc_bus)
1968                 intel_i2c_destroy(sdvo_priv->analog_ddc_bus);
1969
1970         if (sdvo_priv->sdvo_lvds_fixed_mode != NULL)
1971                 drm_mode_destroy(connector->dev,
1972                                  sdvo_priv->sdvo_lvds_fixed_mode);
1973
1974         if (sdvo_priv->tv_format_property)
1975                 drm_property_destroy(connector->dev,
1976                                      sdvo_priv->tv_format_property);
1977
1978         if (sdvo_priv->is_tv || sdvo_priv->is_lvds)
1979                 intel_sdvo_destroy_enhance_property(connector);
1980
1981         drm_sysfs_connector_remove(connector);
1982         drm_connector_cleanup(connector);
1983
1984         kfree(intel_encoder);
1985 }
1986
1987 static int
1988 intel_sdvo_set_property(struct drm_connector *connector,
1989                         struct drm_property *property,
1990                         uint64_t val)
1991 {
1992         struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1993         struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1994         struct drm_encoder *encoder = &intel_encoder->enc;
1995         struct drm_crtc *crtc = encoder->crtc;
1996         int ret = 0;
1997         bool changed = false;
1998         uint8_t cmd, status;
1999         uint16_t temp_value;
2000
2001         ret = drm_connector_property_set_value(connector, property, val);
2002         if (ret < 0)
2003                 goto out;
2004
2005         if (property == sdvo_priv->tv_format_property) {
2006                 if (val >= TV_FORMAT_NUM) {
2007                         ret = -EINVAL;
2008                         goto out;
2009                 }
2010                 if (sdvo_priv->tv_format_name ==
2011                     sdvo_priv->tv_format_supported[val])
2012                         goto out;
2013
2014                 sdvo_priv->tv_format_name = sdvo_priv->tv_format_supported[val];
2015                 changed = true;
2016         }
2017
2018         if (sdvo_priv->is_tv || sdvo_priv->is_lvds) {
2019                 cmd = 0;
2020                 temp_value = val;
2021                 if (sdvo_priv->left_property == property) {
2022                         drm_connector_property_set_value(connector,
2023                                 sdvo_priv->right_property, val);
2024                         if (sdvo_priv->left_margin == temp_value)
2025                                 goto out;
2026
2027                         sdvo_priv->left_margin = temp_value;
2028                         sdvo_priv->right_margin = temp_value;
2029                         temp_value = sdvo_priv->max_hscan -
2030                                         sdvo_priv->left_margin;
2031                         cmd = SDVO_CMD_SET_OVERSCAN_H;
2032                 } else if (sdvo_priv->right_property == property) {
2033                         drm_connector_property_set_value(connector,
2034                                 sdvo_priv->left_property, val);
2035                         if (sdvo_priv->right_margin == temp_value)
2036                                 goto out;
2037
2038                         sdvo_priv->left_margin = temp_value;
2039                         sdvo_priv->right_margin = temp_value;
2040                         temp_value = sdvo_priv->max_hscan -
2041                                 sdvo_priv->left_margin;
2042                         cmd = SDVO_CMD_SET_OVERSCAN_H;
2043                 } else if (sdvo_priv->top_property == property) {
2044                         drm_connector_property_set_value(connector,
2045                                 sdvo_priv->bottom_property, val);
2046                         if (sdvo_priv->top_margin == temp_value)
2047                                 goto out;
2048
2049                         sdvo_priv->top_margin = temp_value;
2050                         sdvo_priv->bottom_margin = temp_value;
2051                         temp_value = sdvo_priv->max_vscan -
2052                                         sdvo_priv->top_margin;
2053                         cmd = SDVO_CMD_SET_OVERSCAN_V;
2054                 } else if (sdvo_priv->bottom_property == property) {
2055                         drm_connector_property_set_value(connector,
2056                                 sdvo_priv->top_property, val);
2057                         if (sdvo_priv->bottom_margin == temp_value)
2058                                 goto out;
2059                         sdvo_priv->top_margin = temp_value;
2060                         sdvo_priv->bottom_margin = temp_value;
2061                         temp_value = sdvo_priv->max_vscan -
2062                                         sdvo_priv->top_margin;
2063                         cmd = SDVO_CMD_SET_OVERSCAN_V;
2064                 } else if (sdvo_priv->hpos_property == property) {
2065                         if (sdvo_priv->cur_hpos == temp_value)
2066                                 goto out;
2067
2068                         cmd = SDVO_CMD_SET_POSITION_H;
2069                         sdvo_priv->cur_hpos = temp_value;
2070                 } else if (sdvo_priv->vpos_property == property) {
2071                         if (sdvo_priv->cur_vpos == temp_value)
2072                                 goto out;
2073
2074                         cmd = SDVO_CMD_SET_POSITION_V;
2075                         sdvo_priv->cur_vpos = temp_value;
2076                 } else if (sdvo_priv->saturation_property == property) {
2077                         if (sdvo_priv->cur_saturation == temp_value)
2078                                 goto out;
2079
2080                         cmd = SDVO_CMD_SET_SATURATION;
2081                         sdvo_priv->cur_saturation = temp_value;
2082                 } else if (sdvo_priv->contrast_property == property) {
2083                         if (sdvo_priv->cur_contrast == temp_value)
2084                                 goto out;
2085
2086                         cmd = SDVO_CMD_SET_CONTRAST;
2087                         sdvo_priv->cur_contrast = temp_value;
2088                 } else if (sdvo_priv->hue_property == property) {
2089                         if (sdvo_priv->cur_hue == temp_value)
2090                                 goto out;
2091
2092                         cmd = SDVO_CMD_SET_HUE;
2093                         sdvo_priv->cur_hue = temp_value;
2094                 } else if (sdvo_priv->brightness_property == property) {
2095                         if (sdvo_priv->cur_brightness == temp_value)
2096                                 goto out;
2097
2098                         cmd = SDVO_CMD_SET_BRIGHTNESS;
2099                         sdvo_priv->cur_brightness = temp_value;
2100                 }
2101                 if (cmd) {
2102                         intel_sdvo_write_cmd(intel_encoder, cmd, &temp_value, 2);
2103                         status = intel_sdvo_read_response(intel_encoder,
2104                                                                 NULL, 0);
2105                         if (status != SDVO_CMD_STATUS_SUCCESS) {
2106                                 DRM_DEBUG_KMS("Incorrect SDVO command \n");
2107                                 return -EINVAL;
2108                         }
2109                         changed = true;
2110                 }
2111         }
2112         if (changed && crtc)
2113                 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
2114                                 crtc->y, crtc->fb);
2115 out:
2116         return ret;
2117 }
2118
2119 static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
2120         .dpms = intel_sdvo_dpms,
2121         .mode_fixup = intel_sdvo_mode_fixup,
2122         .prepare = intel_encoder_prepare,
2123         .mode_set = intel_sdvo_mode_set,
2124         .commit = intel_encoder_commit,
2125 };
2126
2127 static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
2128         .dpms = drm_helper_connector_dpms,
2129         .save = intel_sdvo_save,
2130         .restore = intel_sdvo_restore,
2131         .detect = intel_sdvo_detect,
2132         .fill_modes = drm_helper_probe_single_connector_modes,
2133         .set_property = intel_sdvo_set_property,
2134         .destroy = intel_sdvo_destroy,
2135 };
2136
2137 static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
2138         .get_modes = intel_sdvo_get_modes,
2139         .mode_valid = intel_sdvo_mode_valid,
2140         .best_encoder = intel_best_encoder,
2141 };
2142
2143 static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
2144 {
2145         drm_encoder_cleanup(encoder);
2146 }
2147
2148 static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
2149         .destroy = intel_sdvo_enc_destroy,
2150 };
2151
2152
2153 /**
2154  * Choose the appropriate DDC bus for control bus switch command for this
2155  * SDVO output based on the controlled output.
2156  *
2157  * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
2158  * outputs, then LVDS outputs.
2159  */
2160 static void
2161 intel_sdvo_select_ddc_bus(struct intel_sdvo_priv *dev_priv)
2162 {
2163         uint16_t mask = 0;
2164         unsigned int num_bits;
2165
2166         /* Make a mask of outputs less than or equal to our own priority in the
2167          * list.
2168          */
2169         switch (dev_priv->controlled_output) {
2170         case SDVO_OUTPUT_LVDS1:
2171                 mask |= SDVO_OUTPUT_LVDS1;
2172         case SDVO_OUTPUT_LVDS0:
2173                 mask |= SDVO_OUTPUT_LVDS0;
2174         case SDVO_OUTPUT_TMDS1:
2175                 mask |= SDVO_OUTPUT_TMDS1;
2176         case SDVO_OUTPUT_TMDS0:
2177                 mask |= SDVO_OUTPUT_TMDS0;
2178         case SDVO_OUTPUT_RGB1:
2179                 mask |= SDVO_OUTPUT_RGB1;
2180         case SDVO_OUTPUT_RGB0:
2181                 mask |= SDVO_OUTPUT_RGB0;
2182                 break;
2183         }
2184
2185         /* Count bits to find what number we are in the priority list. */
2186         mask &= dev_priv->caps.output_flags;
2187         num_bits = hweight16(mask);
2188         if (num_bits > 3) {
2189                 /* if more than 3 outputs, default to DDC bus 3 for now */
2190                 num_bits = 3;
2191         }
2192
2193         /* Corresponds to SDVO_CONTROL_BUS_DDCx */
2194         dev_priv->ddc_bus = 1 << num_bits;
2195 }
2196
2197 static bool
2198 intel_sdvo_get_digital_encoding_mode(struct intel_encoder *output)
2199 {
2200         struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
2201         uint8_t status;
2202
2203         intel_sdvo_set_target_output(output, sdvo_priv->controlled_output);
2204
2205         intel_sdvo_write_cmd(output, SDVO_CMD_GET_ENCODE, NULL, 0);
2206         status = intel_sdvo_read_response(output, &sdvo_priv->is_hdmi, 1);
2207         if (status != SDVO_CMD_STATUS_SUCCESS)
2208                 return false;
2209         return true;
2210 }
2211
2212 static struct intel_encoder *
2213 intel_sdvo_chan_to_intel_encoder(struct intel_i2c_chan *chan)
2214 {
2215         struct drm_device *dev = chan->drm_dev;
2216         struct drm_connector *connector;
2217         struct intel_encoder *intel_encoder = NULL;
2218
2219         list_for_each_entry(connector,
2220                         &dev->mode_config.connector_list, head) {
2221                 if (to_intel_encoder(connector)->ddc_bus == &chan->adapter) {
2222                         intel_encoder = to_intel_encoder(connector);
2223                         break;
2224                 }
2225         }
2226         return intel_encoder;
2227 }
2228
2229 static int intel_sdvo_master_xfer(struct i2c_adapter *i2c_adap,
2230                                   struct i2c_msg msgs[], int num)
2231 {
2232         struct intel_encoder *intel_encoder;
2233         struct intel_sdvo_priv *sdvo_priv;
2234         struct i2c_algo_bit_data *algo_data;
2235         const struct i2c_algorithm *algo;
2236
2237         algo_data = (struct i2c_algo_bit_data *)i2c_adap->algo_data;
2238         intel_encoder =
2239                 intel_sdvo_chan_to_intel_encoder(
2240                                 (struct intel_i2c_chan *)(algo_data->data));
2241         if (intel_encoder == NULL)
2242                 return -EINVAL;
2243
2244         sdvo_priv = intel_encoder->dev_priv;
2245         algo = intel_encoder->i2c_bus->algo;
2246
2247         intel_sdvo_set_control_bus_switch(intel_encoder, sdvo_priv->ddc_bus);
2248         return algo->master_xfer(i2c_adap, msgs, num);
2249 }
2250
2251 static struct i2c_algorithm intel_sdvo_i2c_bit_algo = {
2252         .master_xfer    = intel_sdvo_master_xfer,
2253 };
2254
2255 static u8
2256 intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg)
2257 {
2258         struct drm_i915_private *dev_priv = dev->dev_private;
2259         struct sdvo_device_mapping *my_mapping, *other_mapping;
2260
2261         if (sdvo_reg == SDVOB) {
2262                 my_mapping = &dev_priv->sdvo_mappings[0];
2263                 other_mapping = &dev_priv->sdvo_mappings[1];
2264         } else {
2265                 my_mapping = &dev_priv->sdvo_mappings[1];
2266                 other_mapping = &dev_priv->sdvo_mappings[0];
2267         }
2268
2269         /* If the BIOS described our SDVO device, take advantage of it. */
2270         if (my_mapping->slave_addr)
2271                 return my_mapping->slave_addr;
2272
2273         /* If the BIOS only described a different SDVO device, use the
2274          * address that it isn't using.
2275          */
2276         if (other_mapping->slave_addr) {
2277                 if (other_mapping->slave_addr == 0x70)
2278                         return 0x72;
2279                 else
2280                         return 0x70;
2281         }
2282
2283         /* No SDVO device info is found for another DVO port,
2284          * so use mapping assumption we had before BIOS parsing.
2285          */
2286         if (sdvo_reg == SDVOB)
2287                 return 0x70;
2288         else
2289                 return 0x72;
2290 }
2291
2292 static int intel_sdvo_bad_tv_callback(const struct dmi_system_id *id)
2293 {
2294         DRM_DEBUG_KMS("Ignoring bad SDVO TV connector for %s\n", id->ident);
2295         return 1;
2296 }
2297
2298 static struct dmi_system_id intel_sdvo_bad_tv[] = {
2299         {
2300                 .callback = intel_sdvo_bad_tv_callback,
2301                 .ident = "IntelG45/ICH10R/DME1737",
2302                 .matches = {
2303                         DMI_MATCH(DMI_SYS_VENDOR, "IBM CORPORATION"),
2304                         DMI_MATCH(DMI_PRODUCT_NAME, "4800784"),
2305                 },
2306         },
2307
2308         { }     /* terminating entry */
2309 };
2310
2311 static bool
2312 intel_sdvo_output_setup(struct intel_encoder *intel_encoder, uint16_t flags)
2313 {
2314         struct drm_connector *connector = &intel_encoder->base;
2315         struct drm_encoder *encoder = &intel_encoder->enc;
2316         struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
2317         bool ret = true, registered = false;
2318
2319         sdvo_priv->is_tv = false;
2320         intel_encoder->needs_tv_clock = false;
2321         sdvo_priv->is_lvds = false;
2322
2323         if (device_is_registered(&connector->kdev)) {
2324                 drm_sysfs_connector_remove(connector);
2325                 registered = true;
2326         }
2327
2328         if (flags &
2329             (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) {
2330                 if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_TMDS0)
2331                         sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS0;
2332                 else
2333                         sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS1;
2334
2335                 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2336                 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2337
2338                 if (intel_sdvo_get_supp_encode(intel_encoder,
2339                                                &sdvo_priv->encode) &&
2340                     intel_sdvo_get_digital_encoding_mode(intel_encoder) &&
2341                     sdvo_priv->is_hdmi) {
2342                         /* enable hdmi encoding mode if supported */
2343                         intel_sdvo_set_encode(intel_encoder, SDVO_ENCODE_HDMI);
2344                         intel_sdvo_set_colorimetry(intel_encoder,
2345                                                    SDVO_COLORIMETRY_RGB256);
2346                         connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
2347                         intel_encoder->clone_mask =
2348                                         (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2349                                         (1 << INTEL_ANALOG_CLONE_BIT);
2350                 }
2351         } else if ((flags & SDVO_OUTPUT_SVID0) &&
2352                    !dmi_check_system(intel_sdvo_bad_tv)) {
2353
2354                 sdvo_priv->controlled_output = SDVO_OUTPUT_SVID0;
2355                 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2356                 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
2357                 sdvo_priv->is_tv = true;
2358                 intel_encoder->needs_tv_clock = true;
2359                 intel_encoder->clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
2360         } else if (flags & SDVO_OUTPUT_RGB0) {
2361
2362                 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB0;
2363                 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2364                 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2365                 intel_encoder->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2366                                         (1 << INTEL_ANALOG_CLONE_BIT);
2367         } else if (flags & SDVO_OUTPUT_RGB1) {
2368
2369                 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB1;
2370                 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2371                 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2372                 intel_encoder->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2373                                         (1 << INTEL_ANALOG_CLONE_BIT);
2374         } else if (flags & SDVO_OUTPUT_CVBS0) {
2375
2376                 sdvo_priv->controlled_output = SDVO_OUTPUT_CVBS0;
2377                 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2378                 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
2379                 sdvo_priv->is_tv = true;
2380                 intel_encoder->needs_tv_clock = true;
2381                 intel_encoder->clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
2382         } else if (flags & SDVO_OUTPUT_LVDS0) {
2383
2384                 sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS0;
2385                 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2386                 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2387                 sdvo_priv->is_lvds = true;
2388                 intel_encoder->clone_mask = (1 << INTEL_ANALOG_CLONE_BIT) |
2389                                         (1 << INTEL_SDVO_LVDS_CLONE_BIT);
2390         } else if (flags & SDVO_OUTPUT_LVDS1) {
2391
2392                 sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS1;
2393                 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2394                 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2395                 sdvo_priv->is_lvds = true;
2396                 intel_encoder->clone_mask = (1 << INTEL_ANALOG_CLONE_BIT) |
2397                                         (1 << INTEL_SDVO_LVDS_CLONE_BIT);
2398         } else {
2399
2400                 unsigned char bytes[2];
2401
2402                 sdvo_priv->controlled_output = 0;
2403                 memcpy(bytes, &sdvo_priv->caps.output_flags, 2);
2404                 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
2405                               SDVO_NAME(sdvo_priv),
2406                               bytes[0], bytes[1]);
2407                 ret = false;
2408         }
2409         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
2410
2411         if (ret && registered)
2412                 ret = drm_sysfs_connector_add(connector) == 0 ? true : false;
2413
2414
2415         return ret;
2416
2417 }
2418
2419 static void intel_sdvo_tv_create_property(struct drm_connector *connector)
2420 {
2421       struct intel_encoder *intel_encoder = to_intel_encoder(connector);
2422         struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
2423         struct intel_sdvo_tv_format format;
2424         uint32_t format_map, i;
2425         uint8_t status;
2426
2427         intel_sdvo_set_target_output(intel_encoder,
2428                                      sdvo_priv->controlled_output);
2429
2430         intel_sdvo_write_cmd(intel_encoder,
2431                              SDVO_CMD_GET_SUPPORTED_TV_FORMATS, NULL, 0);
2432         status = intel_sdvo_read_response(intel_encoder,
2433                                           &format, sizeof(format));
2434         if (status != SDVO_CMD_STATUS_SUCCESS)
2435                 return;
2436
2437         memcpy(&format_map, &format, sizeof(format) > sizeof(format_map) ?
2438                sizeof(format_map) : sizeof(format));
2439
2440         if (format_map == 0)
2441                 return;
2442
2443         sdvo_priv->format_supported_num = 0;
2444         for (i = 0 ; i < TV_FORMAT_NUM; i++)
2445                 if (format_map & (1 << i)) {
2446                         sdvo_priv->tv_format_supported
2447                         [sdvo_priv->format_supported_num++] =
2448                         tv_format_names[i];
2449                 }
2450
2451
2452         sdvo_priv->tv_format_property =
2453                         drm_property_create(
2454                                 connector->dev, DRM_MODE_PROP_ENUM,
2455                                 "mode", sdvo_priv->format_supported_num);
2456
2457         for (i = 0; i < sdvo_priv->format_supported_num; i++)
2458                 drm_property_add_enum(
2459                                 sdvo_priv->tv_format_property, i,
2460                                 i, sdvo_priv->tv_format_supported[i]);
2461
2462         sdvo_priv->tv_format_name = sdvo_priv->tv_format_supported[0];
2463         drm_connector_attach_property(
2464                         connector, sdvo_priv->tv_format_property, 0);
2465
2466 }
2467
2468 static void intel_sdvo_create_enhance_property(struct drm_connector *connector)
2469 {
2470         struct intel_encoder *intel_encoder = to_intel_encoder(connector);
2471         struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
2472         struct intel_sdvo_enhancements_reply sdvo_data;
2473         struct drm_device *dev = connector->dev;
2474         uint8_t status;
2475         uint16_t response, data_value[2];
2476
2477         intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2478                                                 NULL, 0);
2479         status = intel_sdvo_read_response(intel_encoder, &sdvo_data,
2480                                         sizeof(sdvo_data));
2481         if (status != SDVO_CMD_STATUS_SUCCESS) {
2482                 DRM_DEBUG_KMS(" incorrect response is returned\n");
2483                 return;
2484         }
2485         response = *((uint16_t *)&sdvo_data);
2486         if (!response) {
2487                 DRM_DEBUG_KMS("No enhancement is supported\n");
2488                 return;
2489         }
2490         if (sdvo_priv->is_tv) {
2491                 /* when horizontal overscan is supported, Add the left/right
2492                  * property
2493                  */
2494                 if (sdvo_data.overscan_h) {
2495                         intel_sdvo_write_cmd(intel_encoder,
2496                                 SDVO_CMD_GET_MAX_OVERSCAN_H, NULL, 0);
2497                         status = intel_sdvo_read_response(intel_encoder,
2498                                 &data_value, 4);
2499                         if (status != SDVO_CMD_STATUS_SUCCESS) {
2500                                 DRM_DEBUG_KMS("Incorrect SDVO max "
2501                                                 "h_overscan\n");
2502                                 return;
2503                         }
2504                         intel_sdvo_write_cmd(intel_encoder,
2505                                 SDVO_CMD_GET_OVERSCAN_H, NULL, 0);
2506                         status = intel_sdvo_read_response(intel_encoder,
2507                                 &response, 2);
2508                         if (status != SDVO_CMD_STATUS_SUCCESS) {
2509                                 DRM_DEBUG_KMS("Incorrect SDVO h_overscan\n");
2510                                 return;
2511                         }
2512                         sdvo_priv->max_hscan = data_value[0];
2513                         sdvo_priv->left_margin = data_value[0] - response;
2514                         sdvo_priv->right_margin = sdvo_priv->left_margin;
2515                         sdvo_priv->left_property =
2516                                 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2517                                                 "left_margin", 2);
2518                         sdvo_priv->left_property->values[0] = 0;
2519                         sdvo_priv->left_property->values[1] = data_value[0];
2520                         drm_connector_attach_property(connector,
2521                                                 sdvo_priv->left_property,
2522                                                 sdvo_priv->left_margin);
2523                         sdvo_priv->right_property =
2524                                 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2525                                                 "right_margin", 2);
2526                         sdvo_priv->right_property->values[0] = 0;
2527                         sdvo_priv->right_property->values[1] = data_value[0];
2528                         drm_connector_attach_property(connector,
2529                                                 sdvo_priv->right_property,
2530                                                 sdvo_priv->right_margin);
2531                         DRM_DEBUG_KMS("h_overscan: max %d, "
2532                                         "default %d, current %d\n",
2533                                         data_value[0], data_value[1], response);
2534                 }
2535                 if (sdvo_data.overscan_v) {
2536                         intel_sdvo_write_cmd(intel_encoder,
2537                                 SDVO_CMD_GET_MAX_OVERSCAN_V, NULL, 0);
2538                         status = intel_sdvo_read_response(intel_encoder,
2539                                 &data_value, 4);
2540                         if (status != SDVO_CMD_STATUS_SUCCESS) {
2541                                 DRM_DEBUG_KMS("Incorrect SDVO max "
2542                                                 "v_overscan\n");
2543                                 return;
2544                         }
2545                         intel_sdvo_write_cmd(intel_encoder,
2546                                 SDVO_CMD_GET_OVERSCAN_V, NULL, 0);
2547                         status = intel_sdvo_read_response(intel_encoder,
2548                                 &response, 2);
2549                         if (status != SDVO_CMD_STATUS_SUCCESS) {
2550                                 DRM_DEBUG_KMS("Incorrect SDVO v_overscan\n");
2551                                 return;
2552                         }
2553                         sdvo_priv->max_vscan = data_value[0];
2554                         sdvo_priv->top_margin = data_value[0] - response;
2555                         sdvo_priv->bottom_margin = sdvo_priv->top_margin;
2556                         sdvo_priv->top_property =
2557                                 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2558                                                 "top_margin", 2);
2559                         sdvo_priv->top_property->values[0] = 0;
2560                         sdvo_priv->top_property->values[1] = data_value[0];
2561                         drm_connector_attach_property(connector,
2562                                                 sdvo_priv->top_property,
2563                                                 sdvo_priv->top_margin);
2564                         sdvo_priv->bottom_property =
2565                                 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2566                                                 "bottom_margin", 2);
2567                         sdvo_priv->bottom_property->values[0] = 0;
2568                         sdvo_priv->bottom_property->values[1] = data_value[0];
2569                         drm_connector_attach_property(connector,
2570                                                 sdvo_priv->bottom_property,
2571                                                 sdvo_priv->bottom_margin);
2572                         DRM_DEBUG_KMS("v_overscan: max %d, "
2573                                         "default %d, current %d\n",
2574                                         data_value[0], data_value[1], response);
2575                 }
2576                 if (sdvo_data.position_h) {
2577                         intel_sdvo_write_cmd(intel_encoder,
2578                                 SDVO_CMD_GET_MAX_POSITION_H, NULL, 0);
2579                         status = intel_sdvo_read_response(intel_encoder,
2580                                 &data_value, 4);
2581                         if (status != SDVO_CMD_STATUS_SUCCESS) {
2582                                 DRM_DEBUG_KMS("Incorrect SDVO Max h_pos\n");
2583                                 return;
2584                         }
2585                         intel_sdvo_write_cmd(intel_encoder,
2586                                 SDVO_CMD_GET_POSITION_H, NULL, 0);
2587                         status = intel_sdvo_read_response(intel_encoder,
2588                                 &response, 2);
2589                         if (status != SDVO_CMD_STATUS_SUCCESS) {
2590                                 DRM_DEBUG_KMS("Incorrect SDVO get h_postion\n");
2591                                 return;
2592                         }
2593                         sdvo_priv->max_hpos = data_value[0];
2594                         sdvo_priv->cur_hpos = response;
2595                         sdvo_priv->hpos_property =
2596                                 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2597                                                 "hpos", 2);
2598                         sdvo_priv->hpos_property->values[0] = 0;
2599                         sdvo_priv->hpos_property->values[1] = data_value[0];
2600                         drm_connector_attach_property(connector,
2601                                                 sdvo_priv->hpos_property,
2602                                                 sdvo_priv->cur_hpos);
2603                         DRM_DEBUG_KMS("h_position: max %d, "
2604                                         "default %d, current %d\n",
2605                                         data_value[0], data_value[1], response);
2606                 }
2607                 if (sdvo_data.position_v) {
2608                         intel_sdvo_write_cmd(intel_encoder,
2609                                 SDVO_CMD_GET_MAX_POSITION_V, NULL, 0);
2610                         status = intel_sdvo_read_response(intel_encoder,
2611                                 &data_value, 4);
2612                         if (status != SDVO_CMD_STATUS_SUCCESS) {
2613                                 DRM_DEBUG_KMS("Incorrect SDVO Max v_pos\n");
2614                                 return;
2615                         }
2616                         intel_sdvo_write_cmd(intel_encoder,
2617                                 SDVO_CMD_GET_POSITION_V, NULL, 0);
2618                         status = intel_sdvo_read_response(intel_encoder,
2619                                 &response, 2);
2620                         if (status != SDVO_CMD_STATUS_SUCCESS) {
2621                                 DRM_DEBUG_KMS("Incorrect SDVO get v_postion\n");
2622                                 return;
2623                         }
2624                         sdvo_priv->max_vpos = data_value[0];
2625                         sdvo_priv->cur_vpos = response;
2626                         sdvo_priv->vpos_property =
2627                                 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2628                                                 "vpos", 2);
2629                         sdvo_priv->vpos_property->values[0] = 0;
2630                         sdvo_priv->vpos_property->values[1] = data_value[0];
2631                         drm_connector_attach_property(connector,
2632                                                 sdvo_priv->vpos_property,
2633                                                 sdvo_priv->cur_vpos);
2634                         DRM_DEBUG_KMS("v_position: max %d, "
2635                                         "default %d, current %d\n",
2636                                         data_value[0], data_value[1], response);
2637                 }
2638         }
2639         if (sdvo_priv->is_tv) {
2640                 if (sdvo_data.saturation) {
2641                         intel_sdvo_write_cmd(intel_encoder,
2642                                 SDVO_CMD_GET_MAX_SATURATION, NULL, 0);
2643                         status = intel_sdvo_read_response(intel_encoder,
2644                                 &data_value, 4);
2645                         if (status != SDVO_CMD_STATUS_SUCCESS) {
2646                                 DRM_DEBUG_KMS("Incorrect SDVO Max sat\n");
2647                                 return;
2648                         }
2649                         intel_sdvo_write_cmd(intel_encoder,
2650                                 SDVO_CMD_GET_SATURATION, NULL, 0);
2651                         status = intel_sdvo_read_response(intel_encoder,
2652                                 &response, 2);
2653                         if (status != SDVO_CMD_STATUS_SUCCESS) {
2654                                 DRM_DEBUG_KMS("Incorrect SDVO get sat\n");
2655                                 return;
2656                         }
2657                         sdvo_priv->max_saturation = data_value[0];
2658                         sdvo_priv->cur_saturation = response;
2659                         sdvo_priv->saturation_property =
2660                                 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2661                                                 "saturation", 2);
2662                         sdvo_priv->saturation_property->values[0] = 0;
2663                         sdvo_priv->saturation_property->values[1] =
2664                                                         data_value[0];
2665                         drm_connector_attach_property(connector,
2666                                                 sdvo_priv->saturation_property,
2667                                                 sdvo_priv->cur_saturation);
2668                         DRM_DEBUG_KMS("saturation: max %d, "
2669                                         "default %d, current %d\n",
2670                                         data_value[0], data_value[1], response);
2671                 }
2672                 if (sdvo_data.contrast) {
2673                         intel_sdvo_write_cmd(intel_encoder,
2674                                 SDVO_CMD_GET_MAX_CONTRAST, NULL, 0);
2675                         status = intel_sdvo_read_response(intel_encoder,
2676                                 &data_value, 4);
2677                         if (status != SDVO_CMD_STATUS_SUCCESS) {
2678                                 DRM_DEBUG_KMS("Incorrect SDVO Max contrast\n");
2679                                 return;
2680                         }
2681                         intel_sdvo_write_cmd(intel_encoder,
2682                                 SDVO_CMD_GET_CONTRAST, NULL, 0);
2683                         status = intel_sdvo_read_response(intel_encoder,
2684                                 &response, 2);
2685                         if (status != SDVO_CMD_STATUS_SUCCESS) {
2686                                 DRM_DEBUG_KMS("Incorrect SDVO get contrast\n");
2687                                 return;
2688                         }
2689                         sdvo_priv->max_contrast = data_value[0];
2690                         sdvo_priv->cur_contrast = response;
2691                         sdvo_priv->contrast_property =
2692                                 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2693                                                 "contrast", 2);
2694                         sdvo_priv->contrast_property->values[0] = 0;
2695                         sdvo_priv->contrast_property->values[1] = data_value[0];
2696                         drm_connector_attach_property(connector,
2697                                                 sdvo_priv->contrast_property,
2698                                                 sdvo_priv->cur_contrast);
2699                         DRM_DEBUG_KMS("contrast: max %d, "
2700                                         "default %d, current %d\n",
2701                                         data_value[0], data_value[1], response);
2702                 }
2703                 if (sdvo_data.hue) {
2704                         intel_sdvo_write_cmd(intel_encoder,
2705                                 SDVO_CMD_GET_MAX_HUE, NULL, 0);
2706                         status = intel_sdvo_read_response(intel_encoder,
2707                                 &data_value, 4);
2708                         if (status != SDVO_CMD_STATUS_SUCCESS) {
2709                                 DRM_DEBUG_KMS("Incorrect SDVO Max hue\n");
2710                                 return;
2711                         }
2712                         intel_sdvo_write_cmd(intel_encoder,
2713                                 SDVO_CMD_GET_HUE, NULL, 0);
2714                         status = intel_sdvo_read_response(intel_encoder,
2715                                 &response, 2);
2716                         if (status != SDVO_CMD_STATUS_SUCCESS) {
2717                                 DRM_DEBUG_KMS("Incorrect SDVO get hue\n");
2718                                 return;
2719                         }
2720                         sdvo_priv->max_hue = data_value[0];
2721                         sdvo_priv->cur_hue = response;
2722                         sdvo_priv->hue_property =
2723                                 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2724                                                 "hue", 2);
2725                         sdvo_priv->hue_property->values[0] = 0;
2726                         sdvo_priv->hue_property->values[1] =
2727                                                         data_value[0];
2728                         drm_connector_attach_property(connector,
2729                                                 sdvo_priv->hue_property,
2730                                                 sdvo_priv->cur_hue);
2731                         DRM_DEBUG_KMS("hue: max %d, default %d, current %d\n",
2732                                         data_value[0], data_value[1], response);
2733                 }
2734         }
2735         if (sdvo_priv->is_tv || sdvo_priv->is_lvds) {
2736                 if (sdvo_data.brightness) {
2737                         intel_sdvo_write_cmd(intel_encoder,
2738                                 SDVO_CMD_GET_MAX_BRIGHTNESS, NULL, 0);
2739                         status = intel_sdvo_read_response(intel_encoder,
2740                                 &data_value, 4);
2741                         if (status != SDVO_CMD_STATUS_SUCCESS) {
2742                                 DRM_DEBUG_KMS("Incorrect SDVO Max bright\n");
2743                                 return;
2744                         }
2745                         intel_sdvo_write_cmd(intel_encoder,
2746                                 SDVO_CMD_GET_BRIGHTNESS, NULL, 0);
2747                         status = intel_sdvo_read_response(intel_encoder,
2748                                 &response, 2);
2749                         if (status != SDVO_CMD_STATUS_SUCCESS) {
2750                                 DRM_DEBUG_KMS("Incorrect SDVO get brigh\n");
2751                                 return;
2752                         }
2753                         sdvo_priv->max_brightness = data_value[0];
2754                         sdvo_priv->cur_brightness = response;
2755                         sdvo_priv->brightness_property =
2756                                 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2757                                                 "brightness", 2);
2758                         sdvo_priv->brightness_property->values[0] = 0;
2759                         sdvo_priv->brightness_property->values[1] =
2760                                                         data_value[0];
2761                         drm_connector_attach_property(connector,
2762                                                 sdvo_priv->brightness_property,
2763                                                 sdvo_priv->cur_brightness);
2764                         DRM_DEBUG_KMS("brightness: max %d, "
2765                                         "default %d, current %d\n",
2766                                         data_value[0], data_value[1], response);
2767                 }
2768         }
2769         return;
2770 }
2771
2772 bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg)
2773 {
2774         struct drm_i915_private *dev_priv = dev->dev_private;
2775         struct drm_connector *connector;
2776         struct intel_encoder *intel_encoder;
2777         struct intel_sdvo_priv *sdvo_priv;
2778
2779         u8 ch[0x40];
2780         int i;
2781
2782         intel_encoder = kcalloc(sizeof(struct intel_encoder)+sizeof(struct intel_sdvo_priv), 1, GFP_KERNEL);
2783         if (!intel_encoder) {
2784                 return false;
2785         }
2786
2787         sdvo_priv = (struct intel_sdvo_priv *)(intel_encoder + 1);
2788         sdvo_priv->sdvo_reg = sdvo_reg;
2789
2790         intel_encoder->dev_priv = sdvo_priv;
2791         intel_encoder->type = INTEL_OUTPUT_SDVO;
2792
2793         /* setup the DDC bus. */
2794         if (sdvo_reg == SDVOB)
2795                 intel_encoder->i2c_bus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOB");
2796         else
2797                 intel_encoder->i2c_bus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOC");
2798
2799         if (!intel_encoder->i2c_bus)
2800                 goto err_inteloutput;
2801
2802         sdvo_priv->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg);
2803
2804         /* Save the bit-banging i2c functionality for use by the DDC wrapper */
2805         intel_sdvo_i2c_bit_algo.functionality = intel_encoder->i2c_bus->algo->functionality;
2806
2807         /* Read the regs to test if we can talk to the device */
2808         for (i = 0; i < 0x40; i++) {
2809                 if (!intel_sdvo_read_byte(intel_encoder, i, &ch[i])) {
2810                         DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n",
2811                                         sdvo_reg == SDVOB ? 'B' : 'C');
2812                         goto err_i2c;
2813                 }
2814         }
2815
2816         /* setup the DDC bus. */
2817         if (sdvo_reg == SDVOB) {
2818                 intel_encoder->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOB DDC BUS");
2819                 sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA,
2820                                                 "SDVOB/VGA DDC BUS");
2821                 dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS;
2822         } else {
2823                 intel_encoder->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOC DDC BUS");
2824                 sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA,
2825                                                 "SDVOC/VGA DDC BUS");
2826                 dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;
2827         }
2828
2829         if (intel_encoder->ddc_bus == NULL)
2830                 goto err_i2c;
2831
2832         /* Wrap with our custom algo which switches to DDC mode */
2833         intel_encoder->ddc_bus->algo = &intel_sdvo_i2c_bit_algo;
2834
2835         /* In default case sdvo lvds is false */
2836         intel_sdvo_get_capabilities(intel_encoder, &sdvo_priv->caps);
2837
2838         if (intel_sdvo_output_setup(intel_encoder,
2839                                     sdvo_priv->caps.output_flags) != true) {
2840                 DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n",
2841                           sdvo_reg == SDVOB ? 'B' : 'C');
2842                 goto err_i2c;
2843         }
2844
2845
2846         connector = &intel_encoder->base;
2847         drm_connector_init(dev, connector, &intel_sdvo_connector_funcs,
2848                            connector->connector_type);
2849
2850         drm_connector_helper_add(connector, &intel_sdvo_connector_helper_funcs);
2851         connector->interlace_allowed = 0;
2852         connector->doublescan_allowed = 0;
2853         connector->display_info.subpixel_order = SubPixelHorizontalRGB;
2854
2855         drm_encoder_init(dev, &intel_encoder->enc,
2856                         &intel_sdvo_enc_funcs, intel_encoder->enc.encoder_type);
2857
2858         drm_encoder_helper_add(&intel_encoder->enc, &intel_sdvo_helper_funcs);
2859
2860         drm_mode_connector_attach_encoder(&intel_encoder->base, &intel_encoder->enc);
2861         if (sdvo_priv->is_tv)
2862                 intel_sdvo_tv_create_property(connector);
2863
2864         if (sdvo_priv->is_tv || sdvo_priv->is_lvds)
2865                 intel_sdvo_create_enhance_property(connector);
2866
2867         drm_sysfs_connector_add(connector);
2868
2869         intel_sdvo_select_ddc_bus(sdvo_priv);
2870
2871         /* Set the input timing to the screen. Assume always input 0. */
2872         intel_sdvo_set_target_input(intel_encoder, true, false);
2873
2874         intel_sdvo_get_input_pixel_clock_range(intel_encoder,
2875                                                &sdvo_priv->pixel_clock_min,
2876                                                &sdvo_priv->pixel_clock_max);
2877
2878
2879         DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
2880                         "clock range %dMHz - %dMHz, "
2881                         "input 1: %c, input 2: %c, "
2882                         "output 1: %c, output 2: %c\n",
2883                         SDVO_NAME(sdvo_priv),
2884                         sdvo_priv->caps.vendor_id, sdvo_priv->caps.device_id,
2885                         sdvo_priv->caps.device_rev_id,
2886                         sdvo_priv->pixel_clock_min / 1000,
2887                         sdvo_priv->pixel_clock_max / 1000,
2888                         (sdvo_priv->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2889                         (sdvo_priv->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
2890                         /* check currently supported outputs */
2891                         sdvo_priv->caps.output_flags &
2892                         (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
2893                         sdvo_priv->caps.output_flags &
2894                         (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
2895
2896         return true;
2897
2898 err_i2c:
2899         if (sdvo_priv->analog_ddc_bus != NULL)
2900                 intel_i2c_destroy(sdvo_priv->analog_ddc_bus);
2901         if (intel_encoder->ddc_bus != NULL)
2902                 intel_i2c_destroy(intel_encoder->ddc_bus);
2903         if (intel_encoder->i2c_bus != NULL)
2904                 intel_i2c_destroy(intel_encoder->i2c_bus);
2905 err_inteloutput:
2906         kfree(intel_encoder);
2907
2908         return false;
2909 }