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   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include "drmP.h"
  32 #include "intel_drv.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "drm_dp_helper.h"
  36
  37 #include "drm_crtc_helper.h"
  38
  39 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  40
  41 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  42 static void intel_update_watermarks(struct drm_device *dev);
  43 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
  44
  45 typedef struct {
  46     /* given values */
  47     int n;
  48     int m1, m2;
  49     int p1, p2;
  50     /* derived values */
  51     int dot;
  52     int vco;
  53     int m;
  54     int p;
  55 } intel_clock_t;
  56
  57 typedef struct {
  58     int min, max;
  59 } intel_range_t;
  60
  61 typedef struct {
  62     int dot_limit;
  63     int p2_slow, p2_fast;
  64 } intel_p2_t;
  65
  66 #define INTEL_P2_NUM                  2
  67 typedef struct intel_limit intel_limit_t;
  68 struct intel_limit {
  69     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  70     intel_p2_t      p2;
  71     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  72                       int, int, intel_clock_t *);
  73 };
  74
  75 #define I8XX_DOT_MIN              25000
  76 #define I8XX_DOT_MAX             350000
  77 #define I8XX_VCO_MIN             930000
  78 #define I8XX_VCO_MAX            1400000
  79 #define I8XX_N_MIN                    3
  80 #define I8XX_N_MAX                   16
  81 #define I8XX_M_MIN                   96
  82 #define I8XX_M_MAX                  140
  83 #define I8XX_M1_MIN                  18
  84 #define I8XX_M1_MAX                  26
  85 #define I8XX_M2_MIN                   6
  86 #define I8XX_M2_MAX                  16
  87 #define I8XX_P_MIN                    4
  88 #define I8XX_P_MAX                  128
  89 #define I8XX_P1_MIN                   2
  90 #define I8XX_P1_MAX                  33
  91 #define I8XX_P1_LVDS_MIN              1
  92 #define I8XX_P1_LVDS_MAX              6
  93 #define I8XX_P2_SLOW                  4
  94 #define I8XX_P2_FAST                  2
  95 #define I8XX_P2_LVDS_SLOW             14
  96 #define I8XX_P2_LVDS_FAST             7
  97 #define I8XX_P2_SLOW_LIMIT       165000
  98
  99 #define I9XX_DOT_MIN              20000
 100 #define I9XX_DOT_MAX             400000
 101 #define I9XX_VCO_MIN            1400000
 102 #define I9XX_VCO_MAX            2800000
 103 #define PINEVIEW_VCO_MIN                1700000
 104 #define PINEVIEW_VCO_MAX                3500000
 105 #define I9XX_N_MIN                    1
 106 #define I9XX_N_MAX                    6
 107 /* Pineview's Ncounter is a ring counter */
 108 #define PINEVIEW_N_MIN                3
 109 #define PINEVIEW_N_MAX                6
 110 #define I9XX_M_MIN                   70
 111 #define I9XX_M_MAX                  120
 112 #define PINEVIEW_M_MIN                2
 113 #define PINEVIEW_M_MAX              256
 114 #define I9XX_M1_MIN                  10
 115 #define I9XX_M1_MAX                  22
 116 #define I9XX_M2_MIN                   5
 117 #define I9XX_M2_MAX                   9
 118 /* Pineview M1 is reserved, and must be 0 */
 119 #define PINEVIEW_M1_MIN               0
 120 #define PINEVIEW_M1_MAX               0
 121 #define PINEVIEW_M2_MIN               0
 122 #define PINEVIEW_M2_MAX               254
 123 #define I9XX_P_SDVO_DAC_MIN           5
 124 #define I9XX_P_SDVO_DAC_MAX          80
 125 #define I9XX_P_LVDS_MIN               7
 126 #define I9XX_P_LVDS_MAX              98
 127 #define PINEVIEW_P_LVDS_MIN                   7
 128 #define PINEVIEW_P_LVDS_MAX                  112
 129 #define I9XX_P1_MIN                   1
 130 #define I9XX_P1_MAX                   8
 131 #define I9XX_P2_SDVO_DAC_SLOW                10
 132 #define I9XX_P2_SDVO_DAC_FAST                 5
 133 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 134 #define I9XX_P2_LVDS_SLOW                    14
 135 #define I9XX_P2_LVDS_FAST                     7
 136 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 137
 138 /*The parameter is for SDVO on G4x platform*/
 139 #define G4X_DOT_SDVO_MIN           25000
 140 #define G4X_DOT_SDVO_MAX           270000
 141 #define G4X_VCO_MIN                1750000
 142 #define G4X_VCO_MAX                3500000
 143 #define G4X_N_SDVO_MIN             1
 144 #define G4X_N_SDVO_MAX             4
 145 #define G4X_M_SDVO_MIN             104
 146 #define G4X_M_SDVO_MAX             138
 147 #define G4X_M1_SDVO_MIN            17
 148 #define G4X_M1_SDVO_MAX            23
 149 #define G4X_M2_SDVO_MIN            5
 150 #define G4X_M2_SDVO_MAX            11
 151 #define G4X_P_SDVO_MIN             10
 152 #define G4X_P_SDVO_MAX             30
 153 #define G4X_P1_SDVO_MIN            1
 154 #define G4X_P1_SDVO_MAX            3
 155 #define G4X_P2_SDVO_SLOW           10
 156 #define G4X_P2_SDVO_FAST           10
 157 #define G4X_P2_SDVO_LIMIT          270000
 158
 159 /*The parameter is for HDMI_DAC on G4x platform*/
 160 #define G4X_DOT_HDMI_DAC_MIN           22000
 161 #define G4X_DOT_HDMI_DAC_MAX           400000
 162 #define G4X_N_HDMI_DAC_MIN             1
 163 #define G4X_N_HDMI_DAC_MAX             4
 164 #define G4X_M_HDMI_DAC_MIN             104
 165 #define G4X_M_HDMI_DAC_MAX             138
 166 #define G4X_M1_HDMI_DAC_MIN            16
 167 #define G4X_M1_HDMI_DAC_MAX            23
 168 #define G4X_M2_HDMI_DAC_MIN            5
 169 #define G4X_M2_HDMI_DAC_MAX            11
 170 #define G4X_P_HDMI_DAC_MIN             5
 171 #define G4X_P_HDMI_DAC_MAX             80
 172 #define G4X_P1_HDMI_DAC_MIN            1
 173 #define G4X_P1_HDMI_DAC_MAX            8
 174 #define G4X_P2_HDMI_DAC_SLOW           10
 175 #define G4X_P2_HDMI_DAC_FAST           5
 176 #define G4X_P2_HDMI_DAC_LIMIT          165000
 177
 178 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 179 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 180 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 181 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 182 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 183 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 184 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 185 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 186 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 187 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 188 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 189 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 190 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 191 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 192 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 193 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 194 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 195 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 196
 197 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 198 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 199 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 200 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 201 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 202 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 203 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 204 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 205 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 206 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 207 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 208 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 209 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 210 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 211 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 212 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 213 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 214 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 215
 216 /*The parameter is for DISPLAY PORT on G4x platform*/
 217 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 218 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 219 #define G4X_N_DISPLAY_PORT_MIN             1
 220 #define G4X_N_DISPLAY_PORT_MAX             2
 221 #define G4X_M_DISPLAY_PORT_MIN             97
 222 #define G4X_M_DISPLAY_PORT_MAX             108
 223 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 224 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 225 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 226 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 227 #define G4X_P_DISPLAY_PORT_MIN             10
 228 #define G4X_P_DISPLAY_PORT_MAX             20
 229 #define G4X_P1_DISPLAY_PORT_MIN            1
 230 #define G4X_P1_DISPLAY_PORT_MAX            2
 231 #define G4X_P2_DISPLAY_PORT_SLOW           10
 232 #define G4X_P2_DISPLAY_PORT_FAST           10
 233 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 234
 235 /* Ironlake / Sandybridge */
 236 /* as we calculate clock using (register_value + 2) for
 237    N/M1/M2, so here the range value for them is (actual_value-2).
 238  */
 239 #define IRONLAKE_DOT_MIN         25000
 240 #define IRONLAKE_DOT_MAX         350000
 241 #define IRONLAKE_VCO_MIN         1760000
 242 #define IRONLAKE_VCO_MAX         3510000
 243 #define IRONLAKE_M1_MIN          12
 244 #define IRONLAKE_M1_MAX          22
 245 #define IRONLAKE_M2_MIN          5
 246 #define IRONLAKE_M2_MAX          9
 247 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
 248
 249 /* We have parameter ranges for different type of outputs. */
 250
 251 /* DAC & HDMI Refclk 120Mhz */
 252 #define IRONLAKE_DAC_N_MIN      1
 253 #define IRONLAKE_DAC_N_MAX      5
 254 #define IRONLAKE_DAC_M_MIN      79
 255 #define IRONLAKE_DAC_M_MAX      127
 256 #define IRONLAKE_DAC_P_MIN      5
 257 #define IRONLAKE_DAC_P_MAX      80
 258 #define IRONLAKE_DAC_P1_MIN     1
 259 #define IRONLAKE_DAC_P1_MAX     8
 260 #define IRONLAKE_DAC_P2_SLOW    10
 261 #define IRONLAKE_DAC_P2_FAST    5
 262
 263 /* LVDS single-channel 120Mhz refclk */
 264 #define IRONLAKE_LVDS_S_N_MIN   1
 265 #define IRONLAKE_LVDS_S_N_MAX   3
 266 #define IRONLAKE_LVDS_S_M_MIN   79
 267 #define IRONLAKE_LVDS_S_M_MAX   118
 268 #define IRONLAKE_LVDS_S_P_MIN   28
 269 #define IRONLAKE_LVDS_S_P_MAX   112
 270 #define IRONLAKE_LVDS_S_P1_MIN  2
 271 #define IRONLAKE_LVDS_S_P1_MAX  8
 272 #define IRONLAKE_LVDS_S_P2_SLOW 14
 273 #define IRONLAKE_LVDS_S_P2_FAST 14
 274
 275 /* LVDS dual-channel 120Mhz refclk */
 276 #define IRONLAKE_LVDS_D_N_MIN   1
 277 #define IRONLAKE_LVDS_D_N_MAX   3
 278 #define IRONLAKE_LVDS_D_M_MIN   79
 279 #define IRONLAKE_LVDS_D_M_MAX   127
 280 #define IRONLAKE_LVDS_D_P_MIN   14
 281 #define IRONLAKE_LVDS_D_P_MAX   56
 282 #define IRONLAKE_LVDS_D_P1_MIN  2
 283 #define IRONLAKE_LVDS_D_P1_MAX  8
 284 #define IRONLAKE_LVDS_D_P2_SLOW 7
 285 #define IRONLAKE_LVDS_D_P2_FAST 7
 286
 287 /* LVDS single-channel 100Mhz refclk */
 288 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
 289 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
 290 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
 291 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
 292 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
 293 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
 294 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
 295 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
 296 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
 297 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
 298
 299 /* LVDS dual-channel 100Mhz refclk */
 300 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
 301 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
 302 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
 303 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
 304 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
 305 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
 306 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
 307 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
 308 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
 309 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
 310
 311 /* DisplayPort */
 312 #define IRONLAKE_DP_N_MIN               1
 313 #define IRONLAKE_DP_N_MAX               2
 314 #define IRONLAKE_DP_M_MIN               81
 315 #define IRONLAKE_DP_M_MAX               90
 316 #define IRONLAKE_DP_P_MIN               10
 317 #define IRONLAKE_DP_P_MAX               20
 318 #define IRONLAKE_DP_P2_FAST             10
 319 #define IRONLAKE_DP_P2_SLOW             10
 320 #define IRONLAKE_DP_P2_LIMIT            0
 321 #define IRONLAKE_DP_P1_MIN              1
 322 #define IRONLAKE_DP_P1_MAX              2
 323
 324 static bool
 325 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 326                     int target, int refclk, intel_clock_t *best_clock);
 327 static bool
 328 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 329                         int target, int refclk, intel_clock_t *best_clock);
 330
 331 static bool
 332 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 333                       int target, int refclk, intel_clock_t *best_clock);
 334 static bool
 335 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 336                            int target, int refclk, intel_clock_t *best_clock);
 337
 338 static const intel_limit_t intel_limits_i8xx_dvo = {
 339         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 340         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 341         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 342         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 343         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 344         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 345         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 346         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 347         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 348                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 349         .find_pll = intel_find_best_PLL,
 350 };
 351
 352 static const intel_limit_t intel_limits_i8xx_lvds = {
 353         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 354         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 355         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 356         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 357         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 358         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 359         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 360         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 361         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 362                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 363         .find_pll = intel_find_best_PLL,
 364 };
 365
 366 static const intel_limit_t intel_limits_i9xx_sdvo = {
 367         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 368         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 369         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 370         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 371         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 372         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 373         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 374         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 375         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 376                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 377         .find_pll = intel_find_best_PLL,
 378 };
 379
 380 static const intel_limit_t intel_limits_i9xx_lvds = {
 381         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 382         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 383         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 384         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 385         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 386         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 387         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 388         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 389         /* The single-channel range is 25-112Mhz, and dual-channel
 390          * is 80-224Mhz.  Prefer single channel as much as possible.
 391          */
 392         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 393                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 394         .find_pll = intel_find_best_PLL,
 395 };
 396
 397     /* below parameter and function is for G4X Chipset Family*/
 398 static const intel_limit_t intel_limits_g4x_sdvo = {
 399         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 400         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 401         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 402         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 403         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 404         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 405         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 406         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 407         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 408                  .p2_slow = G4X_P2_SDVO_SLOW,
 409                  .p2_fast = G4X_P2_SDVO_FAST
 410         },
 411         .find_pll = intel_g4x_find_best_PLL,
 412 };
 413
 414 static const intel_limit_t intel_limits_g4x_hdmi = {
 415         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 416         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 417         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 418         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 419         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 420         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 421         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 422         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 423         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 424                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 425                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 426         },
 427         .find_pll = intel_g4x_find_best_PLL,
 428 };
 429
 430 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 431         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 432                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 433         .vco = { .min = G4X_VCO_MIN,
 434                  .max = G4X_VCO_MAX },
 435         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 436                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 437         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 438                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 439         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 440                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 441         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 442                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 443         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 444                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 445         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 446                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 447         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 448                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 449                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 450         },
 451         .find_pll = intel_g4x_find_best_PLL,
 452 };
 453
 454 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 455         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 456                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 457         .vco = { .min = G4X_VCO_MIN,
 458                  .max = G4X_VCO_MAX },
 459         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 460                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 461         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 462                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 463         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 464                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 465         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 466                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 467         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 468                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 469         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 470                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 471         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 472                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 473                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 474         },
 475         .find_pll = intel_g4x_find_best_PLL,
 476 };
 477
 478 static const intel_limit_t intel_limits_g4x_display_port = {
 479         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 480                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 481         .vco = { .min = G4X_VCO_MIN,
 482                  .max = G4X_VCO_MAX},
 483         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 484                  .max = G4X_N_DISPLAY_PORT_MAX },
 485         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 486                  .max = G4X_M_DISPLAY_PORT_MAX },
 487         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 488                  .max = G4X_M1_DISPLAY_PORT_MAX },
 489         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 490                  .max = G4X_M2_DISPLAY_PORT_MAX },
 491         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 492                  .max = G4X_P_DISPLAY_PORT_MAX },
 493         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 494                  .max = G4X_P1_DISPLAY_PORT_MAX},
 495         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 496                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 497                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 498         .find_pll = intel_find_pll_g4x_dp,
 499 };
 500
 501 static const intel_limit_t intel_limits_pineview_sdvo = {
 502         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 503         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 504         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 505         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 506         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 507         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 508         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 509         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 510         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 511                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 512         .find_pll = intel_find_best_PLL,
 513 };
 514
 515 static const intel_limit_t intel_limits_pineview_lvds = {
 516         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 517         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 518         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 519         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 520         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 521         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 522         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
 523         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 524         /* Pineview only supports single-channel mode. */
 525         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 526                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 527         .find_pll = intel_find_best_PLL,
 528 };
 529
 530 static const intel_limit_t intel_limits_ironlake_dac = {
 531         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 532         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 533         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
 534         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
 535         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 536         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 537         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
 538         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
 539         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 540                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
 541                  .p2_fast = IRONLAKE_DAC_P2_FAST },
 542         .find_pll = intel_g4x_find_best_PLL,
 543 };
 544
 545 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 546         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 547         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 548         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
 549         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
 550         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 551         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 552         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
 553         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
 554         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 555                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
 556                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
 557         .find_pll = intel_g4x_find_best_PLL,
 558 };
 559
 560 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 561         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 562         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 563         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
 564         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
 565         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 566         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 567         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
 568         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
 569         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 570                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
 571                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
 572         .find_pll = intel_g4x_find_best_PLL,
 573 };
 574
 575 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 576         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 577         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 578         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
 579         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
 580         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 581         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 582         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
 583         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
 584         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 585                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
 586                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
 587         .find_pll = intel_g4x_find_best_PLL,
 588 };
 589
 590 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 591         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 592         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 593         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
 594         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
 595         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 596         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 597         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
 598         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
 599         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 600                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
 601                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
 602         .find_pll = intel_g4x_find_best_PLL,
 603 };
 604
 605 static const intel_limit_t intel_limits_ironlake_display_port = {
 606         .dot = { .min = IRONLAKE_DOT_MIN,
 607                  .max = IRONLAKE_DOT_MAX },
 608         .vco = { .min = IRONLAKE_VCO_MIN,
 609                  .max = IRONLAKE_VCO_MAX},
 610         .n   = { .min = IRONLAKE_DP_N_MIN,
 611                  .max = IRONLAKE_DP_N_MAX },
 612         .m   = { .min = IRONLAKE_DP_M_MIN,
 613                  .max = IRONLAKE_DP_M_MAX },
 614         .m1  = { .min = IRONLAKE_M1_MIN,
 615                  .max = IRONLAKE_M1_MAX },
 616         .m2  = { .min = IRONLAKE_M2_MIN,
 617                  .max = IRONLAKE_M2_MAX },
 618         .p   = { .min = IRONLAKE_DP_P_MIN,
 619                  .max = IRONLAKE_DP_P_MAX },
 620         .p1  = { .min = IRONLAKE_DP_P1_MIN,
 621                  .max = IRONLAKE_DP_P1_MAX},
 622         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
 623                  .p2_slow = IRONLAKE_DP_P2_SLOW,
 624                  .p2_fast = IRONLAKE_DP_P2_FAST },
 625         .find_pll = intel_find_pll_ironlake_dp,
 626 };
 627
 628 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
 629 {
 630         struct drm_device *dev = crtc->dev;
 631         struct drm_i915_private *dev_priv = dev->dev_private;
 632         const intel_limit_t *limit;
 633         int refclk = 120;
 634
 635         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 636                 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
 637                         refclk = 100;
 638
 639                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 640                     LVDS_CLKB_POWER_UP) {
 641                         /* LVDS dual channel */
 642                         if (refclk == 100)
 643                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 644                         else
 645                                 limit = &intel_limits_ironlake_dual_lvds;
 646                 } else {
 647                         if (refclk == 100)
 648                                 limit = &intel_limits_ironlake_single_lvds_100m;
 649                         else
 650                                 limit = &intel_limits_ironlake_single_lvds;
 651                 }
 652         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 653                         HAS_eDP)
 654                 limit = &intel_limits_ironlake_display_port;
 655         else
 656                 limit = &intel_limits_ironlake_dac;
 657
 658         return limit;
 659 }
 660
 661 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 662 {
 663         struct drm_device *dev = crtc->dev;
 664         struct drm_i915_private *dev_priv = dev->dev_private;
 665         const intel_limit_t *limit;
 666
 667         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 668                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 669                     LVDS_CLKB_POWER_UP)
 670                         /* LVDS with dual channel */
 671                         limit = &intel_limits_g4x_dual_channel_lvds;
 672                 else
 673                         /* LVDS with dual channel */
 674                         limit = &intel_limits_g4x_single_channel_lvds;
 675         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 676                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 677                 limit = &intel_limits_g4x_hdmi;
 678         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 679                 limit = &intel_limits_g4x_sdvo;
 680         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 681                 limit = &intel_limits_g4x_display_port;
 682         } else /* The option is for other outputs */
 683                 limit = &intel_limits_i9xx_sdvo;
 684
 685         return limit;
 686 }
 687
 688 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 689 {
 690         struct drm_device *dev = crtc->dev;
 691         const intel_limit_t *limit;
 692
 693         if (HAS_PCH_SPLIT(dev))
 694                 limit = intel_ironlake_limit(crtc);
 695         else if (IS_G4X(dev)) {
 696                 limit = intel_g4x_limit(crtc);
 697         } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
 698                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 699                         limit = &intel_limits_i9xx_lvds;
 700                 else
 701                         limit = &intel_limits_i9xx_sdvo;
 702         } else if (IS_PINEVIEW(dev)) {
 703                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 704                         limit = &intel_limits_pineview_lvds;
 705                 else
 706                         limit = &intel_limits_pineview_sdvo;
 707         } else {
 708                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 709                         limit = &intel_limits_i8xx_lvds;
 710                 else
 711                         limit = &intel_limits_i8xx_dvo;
 712         }
 713         return limit;
 714 }
 715
 716 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 717 static void pineview_clock(int refclk, intel_clock_t *clock)
 718 {
 719         clock->m = clock->m2 + 2;
 720         clock->p = clock->p1 * clock->p2;
 721         clock->vco = refclk * clock->m / clock->n;
 722         clock->dot = clock->vco / clock->p;
 723 }
 724
 725 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 726 {
 727         if (IS_PINEVIEW(dev)) {
 728                 pineview_clock(refclk, clock);
 729                 return;
 730         }
 731         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 732         clock->p = clock->p1 * clock->p2;
 733         clock->vco = refclk * clock->m / (clock->n + 2);
 734         clock->dot = clock->vco / clock->p;
 735 }
 736
 737 /**
 738  * Returns whether any output on the specified pipe is of the specified type
 739  */
 740 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
 741 {
 742     struct drm_device *dev = crtc->dev;
 743     struct drm_mode_config *mode_config = &dev->mode_config;
 744     struct drm_encoder *l_entry;
 745
 746     list_for_each_entry(l_entry, &mode_config->encoder_list, head) {
 747             if (l_entry && l_entry->crtc == crtc) {
 748                     struct intel_encoder *intel_encoder = enc_to_intel_encoder(l_entry);
 749                     if (intel_encoder->type == type)
 750                             return true;
 751             }
 752     }
 753     return false;
 754 }
 755
 756 static struct drm_connector *
 757 intel_pipe_get_connector (struct drm_crtc *crtc)
 758 {
 759     struct drm_device *dev = crtc->dev;
 760     struct drm_mode_config *mode_config = &dev->mode_config;
 761     struct drm_connector *l_entry, *ret = NULL;
 762
 763     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 764             if (l_entry->encoder &&
 765                 l_entry->encoder->crtc == crtc) {
 766                     ret = l_entry;
 767                     break;
 768             }
 769     }
 770     return ret;
 771 }
 772
 773 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 774 /**
 775  * Returns whether the given set of divisors are valid for a given refclk with
 776  * the given connectors.
 777  */
 778
 779 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 780 {
 781         const intel_limit_t *limit = intel_limit (crtc);
 782         struct drm_device *dev = crtc->dev;
 783
 784         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 785                 INTELPllInvalid ("p1 out of range\n");
 786         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 787                 INTELPllInvalid ("p out of range\n");
 788         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 789                 INTELPllInvalid ("m2 out of range\n");
 790         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 791                 INTELPllInvalid ("m1 out of range\n");
 792         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 793                 INTELPllInvalid ("m1 <= m2\n");
 794         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 795                 INTELPllInvalid ("m out of range\n");
 796         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 797                 INTELPllInvalid ("n out of range\n");
 798         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 799                 INTELPllInvalid ("vco out of range\n");
 800         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 801          * connector, etc., rather than just a single range.
 802          */
 803         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 804                 INTELPllInvalid ("dot out of range\n");
 805
 806         return true;
 807 }
 808
 809 static bool
 810 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 811                     int target, int refclk, intel_clock_t *best_clock)
 812
 813 {
 814         struct drm_device *dev = crtc->dev;
 815         struct drm_i915_private *dev_priv = dev->dev_private;
 816         intel_clock_t clock;
 817         int err = target;
 818
 819         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 820             (I915_READ(LVDS)) != 0) {
 821                 /*
 822                  * For LVDS, if the panel is on, just rely on its current
 823                  * settings for dual-channel.  We haven't figured out how to
 824                  * reliably set up different single/dual channel state, if we
 825                  * even can.
 826                  */
 827                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 828                     LVDS_CLKB_POWER_UP)
 829                         clock.p2 = limit->p2.p2_fast;
 830                 else
 831                         clock.p2 = limit->p2.p2_slow;
 832         } else {
 833                 if (target < limit->p2.dot_limit)
 834                         clock.p2 = limit->p2.p2_slow;
 835                 else
 836                         clock.p2 = limit->p2.p2_fast;
 837         }
 838
 839         memset (best_clock, 0, sizeof (*best_clock));
 840
 841         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 842              clock.m1++) {
 843                 for (clock.m2 = limit->m2.min;
 844                      clock.m2 <= limit->m2.max; clock.m2++) {
 845                         /* m1 is always 0 in Pineview */
 846                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 847                                 break;
 848                         for (clock.n = limit->n.min;
 849                              clock.n <= limit->n.max; clock.n++) {
 850                                 for (clock.p1 = limit->p1.min;
 851                                         clock.p1 <= limit->p1.max; clock.p1++) {
 852                                         int this_err;
 853
 854                                         intel_clock(dev, refclk, &clock);
 855
 856                                         if (!intel_PLL_is_valid(crtc, &clock))
 857                                                 continue;
 858
 859                                         this_err = abs(clock.dot - target);
 860                                         if (this_err < err) {
 861                                                 *best_clock = clock;
 862                                                 err = this_err;
 863                                         }
 864                                 }
 865                         }
 866                 }
 867         }
 868
 869         return (err != target);
 870 }
 871
 872 static bool
 873 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 874                         int target, int refclk, intel_clock_t *best_clock)
 875 {
 876         struct drm_device *dev = crtc->dev;
 877         struct drm_i915_private *dev_priv = dev->dev_private;
 878         intel_clock_t clock;
 879         int max_n;
 880         bool found;
 881         /* approximately equals target * 0.00488 */
 882         int err_most = (target >> 8) + (target >> 10);
 883         found = false;
 884
 885         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 886                 int lvds_reg;
 887
 888                 if (HAS_PCH_SPLIT(dev))
 889                         lvds_reg = PCH_LVDS;
 890                 else
 891                         lvds_reg = LVDS;
 892                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 893                     LVDS_CLKB_POWER_UP)
 894                         clock.p2 = limit->p2.p2_fast;
 895                 else
 896                         clock.p2 = limit->p2.p2_slow;
 897         } else {
 898                 if (target < limit->p2.dot_limit)
 899                         clock.p2 = limit->p2.p2_slow;
 900                 else
 901                         clock.p2 = limit->p2.p2_fast;
 902         }
 903
 904         memset(best_clock, 0, sizeof(*best_clock));
 905         max_n = limit->n.max;
 906         /* based on hardware requriment prefer smaller n to precision */
 907         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 908                 /* based on hardware requirment prefere larger m1,m2 */
 909                 for (clock.m1 = limit->m1.max;
 910                      clock.m1 >= limit->m1.min; clock.m1--) {
 911                         for (clock.m2 = limit->m2.max;
 912                              clock.m2 >= limit->m2.min; clock.m2--) {
 913                                 for (clock.p1 = limit->p1.max;
 914                                      clock.p1 >= limit->p1.min; clock.p1--) {
 915                                         int this_err;
 916
 917                                         intel_clock(dev, refclk, &clock);
 918                                         if (!intel_PLL_is_valid(crtc, &clock))
 919                                                 continue;
 920                                         this_err = abs(clock.dot - target) ;
 921                                         if (this_err < err_most) {
 922                                                 *best_clock = clock;
 923                                                 err_most = this_err;
 924                                                 max_n = clock.n;
 925                                                 found = true;
 926                                         }
 927                                 }
 928                         }
 929                 }
 930         }
 931         return found;
 932 }
 933
 934 static bool
 935 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 936                            int target, int refclk, intel_clock_t *best_clock)
 937 {
 938         struct drm_device *dev = crtc->dev;
 939         intel_clock_t clock;
 940
 941         /* return directly when it is eDP */
 942         if (HAS_eDP)
 943                 return true;
 944
 945         if (target < 200000) {
 946                 clock.n = 1;
 947                 clock.p1 = 2;
 948                 clock.p2 = 10;
 949                 clock.m1 = 12;
 950                 clock.m2 = 9;
 951         } else {
 952                 clock.n = 2;
 953                 clock.p1 = 1;
 954                 clock.p2 = 10;
 955                 clock.m1 = 14;
 956                 clock.m2 = 8;
 957         }
 958         intel_clock(dev, refclk, &clock);
 959         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 960         return true;
 961 }
 962
 963 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 964 static bool
 965 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 966                       int target, int refclk, intel_clock_t *best_clock)
 967 {
 968     intel_clock_t clock;
 969     if (target < 200000) {
 970         clock.p1 = 2;
 971         clock.p2 = 10;
 972         clock.n = 2;
 973         clock.m1 = 23;
 974         clock.m2 = 8;
 975     } else {
 976         clock.p1 = 1;
 977         clock.p2 = 10;
 978         clock.n = 1;
 979         clock.m1 = 14;
 980         clock.m2 = 2;
 981     }
 982     clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 983     clock.p = (clock.p1 * clock.p2);
 984     clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 985     clock.vco = 0;
 986     memcpy(best_clock, &clock, sizeof(intel_clock_t));
 987     return true;
 988 }
 989
 990 void
 991 intel_wait_for_vblank(struct drm_device *dev)
 992 {
 993         /* Wait for 20ms, i.e. one cycle at 50hz. */
 994         msleep(20);
 995 }
 996
 997 /* Parameters have changed, update FBC info */
 998 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 999 {
1000         struct drm_device *dev = crtc->dev;
1001         struct drm_i915_private *dev_priv = dev->dev_private;
1002         struct drm_framebuffer *fb = crtc->fb;
1003         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1004         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1005         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1006         int plane, i;
1007         u32 fbc_ctl, fbc_ctl2;
1008
1009         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1010
1011         if (fb->pitch < dev_priv->cfb_pitch)
1012                 dev_priv->cfb_pitch = fb->pitch;
1013
1014         /* FBC_CTL wants 64B units */
1015         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1016         dev_priv->cfb_fence = obj_priv->fence_reg;
1017         dev_priv->cfb_plane = intel_crtc->plane;
1018         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1019
1020         /* Clear old tags */
1021         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1022                 I915_WRITE(FBC_TAG + (i * 4), 0);
1023
1024         /* Set it up... */
1025         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1026         if (obj_priv->tiling_mode != I915_TILING_NONE)
1027                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1028         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1029         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1030
1031         /* enable it... */
1032         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1033         if (IS_I945GM(dev))
1034                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1035         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1036         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1037         if (obj_priv->tiling_mode != I915_TILING_NONE)
1038                 fbc_ctl |= dev_priv->cfb_fence;
1039         I915_WRITE(FBC_CONTROL, fbc_ctl);
1040
1041         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1042                   dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1043 }
1044
1045 void i8xx_disable_fbc(struct drm_device *dev)
1046 {
1047         struct drm_i915_private *dev_priv = dev->dev_private;
1048         u32 fbc_ctl;
1049
1050         if (!I915_HAS_FBC(dev))
1051                 return;
1052
1053         /* Disable compression */
1054         fbc_ctl = I915_READ(FBC_CONTROL);
1055         fbc_ctl &= ~FBC_CTL_EN;
1056         I915_WRITE(FBC_CONTROL, fbc_ctl);
1057
1058         /* Wait for compressing bit to clear */
1059         while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING)
1060                 ; /* nothing */
1061
1062         intel_wait_for_vblank(dev);
1063
1064         DRM_DEBUG_KMS("disabled FBC\n");
1065 }
1066
1067 static bool i8xx_fbc_enabled(struct drm_crtc *crtc)
1068 {
1069         struct drm_device *dev = crtc->dev;
1070         struct drm_i915_private *dev_priv = dev->dev_private;
1071
1072         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1073 }
1074
1075 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1076 {
1077         struct drm_device *dev = crtc->dev;
1078         struct drm_i915_private *dev_priv = dev->dev_private;
1079         struct drm_framebuffer *fb = crtc->fb;
1080         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1081         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1082         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1083         int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1084                      DPFC_CTL_PLANEB);
1085         unsigned long stall_watermark = 200;
1086         u32 dpfc_ctl;
1087
1088         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1089         dev_priv->cfb_fence = obj_priv->fence_reg;
1090         dev_priv->cfb_plane = intel_crtc->plane;
1091
1092         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1093         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1094                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1095                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1096         } else {
1097                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1098         }
1099
1100         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1101         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1102                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1103                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1104         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1105
1106         /* enable it... */
1107         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1108
1109         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1110 }
1111
1112 void g4x_disable_fbc(struct drm_device *dev)
1113 {
1114         struct drm_i915_private *dev_priv = dev->dev_private;
1115         u32 dpfc_ctl;
1116
1117         /* Disable compression */
1118         dpfc_ctl = I915_READ(DPFC_CONTROL);
1119         dpfc_ctl &= ~DPFC_CTL_EN;
1120         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1121         intel_wait_for_vblank(dev);
1122
1123         DRM_DEBUG_KMS("disabled FBC\n");
1124 }
1125
1126 static bool g4x_fbc_enabled(struct drm_crtc *crtc)
1127 {
1128         struct drm_device *dev = crtc->dev;
1129         struct drm_i915_private *dev_priv = dev->dev_private;
1130
1131         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1132 }
1133
1134 /**
1135  * intel_update_fbc - enable/disable FBC as needed
1136  * @crtc: CRTC to point the compressor at
1137  * @mode: mode in use
1138  *
1139  * Set up the framebuffer compression hardware at mode set time.  We
1140  * enable it if possible:
1141  *   - plane A only (on pre-965)
1142  *   - no pixel mulitply/line duplication
1143  *   - no alpha buffer discard
1144  *   - no dual wide
1145  *   - framebuffer <= 2048 in width, 1536 in height
1146  *
1147  * We can't assume that any compression will take place (worst case),
1148  * so the compressed buffer has to be the same size as the uncompressed
1149  * one.  It also must reside (along with the line length buffer) in
1150  * stolen memory.
1151  *
1152  * We need to enable/disable FBC on a global basis.
1153  */
1154 static void intel_update_fbc(struct drm_crtc *crtc,
1155                              struct drm_display_mode *mode)
1156 {
1157         struct drm_device *dev = crtc->dev;
1158         struct drm_i915_private *dev_priv = dev->dev_private;
1159         struct drm_framebuffer *fb = crtc->fb;
1160         struct intel_framebuffer *intel_fb;
1161         struct drm_i915_gem_object *obj_priv;
1162         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1163         int plane = intel_crtc->plane;
1164
1165         if (!i915_powersave)
1166                 return;
1167
1168         if (!dev_priv->display.fbc_enabled ||
1169             !dev_priv->display.enable_fbc ||
1170             !dev_priv->display.disable_fbc)
1171                 return;
1172
1173         if (!crtc->fb)
1174                 return;
1175
1176         intel_fb = to_intel_framebuffer(fb);
1177         obj_priv = to_intel_bo(intel_fb->obj);
1178
1179         /*
1180          * If FBC is already on, we just have to verify that we can
1181          * keep it that way...
1182          * Need to disable if:
1183          *   - changing FBC params (stride, fence, mode)
1184          *   - new fb is too large to fit in compressed buffer
1185          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1186          */
1187         if (intel_fb->obj->size > dev_priv->cfb_size) {
1188                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1189                                 "compression\n");
1190                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1191                 goto out_disable;
1192         }
1193         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1194             (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1195                 DRM_DEBUG_KMS("mode incompatible with compression, "
1196                                 "disabling\n");
1197                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1198                 goto out_disable;
1199         }
1200         if ((mode->hdisplay > 2048) ||
1201             (mode->vdisplay > 1536)) {
1202                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1203                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1204                 goto out_disable;
1205         }
1206         if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1207                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1208                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1209                 goto out_disable;
1210         }
1211         if (obj_priv->tiling_mode != I915_TILING_X) {
1212                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1213                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1214                 goto out_disable;
1215         }
1216
1217         if (dev_priv->display.fbc_enabled(crtc)) {
1218                 /* We can re-enable it in this case, but need to update pitch */
1219                 if (fb->pitch > dev_priv->cfb_pitch)
1220                         dev_priv->display.disable_fbc(dev);
1221                 if (obj_priv->fence_reg != dev_priv->cfb_fence)
1222                         dev_priv->display.disable_fbc(dev);
1223                 if (plane != dev_priv->cfb_plane)
1224                         dev_priv->display.disable_fbc(dev);
1225         }
1226
1227         if (!dev_priv->display.fbc_enabled(crtc)) {
1228                 /* Now try to turn it back on if possible */
1229                 dev_priv->display.enable_fbc(crtc, 500);
1230         }
1231
1232         return;
1233
1234 out_disable:
1235         DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1236         /* Multiple disables should be harmless */
1237         if (dev_priv->display.fbc_enabled(crtc))
1238                 dev_priv->display.disable_fbc(dev);
1239 }
1240
1241 static int
1242 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1243 {
1244         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1245         u32 alignment;
1246         int ret;
1247
1248         switch (obj_priv->tiling_mode) {
1249         case I915_TILING_NONE:
1250                 alignment = 64 * 1024;
1251                 break;
1252         case I915_TILING_X:
1253                 /* pin() will align the object as required by fence */
1254                 alignment = 0;
1255                 break;
1256         case I915_TILING_Y:
1257                 /* FIXME: Is this true? */
1258                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1259                 return -EINVAL;
1260         default:
1261                 BUG();
1262         }
1263
1264         ret = i915_gem_object_pin(obj, alignment);
1265         if (ret != 0)
1266                 return ret;
1267
1268         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1269          * fence, whereas 965+ only requires a fence if using
1270          * framebuffer compression.  For simplicity, we always install
1271          * a fence as the cost is not that onerous.
1272          */
1273         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1274             obj_priv->tiling_mode != I915_TILING_NONE) {
1275                 ret = i915_gem_object_get_fence_reg(obj);
1276                 if (ret != 0) {
1277                         i915_gem_object_unpin(obj);
1278                         return ret;
1279                 }
1280         }
1281
1282         return 0;
1283 }
1284
1285 static int
1286 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1287                     struct drm_framebuffer *old_fb)
1288 {
1289         struct drm_device *dev = crtc->dev;
1290         struct drm_i915_private *dev_priv = dev->dev_private;
1291         struct drm_i915_master_private *master_priv;
1292         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1293         struct intel_framebuffer *intel_fb;
1294         struct drm_i915_gem_object *obj_priv;
1295         struct drm_gem_object *obj;
1296         int pipe = intel_crtc->pipe;
1297         int plane = intel_crtc->plane;
1298         unsigned long Start, Offset;
1299         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1300         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1301         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1302         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1303         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1304         u32 dspcntr;
1305         int ret;
1306
1307         /* no fb bound */
1308         if (!crtc->fb) {
1309                 DRM_DEBUG_KMS("No FB bound\n");
1310                 return 0;
1311         }
1312
1313         switch (plane) {
1314         case 0:
1315         case 1:
1316                 break;
1317         default:
1318                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1319                 return -EINVAL;
1320         }
1321
1322         intel_fb = to_intel_framebuffer(crtc->fb);
1323         obj = intel_fb->obj;
1324         obj_priv = to_intel_bo(obj);
1325
1326         mutex_lock(&dev->struct_mutex);
1327         ret = intel_pin_and_fence_fb_obj(dev, obj);
1328         if (ret != 0) {
1329                 mutex_unlock(&dev->struct_mutex);
1330                 return ret;
1331         }
1332
1333         ret = i915_gem_object_set_to_display_plane(obj);
1334         if (ret != 0) {
1335                 i915_gem_object_unpin(obj);
1336                 mutex_unlock(&dev->struct_mutex);
1337                 return ret;
1338         }
1339
1340         dspcntr = I915_READ(dspcntr_reg);
1341         /* Mask out pixel format bits in case we change it */
1342         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1343         switch (crtc->fb->bits_per_pixel) {
1344         case 8:
1345                 dspcntr |= DISPPLANE_8BPP;
1346                 break;
1347         case 16:
1348                 if (crtc->fb->depth == 15)
1349                         dspcntr |= DISPPLANE_15_16BPP;
1350                 else
1351                         dspcntr |= DISPPLANE_16BPP;
1352                 break;
1353         case 24:
1354         case 32:
1355                 if (crtc->fb->depth == 30)
1356                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1357                 else
1358                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1359                 break;
1360         default:
1361                 DRM_ERROR("Unknown color depth\n");
1362                 i915_gem_object_unpin(obj);
1363                 mutex_unlock(&dev->struct_mutex);
1364                 return -EINVAL;
1365         }
1366         if (IS_I965G(dev)) {
1367                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1368                         dspcntr |= DISPPLANE_TILED;
1369                 else
1370                         dspcntr &= ~DISPPLANE_TILED;
1371         }
1372
1373         if (HAS_PCH_SPLIT(dev))
1374                 /* must disable */
1375                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1376
1377         I915_WRITE(dspcntr_reg, dspcntr);
1378
1379         Start = obj_priv->gtt_offset;
1380         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1381
1382         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1383         I915_WRITE(dspstride, crtc->fb->pitch);
1384         if (IS_I965G(dev)) {
1385                 I915_WRITE(dspbase, Offset);
1386                 I915_READ(dspbase);
1387                 I915_WRITE(dspsurf, Start);
1388                 I915_READ(dspsurf);
1389                 I915_WRITE(dsptileoff, (y << 16) | x);
1390         } else {
1391                 I915_WRITE(dspbase, Start + Offset);
1392                 I915_READ(dspbase);
1393         }
1394
1395         if ((IS_I965G(dev) || plane == 0))
1396                 intel_update_fbc(crtc, &crtc->mode);
1397
1398         intel_wait_for_vblank(dev);
1399
1400         if (old_fb) {
1401                 intel_fb = to_intel_framebuffer(old_fb);
1402                 obj_priv = to_intel_bo(intel_fb->obj);
1403                 i915_gem_object_unpin(intel_fb->obj);
1404         }
1405         intel_increase_pllclock(crtc, true);
1406
1407         mutex_unlock(&dev->struct_mutex);
1408
1409         if (!dev->primary->master)
1410                 return 0;
1411
1412         master_priv = dev->primary->master->driver_priv;
1413         if (!master_priv->sarea_priv)
1414                 return 0;
1415
1416         if (pipe) {
1417                 master_priv->sarea_priv->pipeB_x = x;
1418                 master_priv->sarea_priv->pipeB_y = y;
1419         } else {
1420                 master_priv->sarea_priv->pipeA_x = x;
1421                 master_priv->sarea_priv->pipeA_y = y;
1422         }
1423
1424         return 0;
1425 }
1426
1427 /* Disable the VGA plane that we never use */
1428 static void i915_disable_vga (struct drm_device *dev)
1429 {
1430         struct drm_i915_private *dev_priv = dev->dev_private;
1431         u8 sr1;
1432         u32 vga_reg;
1433
1434         if (HAS_PCH_SPLIT(dev))
1435                 vga_reg = CPU_VGACNTRL;
1436         else
1437                 vga_reg = VGACNTRL;
1438
1439         if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1440                 return;
1441
1442         I915_WRITE8(VGA_SR_INDEX, 1);
1443         sr1 = I915_READ8(VGA_SR_DATA);
1444         I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1445         udelay(100);
1446
1447         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1448 }
1449
1450 static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
1451 {
1452         struct drm_device *dev = crtc->dev;
1453         struct drm_i915_private *dev_priv = dev->dev_private;
1454         u32 dpa_ctl;
1455
1456         DRM_DEBUG_KMS("\n");
1457         dpa_ctl = I915_READ(DP_A);
1458         dpa_ctl &= ~DP_PLL_ENABLE;
1459         I915_WRITE(DP_A, dpa_ctl);
1460 }
1461
1462 static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
1463 {
1464         struct drm_device *dev = crtc->dev;
1465         struct drm_i915_private *dev_priv = dev->dev_private;
1466         u32 dpa_ctl;
1467
1468         dpa_ctl = I915_READ(DP_A);
1469         dpa_ctl |= DP_PLL_ENABLE;
1470         I915_WRITE(DP_A, dpa_ctl);
1471         udelay(200);
1472 }
1473
1474
1475 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1476 {
1477         struct drm_device *dev = crtc->dev;
1478         struct drm_i915_private *dev_priv = dev->dev_private;
1479         u32 dpa_ctl;
1480
1481         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1482         dpa_ctl = I915_READ(DP_A);
1483         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1484
1485         if (clock < 200000) {
1486                 u32 temp;
1487                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1488                 /* workaround for 160Mhz:
1489                    1) program 0x4600c bits 15:0 = 0x8124
1490                    2) program 0x46010 bit 0 = 1
1491                    3) program 0x46034 bit 24 = 1
1492                    4) program 0x64000 bit 14 = 1
1493                    */
1494                 temp = I915_READ(0x4600c);
1495                 temp &= 0xffff0000;
1496                 I915_WRITE(0x4600c, temp | 0x8124);
1497
1498                 temp = I915_READ(0x46010);
1499                 I915_WRITE(0x46010, temp | 1);
1500
1501                 temp = I915_READ(0x46034);
1502                 I915_WRITE(0x46034, temp | (1 << 24));
1503         } else {
1504                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1505         }
1506         I915_WRITE(DP_A, dpa_ctl);
1507
1508         udelay(500);
1509 }
1510
1511 /* The FDI link training functions for ILK/Ibexpeak. */
1512 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1513 {
1514         struct drm_device *dev = crtc->dev;
1515         struct drm_i915_private *dev_priv = dev->dev_private;
1516         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1517         int pipe = intel_crtc->pipe;
1518         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1519         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1520         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1521         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1522         u32 temp, tries = 0;
1523
1524         /* enable CPU FDI TX and PCH FDI RX */
1525         temp = I915_READ(fdi_tx_reg);
1526         temp |= FDI_TX_ENABLE;
1527         temp |= FDI_DP_PORT_WIDTH_X4; /* default */
1528         temp &= ~FDI_LINK_TRAIN_NONE;
1529         temp |= FDI_LINK_TRAIN_PATTERN_1;
1530         I915_WRITE(fdi_tx_reg, temp);
1531         I915_READ(fdi_tx_reg);
1532
1533         temp = I915_READ(fdi_rx_reg);
1534         temp &= ~FDI_LINK_TRAIN_NONE;
1535         temp |= FDI_LINK_TRAIN_PATTERN_1;
1536         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1537         I915_READ(fdi_rx_reg);
1538         udelay(150);
1539
1540         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1541            for train result */
1542         temp = I915_READ(fdi_rx_imr_reg);
1543         temp &= ~FDI_RX_SYMBOL_LOCK;
1544         temp &= ~FDI_RX_BIT_LOCK;
1545         I915_WRITE(fdi_rx_imr_reg, temp);
1546         I915_READ(fdi_rx_imr_reg);
1547         udelay(150);
1548
1549         for (;;) {
1550                 temp = I915_READ(fdi_rx_iir_reg);
1551                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1552
1553                 if ((temp & FDI_RX_BIT_LOCK)) {
1554                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1555                         I915_WRITE(fdi_rx_iir_reg,
1556                                    temp | FDI_RX_BIT_LOCK);
1557                         break;
1558                 }
1559
1560                 tries++;
1561
1562                 if (tries > 5) {
1563                         DRM_DEBUG_KMS("FDI train 1 fail!\n");
1564                         break;
1565                 }
1566         }
1567
1568         /* Train 2 */
1569         temp = I915_READ(fdi_tx_reg);
1570         temp &= ~FDI_LINK_TRAIN_NONE;
1571         temp |= FDI_LINK_TRAIN_PATTERN_2;
1572         I915_WRITE(fdi_tx_reg, temp);
1573
1574         temp = I915_READ(fdi_rx_reg);
1575         temp &= ~FDI_LINK_TRAIN_NONE;
1576         temp |= FDI_LINK_TRAIN_PATTERN_2;
1577         I915_WRITE(fdi_rx_reg, temp);
1578         udelay(150);
1579
1580         tries = 0;
1581
1582         for (;;) {
1583                 temp = I915_READ(fdi_rx_iir_reg);
1584                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1585
1586                 if (temp & FDI_RX_SYMBOL_LOCK) {
1587                         I915_WRITE(fdi_rx_iir_reg,
1588                                    temp | FDI_RX_SYMBOL_LOCK);
1589                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1590                         break;
1591                 }
1592
1593                 tries++;
1594
1595                 if (tries > 5) {
1596                         DRM_DEBUG_KMS("FDI train 2 fail!\n");
1597                         break;
1598                 }
1599         }
1600
1601         DRM_DEBUG_KMS("FDI train done\n");
1602 }
1603
1604 static int snb_b_fdi_train_param [] = {
1605         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1606         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1607         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1608         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1609 };
1610
1611 /* The FDI link training functions for SNB/Cougarpoint. */
1612 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1613 {
1614         struct drm_device *dev = crtc->dev;
1615         struct drm_i915_private *dev_priv = dev->dev_private;
1616         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1617         int pipe = intel_crtc->pipe;
1618         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1619         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1620         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1621         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1622         u32 temp, i;
1623
1624         /* enable CPU FDI TX and PCH FDI RX */
1625         temp = I915_READ(fdi_tx_reg);
1626         temp |= FDI_TX_ENABLE;
1627         temp |= FDI_DP_PORT_WIDTH_X4; /* default */
1628         temp &= ~FDI_LINK_TRAIN_NONE;
1629         temp |= FDI_LINK_TRAIN_PATTERN_1;
1630         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1631         /* SNB-B */
1632         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1633         I915_WRITE(fdi_tx_reg, temp);
1634         I915_READ(fdi_tx_reg);
1635
1636         temp = I915_READ(fdi_rx_reg);
1637         if (HAS_PCH_CPT(dev)) {
1638                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1639                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1640         } else {
1641                 temp &= ~FDI_LINK_TRAIN_NONE;
1642                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1643         }
1644         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1645         I915_READ(fdi_rx_reg);
1646         udelay(150);
1647
1648         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1649            for train result */
1650         temp = I915_READ(fdi_rx_imr_reg);
1651         temp &= ~FDI_RX_SYMBOL_LOCK;
1652         temp &= ~FDI_RX_BIT_LOCK;
1653         I915_WRITE(fdi_rx_imr_reg, temp);
1654         I915_READ(fdi_rx_imr_reg);
1655         udelay(150);
1656
1657         for (i = 0; i < 4; i++ ) {
1658                 temp = I915_READ(fdi_tx_reg);
1659                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1660                 temp |= snb_b_fdi_train_param[i];
1661                 I915_WRITE(fdi_tx_reg, temp);
1662                 udelay(500);
1663
1664                 temp = I915_READ(fdi_rx_iir_reg);
1665                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1666
1667                 if (temp & FDI_RX_BIT_LOCK) {
1668                         I915_WRITE(fdi_rx_iir_reg,
1669                                    temp | FDI_RX_BIT_LOCK);
1670                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1671                         break;
1672                 }
1673         }
1674         if (i == 4)
1675                 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1676
1677         /* Train 2 */
1678         temp = I915_READ(fdi_tx_reg);
1679         temp &= ~FDI_LINK_TRAIN_NONE;
1680         temp |= FDI_LINK_TRAIN_PATTERN_2;
1681         if (IS_GEN6(dev)) {
1682                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1683                 /* SNB-B */
1684                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1685         }
1686         I915_WRITE(fdi_tx_reg, temp);
1687
1688         temp = I915_READ(fdi_rx_reg);
1689         if (HAS_PCH_CPT(dev)) {
1690                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1691                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1692         } else {
1693                 temp &= ~FDI_LINK_TRAIN_NONE;
1694                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1695         }
1696         I915_WRITE(fdi_rx_reg, temp);
1697         udelay(150);
1698
1699         for (i = 0; i < 4; i++ ) {
1700                 temp = I915_READ(fdi_tx_reg);
1701                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1702                 temp |= snb_b_fdi_train_param[i];
1703                 I915_WRITE(fdi_tx_reg, temp);
1704                 udelay(500);
1705
1706                 temp = I915_READ(fdi_rx_iir_reg);
1707                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1708
1709                 if (temp & FDI_RX_SYMBOL_LOCK) {
1710                         I915_WRITE(fdi_rx_iir_reg,
1711                                    temp | FDI_RX_SYMBOL_LOCK);
1712                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1713                         break;
1714                 }
1715         }
1716         if (i == 4)
1717                 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1718
1719         DRM_DEBUG_KMS("FDI train done.\n");
1720 }
1721
1722 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1723 {
1724         struct drm_device *dev = crtc->dev;
1725         struct drm_i915_private *dev_priv = dev->dev_private;
1726         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1727         int pipe = intel_crtc->pipe;
1728         int plane = intel_crtc->plane;
1729         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1730         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1731         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1732         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1733         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1734         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1735         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1736         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1737         int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1738         int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1739         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1740         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1741         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1742         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1743         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1744         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1745         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1746         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1747         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1748         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1749         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1750         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1751         int trans_dpll_sel = (pipe == 0) ? 0 : 1;
1752         u32 temp;
1753         int n;
1754         u32 pipe_bpc;
1755
1756         temp = I915_READ(pipeconf_reg);
1757         pipe_bpc = temp & PIPE_BPC_MASK;
1758
1759         /* XXX: When our outputs are all unaware of DPMS modes other than off
1760          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1761          */
1762         switch (mode) {
1763         case DRM_MODE_DPMS_ON:
1764         case DRM_MODE_DPMS_STANDBY:
1765         case DRM_MODE_DPMS_SUSPEND:
1766                 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
1767
1768                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1769                         temp = I915_READ(PCH_LVDS);
1770                         if ((temp & LVDS_PORT_EN) == 0) {
1771                                 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1772                                 POSTING_READ(PCH_LVDS);
1773                         }
1774                 }
1775
1776                 if (HAS_eDP) {
1777                         /* enable eDP PLL */
1778                         ironlake_enable_pll_edp(crtc);
1779                 } else {
1780
1781                         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1782                         temp = I915_READ(fdi_rx_reg);
1783                         /*
1784                          * make the BPC in FDI Rx be consistent with that in
1785                          * pipeconf reg.
1786                          */
1787                         temp &= ~(0x7 << 16);
1788                         temp |= (pipe_bpc << 11);
1789                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
1790                                         FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
1791                         I915_READ(fdi_rx_reg);
1792                         udelay(200);
1793
1794                         /* Switch from Rawclk to PCDclk */
1795                         temp = I915_READ(fdi_rx_reg);
1796                         I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
1797                         I915_READ(fdi_rx_reg);
1798                         udelay(200);
1799
1800                         /* Enable CPU FDI TX PLL, always on for Ironlake */
1801                         temp = I915_READ(fdi_tx_reg);
1802                         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1803                                 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1804                                 I915_READ(fdi_tx_reg);
1805                                 udelay(100);
1806                         }
1807                 }
1808
1809                 /* Enable panel fitting for LVDS */
1810                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1811                         temp = I915_READ(pf_ctl_reg);
1812                         I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1813
1814                         /* currently full aspect */
1815                         I915_WRITE(pf_win_pos, 0);
1816
1817                         I915_WRITE(pf_win_size,
1818                                    (dev_priv->panel_fixed_mode->hdisplay << 16) |
1819                                    (dev_priv->panel_fixed_mode->vdisplay));
1820                 }
1821
1822                 /* Enable CPU pipe */
1823                 temp = I915_READ(pipeconf_reg);
1824                 if ((temp & PIPEACONF_ENABLE) == 0) {
1825                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1826                         I915_READ(pipeconf_reg);
1827                         udelay(100);
1828                 }
1829
1830                 /* configure and enable CPU plane */
1831                 temp = I915_READ(dspcntr_reg);
1832                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1833                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1834                         /* Flush the plane changes */
1835                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1836                 }
1837
1838                 if (!HAS_eDP) {
1839                         /* For PCH output, training FDI link */
1840                         if (IS_GEN6(dev))
1841                                 gen6_fdi_link_train(crtc);
1842                         else
1843                                 ironlake_fdi_link_train(crtc);
1844
1845                         /* enable PCH DPLL */
1846                         temp = I915_READ(pch_dpll_reg);
1847                         if ((temp & DPLL_VCO_ENABLE) == 0) {
1848                                 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1849                                 I915_READ(pch_dpll_reg);
1850                         }
1851                         udelay(200);
1852
1853                         if (HAS_PCH_CPT(dev)) {
1854                                 /* Be sure PCH DPLL SEL is set */
1855                                 temp = I915_READ(PCH_DPLL_SEL);
1856                                 if (trans_dpll_sel == 0 &&
1857                                                 (temp & TRANSA_DPLL_ENABLE) == 0)
1858                                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
1859                                 else if (trans_dpll_sel == 1 &&
1860                                                 (temp & TRANSB_DPLL_ENABLE) == 0)
1861                                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
1862                                 I915_WRITE(PCH_DPLL_SEL, temp);
1863                                 I915_READ(PCH_DPLL_SEL);
1864                         }
1865
1866                         /* set transcoder timing */
1867                         I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1868                         I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1869                         I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1870
1871                         I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1872                         I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1873                         I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1874
1875                         /* enable normal train */
1876                         temp = I915_READ(fdi_tx_reg);
1877                         temp &= ~FDI_LINK_TRAIN_NONE;
1878                         I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1879                                         FDI_TX_ENHANCE_FRAME_ENABLE);
1880                         I915_READ(fdi_tx_reg);
1881
1882                         temp = I915_READ(fdi_rx_reg);
1883                         if (HAS_PCH_CPT(dev)) {
1884                                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1885                                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
1886                         } else {
1887                                 temp &= ~FDI_LINK_TRAIN_NONE;
1888                                 temp |= FDI_LINK_TRAIN_NONE;
1889                         }
1890                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
1891                         I915_READ(fdi_rx_reg);
1892
1893                         /* wait one idle pattern time */
1894                         udelay(100);
1895
1896                         /* enable PCH transcoder */
1897                         temp = I915_READ(transconf_reg);
1898                         /*
1899                          * make the BPC in transcoder be consistent with
1900                          * that in pipeconf reg.
1901                          */
1902                         temp &= ~PIPE_BPC_MASK;
1903                         temp |= pipe_bpc;
1904                         I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1905                         I915_READ(transconf_reg);
1906
1907                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1908                                 ;
1909
1910                 }
1911
1912                 intel_crtc_load_lut(crtc);
1913
1914         break;
1915         case DRM_MODE_DPMS_OFF:
1916                 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
1917
1918                 drm_vblank_off(dev, pipe);
1919                 /* Disable display plane */
1920                 temp = I915_READ(dspcntr_reg);
1921                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1922                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1923                         /* Flush the plane changes */
1924                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1925                         I915_READ(dspbase_reg);
1926                 }
1927
1928                 i915_disable_vga(dev);
1929
1930                 /* disable cpu pipe, disable after all planes disabled */
1931                 temp = I915_READ(pipeconf_reg);
1932                 if ((temp & PIPEACONF_ENABLE) != 0) {
1933                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1934                         I915_READ(pipeconf_reg);
1935                         n = 0;
1936                         /* wait for cpu pipe off, pipe state */
1937                         while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
1938                                 n++;
1939                                 if (n < 60) {
1940                                         udelay(500);
1941                                         continue;
1942                                 } else {
1943                                         DRM_DEBUG_KMS("pipe %d off delay\n",
1944                                                                 pipe);
1945                                         break;
1946                                 }
1947                         }
1948                 } else
1949                         DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
1950
1951                 udelay(100);
1952
1953                 /* Disable PF */
1954                 temp = I915_READ(pf_ctl_reg);
1955                 if ((temp & PF_ENABLE) != 0) {
1956                         I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1957                         I915_READ(pf_ctl_reg);
1958                 }
1959                 I915_WRITE(pf_win_size, 0);
1960                 POSTING_READ(pf_win_size);
1961
1962
1963                 /* disable CPU FDI tx and PCH FDI rx */
1964                 temp = I915_READ(fdi_tx_reg);
1965                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
1966                 I915_READ(fdi_tx_reg);
1967
1968                 temp = I915_READ(fdi_rx_reg);
1969                 /* BPC in FDI rx is consistent with that in pipeconf */
1970                 temp &= ~(0x07 << 16);
1971                 temp |= (pipe_bpc << 11);
1972                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
1973                 I915_READ(fdi_rx_reg);
1974
1975                 udelay(100);
1976
1977                 /* still set train pattern 1 */
1978                 temp = I915_READ(fdi_tx_reg);
1979                 temp &= ~FDI_LINK_TRAIN_NONE;
1980                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1981                 I915_WRITE(fdi_tx_reg, temp);
1982                 POSTING_READ(fdi_tx_reg);
1983
1984                 temp = I915_READ(fdi_rx_reg);
1985                 if (HAS_PCH_CPT(dev)) {
1986                         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1987                         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1988                 } else {
1989                         temp &= ~FDI_LINK_TRAIN_NONE;
1990                         temp |= FDI_LINK_TRAIN_PATTERN_1;
1991                 }
1992                 I915_WRITE(fdi_rx_reg, temp);
1993                 POSTING_READ(fdi_rx_reg);
1994
1995                 udelay(100);
1996
1997                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1998                         temp = I915_READ(PCH_LVDS);
1999                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2000                         I915_READ(PCH_LVDS);
2001                         udelay(100);
2002                 }
2003
2004                 /* disable PCH transcoder */
2005                 temp = I915_READ(transconf_reg);
2006                 if ((temp & TRANS_ENABLE) != 0) {
2007                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
2008                         I915_READ(transconf_reg);
2009                         n = 0;
2010                         /* wait for PCH transcoder off, transcoder state */
2011                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
2012                                 n++;
2013                                 if (n < 60) {
2014                                         udelay(500);
2015                                         continue;
2016                                 } else {
2017                                         DRM_DEBUG_KMS("transcoder %d off "
2018                                                         "delay\n", pipe);
2019                                         break;
2020                                 }
2021                         }
2022                 }
2023
2024                 temp = I915_READ(transconf_reg);
2025                 /* BPC in transcoder is consistent with that in pipeconf */
2026                 temp &= ~PIPE_BPC_MASK;
2027                 temp |= pipe_bpc;
2028                 I915_WRITE(transconf_reg, temp);
2029                 I915_READ(transconf_reg);
2030                 udelay(100);
2031
2032                 if (HAS_PCH_CPT(dev)) {
2033
2034                         /* disable DPLL_SEL */
2035                         temp = I915_READ(PCH_DPLL_SEL);
2036                         if (trans_dpll_sel == 0)
2037                                 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2038                         else
2039                                 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2040                         I915_WRITE(PCH_DPLL_SEL, temp);
2041                         I915_READ(PCH_DPLL_SEL);
2042
2043                 }
2044
2045                 /* disable PCH DPLL */
2046                 temp = I915_READ(pch_dpll_reg);
2047                 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
2048                 I915_READ(pch_dpll_reg);
2049
2050                 if (HAS_eDP) {
2051                         ironlake_disable_pll_edp(crtc);
2052                 }
2053
2054                 /* Switch from PCDclk to Rawclk */
2055                 temp = I915_READ(fdi_rx_reg);
2056                 temp &= ~FDI_SEL_PCDCLK;
2057                 I915_WRITE(fdi_rx_reg, temp);
2058                 I915_READ(fdi_rx_reg);
2059
2060                 /* Disable CPU FDI TX PLL */
2061                 temp = I915_READ(fdi_tx_reg);
2062                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
2063                 I915_READ(fdi_tx_reg);
2064                 udelay(100);
2065
2066                 temp = I915_READ(fdi_rx_reg);
2067                 temp &= ~FDI_RX_PLL_ENABLE;
2068                 I915_WRITE(fdi_rx_reg, temp);
2069                 I915_READ(fdi_rx_reg);
2070
2071                 /* Wait for the clocks to turn off. */
2072                 udelay(100);
2073                 break;
2074         }
2075 }
2076
2077 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2078 {
2079         struct intel_overlay *overlay;
2080         int ret;
2081
2082         if (!enable && intel_crtc->overlay) {
2083                 overlay = intel_crtc->overlay;
2084                 mutex_lock(&overlay->dev->struct_mutex);
2085                 for (;;) {
2086                         ret = intel_overlay_switch_off(overlay);
2087                         if (ret == 0)
2088                                 break;
2089
2090                         ret = intel_overlay_recover_from_interrupt(overlay, 0);
2091                         if (ret != 0) {
2092                                 /* overlay doesn't react anymore. Usually
2093                                  * results in a black screen and an unkillable
2094                                  * X server. */
2095                                 BUG();
2096                                 overlay->hw_wedged = HW_WEDGED;
2097                                 break;
2098                         }
2099                 }
2100                 mutex_unlock(&overlay->dev->struct_mutex);
2101         }
2102         /* Let userspace switch the overlay on again. In most cases userspace
2103          * has to recompute where to put it anyway. */
2104
2105         return;
2106 }
2107
2108 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2109 {
2110         struct drm_device *dev = crtc->dev;
2111         struct drm_i915_private *dev_priv = dev->dev_private;
2112         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2113         int pipe = intel_crtc->pipe;
2114         int plane = intel_crtc->plane;
2115         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2116         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2117         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
2118         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2119         u32 temp;
2120
2121         /* XXX: When our outputs are all unaware of DPMS modes other than off
2122          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2123          */
2124         switch (mode) {
2125         case DRM_MODE_DPMS_ON:
2126         case DRM_MODE_DPMS_STANDBY:
2127         case DRM_MODE_DPMS_SUSPEND:
2128                 intel_update_watermarks(dev);
2129
2130                 /* Enable the DPLL */
2131                 temp = I915_READ(dpll_reg);
2132                 if ((temp & DPLL_VCO_ENABLE) == 0) {
2133                         I915_WRITE(dpll_reg, temp);
2134                         I915_READ(dpll_reg);
2135                         /* Wait for the clocks to stabilize. */
2136                         udelay(150);
2137                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2138                         I915_READ(dpll_reg);
2139                         /* Wait for the clocks to stabilize. */
2140                         udelay(150);
2141                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2142                         I915_READ(dpll_reg);
2143                         /* Wait for the clocks to stabilize. */
2144                         udelay(150);
2145                 }
2146
2147                 /* Enable the pipe */
2148                 temp = I915_READ(pipeconf_reg);
2149                 if ((temp & PIPEACONF_ENABLE) == 0)
2150                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2151
2152                 /* Enable the plane */
2153                 temp = I915_READ(dspcntr_reg);
2154                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2155                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2156                         /* Flush the plane changes */
2157                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2158                 }
2159
2160                 intel_crtc_load_lut(crtc);
2161
2162                 if ((IS_I965G(dev) || plane == 0))
2163                         intel_update_fbc(crtc, &crtc->mode);
2164
2165                 /* Give the overlay scaler a chance to enable if it's on this pipe */
2166                 intel_crtc_dpms_overlay(intel_crtc, true);
2167         break;
2168         case DRM_MODE_DPMS_OFF:
2169                 intel_update_watermarks(dev);
2170
2171                 /* Give the overlay scaler a chance to disable if it's on this pipe */
2172                 intel_crtc_dpms_overlay(intel_crtc, false);
2173                 drm_vblank_off(dev, pipe);
2174
2175                 if (dev_priv->cfb_plane == plane &&
2176                     dev_priv->display.disable_fbc)
2177                         dev_priv->display.disable_fbc(dev);
2178
2179                 /* Disable the VGA plane that we never use */
2180                 i915_disable_vga(dev);
2181
2182                 /* Disable display plane */
2183                 temp = I915_READ(dspcntr_reg);
2184                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2185                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2186                         /* Flush the plane changes */
2187                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2188                         I915_READ(dspbase_reg);
2189                 }
2190
2191                 if (!IS_I9XX(dev)) {
2192                         /* Wait for vblank for the disable to take effect */
2193                         intel_wait_for_vblank(dev);
2194                 }
2195
2196                 /* Next, disable display pipes */
2197                 temp = I915_READ(pipeconf_reg);
2198                 if ((temp & PIPEACONF_ENABLE) != 0) {
2199                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2200                         I915_READ(pipeconf_reg);
2201                 }
2202
2203                 /* Wait for vblank for the disable to take effect. */
2204                 intel_wait_for_vblank(dev);
2205
2206                 temp = I915_READ(dpll_reg);
2207                 if ((temp & DPLL_VCO_ENABLE) != 0) {
2208                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
2209                         I915_READ(dpll_reg);
2210                 }
2211
2212                 /* Wait for the clocks to turn off. */
2213                 udelay(150);
2214                 break;
2215         }
2216 }
2217
2218 /**
2219  * Sets the power management mode of the pipe and plane.
2220  *
2221  * This code should probably grow support for turning the cursor off and back
2222  * on appropriately at the same time as we're turning the pipe off/on.
2223  */
2224 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2225 {
2226         struct drm_device *dev = crtc->dev;
2227         struct drm_i915_private *dev_priv = dev->dev_private;
2228         struct drm_i915_master_private *master_priv;
2229         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2230         int pipe = intel_crtc->pipe;
2231         bool enabled;
2232
2233         dev_priv->display.dpms(crtc, mode);
2234
2235         intel_crtc->dpms_mode = mode;
2236
2237         if (!dev->primary->master)
2238                 return;
2239
2240         master_priv = dev->primary->master->driver_priv;
2241         if (!master_priv->sarea_priv)
2242                 return;
2243
2244         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2245
2246         switch (pipe) {
2247         case 0:
2248                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2249                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2250                 break;
2251         case 1:
2252                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2253                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2254                 break;
2255         default:
2256                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2257                 break;
2258         }
2259 }
2260
2261 static void intel_crtc_prepare (struct drm_crtc *crtc)
2262 {
2263         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2264         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2265 }
2266
2267 static void intel_crtc_commit (struct drm_crtc *crtc)
2268 {
2269         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2270         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2271 }
2272
2273 void intel_encoder_prepare (struct drm_encoder *encoder)
2274 {
2275         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2276         /* lvds has its own version of prepare see intel_lvds_prepare */
2277         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2278 }
2279
2280 void intel_encoder_commit (struct drm_encoder *encoder)
2281 {
2282         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2283         /* lvds has its own version of commit see intel_lvds_commit */
2284         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2285 }
2286
2287 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2288                                   struct drm_display_mode *mode,
2289                                   struct drm_display_mode *adjusted_mode)
2290 {
2291         struct drm_device *dev = crtc->dev;
2292         if (HAS_PCH_SPLIT(dev)) {
2293                 /* FDI link clock is fixed at 2.7G */
2294                 if (mode->clock * 3 > 27000 * 4)
2295                         return MODE_CLOCK_HIGH;
2296         }
2297         return true;
2298 }
2299
2300 static int i945_get_display_clock_speed(struct drm_device *dev)
2301 {
2302         return 400000;
2303 }
2304
2305 static int i915_get_display_clock_speed(struct drm_device *dev)
2306 {
2307         return 333000;
2308 }
2309
2310 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2311 {
2312         return 200000;
2313 }
2314
2315 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2316 {
2317         u16 gcfgc = 0;
2318
2319         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2320
2321         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2322                 return 133000;
2323         else {
2324                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2325                 case GC_DISPLAY_CLOCK_333_MHZ:
2326                         return 333000;
2327                 default:
2328                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2329                         return 190000;
2330                 }
2331         }
2332 }
2333
2334 static int i865_get_display_clock_speed(struct drm_device *dev)
2335 {
2336         return 266000;
2337 }
2338
2339 static int i855_get_display_clock_speed(struct drm_device *dev)
2340 {
2341         u16 hpllcc = 0;
2342         /* Assume that the hardware is in the high speed state.  This
2343          * should be the default.
2344          */
2345         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2346         case GC_CLOCK_133_200:
2347         case GC_CLOCK_100_200:
2348                 return 200000;
2349         case GC_CLOCK_166_250:
2350                 return 250000;
2351         case GC_CLOCK_100_133:
2352                 return 133000;
2353         }
2354
2355         /* Shouldn't happen */
2356         return 0;
2357 }
2358
2359 static int i830_get_display_clock_speed(struct drm_device *dev)
2360 {
2361         return 133000;
2362 }
2363
2364 /**
2365  * Return the pipe currently connected to the panel fitter,
2366  * or -1 if the panel fitter is not present or not in use
2367  */
2368 int intel_panel_fitter_pipe (struct drm_device *dev)
2369 {
2370         struct drm_i915_private *dev_priv = dev->dev_private;
2371         u32  pfit_control;
2372
2373         /* i830 doesn't have a panel fitter */
2374         if (IS_I830(dev))
2375                 return -1;
2376
2377         pfit_control = I915_READ(PFIT_CONTROL);
2378
2379         /* See if the panel fitter is in use */
2380         if ((pfit_control & PFIT_ENABLE) == 0)
2381                 return -1;
2382
2383         /* 965 can place panel fitter on either pipe */
2384         if (IS_I965G(dev))
2385                 return (pfit_control >> 29) & 0x3;
2386
2387         /* older chips can only use pipe 1 */
2388         return 1;
2389 }
2390
2391 struct fdi_m_n {
2392         u32        tu;
2393         u32        gmch_m;
2394         u32        gmch_n;
2395         u32        link_m;
2396         u32        link_n;
2397 };
2398
2399 static void
2400 fdi_reduce_ratio(u32 *num, u32 *den)
2401 {
2402         while (*num > 0xffffff || *den > 0xffffff) {
2403                 *num >>= 1;
2404                 *den >>= 1;
2405         }
2406 }
2407
2408 #define DATA_N 0x800000
2409 #define LINK_N 0x80000
2410
2411 static void
2412 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2413                      int link_clock, struct fdi_m_n *m_n)
2414 {
2415         u64 temp;
2416
2417         m_n->tu = 64; /* default size */
2418
2419         temp = (u64) DATA_N * pixel_clock;
2420         temp = div_u64(temp, link_clock);
2421         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2422         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2423         m_n->gmch_n = DATA_N;
2424         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2425
2426         temp = (u64) LINK_N * pixel_clock;
2427         m_n->link_m = div_u64(temp, link_clock);
2428         m_n->link_n = LINK_N;
2429         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2430 }
2431
2432
2433 struct intel_watermark_params {
2434         unsigned long fifo_size;
2435         unsigned long max_wm;
2436         unsigned long default_wm;
2437         unsigned long guard_size;
2438         unsigned long cacheline_size;
2439 };
2440
2441 /* Pineview has different values for various configs */
2442 static struct intel_watermark_params pineview_display_wm = {
2443         PINEVIEW_DISPLAY_FIFO,
2444         PINEVIEW_MAX_WM,
2445         PINEVIEW_DFT_WM,
2446         PINEVIEW_GUARD_WM,
2447         PINEVIEW_FIFO_LINE_SIZE
2448 };
2449 static struct intel_watermark_params pineview_display_hplloff_wm = {
2450         PINEVIEW_DISPLAY_FIFO,
2451         PINEVIEW_MAX_WM,
2452         PINEVIEW_DFT_HPLLOFF_WM,
2453         PINEVIEW_GUARD_WM,
2454         PINEVIEW_FIFO_LINE_SIZE
2455 };
2456 static struct intel_watermark_params pineview_cursor_wm = {
2457         PINEVIEW_CURSOR_FIFO,
2458         PINEVIEW_CURSOR_MAX_WM,
2459         PINEVIEW_CURSOR_DFT_WM,
2460         PINEVIEW_CURSOR_GUARD_WM,
2461         PINEVIEW_FIFO_LINE_SIZE,
2462 };
2463 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2464         PINEVIEW_CURSOR_FIFO,
2465         PINEVIEW_CURSOR_MAX_WM,
2466         PINEVIEW_CURSOR_DFT_WM,
2467         PINEVIEW_CURSOR_GUARD_WM,
2468         PINEVIEW_FIFO_LINE_SIZE
2469 };
2470 static struct intel_watermark_params g4x_wm_info = {
2471         G4X_FIFO_SIZE,
2472         G4X_MAX_WM,
2473         G4X_MAX_WM,
2474         2,
2475         G4X_FIFO_LINE_SIZE,
2476 };
2477 static struct intel_watermark_params i945_wm_info = {
2478         I945_FIFO_SIZE,
2479         I915_MAX_WM,
2480         1,
2481         2,
2482         I915_FIFO_LINE_SIZE
2483 };
2484 static struct intel_watermark_params i915_wm_info = {
2485         I915_FIFO_SIZE,
2486         I915_MAX_WM,
2487         1,
2488         2,
2489         I915_FIFO_LINE_SIZE
2490 };
2491 static struct intel_watermark_params i855_wm_info = {
2492         I855GM_FIFO_SIZE,
2493         I915_MAX_WM,
2494         1,
2495         2,
2496         I830_FIFO_LINE_SIZE
2497 };
2498 static struct intel_watermark_params i830_wm_info = {
2499         I830_FIFO_SIZE,
2500         I915_MAX_WM,
2501         1,
2502         2,
2503         I830_FIFO_LINE_SIZE
2504 };
2505
2506 /**
2507  * intel_calculate_wm - calculate watermark level
2508  * @clock_in_khz: pixel clock
2509  * @wm: chip FIFO params
2510  * @pixel_size: display pixel size
2511  * @latency_ns: memory latency for the platform
2512  *
2513  * Calculate the watermark level (the level at which the display plane will
2514  * start fetching from memory again).  Each chip has a different display
2515  * FIFO size and allocation, so the caller needs to figure that out and pass
2516  * in the correct intel_watermark_params structure.
2517  *
2518  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2519  * on the pixel size.  When it reaches the watermark level, it'll start
2520  * fetching FIFO line sized based chunks from memory until the FIFO fills
2521  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2522  * will occur, and a display engine hang could result.
2523  */
2524 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2525                                         struct intel_watermark_params *wm,
2526                                         int pixel_size,
2527                                         unsigned long latency_ns)
2528 {
2529         long entries_required, wm_size;
2530
2531         /*
2532          * Note: we need to make sure we don't overflow for various clock &
2533          * latency values.
2534          * clocks go from a few thousand to several hundred thousand.
2535          * latency is usually a few thousand
2536          */
2537         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2538                 1000;
2539         entries_required /= wm->cacheline_size;
2540
2541         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2542
2543         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2544
2545         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2546
2547         /* Don't promote wm_size to unsigned... */
2548         if (wm_size > (long)wm->max_wm)
2549                 wm_size = wm->max_wm;
2550         if (wm_size <= 0)
2551                 wm_size = wm->default_wm;
2552         return wm_size;
2553 }
2554
2555 struct cxsr_latency {
2556         int is_desktop;
2557         unsigned long fsb_freq;
2558         unsigned long mem_freq;
2559         unsigned long display_sr;
2560         unsigned long display_hpll_disable;
2561         unsigned long cursor_sr;
2562         unsigned long cursor_hpll_disable;
2563 };
2564
2565 static struct cxsr_latency cxsr_latency_table[] = {
2566         {1, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2567         {1, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2568         {1, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2569
2570         {1, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2571         {1, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2572         {1, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2573
2574         {1, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2575         {1, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2576         {1, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2577
2578         {0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2579         {0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2580         {0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2581
2582         {0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2583         {0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2584         {0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2585
2586         {0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2587         {0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2588         {0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2589 };
2590
2591 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
2592                                                    int mem)
2593 {
2594         int i;
2595         struct cxsr_latency *latency;
2596
2597         if (fsb == 0 || mem == 0)
2598                 return NULL;
2599
2600         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2601                 latency = &cxsr_latency_table[i];
2602                 if (is_desktop == latency->is_desktop &&
2603                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2604                         return latency;
2605         }
2606
2607         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2608
2609         return NULL;
2610 }
2611
2612 static void pineview_disable_cxsr(struct drm_device *dev)
2613 {
2614         struct drm_i915_private *dev_priv = dev->dev_private;
2615         u32 reg;
2616
2617         /* deactivate cxsr */
2618         reg = I915_READ(DSPFW3);
2619         reg &= ~(PINEVIEW_SELF_REFRESH_EN);
2620         I915_WRITE(DSPFW3, reg);
2621         DRM_INFO("Big FIFO is disabled\n");
2622 }
2623
2624 static void pineview_enable_cxsr(struct drm_device *dev, unsigned long clock,
2625                                  int pixel_size)
2626 {
2627         struct drm_i915_private *dev_priv = dev->dev_private;
2628         u32 reg;
2629         unsigned long wm;
2630         struct cxsr_latency *latency;
2631
2632         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->fsb_freq,
2633                 dev_priv->mem_freq);
2634         if (!latency) {
2635                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2636                 pineview_disable_cxsr(dev);
2637                 return;
2638         }
2639
2640         /* Display SR */
2641         wm = intel_calculate_wm(clock, &pineview_display_wm, pixel_size,
2642                                 latency->display_sr);
2643         reg = I915_READ(DSPFW1);
2644         reg &= 0x7fffff;
2645         reg |= wm << 23;
2646         I915_WRITE(DSPFW1, reg);
2647         DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2648
2649         /* cursor SR */
2650         wm = intel_calculate_wm(clock, &pineview_cursor_wm, pixel_size,
2651                                 latency->cursor_sr);
2652         reg = I915_READ(DSPFW3);
2653         reg &= ~(0x3f << 24);
2654         reg |= (wm & 0x3f) << 24;
2655         I915_WRITE(DSPFW3, reg);
2656
2657         /* Display HPLL off SR */
2658         wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
2659                 latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
2660         reg = I915_READ(DSPFW3);
2661         reg &= 0xfffffe00;
2662         reg |= wm & 0x1ff;
2663         I915_WRITE(DSPFW3, reg);
2664
2665         /* cursor HPLL off SR */
2666         wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, pixel_size,
2667                                 latency->cursor_hpll_disable);
2668         reg = I915_READ(DSPFW3);
2669         reg &= ~(0x3f << 16);
2670         reg |= (wm & 0x3f) << 16;
2671         I915_WRITE(DSPFW3, reg);
2672         DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2673
2674         /* activate cxsr */
2675         reg = I915_READ(DSPFW3);
2676         reg |= PINEVIEW_SELF_REFRESH_EN;
2677         I915_WRITE(DSPFW3, reg);
2678
2679         DRM_INFO("Big FIFO is enabled\n");
2680
2681         return;
2682 }
2683
2684 /*
2685  * Latency for FIFO fetches is dependent on several factors:
2686  *   - memory configuration (speed, channels)
2687  *   - chipset
2688  *   - current MCH state
2689  * It can be fairly high in some situations, so here we assume a fairly
2690  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2691  * set this value too high, the FIFO will fetch frequently to stay full)
2692  * and power consumption (set it too low to save power and we might see
2693  * FIFO underruns and display "flicker").
2694  *
2695  * A value of 5us seems to be a good balance; safe for very low end
2696  * platforms but not overly aggressive on lower latency configs.
2697  */
2698 static const int latency_ns = 5000;
2699
2700 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2701 {
2702         struct drm_i915_private *dev_priv = dev->dev_private;
2703         uint32_t dsparb = I915_READ(DSPARB);
2704         int size;
2705
2706         if (plane == 0)
2707                 size = dsparb & 0x7f;
2708         else
2709                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2710                         (dsparb & 0x7f);
2711
2712         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2713                         plane ? "B" : "A", size);
2714
2715         return size;
2716 }
2717
2718 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2719 {
2720         struct drm_i915_private *dev_priv = dev->dev_private;
2721         uint32_t dsparb = I915_READ(DSPARB);
2722         int size;
2723
2724         if (plane == 0)
2725                 size = dsparb & 0x1ff;
2726         else
2727                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2728                         (dsparb & 0x1ff);
2729         size >>= 1; /* Convert to cachelines */
2730
2731         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2732                         plane ? "B" : "A", size);
2733
2734         return size;
2735 }
2736
2737 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2738 {
2739         struct drm_i915_private *dev_priv = dev->dev_private;
2740         uint32_t dsparb = I915_READ(DSPARB);
2741         int size;
2742
2743         size = dsparb & 0x7f;
2744         size >>= 2; /* Convert to cachelines */
2745
2746         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2747                         plane ? "B" : "A",
2748                   size);
2749
2750         return size;
2751 }
2752
2753 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2754 {
2755         struct drm_i915_private *dev_priv = dev->dev_private;
2756         uint32_t dsparb = I915_READ(DSPARB);
2757         int size;
2758
2759         size = dsparb & 0x7f;
2760         size >>= 1; /* Convert to cachelines */
2761
2762         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2763                         plane ? "B" : "A", size);
2764
2765         return size;
2766 }
2767
2768 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
2769                           int planeb_clock, int sr_hdisplay, int pixel_size)
2770 {
2771         struct drm_i915_private *dev_priv = dev->dev_private;
2772         int total_size, cacheline_size;
2773         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
2774         struct intel_watermark_params planea_params, planeb_params;
2775         unsigned long line_time_us;
2776         int sr_clock, sr_entries = 0, entries_required;
2777
2778         /* Create copies of the base settings for each pipe */
2779         planea_params = planeb_params = g4x_wm_info;
2780
2781         /* Grab a couple of global values before we overwrite them */
2782         total_size = planea_params.fifo_size;
2783         cacheline_size = planea_params.cacheline_size;
2784
2785         /*
2786          * Note: we need to make sure we don't overflow for various clock &
2787          * latency values.
2788          * clocks go from a few thousand to several hundred thousand.
2789          * latency is usually a few thousand
2790          */
2791         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
2792                 1000;
2793         entries_required /= G4X_FIFO_LINE_SIZE;
2794         planea_wm = entries_required + planea_params.guard_size;
2795
2796         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
2797                 1000;
2798         entries_required /= G4X_FIFO_LINE_SIZE;
2799         planeb_wm = entries_required + planeb_params.guard_size;
2800
2801         cursora_wm = cursorb_wm = 16;
2802         cursor_sr = 32;
2803
2804         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2805
2806         /* Calc sr entries for one plane configs */
2807         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2808                 /* self-refresh has much higher latency */
2809                 static const int sr_latency_ns = 12000;
2810
2811                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2812                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2813
2814                 /* Use ns/us then divide to preserve precision */
2815                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2816                               pixel_size * sr_hdisplay) / 1000;
2817                 sr_entries = roundup(sr_entries / cacheline_size, 1);
2818                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2819                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2820         } else {
2821                 /* Turn off self refresh if both pipes are enabled */
2822                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2823                                         & ~FW_BLC_SELF_EN);
2824         }
2825
2826         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
2827                   planea_wm, planeb_wm, sr_entries);
2828
2829         planea_wm &= 0x3f;
2830         planeb_wm &= 0x3f;
2831
2832         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
2833                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
2834                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
2835         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
2836                    (cursora_wm << DSPFW_CURSORA_SHIFT));
2837         /* HPLL off in SR has some issues on G4x... disable it */
2838         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
2839                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
2840 }
2841
2842 static void i965_update_wm(struct drm_device *dev, int planea_clock,
2843                            int planeb_clock, int sr_hdisplay, int pixel_size)
2844 {
2845         struct drm_i915_private *dev_priv = dev->dev_private;
2846         unsigned long line_time_us;
2847         int sr_clock, sr_entries, srwm = 1;
2848
2849         /* Calc sr entries for one plane configs */
2850         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2851                 /* self-refresh has much higher latency */
2852                 static const int sr_latency_ns = 12000;
2853
2854                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2855                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2856
2857                 /* Use ns/us then divide to preserve precision */
2858                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2859                               pixel_size * sr_hdisplay) / 1000;
2860                 sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
2861                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2862                 srwm = I945_FIFO_SIZE - sr_entries;
2863                 if (srwm < 0)
2864                         srwm = 1;
2865                 srwm &= 0x3f;
2866                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2867         } else {
2868                 /* Turn off self refresh if both pipes are enabled */
2869                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2870                                         & ~FW_BLC_SELF_EN);
2871         }
2872
2873         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2874                       srwm);
2875
2876         /* 965 has limitations... */
2877         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
2878                    (8 << 0));
2879         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
2880 }
2881
2882 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2883                            int planeb_clock, int sr_hdisplay, int pixel_size)
2884 {
2885         struct drm_i915_private *dev_priv = dev->dev_private;
2886         uint32_t fwater_lo;
2887         uint32_t fwater_hi;
2888         int total_size, cacheline_size, cwm, srwm = 1;
2889         int planea_wm, planeb_wm;
2890         struct intel_watermark_params planea_params, planeb_params;
2891         unsigned long line_time_us;
2892         int sr_clock, sr_entries = 0;
2893
2894         /* Create copies of the base settings for each pipe */
2895         if (IS_I965GM(dev) || IS_I945GM(dev))
2896                 planea_params = planeb_params = i945_wm_info;
2897         else if (IS_I9XX(dev))
2898                 planea_params = planeb_params = i915_wm_info;
2899         else
2900                 planea_params = planeb_params = i855_wm_info;
2901
2902         /* Grab a couple of global values before we overwrite them */
2903         total_size = planea_params.fifo_size;
2904         cacheline_size = planea_params.cacheline_size;
2905
2906         /* Update per-plane FIFO sizes */
2907         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2908         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
2909
2910         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
2911                                        pixel_size, latency_ns);
2912         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
2913                                        pixel_size, latency_ns);
2914         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2915
2916         /*
2917          * Overlay gets an aggressive default since video jitter is bad.
2918          */
2919         cwm = 2;
2920
2921         /* Calc sr entries for one plane configs */
2922         if (HAS_FW_BLC(dev) && sr_hdisplay &&
2923             (!planea_clock || !planeb_clock)) {
2924                 /* self-refresh has much higher latency */
2925                 static const int sr_latency_ns = 6000;
2926
2927                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2928                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2929
2930                 /* Use ns/us then divide to preserve precision */
2931                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2932                               pixel_size * sr_hdisplay) / 1000;
2933                 sr_entries = roundup(sr_entries / cacheline_size, 1);
2934                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
2935                 srwm = total_size - sr_entries;
2936                 if (srwm < 0)
2937                         srwm = 1;
2938
2939                 if (IS_I945G(dev) || IS_I945GM(dev))
2940                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
2941                 else if (IS_I915GM(dev)) {
2942                         /* 915M has a smaller SRWM field */
2943                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
2944                         I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
2945                 }
2946         } else {
2947                 /* Turn off self refresh if both pipes are enabled */
2948                 if (IS_I945G(dev) || IS_I945GM(dev)) {
2949                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2950                                    & ~FW_BLC_SELF_EN);
2951                 } else if (IS_I915GM(dev)) {
2952                         I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
2953                 }
2954         }
2955
2956         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2957                   planea_wm, planeb_wm, cwm, srwm);
2958
2959         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
2960         fwater_hi = (cwm & 0x1f);
2961
2962         /* Set request length to 8 cachelines per fetch */
2963         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
2964         fwater_hi = fwater_hi | (1 << 8);
2965
2966         I915_WRITE(FW_BLC, fwater_lo);
2967         I915_WRITE(FW_BLC2, fwater_hi);
2968 }
2969
2970 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
2971                            int unused2, int pixel_size)
2972 {
2973         struct drm_i915_private *dev_priv = dev->dev_private;
2974         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
2975         int planea_wm;
2976
2977         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2978
2979         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
2980                                        pixel_size, latency_ns);
2981         fwater_lo |= (3<<8) | planea_wm;
2982
2983         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
2984
2985         I915_WRITE(FW_BLC, fwater_lo);
2986 }
2987
2988 /**
2989  * intel_update_watermarks - update FIFO watermark values based on current modes
2990  *
2991  * Calculate watermark values for the various WM regs based on current mode
2992  * and plane configuration.
2993  *
2994  * There are several cases to deal with here:
2995  *   - normal (i.e. non-self-refresh)
2996  *   - self-refresh (SR) mode
2997  *   - lines are large relative to FIFO size (buffer can hold up to 2)
2998  *   - lines are small relative to FIFO size (buffer can hold more than 2
2999  *     lines), so need to account for TLB latency
3000  *
3001  *   The normal calculation is:
3002  *     watermark = dotclock * bytes per pixel * latency
3003  *   where latency is platform & configuration dependent (we assume pessimal
3004  *   values here).
3005  *
3006  *   The SR calculation is:
3007  *     watermark = (trunc(latency/line time)+1) * surface width *
3008  *       bytes per pixel
3009  *   where
3010  *     line time = htotal / dotclock
3011  *   and latency is assumed to be high, as above.
3012  *
3013  * The final value programmed to the register should always be rounded up,
3014  * and include an extra 2 entries to account for clock crossings.
3015  *
3016  * We don't use the sprite, so we can ignore that.  And on Crestline we have
3017  * to set the non-SR watermarks to 8.
3018   */
3019 static void intel_update_watermarks(struct drm_device *dev)
3020 {
3021         struct drm_i915_private *dev_priv = dev->dev_private;
3022         struct drm_crtc *crtc;
3023         struct intel_crtc *intel_crtc;
3024         int sr_hdisplay = 0;
3025         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3026         int enabled = 0, pixel_size = 0;
3027
3028         if (!dev_priv->display.update_wm)
3029                 return;
3030
3031         /* Get the clock config from both planes */
3032         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3033                 intel_crtc = to_intel_crtc(crtc);
3034                 if (crtc->enabled) {
3035                         enabled++;
3036                         if (intel_crtc->plane == 0) {
3037                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3038                                           intel_crtc->pipe, crtc->mode.clock);
3039                                 planea_clock = crtc->mode.clock;
3040                         } else {
3041                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3042                                           intel_crtc->pipe, crtc->mode.clock);
3043                                 planeb_clock = crtc->mode.clock;
3044                         }
3045                         sr_hdisplay = crtc->mode.hdisplay;
3046                         sr_clock = crtc->mode.clock;
3047                         if (crtc->fb)
3048                                 pixel_size = crtc->fb->bits_per_pixel / 8;
3049                         else
3050                                 pixel_size = 4; /* by default */
3051                 }
3052         }
3053
3054         if (enabled <= 0)
3055                 return;
3056
3057         /* Single plane configs can enable self refresh */
3058         if (enabled == 1 && IS_PINEVIEW(dev))
3059                 pineview_enable_cxsr(dev, sr_clock, pixel_size);
3060         else if (IS_PINEVIEW(dev))
3061                 pineview_disable_cxsr(dev);
3062
3063         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3064                                     sr_hdisplay, pixel_size);
3065 }
3066
3067 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3068                                struct drm_display_mode *mode,
3069                                struct drm_display_mode *adjusted_mode,
3070                                int x, int y,
3071                                struct drm_framebuffer *old_fb)
3072 {
3073         struct drm_device *dev = crtc->dev;
3074         struct drm_i915_private *dev_priv = dev->dev_private;
3075         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3076         int pipe = intel_crtc->pipe;
3077         int plane = intel_crtc->plane;
3078         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
3079         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3080         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
3081         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
3082         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
3083         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
3084         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
3085         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
3086         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
3087         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
3088         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
3089         int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
3090         int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
3091         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
3092         int refclk, num_connectors = 0;
3093         intel_clock_t clock, reduced_clock;
3094         u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
3095         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3096         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3097         bool is_edp = false;
3098         struct drm_mode_config *mode_config = &dev->mode_config;
3099         struct drm_encoder *encoder;
3100         struct intel_encoder *intel_encoder;
3101         const intel_limit_t *limit;
3102         int ret;
3103         struct fdi_m_n m_n = {0};
3104         int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
3105         int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
3106         int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
3107         int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
3108         int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
3109         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
3110         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
3111         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
3112         int trans_dpll_sel = (pipe == 0) ? 0 : 1;
3113         int lvds_reg = LVDS;
3114         u32 temp;
3115         int sdvo_pixel_multiply;
3116         int target_clock;
3117
3118         drm_vblank_pre_modeset(dev, pipe);
3119
3120         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
3121
3122                 if (!encoder || encoder->crtc != crtc)
3123                         continue;
3124
3125                 intel_encoder = enc_to_intel_encoder(encoder);
3126
3127                 switch (intel_encoder->type) {
3128                 case INTEL_OUTPUT_LVDS:
3129                         is_lvds = true;
3130                         break;
3131                 case INTEL_OUTPUT_SDVO:
3132                 case INTEL_OUTPUT_HDMI:
3133                         is_sdvo = true;
3134                         if (intel_encoder->needs_tv_clock)
3135                                 is_tv = true;
3136                         break;
3137                 case INTEL_OUTPUT_DVO:
3138                         is_dvo = true;
3139                         break;
3140                 case INTEL_OUTPUT_TVOUT:
3141                         is_tv = true;
3142                         break;
3143                 case INTEL_OUTPUT_ANALOG:
3144                         is_crt = true;
3145                         break;
3146                 case INTEL_OUTPUT_DISPLAYPORT:
3147                         is_dp = true;
3148                         break;
3149                 case INTEL_OUTPUT_EDP:
3150                         is_edp = true;
3151                         break;
3152                 }
3153
3154                 num_connectors++;
3155         }
3156
3157         if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3158                 refclk = dev_priv->lvds_ssc_freq * 1000;
3159                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3160                                         refclk / 1000);
3161         } else if (IS_I9XX(dev)) {
3162                 refclk = 96000;
3163                 if (HAS_PCH_SPLIT(dev))
3164                         refclk = 120000; /* 120Mhz refclk */
3165         } else {
3166                 refclk = 48000;
3167         }
3168
3169
3170         /*
3171          * Returns a set of divisors for the desired target clock with the given
3172          * refclk, or FALSE.  The returned values represent the clock equation:
3173          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3174          */
3175         limit = intel_limit(crtc);
3176         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3177         if (!ok) {
3178                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3179                 drm_vblank_post_modeset(dev, pipe);
3180                 return -EINVAL;
3181         }
3182
3183         if (is_lvds && dev_priv->lvds_downclock_avail) {
3184                 has_reduced_clock = limit->find_pll(limit, crtc,
3185                                                             dev_priv->lvds_downclock,
3186                                                             refclk,
3187                                                             &reduced_clock);
3188                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3189                         /*
3190                          * If the different P is found, it means that we can't
3191                          * switch the display clock by using the FP0/FP1.
3192                          * In such case we will disable the LVDS downclock
3193                          * feature.
3194                          */
3195                         DRM_DEBUG_KMS("Different P is found for "
3196                                                 "LVDS clock/downclock\n");
3197                         has_reduced_clock = 0;
3198                 }
3199         }
3200         /* SDVO TV has fixed PLL values depend on its clock range,
3201            this mirrors vbios setting. */
3202         if (is_sdvo && is_tv) {
3203                 if (adjusted_mode->clock >= 100000
3204                                 && adjusted_mode->clock < 140500) {
3205                         clock.p1 = 2;
3206                         clock.p2 = 10;
3207                         clock.n = 3;
3208                         clock.m1 = 16;
3209                         clock.m2 = 8;
3210                 } else if (adjusted_mode->clock >= 140500
3211                                 && adjusted_mode->clock <= 200000) {
3212                         clock.p1 = 1;
3213                         clock.p2 = 10;
3214                         clock.n = 6;
3215                         clock.m1 = 12;
3216                         clock.m2 = 8;
3217                 }
3218         }
3219
3220         /* FDI link */
3221         if (HAS_PCH_SPLIT(dev)) {
3222                 int lane, link_bw, bpp;
3223                 /* eDP doesn't require FDI link, so just set DP M/N
3224                    according to current link config */
3225                 if (is_edp) {
3226                         struct drm_connector *edp;
3227                         target_clock = mode->clock;
3228                         edp = intel_pipe_get_connector(crtc);
3229                         intel_edp_link_config(to_intel_encoder(edp),
3230                                         &lane, &link_bw);
3231                 } else {
3232                         /* DP over FDI requires target mode clock
3233                            instead of link clock */
3234                         if (is_dp)
3235                                 target_clock = mode->clock;
3236                         else
3237                                 target_clock = adjusted_mode->clock;
3238                         lane = 4;
3239                         link_bw = 270000;
3240                 }
3241
3242                 /* determine panel color depth */
3243                 temp = I915_READ(pipeconf_reg);
3244                 temp &= ~PIPE_BPC_MASK;
3245                 if (is_lvds) {
3246                         int lvds_reg = I915_READ(PCH_LVDS);
3247                         /* the BPC will be 6 if it is 18-bit LVDS panel */
3248                         if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3249                                 temp |= PIPE_8BPC;
3250                         else
3251                                 temp |= PIPE_6BPC;
3252                 } else if (is_edp) {
3253                         switch (dev_priv->edp_bpp/3) {
3254                         case 8:
3255                                 temp |= PIPE_8BPC;
3256                                 break;
3257                         case 10:
3258                                 temp |= PIPE_10BPC;
3259                                 break;
3260                         case 6:
3261                                 temp |= PIPE_6BPC;
3262                                 break;
3263                         case 12:
3264                                 temp |= PIPE_12BPC;
3265                                 break;
3266                         }
3267                 } else
3268                         temp |= PIPE_8BPC;
3269                 I915_WRITE(pipeconf_reg, temp);
3270                 I915_READ(pipeconf_reg);
3271
3272                 switch (temp & PIPE_BPC_MASK) {
3273                 case PIPE_8BPC:
3274                         bpp = 24;
3275                         break;
3276                 case PIPE_10BPC:
3277                         bpp = 30;
3278                         break;
3279                 case PIPE_6BPC:
3280                         bpp = 18;
3281                         break;
3282                 case PIPE_12BPC:
3283                         bpp = 36;
3284                         break;
3285                 default:
3286                         DRM_ERROR("unknown pipe bpc value\n");
3287                         bpp = 24;
3288                 }
3289
3290                 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3291         }
3292
3293         /* Ironlake: try to setup display ref clock before DPLL
3294          * enabling. This is only under driver's control after
3295          * PCH B stepping, previous chipset stepping should be
3296          * ignoring this setting.
3297          */
3298         if (HAS_PCH_SPLIT(dev)) {
3299                 temp = I915_READ(PCH_DREF_CONTROL);
3300                 /* Always enable nonspread source */
3301                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3302                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3303                 I915_WRITE(PCH_DREF_CONTROL, temp);
3304                 POSTING_READ(PCH_DREF_CONTROL);
3305
3306                 temp &= ~DREF_SSC_SOURCE_MASK;
3307                 temp |= DREF_SSC_SOURCE_ENABLE;
3308                 I915_WRITE(PCH_DREF_CONTROL, temp);
3309                 POSTING_READ(PCH_DREF_CONTROL);
3310
3311                 udelay(200);
3312
3313                 if (is_edp) {
3314                         if (dev_priv->lvds_use_ssc) {
3315                                 temp |= DREF_SSC1_ENABLE;
3316                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3317                                 POSTING_READ(PCH_DREF_CONTROL);
3318
3319                                 udelay(200);
3320
3321                                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3322                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3323                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3324                                 POSTING_READ(PCH_DREF_CONTROL);
3325                         } else {
3326                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3327                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3328                                 POSTING_READ(PCH_DREF_CONTROL);
3329                         }
3330                 }
3331         }
3332
3333         if (IS_PINEVIEW(dev)) {
3334                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3335                 if (has_reduced_clock)
3336                         fp2 = (1 << reduced_clock.n) << 16 |
3337                                 reduced_clock.m1 << 8 | reduced_clock.m2;
3338         } else {
3339                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3340                 if (has_reduced_clock)
3341                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3342                                 reduced_clock.m2;
3343         }
3344
3345         if (!HAS_PCH_SPLIT(dev))
3346                 dpll = DPLL_VGA_MODE_DIS;
3347
3348         if (IS_I9XX(dev)) {
3349                 if (is_lvds)
3350                         dpll |= DPLLB_MODE_LVDS;
3351                 else
3352                         dpll |= DPLLB_MODE_DAC_SERIAL;
3353                 if (is_sdvo) {
3354                         dpll |= DPLL_DVO_HIGH_SPEED;
3355                         sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3356                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3357                                 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3358                         else if (HAS_PCH_SPLIT(dev))
3359                                 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3360                 }
3361                 if (is_dp)
3362                         dpll |= DPLL_DVO_HIGH_SPEED;
3363
3364                 /* compute bitmask from p1 value */
3365                 if (IS_PINEVIEW(dev))
3366                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3367                 else {
3368                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3369                         /* also FPA1 */
3370                         if (HAS_PCH_SPLIT(dev))
3371                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3372                         if (IS_G4X(dev) && has_reduced_clock)
3373                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3374                 }
3375                 switch (clock.p2) {
3376                 case 5:
3377                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3378                         break;
3379                 case 7:
3380                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3381                         break;
3382                 case 10:
3383                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3384                         break;
3385                 case 14:
3386                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3387                         break;
3388                 }
3389                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
3390                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3391         } else {
3392                 if (is_lvds) {
3393                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3394                 } else {
3395                         if (clock.p1 == 2)
3396                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
3397                         else
3398                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3399                         if (clock.p2 == 4)
3400                                 dpll |= PLL_P2_DIVIDE_BY_4;
3401                 }
3402         }
3403
3404         if (is_sdvo && is_tv)
3405                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3406         else if (is_tv)
3407                 /* XXX: just matching BIOS for now */
3408                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3409                 dpll |= 3;
3410         else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3411                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3412         else
3413                 dpll |= PLL_REF_INPUT_DREFCLK;
3414
3415         /* setup pipeconf */
3416         pipeconf = I915_READ(pipeconf_reg);
3417
3418         /* Set up the display plane register */
3419         dspcntr = DISPPLANE_GAMMA_ENABLE;
3420
3421         /* Ironlake's plane is forced to pipe, bit 24 is to
3422            enable color space conversion */
3423         if (!HAS_PCH_SPLIT(dev)) {
3424                 if (pipe == 0)
3425                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3426                 else
3427                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3428         }
3429
3430         if (pipe == 0 && !IS_I965G(dev)) {
3431                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3432                  * core speed.
3433                  *
3434                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3435                  * pipe == 0 check?
3436                  */
3437                 if (mode->clock >
3438                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3439                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
3440                 else
3441                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3442         }
3443
3444         dspcntr |= DISPLAY_PLANE_ENABLE;
3445         pipeconf |= PIPEACONF_ENABLE;
3446         dpll |= DPLL_VCO_ENABLE;
3447
3448
3449         /* Disable the panel fitter if it was on our pipe */
3450         if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
3451                 I915_WRITE(PFIT_CONTROL, 0);
3452
3453         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3454         drm_mode_debug_printmodeline(mode);
3455
3456         /* assign to Ironlake registers */
3457         if (HAS_PCH_SPLIT(dev)) {
3458                 fp_reg = pch_fp_reg;
3459                 dpll_reg = pch_dpll_reg;
3460         }
3461
3462         if (is_edp) {
3463                 ironlake_disable_pll_edp(crtc);
3464         } else if ((dpll & DPLL_VCO_ENABLE)) {
3465                 I915_WRITE(fp_reg, fp);
3466                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3467                 I915_READ(dpll_reg);
3468                 udelay(150);
3469         }
3470
3471         /* enable transcoder DPLL */
3472         if (HAS_PCH_CPT(dev)) {
3473                 temp = I915_READ(PCH_DPLL_SEL);
3474                 if (trans_dpll_sel == 0)
3475                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3476                 else
3477                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3478                 I915_WRITE(PCH_DPLL_SEL, temp);
3479                 I915_READ(PCH_DPLL_SEL);
3480                 udelay(150);
3481         }
3482
3483         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3484          * This is an exception to the general rule that mode_set doesn't turn
3485          * things on.
3486          */
3487         if (is_lvds) {
3488                 u32 lvds;
3489
3490                 if (HAS_PCH_SPLIT(dev))
3491                         lvds_reg = PCH_LVDS;
3492
3493                 lvds = I915_READ(lvds_reg);
3494                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3495                 if (pipe == 1)
3496                         lvds |= LVDS_PIPEB_SELECT;
3497                 else
3498                         lvds &= ~LVDS_PIPEB_SELECT;
3499                 /* set the corresponsding LVDS_BORDER bit */
3500                 lvds |= dev_priv->lvds_border_bits;
3501                 /* Set the B0-B3 data pairs corresponding to whether we're going to
3502                  * set the DPLLs for dual-channel mode or not.
3503                  */
3504                 if (clock.p2 == 7)
3505                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3506                 else
3507                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3508
3509                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3510                  * appropriately here, but we need to look more thoroughly into how
3511                  * panels behave in the two modes.
3512                  */
3513                 /* set the dithering flag */
3514                 if (IS_I965G(dev)) {
3515                         if (dev_priv->lvds_dither) {
3516                                 if (HAS_PCH_SPLIT(dev))
3517                                         pipeconf |= PIPE_ENABLE_DITHER;
3518                                 else
3519                                         lvds |= LVDS_ENABLE_DITHER;
3520                         } else {
3521                                 if (HAS_PCH_SPLIT(dev))
3522                                         pipeconf &= ~PIPE_ENABLE_DITHER;
3523                                 else
3524                                         lvds &= ~LVDS_ENABLE_DITHER;
3525                         }
3526                 }
3527                 I915_WRITE(lvds_reg, lvds);
3528                 I915_READ(lvds_reg);
3529         }
3530         if (is_dp)
3531                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3532         else if (HAS_PCH_SPLIT(dev)) {
3533                 /* For non-DP output, clear any trans DP clock recovery setting.*/
3534                 if (pipe == 0) {
3535                         I915_WRITE(TRANSA_DATA_M1, 0);
3536                         I915_WRITE(TRANSA_DATA_N1, 0);
3537                         I915_WRITE(TRANSA_DP_LINK_M1, 0);
3538                         I915_WRITE(TRANSA_DP_LINK_N1, 0);
3539                 } else {
3540                         I915_WRITE(TRANSB_DATA_M1, 0);
3541                         I915_WRITE(TRANSB_DATA_N1, 0);
3542                         I915_WRITE(TRANSB_DP_LINK_M1, 0);
3543                         I915_WRITE(TRANSB_DP_LINK_N1, 0);
3544                 }
3545         }
3546
3547         if (!is_edp) {
3548                 I915_WRITE(fp_reg, fp);
3549                 I915_WRITE(dpll_reg, dpll);
3550                 I915_READ(dpll_reg);
3551                 /* Wait for the clocks to stabilize. */
3552                 udelay(150);
3553
3554                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
3555                         if (is_sdvo) {
3556                                 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3557                                 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
3558                                         ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
3559                         } else
3560                                 I915_WRITE(dpll_md_reg, 0);
3561                 } else {
3562                         /* write it again -- the BIOS does, after all */
3563                         I915_WRITE(dpll_reg, dpll);
3564                 }
3565                 I915_READ(dpll_reg);
3566                 /* Wait for the clocks to stabilize. */
3567                 udelay(150);
3568         }
3569
3570         if (is_lvds && has_reduced_clock && i915_powersave) {
3571                 I915_WRITE(fp_reg + 4, fp2);
3572                 intel_crtc->lowfreq_avail = true;
3573                 if (HAS_PIPE_CXSR(dev)) {
3574                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3575                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3576                 }
3577         } else {
3578                 I915_WRITE(fp_reg + 4, fp);
3579                 intel_crtc->lowfreq_avail = false;
3580                 if (HAS_PIPE_CXSR(dev)) {
3581                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3582                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3583                 }
3584         }
3585
3586         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
3587                    ((adjusted_mode->crtc_htotal - 1) << 16));
3588         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
3589                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
3590         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
3591                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
3592         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
3593                    ((adjusted_mode->crtc_vtotal - 1) << 16));
3594         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
3595                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
3596         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
3597                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
3598         /* pipesrc and dspsize control the size that is scaled from, which should
3599          * always be the user's requested size.
3600          */
3601         if (!HAS_PCH_SPLIT(dev)) {
3602                 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
3603                                 (mode->hdisplay - 1));
3604                 I915_WRITE(dsppos_reg, 0);
3605         }
3606         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3607
3608         if (HAS_PCH_SPLIT(dev)) {
3609                 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
3610                 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
3611                 I915_WRITE(link_m1_reg, m_n.link_m);
3612                 I915_WRITE(link_n1_reg, m_n.link_n);
3613
3614                 if (is_edp) {
3615                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
3616                 } else {
3617                         /* enable FDI RX PLL too */
3618                         temp = I915_READ(fdi_rx_reg);
3619                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
3620                         I915_READ(fdi_rx_reg);
3621                         udelay(200);
3622
3623                         /* enable FDI TX PLL too */
3624                         temp = I915_READ(fdi_tx_reg);
3625                         I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
3626                         I915_READ(fdi_tx_reg);
3627
3628                         /* enable FDI RX PCDCLK */
3629                         temp = I915_READ(fdi_rx_reg);
3630                         I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
3631                         I915_READ(fdi_rx_reg);
3632                         udelay(200);
3633                 }
3634         }
3635
3636         I915_WRITE(pipeconf_reg, pipeconf);
3637         I915_READ(pipeconf_reg);
3638
3639         intel_wait_for_vblank(dev);
3640
3641         if (IS_IRONLAKE(dev)) {
3642                 /* enable address swizzle for tiling buffer */
3643                 temp = I915_READ(DISP_ARB_CTL);
3644                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
3645         }
3646
3647         I915_WRITE(dspcntr_reg, dspcntr);
3648
3649         /* Flush the plane changes */
3650         ret = intel_pipe_set_base(crtc, x, y, old_fb);
3651
3652         if ((IS_I965G(dev) || plane == 0))
3653                 intel_update_fbc(crtc, &crtc->mode);
3654
3655         intel_update_watermarks(dev);
3656
3657         drm_vblank_post_modeset(dev, pipe);
3658
3659         return ret;
3660 }
3661
3662 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3663 void intel_crtc_load_lut(struct drm_crtc *crtc)
3664 {
3665         struct drm_device *dev = crtc->dev;
3666         struct drm_i915_private *dev_priv = dev->dev_private;
3667         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3668         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
3669         int i;
3670
3671         /* The clocks have to be on to load the palette. */
3672         if (!crtc->enabled)
3673                 return;
3674
3675         /* use legacy palette for Ironlake */
3676         if (HAS_PCH_SPLIT(dev))
3677                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
3678                                                    LGC_PALETTE_B;
3679
3680         for (i = 0; i < 256; i++) {
3681                 I915_WRITE(palreg + 4 * i,
3682                            (intel_crtc->lut_r[i] << 16) |
3683                            (intel_crtc->lut_g[i] << 8) |
3684                            intel_crtc->lut_b[i]);
3685         }
3686 }
3687
3688 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3689                                  struct drm_file *file_priv,
3690                                  uint32_t handle,
3691                                  uint32_t width, uint32_t height)
3692 {
3693         struct drm_device *dev = crtc->dev;
3694         struct drm_i915_private *dev_priv = dev->dev_private;
3695         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3696         struct drm_gem_object *bo;
3697         struct drm_i915_gem_object *obj_priv;
3698         int pipe = intel_crtc->pipe;
3699         uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
3700         uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
3701         uint32_t temp = I915_READ(control);
3702         size_t addr;
3703         int ret;
3704
3705         DRM_DEBUG_KMS("\n");
3706
3707         /* if we want to turn off the cursor ignore width and height */
3708         if (!handle) {
3709                 DRM_DEBUG_KMS("cursor off\n");
3710                 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3711                         temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
3712                         temp |= CURSOR_MODE_DISABLE;
3713                 } else {
3714                         temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
3715                 }
3716                 addr = 0;
3717                 bo = NULL;
3718                 mutex_lock(&dev->struct_mutex);
3719                 goto finish;
3720         }
3721
3722         /* Currently we only support 64x64 cursors */
3723         if (width != 64 || height != 64) {
3724                 DRM_ERROR("we currently only support 64x64 cursors\n");
3725                 return -EINVAL;
3726         }
3727
3728         bo = drm_gem_object_lookup(dev, file_priv, handle);
3729         if (!bo)
3730                 return -ENOENT;
3731
3732         obj_priv = to_intel_bo(bo);
3733
3734         if (bo->size < width * height * 4) {
3735                 DRM_ERROR("buffer is to small\n");
3736                 ret = -ENOMEM;
3737                 goto fail;
3738         }
3739
3740         /* we only need to pin inside GTT if cursor is non-phy */
3741         mutex_lock(&dev->struct_mutex);
3742         if (!dev_priv->info->cursor_needs_physical) {
3743                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
3744                 if (ret) {
3745                         DRM_ERROR("failed to pin cursor bo\n");
3746                         goto fail_locked;
3747                 }
3748                 addr = obj_priv->gtt_offset;
3749         } else {
3750                 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
3751                 if (ret) {
3752                         DRM_ERROR("failed to attach phys object\n");
3753                         goto fail_locked;
3754                 }
3755                 addr = obj_priv->phys_obj->handle->busaddr;
3756         }
3757
3758         if (!IS_I9XX(dev))
3759                 I915_WRITE(CURSIZE, (height << 12) | width);
3760
3761         /* Hooray for CUR*CNTR differences */
3762         if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3763                 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
3764                 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
3765                 temp |= (pipe << 28); /* Connect to correct pipe */
3766         } else {
3767                 temp &= ~(CURSOR_FORMAT_MASK);
3768                 temp |= CURSOR_ENABLE;
3769                 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
3770         }
3771
3772  finish:
3773         I915_WRITE(control, temp);
3774         I915_WRITE(base, addr);
3775
3776         if (intel_crtc->cursor_bo) {
3777                 if (dev_priv->info->cursor_needs_physical) {
3778                         if (intel_crtc->cursor_bo != bo)
3779                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
3780                 } else
3781                         i915_gem_object_unpin(intel_crtc->cursor_bo);
3782                 drm_gem_object_unreference(intel_crtc->cursor_bo);
3783         }
3784
3785         mutex_unlock(&dev->struct_mutex);
3786
3787         intel_crtc->cursor_addr = addr;
3788         intel_crtc->cursor_bo = bo;
3789
3790         return 0;
3791 fail_locked:
3792         mutex_unlock(&dev->struct_mutex);
3793 fail:
3794         drm_gem_object_unreference_unlocked(bo);
3795         return ret;
3796 }
3797
3798 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
3799 {
3800         struct drm_device *dev = crtc->dev;
3801         struct drm_i915_private *dev_priv = dev->dev_private;
3802         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3803         struct intel_framebuffer *intel_fb;
3804         int pipe = intel_crtc->pipe;
3805         uint32_t temp = 0;
3806         uint32_t adder;
3807
3808         if (crtc->fb) {
3809                 intel_fb = to_intel_framebuffer(crtc->fb);
3810                 intel_mark_busy(dev, intel_fb->obj);
3811         }
3812
3813         if (x < 0) {
3814                 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
3815                 x = -x;
3816         }
3817         if (y < 0) {
3818                 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
3819                 y = -y;
3820         }
3821
3822         temp |= x << CURSOR_X_SHIFT;
3823         temp |= y << CURSOR_Y_SHIFT;
3824
3825         adder = intel_crtc->cursor_addr;
3826         I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
3827         I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
3828
3829         return 0;
3830 }
3831
3832 /** Sets the color ramps on behalf of RandR */
3833 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
3834                                  u16 blue, int regno)
3835 {
3836         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3837
3838         intel_crtc->lut_r[regno] = red >> 8;
3839         intel_crtc->lut_g[regno] = green >> 8;
3840         intel_crtc->lut_b[regno] = blue >> 8;
3841 }
3842
3843 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
3844                              u16 *blue, int regno)
3845 {
3846         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3847
3848         *red = intel_crtc->lut_r[regno] << 8;
3849         *green = intel_crtc->lut_g[regno] << 8;
3850         *blue = intel_crtc->lut_b[regno] << 8;
3851 }
3852
3853 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
3854                                  u16 *blue, uint32_t size)
3855 {
3856         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3857         int i;
3858
3859         if (size != 256)
3860                 return;
3861
3862         for (i = 0; i < 256; i++) {
3863                 intel_crtc->lut_r[i] = red[i] >> 8;
3864                 intel_crtc->lut_g[i] = green[i] >> 8;
3865                 intel_crtc->lut_b[i] = blue[i] >> 8;
3866         }
3867
3868         intel_crtc_load_lut(crtc);
3869 }
3870
3871 /**
3872  * Get a pipe with a simple mode set on it for doing load-based monitor
3873  * detection.
3874  *
3875  * It will be up to the load-detect code to adjust the pipe as appropriate for
3876  * its requirements.  The pipe will be connected to no other encoders.
3877  *
3878  * Currently this code will only succeed if there is a pipe with no encoders
3879  * configured for it.  In the future, it could choose to temporarily disable
3880  * some outputs to free up a pipe for its use.
3881  *
3882  * \return crtc, or NULL if no pipes are available.
3883  */
3884
3885 /* VESA 640x480x72Hz mode to set on the pipe */
3886 static struct drm_display_mode load_detect_mode = {
3887         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
3888                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
3889 };
3890
3891 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
3892                                             struct drm_connector *connector,
3893                                             struct drm_display_mode *mode,
3894                                             int *dpms_mode)
3895 {
3896         struct intel_crtc *intel_crtc;
3897         struct drm_crtc *possible_crtc;
3898         struct drm_crtc *supported_crtc =NULL;
3899         struct drm_encoder *encoder = &intel_encoder->enc;
3900         struct drm_crtc *crtc = NULL;
3901         struct drm_device *dev = encoder->dev;
3902         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3903         struct drm_crtc_helper_funcs *crtc_funcs;
3904         int i = -1;
3905
3906         /*
3907          * Algorithm gets a little messy:
3908          *   - if the connector already has an assigned crtc, use it (but make
3909          *     sure it's on first)
3910          *   - try to find the first unused crtc that can drive this connector,
3911          *     and use that if we find one
3912          *   - if there are no unused crtcs available, try to use the first
3913          *     one we found that supports the connector
3914          */
3915
3916         /* See if we already have a CRTC for this connector */
3917         if (encoder->crtc) {
3918                 crtc = encoder->crtc;
3919                 /* Make sure the crtc and connector are running */
3920                 intel_crtc = to_intel_crtc(crtc);
3921                 *dpms_mode = intel_crtc->dpms_mode;
3922                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3923                         crtc_funcs = crtc->helper_private;
3924                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3925                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3926                 }
3927                 return crtc;
3928         }
3929
3930         /* Find an unused one (if possible) */
3931         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
3932                 i++;
3933                 if (!(encoder->possible_crtcs & (1 << i)))
3934                         continue;
3935                 if (!possible_crtc->enabled) {
3936                         crtc = possible_crtc;
3937                         break;
3938                 }
3939                 if (!supported_crtc)
3940                         supported_crtc = possible_crtc;
3941         }
3942
3943         /*
3944          * If we didn't find an unused CRTC, don't use any.
3945          */
3946         if (!crtc) {
3947                 return NULL;
3948         }
3949
3950         encoder->crtc = crtc;
3951         connector->encoder = encoder;
3952         intel_encoder->load_detect_temp = true;
3953
3954         intel_crtc = to_intel_crtc(crtc);
3955         *dpms_mode = intel_crtc->dpms_mode;
3956
3957         if (!crtc->enabled) {
3958                 if (!mode)
3959                         mode = &load_detect_mode;
3960                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
3961         } else {
3962                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3963                         crtc_funcs = crtc->helper_private;
3964                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3965                 }
3966
3967                 /* Add this connector to the crtc */
3968                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
3969                 encoder_funcs->commit(encoder);
3970         }
3971         /* let the connector get through one full cycle before testing */
3972         intel_wait_for_vblank(dev);
3973
3974         return crtc;
3975 }
3976
3977 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
3978                                     struct drm_connector *connector, int dpms_mode)
3979 {
3980         struct drm_encoder *encoder = &intel_encoder->enc;
3981         struct drm_device *dev = encoder->dev;
3982         struct drm_crtc *crtc = encoder->crtc;
3983         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3984         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3985
3986         if (intel_encoder->load_detect_temp) {
3987                 encoder->crtc = NULL;
3988                 connector->encoder = NULL;
3989                 intel_encoder->load_detect_temp = false;
3990                 crtc->enabled = drm_helper_crtc_in_use(crtc);
3991                 drm_helper_disable_unused_functions(dev);
3992         }
3993
3994         /* Switch crtc and encoder back off if necessary */
3995         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
3996                 if (encoder->crtc == crtc)
3997                         encoder_funcs->dpms(encoder, dpms_mode);
3998                 crtc_funcs->dpms(crtc, dpms_mode);
3999         }
4000 }
4001
4002 /* Returns the clock of the currently programmed mode of the given pipe. */
4003 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4004 {
4005         struct drm_i915_private *dev_priv = dev->dev_private;
4006         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4007         int pipe = intel_crtc->pipe;
4008         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4009         u32 fp;
4010         intel_clock_t clock;
4011
4012         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4013                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4014         else
4015                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4016
4017         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4018         if (IS_PINEVIEW(dev)) {
4019                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4020                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4021         } else {
4022                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4023                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4024         }
4025
4026         if (IS_I9XX(dev)) {
4027                 if (IS_PINEVIEW(dev))
4028                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4029                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4030                 else
4031                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4032                                DPLL_FPA01_P1_POST_DIV_SHIFT);
4033
4034                 switch (dpll & DPLL_MODE_MASK) {
4035                 case DPLLB_MODE_DAC_SERIAL:
4036                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4037                                 5 : 10;
4038                         break;
4039                 case DPLLB_MODE_LVDS:
4040                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4041                                 7 : 14;
4042                         break;
4043                 default:
4044                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4045                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
4046                         return 0;
4047                 }
4048
4049                 /* XXX: Handle the 100Mhz refclk */
4050                 intel_clock(dev, 96000, &clock);
4051         } else {
4052                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4053
4054                 if (is_lvds) {
4055                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4056                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
4057                         clock.p2 = 14;
4058
4059                         if ((dpll & PLL_REF_INPUT_MASK) ==
4060                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4061                                 /* XXX: might not be 66MHz */
4062                                 intel_clock(dev, 66000, &clock);
4063                         } else
4064                                 intel_clock(dev, 48000, &clock);
4065                 } else {
4066                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
4067                                 clock.p1 = 2;
4068                         else {
4069                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4070                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4071                         }
4072                         if (dpll & PLL_P2_DIVIDE_BY_4)
4073                                 clock.p2 = 4;
4074                         else
4075                                 clock.p2 = 2;
4076
4077                         intel_clock(dev, 48000, &clock);
4078                 }
4079         }
4080
4081         /* XXX: It would be nice to validate the clocks, but we can't reuse
4082          * i830PllIsValid() because it relies on the xf86_config connector
4083          * configuration being accurate, which it isn't necessarily.
4084          */
4085
4086         return clock.dot;
4087 }
4088
4089 /** Returns the currently programmed mode of the given pipe. */
4090 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4091                                              struct drm_crtc *crtc)
4092 {
4093         struct drm_i915_private *dev_priv = dev->dev_private;
4094         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4095         int pipe = intel_crtc->pipe;
4096         struct drm_display_mode *mode;
4097         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4098         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4099         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4100         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4101
4102         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4103         if (!mode)
4104                 return NULL;
4105
4106         mode->clock = intel_crtc_clock_get(dev, crtc);
4107         mode->hdisplay = (htot & 0xffff) + 1;
4108         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4109         mode->hsync_start = (hsync & 0xffff) + 1;
4110         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4111         mode->vdisplay = (vtot & 0xffff) + 1;
4112         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4113         mode->vsync_start = (vsync & 0xffff) + 1;
4114         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4115
4116         drm_mode_set_name(mode);
4117         drm_mode_set_crtcinfo(mode, 0);
4118
4119         return mode;
4120 }
4121
4122 #define GPU_IDLE_TIMEOUT 500 /* ms */
4123
4124 /* When this timer fires, we've been idle for awhile */
4125 static void intel_gpu_idle_timer(unsigned long arg)
4126 {
4127         struct drm_device *dev = (struct drm_device *)arg;
4128         drm_i915_private_t *dev_priv = dev->dev_private;
4129
4130         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4131
4132         dev_priv->busy = false;
4133
4134         queue_work(dev_priv->wq, &dev_priv->idle_work);
4135 }
4136
4137 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4138
4139 static void intel_crtc_idle_timer(unsigned long arg)
4140 {
4141         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4142         struct drm_crtc *crtc = &intel_crtc->base;
4143         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4144
4145         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4146
4147         intel_crtc->busy = false;
4148
4149         queue_work(dev_priv->wq, &dev_priv->idle_work);
4150 }
4151
4152 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
4153 {
4154         struct drm_device *dev = crtc->dev;
4155         drm_i915_private_t *dev_priv = dev->dev_private;
4156         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4157         int pipe = intel_crtc->pipe;
4158         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4159         int dpll = I915_READ(dpll_reg);
4160
4161         if (HAS_PCH_SPLIT(dev))
4162                 return;
4163
4164         if (!dev_priv->lvds_downclock_avail)
4165                 return;
4166
4167         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4168                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4169
4170                 /* Unlock panel regs */
4171                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
4172
4173                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4174                 I915_WRITE(dpll_reg, dpll);
4175                 dpll = I915_READ(dpll_reg);
4176                 intel_wait_for_vblank(dev);
4177                 dpll = I915_READ(dpll_reg);
4178                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4179                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4180
4181                 /* ...and lock them again */
4182                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4183         }
4184
4185         /* Schedule downclock */
4186         if (schedule)
4187                 mod_timer(&intel_crtc->idle_timer, jiffies +
4188                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4189 }
4190
4191 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4192 {
4193         struct drm_device *dev = crtc->dev;
4194         drm_i915_private_t *dev_priv = dev->dev_private;
4195         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4196         int pipe = intel_crtc->pipe;
4197         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4198         int dpll = I915_READ(dpll_reg);
4199
4200         if (HAS_PCH_SPLIT(dev))
4201                 return;
4202
4203         if (!dev_priv->lvds_downclock_avail)
4204                 return;
4205
4206         /*
4207          * Since this is called by a timer, we should never get here in
4208          * the manual case.
4209          */
4210         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4211                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4212
4213                 /* Unlock panel regs */
4214                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
4215
4216                 dpll |= DISPLAY_RATE_SELECT_FPA1;
4217                 I915_WRITE(dpll_reg, dpll);
4218                 dpll = I915_READ(dpll_reg);
4219                 intel_wait_for_vblank(dev);
4220                 dpll = I915_READ(dpll_reg);
4221                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4222                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4223
4224                 /* ...and lock them again */
4225                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4226         }
4227
4228 }
4229
4230 /**
4231  * intel_idle_update - adjust clocks for idleness
4232  * @work: work struct
4233  *
4234  * Either the GPU or display (or both) went idle.  Check the busy status
4235  * here and adjust the CRTC and GPU clocks as necessary.
4236  */
4237 static void intel_idle_update(struct work_struct *work)
4238 {
4239         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4240                                                     idle_work);
4241         struct drm_device *dev = dev_priv->dev;
4242         struct drm_crtc *crtc;
4243         struct intel_crtc *intel_crtc;
4244
4245         if (!i915_powersave)
4246                 return;
4247
4248         mutex_lock(&dev->struct_mutex);
4249
4250         if (IS_I945G(dev) || IS_I945GM(dev)) {
4251                 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4252                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4253         }
4254
4255         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4256                 /* Skip inactive CRTCs */
4257                 if (!crtc->fb)
4258                         continue;
4259
4260                 intel_crtc = to_intel_crtc(crtc);
4261                 if (!intel_crtc->busy)
4262                         intel_decrease_pllclock(crtc);
4263         }
4264
4265         mutex_unlock(&dev->struct_mutex);
4266 }
4267
4268 /**
4269  * intel_mark_busy - mark the GPU and possibly the display busy
4270  * @dev: drm device
4271  * @obj: object we're operating on
4272  *
4273  * Callers can use this function to indicate that the GPU is busy processing
4274  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
4275  * buffer), we'll also mark the display as busy, so we know to increase its
4276  * clock frequency.
4277  */
4278 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4279 {
4280         drm_i915_private_t *dev_priv = dev->dev_private;
4281         struct drm_crtc *crtc = NULL;
4282         struct intel_framebuffer *intel_fb;
4283         struct intel_crtc *intel_crtc;
4284
4285         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4286                 return;
4287
4288         if (!dev_priv->busy) {
4289                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4290                         u32 fw_blc_self;
4291
4292                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4293                         fw_blc_self = I915_READ(FW_BLC_SELF);
4294                         fw_blc_self &= ~FW_BLC_SELF_EN;
4295                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4296                 }
4297                 dev_priv->busy = true;
4298         } else
4299                 mod_timer(&dev_priv->idle_timer, jiffies +
4300                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4301
4302         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4303                 if (!crtc->fb)
4304                         continue;
4305
4306                 intel_crtc = to_intel_crtc(crtc);
4307                 intel_fb = to_intel_framebuffer(crtc->fb);
4308                 if (intel_fb->obj == obj) {
4309                         if (!intel_crtc->busy) {
4310                                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4311                                         u32 fw_blc_self;
4312
4313                                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4314                                         fw_blc_self = I915_READ(FW_BLC_SELF);
4315                                         fw_blc_self &= ~FW_BLC_SELF_EN;
4316                                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4317                                 }
4318                                 /* Non-busy -> busy, upclock */
4319                                 intel_increase_pllclock(crtc, true);
4320                                 intel_crtc->busy = true;
4321                         } else {
4322                                 /* Busy -> busy, put off timer */
4323                                 mod_timer(&intel_crtc->idle_timer, jiffies +
4324                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4325                         }
4326                 }
4327         }
4328 }
4329
4330 static void intel_crtc_destroy(struct drm_crtc *crtc)
4331 {
4332         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4333
4334         drm_crtc_cleanup(crtc);
4335         kfree(intel_crtc);
4336 }
4337
4338 struct intel_unpin_work {
4339         struct work_struct work;
4340         struct drm_device *dev;
4341         struct drm_gem_object *old_fb_obj;
4342         struct drm_gem_object *pending_flip_obj;
4343         struct drm_pending_vblank_event *event;
4344         int pending;
4345 };
4346
4347 static void intel_unpin_work_fn(struct work_struct *__work)
4348 {
4349         struct intel_unpin_work *work =
4350                 container_of(__work, struct intel_unpin_work, work);
4351
4352         mutex_lock(&work->dev->struct_mutex);
4353         i915_gem_object_unpin(work->old_fb_obj);
4354         drm_gem_object_unreference(work->pending_flip_obj);
4355         drm_gem_object_unreference(work->old_fb_obj);
4356         mutex_unlock(&work->dev->struct_mutex);
4357         kfree(work);
4358 }
4359
4360 void intel_finish_page_flip(struct drm_device *dev, int pipe)
4361 {
4362         drm_i915_private_t *dev_priv = dev->dev_private;
4363         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4364         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4365         struct intel_unpin_work *work;
4366         struct drm_i915_gem_object *obj_priv;
4367         struct drm_pending_vblank_event *e;
4368         struct timeval now;
4369         unsigned long flags;
4370
4371         /* Ignore early vblank irqs */
4372         if (intel_crtc == NULL)
4373                 return;
4374
4375         spin_lock_irqsave(&dev->event_lock, flags);
4376         work = intel_crtc->unpin_work;
4377         if (work == NULL || !work->pending) {
4378                 if (work && !work->pending) {
4379                         obj_priv = to_intel_bo(work->pending_flip_obj);
4380                         DRM_DEBUG_DRIVER("flip finish: %p (%d) not pending?\n",
4381                                          obj_priv,
4382                                          atomic_read(&obj_priv->pending_flip));
4383                 }
4384                 spin_unlock_irqrestore(&dev->event_lock, flags);
4385                 return;
4386         }
4387
4388         intel_crtc->unpin_work = NULL;
4389         drm_vblank_put(dev, intel_crtc->pipe);
4390
4391         if (work->event) {
4392                 e = work->event;
4393                 do_gettimeofday(&now);
4394                 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4395                 e->event.tv_sec = now.tv_sec;
4396                 e->event.tv_usec = now.tv_usec;
4397                 list_add_tail(&e->base.link,
4398                               &e->base.file_priv->event_list);
4399                 wake_up_interruptible(&e->base.file_priv->event_wait);
4400         }
4401
4402         spin_unlock_irqrestore(&dev->event_lock, flags);
4403
4404         obj_priv = to_intel_bo(work->pending_flip_obj);
4405
4406         /* Initial scanout buffer will have a 0 pending flip count */
4407         if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4408             atomic_dec_and_test(&obj_priv->pending_flip))
4409                 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4410         schedule_work(&work->work);
4411 }
4412
4413 void intel_prepare_page_flip(struct drm_device *dev, int plane)
4414 {
4415         drm_i915_private_t *dev_priv = dev->dev_private;
4416         struct intel_crtc *intel_crtc =
4417                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
4418         unsigned long flags;
4419
4420         spin_lock_irqsave(&dev->event_lock, flags);
4421         if (intel_crtc->unpin_work) {
4422                 intel_crtc->unpin_work->pending = 1;
4423         } else {
4424                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
4425         }
4426         spin_unlock_irqrestore(&dev->event_lock, flags);
4427 }
4428
4429 static int intel_crtc_page_flip(struct drm_crtc *crtc,
4430                                 struct drm_framebuffer *fb,
4431                                 struct drm_pending_vblank_event *event)
4432 {
4433         struct drm_device *dev = crtc->dev;
4434         struct drm_i915_private *dev_priv = dev->dev_private;
4435         struct intel_framebuffer *intel_fb;
4436         struct drm_i915_gem_object *obj_priv;
4437         struct drm_gem_object *obj;
4438         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4439         struct intel_unpin_work *work;
4440         unsigned long flags;
4441         int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
4442         int ret, pipesrc;
4443         RING_LOCALS;
4444
4445         work = kzalloc(sizeof *work, GFP_KERNEL);
4446         if (work == NULL)
4447                 return -ENOMEM;
4448
4449         mutex_lock(&dev->struct_mutex);
4450
4451         work->event = event;
4452         work->dev = crtc->dev;
4453         intel_fb = to_intel_framebuffer(crtc->fb);
4454         work->old_fb_obj = intel_fb->obj;
4455         INIT_WORK(&work->work, intel_unpin_work_fn);
4456
4457         /* We borrow the event spin lock for protecting unpin_work */
4458         spin_lock_irqsave(&dev->event_lock, flags);
4459         if (intel_crtc->unpin_work) {
4460                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
4461                 spin_unlock_irqrestore(&dev->event_lock, flags);
4462                 kfree(work);
4463                 mutex_unlock(&dev->struct_mutex);
4464                 return -EBUSY;
4465         }
4466         intel_crtc->unpin_work = work;
4467         spin_unlock_irqrestore(&dev->event_lock, flags);
4468
4469         intel_fb = to_intel_framebuffer(fb);
4470         obj = intel_fb->obj;
4471
4472         ret = intel_pin_and_fence_fb_obj(dev, obj);
4473         if (ret != 0) {
4474                 DRM_DEBUG_DRIVER("flip queue: %p pin & fence failed\n",
4475                           to_intel_bo(obj));
4476                 kfree(work);
4477                 intel_crtc->unpin_work = NULL;
4478                 mutex_unlock(&dev->struct_mutex);
4479                 return ret;
4480         }
4481
4482         /* Reference the objects for the scheduled work. */
4483         drm_gem_object_reference(work->old_fb_obj);
4484         drm_gem_object_reference(obj);
4485
4486         crtc->fb = fb;
4487         i915_gem_object_flush_write_domain(obj);
4488         drm_vblank_get(dev, intel_crtc->pipe);
4489         obj_priv = to_intel_bo(obj);
4490         atomic_inc(&obj_priv->pending_flip);
4491         work->pending_flip_obj = obj;
4492
4493         BEGIN_LP_RING(4);
4494         OUT_RING(MI_DISPLAY_FLIP |
4495                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
4496         OUT_RING(fb->pitch);
4497         if (IS_I965G(dev)) {
4498                 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
4499                 pipesrc = I915_READ(pipesrc_reg);
4500                 OUT_RING(pipesrc & 0x0fff0fff);
4501         } else {
4502                 OUT_RING(obj_priv->gtt_offset);
4503                 OUT_RING(MI_NOOP);
4504         }
4505         ADVANCE_LP_RING();
4506
4507         mutex_unlock(&dev->struct_mutex);
4508
4509         return 0;
4510 }
4511
4512 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
4513         .dpms = intel_crtc_dpms,
4514         .mode_fixup = intel_crtc_mode_fixup,
4515         .mode_set = intel_crtc_mode_set,
4516         .mode_set_base = intel_pipe_set_base,
4517         .prepare = intel_crtc_prepare,
4518         .commit = intel_crtc_commit,
4519         .load_lut = intel_crtc_load_lut,
4520 };
4521
4522 static const struct drm_crtc_funcs intel_crtc_funcs = {
4523         .cursor_set = intel_crtc_cursor_set,
4524         .cursor_move = intel_crtc_cursor_move,
4525         .gamma_set = intel_crtc_gamma_set,
4526         .set_config = drm_crtc_helper_set_config,
4527         .destroy = intel_crtc_destroy,
4528         .page_flip = intel_crtc_page_flip,
4529 };
4530
4531
4532 static void intel_crtc_init(struct drm_device *dev, int pipe)
4533 {
4534         drm_i915_private_t *dev_priv = dev->dev_private;
4535         struct intel_crtc *intel_crtc;
4536         int i;
4537
4538         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
4539         if (intel_crtc == NULL)
4540                 return;
4541
4542         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
4543
4544         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
4545         intel_crtc->pipe = pipe;
4546         intel_crtc->plane = pipe;
4547         for (i = 0; i < 256; i++) {
4548                 intel_crtc->lut_r[i] = i;
4549                 intel_crtc->lut_g[i] = i;
4550                 intel_crtc->lut_b[i] = i;
4551         }
4552
4553         /* Swap pipes & planes for FBC on pre-965 */
4554         intel_crtc->pipe = pipe;
4555         intel_crtc->plane = pipe;
4556         if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
4557                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
4558                 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
4559         }
4560
4561         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
4562                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
4563         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
4564         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
4565
4566         intel_crtc->cursor_addr = 0;
4567         intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4568         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
4569
4570         intel_crtc->busy = false;
4571
4572         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
4573                     (unsigned long)intel_crtc);
4574 }
4575
4576 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
4577                                 struct drm_file *file_priv)
4578 {
4579         drm_i915_private_t *dev_priv = dev->dev_private;
4580         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
4581         struct drm_mode_object *drmmode_obj;
4582         struct intel_crtc *crtc;
4583
4584         if (!dev_priv) {
4585                 DRM_ERROR("called with no initialization\n");
4586                 return -EINVAL;
4587         }
4588
4589         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
4590                         DRM_MODE_OBJECT_CRTC);
4591
4592         if (!drmmode_obj) {
4593                 DRM_ERROR("no such CRTC id\n");
4594                 return -EINVAL;
4595         }
4596
4597         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
4598         pipe_from_crtc_id->pipe = crtc->pipe;
4599
4600         return 0;
4601 }
4602
4603 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
4604 {
4605         struct drm_crtc *crtc = NULL;
4606
4607         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4608                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4609                 if (intel_crtc->pipe == pipe)
4610                         break;
4611         }
4612         return crtc;
4613 }
4614
4615 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
4616 {
4617         int index_mask = 0;
4618         struct drm_encoder *encoder;
4619         int entry = 0;
4620
4621         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4622                 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
4623                 if (type_mask & intel_encoder->clone_mask)
4624                         index_mask |= (1 << entry);
4625                 entry++;
4626         }
4627         return index_mask;
4628 }
4629
4630
4631 static void intel_setup_outputs(struct drm_device *dev)
4632 {
4633         struct drm_i915_private *dev_priv = dev->dev_private;
4634         struct drm_encoder *encoder;
4635
4636         intel_crt_init(dev);
4637
4638         /* Set up integrated LVDS */
4639         if (IS_MOBILE(dev) && !IS_I830(dev))
4640                 intel_lvds_init(dev);
4641
4642         if (HAS_PCH_SPLIT(dev)) {
4643                 int found;
4644
4645                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
4646                         intel_dp_init(dev, DP_A);
4647
4648                 if (I915_READ(HDMIB) & PORT_DETECTED) {
4649                         /* check SDVOB */
4650                         /* found = intel_sdvo_init(dev, HDMIB); */
4651                         found = 0;
4652                         if (!found)
4653                                 intel_hdmi_init(dev, HDMIB);
4654                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
4655                                 intel_dp_init(dev, PCH_DP_B);
4656                 }
4657
4658                 if (I915_READ(HDMIC) & PORT_DETECTED)
4659                         intel_hdmi_init(dev, HDMIC);
4660
4661                 if (I915_READ(HDMID) & PORT_DETECTED)
4662                         intel_hdmi_init(dev, HDMID);
4663
4664                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
4665                         intel_dp_init(dev, PCH_DP_C);
4666
4667                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
4668                         intel_dp_init(dev, PCH_DP_D);
4669
4670         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
4671                 bool found = false;
4672
4673                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4674                         DRM_DEBUG_KMS("probing SDVOB\n");
4675                         found = intel_sdvo_init(dev, SDVOB);
4676                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
4677                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
4678                                 intel_hdmi_init(dev, SDVOB);
4679                         }
4680
4681                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
4682                                 DRM_DEBUG_KMS("probing DP_B\n");
4683                                 intel_dp_init(dev, DP_B);
4684                         }
4685                 }
4686
4687                 /* Before G4X SDVOC doesn't have its own detect register */
4688
4689                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4690                         DRM_DEBUG_KMS("probing SDVOC\n");
4691                         found = intel_sdvo_init(dev, SDVOC);
4692                 }
4693
4694                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
4695
4696                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
4697                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
4698                                 intel_hdmi_init(dev, SDVOC);
4699                         }
4700                         if (SUPPORTS_INTEGRATED_DP(dev)) {
4701                                 DRM_DEBUG_KMS("probing DP_C\n");
4702                                 intel_dp_init(dev, DP_C);
4703                         }
4704                 }
4705
4706                 if (SUPPORTS_INTEGRATED_DP(dev) &&
4707                     (I915_READ(DP_D) & DP_DETECTED)) {
4708                         DRM_DEBUG_KMS("probing DP_D\n");
4709                         intel_dp_init(dev, DP_D);
4710                 }
4711         } else if (IS_GEN2(dev))
4712                 intel_dvo_init(dev);
4713
4714         if (SUPPORTS_TV(dev))
4715                 intel_tv_init(dev);
4716
4717         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4718                 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
4719
4720                 encoder->possible_crtcs = intel_encoder->crtc_mask;
4721                 encoder->possible_clones = intel_encoder_clones(dev,
4722                                                 intel_encoder->clone_mask);
4723         }
4724 }
4725
4726 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
4727 {
4728         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4729         struct drm_device *dev = fb->dev;
4730
4731         if (fb->fbdev)
4732                 intelfb_remove(dev, fb);
4733
4734         drm_framebuffer_cleanup(fb);
4735         drm_gem_object_unreference_unlocked(intel_fb->obj);
4736
4737         kfree(intel_fb);
4738 }
4739
4740 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
4741                                                 struct drm_file *file_priv,
4742                                                 unsigned int *handle)
4743 {
4744         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4745         struct drm_gem_object *object = intel_fb->obj;
4746
4747         return drm_gem_handle_create(file_priv, object, handle);
4748 }
4749
4750 static const struct drm_framebuffer_funcs intel_fb_funcs = {
4751         .destroy = intel_user_framebuffer_destroy,
4752         .create_handle = intel_user_framebuffer_create_handle,
4753 };
4754
4755 int intel_framebuffer_create(struct drm_device *dev,
4756                              struct drm_mode_fb_cmd *mode_cmd,
4757                              struct drm_framebuffer **fb,
4758                              struct drm_gem_object *obj)
4759 {
4760         struct intel_framebuffer *intel_fb;
4761         int ret;
4762
4763         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
4764         if (!intel_fb)
4765                 return -ENOMEM;
4766
4767         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
4768         if (ret) {
4769                 DRM_ERROR("framebuffer init failed %d\n", ret);
4770                 return ret;
4771         }
4772
4773         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
4774
4775         intel_fb->obj = obj;
4776
4777         *fb = &intel_fb->base;
4778
4779         return 0;
4780 }
4781
4782
4783 static struct drm_framebuffer *
4784 intel_user_framebuffer_create(struct drm_device *dev,
4785                               struct drm_file *filp,
4786                               struct drm_mode_fb_cmd *mode_cmd)
4787 {
4788         struct drm_gem_object *obj;
4789         struct drm_framebuffer *fb;
4790         int ret;
4791
4792         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
4793         if (!obj)
4794                 return NULL;
4795
4796         ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
4797         if (ret) {
4798                 drm_gem_object_unreference_unlocked(obj);
4799                 return NULL;
4800         }
4801
4802         return fb;
4803 }
4804
4805 static const struct drm_mode_config_funcs intel_mode_funcs = {
4806         .fb_create = intel_user_framebuffer_create,
4807         .fb_changed = intelfb_probe,
4808 };
4809
4810 static struct drm_gem_object *
4811 intel_alloc_power_context(struct drm_device *dev)
4812 {
4813         struct drm_gem_object *pwrctx;
4814         int ret;
4815
4816         pwrctx = drm_gem_object_alloc(dev, 4096);
4817         if (!pwrctx) {
4818                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
4819                 return NULL;
4820         }
4821
4822         mutex_lock(&dev->struct_mutex);
4823         ret = i915_gem_object_pin(pwrctx, 4096);
4824         if (ret) {
4825                 DRM_ERROR("failed to pin power context: %d\n", ret);
4826                 goto err_unref;
4827         }
4828
4829         ret = i915_gem_object_set_to_gtt_domain(pwrctx, 1);
4830         if (ret) {
4831                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
4832                 goto err_unpin;
4833         }
4834         mutex_unlock(&dev->struct_mutex);
4835
4836         return pwrctx;
4837
4838 err_unpin:
4839         i915_gem_object_unpin(pwrctx);
4840 err_unref:
4841         drm_gem_object_unreference(pwrctx);
4842         mutex_unlock(&dev->struct_mutex);
4843         return NULL;
4844 }
4845
4846 void ironlake_enable_drps(struct drm_device *dev)
4847 {
4848         struct drm_i915_private *dev_priv = dev->dev_private;
4849         u32 rgvmodectl = I915_READ(MEMMODECTL), rgvswctl;
4850         u8 fmax, fmin, fstart, vstart;
4851         int i = 0;
4852
4853         /* 100ms RC evaluation intervals */
4854         I915_WRITE(RCUPEI, 100000);
4855         I915_WRITE(RCDNEI, 100000);
4856
4857         /* Set max/min thresholds to 90ms and 80ms respectively */
4858         I915_WRITE(RCBMAXAVG, 90000);
4859         I915_WRITE(RCBMINAVG, 80000);
4860
4861         I915_WRITE(MEMIHYST, 1);
4862
4863         /* Set up min, max, and cur for interrupt handling */
4864         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4865         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4866         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4867                 MEMMODE_FSTART_SHIFT;
4868         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
4869                 PXVFREQ_PX_SHIFT;
4870
4871         dev_priv->max_delay = fstart; /* can't go to fmax w/o IPS */
4872         dev_priv->min_delay = fmin;
4873         dev_priv->cur_delay = fstart;
4874
4875         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4876
4877         /*
4878          * Interrupts will be enabled in ironlake_irq_postinstall
4879          */
4880
4881         I915_WRITE(VIDSTART, vstart);
4882         POSTING_READ(VIDSTART);
4883
4884         rgvmodectl |= MEMMODE_SWMODE_EN;
4885         I915_WRITE(MEMMODECTL, rgvmodectl);
4886
4887         while (I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) {
4888                 if (i++ > 100) {
4889                         DRM_ERROR("stuck trying to change perf mode\n");
4890                         break;
4891                 }
4892                 msleep(1);
4893         }
4894         msleep(1);
4895
4896         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4897                 (fstart << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4898         I915_WRITE(MEMSWCTL, rgvswctl);
4899         POSTING_READ(MEMSWCTL);
4900
4901         rgvswctl |= MEMCTL_CMD_STS;
4902         I915_WRITE(MEMSWCTL, rgvswctl);
4903 }
4904
4905 void ironlake_disable_drps(struct drm_device *dev)
4906 {
4907         struct drm_i915_private *dev_priv = dev->dev_private;
4908         u32 rgvswctl;
4909         u8 fstart;
4910
4911         /* Ack interrupts, disable EFC interrupt */
4912         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4913         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4914         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4915         I915_WRITE(DEIIR, DE_PCU_EVENT);
4916         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4917
4918         /* Go back to the starting frequency */
4919         fstart = (I915_READ(MEMMODECTL) & MEMMODE_FSTART_MASK) >>
4920                 MEMMODE_FSTART_SHIFT;
4921         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4922                 (fstart << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4923         I915_WRITE(MEMSWCTL, rgvswctl);
4924         msleep(1);
4925         rgvswctl |= MEMCTL_CMD_STS;
4926         I915_WRITE(MEMSWCTL, rgvswctl);
4927         msleep(1);
4928
4929 }
4930
4931 void intel_init_clock_gating(struct drm_device *dev)
4932 {
4933         struct drm_i915_private *dev_priv = dev->dev_private;
4934
4935         /*
4936          * Disable clock gating reported to work incorrectly according to the
4937          * specs, but enable as much else as we can.
4938          */
4939         if (HAS_PCH_SPLIT(dev)) {
4940                 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
4941
4942                 if (IS_IRONLAKE(dev)) {
4943                         /* Required for FBC */
4944                         dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
4945                         /* Required for CxSR */
4946                         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
4947
4948                         I915_WRITE(PCH_3DCGDIS0,
4949                                    MARIUNIT_CLOCK_GATE_DISABLE |
4950                                    SVSMUNIT_CLOCK_GATE_DISABLE);
4951                 }
4952
4953                 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
4954                 return;
4955         } else if (IS_G4X(dev)) {
4956                 uint32_t dspclk_gate;
4957                 I915_WRITE(RENCLK_GATE_D1, 0);
4958                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4959                        GS_UNIT_CLOCK_GATE_DISABLE |
4960                        CL_UNIT_CLOCK_GATE_DISABLE);
4961                 I915_WRITE(RAMCLK_GATE_D, 0);
4962                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4963                         OVRUNIT_CLOCK_GATE_DISABLE |
4964                         OVCUNIT_CLOCK_GATE_DISABLE;
4965                 if (IS_GM45(dev))
4966                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4967                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4968         } else if (IS_I965GM(dev)) {
4969                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4970                 I915_WRITE(RENCLK_GATE_D2, 0);
4971                 I915_WRITE(DSPCLK_GATE_D, 0);
4972                 I915_WRITE(RAMCLK_GATE_D, 0);
4973                 I915_WRITE16(DEUC, 0);
4974         } else if (IS_I965G(dev)) {
4975                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4976                        I965_RCC_CLOCK_GATE_DISABLE |
4977                        I965_RCPB_CLOCK_GATE_DISABLE |
4978                        I965_ISC_CLOCK_GATE_DISABLE |
4979                        I965_FBC_CLOCK_GATE_DISABLE);
4980                 I915_WRITE(RENCLK_GATE_D2, 0);
4981         } else if (IS_I9XX(dev)) {
4982                 u32 dstate = I915_READ(D_STATE);
4983
4984                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4985                         DSTATE_DOT_CLOCK_GATING;
4986                 I915_WRITE(D_STATE, dstate);
4987         } else if (IS_I85X(dev) || IS_I865G(dev)) {
4988                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4989         } else if (IS_I830(dev)) {
4990                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4991         }
4992
4993         /*
4994          * GPU can automatically power down the render unit if given a page
4995          * to save state.
4996          */
4997         if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
4998                 struct drm_i915_gem_object *obj_priv = NULL;
4999
5000                 if (dev_priv->pwrctx) {
5001                         obj_priv = to_intel_bo(dev_priv->pwrctx);
5002                 } else {
5003                         struct drm_gem_object *pwrctx;
5004
5005                         pwrctx = intel_alloc_power_context(dev);
5006                         if (pwrctx) {
5007                                 dev_priv->pwrctx = pwrctx;
5008                                 obj_priv = to_intel_bo(pwrctx);
5009                         }
5010                 }
5011
5012                 if (obj_priv) {
5013                         I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5014                         I915_WRITE(MCHBAR_RENDER_STANDBY,
5015                                    I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5016                 }
5017         }
5018 }
5019
5020 /* Set up chip specific display functions */
5021 static void intel_init_display(struct drm_device *dev)
5022 {
5023         struct drm_i915_private *dev_priv = dev->dev_private;
5024
5025         /* We always want a DPMS function */
5026         if (HAS_PCH_SPLIT(dev))
5027                 dev_priv->display.dpms = ironlake_crtc_dpms;
5028         else
5029                 dev_priv->display.dpms = i9xx_crtc_dpms;
5030
5031         /* Only mobile has FBC, leave pointers NULL for other chips */
5032         if (IS_MOBILE(dev)) {
5033                 if (IS_GM45(dev)) {
5034                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5035                         dev_priv->display.enable_fbc = g4x_enable_fbc;
5036                         dev_priv->display.disable_fbc = g4x_disable_fbc;
5037                 } else if (IS_I965GM(dev)) {
5038                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5039                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
5040                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
5041                 }
5042                 /* 855GM needs testing */
5043         }
5044
5045         /* Returns the core display clock speed */
5046         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5047                 dev_priv->display.get_display_clock_speed =
5048                         i945_get_display_clock_speed;
5049         else if (IS_I915G(dev))
5050                 dev_priv->display.get_display_clock_speed =
5051                         i915_get_display_clock_speed;
5052         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5053                 dev_priv->display.get_display_clock_speed =
5054                         i9xx_misc_get_display_clock_speed;
5055         else if (IS_I915GM(dev))
5056                 dev_priv->display.get_display_clock_speed =
5057                         i915gm_get_display_clock_speed;
5058         else if (IS_I865G(dev))
5059                 dev_priv->display.get_display_clock_speed =
5060                         i865_get_display_clock_speed;
5061         else if (IS_I85X(dev))
5062                 dev_priv->display.get_display_clock_speed =
5063                         i855_get_display_clock_speed;
5064         else /* 852, 830 */
5065                 dev_priv->display.get_display_clock_speed =
5066                         i830_get_display_clock_speed;
5067
5068         /* For FIFO watermark updates */
5069         if (HAS_PCH_SPLIT(dev))
5070                 dev_priv->display.update_wm = NULL;
5071         else if (IS_G4X(dev))
5072                 dev_priv->display.update_wm = g4x_update_wm;
5073         else if (IS_I965G(dev))
5074                 dev_priv->display.update_wm = i965_update_wm;
5075         else if (IS_I9XX(dev) || IS_MOBILE(dev)) {
5076                 dev_priv->display.update_wm = i9xx_update_wm;
5077                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5078         } else {
5079                 if (IS_I85X(dev))
5080                         dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5081                 else if (IS_845G(dev))
5082                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
5083                 else
5084                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
5085                 dev_priv->display.update_wm = i830_update_wm;
5086         }
5087 }
5088
5089 void intel_modeset_init(struct drm_device *dev)
5090 {
5091         struct drm_i915_private *dev_priv = dev->dev_private;
5092         int num_pipe;
5093         int i;
5094
5095         drm_mode_config_init(dev);
5096
5097         dev->mode_config.min_width = 0;
5098         dev->mode_config.min_height = 0;
5099
5100         dev->mode_config.funcs = (void *)&intel_mode_funcs;
5101
5102         intel_init_display(dev);
5103
5104         if (IS_I965G(dev)) {
5105                 dev->mode_config.max_width = 8192;
5106                 dev->mode_config.max_height = 8192;
5107         } else if (IS_I9XX(dev)) {
5108                 dev->mode_config.max_width = 4096;
5109                 dev->mode_config.max_height = 4096;
5110         } else {
5111                 dev->mode_config.max_width = 2048;
5112                 dev->mode_config.max_height = 2048;
5113         }
5114
5115         /* set memory base */
5116         if (IS_I9XX(dev))
5117                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
5118         else
5119                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
5120
5121         if (IS_MOBILE(dev) || IS_I9XX(dev))
5122                 num_pipe = 2;
5123         else
5124                 num_pipe = 1;
5125         DRM_DEBUG_KMS("%d display pipe%s available.\n",
5126                   num_pipe, num_pipe > 1 ? "s" : "");
5127
5128         for (i = 0; i < num_pipe; i++) {
5129                 intel_crtc_init(dev, i);
5130         }
5131
5132         intel_setup_outputs(dev);
5133
5134         intel_init_clock_gating(dev);
5135
5136         if (IS_IRONLAKE_M(dev))
5137                 ironlake_enable_drps(dev);
5138
5139         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
5140         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
5141                     (unsigned long)dev);
5142
5143         intel_setup_overlay(dev);
5144
5145         if (IS_PINEVIEW(dev) && !intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5146                                                         dev_priv->fsb_freq,
5147                                                         dev_priv->mem_freq))
5148                 DRM_INFO("failed to find known CxSR latency "
5149                          "(found fsb freq %d, mem freq %d), disabling CxSR\n",
5150                          dev_priv->fsb_freq, dev_priv->mem_freq);
5151 }
5152
5153 void intel_modeset_cleanup(struct drm_device *dev)
5154 {
5155         struct drm_i915_private *dev_priv = dev->dev_private;
5156         struct drm_crtc *crtc;
5157         struct intel_crtc *intel_crtc;
5158
5159         mutex_lock(&dev->struct_mutex);
5160
5161         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5162                 /* Skip inactive CRTCs */
5163                 if (!crtc->fb)
5164                         continue;
5165
5166                 intel_crtc = to_intel_crtc(crtc);
5167                 intel_increase_pllclock(crtc, false);
5168                 del_timer_sync(&intel_crtc->idle_timer);
5169         }
5170
5171         del_timer_sync(&dev_priv->idle_timer);
5172
5173         if (dev_priv->display.disable_fbc)
5174                 dev_priv->display.disable_fbc(dev);
5175
5176         if (dev_priv->pwrctx) {
5177                 struct drm_i915_gem_object *obj_priv;
5178
5179                 obj_priv = to_intel_bo(dev_priv->pwrctx);
5180                 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
5181                 I915_READ(PWRCTXA);
5182                 i915_gem_object_unpin(dev_priv->pwrctx);
5183                 drm_gem_object_unreference(dev_priv->pwrctx);
5184         }
5185
5186         if (IS_IRONLAKE_M(dev))
5187                 ironlake_disable_drps(dev);
5188
5189         mutex_unlock(&dev->struct_mutex);
5190
5191         drm_mode_config_cleanup(dev);
5192 }
5193
5194
5195 /* current intel driver doesn't take advantage of encoders
5196    always give back the encoder for the connector
5197 */
5198 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
5199 {
5200         struct intel_encoder *intel_encoder = to_intel_encoder(connector);
5201
5202         return &intel_encoder->enc;
5203 }
5204
5205 /*
5206  * Return which encoder is currently attached for connector.
5207  */
5208 struct drm_encoder *intel_attached_encoder (struct drm_connector *connector)
5209 {
5210         struct drm_mode_object *obj;
5211         struct drm_encoder *encoder;
5212         int i;
5213
5214         for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
5215                 if (connector->encoder_ids[i] == 0)
5216                         break;
5217
5218                 obj = drm_mode_object_find(connector->dev,
5219                                            connector->encoder_ids[i],
5220                                            DRM_MODE_OBJECT_ENCODER);
5221                 if (!obj)
5222                         continue;
5223
5224                 encoder = obj_to_encoder(obj);
5225                 return encoder;
5226         }
5227         return NULL;
5228 }
5229
5230 /*
5231  * set vga decode state - true == enable VGA decode
5232  */
5233 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
5234 {
5235         struct drm_i915_private *dev_priv = dev->dev_private;
5236         u16 gmch_ctrl;
5237
5238         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
5239         if (state)
5240                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
5241         else
5242                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
5243         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
5244         return 0;
5245 }