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   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include "drmP.h"
  32 #include "intel_drv.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "intel_dp.h"
  36
  37 #include "drm_crtc_helper.h"
  38
  39 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  40
  41 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  42 static void intel_update_watermarks(struct drm_device *dev);
  43 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
  44
  45 typedef struct {
  46     /* given values */
  47     int n;
  48     int m1, m2;
  49     int p1, p2;
  50     /* derived values */
  51     int dot;
  52     int vco;
  53     int m;
  54     int p;
  55 } intel_clock_t;
  56
  57 typedef struct {
  58     int min, max;
  59 } intel_range_t;
  60
  61 typedef struct {
  62     int dot_limit;
  63     int p2_slow, p2_fast;
  64 } intel_p2_t;
  65
  66 #define INTEL_P2_NUM                  2
  67 typedef struct intel_limit intel_limit_t;
  68 struct intel_limit {
  69     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  70     intel_p2_t      p2;
  71     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  72                       int, int, intel_clock_t *);
  73     bool (* find_reduced_pll)(const intel_limit_t *, struct drm_crtc *,
  74                               int, int, intel_clock_t *);
  75 };
  76
  77 #define I8XX_DOT_MIN              25000
  78 #define I8XX_DOT_MAX             350000
  79 #define I8XX_VCO_MIN             930000
  80 #define I8XX_VCO_MAX            1400000
  81 #define I8XX_N_MIN                    3
  82 #define I8XX_N_MAX                   16
  83 #define I8XX_M_MIN                   96
  84 #define I8XX_M_MAX                  140
  85 #define I8XX_M1_MIN                  18
  86 #define I8XX_M1_MAX                  26
  87 #define I8XX_M2_MIN                   6
  88 #define I8XX_M2_MAX                  16
  89 #define I8XX_P_MIN                    4
  90 #define I8XX_P_MAX                  128
  91 #define I8XX_P1_MIN                   2
  92 #define I8XX_P1_MAX                  33
  93 #define I8XX_P1_LVDS_MIN              1
  94 #define I8XX_P1_LVDS_MAX              6
  95 #define I8XX_P2_SLOW                  4
  96 #define I8XX_P2_FAST                  2
  97 #define I8XX_P2_LVDS_SLOW             14
  98 #define I8XX_P2_LVDS_FAST             7
  99 #define I8XX_P2_SLOW_LIMIT       165000
 100
 101 #define I9XX_DOT_MIN              20000
 102 #define I9XX_DOT_MAX             400000
 103 #define I9XX_VCO_MIN            1400000
 104 #define I9XX_VCO_MAX            2800000
 105 #define IGD_VCO_MIN             1700000
 106 #define IGD_VCO_MAX             3500000
 107 #define I9XX_N_MIN                    1
 108 #define I9XX_N_MAX                    6
 109 /* IGD's Ncounter is a ring counter */
 110 #define IGD_N_MIN                     3
 111 #define IGD_N_MAX                     6
 112 #define I9XX_M_MIN                   70
 113 #define I9XX_M_MAX                  120
 114 #define IGD_M_MIN                     2
 115 #define IGD_M_MAX                   256
 116 #define I9XX_M1_MIN                  10
 117 #define I9XX_M1_MAX                  22
 118 #define I9XX_M2_MIN                   5
 119 #define I9XX_M2_MAX                   9
 120 /* IGD M1 is reserved, and must be 0 */
 121 #define IGD_M1_MIN                    0
 122 #define IGD_M1_MAX                    0
 123 #define IGD_M2_MIN                    0
 124 #define IGD_M2_MAX                    254
 125 #define I9XX_P_SDVO_DAC_MIN           5
 126 #define I9XX_P_SDVO_DAC_MAX          80
 127 #define I9XX_P_LVDS_MIN               7
 128 #define I9XX_P_LVDS_MAX              98
 129 #define IGD_P_LVDS_MIN                7
 130 #define IGD_P_LVDS_MAX               112
 131 #define I9XX_P1_MIN                   1
 132 #define I9XX_P1_MAX                   8
 133 #define I9XX_P2_SDVO_DAC_SLOW                10
 134 #define I9XX_P2_SDVO_DAC_FAST                 5
 135 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 136 #define I9XX_P2_LVDS_SLOW                    14
 137 #define I9XX_P2_LVDS_FAST                     7
 138 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 139
 140 /*The parameter is for SDVO on G4x platform*/
 141 #define G4X_DOT_SDVO_MIN           25000
 142 #define G4X_DOT_SDVO_MAX           270000
 143 #define G4X_VCO_MIN                1750000
 144 #define G4X_VCO_MAX                3500000
 145 #define G4X_N_SDVO_MIN             1
 146 #define G4X_N_SDVO_MAX             4
 147 #define G4X_M_SDVO_MIN             104
 148 #define G4X_M_SDVO_MAX             138
 149 #define G4X_M1_SDVO_MIN            17
 150 #define G4X_M1_SDVO_MAX            23
 151 #define G4X_M2_SDVO_MIN            5
 152 #define G4X_M2_SDVO_MAX            11
 153 #define G4X_P_SDVO_MIN             10
 154 #define G4X_P_SDVO_MAX             30
 155 #define G4X_P1_SDVO_MIN            1
 156 #define G4X_P1_SDVO_MAX            3
 157 #define G4X_P2_SDVO_SLOW           10
 158 #define G4X_P2_SDVO_FAST           10
 159 #define G4X_P2_SDVO_LIMIT          270000
 160
 161 /*The parameter is for HDMI_DAC on G4x platform*/
 162 #define G4X_DOT_HDMI_DAC_MIN           22000
 163 #define G4X_DOT_HDMI_DAC_MAX           400000
 164 #define G4X_N_HDMI_DAC_MIN             1
 165 #define G4X_N_HDMI_DAC_MAX             4
 166 #define G4X_M_HDMI_DAC_MIN             104
 167 #define G4X_M_HDMI_DAC_MAX             138
 168 #define G4X_M1_HDMI_DAC_MIN            16
 169 #define G4X_M1_HDMI_DAC_MAX            23
 170 #define G4X_M2_HDMI_DAC_MIN            5
 171 #define G4X_M2_HDMI_DAC_MAX            11
 172 #define G4X_P_HDMI_DAC_MIN             5
 173 #define G4X_P_HDMI_DAC_MAX             80
 174 #define G4X_P1_HDMI_DAC_MIN            1
 175 #define G4X_P1_HDMI_DAC_MAX            8
 176 #define G4X_P2_HDMI_DAC_SLOW           10
 177 #define G4X_P2_HDMI_DAC_FAST           5
 178 #define G4X_P2_HDMI_DAC_LIMIT          165000
 179
 180 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 181 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 182 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 183 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 184 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 185 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 186 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 187 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 188 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 189 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 190 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 191 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 192 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 193 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 194 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 195 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 196 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 198
 199 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 200 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 201 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 202 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 203 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 204 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 205 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 206 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 207 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 208 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 209 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 210 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 211 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 212 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 213 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 214 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 215 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 217
 218 /*The parameter is for DISPLAY PORT on G4x platform*/
 219 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 220 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 221 #define G4X_N_DISPLAY_PORT_MIN             1
 222 #define G4X_N_DISPLAY_PORT_MAX             2
 223 #define G4X_M_DISPLAY_PORT_MIN             97
 224 #define G4X_M_DISPLAY_PORT_MAX             108
 225 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 226 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 227 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 228 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 229 #define G4X_P_DISPLAY_PORT_MIN             10
 230 #define G4X_P_DISPLAY_PORT_MAX             20
 231 #define G4X_P1_DISPLAY_PORT_MIN            1
 232 #define G4X_P1_DISPLAY_PORT_MAX            2
 233 #define G4X_P2_DISPLAY_PORT_SLOW           10
 234 #define G4X_P2_DISPLAY_PORT_FAST           10
 235 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 236
 237 /* IGDNG */
 238 /* as we calculate clock using (register_value + 2) for
 239    N/M1/M2, so here the range value for them is (actual_value-2).
 240  */
 241 #define IGDNG_DOT_MIN         25000
 242 #define IGDNG_DOT_MAX         350000
 243 #define IGDNG_VCO_MIN         1760000
 244 #define IGDNG_VCO_MAX         3510000
 245 #define IGDNG_N_MIN           1
 246 #define IGDNG_N_MAX           5
 247 #define IGDNG_M_MIN           79
 248 #define IGDNG_M_MAX           118
 249 #define IGDNG_M1_MIN          12
 250 #define IGDNG_M1_MAX          23
 251 #define IGDNG_M2_MIN          5
 252 #define IGDNG_M2_MAX          9
 253 #define IGDNG_P_SDVO_DAC_MIN  5
 254 #define IGDNG_P_SDVO_DAC_MAX  80
 255 #define IGDNG_P_LVDS_MIN      28
 256 #define IGDNG_P_LVDS_MAX      112
 257 #define IGDNG_P1_MIN          1
 258 #define IGDNG_P1_MAX          8
 259 #define IGDNG_P2_SDVO_DAC_SLOW 10
 260 #define IGDNG_P2_SDVO_DAC_FAST 5
 261 #define IGDNG_P2_LVDS_SLOW    14 /* single channel */
 262 #define IGDNG_P2_LVDS_FAST    7  /* double channel */
 263 #define IGDNG_P2_DOT_LIMIT    225000 /* 225Mhz */
 264
 265 static bool
 266 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 267                     int target, int refclk, intel_clock_t *best_clock);
 268 static bool
 269 intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 270                             int target, int refclk, intel_clock_t *best_clock);
 271 static bool
 272 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 273                         int target, int refclk, intel_clock_t *best_clock);
 274 static bool
 275 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 276                         int target, int refclk, intel_clock_t *best_clock);
 277
 278 static bool
 279 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 280                       int target, int refclk, intel_clock_t *best_clock);
 281 static bool
 282 intel_find_pll_igdng_dp(const intel_limit_t *, struct drm_crtc *crtc,
 283                       int target, int refclk, intel_clock_t *best_clock);
 284
 285 static const intel_limit_t intel_limits_i8xx_dvo = {
 286         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 287         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 288         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 289         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 290         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 291         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 292         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 293         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 294         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 295                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 296         .find_pll = intel_find_best_PLL,
 297         .find_reduced_pll = intel_find_best_reduced_PLL,
 298 };
 299
 300 static const intel_limit_t intel_limits_i8xx_lvds = {
 301         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 302         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 303         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 304         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 305         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 306         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 307         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 308         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 309         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 310                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 311         .find_pll = intel_find_best_PLL,
 312         .find_reduced_pll = intel_find_best_reduced_PLL,
 313 };
 314
 315 static const intel_limit_t intel_limits_i9xx_sdvo = {
 316         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 317         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 318         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 319         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 320         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 321         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 322         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 323         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 324         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 325                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 326         .find_pll = intel_find_best_PLL,
 327         .find_reduced_pll = intel_find_best_reduced_PLL,
 328 };
 329
 330 static const intel_limit_t intel_limits_i9xx_lvds = {
 331         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 332         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 333         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 334         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 335         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 336         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 337         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 338         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 339         /* The single-channel range is 25-112Mhz, and dual-channel
 340          * is 80-224Mhz.  Prefer single channel as much as possible.
 341          */
 342         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 343                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 344         .find_pll = intel_find_best_PLL,
 345         .find_reduced_pll = intel_find_best_reduced_PLL,
 346 };
 347
 348     /* below parameter and function is for G4X Chipset Family*/
 349 static const intel_limit_t intel_limits_g4x_sdvo = {
 350         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 351         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 352         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 353         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 354         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 355         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 356         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 357         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 358         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 359                  .p2_slow = G4X_P2_SDVO_SLOW,
 360                  .p2_fast = G4X_P2_SDVO_FAST
 361         },
 362         .find_pll = intel_g4x_find_best_PLL,
 363         .find_reduced_pll = intel_g4x_find_best_PLL,
 364 };
 365
 366 static const intel_limit_t intel_limits_g4x_hdmi = {
 367         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 368         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 369         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 370         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 371         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 372         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 373         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 374         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 375         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 376                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 377                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 378         },
 379         .find_pll = intel_g4x_find_best_PLL,
 380         .find_reduced_pll = intel_g4x_find_best_PLL,
 381 };
 382
 383 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 384         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 385                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 386         .vco = { .min = G4X_VCO_MIN,
 387                  .max = G4X_VCO_MAX },
 388         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 389                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 390         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 391                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 392         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 393                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 394         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 395                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 396         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 397                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 398         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 399                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 400         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 401                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 402                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 403         },
 404         .find_pll = intel_g4x_find_best_PLL,
 405         .find_reduced_pll = intel_g4x_find_best_PLL,
 406 };
 407
 408 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 409         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 410                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 411         .vco = { .min = G4X_VCO_MIN,
 412                  .max = G4X_VCO_MAX },
 413         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 414                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 415         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 416                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 417         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 418                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 419         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 420                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 421         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 422                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 423         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 424                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 425         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 426                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 427                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 428         },
 429         .find_pll = intel_g4x_find_best_PLL,
 430         .find_reduced_pll = intel_g4x_find_best_PLL,
 431 };
 432
 433 static const intel_limit_t intel_limits_g4x_display_port = {
 434         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 435                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 436         .vco = { .min = G4X_VCO_MIN,
 437                  .max = G4X_VCO_MAX},
 438         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 439                  .max = G4X_N_DISPLAY_PORT_MAX },
 440         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 441                  .max = G4X_M_DISPLAY_PORT_MAX },
 442         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 443                  .max = G4X_M1_DISPLAY_PORT_MAX },
 444         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 445                  .max = G4X_M2_DISPLAY_PORT_MAX },
 446         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 447                  .max = G4X_P_DISPLAY_PORT_MAX },
 448         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 449                  .max = G4X_P1_DISPLAY_PORT_MAX},
 450         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 451                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 452                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 453         .find_pll = intel_find_pll_g4x_dp,
 454 };
 455
 456 static const intel_limit_t intel_limits_igd_sdvo = {
 457         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 458         .vco = { .min = IGD_VCO_MIN,            .max = IGD_VCO_MAX },
 459         .n   = { .min = IGD_N_MIN,              .max = IGD_N_MAX },
 460         .m   = { .min = IGD_M_MIN,              .max = IGD_M_MAX },
 461         .m1  = { .min = IGD_M1_MIN,             .max = IGD_M1_MAX },
 462         .m2  = { .min = IGD_M2_MIN,             .max = IGD_M2_MAX },
 463         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 464         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 465         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 466                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 467         .find_pll = intel_find_best_PLL,
 468         .find_reduced_pll = intel_find_best_reduced_PLL,
 469 };
 470
 471 static const intel_limit_t intel_limits_igd_lvds = {
 472         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 473         .vco = { .min = IGD_VCO_MIN,            .max = IGD_VCO_MAX },
 474         .n   = { .min = IGD_N_MIN,              .max = IGD_N_MAX },
 475         .m   = { .min = IGD_M_MIN,              .max = IGD_M_MAX },
 476         .m1  = { .min = IGD_M1_MIN,             .max = IGD_M1_MAX },
 477         .m2  = { .min = IGD_M2_MIN,             .max = IGD_M2_MAX },
 478         .p   = { .min = IGD_P_LVDS_MIN, .max = IGD_P_LVDS_MAX },
 479         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 480         /* IGD only supports single-channel mode. */
 481         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 482                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 483         .find_pll = intel_find_best_PLL,
 484         .find_reduced_pll = intel_find_best_reduced_PLL,
 485 };
 486
 487 static const intel_limit_t intel_limits_igdng_sdvo = {
 488         .dot = { .min = IGDNG_DOT_MIN,          .max = IGDNG_DOT_MAX },
 489         .vco = { .min = IGDNG_VCO_MIN,          .max = IGDNG_VCO_MAX },
 490         .n   = { .min = IGDNG_N_MIN,            .max = IGDNG_N_MAX },
 491         .m   = { .min = IGDNG_M_MIN,            .max = IGDNG_M_MAX },
 492         .m1  = { .min = IGDNG_M1_MIN,           .max = IGDNG_M1_MAX },
 493         .m2  = { .min = IGDNG_M2_MIN,           .max = IGDNG_M2_MAX },
 494         .p   = { .min = IGDNG_P_SDVO_DAC_MIN,   .max = IGDNG_P_SDVO_DAC_MAX },
 495         .p1  = { .min = IGDNG_P1_MIN,           .max = IGDNG_P1_MAX },
 496         .p2  = { .dot_limit = IGDNG_P2_DOT_LIMIT,
 497                  .p2_slow = IGDNG_P2_SDVO_DAC_SLOW,
 498                  .p2_fast = IGDNG_P2_SDVO_DAC_FAST },
 499         .find_pll = intel_igdng_find_best_PLL,
 500 };
 501
 502 static const intel_limit_t intel_limits_igdng_lvds = {
 503         .dot = { .min = IGDNG_DOT_MIN,          .max = IGDNG_DOT_MAX },
 504         .vco = { .min = IGDNG_VCO_MIN,          .max = IGDNG_VCO_MAX },
 505         .n   = { .min = IGDNG_N_MIN,            .max = IGDNG_N_MAX },
 506         .m   = { .min = IGDNG_M_MIN,            .max = IGDNG_M_MAX },
 507         .m1  = { .min = IGDNG_M1_MIN,           .max = IGDNG_M1_MAX },
 508         .m2  = { .min = IGDNG_M2_MIN,           .max = IGDNG_M2_MAX },
 509         .p   = { .min = IGDNG_P_LVDS_MIN,       .max = IGDNG_P_LVDS_MAX },
 510         .p1  = { .min = IGDNG_P1_MIN,           .max = IGDNG_P1_MAX },
 511         .p2  = { .dot_limit = IGDNG_P2_DOT_LIMIT,
 512                  .p2_slow = IGDNG_P2_LVDS_SLOW,
 513                  .p2_fast = IGDNG_P2_LVDS_FAST },
 514         .find_pll = intel_igdng_find_best_PLL,
 515 };
 516
 517 static const intel_limit_t *intel_igdng_limit(struct drm_crtc *crtc)
 518 {
 519         const intel_limit_t *limit;
 520         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 521                 limit = &intel_limits_igdng_lvds;
 522         else
 523                 limit = &intel_limits_igdng_sdvo;
 524
 525         return limit;
 526 }
 527
 528 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 529 {
 530         struct drm_device *dev = crtc->dev;
 531         struct drm_i915_private *dev_priv = dev->dev_private;
 532         const intel_limit_t *limit;
 533
 534         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 535                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 536                     LVDS_CLKB_POWER_UP)
 537                         /* LVDS with dual channel */
 538                         limit = &intel_limits_g4x_dual_channel_lvds;
 539                 else
 540                         /* LVDS with dual channel */
 541                         limit = &intel_limits_g4x_single_channel_lvds;
 542         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 543                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 544                 limit = &intel_limits_g4x_hdmi;
 545         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 546                 limit = &intel_limits_g4x_sdvo;
 547         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 548                 limit = &intel_limits_g4x_display_port;
 549         } else /* The option is for other outputs */
 550                 limit = &intel_limits_i9xx_sdvo;
 551
 552         return limit;
 553 }
 554
 555 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 556 {
 557         struct drm_device *dev = crtc->dev;
 558         const intel_limit_t *limit;
 559
 560         if (IS_IGDNG(dev))
 561                 limit = intel_igdng_limit(crtc);
 562         else if (IS_G4X(dev)) {
 563                 limit = intel_g4x_limit(crtc);
 564         } else if (IS_I9XX(dev) && !IS_IGD(dev)) {
 565                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 566                         limit = &intel_limits_i9xx_lvds;
 567                 else
 568                         limit = &intel_limits_i9xx_sdvo;
 569         } else if (IS_IGD(dev)) {
 570                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 571                         limit = &intel_limits_igd_lvds;
 572                 else
 573                         limit = &intel_limits_igd_sdvo;
 574         } else {
 575                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 576                         limit = &intel_limits_i8xx_lvds;
 577                 else
 578                         limit = &intel_limits_i8xx_dvo;
 579         }
 580         return limit;
 581 }
 582
 583 /* m1 is reserved as 0 in IGD, n is a ring counter */
 584 static void igd_clock(int refclk, intel_clock_t *clock)
 585 {
 586         clock->m = clock->m2 + 2;
 587         clock->p = clock->p1 * clock->p2;
 588         clock->vco = refclk * clock->m / clock->n;
 589         clock->dot = clock->vco / clock->p;
 590 }
 591
 592 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 593 {
 594         if (IS_IGD(dev)) {
 595                 igd_clock(refclk, clock);
 596                 return;
 597         }
 598         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 599         clock->p = clock->p1 * clock->p2;
 600         clock->vco = refclk * clock->m / (clock->n + 2);
 601         clock->dot = clock->vco / clock->p;
 602 }
 603
 604 /**
 605  * Returns whether any output on the specified pipe is of the specified type
 606  */
 607 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
 608 {
 609     struct drm_device *dev = crtc->dev;
 610     struct drm_mode_config *mode_config = &dev->mode_config;
 611     struct drm_connector *l_entry;
 612
 613     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 614             if (l_entry->encoder &&
 615                 l_entry->encoder->crtc == crtc) {
 616                     struct intel_output *intel_output = to_intel_output(l_entry);
 617                     if (intel_output->type == type)
 618                             return true;
 619             }
 620     }
 621     return false;
 622 }
 623
 624 struct drm_connector *
 625 intel_pipe_get_output (struct drm_crtc *crtc)
 626 {
 627     struct drm_device *dev = crtc->dev;
 628     struct drm_mode_config *mode_config = &dev->mode_config;
 629     struct drm_connector *l_entry, *ret = NULL;
 630
 631     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 632             if (l_entry->encoder &&
 633                 l_entry->encoder->crtc == crtc) {
 634                     ret = l_entry;
 635                     break;
 636             }
 637     }
 638     return ret;
 639 }
 640
 641 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 642 /**
 643  * Returns whether the given set of divisors are valid for a given refclk with
 644  * the given connectors.
 645  */
 646
 647 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 648 {
 649         const intel_limit_t *limit = intel_limit (crtc);
 650         struct drm_device *dev = crtc->dev;
 651
 652         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 653                 INTELPllInvalid ("p1 out of range\n");
 654         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 655                 INTELPllInvalid ("p out of range\n");
 656         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 657                 INTELPllInvalid ("m2 out of range\n");
 658         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 659                 INTELPllInvalid ("m1 out of range\n");
 660         if (clock->m1 <= clock->m2 && !IS_IGD(dev))
 661                 INTELPllInvalid ("m1 <= m2\n");
 662         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 663                 INTELPllInvalid ("m out of range\n");
 664         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 665                 INTELPllInvalid ("n out of range\n");
 666         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 667                 INTELPllInvalid ("vco out of range\n");
 668         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 669          * connector, etc., rather than just a single range.
 670          */
 671         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 672                 INTELPllInvalid ("dot out of range\n");
 673
 674         return true;
 675 }
 676
 677 static bool
 678 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 679                     int target, int refclk, intel_clock_t *best_clock)
 680
 681 {
 682         struct drm_device *dev = crtc->dev;
 683         struct drm_i915_private *dev_priv = dev->dev_private;
 684         intel_clock_t clock;
 685         int err = target;
 686
 687         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 688             (I915_READ(LVDS)) != 0) {
 689                 /*
 690                  * For LVDS, if the panel is on, just rely on its current
 691                  * settings for dual-channel.  We haven't figured out how to
 692                  * reliably set up different single/dual channel state, if we
 693                  * even can.
 694                  */
 695                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 696                     LVDS_CLKB_POWER_UP)
 697                         clock.p2 = limit->p2.p2_fast;
 698                 else
 699                         clock.p2 = limit->p2.p2_slow;
 700         } else {
 701                 if (target < limit->p2.dot_limit)
 702                         clock.p2 = limit->p2.p2_slow;
 703                 else
 704                         clock.p2 = limit->p2.p2_fast;
 705         }
 706
 707         memset (best_clock, 0, sizeof (*best_clock));
 708
 709         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 710              clock.m1++) {
 711                 for (clock.m2 = limit->m2.min;
 712                      clock.m2 <= limit->m2.max; clock.m2++) {
 713                         /* m1 is always 0 in IGD */
 714                         if (clock.m2 >= clock.m1 && !IS_IGD(dev))
 715                                 break;
 716                         for (clock.n = limit->n.min;
 717                              clock.n <= limit->n.max; clock.n++) {
 718                                 for (clock.p1 = limit->p1.min;
 719                                         clock.p1 <= limit->p1.max; clock.p1++) {
 720                                         int this_err;
 721
 722                                         intel_clock(dev, refclk, &clock);
 723
 724                                         if (!intel_PLL_is_valid(crtc, &clock))
 725                                                 continue;
 726
 727                                         this_err = abs(clock.dot - target);
 728                                         if (this_err < err) {
 729                                                 *best_clock = clock;
 730                                                 err = this_err;
 731                                         }
 732                                 }
 733                         }
 734                 }
 735         }
 736
 737         return (err != target);
 738 }
 739
 740
 741 static bool
 742 intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 743                             int target, int refclk, intel_clock_t *best_clock)
 744
 745 {
 746         struct drm_device *dev = crtc->dev;
 747         intel_clock_t clock;
 748         int err = target;
 749         bool found = false;
 750
 751         memcpy(&clock, best_clock, sizeof(intel_clock_t));
 752
 753         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 754                 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
 755                         /* m1 is always 0 in IGD */
 756                         if (clock.m2 >= clock.m1 && !IS_IGD(dev))
 757                                 break;
 758                         for (clock.n = limit->n.min; clock.n <= limit->n.max;
 759                              clock.n++) {
 760                                 int this_err;
 761
 762                                 intel_clock(dev, refclk, &clock);
 763
 764                                 if (!intel_PLL_is_valid(crtc, &clock))
 765                                         continue;
 766
 767                                 this_err = abs(clock.dot - target);
 768                                 if (this_err < err) {
 769                                         *best_clock = clock;
 770                                         err = this_err;
 771                                         found = true;
 772                                 }
 773                         }
 774                 }
 775         }
 776
 777         return found;
 778 }
 779
 780 static bool
 781 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 782                         int target, int refclk, intel_clock_t *best_clock)
 783 {
 784         struct drm_device *dev = crtc->dev;
 785         struct drm_i915_private *dev_priv = dev->dev_private;
 786         intel_clock_t clock;
 787         int max_n;
 788         bool found;
 789         /* approximately equals target * 0.00488 */
 790         int err_most = (target >> 8) + (target >> 10);
 791         found = false;
 792
 793         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 794                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 795                     LVDS_CLKB_POWER_UP)
 796                         clock.p2 = limit->p2.p2_fast;
 797                 else
 798                         clock.p2 = limit->p2.p2_slow;
 799         } else {
 800                 if (target < limit->p2.dot_limit)
 801                         clock.p2 = limit->p2.p2_slow;
 802                 else
 803                         clock.p2 = limit->p2.p2_fast;
 804         }
 805
 806         memset(best_clock, 0, sizeof(*best_clock));
 807         max_n = limit->n.max;
 808         /* based on hardware requriment prefer smaller n to precision */
 809         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 810                 /* based on hardware requirment prefere larger m1,m2 */
 811                 for (clock.m1 = limit->m1.max;
 812                      clock.m1 >= limit->m1.min; clock.m1--) {
 813                         for (clock.m2 = limit->m2.max;
 814                              clock.m2 >= limit->m2.min; clock.m2--) {
 815                                 for (clock.p1 = limit->p1.max;
 816                                      clock.p1 >= limit->p1.min; clock.p1--) {
 817                                         int this_err;
 818
 819                                         intel_clock(dev, refclk, &clock);
 820                                         if (!intel_PLL_is_valid(crtc, &clock))
 821                                                 continue;
 822                                         this_err = abs(clock.dot - target) ;
 823                                         if (this_err < err_most) {
 824                                                 *best_clock = clock;
 825                                                 err_most = this_err;
 826                                                 max_n = clock.n;
 827                                                 found = true;
 828                                         }
 829                                 }
 830                         }
 831                 }
 832         }
 833         return found;
 834 }
 835
 836 static bool
 837 intel_find_pll_igdng_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 838                       int target, int refclk, intel_clock_t *best_clock)
 839 {
 840         struct drm_device *dev = crtc->dev;
 841         intel_clock_t clock;
 842         if (target < 200000) {
 843                 clock.n = 1;
 844                 clock.p1 = 2;
 845                 clock.p2 = 10;
 846                 clock.m1 = 12;
 847                 clock.m2 = 9;
 848         } else {
 849                 clock.n = 2;
 850                 clock.p1 = 1;
 851                 clock.p2 = 10;
 852                 clock.m1 = 14;
 853                 clock.m2 = 8;
 854         }
 855         intel_clock(dev, refclk, &clock);
 856         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 857         return true;
 858 }
 859
 860 static bool
 861 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 862                         int target, int refclk, intel_clock_t *best_clock)
 863 {
 864         struct drm_device *dev = crtc->dev;
 865         struct drm_i915_private *dev_priv = dev->dev_private;
 866         intel_clock_t clock;
 867         int err_most = 47;
 868         int err_min = 10000;
 869
 870         /* eDP has only 2 clock choice, no n/m/p setting */
 871         if (HAS_eDP)
 872                 return true;
 873
 874         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
 875                 return intel_find_pll_igdng_dp(limit, crtc, target,
 876                                                refclk, best_clock);
 877
 878         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 879                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 880                     LVDS_CLKB_POWER_UP)
 881                         clock.p2 = limit->p2.p2_fast;
 882                 else
 883                         clock.p2 = limit->p2.p2_slow;
 884         } else {
 885                 if (target < limit->p2.dot_limit)
 886                         clock.p2 = limit->p2.p2_slow;
 887                 else
 888                         clock.p2 = limit->p2.p2_fast;
 889         }
 890
 891         memset(best_clock, 0, sizeof(*best_clock));
 892         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 893                 /* based on hardware requriment prefer smaller n to precision */
 894                 for (clock.n = limit->n.min; clock.n <= limit->n.max; clock.n++) {
 895                         /* based on hardware requirment prefere larger m1,m2 */
 896                         for (clock.m1 = limit->m1.max;
 897                              clock.m1 >= limit->m1.min; clock.m1--) {
 898                                 for (clock.m2 = limit->m2.max;
 899                                      clock.m2 >= limit->m2.min; clock.m2--) {
 900                                         int this_err;
 901
 902                                         intel_clock(dev, refclk, &clock);
 903                                         if (!intel_PLL_is_valid(crtc, &clock))
 904                                                 continue;
 905                                         this_err = abs((10000 - (target*10000/clock.dot)));
 906                                         if (this_err < err_most) {
 907                                                 *best_clock = clock;
 908                                                 /* found on first matching */
 909                                                 goto out;
 910                                         } else if (this_err < err_min) {
 911                                                 *best_clock = clock;
 912                                                 err_min = this_err;
 913                                         }
 914                                 }
 915                         }
 916                 }
 917         }
 918 out:
 919         return true;
 920 }
 921
 922 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 923 static bool
 924 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 925                       int target, int refclk, intel_clock_t *best_clock)
 926 {
 927     intel_clock_t clock;
 928     if (target < 200000) {
 929         clock.p1 = 2;
 930         clock.p2 = 10;
 931         clock.n = 2;
 932         clock.m1 = 23;
 933         clock.m2 = 8;
 934     } else {
 935         clock.p1 = 1;
 936         clock.p2 = 10;
 937         clock.n = 1;
 938         clock.m1 = 14;
 939         clock.m2 = 2;
 940     }
 941     clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 942     clock.p = (clock.p1 * clock.p2);
 943     clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 944     clock.vco = 0;
 945     memcpy(best_clock, &clock, sizeof(intel_clock_t));
 946     return true;
 947 }
 948
 949 void
 950 intel_wait_for_vblank(struct drm_device *dev)
 951 {
 952         /* Wait for 20ms, i.e. one cycle at 50hz. */
 953         msleep(20);
 954 }
 955
 956 /* Parameters have changed, update FBC info */
 957 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 958 {
 959         struct drm_device *dev = crtc->dev;
 960         struct drm_i915_private *dev_priv = dev->dev_private;
 961         struct drm_framebuffer *fb = crtc->fb;
 962         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 963         struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
 964         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 965         int plane, i;
 966         u32 fbc_ctl, fbc_ctl2;
 967
 968         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
 969
 970         if (fb->pitch < dev_priv->cfb_pitch)
 971                 dev_priv->cfb_pitch = fb->pitch;
 972
 973         /* FBC_CTL wants 64B units */
 974         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
 975         dev_priv->cfb_fence = obj_priv->fence_reg;
 976         dev_priv->cfb_plane = intel_crtc->plane;
 977         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
 978
 979         /* Clear old tags */
 980         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 981                 I915_WRITE(FBC_TAG + (i * 4), 0);
 982
 983         /* Set it up... */
 984         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
 985         if (obj_priv->tiling_mode != I915_TILING_NONE)
 986                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
 987         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 988         I915_WRITE(FBC_FENCE_OFF, crtc->y);
 989
 990         /* enable it... */
 991         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
 992         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 993         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
 994         if (obj_priv->tiling_mode != I915_TILING_NONE)
 995                 fbc_ctl |= dev_priv->cfb_fence;
 996         I915_WRITE(FBC_CONTROL, fbc_ctl);
 997
 998         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
 999                   dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1000 }
1001
1002 void i8xx_disable_fbc(struct drm_device *dev)
1003 {
1004         struct drm_i915_private *dev_priv = dev->dev_private;
1005         u32 fbc_ctl;
1006
1007         if (!I915_HAS_FBC(dev))
1008                 return;
1009
1010         /* Disable compression */
1011         fbc_ctl = I915_READ(FBC_CONTROL);
1012         fbc_ctl &= ~FBC_CTL_EN;
1013         I915_WRITE(FBC_CONTROL, fbc_ctl);
1014
1015         /* Wait for compressing bit to clear */
1016         while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING)
1017                 ; /* nothing */
1018
1019         intel_wait_for_vblank(dev);
1020
1021         DRM_DEBUG_KMS("disabled FBC\n");
1022 }
1023
1024 static bool i8xx_fbc_enabled(struct drm_crtc *crtc)
1025 {
1026         struct drm_device *dev = crtc->dev;
1027         struct drm_i915_private *dev_priv = dev->dev_private;
1028
1029         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1030 }
1031
1032 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1033 {
1034         struct drm_device *dev = crtc->dev;
1035         struct drm_i915_private *dev_priv = dev->dev_private;
1036         struct drm_framebuffer *fb = crtc->fb;
1037         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1038         struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
1039         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1040         int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1041                      DPFC_CTL_PLANEB);
1042         unsigned long stall_watermark = 200;
1043         u32 dpfc_ctl;
1044
1045         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1046         dev_priv->cfb_fence = obj_priv->fence_reg;
1047         dev_priv->cfb_plane = intel_crtc->plane;
1048
1049         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1050         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1051                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1052                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1053         } else {
1054                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1055         }
1056
1057         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1058         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1059                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1060                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1061         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1062
1063         /* enable it... */
1064         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1065
1066         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1067 }
1068
1069 void g4x_disable_fbc(struct drm_device *dev)
1070 {
1071         struct drm_i915_private *dev_priv = dev->dev_private;
1072         u32 dpfc_ctl;
1073
1074         /* Disable compression */
1075         dpfc_ctl = I915_READ(DPFC_CONTROL);
1076         dpfc_ctl &= ~DPFC_CTL_EN;
1077         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1078         intel_wait_for_vblank(dev);
1079
1080         DRM_DEBUG_KMS("disabled FBC\n");
1081 }
1082
1083 static bool g4x_fbc_enabled(struct drm_crtc *crtc)
1084 {
1085         struct drm_device *dev = crtc->dev;
1086         struct drm_i915_private *dev_priv = dev->dev_private;
1087
1088         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1089 }
1090
1091 /**
1092  * intel_update_fbc - enable/disable FBC as needed
1093  * @crtc: CRTC to point the compressor at
1094  * @mode: mode in use
1095  *
1096  * Set up the framebuffer compression hardware at mode set time.  We
1097  * enable it if possible:
1098  *   - plane A only (on pre-965)
1099  *   - no pixel mulitply/line duplication
1100  *   - no alpha buffer discard
1101  *   - no dual wide
1102  *   - framebuffer <= 2048 in width, 1536 in height
1103  *
1104  * We can't assume that any compression will take place (worst case),
1105  * so the compressed buffer has to be the same size as the uncompressed
1106  * one.  It also must reside (along with the line length buffer) in
1107  * stolen memory.
1108  *
1109  * We need to enable/disable FBC on a global basis.
1110  */
1111 static void intel_update_fbc(struct drm_crtc *crtc,
1112                              struct drm_display_mode *mode)
1113 {
1114         struct drm_device *dev = crtc->dev;
1115         struct drm_i915_private *dev_priv = dev->dev_private;
1116         struct drm_framebuffer *fb = crtc->fb;
1117         struct intel_framebuffer *intel_fb;
1118         struct drm_i915_gem_object *obj_priv;
1119         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1120         int plane = intel_crtc->plane;
1121
1122         if (!i915_powersave)
1123                 return;
1124
1125         if (!dev_priv->display.fbc_enabled ||
1126             !dev_priv->display.enable_fbc ||
1127             !dev_priv->display.disable_fbc)
1128                 return;
1129
1130         if (!crtc->fb)
1131                 return;
1132
1133         intel_fb = to_intel_framebuffer(fb);
1134         obj_priv = intel_fb->obj->driver_private;
1135
1136         /*
1137          * If FBC is already on, we just have to verify that we can
1138          * keep it that way...
1139          * Need to disable if:
1140          *   - changing FBC params (stride, fence, mode)
1141          *   - new fb is too large to fit in compressed buffer
1142          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1143          */
1144         if (intel_fb->obj->size > dev_priv->cfb_size) {
1145                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1146                                 "compression\n");
1147                 goto out_disable;
1148         }
1149         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1150             (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1151                 DRM_DEBUG_KMS("mode incompatible with compression, "
1152                                 "disabling\n");
1153                 goto out_disable;
1154         }
1155         if ((mode->hdisplay > 2048) ||
1156             (mode->vdisplay > 1536)) {
1157                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1158                 goto out_disable;
1159         }
1160         if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1161                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1162                 goto out_disable;
1163         }
1164         if (obj_priv->tiling_mode != I915_TILING_X) {
1165                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1166                 goto out_disable;
1167         }
1168
1169         if (dev_priv->display.fbc_enabled(crtc)) {
1170                 /* We can re-enable it in this case, but need to update pitch */
1171                 if (fb->pitch > dev_priv->cfb_pitch)
1172                         dev_priv->display.disable_fbc(dev);
1173                 if (obj_priv->fence_reg != dev_priv->cfb_fence)
1174                         dev_priv->display.disable_fbc(dev);
1175                 if (plane != dev_priv->cfb_plane)
1176                         dev_priv->display.disable_fbc(dev);
1177         }
1178
1179         if (!dev_priv->display.fbc_enabled(crtc)) {
1180                 /* Now try to turn it back on if possible */
1181                 dev_priv->display.enable_fbc(crtc, 500);
1182         }
1183
1184         return;
1185
1186 out_disable:
1187         DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1188         /* Multiple disables should be harmless */
1189         if (dev_priv->display.fbc_enabled(crtc))
1190                 dev_priv->display.disable_fbc(dev);
1191 }
1192
1193 static int
1194 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1195                     struct drm_framebuffer *old_fb)
1196 {
1197         struct drm_device *dev = crtc->dev;
1198         struct drm_i915_private *dev_priv = dev->dev_private;
1199         struct drm_i915_master_private *master_priv;
1200         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1201         struct intel_framebuffer *intel_fb;
1202         struct drm_i915_gem_object *obj_priv;
1203         struct drm_gem_object *obj;
1204         int pipe = intel_crtc->pipe;
1205         int plane = intel_crtc->plane;
1206         unsigned long Start, Offset;
1207         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1208         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1209         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1210         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1211         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1212         u32 dspcntr, alignment;
1213         int ret;
1214
1215         /* no fb bound */
1216         if (!crtc->fb) {
1217                 DRM_DEBUG_KMS("No FB bound\n");
1218                 return 0;
1219         }
1220
1221         switch (plane) {
1222         case 0:
1223         case 1:
1224                 break;
1225         default:
1226                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1227                 return -EINVAL;
1228         }
1229
1230         intel_fb = to_intel_framebuffer(crtc->fb);
1231         obj = intel_fb->obj;
1232         obj_priv = obj->driver_private;
1233
1234         switch (obj_priv->tiling_mode) {
1235         case I915_TILING_NONE:
1236                 alignment = 64 * 1024;
1237                 break;
1238         case I915_TILING_X:
1239                 /* pin() will align the object as required by fence */
1240                 alignment = 0;
1241                 break;
1242         case I915_TILING_Y:
1243                 /* FIXME: Is this true? */
1244                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1245                 return -EINVAL;
1246         default:
1247                 BUG();
1248         }
1249
1250         mutex_lock(&dev->struct_mutex);
1251         ret = i915_gem_object_pin(obj, alignment);
1252         if (ret != 0) {
1253                 mutex_unlock(&dev->struct_mutex);
1254                 return ret;
1255         }
1256
1257         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
1258         if (ret != 0) {
1259                 i915_gem_object_unpin(obj);
1260                 mutex_unlock(&dev->struct_mutex);
1261                 return ret;
1262         }
1263
1264         /* Install a fence for tiled scan-out. Pre-i965 always needs a fence,
1265          * whereas 965+ only requires a fence if using framebuffer compression.
1266          * For simplicity, we always install a fence as the cost is not that onerous.
1267          */
1268         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1269             obj_priv->tiling_mode != I915_TILING_NONE) {
1270                 ret = i915_gem_object_get_fence_reg(obj);
1271                 if (ret != 0) {
1272                         i915_gem_object_unpin(obj);
1273                         mutex_unlock(&dev->struct_mutex);
1274                         return ret;
1275                 }
1276         }
1277
1278         dspcntr = I915_READ(dspcntr_reg);
1279         /* Mask out pixel format bits in case we change it */
1280         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1281         switch (crtc->fb->bits_per_pixel) {
1282         case 8:
1283                 dspcntr |= DISPPLANE_8BPP;
1284                 break;
1285         case 16:
1286                 if (crtc->fb->depth == 15)
1287                         dspcntr |= DISPPLANE_15_16BPP;
1288                 else
1289                         dspcntr |= DISPPLANE_16BPP;
1290                 break;
1291         case 24:
1292         case 32:
1293                 if (crtc->fb->depth == 30)
1294                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1295                 else
1296                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1297                 break;
1298         default:
1299                 DRM_ERROR("Unknown color depth\n");
1300                 i915_gem_object_unpin(obj);
1301                 mutex_unlock(&dev->struct_mutex);
1302                 return -EINVAL;
1303         }
1304         if (IS_I965G(dev)) {
1305                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1306                         dspcntr |= DISPPLANE_TILED;
1307                 else
1308                         dspcntr &= ~DISPPLANE_TILED;
1309         }
1310
1311         if (IS_IGDNG(dev))
1312                 /* must disable */
1313                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1314
1315         I915_WRITE(dspcntr_reg, dspcntr);
1316
1317         Start = obj_priv->gtt_offset;
1318         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1319
1320         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1321         I915_WRITE(dspstride, crtc->fb->pitch);
1322         if (IS_I965G(dev)) {
1323                 I915_WRITE(dspbase, Offset);
1324                 I915_READ(dspbase);
1325                 I915_WRITE(dspsurf, Start);
1326                 I915_READ(dspsurf);
1327                 I915_WRITE(dsptileoff, (y << 16) | x);
1328         } else {
1329                 I915_WRITE(dspbase, Start + Offset);
1330                 I915_READ(dspbase);
1331         }
1332
1333         if ((IS_I965G(dev) || plane == 0))
1334                 intel_update_fbc(crtc, &crtc->mode);
1335
1336         intel_wait_for_vblank(dev);
1337
1338         if (old_fb) {
1339                 intel_fb = to_intel_framebuffer(old_fb);
1340                 obj_priv = intel_fb->obj->driver_private;
1341                 i915_gem_object_unpin(intel_fb->obj);
1342         }
1343         intel_increase_pllclock(crtc, true);
1344
1345         mutex_unlock(&dev->struct_mutex);
1346
1347         if (!dev->primary->master)
1348                 return 0;
1349
1350         master_priv = dev->primary->master->driver_priv;
1351         if (!master_priv->sarea_priv)
1352                 return 0;
1353
1354         if (pipe) {
1355                 master_priv->sarea_priv->pipeB_x = x;
1356                 master_priv->sarea_priv->pipeB_y = y;
1357         } else {
1358                 master_priv->sarea_priv->pipeA_x = x;
1359                 master_priv->sarea_priv->pipeA_y = y;
1360         }
1361
1362         return 0;
1363 }
1364
1365 /* Disable the VGA plane that we never use */
1366 static void i915_disable_vga (struct drm_device *dev)
1367 {
1368         struct drm_i915_private *dev_priv = dev->dev_private;
1369         u8 sr1;
1370         u32 vga_reg;
1371
1372         if (IS_IGDNG(dev))
1373                 vga_reg = CPU_VGACNTRL;
1374         else
1375                 vga_reg = VGACNTRL;
1376
1377         if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1378                 return;
1379
1380         I915_WRITE8(VGA_SR_INDEX, 1);
1381         sr1 = I915_READ8(VGA_SR_DATA);
1382         I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1383         udelay(100);
1384
1385         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1386 }
1387
1388 static void igdng_disable_pll_edp (struct drm_crtc *crtc)
1389 {
1390         struct drm_device *dev = crtc->dev;
1391         struct drm_i915_private *dev_priv = dev->dev_private;
1392         u32 dpa_ctl;
1393
1394         DRM_DEBUG_KMS("\n");
1395         dpa_ctl = I915_READ(DP_A);
1396         dpa_ctl &= ~DP_PLL_ENABLE;
1397         I915_WRITE(DP_A, dpa_ctl);
1398 }
1399
1400 static void igdng_enable_pll_edp (struct drm_crtc *crtc)
1401 {
1402         struct drm_device *dev = crtc->dev;
1403         struct drm_i915_private *dev_priv = dev->dev_private;
1404         u32 dpa_ctl;
1405
1406         dpa_ctl = I915_READ(DP_A);
1407         dpa_ctl |= DP_PLL_ENABLE;
1408         I915_WRITE(DP_A, dpa_ctl);
1409         udelay(200);
1410 }
1411
1412
1413 static void igdng_set_pll_edp (struct drm_crtc *crtc, int clock)
1414 {
1415         struct drm_device *dev = crtc->dev;
1416         struct drm_i915_private *dev_priv = dev->dev_private;
1417         u32 dpa_ctl;
1418
1419         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1420         dpa_ctl = I915_READ(DP_A);
1421         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1422
1423         if (clock < 200000) {
1424                 u32 temp;
1425                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1426                 /* workaround for 160Mhz:
1427                    1) program 0x4600c bits 15:0 = 0x8124
1428                    2) program 0x46010 bit 0 = 1
1429                    3) program 0x46034 bit 24 = 1
1430                    4) program 0x64000 bit 14 = 1
1431                    */
1432                 temp = I915_READ(0x4600c);
1433                 temp &= 0xffff0000;
1434                 I915_WRITE(0x4600c, temp | 0x8124);
1435
1436                 temp = I915_READ(0x46010);
1437                 I915_WRITE(0x46010, temp | 1);
1438
1439                 temp = I915_READ(0x46034);
1440                 I915_WRITE(0x46034, temp | (1 << 24));
1441         } else {
1442                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1443         }
1444         I915_WRITE(DP_A, dpa_ctl);
1445
1446         udelay(500);
1447 }
1448
1449 static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1450 {
1451         struct drm_device *dev = crtc->dev;
1452         struct drm_i915_private *dev_priv = dev->dev_private;
1453         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1454         int pipe = intel_crtc->pipe;
1455         int plane = intel_crtc->plane;
1456         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1457         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1458         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1459         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1460         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1461         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1462         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1463         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1464         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1465         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1466         int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1467         int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1468         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1469         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1470         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1471         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1472         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1473         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1474         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1475         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1476         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1477         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1478         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1479         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1480         u32 temp;
1481         int tries = 5, j, n;
1482
1483         /* XXX: When our outputs are all unaware of DPMS modes other than off
1484          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1485          */
1486         switch (mode) {
1487         case DRM_MODE_DPMS_ON:
1488         case DRM_MODE_DPMS_STANDBY:
1489         case DRM_MODE_DPMS_SUSPEND:
1490                 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
1491
1492                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1493                         temp = I915_READ(PCH_LVDS);
1494                         if ((temp & LVDS_PORT_EN) == 0) {
1495                                 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1496                                 POSTING_READ(PCH_LVDS);
1497                         }
1498                 }
1499
1500                 if (HAS_eDP) {
1501                         /* enable eDP PLL */
1502                         igdng_enable_pll_edp(crtc);
1503                 } else {
1504                         /* enable PCH DPLL */
1505                         temp = I915_READ(pch_dpll_reg);
1506                         if ((temp & DPLL_VCO_ENABLE) == 0) {
1507                                 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1508                                 I915_READ(pch_dpll_reg);
1509                         }
1510
1511                         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1512                         temp = I915_READ(fdi_rx_reg);
1513                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
1514                                         FDI_SEL_PCDCLK |
1515                                         FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
1516                         I915_READ(fdi_rx_reg);
1517                         udelay(200);
1518
1519                         /* Enable CPU FDI TX PLL, always on for IGDNG */
1520                         temp = I915_READ(fdi_tx_reg);
1521                         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1522                                 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1523                                 I915_READ(fdi_tx_reg);
1524                                 udelay(100);
1525                         }
1526                 }
1527
1528                 /* Enable panel fitting for LVDS */
1529                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1530                         temp = I915_READ(pf_ctl_reg);
1531                         I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1532
1533                         /* currently full aspect */
1534                         I915_WRITE(pf_win_pos, 0);
1535
1536                         I915_WRITE(pf_win_size,
1537                                    (dev_priv->panel_fixed_mode->hdisplay << 16) |
1538                                    (dev_priv->panel_fixed_mode->vdisplay));
1539                 }
1540
1541                 /* Enable CPU pipe */
1542                 temp = I915_READ(pipeconf_reg);
1543                 if ((temp & PIPEACONF_ENABLE) == 0) {
1544                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1545                         I915_READ(pipeconf_reg);
1546                         udelay(100);
1547                 }
1548
1549                 /* configure and enable CPU plane */
1550                 temp = I915_READ(dspcntr_reg);
1551                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1552                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1553                         /* Flush the plane changes */
1554                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1555                 }
1556
1557                 if (!HAS_eDP) {
1558                         /* enable CPU FDI TX and PCH FDI RX */
1559                         temp = I915_READ(fdi_tx_reg);
1560                         temp |= FDI_TX_ENABLE;
1561                         temp |= FDI_DP_PORT_WIDTH_X4; /* default */
1562                         temp &= ~FDI_LINK_TRAIN_NONE;
1563                         temp |= FDI_LINK_TRAIN_PATTERN_1;
1564                         I915_WRITE(fdi_tx_reg, temp);
1565                         I915_READ(fdi_tx_reg);
1566
1567                         temp = I915_READ(fdi_rx_reg);
1568                         temp &= ~FDI_LINK_TRAIN_NONE;
1569                         temp |= FDI_LINK_TRAIN_PATTERN_1;
1570                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1571                         I915_READ(fdi_rx_reg);
1572
1573                         udelay(150);
1574
1575                         /* Train FDI. */
1576                         /* umask FDI RX Interrupt symbol_lock and bit_lock bit
1577                            for train result */
1578                         temp = I915_READ(fdi_rx_imr_reg);
1579                         temp &= ~FDI_RX_SYMBOL_LOCK;
1580                         temp &= ~FDI_RX_BIT_LOCK;
1581                         I915_WRITE(fdi_rx_imr_reg, temp);
1582                         I915_READ(fdi_rx_imr_reg);
1583                         udelay(150);
1584
1585                         temp = I915_READ(fdi_rx_iir_reg);
1586                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1587
1588                         if ((temp & FDI_RX_BIT_LOCK) == 0) {
1589                                 for (j = 0; j < tries; j++) {
1590                                         temp = I915_READ(fdi_rx_iir_reg);
1591                                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1592                                                                 temp);
1593                                         if (temp & FDI_RX_BIT_LOCK)
1594                                                 break;
1595                                         udelay(200);
1596                                 }
1597                                 if (j != tries)
1598                                         I915_WRITE(fdi_rx_iir_reg,
1599                                                         temp | FDI_RX_BIT_LOCK);
1600                                 else
1601                                         DRM_DEBUG_KMS("train 1 fail\n");
1602                         } else {
1603                                 I915_WRITE(fdi_rx_iir_reg,
1604                                                 temp | FDI_RX_BIT_LOCK);
1605                                 DRM_DEBUG_KMS("train 1 ok 2!\n");
1606                         }
1607                         temp = I915_READ(fdi_tx_reg);
1608                         temp &= ~FDI_LINK_TRAIN_NONE;
1609                         temp |= FDI_LINK_TRAIN_PATTERN_2;
1610                         I915_WRITE(fdi_tx_reg, temp);
1611
1612                         temp = I915_READ(fdi_rx_reg);
1613                         temp &= ~FDI_LINK_TRAIN_NONE;
1614                         temp |= FDI_LINK_TRAIN_PATTERN_2;
1615                         I915_WRITE(fdi_rx_reg, temp);
1616
1617                         udelay(150);
1618
1619                         temp = I915_READ(fdi_rx_iir_reg);
1620                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1621
1622                         if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
1623                                 for (j = 0; j < tries; j++) {
1624                                         temp = I915_READ(fdi_rx_iir_reg);
1625                                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1626                                                                 temp);
1627                                         if (temp & FDI_RX_SYMBOL_LOCK)
1628                                                 break;
1629                                         udelay(200);
1630                                 }
1631                                 if (j != tries) {
1632                                         I915_WRITE(fdi_rx_iir_reg,
1633                                                         temp | FDI_RX_SYMBOL_LOCK);
1634                                         DRM_DEBUG_KMS("train 2 ok 1!\n");
1635                                 } else
1636                                         DRM_DEBUG_KMS("train 2 fail\n");
1637                         } else {
1638                                 I915_WRITE(fdi_rx_iir_reg,
1639                                                 temp | FDI_RX_SYMBOL_LOCK);
1640                                 DRM_DEBUG_KMS("train 2 ok 2!\n");
1641                         }
1642                         DRM_DEBUG_KMS("train done\n");
1643
1644                         /* set transcoder timing */
1645                         I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1646                         I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1647                         I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1648
1649                         I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1650                         I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1651                         I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1652
1653                         /* enable PCH transcoder */
1654                         temp = I915_READ(transconf_reg);
1655                         I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1656                         I915_READ(transconf_reg);
1657
1658                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1659                                 ;
1660
1661                         /* enable normal */
1662
1663                         temp = I915_READ(fdi_tx_reg);
1664                         temp &= ~FDI_LINK_TRAIN_NONE;
1665                         I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1666                                         FDI_TX_ENHANCE_FRAME_ENABLE);
1667                         I915_READ(fdi_tx_reg);
1668
1669                         temp = I915_READ(fdi_rx_reg);
1670                         temp &= ~FDI_LINK_TRAIN_NONE;
1671                         I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
1672                                         FDI_RX_ENHANCE_FRAME_ENABLE);
1673                         I915_READ(fdi_rx_reg);
1674
1675                         /* wait one idle pattern time */
1676                         udelay(100);
1677
1678                 }
1679
1680                 intel_crtc_load_lut(crtc);
1681
1682         break;
1683         case DRM_MODE_DPMS_OFF:
1684                 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
1685
1686                 /* Disable display plane */
1687                 temp = I915_READ(dspcntr_reg);
1688                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1689                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1690                         /* Flush the plane changes */
1691                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1692                         I915_READ(dspbase_reg);
1693                 }
1694
1695                 i915_disable_vga(dev);
1696
1697                 /* disable cpu pipe, disable after all planes disabled */
1698                 temp = I915_READ(pipeconf_reg);
1699                 if ((temp & PIPEACONF_ENABLE) != 0) {
1700                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1701                         I915_READ(pipeconf_reg);
1702                         n = 0;
1703                         /* wait for cpu pipe off, pipe state */
1704                         while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
1705                                 n++;
1706                                 if (n < 60) {
1707                                         udelay(500);
1708                                         continue;
1709                                 } else {
1710                                         DRM_DEBUG_KMS("pipe %d off delay\n",
1711                                                                 pipe);
1712                                         break;
1713                                 }
1714                         }
1715                 } else
1716                         DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
1717
1718                 udelay(100);
1719
1720                 /* Disable PF */
1721                 temp = I915_READ(pf_ctl_reg);
1722                 if ((temp & PF_ENABLE) != 0) {
1723                         I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1724                         I915_READ(pf_ctl_reg);
1725                 }
1726                 I915_WRITE(pf_win_size, 0);
1727
1728                 /* disable CPU FDI tx and PCH FDI rx */
1729                 temp = I915_READ(fdi_tx_reg);
1730                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
1731                 I915_READ(fdi_tx_reg);
1732
1733                 temp = I915_READ(fdi_rx_reg);
1734                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
1735                 I915_READ(fdi_rx_reg);
1736
1737                 udelay(100);
1738
1739                 /* still set train pattern 1 */
1740                 temp = I915_READ(fdi_tx_reg);
1741                 temp &= ~FDI_LINK_TRAIN_NONE;
1742                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1743                 I915_WRITE(fdi_tx_reg, temp);
1744
1745                 temp = I915_READ(fdi_rx_reg);
1746                 temp &= ~FDI_LINK_TRAIN_NONE;
1747                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1748                 I915_WRITE(fdi_rx_reg, temp);
1749
1750                 udelay(100);
1751
1752                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1753                         temp = I915_READ(PCH_LVDS);
1754                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
1755                         I915_READ(PCH_LVDS);
1756                         udelay(100);
1757                 }
1758
1759                 /* disable PCH transcoder */
1760                 temp = I915_READ(transconf_reg);
1761                 if ((temp & TRANS_ENABLE) != 0) {
1762                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
1763                         I915_READ(transconf_reg);
1764                         n = 0;
1765                         /* wait for PCH transcoder off, transcoder state */
1766                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
1767                                 n++;
1768                                 if (n < 60) {
1769                                         udelay(500);
1770                                         continue;
1771                                 } else {
1772                                         DRM_DEBUG_KMS("transcoder %d off "
1773                                                         "delay\n", pipe);
1774                                         break;
1775                                 }
1776                         }
1777                 }
1778
1779                 udelay(100);
1780
1781                 /* disable PCH DPLL */
1782                 temp = I915_READ(pch_dpll_reg);
1783                 if ((temp & DPLL_VCO_ENABLE) != 0) {
1784                         I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
1785                         I915_READ(pch_dpll_reg);
1786                 }
1787
1788                 if (HAS_eDP) {
1789                         igdng_disable_pll_edp(crtc);
1790                 }
1791
1792                 temp = I915_READ(fdi_rx_reg);
1793                 temp &= ~FDI_SEL_PCDCLK;
1794                 I915_WRITE(fdi_rx_reg, temp);
1795                 I915_READ(fdi_rx_reg);
1796
1797                 temp = I915_READ(fdi_rx_reg);
1798                 temp &= ~FDI_RX_PLL_ENABLE;
1799                 I915_WRITE(fdi_rx_reg, temp);
1800                 I915_READ(fdi_rx_reg);
1801
1802                 /* Disable CPU FDI TX PLL */
1803                 temp = I915_READ(fdi_tx_reg);
1804                 if ((temp & FDI_TX_PLL_ENABLE) != 0) {
1805                         I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
1806                         I915_READ(fdi_tx_reg);
1807                         udelay(100);
1808                 }
1809
1810                 /* Wait for the clocks to turn off. */
1811                 udelay(100);
1812                 break;
1813         }
1814 }
1815
1816 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
1817 {
1818         struct intel_overlay *overlay;
1819         int ret;
1820
1821         if (!enable && intel_crtc->overlay) {
1822                 overlay = intel_crtc->overlay;
1823                 mutex_lock(&overlay->dev->struct_mutex);
1824                 for (;;) {
1825                         ret = intel_overlay_switch_off(overlay);
1826                         if (ret == 0)
1827                                 break;
1828
1829                         ret = intel_overlay_recover_from_interrupt(overlay, 0);
1830                         if (ret != 0) {
1831                                 /* overlay doesn't react anymore. Usually
1832                                  * results in a black screen and an unkillable
1833                                  * X server. */
1834                                 BUG();
1835                                 overlay->hw_wedged = HW_WEDGED;
1836                                 break;
1837                         }
1838                 }
1839                 mutex_unlock(&overlay->dev->struct_mutex);
1840         }
1841         /* Let userspace switch the overlay on again. In most cases userspace
1842          * has to recompute where to put it anyway. */
1843
1844         return;
1845 }
1846
1847 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1848 {
1849         struct drm_device *dev = crtc->dev;
1850         struct drm_i915_private *dev_priv = dev->dev_private;
1851         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1852         int pipe = intel_crtc->pipe;
1853         int plane = intel_crtc->plane;
1854         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
1855         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1856         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1857         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1858         u32 temp;
1859
1860         /* XXX: When our outputs are all unaware of DPMS modes other than off
1861          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1862          */
1863         switch (mode) {
1864         case DRM_MODE_DPMS_ON:
1865         case DRM_MODE_DPMS_STANDBY:
1866         case DRM_MODE_DPMS_SUSPEND:
1867                 intel_update_watermarks(dev);
1868
1869                 /* Enable the DPLL */
1870                 temp = I915_READ(dpll_reg);
1871                 if ((temp & DPLL_VCO_ENABLE) == 0) {
1872                         I915_WRITE(dpll_reg, temp);
1873                         I915_READ(dpll_reg);
1874                         /* Wait for the clocks to stabilize. */
1875                         udelay(150);
1876                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1877                         I915_READ(dpll_reg);
1878                         /* Wait for the clocks to stabilize. */
1879                         udelay(150);
1880                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1881                         I915_READ(dpll_reg);
1882                         /* Wait for the clocks to stabilize. */
1883                         udelay(150);
1884                 }
1885
1886                 /* Enable the pipe */
1887                 temp = I915_READ(pipeconf_reg);
1888                 if ((temp & PIPEACONF_ENABLE) == 0)
1889                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1890
1891                 /* Enable the plane */
1892                 temp = I915_READ(dspcntr_reg);
1893                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1894                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1895                         /* Flush the plane changes */
1896                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1897                 }
1898
1899                 intel_crtc_load_lut(crtc);
1900
1901                 if ((IS_I965G(dev) || plane == 0))
1902                         intel_update_fbc(crtc, &crtc->mode);
1903
1904                 /* Give the overlay scaler a chance to enable if it's on this pipe */
1905                 intel_crtc_dpms_overlay(intel_crtc, true);
1906         break;
1907         case DRM_MODE_DPMS_OFF:
1908                 intel_update_watermarks(dev);
1909
1910                 /* Give the overlay scaler a chance to disable if it's on this pipe */
1911                 intel_crtc_dpms_overlay(intel_crtc, false);
1912
1913                 if (dev_priv->cfb_plane == plane &&
1914                     dev_priv->display.disable_fbc)
1915                         dev_priv->display.disable_fbc(dev);
1916
1917                 /* Disable the VGA plane that we never use */
1918                 i915_disable_vga(dev);
1919
1920                 /* Disable display plane */
1921                 temp = I915_READ(dspcntr_reg);
1922                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1923                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1924                         /* Flush the plane changes */
1925                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1926                         I915_READ(dspbase_reg);
1927                 }
1928
1929                 if (!IS_I9XX(dev)) {
1930                         /* Wait for vblank for the disable to take effect */
1931                         intel_wait_for_vblank(dev);
1932                 }
1933
1934                 /* Next, disable display pipes */
1935                 temp = I915_READ(pipeconf_reg);
1936                 if ((temp & PIPEACONF_ENABLE) != 0) {
1937                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1938                         I915_READ(pipeconf_reg);
1939                 }
1940
1941                 /* Wait for vblank for the disable to take effect. */
1942                 intel_wait_for_vblank(dev);
1943
1944                 temp = I915_READ(dpll_reg);
1945                 if ((temp & DPLL_VCO_ENABLE) != 0) {
1946                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
1947                         I915_READ(dpll_reg);
1948                 }
1949
1950                 /* Wait for the clocks to turn off. */
1951                 udelay(150);
1952                 break;
1953         }
1954 }
1955
1956 /**
1957  * Sets the power management mode of the pipe and plane.
1958  *
1959  * This code should probably grow support for turning the cursor off and back
1960  * on appropriately at the same time as we're turning the pipe off/on.
1961  */
1962 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
1963 {
1964         struct drm_device *dev = crtc->dev;
1965         struct drm_i915_private *dev_priv = dev->dev_private;
1966         struct drm_i915_master_private *master_priv;
1967         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1968         int pipe = intel_crtc->pipe;
1969         bool enabled;
1970
1971         dev_priv->display.dpms(crtc, mode);
1972
1973         intel_crtc->dpms_mode = mode;
1974
1975         if (!dev->primary->master)
1976                 return;
1977
1978         master_priv = dev->primary->master->driver_priv;
1979         if (!master_priv->sarea_priv)
1980                 return;
1981
1982         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
1983
1984         switch (pipe) {
1985         case 0:
1986                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
1987                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
1988                 break;
1989         case 1:
1990                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
1991                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
1992                 break;
1993         default:
1994                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
1995                 break;
1996         }
1997 }
1998
1999 static void intel_crtc_prepare (struct drm_crtc *crtc)
2000 {
2001         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2002         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2003 }
2004
2005 static void intel_crtc_commit (struct drm_crtc *crtc)
2006 {
2007         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2008         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2009 }
2010
2011 void intel_encoder_prepare (struct drm_encoder *encoder)
2012 {
2013         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2014         /* lvds has its own version of prepare see intel_lvds_prepare */
2015         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2016 }
2017
2018 void intel_encoder_commit (struct drm_encoder *encoder)
2019 {
2020         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2021         /* lvds has its own version of commit see intel_lvds_commit */
2022         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2023 }
2024
2025 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2026                                   struct drm_display_mode *mode,
2027                                   struct drm_display_mode *adjusted_mode)
2028 {
2029         struct drm_device *dev = crtc->dev;
2030         if (IS_IGDNG(dev)) {
2031                 /* FDI link clock is fixed at 2.7G */
2032                 if (mode->clock * 3 > 27000 * 4)
2033                         return MODE_CLOCK_HIGH;
2034         }
2035         return true;
2036 }
2037
2038 static int i945_get_display_clock_speed(struct drm_device *dev)
2039 {
2040         return 400000;
2041 }
2042
2043 static int i915_get_display_clock_speed(struct drm_device *dev)
2044 {
2045         return 333000;
2046 }
2047
2048 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2049 {
2050         return 200000;
2051 }
2052
2053 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2054 {
2055         u16 gcfgc = 0;
2056
2057         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2058
2059         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2060                 return 133000;
2061         else {
2062                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2063                 case GC_DISPLAY_CLOCK_333_MHZ:
2064                         return 333000;
2065                 default:
2066                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2067                         return 190000;
2068                 }
2069         }
2070 }
2071
2072 static int i865_get_display_clock_speed(struct drm_device *dev)
2073 {
2074         return 266000;
2075 }
2076
2077 static int i855_get_display_clock_speed(struct drm_device *dev)
2078 {
2079         u16 hpllcc = 0;
2080         /* Assume that the hardware is in the high speed state.  This
2081          * should be the default.
2082          */
2083         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2084         case GC_CLOCK_133_200:
2085         case GC_CLOCK_100_200:
2086                 return 200000;
2087         case GC_CLOCK_166_250:
2088                 return 250000;
2089         case GC_CLOCK_100_133:
2090                 return 133000;
2091         }
2092
2093         /* Shouldn't happen */
2094         return 0;
2095 }
2096
2097 static int i830_get_display_clock_speed(struct drm_device *dev)
2098 {
2099         return 133000;
2100 }
2101
2102 /**
2103  * Return the pipe currently connected to the panel fitter,
2104  * or -1 if the panel fitter is not present or not in use
2105  */
2106 int intel_panel_fitter_pipe (struct drm_device *dev)
2107 {
2108         struct drm_i915_private *dev_priv = dev->dev_private;
2109         u32  pfit_control;
2110
2111         /* i830 doesn't have a panel fitter */
2112         if (IS_I830(dev))
2113                 return -1;
2114
2115         pfit_control = I915_READ(PFIT_CONTROL);
2116
2117         /* See if the panel fitter is in use */
2118         if ((pfit_control & PFIT_ENABLE) == 0)
2119                 return -1;
2120
2121         /* 965 can place panel fitter on either pipe */
2122         if (IS_I965G(dev))
2123                 return (pfit_control >> 29) & 0x3;
2124
2125         /* older chips can only use pipe 1 */
2126         return 1;
2127 }
2128
2129 struct fdi_m_n {
2130         u32        tu;
2131         u32        gmch_m;
2132         u32        gmch_n;
2133         u32        link_m;
2134         u32        link_n;
2135 };
2136
2137 static void
2138 fdi_reduce_ratio(u32 *num, u32 *den)
2139 {
2140         while (*num > 0xffffff || *den > 0xffffff) {
2141                 *num >>= 1;
2142                 *den >>= 1;
2143         }
2144 }
2145
2146 #define DATA_N 0x800000
2147 #define LINK_N 0x80000
2148
2149 static void
2150 igdng_compute_m_n(int bits_per_pixel, int nlanes,
2151                 int pixel_clock, int link_clock,
2152                 struct fdi_m_n *m_n)
2153 {
2154         u64 temp;
2155
2156         m_n->tu = 64; /* default size */
2157
2158         temp = (u64) DATA_N * pixel_clock;
2159         temp = div_u64(temp, link_clock);
2160         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2161         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2162         m_n->gmch_n = DATA_N;
2163         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2164
2165         temp = (u64) LINK_N * pixel_clock;
2166         m_n->link_m = div_u64(temp, link_clock);
2167         m_n->link_n = LINK_N;
2168         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2169 }
2170
2171
2172 struct intel_watermark_params {
2173         unsigned long fifo_size;
2174         unsigned long max_wm;
2175         unsigned long default_wm;
2176         unsigned long guard_size;
2177         unsigned long cacheline_size;
2178 };
2179
2180 /* IGD has different values for various configs */
2181 static struct intel_watermark_params igd_display_wm = {
2182         IGD_DISPLAY_FIFO,
2183         IGD_MAX_WM,
2184         IGD_DFT_WM,
2185         IGD_GUARD_WM,
2186         IGD_FIFO_LINE_SIZE
2187 };
2188 static struct intel_watermark_params igd_display_hplloff_wm = {
2189         IGD_DISPLAY_FIFO,
2190         IGD_MAX_WM,
2191         IGD_DFT_HPLLOFF_WM,
2192         IGD_GUARD_WM,
2193         IGD_FIFO_LINE_SIZE
2194 };
2195 static struct intel_watermark_params igd_cursor_wm = {
2196         IGD_CURSOR_FIFO,
2197         IGD_CURSOR_MAX_WM,
2198         IGD_CURSOR_DFT_WM,
2199         IGD_CURSOR_GUARD_WM,
2200         IGD_FIFO_LINE_SIZE,
2201 };
2202 static struct intel_watermark_params igd_cursor_hplloff_wm = {
2203         IGD_CURSOR_FIFO,
2204         IGD_CURSOR_MAX_WM,
2205         IGD_CURSOR_DFT_WM,
2206         IGD_CURSOR_GUARD_WM,
2207         IGD_FIFO_LINE_SIZE
2208 };
2209 static struct intel_watermark_params g4x_wm_info = {
2210         G4X_FIFO_SIZE,
2211         G4X_MAX_WM,
2212         G4X_MAX_WM,
2213         2,
2214         G4X_FIFO_LINE_SIZE,
2215 };
2216 static struct intel_watermark_params i945_wm_info = {
2217         I945_FIFO_SIZE,
2218         I915_MAX_WM,
2219         1,
2220         2,
2221         I915_FIFO_LINE_SIZE
2222 };
2223 static struct intel_watermark_params i915_wm_info = {
2224         I915_FIFO_SIZE,
2225         I915_MAX_WM,
2226         1,
2227         2,
2228         I915_FIFO_LINE_SIZE
2229 };
2230 static struct intel_watermark_params i855_wm_info = {
2231         I855GM_FIFO_SIZE,
2232         I915_MAX_WM,
2233         1,
2234         2,
2235         I830_FIFO_LINE_SIZE
2236 };
2237 static struct intel_watermark_params i830_wm_info = {
2238         I830_FIFO_SIZE,
2239         I915_MAX_WM,
2240         1,
2241         2,
2242         I830_FIFO_LINE_SIZE
2243 };
2244
2245 /**
2246  * intel_calculate_wm - calculate watermark level
2247  * @clock_in_khz: pixel clock
2248  * @wm: chip FIFO params
2249  * @pixel_size: display pixel size
2250  * @latency_ns: memory latency for the platform
2251  *
2252  * Calculate the watermark level (the level at which the display plane will
2253  * start fetching from memory again).  Each chip has a different display
2254  * FIFO size and allocation, so the caller needs to figure that out and pass
2255  * in the correct intel_watermark_params structure.
2256  *
2257  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2258  * on the pixel size.  When it reaches the watermark level, it'll start
2259  * fetching FIFO line sized based chunks from memory until the FIFO fills
2260  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2261  * will occur, and a display engine hang could result.
2262  */
2263 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2264                                         struct intel_watermark_params *wm,
2265                                         int pixel_size,
2266                                         unsigned long latency_ns)
2267 {
2268         long entries_required, wm_size;
2269
2270         /*
2271          * Note: we need to make sure we don't overflow for various clock &
2272          * latency values.
2273          * clocks go from a few thousand to several hundred thousand.
2274          * latency is usually a few thousand
2275          */
2276         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2277                 1000;
2278         entries_required /= wm->cacheline_size;
2279
2280         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2281
2282         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2283
2284         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2285
2286         /* Don't promote wm_size to unsigned... */
2287         if (wm_size > (long)wm->max_wm)
2288                 wm_size = wm->max_wm;
2289         if (wm_size <= 0)
2290                 wm_size = wm->default_wm;
2291         return wm_size;
2292 }
2293
2294 struct cxsr_latency {
2295         int is_desktop;
2296         unsigned long fsb_freq;
2297         unsigned long mem_freq;
2298         unsigned long display_sr;
2299         unsigned long display_hpll_disable;
2300         unsigned long cursor_sr;
2301         unsigned long cursor_hpll_disable;
2302 };
2303
2304 static struct cxsr_latency cxsr_latency_table[] = {
2305         {1, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2306         {1, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2307         {1, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2308
2309         {1, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2310         {1, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2311         {1, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2312
2313         {1, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2314         {1, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2315         {1, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2316
2317         {0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2318         {0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2319         {0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2320
2321         {0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2322         {0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2323         {0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2324
2325         {0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2326         {0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2327         {0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2328 };
2329
2330 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
2331                                                    int mem)
2332 {
2333         int i;
2334         struct cxsr_latency *latency;
2335
2336         if (fsb == 0 || mem == 0)
2337                 return NULL;
2338
2339         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2340                 latency = &cxsr_latency_table[i];
2341                 if (is_desktop == latency->is_desktop &&
2342                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2343                         return latency;
2344         }
2345
2346         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2347
2348         return NULL;
2349 }
2350
2351 static void igd_disable_cxsr(struct drm_device *dev)
2352 {
2353         struct drm_i915_private *dev_priv = dev->dev_private;
2354         u32 reg;
2355
2356         /* deactivate cxsr */
2357         reg = I915_READ(DSPFW3);
2358         reg &= ~(IGD_SELF_REFRESH_EN);
2359         I915_WRITE(DSPFW3, reg);
2360         DRM_INFO("Big FIFO is disabled\n");
2361 }
2362
2363 static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
2364                             int pixel_size)
2365 {
2366         struct drm_i915_private *dev_priv = dev->dev_private;
2367         u32 reg;
2368         unsigned long wm;
2369         struct cxsr_latency *latency;
2370
2371         latency = intel_get_cxsr_latency(IS_IGDG(dev), dev_priv->fsb_freq,
2372                 dev_priv->mem_freq);
2373         if (!latency) {
2374                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2375                 igd_disable_cxsr(dev);
2376                 return;
2377         }
2378
2379         /* Display SR */
2380         wm = intel_calculate_wm(clock, &igd_display_wm, pixel_size,
2381                                 latency->display_sr);
2382         reg = I915_READ(DSPFW1);
2383         reg &= 0x7fffff;
2384         reg |= wm << 23;
2385         I915_WRITE(DSPFW1, reg);
2386         DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2387
2388         /* cursor SR */
2389         wm = intel_calculate_wm(clock, &igd_cursor_wm, pixel_size,
2390                                 latency->cursor_sr);
2391         reg = I915_READ(DSPFW3);
2392         reg &= ~(0x3f << 24);
2393         reg |= (wm & 0x3f) << 24;
2394         I915_WRITE(DSPFW3, reg);
2395
2396         /* Display HPLL off SR */
2397         wm = intel_calculate_wm(clock, &igd_display_hplloff_wm,
2398                 latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
2399         reg = I915_READ(DSPFW3);
2400         reg &= 0xfffffe00;
2401         reg |= wm & 0x1ff;
2402         I915_WRITE(DSPFW3, reg);
2403
2404         /* cursor HPLL off SR */
2405         wm = intel_calculate_wm(clock, &igd_cursor_hplloff_wm, pixel_size,
2406                                 latency->cursor_hpll_disable);
2407         reg = I915_READ(DSPFW3);
2408         reg &= ~(0x3f << 16);
2409         reg |= (wm & 0x3f) << 16;
2410         I915_WRITE(DSPFW3, reg);
2411         DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2412
2413         /* activate cxsr */
2414         reg = I915_READ(DSPFW3);
2415         reg |= IGD_SELF_REFRESH_EN;
2416         I915_WRITE(DSPFW3, reg);
2417
2418         DRM_INFO("Big FIFO is enabled\n");
2419
2420         return;
2421 }
2422
2423 /*
2424  * Latency for FIFO fetches is dependent on several factors:
2425  *   - memory configuration (speed, channels)
2426  *   - chipset
2427  *   - current MCH state
2428  * It can be fairly high in some situations, so here we assume a fairly
2429  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2430  * set this value too high, the FIFO will fetch frequently to stay full)
2431  * and power consumption (set it too low to save power and we might see
2432  * FIFO underruns and display "flicker").
2433  *
2434  * A value of 5us seems to be a good balance; safe for very low end
2435  * platforms but not overly aggressive on lower latency configs.
2436  */
2437 const static int latency_ns = 5000;
2438
2439 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2440 {
2441         struct drm_i915_private *dev_priv = dev->dev_private;
2442         uint32_t dsparb = I915_READ(DSPARB);
2443         int size;
2444
2445         if (plane == 0)
2446                 size = dsparb & 0x7f;
2447         else
2448                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2449                         (dsparb & 0x7f);
2450
2451         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2452                         plane ? "B" : "A", size);
2453
2454         return size;
2455 }
2456
2457 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2458 {
2459         struct drm_i915_private *dev_priv = dev->dev_private;
2460         uint32_t dsparb = I915_READ(DSPARB);
2461         int size;
2462
2463         if (plane == 0)
2464                 size = dsparb & 0x1ff;
2465         else
2466                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2467                         (dsparb & 0x1ff);
2468         size >>= 1; /* Convert to cachelines */
2469
2470         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2471                         plane ? "B" : "A", size);
2472
2473         return size;
2474 }
2475
2476 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2477 {
2478         struct drm_i915_private *dev_priv = dev->dev_private;
2479         uint32_t dsparb = I915_READ(DSPARB);
2480         int size;
2481
2482         size = dsparb & 0x7f;
2483         size >>= 2; /* Convert to cachelines */
2484
2485         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2486                         plane ? "B" : "A",
2487                   size);
2488
2489         return size;
2490 }
2491
2492 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2493 {
2494         struct drm_i915_private *dev_priv = dev->dev_private;
2495         uint32_t dsparb = I915_READ(DSPARB);
2496         int size;
2497
2498         size = dsparb & 0x7f;
2499         size >>= 1; /* Convert to cachelines */
2500
2501         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2502                         plane ? "B" : "A", size);
2503
2504         return size;
2505 }
2506
2507 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
2508                           int planeb_clock, int sr_hdisplay, int pixel_size)
2509 {
2510         struct drm_i915_private *dev_priv = dev->dev_private;
2511         int total_size, cacheline_size;
2512         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
2513         struct intel_watermark_params planea_params, planeb_params;
2514         unsigned long line_time_us;
2515         int sr_clock, sr_entries = 0, entries_required;
2516
2517         /* Create copies of the base settings for each pipe */
2518         planea_params = planeb_params = g4x_wm_info;
2519
2520         /* Grab a couple of global values before we overwrite them */
2521         total_size = planea_params.fifo_size;
2522         cacheline_size = planea_params.cacheline_size;
2523
2524         /*
2525          * Note: we need to make sure we don't overflow for various clock &
2526          * latency values.
2527          * clocks go from a few thousand to several hundred thousand.
2528          * latency is usually a few thousand
2529          */
2530         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
2531                 1000;
2532         entries_required /= G4X_FIFO_LINE_SIZE;
2533         planea_wm = entries_required + planea_params.guard_size;
2534
2535         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
2536                 1000;
2537         entries_required /= G4X_FIFO_LINE_SIZE;
2538         planeb_wm = entries_required + planeb_params.guard_size;
2539
2540         cursora_wm = cursorb_wm = 16;
2541         cursor_sr = 32;
2542
2543         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2544
2545         /* Calc sr entries for one plane configs */
2546         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2547                 /* self-refresh has much higher latency */
2548                 const static int sr_latency_ns = 12000;
2549
2550                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2551                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2552
2553                 /* Use ns/us then divide to preserve precision */
2554                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2555                               pixel_size * sr_hdisplay) / 1000;
2556                 sr_entries = roundup(sr_entries / cacheline_size, 1);
2557                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2558                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2559         }
2560
2561         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
2562                   planea_wm, planeb_wm, sr_entries);
2563
2564         planea_wm &= 0x3f;
2565         planeb_wm &= 0x3f;
2566
2567         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
2568                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
2569                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
2570         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
2571                    (cursora_wm << DSPFW_CURSORA_SHIFT));
2572         /* HPLL off in SR has some issues on G4x... disable it */
2573         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
2574                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
2575 }
2576
2577 static void i965_update_wm(struct drm_device *dev, int planea_clock,
2578                            int planeb_clock, int sr_hdisplay, int pixel_size)
2579 {
2580         struct drm_i915_private *dev_priv = dev->dev_private;
2581         unsigned long line_time_us;
2582         int sr_clock, sr_entries, srwm = 1;
2583
2584         /* Calc sr entries for one plane configs */
2585         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2586                 /* self-refresh has much higher latency */
2587                 const static int sr_latency_ns = 12000;
2588
2589                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2590                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2591
2592                 /* Use ns/us then divide to preserve precision */
2593                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2594                               pixel_size * sr_hdisplay) / 1000;
2595                 sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
2596                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2597                 srwm = I945_FIFO_SIZE - sr_entries;
2598                 if (srwm < 0)
2599                         srwm = 1;
2600                 srwm &= 0x3f;
2601                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2602         }
2603
2604         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2605                       srwm);
2606
2607         /* 965 has limitations... */
2608         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
2609                    (8 << 0));
2610         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
2611 }
2612
2613 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2614                            int planeb_clock, int sr_hdisplay, int pixel_size)
2615 {
2616         struct drm_i915_private *dev_priv = dev->dev_private;
2617         uint32_t fwater_lo;
2618         uint32_t fwater_hi;
2619         int total_size, cacheline_size, cwm, srwm = 1;
2620         int planea_wm, planeb_wm;
2621         struct intel_watermark_params planea_params, planeb_params;
2622         unsigned long line_time_us;
2623         int sr_clock, sr_entries = 0;
2624
2625         /* Create copies of the base settings for each pipe */
2626         if (IS_I965GM(dev) || IS_I945GM(dev))
2627                 planea_params = planeb_params = i945_wm_info;
2628         else if (IS_I9XX(dev))
2629                 planea_params = planeb_params = i915_wm_info;
2630         else
2631                 planea_params = planeb_params = i855_wm_info;
2632
2633         /* Grab a couple of global values before we overwrite them */
2634         total_size = planea_params.fifo_size;
2635         cacheline_size = planea_params.cacheline_size;
2636
2637         /* Update per-plane FIFO sizes */
2638         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2639         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
2640
2641         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
2642                                        pixel_size, latency_ns);
2643         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
2644                                        pixel_size, latency_ns);
2645         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2646
2647         /*
2648          * Overlay gets an aggressive default since video jitter is bad.
2649          */
2650         cwm = 2;
2651
2652         /* Calc sr entries for one plane configs */
2653         if (HAS_FW_BLC(dev) && sr_hdisplay &&
2654             (!planea_clock || !planeb_clock)) {
2655                 /* self-refresh has much higher latency */
2656                 const static int sr_latency_ns = 6000;
2657
2658                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2659                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2660
2661                 /* Use ns/us then divide to preserve precision */
2662                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2663                               pixel_size * sr_hdisplay) / 1000;
2664                 sr_entries = roundup(sr_entries / cacheline_size, 1);
2665                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
2666                 srwm = total_size - sr_entries;
2667                 if (srwm < 0)
2668                         srwm = 1;
2669                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f));
2670         }
2671
2672         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2673                   planea_wm, planeb_wm, cwm, srwm);
2674
2675         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
2676         fwater_hi = (cwm & 0x1f);
2677
2678         /* Set request length to 8 cachelines per fetch */
2679         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
2680         fwater_hi = fwater_hi | (1 << 8);
2681
2682         I915_WRITE(FW_BLC, fwater_lo);
2683         I915_WRITE(FW_BLC2, fwater_hi);
2684 }
2685
2686 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
2687                            int unused2, int pixel_size)
2688 {
2689         struct drm_i915_private *dev_priv = dev->dev_private;
2690         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
2691         int planea_wm;
2692
2693         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2694
2695         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
2696                                        pixel_size, latency_ns);
2697         fwater_lo |= (3<<8) | planea_wm;
2698
2699         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
2700
2701         I915_WRITE(FW_BLC, fwater_lo);
2702 }
2703
2704 /**
2705  * intel_update_watermarks - update FIFO watermark values based on current modes
2706  *
2707  * Calculate watermark values for the various WM regs based on current mode
2708  * and plane configuration.
2709  *
2710  * There are several cases to deal with here:
2711  *   - normal (i.e. non-self-refresh)
2712  *   - self-refresh (SR) mode
2713  *   - lines are large relative to FIFO size (buffer can hold up to 2)
2714  *   - lines are small relative to FIFO size (buffer can hold more than 2
2715  *     lines), so need to account for TLB latency
2716  *
2717  *   The normal calculation is:
2718  *     watermark = dotclock * bytes per pixel * latency
2719  *   where latency is platform & configuration dependent (we assume pessimal
2720  *   values here).
2721  *
2722  *   The SR calculation is:
2723  *     watermark = (trunc(latency/line time)+1) * surface width *
2724  *       bytes per pixel
2725  *   where
2726  *     line time = htotal / dotclock
2727  *   and latency is assumed to be high, as above.
2728  *
2729  * The final value programmed to the register should always be rounded up,
2730  * and include an extra 2 entries to account for clock crossings.
2731  *
2732  * We don't use the sprite, so we can ignore that.  And on Crestline we have
2733  * to set the non-SR watermarks to 8.
2734   */
2735 static void intel_update_watermarks(struct drm_device *dev)
2736 {
2737         struct drm_i915_private *dev_priv = dev->dev_private;
2738         struct drm_crtc *crtc;
2739         struct intel_crtc *intel_crtc;
2740         int sr_hdisplay = 0;
2741         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
2742         int enabled = 0, pixel_size = 0;
2743
2744         if (!dev_priv->display.update_wm)
2745                 return;
2746
2747         /* Get the clock config from both planes */
2748         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2749                 intel_crtc = to_intel_crtc(crtc);
2750                 if (crtc->enabled) {
2751                         enabled++;
2752                         if (intel_crtc->plane == 0) {
2753                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
2754                                           intel_crtc->pipe, crtc->mode.clock);
2755                                 planea_clock = crtc->mode.clock;
2756                         } else {
2757                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
2758                                           intel_crtc->pipe, crtc->mode.clock);
2759                                 planeb_clock = crtc->mode.clock;
2760                         }
2761                         sr_hdisplay = crtc->mode.hdisplay;
2762                         sr_clock = crtc->mode.clock;
2763                         if (crtc->fb)
2764                                 pixel_size = crtc->fb->bits_per_pixel / 8;
2765                         else
2766                                 pixel_size = 4; /* by default */
2767                 }
2768         }
2769
2770         if (enabled <= 0)
2771                 return;
2772
2773         /* Single plane configs can enable self refresh */
2774         if (enabled == 1 && IS_IGD(dev))
2775                 igd_enable_cxsr(dev, sr_clock, pixel_size);
2776         else if (IS_IGD(dev))
2777                 igd_disable_cxsr(dev);
2778
2779         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
2780                                     sr_hdisplay, pixel_size);
2781 }
2782
2783 static int intel_crtc_mode_set(struct drm_crtc *crtc,
2784                                struct drm_display_mode *mode,
2785                                struct drm_display_mode *adjusted_mode,
2786                                int x, int y,
2787                                struct drm_framebuffer *old_fb)
2788 {
2789         struct drm_device *dev = crtc->dev;
2790         struct drm_i915_private *dev_priv = dev->dev_private;
2791         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2792         int pipe = intel_crtc->pipe;
2793         int plane = intel_crtc->plane;
2794         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
2795         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2796         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
2797         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2798         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2799         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
2800         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
2801         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
2802         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
2803         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
2804         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
2805         int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
2806         int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
2807         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
2808         int refclk, num_outputs = 0;
2809         intel_clock_t clock, reduced_clock;
2810         u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
2811         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
2812         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
2813         bool is_edp = false;
2814         struct drm_mode_config *mode_config = &dev->mode_config;
2815         struct drm_connector *connector;
2816         const intel_limit_t *limit;
2817         int ret;
2818         struct fdi_m_n m_n = {0};
2819         int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
2820         int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
2821         int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
2822         int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
2823         int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
2824         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
2825         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
2826         int lvds_reg = LVDS;
2827         u32 temp;
2828         int sdvo_pixel_multiply;
2829         int target_clock;
2830
2831         drm_vblank_pre_modeset(dev, pipe);
2832
2833         list_for_each_entry(connector, &mode_config->connector_list, head) {
2834                 struct intel_output *intel_output = to_intel_output(connector);
2835
2836                 if (!connector->encoder || connector->encoder->crtc != crtc)
2837                         continue;
2838
2839                 switch (intel_output->type) {
2840                 case INTEL_OUTPUT_LVDS:
2841                         is_lvds = true;
2842                         break;
2843                 case INTEL_OUTPUT_SDVO:
2844                 case INTEL_OUTPUT_HDMI:
2845                         is_sdvo = true;
2846                         if (intel_output->needs_tv_clock)
2847                                 is_tv = true;
2848                         break;
2849                 case INTEL_OUTPUT_DVO:
2850                         is_dvo = true;
2851                         break;
2852                 case INTEL_OUTPUT_TVOUT:
2853                         is_tv = true;
2854                         break;
2855                 case INTEL_OUTPUT_ANALOG:
2856                         is_crt = true;
2857                         break;
2858                 case INTEL_OUTPUT_DISPLAYPORT:
2859                         is_dp = true;
2860                         break;
2861                 case INTEL_OUTPUT_EDP:
2862                         is_edp = true;
2863                         break;
2864                 }
2865
2866                 num_outputs++;
2867         }
2868
2869         if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
2870                 refclk = dev_priv->lvds_ssc_freq * 1000;
2871                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
2872                                         refclk / 1000);
2873         } else if (IS_I9XX(dev)) {
2874                 refclk = 96000;
2875                 if (IS_IGDNG(dev))
2876                         refclk = 120000; /* 120Mhz refclk */
2877         } else {
2878                 refclk = 48000;
2879         }
2880
2881
2882         /*
2883          * Returns a set of divisors for the desired target clock with the given
2884          * refclk, or FALSE.  The returned values represent the clock equation:
2885          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
2886          */
2887         limit = intel_limit(crtc);
2888         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
2889         if (!ok) {
2890                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
2891                 drm_vblank_post_modeset(dev, pipe);
2892                 return -EINVAL;
2893         }
2894
2895         if (is_lvds && limit->find_reduced_pll &&
2896                         dev_priv->lvds_downclock_avail) {
2897                 memcpy(&reduced_clock, &clock, sizeof(intel_clock_t));
2898                 has_reduced_clock = limit->find_reduced_pll(limit, crtc,
2899                                                             dev_priv->lvds_downclock,
2900                                                             refclk,
2901                                                             &reduced_clock);
2902                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
2903                         /*
2904                          * If the different P is found, it means that we can't
2905                          * switch the display clock by using the FP0/FP1.
2906                          * In such case we will disable the LVDS downclock
2907                          * feature.
2908                          */
2909                         DRM_DEBUG_KMS("Different P is found for "
2910                                                 "LVDS clock/downclock\n");
2911                         has_reduced_clock = 0;
2912                 }
2913         }
2914         /* SDVO TV has fixed PLL values depend on its clock range,
2915            this mirrors vbios setting. */
2916         if (is_sdvo && is_tv) {
2917                 if (adjusted_mode->clock >= 100000
2918                                 && adjusted_mode->clock < 140500) {
2919                         clock.p1 = 2;
2920                         clock.p2 = 10;
2921                         clock.n = 3;
2922                         clock.m1 = 16;
2923                         clock.m2 = 8;
2924                 } else if (adjusted_mode->clock >= 140500
2925                                 && adjusted_mode->clock <= 200000) {
2926                         clock.p1 = 1;
2927                         clock.p2 = 10;
2928                         clock.n = 6;
2929                         clock.m1 = 12;
2930                         clock.m2 = 8;
2931                 }
2932         }
2933
2934         /* FDI link */
2935         if (IS_IGDNG(dev)) {
2936                 int lane, link_bw, bpp;
2937                 /* eDP doesn't require FDI link, so just set DP M/N
2938                    according to current link config */
2939                 if (is_edp) {
2940                         struct drm_connector *edp;
2941                         target_clock = mode->clock;
2942                         edp = intel_pipe_get_output(crtc);
2943                         intel_edp_link_config(to_intel_output(edp),
2944                                         &lane, &link_bw);
2945                 } else {
2946                         /* DP over FDI requires target mode clock
2947                            instead of link clock */
2948                         if (is_dp)
2949                                 target_clock = mode->clock;
2950                         else
2951                                 target_clock = adjusted_mode->clock;
2952                         lane = 4;
2953                         link_bw = 270000;
2954                 }
2955
2956                 /* determine panel color depth */
2957                 temp = I915_READ(pipeconf_reg);
2958
2959                 switch (temp & PIPE_BPC_MASK) {
2960                 case PIPE_8BPC:
2961                         bpp = 24;
2962                         break;
2963                 case PIPE_10BPC:
2964                         bpp = 30;
2965                         break;
2966                 case PIPE_6BPC:
2967                         bpp = 18;
2968                         break;
2969                 case PIPE_12BPC:
2970                         bpp = 36;
2971                         break;
2972                 default:
2973                         DRM_ERROR("unknown pipe bpc value\n");
2974                         bpp = 24;
2975                 }
2976
2977                 igdng_compute_m_n(bpp, lane, target_clock,
2978                                   link_bw, &m_n);
2979         }
2980
2981         /* Ironlake: try to setup display ref clock before DPLL
2982          * enabling. This is only under driver's control after
2983          * PCH B stepping, previous chipset stepping should be
2984          * ignoring this setting.
2985          */
2986         if (IS_IGDNG(dev)) {
2987                 temp = I915_READ(PCH_DREF_CONTROL);
2988                 /* Always enable nonspread source */
2989                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
2990                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
2991                 I915_WRITE(PCH_DREF_CONTROL, temp);
2992                 POSTING_READ(PCH_DREF_CONTROL);
2993
2994                 temp &= ~DREF_SSC_SOURCE_MASK;
2995                 temp |= DREF_SSC_SOURCE_ENABLE;
2996                 I915_WRITE(PCH_DREF_CONTROL, temp);
2997                 POSTING_READ(PCH_DREF_CONTROL);
2998
2999                 udelay(200);
3000
3001                 if (is_edp) {
3002                         if (dev_priv->lvds_use_ssc) {
3003                                 temp |= DREF_SSC1_ENABLE;
3004                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3005                                 POSTING_READ(PCH_DREF_CONTROL);
3006
3007                                 udelay(200);
3008
3009                                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3010                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3011                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3012                                 POSTING_READ(PCH_DREF_CONTROL);
3013                         } else {
3014                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3015                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3016                                 POSTING_READ(PCH_DREF_CONTROL);
3017                         }
3018                 }
3019         }
3020
3021         if (IS_IGD(dev)) {
3022                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3023                 if (has_reduced_clock)
3024                         fp2 = (1 << reduced_clock.n) << 16 |
3025                                 reduced_clock.m1 << 8 | reduced_clock.m2;
3026         } else {
3027                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3028                 if (has_reduced_clock)
3029                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3030                                 reduced_clock.m2;
3031         }
3032
3033         if (!IS_IGDNG(dev))
3034                 dpll = DPLL_VGA_MODE_DIS;
3035
3036         if (IS_I9XX(dev)) {
3037                 if (is_lvds)
3038                         dpll |= DPLLB_MODE_LVDS;
3039                 else
3040                         dpll |= DPLLB_MODE_DAC_SERIAL;
3041                 if (is_sdvo) {
3042                         dpll |= DPLL_DVO_HIGH_SPEED;
3043                         sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3044                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3045                                 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3046                         else if (IS_IGDNG(dev))
3047                                 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3048                 }
3049                 if (is_dp)
3050                         dpll |= DPLL_DVO_HIGH_SPEED;
3051
3052                 /* compute bitmask from p1 value */
3053                 if (IS_IGD(dev))
3054                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD;
3055                 else {
3056                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3057                         /* also FPA1 */
3058                         if (IS_IGDNG(dev))
3059                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3060                         if (IS_G4X(dev) && has_reduced_clock)
3061                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3062                 }
3063                 switch (clock.p2) {
3064                 case 5:
3065                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3066                         break;
3067                 case 7:
3068                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3069                         break;
3070                 case 10:
3071                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3072                         break;
3073                 case 14:
3074                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3075                         break;
3076                 }
3077                 if (IS_I965G(dev) && !IS_IGDNG(dev))
3078                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3079         } else {
3080                 if (is_lvds) {
3081                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3082                 } else {
3083                         if (clock.p1 == 2)
3084                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
3085                         else
3086                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3087                         if (clock.p2 == 4)
3088                                 dpll |= PLL_P2_DIVIDE_BY_4;
3089                 }
3090         }
3091
3092         if (is_sdvo && is_tv)
3093                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3094         else if (is_tv)
3095                 /* XXX: just matching BIOS for now */
3096                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3097                 dpll |= 3;
3098         else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
3099                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3100         else
3101                 dpll |= PLL_REF_INPUT_DREFCLK;
3102
3103         /* setup pipeconf */
3104         pipeconf = I915_READ(pipeconf_reg);
3105
3106         /* Set up the display plane register */
3107         dspcntr = DISPPLANE_GAMMA_ENABLE;
3108
3109         /* IGDNG's plane is forced to pipe, bit 24 is to
3110            enable color space conversion */
3111         if (!IS_IGDNG(dev)) {
3112                 if (pipe == 0)
3113                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3114                 else
3115                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3116         }
3117
3118         if (pipe == 0 && !IS_I965G(dev)) {
3119                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3120                  * core speed.
3121                  *
3122                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3123                  * pipe == 0 check?
3124                  */
3125                 if (mode->clock >
3126                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3127                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
3128                 else
3129                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3130         }
3131
3132         dspcntr |= DISPLAY_PLANE_ENABLE;
3133         pipeconf |= PIPEACONF_ENABLE;
3134         dpll |= DPLL_VCO_ENABLE;
3135
3136
3137         /* Disable the panel fitter if it was on our pipe */
3138         if (!IS_IGDNG(dev) && intel_panel_fitter_pipe(dev) == pipe)
3139                 I915_WRITE(PFIT_CONTROL, 0);
3140
3141         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3142         drm_mode_debug_printmodeline(mode);
3143
3144         /* assign to IGDNG registers */
3145         if (IS_IGDNG(dev)) {
3146                 fp_reg = pch_fp_reg;
3147                 dpll_reg = pch_dpll_reg;
3148         }
3149
3150         if (is_edp) {
3151                 igdng_disable_pll_edp(crtc);
3152         } else if ((dpll & DPLL_VCO_ENABLE)) {
3153                 I915_WRITE(fp_reg, fp);
3154                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3155                 I915_READ(dpll_reg);
3156                 udelay(150);
3157         }
3158
3159         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3160          * This is an exception to the general rule that mode_set doesn't turn
3161          * things on.
3162          */
3163         if (is_lvds) {
3164                 u32 lvds;
3165
3166                 if (IS_IGDNG(dev))
3167                         lvds_reg = PCH_LVDS;
3168
3169                 lvds = I915_READ(lvds_reg);
3170                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
3171                 /* set the corresponsding LVDS_BORDER bit */
3172                 lvds |= dev_priv->lvds_border_bits;
3173                 /* Set the B0-B3 data pairs corresponding to whether we're going to
3174                  * set the DPLLs for dual-channel mode or not.
3175                  */
3176                 if (clock.p2 == 7)
3177                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3178                 else
3179                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3180
3181                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3182                  * appropriately here, but we need to look more thoroughly into how
3183                  * panels behave in the two modes.
3184                  */
3185
3186                 I915_WRITE(lvds_reg, lvds);
3187                 I915_READ(lvds_reg);
3188         }
3189         if (is_dp)
3190                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3191
3192         if (!is_edp) {
3193                 I915_WRITE(fp_reg, fp);
3194                 I915_WRITE(dpll_reg, dpll);
3195                 I915_READ(dpll_reg);
3196                 /* Wait for the clocks to stabilize. */
3197                 udelay(150);
3198
3199                 if (IS_I965G(dev) && !IS_IGDNG(dev)) {
3200                         if (is_sdvo) {
3201                                 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3202                                 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
3203                                         ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
3204                         } else
3205                                 I915_WRITE(dpll_md_reg, 0);
3206                 } else {
3207                         /* write it again -- the BIOS does, after all */
3208                         I915_WRITE(dpll_reg, dpll);
3209                 }
3210                 I915_READ(dpll_reg);
3211                 /* Wait for the clocks to stabilize. */
3212                 udelay(150);
3213         }
3214
3215         if (is_lvds && has_reduced_clock && i915_powersave) {
3216                 I915_WRITE(fp_reg + 4, fp2);
3217                 intel_crtc->lowfreq_avail = true;
3218                 if (HAS_PIPE_CXSR(dev)) {
3219                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3220                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3221                 }
3222         } else {
3223                 I915_WRITE(fp_reg + 4, fp);
3224                 intel_crtc->lowfreq_avail = false;
3225                 if (HAS_PIPE_CXSR(dev)) {
3226                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3227                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3228                 }
3229         }
3230
3231         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
3232                    ((adjusted_mode->crtc_htotal - 1) << 16));
3233         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
3234                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
3235         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
3236                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
3237         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
3238                    ((adjusted_mode->crtc_vtotal - 1) << 16));
3239         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
3240                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
3241         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
3242                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
3243         /* pipesrc and dspsize control the size that is scaled from, which should
3244          * always be the user's requested size.
3245          */
3246         if (!IS_IGDNG(dev)) {
3247                 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
3248                                 (mode->hdisplay - 1));
3249                 I915_WRITE(dsppos_reg, 0);
3250         }
3251         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3252
3253         if (IS_IGDNG(dev)) {
3254                 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
3255                 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
3256                 I915_WRITE(link_m1_reg, m_n.link_m);
3257                 I915_WRITE(link_n1_reg, m_n.link_n);
3258
3259                 if (is_edp) {
3260                         igdng_set_pll_edp(crtc, adjusted_mode->clock);
3261                 } else {
3262                         /* enable FDI RX PLL too */
3263                         temp = I915_READ(fdi_rx_reg);
3264                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
3265                         udelay(200);
3266                 }
3267         }
3268
3269         I915_WRITE(pipeconf_reg, pipeconf);
3270         I915_READ(pipeconf_reg);
3271
3272         intel_wait_for_vblank(dev);
3273
3274         if (IS_IGDNG(dev)) {
3275                 /* enable address swizzle for tiling buffer */
3276                 temp = I915_READ(DISP_ARB_CTL);
3277                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
3278         }
3279
3280         I915_WRITE(dspcntr_reg, dspcntr);
3281
3282         /* Flush the plane changes */
3283         ret = intel_pipe_set_base(crtc, x, y, old_fb);
3284
3285         if ((IS_I965G(dev) || plane == 0))
3286                 intel_update_fbc(crtc, &crtc->mode);
3287
3288         intel_update_watermarks(dev);
3289
3290         drm_vblank_post_modeset(dev, pipe);
3291
3292         return ret;
3293 }
3294
3295 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3296 void intel_crtc_load_lut(struct drm_crtc *crtc)
3297 {
3298         struct drm_device *dev = crtc->dev;
3299         struct drm_i915_private *dev_priv = dev->dev_private;
3300         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3301         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
3302         int i;
3303
3304         /* The clocks have to be on to load the palette. */
3305         if (!crtc->enabled)
3306                 return;
3307
3308         /* use legacy palette for IGDNG */
3309         if (IS_IGDNG(dev))
3310                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
3311                                                    LGC_PALETTE_B;
3312
3313         for (i = 0; i < 256; i++) {
3314                 I915_WRITE(palreg + 4 * i,
3315                            (intel_crtc->lut_r[i] << 16) |
3316                            (intel_crtc->lut_g[i] << 8) |
3317                            intel_crtc->lut_b[i]);
3318         }
3319 }
3320
3321 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3322                                  struct drm_file *file_priv,
3323                                  uint32_t handle,
3324                                  uint32_t width, uint32_t height)
3325 {
3326         struct drm_device *dev = crtc->dev;
3327         struct drm_i915_private *dev_priv = dev->dev_private;
3328         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3329         struct drm_gem_object *bo;
3330         struct drm_i915_gem_object *obj_priv;
3331         int pipe = intel_crtc->pipe;
3332         uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
3333         uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
3334         uint32_t temp = I915_READ(control);
3335         size_t addr;
3336         int ret;
3337
3338         DRM_DEBUG_KMS("\n");
3339
3340         /* if we want to turn off the cursor ignore width and height */
3341         if (!handle) {
3342                 DRM_DEBUG_KMS("cursor off\n");
3343                 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3344                         temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
3345                         temp |= CURSOR_MODE_DISABLE;
3346                 } else {
3347                         temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
3348                 }
3349                 addr = 0;
3350                 bo = NULL;
3351                 mutex_lock(&dev->struct_mutex);
3352                 goto finish;
3353         }
3354
3355         /* Currently we only support 64x64 cursors */
3356         if (width != 64 || height != 64) {
3357                 DRM_ERROR("we currently only support 64x64 cursors\n");
3358                 return -EINVAL;
3359         }
3360
3361         bo = drm_gem_object_lookup(dev, file_priv, handle);
3362         if (!bo)
3363                 return -ENOENT;
3364
3365         obj_priv = bo->driver_private;
3366
3367         if (bo->size < width * height * 4) {
3368                 DRM_ERROR("buffer is to small\n");
3369                 ret = -ENOMEM;
3370                 goto fail;
3371         }
3372
3373         /* we only need to pin inside GTT if cursor is non-phy */
3374         mutex_lock(&dev->struct_mutex);
3375         if (!dev_priv->cursor_needs_physical) {
3376                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
3377                 if (ret) {
3378                         DRM_ERROR("failed to pin cursor bo\n");
3379                         goto fail_locked;
3380                 }
3381                 addr = obj_priv->gtt_offset;
3382         } else {
3383                 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
3384                 if (ret) {
3385                         DRM_ERROR("failed to attach phys object\n");
3386                         goto fail_locked;
3387                 }
3388                 addr = obj_priv->phys_obj->handle->busaddr;
3389         }
3390
3391         if (!IS_I9XX(dev))
3392                 I915_WRITE(CURSIZE, (height << 12) | width);
3393
3394         /* Hooray for CUR*CNTR differences */
3395         if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3396                 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
3397                 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
3398                 temp |= (pipe << 28); /* Connect to correct pipe */
3399         } else {
3400                 temp &= ~(CURSOR_FORMAT_MASK);
3401                 temp |= CURSOR_ENABLE;
3402                 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
3403         }
3404
3405  finish:
3406         I915_WRITE(control, temp);
3407         I915_WRITE(base, addr);
3408
3409         if (intel_crtc->cursor_bo) {
3410                 if (dev_priv->cursor_needs_physical) {
3411                         if (intel_crtc->cursor_bo != bo)
3412                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
3413                 } else
3414                         i915_gem_object_unpin(intel_crtc->cursor_bo);
3415                 drm_gem_object_unreference(intel_crtc->cursor_bo);
3416         }
3417
3418         mutex_unlock(&dev->struct_mutex);
3419
3420         intel_crtc->cursor_addr = addr;
3421         intel_crtc->cursor_bo = bo;
3422
3423         return 0;
3424 fail:
3425         mutex_lock(&dev->struct_mutex);
3426 fail_locked:
3427         drm_gem_object_unreference(bo);
3428         mutex_unlock(&dev->struct_mutex);
3429         return ret;
3430 }
3431
3432 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
3433 {
3434         struct drm_device *dev = crtc->dev;
3435         struct drm_i915_private *dev_priv = dev->dev_private;
3436         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3437         struct intel_framebuffer *intel_fb;
3438         int pipe = intel_crtc->pipe;
3439         uint32_t temp = 0;
3440         uint32_t adder;
3441
3442         if (crtc->fb) {
3443                 intel_fb = to_intel_framebuffer(crtc->fb);
3444                 intel_mark_busy(dev, intel_fb->obj);
3445         }
3446
3447         if (x < 0) {
3448                 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
3449                 x = -x;
3450         }
3451         if (y < 0) {
3452                 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
3453                 y = -y;
3454         }
3455
3456         temp |= x << CURSOR_X_SHIFT;
3457         temp |= y << CURSOR_Y_SHIFT;
3458
3459         adder = intel_crtc->cursor_addr;
3460         I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
3461         I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
3462
3463         return 0;
3464 }
3465
3466 /** Sets the color ramps on behalf of RandR */
3467 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
3468                                  u16 blue, int regno)
3469 {
3470         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3471
3472         intel_crtc->lut_r[regno] = red >> 8;
3473         intel_crtc->lut_g[regno] = green >> 8;
3474         intel_crtc->lut_b[regno] = blue >> 8;
3475 }
3476
3477 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
3478                              u16 *blue, int regno)
3479 {
3480         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3481
3482         *red = intel_crtc->lut_r[regno] << 8;
3483         *green = intel_crtc->lut_g[regno] << 8;
3484         *blue = intel_crtc->lut_b[regno] << 8;
3485 }
3486
3487 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
3488                                  u16 *blue, uint32_t size)
3489 {
3490         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3491         int i;
3492
3493         if (size != 256)
3494                 return;
3495
3496         for (i = 0; i < 256; i++) {
3497                 intel_crtc->lut_r[i] = red[i] >> 8;
3498                 intel_crtc->lut_g[i] = green[i] >> 8;
3499                 intel_crtc->lut_b[i] = blue[i] >> 8;
3500         }
3501
3502         intel_crtc_load_lut(crtc);
3503 }
3504
3505 /**
3506  * Get a pipe with a simple mode set on it for doing load-based monitor
3507  * detection.
3508  *
3509  * It will be up to the load-detect code to adjust the pipe as appropriate for
3510  * its requirements.  The pipe will be connected to no other outputs.
3511  *
3512  * Currently this code will only succeed if there is a pipe with no outputs
3513  * configured for it.  In the future, it could choose to temporarily disable
3514  * some outputs to free up a pipe for its use.
3515  *
3516  * \return crtc, or NULL if no pipes are available.
3517  */
3518
3519 /* VESA 640x480x72Hz mode to set on the pipe */
3520 static struct drm_display_mode load_detect_mode = {
3521         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
3522                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
3523 };
3524
3525 struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
3526                                             struct drm_display_mode *mode,
3527                                             int *dpms_mode)
3528 {
3529         struct intel_crtc *intel_crtc;
3530         struct drm_crtc *possible_crtc;
3531         struct drm_crtc *supported_crtc =NULL;
3532         struct drm_encoder *encoder = &intel_output->enc;
3533         struct drm_crtc *crtc = NULL;
3534         struct drm_device *dev = encoder->dev;
3535         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3536         struct drm_crtc_helper_funcs *crtc_funcs;
3537         int i = -1;
3538
3539         /*
3540          * Algorithm gets a little messy:
3541          *   - if the connector already has an assigned crtc, use it (but make
3542          *     sure it's on first)
3543          *   - try to find the first unused crtc that can drive this connector,
3544          *     and use that if we find one
3545          *   - if there are no unused crtcs available, try to use the first
3546          *     one we found that supports the connector
3547          */
3548
3549         /* See if we already have a CRTC for this connector */
3550         if (encoder->crtc) {
3551                 crtc = encoder->crtc;
3552                 /* Make sure the crtc and connector are running */
3553                 intel_crtc = to_intel_crtc(crtc);
3554                 *dpms_mode = intel_crtc->dpms_mode;
3555                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3556                         crtc_funcs = crtc->helper_private;
3557                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3558                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3559                 }
3560                 return crtc;
3561         }
3562
3563         /* Find an unused one (if possible) */
3564         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
3565                 i++;
3566                 if (!(encoder->possible_crtcs & (1 << i)))
3567                         continue;
3568                 if (!possible_crtc->enabled) {
3569                         crtc = possible_crtc;
3570                         break;
3571                 }
3572                 if (!supported_crtc)
3573                         supported_crtc = possible_crtc;
3574         }
3575
3576         /*
3577          * If we didn't find an unused CRTC, don't use any.
3578          */
3579         if (!crtc) {
3580                 return NULL;
3581         }
3582
3583         encoder->crtc = crtc;
3584         intel_output->base.encoder = encoder;
3585         intel_output->load_detect_temp = true;
3586
3587         intel_crtc = to_intel_crtc(crtc);
3588         *dpms_mode = intel_crtc->dpms_mode;
3589
3590         if (!crtc->enabled) {
3591                 if (!mode)
3592                         mode = &load_detect_mode;
3593                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
3594         } else {
3595                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3596                         crtc_funcs = crtc->helper_private;
3597                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3598                 }
3599
3600                 /* Add this connector to the crtc */
3601                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
3602                 encoder_funcs->commit(encoder);
3603         }
3604         /* let the connector get through one full cycle before testing */
3605         intel_wait_for_vblank(dev);
3606
3607         return crtc;
3608 }
3609
3610 void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
3611 {
3612         struct drm_encoder *encoder = &intel_output->enc;
3613         struct drm_device *dev = encoder->dev;
3614         struct drm_crtc *crtc = encoder->crtc;
3615         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3616         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3617
3618         if (intel_output->load_detect_temp) {
3619                 encoder->crtc = NULL;
3620                 intel_output->base.encoder = NULL;
3621                 intel_output->load_detect_temp = false;
3622                 crtc->enabled = drm_helper_crtc_in_use(crtc);
3623                 drm_helper_disable_unused_functions(dev);
3624         }
3625
3626         /* Switch crtc and output back off if necessary */
3627         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
3628                 if (encoder->crtc == crtc)
3629                         encoder_funcs->dpms(encoder, dpms_mode);
3630                 crtc_funcs->dpms(crtc, dpms_mode);
3631         }
3632 }
3633
3634 /* Returns the clock of the currently programmed mode of the given pipe. */
3635 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
3636 {
3637         struct drm_i915_private *dev_priv = dev->dev_private;
3638         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3639         int pipe = intel_crtc->pipe;
3640         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
3641         u32 fp;
3642         intel_clock_t clock;
3643
3644         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
3645                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
3646         else
3647                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
3648
3649         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
3650         if (IS_IGD(dev)) {
3651                 clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
3652                 clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT;
3653         } else {
3654                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
3655                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
3656         }
3657
3658         if (IS_I9XX(dev)) {
3659                 if (IS_IGD(dev))
3660                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>
3661                                 DPLL_FPA01_P1_POST_DIV_SHIFT_IGD);
3662                 else
3663                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
3664                                DPLL_FPA01_P1_POST_DIV_SHIFT);
3665
3666                 switch (dpll & DPLL_MODE_MASK) {
3667                 case DPLLB_MODE_DAC_SERIAL:
3668                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
3669                                 5 : 10;
3670                         break;
3671                 case DPLLB_MODE_LVDS:
3672                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
3673                                 7 : 14;
3674                         break;
3675                 default:
3676                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
3677                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
3678                         return 0;
3679                 }
3680
3681                 /* XXX: Handle the 100Mhz refclk */
3682                 intel_clock(dev, 96000, &clock);
3683         } else {
3684                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
3685
3686                 if (is_lvds) {
3687                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
3688                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
3689                         clock.p2 = 14;
3690
3691                         if ((dpll & PLL_REF_INPUT_MASK) ==
3692                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
3693                                 /* XXX: might not be 66MHz */
3694                                 intel_clock(dev, 66000, &clock);
3695                         } else
3696                                 intel_clock(dev, 48000, &clock);
3697                 } else {
3698                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
3699                                 clock.p1 = 2;
3700                         else {
3701                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
3702                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
3703                         }
3704                         if (dpll & PLL_P2_DIVIDE_BY_4)
3705                                 clock.p2 = 4;
3706                         else
3707                                 clock.p2 = 2;
3708
3709                         intel_clock(dev, 48000, &clock);
3710                 }
3711         }
3712
3713         /* XXX: It would be nice to validate the clocks, but we can't reuse
3714          * i830PllIsValid() because it relies on the xf86_config connector
3715          * configuration being accurate, which it isn't necessarily.
3716          */
3717
3718         return clock.dot;
3719 }
3720
3721 /** Returns the currently programmed mode of the given pipe. */
3722 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
3723                                              struct drm_crtc *crtc)
3724 {
3725         struct drm_i915_private *dev_priv = dev->dev_private;
3726         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3727         int pipe = intel_crtc->pipe;
3728         struct drm_display_mode *mode;
3729         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
3730         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
3731         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
3732         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
3733
3734         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
3735         if (!mode)
3736                 return NULL;
3737
3738         mode->clock = intel_crtc_clock_get(dev, crtc);
3739         mode->hdisplay = (htot & 0xffff) + 1;
3740         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
3741         mode->hsync_start = (hsync & 0xffff) + 1;
3742         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
3743         mode->vdisplay = (vtot & 0xffff) + 1;
3744         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
3745         mode->vsync_start = (vsync & 0xffff) + 1;
3746         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
3747
3748         drm_mode_set_name(mode);
3749         drm_mode_set_crtcinfo(mode, 0);
3750
3751         return mode;
3752 }
3753
3754 #define GPU_IDLE_TIMEOUT 500 /* ms */
3755
3756 /* When this timer fires, we've been idle for awhile */
3757 static void intel_gpu_idle_timer(unsigned long arg)
3758 {
3759         struct drm_device *dev = (struct drm_device *)arg;
3760         drm_i915_private_t *dev_priv = dev->dev_private;
3761
3762         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
3763
3764         dev_priv->busy = false;
3765
3766         queue_work(dev_priv->wq, &dev_priv->idle_work);
3767 }
3768
3769 void intel_increase_renderclock(struct drm_device *dev, bool schedule)
3770 {
3771         drm_i915_private_t *dev_priv = dev->dev_private;
3772
3773         if (IS_IGDNG(dev))
3774                 return;
3775
3776         if (!dev_priv->render_reclock_avail) {
3777                 DRM_DEBUG_DRIVER("not reclocking render clock\n");
3778                 return;
3779         }
3780
3781         /* Restore render clock frequency to original value */
3782         if (IS_G4X(dev) || IS_I9XX(dev))
3783                 pci_write_config_word(dev->pdev, GCFGC, dev_priv->orig_clock);
3784         else if (IS_I85X(dev))
3785                 pci_write_config_word(dev->pdev, HPLLCC, dev_priv->orig_clock);
3786         DRM_DEBUG_DRIVER("increasing render clock frequency\n");
3787
3788         /* Schedule downclock */
3789         if (schedule)
3790                 mod_timer(&dev_priv->idle_timer, jiffies +
3791                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
3792 }
3793
3794 void intel_decrease_renderclock(struct drm_device *dev)
3795 {
3796         drm_i915_private_t *dev_priv = dev->dev_private;
3797
3798         if (IS_IGDNG(dev))
3799                 return;
3800
3801         if (!dev_priv->render_reclock_avail) {
3802                 DRM_DEBUG_DRIVER("not reclocking render clock\n");
3803                 return;
3804         }
3805
3806         if (IS_G4X(dev)) {
3807                 u16 gcfgc;
3808
3809                 /* Adjust render clock... */
3810                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3811
3812                 /* Down to minimum... */
3813                 gcfgc &= ~GM45_GC_RENDER_CLOCK_MASK;
3814                 gcfgc |= GM45_GC_RENDER_CLOCK_266_MHZ;
3815
3816                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3817         } else if (IS_I965G(dev)) {
3818                 u16 gcfgc;
3819
3820                 /* Adjust render clock... */
3821                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3822
3823                 /* Down to minimum... */
3824                 gcfgc &= ~I965_GC_RENDER_CLOCK_MASK;
3825                 gcfgc |= I965_GC_RENDER_CLOCK_267_MHZ;
3826
3827                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3828         } else if (IS_I945G(dev) || IS_I945GM(dev)) {
3829                 u16 gcfgc;
3830
3831                 /* Adjust render clock... */
3832                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3833
3834                 /* Down to minimum... */
3835                 gcfgc &= ~I945_GC_RENDER_CLOCK_MASK;
3836                 gcfgc |= I945_GC_RENDER_CLOCK_166_MHZ;
3837
3838                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3839         } else if (IS_I915G(dev)) {
3840                 u16 gcfgc;
3841
3842                 /* Adjust render clock... */
3843                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3844
3845                 /* Down to minimum... */
3846                 gcfgc &= ~I915_GC_RENDER_CLOCK_MASK;
3847                 gcfgc |= I915_GC_RENDER_CLOCK_166_MHZ;
3848
3849                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3850         } else if (IS_I85X(dev)) {
3851                 u16 hpllcc;
3852
3853                 /* Adjust render clock... */
3854                 pci_read_config_word(dev->pdev, HPLLCC, &hpllcc);
3855
3856                 /* Up to maximum... */
3857                 hpllcc &= ~GC_CLOCK_CONTROL_MASK;
3858                 hpllcc |= GC_CLOCK_133_200;
3859
3860                 pci_write_config_word(dev->pdev, HPLLCC, hpllcc);
3861         }
3862         DRM_DEBUG_DRIVER("decreasing render clock frequency\n");
3863 }
3864
3865 /* Note that no increase function is needed for this - increase_renderclock()
3866  *  will also rewrite these bits
3867  */
3868 void intel_decrease_displayclock(struct drm_device *dev)
3869 {
3870         if (IS_IGDNG(dev))
3871                 return;
3872
3873         if (IS_I945G(dev) || IS_I945GM(dev) || IS_I915G(dev) ||
3874             IS_I915GM(dev)) {
3875                 u16 gcfgc;
3876
3877                 /* Adjust render clock... */
3878                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3879
3880                 /* Down to minimum... */
3881                 gcfgc &= ~0xf0;
3882                 gcfgc |= 0x80;
3883
3884                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3885         }
3886 }
3887
3888 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
3889
3890 static void intel_crtc_idle_timer(unsigned long arg)
3891 {
3892         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
3893         struct drm_crtc *crtc = &intel_crtc->base;
3894         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
3895
3896         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
3897
3898         intel_crtc->busy = false;
3899
3900         queue_work(dev_priv->wq, &dev_priv->idle_work);
3901 }
3902
3903 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
3904 {
3905         struct drm_device *dev = crtc->dev;
3906         drm_i915_private_t *dev_priv = dev->dev_private;
3907         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3908         int pipe = intel_crtc->pipe;
3909         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3910         int dpll = I915_READ(dpll_reg);
3911
3912         if (IS_IGDNG(dev))
3913                 return;
3914
3915         if (!dev_priv->lvds_downclock_avail)
3916                 return;
3917
3918         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
3919                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
3920
3921                 /* Unlock panel regs */
3922                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3923
3924                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
3925                 I915_WRITE(dpll_reg, dpll);
3926                 dpll = I915_READ(dpll_reg);
3927                 intel_wait_for_vblank(dev);
3928                 dpll = I915_READ(dpll_reg);
3929                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
3930                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
3931
3932                 /* ...and lock them again */
3933                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3934         }
3935
3936         /* Schedule downclock */
3937         if (schedule)
3938                 mod_timer(&intel_crtc->idle_timer, jiffies +
3939                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3940 }
3941
3942 static void intel_decrease_pllclock(struct drm_crtc *crtc)
3943 {
3944         struct drm_device *dev = crtc->dev;
3945         drm_i915_private_t *dev_priv = dev->dev_private;
3946         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3947         int pipe = intel_crtc->pipe;
3948         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3949         int dpll = I915_READ(dpll_reg);
3950
3951         if (IS_IGDNG(dev))
3952                 return;
3953
3954         if (!dev_priv->lvds_downclock_avail)
3955                 return;
3956
3957         /*
3958          * Since this is called by a timer, we should never get here in
3959          * the manual case.
3960          */
3961         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
3962                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
3963
3964                 /* Unlock panel regs */
3965                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3966
3967                 dpll |= DISPLAY_RATE_SELECT_FPA1;
3968                 I915_WRITE(dpll_reg, dpll);
3969                 dpll = I915_READ(dpll_reg);
3970                 intel_wait_for_vblank(dev);
3971                 dpll = I915_READ(dpll_reg);
3972                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
3973                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
3974
3975                 /* ...and lock them again */
3976                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3977         }
3978
3979 }
3980
3981 /**
3982  * intel_idle_update - adjust clocks for idleness
3983  * @work: work struct
3984  *
3985  * Either the GPU or display (or both) went idle.  Check the busy status
3986  * here and adjust the CRTC and GPU clocks as necessary.
3987  */
3988 static void intel_idle_update(struct work_struct *work)
3989 {
3990         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
3991                                                     idle_work);
3992         struct drm_device *dev = dev_priv->dev;
3993         struct drm_crtc *crtc;
3994         struct intel_crtc *intel_crtc;
3995
3996         if (!i915_powersave)
3997                 return;
3998
3999         mutex_lock(&dev->struct_mutex);
4000
4001         /* GPU isn't processing, downclock it. */
4002         if (!dev_priv->busy) {
4003                 intel_decrease_renderclock(dev);
4004                 intel_decrease_displayclock(dev);
4005         }
4006
4007         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4008                 /* Skip inactive CRTCs */
4009                 if (!crtc->fb)
4010                         continue;
4011
4012                 intel_crtc = to_intel_crtc(crtc);
4013                 if (!intel_crtc->busy)
4014                         intel_decrease_pllclock(crtc);
4015         }
4016
4017         mutex_unlock(&dev->struct_mutex);
4018 }
4019
4020 /**
4021  * intel_mark_busy - mark the GPU and possibly the display busy
4022  * @dev: drm device
4023  * @obj: object we're operating on
4024  *
4025  * Callers can use this function to indicate that the GPU is busy processing
4026  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
4027  * buffer), we'll also mark the display as busy, so we know to increase its
4028  * clock frequency.
4029  */
4030 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4031 {
4032         drm_i915_private_t *dev_priv = dev->dev_private;
4033         struct drm_crtc *crtc = NULL;
4034         struct intel_framebuffer *intel_fb;
4035         struct intel_crtc *intel_crtc;
4036
4037         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4038                 return;
4039
4040         dev_priv->busy = true;
4041         intel_increase_renderclock(dev, true);
4042
4043         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4044                 if (!crtc->fb)
4045                         continue;
4046
4047                 intel_crtc = to_intel_crtc(crtc);
4048                 intel_fb = to_intel_framebuffer(crtc->fb);
4049                 if (intel_fb->obj == obj) {
4050                         if (!intel_crtc->busy) {
4051                                 /* Non-busy -> busy, upclock */
4052                                 intel_increase_pllclock(crtc, true);
4053                                 intel_crtc->busy = true;
4054                         } else {
4055                                 /* Busy -> busy, put off timer */
4056                                 mod_timer(&intel_crtc->idle_timer, jiffies +
4057                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4058                         }
4059                 }
4060         }
4061 }
4062
4063 static void intel_crtc_destroy(struct drm_crtc *crtc)
4064 {
4065         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4066
4067         drm_crtc_cleanup(crtc);
4068         kfree(intel_crtc);
4069 }
4070
4071 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
4072         .dpms = intel_crtc_dpms,
4073         .mode_fixup = intel_crtc_mode_fixup,
4074         .mode_set = intel_crtc_mode_set,
4075         .mode_set_base = intel_pipe_set_base,
4076         .prepare = intel_crtc_prepare,
4077         .commit = intel_crtc_commit,
4078         .load_lut = intel_crtc_load_lut,
4079 };
4080
4081 static const struct drm_crtc_funcs intel_crtc_funcs = {
4082         .cursor_set = intel_crtc_cursor_set,
4083         .cursor_move = intel_crtc_cursor_move,
4084         .gamma_set = intel_crtc_gamma_set,
4085         .set_config = drm_crtc_helper_set_config,
4086         .destroy = intel_crtc_destroy,
4087 };
4088
4089
4090 static void intel_crtc_init(struct drm_device *dev, int pipe)
4091 {
4092         struct intel_crtc *intel_crtc;
4093         int i;
4094
4095         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
4096         if (intel_crtc == NULL)
4097                 return;
4098
4099         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
4100
4101         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
4102         intel_crtc->pipe = pipe;
4103         intel_crtc->plane = pipe;
4104         for (i = 0; i < 256; i++) {
4105                 intel_crtc->lut_r[i] = i;
4106                 intel_crtc->lut_g[i] = i;
4107                 intel_crtc->lut_b[i] = i;
4108         }
4109
4110         /* Swap pipes & planes for FBC on pre-965 */
4111         intel_crtc->pipe = pipe;
4112         intel_crtc->plane = pipe;
4113         if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
4114                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
4115                 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
4116         }
4117
4118         intel_crtc->cursor_addr = 0;
4119         intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4120         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
4121
4122         intel_crtc->busy = false;
4123
4124         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
4125                     (unsigned long)intel_crtc);
4126 }
4127
4128 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
4129                                 struct drm_file *file_priv)
4130 {
4131         drm_i915_private_t *dev_priv = dev->dev_private;
4132         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
4133         struct drm_mode_object *drmmode_obj;
4134         struct intel_crtc *crtc;
4135
4136         if (!dev_priv) {
4137                 DRM_ERROR("called with no initialization\n");
4138                 return -EINVAL;
4139         }
4140
4141         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
4142                         DRM_MODE_OBJECT_CRTC);
4143
4144         if (!drmmode_obj) {
4145                 DRM_ERROR("no such CRTC id\n");
4146                 return -EINVAL;
4147         }
4148
4149         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
4150         pipe_from_crtc_id->pipe = crtc->pipe;
4151
4152         return 0;
4153 }
4154
4155 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
4156 {
4157         struct drm_crtc *crtc = NULL;
4158
4159         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4160                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4161                 if (intel_crtc->pipe == pipe)
4162                         break;
4163         }
4164         return crtc;
4165 }
4166
4167 static int intel_connector_clones(struct drm_device *dev, int type_mask)
4168 {
4169         int index_mask = 0;
4170         struct drm_connector *connector;
4171         int entry = 0;
4172
4173         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4174                 struct intel_output *intel_output = to_intel_output(connector);
4175                 if (type_mask & intel_output->clone_mask)
4176                         index_mask |= (1 << entry);
4177                 entry++;
4178         }
4179         return index_mask;
4180 }
4181
4182
4183 static void intel_setup_outputs(struct drm_device *dev)
4184 {
4185         struct drm_i915_private *dev_priv = dev->dev_private;
4186         struct drm_connector *connector;
4187
4188         intel_crt_init(dev);
4189
4190         /* Set up integrated LVDS */
4191         if (IS_MOBILE(dev) && !IS_I830(dev))
4192                 intel_lvds_init(dev);
4193
4194         if (IS_IGDNG(dev)) {
4195                 int found;
4196
4197                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
4198                         intel_dp_init(dev, DP_A);
4199
4200                 if (I915_READ(HDMIB) & PORT_DETECTED) {
4201                         /* check SDVOB */
4202                         /* found = intel_sdvo_init(dev, HDMIB); */
4203                         found = 0;
4204                         if (!found)
4205                                 intel_hdmi_init(dev, HDMIB);
4206                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
4207                                 intel_dp_init(dev, PCH_DP_B);
4208                 }
4209
4210                 if (I915_READ(HDMIC) & PORT_DETECTED)
4211                         intel_hdmi_init(dev, HDMIC);
4212
4213                 if (I915_READ(HDMID) & PORT_DETECTED)
4214                         intel_hdmi_init(dev, HDMID);
4215
4216                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
4217                         intel_dp_init(dev, PCH_DP_C);
4218
4219                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
4220                         intel_dp_init(dev, PCH_DP_D);
4221
4222         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
4223                 bool found = false;
4224
4225                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4226                         found = intel_sdvo_init(dev, SDVOB);
4227                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
4228                                 intel_hdmi_init(dev, SDVOB);
4229
4230                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
4231                                 intel_dp_init(dev, DP_B);
4232                 }
4233
4234                 /* Before G4X SDVOC doesn't have its own detect register */
4235
4236                 if (I915_READ(SDVOB) & SDVO_DETECTED)
4237                         found = intel_sdvo_init(dev, SDVOC);
4238
4239                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
4240
4241                         if (SUPPORTS_INTEGRATED_HDMI(dev))
4242                                 intel_hdmi_init(dev, SDVOC);
4243                         if (SUPPORTS_INTEGRATED_DP(dev))
4244                                 intel_dp_init(dev, DP_C);
4245                 }
4246
4247                 if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED))
4248                         intel_dp_init(dev, DP_D);
4249         } else if (IS_I8XX(dev))
4250                 intel_dvo_init(dev);
4251
4252         if (SUPPORTS_TV(dev))
4253                 intel_tv_init(dev);
4254
4255         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4256                 struct intel_output *intel_output = to_intel_output(connector);
4257                 struct drm_encoder *encoder = &intel_output->enc;
4258
4259                 encoder->possible_crtcs = intel_output->crtc_mask;
4260                 encoder->possible_clones = intel_connector_clones(dev,
4261                                                 intel_output->clone_mask);
4262         }
4263 }
4264
4265 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
4266 {
4267         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4268         struct drm_device *dev = fb->dev;
4269
4270         if (fb->fbdev)
4271                 intelfb_remove(dev, fb);
4272
4273         drm_framebuffer_cleanup(fb);
4274         mutex_lock(&dev->struct_mutex);
4275         drm_gem_object_unreference(intel_fb->obj);
4276         mutex_unlock(&dev->struct_mutex);
4277
4278         kfree(intel_fb);
4279 }
4280
4281 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
4282                                                 struct drm_file *file_priv,
4283                                                 unsigned int *handle)
4284 {
4285         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4286         struct drm_gem_object *object = intel_fb->obj;
4287
4288         return drm_gem_handle_create(file_priv, object, handle);
4289 }
4290
4291 static const struct drm_framebuffer_funcs intel_fb_funcs = {
4292         .destroy = intel_user_framebuffer_destroy,
4293         .create_handle = intel_user_framebuffer_create_handle,
4294 };
4295
4296 int intel_framebuffer_create(struct drm_device *dev,
4297                              struct drm_mode_fb_cmd *mode_cmd,
4298                              struct drm_framebuffer **fb,
4299                              struct drm_gem_object *obj)
4300 {
4301         struct intel_framebuffer *intel_fb;
4302         int ret;
4303
4304         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
4305         if (!intel_fb)
4306                 return -ENOMEM;
4307
4308         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
4309         if (ret) {
4310                 DRM_ERROR("framebuffer init failed %d\n", ret);
4311                 return ret;
4312         }
4313
4314         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
4315
4316         intel_fb->obj = obj;
4317
4318         *fb = &intel_fb->base;
4319
4320         return 0;
4321 }
4322
4323
4324 static struct drm_framebuffer *
4325 intel_user_framebuffer_create(struct drm_device *dev,
4326                               struct drm_file *filp,
4327                               struct drm_mode_fb_cmd *mode_cmd)
4328 {
4329         struct drm_gem_object *obj;
4330         struct drm_framebuffer *fb;
4331         int ret;
4332
4333         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
4334         if (!obj)
4335                 return NULL;
4336
4337         ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
4338         if (ret) {
4339                 mutex_lock(&dev->struct_mutex);
4340                 drm_gem_object_unreference(obj);
4341                 mutex_unlock(&dev->struct_mutex);
4342                 return NULL;
4343         }
4344
4345         return fb;
4346 }
4347
4348 static const struct drm_mode_config_funcs intel_mode_funcs = {
4349         .fb_create = intel_user_framebuffer_create,
4350         .fb_changed = intelfb_probe,
4351 };
4352
4353 void intel_init_clock_gating(struct drm_device *dev)
4354 {
4355         struct drm_i915_private *dev_priv = dev->dev_private;
4356
4357         /*
4358          * Disable clock gating reported to work incorrectly according to the
4359          * specs, but enable as much else as we can.
4360          */
4361         if (IS_IGDNG(dev)) {
4362                 return;
4363         } else if (IS_G4X(dev)) {
4364                 uint32_t dspclk_gate;
4365                 I915_WRITE(RENCLK_GATE_D1, 0);
4366                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4367                        GS_UNIT_CLOCK_GATE_DISABLE |
4368                        CL_UNIT_CLOCK_GATE_DISABLE);
4369                 I915_WRITE(RAMCLK_GATE_D, 0);
4370                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4371                         OVRUNIT_CLOCK_GATE_DISABLE |
4372                         OVCUNIT_CLOCK_GATE_DISABLE;
4373                 if (IS_GM45(dev))
4374                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4375                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4376         } else if (IS_I965GM(dev)) {
4377                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4378                 I915_WRITE(RENCLK_GATE_D2, 0);
4379                 I915_WRITE(DSPCLK_GATE_D, 0);
4380                 I915_WRITE(RAMCLK_GATE_D, 0);
4381                 I915_WRITE16(DEUC, 0);
4382         } else if (IS_I965G(dev)) {
4383                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4384                        I965_RCC_CLOCK_GATE_DISABLE |
4385                        I965_RCPB_CLOCK_GATE_DISABLE |
4386                        I965_ISC_CLOCK_GATE_DISABLE |
4387                        I965_FBC_CLOCK_GATE_DISABLE);
4388                 I915_WRITE(RENCLK_GATE_D2, 0);
4389         } else if (IS_I9XX(dev)) {
4390                 u32 dstate = I915_READ(D_STATE);
4391
4392                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4393                         DSTATE_DOT_CLOCK_GATING;
4394                 I915_WRITE(D_STATE, dstate);
4395         } else if (IS_I85X(dev) || IS_I865G(dev)) {
4396                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4397         } else if (IS_I830(dev)) {
4398                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4399         }
4400
4401         /*
4402          * GPU can automatically power down the render unit if given a page
4403          * to save state.
4404          */
4405         if (I915_HAS_RC6(dev)) {
4406                 struct drm_gem_object *pwrctx;
4407                 struct drm_i915_gem_object *obj_priv;
4408                 int ret;
4409
4410                 pwrctx = drm_gem_object_alloc(dev, 4096);
4411                 if (!pwrctx) {
4412                         DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
4413                         goto out;
4414                 }
4415
4416                 ret = i915_gem_object_pin(pwrctx, 4096);
4417                 if (ret) {
4418                         DRM_ERROR("failed to pin power context: %d\n", ret);
4419                         drm_gem_object_unreference(pwrctx);
4420                         goto out;
4421                 }
4422
4423                 i915_gem_object_set_to_gtt_domain(pwrctx, 1);
4424
4425                 obj_priv = pwrctx->driver_private;
4426
4427                 I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
4428                 I915_WRITE(MCHBAR_RENDER_STANDBY,
4429                            I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
4430
4431                 dev_priv->pwrctx = pwrctx;
4432         }
4433
4434 out:
4435         return;
4436 }
4437
4438 /* Set up chip specific display functions */
4439 static void intel_init_display(struct drm_device *dev)
4440 {
4441         struct drm_i915_private *dev_priv = dev->dev_private;
4442
4443         /* We always want a DPMS function */
4444         if (IS_IGDNG(dev))
4445                 dev_priv->display.dpms = igdng_crtc_dpms;
4446         else
4447                 dev_priv->display.dpms = i9xx_crtc_dpms;
4448
4449         /* Only mobile has FBC, leave pointers NULL for other chips */
4450         if (IS_MOBILE(dev)) {
4451                 if (IS_GM45(dev)) {
4452                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4453                         dev_priv->display.enable_fbc = g4x_enable_fbc;
4454                         dev_priv->display.disable_fbc = g4x_disable_fbc;
4455                 } else if (IS_I965GM(dev) || IS_I945GM(dev) || IS_I915GM(dev)) {
4456                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4457                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
4458                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
4459                 }
4460                 /* 855GM needs testing */
4461         }
4462
4463         /* Returns the core display clock speed */
4464         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_IGDGM(dev)))
4465                 dev_priv->display.get_display_clock_speed =
4466                         i945_get_display_clock_speed;
4467         else if (IS_I915G(dev))
4468                 dev_priv->display.get_display_clock_speed =
4469                         i915_get_display_clock_speed;
4470         else if (IS_I945GM(dev) || IS_845G(dev) || IS_IGDGM(dev))
4471                 dev_priv->display.get_display_clock_speed =
4472                         i9xx_misc_get_display_clock_speed;
4473         else if (IS_I915GM(dev))
4474                 dev_priv->display.get_display_clock_speed =
4475                         i915gm_get_display_clock_speed;
4476         else if (IS_I865G(dev))
4477                 dev_priv->display.get_display_clock_speed =
4478                         i865_get_display_clock_speed;
4479         else if (IS_I85X(dev))
4480                 dev_priv->display.get_display_clock_speed =
4481                         i855_get_display_clock_speed;
4482         else /* 852, 830 */
4483                 dev_priv->display.get_display_clock_speed =
4484                         i830_get_display_clock_speed;
4485
4486         /* For FIFO watermark updates */
4487         if (IS_IGDNG(dev))
4488                 dev_priv->display.update_wm = NULL;
4489         else if (IS_G4X(dev))
4490                 dev_priv->display.update_wm = g4x_update_wm;
4491         else if (IS_I965G(dev))
4492                 dev_priv->display.update_wm = i965_update_wm;
4493         else if (IS_I9XX(dev) || IS_MOBILE(dev)) {
4494                 dev_priv->display.update_wm = i9xx_update_wm;
4495                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4496         } else {
4497                 if (IS_I85X(dev))
4498                         dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4499                 else if (IS_845G(dev))
4500                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
4501                 else
4502                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
4503                 dev_priv->display.update_wm = i830_update_wm;
4504         }
4505 }
4506
4507 void intel_modeset_init(struct drm_device *dev)
4508 {
4509         struct drm_i915_private *dev_priv = dev->dev_private;
4510         int num_pipe;
4511         int i;
4512
4513         drm_mode_config_init(dev);
4514
4515         dev->mode_config.min_width = 0;
4516         dev->mode_config.min_height = 0;
4517
4518         dev->mode_config.funcs = (void *)&intel_mode_funcs;
4519
4520         intel_init_display(dev);
4521
4522         if (IS_I965G(dev)) {
4523                 dev->mode_config.max_width = 8192;
4524                 dev->mode_config.max_height = 8192;
4525         } else if (IS_I9XX(dev)) {
4526                 dev->mode_config.max_width = 4096;
4527                 dev->mode_config.max_height = 4096;
4528         } else {
4529                 dev->mode_config.max_width = 2048;
4530                 dev->mode_config.max_height = 2048;
4531         }
4532
4533         /* set memory base */
4534         if (IS_I9XX(dev))
4535                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
4536         else
4537                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
4538
4539         if (IS_MOBILE(dev) || IS_I9XX(dev))
4540                 num_pipe = 2;
4541         else
4542                 num_pipe = 1;
4543         DRM_DEBUG_KMS("%d display pipe%s available.\n",
4544                   num_pipe, num_pipe > 1 ? "s" : "");
4545
4546         if (IS_I85X(dev))
4547                 pci_read_config_word(dev->pdev, HPLLCC, &dev_priv->orig_clock);
4548         else if (IS_I9XX(dev) || IS_G4X(dev))
4549                 pci_read_config_word(dev->pdev, GCFGC, &dev_priv->orig_clock);
4550
4551         for (i = 0; i < num_pipe; i++) {
4552                 intel_crtc_init(dev, i);
4553         }
4554
4555         intel_setup_outputs(dev);
4556
4557         intel_init_clock_gating(dev);
4558
4559         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
4560         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
4561                     (unsigned long)dev);
4562
4563         intel_setup_overlay(dev);
4564 }
4565
4566 void intel_modeset_cleanup(struct drm_device *dev)
4567 {
4568         struct drm_i915_private *dev_priv = dev->dev_private;
4569         struct drm_crtc *crtc;
4570         struct intel_crtc *intel_crtc;
4571
4572         mutex_lock(&dev->struct_mutex);
4573
4574         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4575                 /* Skip inactive CRTCs */
4576                 if (!crtc->fb)
4577                         continue;
4578
4579                 intel_crtc = to_intel_crtc(crtc);
4580                 intel_increase_pllclock(crtc, false);
4581                 del_timer_sync(&intel_crtc->idle_timer);
4582         }
4583
4584         intel_increase_renderclock(dev, false);
4585         del_timer_sync(&dev_priv->idle_timer);
4586
4587         if (dev_priv->display.disable_fbc)
4588                 dev_priv->display.disable_fbc(dev);
4589
4590         if (dev_priv->pwrctx) {
4591                 struct drm_i915_gem_object *obj_priv;
4592
4593                 obj_priv = dev_priv->pwrctx->driver_private;
4594                 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
4595                 I915_READ(PWRCTXA);
4596                 i915_gem_object_unpin(dev_priv->pwrctx);
4597                 drm_gem_object_unreference(dev_priv->pwrctx);
4598         }
4599
4600         mutex_unlock(&dev->struct_mutex);
4601
4602         drm_mode_config_cleanup(dev);
4603 }
4604
4605
4606 /* current intel driver doesn't take advantage of encoders
4607    always give back the encoder for the connector
4608 */
4609 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
4610 {
4611         struct intel_output *intel_output = to_intel_output(connector);
4612
4613         return &intel_output->enc;
4614 }
4615
4616 /*
4617  * set vga decode state - true == enable VGA decode
4618  */
4619 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
4620 {
4621         struct drm_i915_private *dev_priv = dev->dev_private;
4622         u16 gmch_ctrl;
4623
4624         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
4625         if (state)
4626                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
4627         else
4628                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
4629         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
4630         return 0;
4631 }