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   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include "drmP.h"
  32 #include "intel_drv.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "intel_dp.h"
  36
  37 #include "drm_crtc_helper.h"
  38
  39 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  40
  41 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  42 static void intel_update_watermarks(struct drm_device *dev);
  43 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
  44
  45 typedef struct {
  46     /* given values */
  47     int n;
  48     int m1, m2;
  49     int p1, p2;
  50     /* derived values */
  51     int dot;
  52     int vco;
  53     int m;
  54     int p;
  55 } intel_clock_t;
  56
  57 typedef struct {
  58     int min, max;
  59 } intel_range_t;
  60
  61 typedef struct {
  62     int dot_limit;
  63     int p2_slow, p2_fast;
  64 } intel_p2_t;
  65
  66 #define INTEL_P2_NUM                  2
  67 typedef struct intel_limit intel_limit_t;
  68 struct intel_limit {
  69     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  70     intel_p2_t      p2;
  71     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  72                       int, int, intel_clock_t *);
  73     bool (* find_reduced_pll)(const intel_limit_t *, struct drm_crtc *,
  74                               int, int, intel_clock_t *);
  75 };
  76
  77 #define I8XX_DOT_MIN              25000
  78 #define I8XX_DOT_MAX             350000
  79 #define I8XX_VCO_MIN             930000
  80 #define I8XX_VCO_MAX            1400000
  81 #define I8XX_N_MIN                    3
  82 #define I8XX_N_MAX                   16
  83 #define I8XX_M_MIN                   96
  84 #define I8XX_M_MAX                  140
  85 #define I8XX_M1_MIN                  18
  86 #define I8XX_M1_MAX                  26
  87 #define I8XX_M2_MIN                   6
  88 #define I8XX_M2_MAX                  16
  89 #define I8XX_P_MIN                    4
  90 #define I8XX_P_MAX                  128
  91 #define I8XX_P1_MIN                   2
  92 #define I8XX_P1_MAX                  33
  93 #define I8XX_P1_LVDS_MIN              1
  94 #define I8XX_P1_LVDS_MAX              6
  95 #define I8XX_P2_SLOW                  4
  96 #define I8XX_P2_FAST                  2
  97 #define I8XX_P2_LVDS_SLOW             14
  98 #define I8XX_P2_LVDS_FAST             7
  99 #define I8XX_P2_SLOW_LIMIT       165000
 100
 101 #define I9XX_DOT_MIN              20000
 102 #define I9XX_DOT_MAX             400000
 103 #define I9XX_VCO_MIN            1400000
 104 #define I9XX_VCO_MAX            2800000
 105 #define IGD_VCO_MIN             1700000
 106 #define IGD_VCO_MAX             3500000
 107 #define I9XX_N_MIN                    1
 108 #define I9XX_N_MAX                    6
 109 /* IGD's Ncounter is a ring counter */
 110 #define IGD_N_MIN                     3
 111 #define IGD_N_MAX                     6
 112 #define I9XX_M_MIN                   70
 113 #define I9XX_M_MAX                  120
 114 #define IGD_M_MIN                     2
 115 #define IGD_M_MAX                   256
 116 #define I9XX_M1_MIN                  10
 117 #define I9XX_M1_MAX                  22
 118 #define I9XX_M2_MIN                   5
 119 #define I9XX_M2_MAX                   9
 120 /* IGD M1 is reserved, and must be 0 */
 121 #define IGD_M1_MIN                    0
 122 #define IGD_M1_MAX                    0
 123 #define IGD_M2_MIN                    0
 124 #define IGD_M2_MAX                    254
 125 #define I9XX_P_SDVO_DAC_MIN           5
 126 #define I9XX_P_SDVO_DAC_MAX          80
 127 #define I9XX_P_LVDS_MIN               7
 128 #define I9XX_P_LVDS_MAX              98
 129 #define IGD_P_LVDS_MIN                7
 130 #define IGD_P_LVDS_MAX               112
 131 #define I9XX_P1_MIN                   1
 132 #define I9XX_P1_MAX                   8
 133 #define I9XX_P2_SDVO_DAC_SLOW                10
 134 #define I9XX_P2_SDVO_DAC_FAST                 5
 135 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 136 #define I9XX_P2_LVDS_SLOW                    14
 137 #define I9XX_P2_LVDS_FAST                     7
 138 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 139
 140 /*The parameter is for SDVO on G4x platform*/
 141 #define G4X_DOT_SDVO_MIN           25000
 142 #define G4X_DOT_SDVO_MAX           270000
 143 #define G4X_VCO_MIN                1750000
 144 #define G4X_VCO_MAX                3500000
 145 #define G4X_N_SDVO_MIN             1
 146 #define G4X_N_SDVO_MAX             4
 147 #define G4X_M_SDVO_MIN             104
 148 #define G4X_M_SDVO_MAX             138
 149 #define G4X_M1_SDVO_MIN            17
 150 #define G4X_M1_SDVO_MAX            23
 151 #define G4X_M2_SDVO_MIN            5
 152 #define G4X_M2_SDVO_MAX            11
 153 #define G4X_P_SDVO_MIN             10
 154 #define G4X_P_SDVO_MAX             30
 155 #define G4X_P1_SDVO_MIN            1
 156 #define G4X_P1_SDVO_MAX            3
 157 #define G4X_P2_SDVO_SLOW           10
 158 #define G4X_P2_SDVO_FAST           10
 159 #define G4X_P2_SDVO_LIMIT          270000
 160
 161 /*The parameter is for HDMI_DAC on G4x platform*/
 162 #define G4X_DOT_HDMI_DAC_MIN           22000
 163 #define G4X_DOT_HDMI_DAC_MAX           400000
 164 #define G4X_N_HDMI_DAC_MIN             1
 165 #define G4X_N_HDMI_DAC_MAX             4
 166 #define G4X_M_HDMI_DAC_MIN             104
 167 #define G4X_M_HDMI_DAC_MAX             138
 168 #define G4X_M1_HDMI_DAC_MIN            16
 169 #define G4X_M1_HDMI_DAC_MAX            23
 170 #define G4X_M2_HDMI_DAC_MIN            5
 171 #define G4X_M2_HDMI_DAC_MAX            11
 172 #define G4X_P_HDMI_DAC_MIN             5
 173 #define G4X_P_HDMI_DAC_MAX             80
 174 #define G4X_P1_HDMI_DAC_MIN            1
 175 #define G4X_P1_HDMI_DAC_MAX            8
 176 #define G4X_P2_HDMI_DAC_SLOW           10
 177 #define G4X_P2_HDMI_DAC_FAST           5
 178 #define G4X_P2_HDMI_DAC_LIMIT          165000
 179
 180 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 181 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 182 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 183 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 184 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 185 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 186 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 187 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 188 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 189 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 190 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 191 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 192 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 193 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 194 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 195 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 196 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 198
 199 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 200 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 201 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 202 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 203 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 204 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 205 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 206 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 207 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 208 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 209 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 210 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 211 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 212 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 213 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 214 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 215 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 217
 218 /*The parameter is for DISPLAY PORT on G4x platform*/
 219 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 220 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 221 #define G4X_N_DISPLAY_PORT_MIN             1
 222 #define G4X_N_DISPLAY_PORT_MAX             2
 223 #define G4X_M_DISPLAY_PORT_MIN             97
 224 #define G4X_M_DISPLAY_PORT_MAX             108
 225 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 226 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 227 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 228 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 229 #define G4X_P_DISPLAY_PORT_MIN             10
 230 #define G4X_P_DISPLAY_PORT_MAX             20
 231 #define G4X_P1_DISPLAY_PORT_MIN            1
 232 #define G4X_P1_DISPLAY_PORT_MAX            2
 233 #define G4X_P2_DISPLAY_PORT_SLOW           10
 234 #define G4X_P2_DISPLAY_PORT_FAST           10
 235 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 236
 237 /* IGDNG */
 238 /* as we calculate clock using (register_value + 2) for
 239    N/M1/M2, so here the range value for them is (actual_value-2).
 240  */
 241 #define IGDNG_DOT_MIN         25000
 242 #define IGDNG_DOT_MAX         350000
 243 #define IGDNG_VCO_MIN         1760000
 244 #define IGDNG_VCO_MAX         3510000
 245 #define IGDNG_N_MIN           1
 246 #define IGDNG_N_MAX           5
 247 #define IGDNG_M_MIN           79
 248 #define IGDNG_M_MAX           118
 249 #define IGDNG_M1_MIN          12
 250 #define IGDNG_M1_MAX          23
 251 #define IGDNG_M2_MIN          5
 252 #define IGDNG_M2_MAX          9
 253 #define IGDNG_P_SDVO_DAC_MIN  5
 254 #define IGDNG_P_SDVO_DAC_MAX  80
 255 #define IGDNG_P_LVDS_MIN      28
 256 #define IGDNG_P_LVDS_MAX      112
 257 #define IGDNG_P1_MIN          1
 258 #define IGDNG_P1_MAX          8
 259 #define IGDNG_P2_SDVO_DAC_SLOW 10
 260 #define IGDNG_P2_SDVO_DAC_FAST 5
 261 #define IGDNG_P2_LVDS_SLOW    14 /* single channel */
 262 #define IGDNG_P2_LVDS_FAST    7  /* double channel */
 263 #define IGDNG_P2_DOT_LIMIT    225000 /* 225Mhz */
 264
 265 static bool
 266 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 267                     int target, int refclk, intel_clock_t *best_clock);
 268 static bool
 269 intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 270                             int target, int refclk, intel_clock_t *best_clock);
 271 static bool
 272 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 273                         int target, int refclk, intel_clock_t *best_clock);
 274 static bool
 275 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 276                         int target, int refclk, intel_clock_t *best_clock);
 277
 278 static bool
 279 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 280                       int target, int refclk, intel_clock_t *best_clock);
 281 static bool
 282 intel_find_pll_igdng_dp(const intel_limit_t *, struct drm_crtc *crtc,
 283                       int target, int refclk, intel_clock_t *best_clock);
 284
 285 static const intel_limit_t intel_limits_i8xx_dvo = {
 286         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 287         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 288         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 289         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 290         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 291         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 292         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 293         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 294         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 295                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 296         .find_pll = intel_find_best_PLL,
 297         .find_reduced_pll = intel_find_best_reduced_PLL,
 298 };
 299
 300 static const intel_limit_t intel_limits_i8xx_lvds = {
 301         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 302         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 303         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 304         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 305         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 306         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 307         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 308         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 309         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 310                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 311         .find_pll = intel_find_best_PLL,
 312         .find_reduced_pll = intel_find_best_reduced_PLL,
 313 };
 314
 315 static const intel_limit_t intel_limits_i9xx_sdvo = {
 316         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 317         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 318         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 319         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 320         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 321         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 322         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 323         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 324         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 325                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 326         .find_pll = intel_find_best_PLL,
 327         .find_reduced_pll = intel_find_best_reduced_PLL,
 328 };
 329
 330 static const intel_limit_t intel_limits_i9xx_lvds = {
 331         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 332         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 333         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 334         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 335         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 336         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 337         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 338         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 339         /* The single-channel range is 25-112Mhz, and dual-channel
 340          * is 80-224Mhz.  Prefer single channel as much as possible.
 341          */
 342         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 343                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 344         .find_pll = intel_find_best_PLL,
 345         .find_reduced_pll = intel_find_best_reduced_PLL,
 346 };
 347
 348     /* below parameter and function is for G4X Chipset Family*/
 349 static const intel_limit_t intel_limits_g4x_sdvo = {
 350         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 351         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 352         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 353         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 354         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 355         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 356         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 357         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 358         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 359                  .p2_slow = G4X_P2_SDVO_SLOW,
 360                  .p2_fast = G4X_P2_SDVO_FAST
 361         },
 362         .find_pll = intel_g4x_find_best_PLL,
 363         .find_reduced_pll = intel_g4x_find_best_PLL,
 364 };
 365
 366 static const intel_limit_t intel_limits_g4x_hdmi = {
 367         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 368         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 369         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 370         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 371         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 372         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 373         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 374         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 375         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 376                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 377                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 378         },
 379         .find_pll = intel_g4x_find_best_PLL,
 380         .find_reduced_pll = intel_g4x_find_best_PLL,
 381 };
 382
 383 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 384         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 385                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 386         .vco = { .min = G4X_VCO_MIN,
 387                  .max = G4X_VCO_MAX },
 388         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 389                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 390         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 391                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 392         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 393                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 394         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 395                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 396         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 397                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 398         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 399                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 400         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 401                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 402                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 403         },
 404         .find_pll = intel_g4x_find_best_PLL,
 405         .find_reduced_pll = intel_g4x_find_best_PLL,
 406 };
 407
 408 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 409         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 410                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 411         .vco = { .min = G4X_VCO_MIN,
 412                  .max = G4X_VCO_MAX },
 413         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 414                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 415         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 416                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 417         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 418                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 419         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 420                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 421         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 422                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 423         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 424                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 425         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 426                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 427                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 428         },
 429         .find_pll = intel_g4x_find_best_PLL,
 430         .find_reduced_pll = intel_g4x_find_best_PLL,
 431 };
 432
 433 static const intel_limit_t intel_limits_g4x_display_port = {
 434         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 435                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 436         .vco = { .min = G4X_VCO_MIN,
 437                  .max = G4X_VCO_MAX},
 438         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 439                  .max = G4X_N_DISPLAY_PORT_MAX },
 440         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 441                  .max = G4X_M_DISPLAY_PORT_MAX },
 442         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 443                  .max = G4X_M1_DISPLAY_PORT_MAX },
 444         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 445                  .max = G4X_M2_DISPLAY_PORT_MAX },
 446         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 447                  .max = G4X_P_DISPLAY_PORT_MAX },
 448         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 449                  .max = G4X_P1_DISPLAY_PORT_MAX},
 450         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 451                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 452                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 453         .find_pll = intel_find_pll_g4x_dp,
 454 };
 455
 456 static const intel_limit_t intel_limits_igd_sdvo = {
 457         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 458         .vco = { .min = IGD_VCO_MIN,            .max = IGD_VCO_MAX },
 459         .n   = { .min = IGD_N_MIN,              .max = IGD_N_MAX },
 460         .m   = { .min = IGD_M_MIN,              .max = IGD_M_MAX },
 461         .m1  = { .min = IGD_M1_MIN,             .max = IGD_M1_MAX },
 462         .m2  = { .min = IGD_M2_MIN,             .max = IGD_M2_MAX },
 463         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 464         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 465         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 466                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 467         .find_pll = intel_find_best_PLL,
 468         .find_reduced_pll = intel_find_best_reduced_PLL,
 469 };
 470
 471 static const intel_limit_t intel_limits_igd_lvds = {
 472         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 473         .vco = { .min = IGD_VCO_MIN,            .max = IGD_VCO_MAX },
 474         .n   = { .min = IGD_N_MIN,              .max = IGD_N_MAX },
 475         .m   = { .min = IGD_M_MIN,              .max = IGD_M_MAX },
 476         .m1  = { .min = IGD_M1_MIN,             .max = IGD_M1_MAX },
 477         .m2  = { .min = IGD_M2_MIN,             .max = IGD_M2_MAX },
 478         .p   = { .min = IGD_P_LVDS_MIN, .max = IGD_P_LVDS_MAX },
 479         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 480         /* IGD only supports single-channel mode. */
 481         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 482                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 483         .find_pll = intel_find_best_PLL,
 484         .find_reduced_pll = intel_find_best_reduced_PLL,
 485 };
 486
 487 static const intel_limit_t intel_limits_igdng_sdvo = {
 488         .dot = { .min = IGDNG_DOT_MIN,          .max = IGDNG_DOT_MAX },
 489         .vco = { .min = IGDNG_VCO_MIN,          .max = IGDNG_VCO_MAX },
 490         .n   = { .min = IGDNG_N_MIN,            .max = IGDNG_N_MAX },
 491         .m   = { .min = IGDNG_M_MIN,            .max = IGDNG_M_MAX },
 492         .m1  = { .min = IGDNG_M1_MIN,           .max = IGDNG_M1_MAX },
 493         .m2  = { .min = IGDNG_M2_MIN,           .max = IGDNG_M2_MAX },
 494         .p   = { .min = IGDNG_P_SDVO_DAC_MIN,   .max = IGDNG_P_SDVO_DAC_MAX },
 495         .p1  = { .min = IGDNG_P1_MIN,           .max = IGDNG_P1_MAX },
 496         .p2  = { .dot_limit = IGDNG_P2_DOT_LIMIT,
 497                  .p2_slow = IGDNG_P2_SDVO_DAC_SLOW,
 498                  .p2_fast = IGDNG_P2_SDVO_DAC_FAST },
 499         .find_pll = intel_igdng_find_best_PLL,
 500 };
 501
 502 static const intel_limit_t intel_limits_igdng_lvds = {
 503         .dot = { .min = IGDNG_DOT_MIN,          .max = IGDNG_DOT_MAX },
 504         .vco = { .min = IGDNG_VCO_MIN,          .max = IGDNG_VCO_MAX },
 505         .n   = { .min = IGDNG_N_MIN,            .max = IGDNG_N_MAX },
 506         .m   = { .min = IGDNG_M_MIN,            .max = IGDNG_M_MAX },
 507         .m1  = { .min = IGDNG_M1_MIN,           .max = IGDNG_M1_MAX },
 508         .m2  = { .min = IGDNG_M2_MIN,           .max = IGDNG_M2_MAX },
 509         .p   = { .min = IGDNG_P_LVDS_MIN,       .max = IGDNG_P_LVDS_MAX },
 510         .p1  = { .min = IGDNG_P1_MIN,           .max = IGDNG_P1_MAX },
 511         .p2  = { .dot_limit = IGDNG_P2_DOT_LIMIT,
 512                  .p2_slow = IGDNG_P2_LVDS_SLOW,
 513                  .p2_fast = IGDNG_P2_LVDS_FAST },
 514         .find_pll = intel_igdng_find_best_PLL,
 515 };
 516
 517 static const intel_limit_t *intel_igdng_limit(struct drm_crtc *crtc)
 518 {
 519         const intel_limit_t *limit;
 520         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 521                 limit = &intel_limits_igdng_lvds;
 522         else
 523                 limit = &intel_limits_igdng_sdvo;
 524
 525         return limit;
 526 }
 527
 528 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 529 {
 530         struct drm_device *dev = crtc->dev;
 531         struct drm_i915_private *dev_priv = dev->dev_private;
 532         const intel_limit_t *limit;
 533
 534         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 535                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 536                     LVDS_CLKB_POWER_UP)
 537                         /* LVDS with dual channel */
 538                         limit = &intel_limits_g4x_dual_channel_lvds;
 539                 else
 540                         /* LVDS with dual channel */
 541                         limit = &intel_limits_g4x_single_channel_lvds;
 542         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 543                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 544                 limit = &intel_limits_g4x_hdmi;
 545         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 546                 limit = &intel_limits_g4x_sdvo;
 547         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 548                 limit = &intel_limits_g4x_display_port;
 549         } else /* The option is for other outputs */
 550                 limit = &intel_limits_i9xx_sdvo;
 551
 552         return limit;
 553 }
 554
 555 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 556 {
 557         struct drm_device *dev = crtc->dev;
 558         const intel_limit_t *limit;
 559
 560         if (IS_IGDNG(dev))
 561                 limit = intel_igdng_limit(crtc);
 562         else if (IS_G4X(dev)) {
 563                 limit = intel_g4x_limit(crtc);
 564         } else if (IS_I9XX(dev) && !IS_IGD(dev)) {
 565                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 566                         limit = &intel_limits_i9xx_lvds;
 567                 else
 568                         limit = &intel_limits_i9xx_sdvo;
 569         } else if (IS_IGD(dev)) {
 570                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 571                         limit = &intel_limits_igd_lvds;
 572                 else
 573                         limit = &intel_limits_igd_sdvo;
 574         } else {
 575                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 576                         limit = &intel_limits_i8xx_lvds;
 577                 else
 578                         limit = &intel_limits_i8xx_dvo;
 579         }
 580         return limit;
 581 }
 582
 583 /* m1 is reserved as 0 in IGD, n is a ring counter */
 584 static void igd_clock(int refclk, intel_clock_t *clock)
 585 {
 586         clock->m = clock->m2 + 2;
 587         clock->p = clock->p1 * clock->p2;
 588         clock->vco = refclk * clock->m / clock->n;
 589         clock->dot = clock->vco / clock->p;
 590 }
 591
 592 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 593 {
 594         if (IS_IGD(dev)) {
 595                 igd_clock(refclk, clock);
 596                 return;
 597         }
 598         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 599         clock->p = clock->p1 * clock->p2;
 600         clock->vco = refclk * clock->m / (clock->n + 2);
 601         clock->dot = clock->vco / clock->p;
 602 }
 603
 604 /**
 605  * Returns whether any output on the specified pipe is of the specified type
 606  */
 607 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
 608 {
 609     struct drm_device *dev = crtc->dev;
 610     struct drm_mode_config *mode_config = &dev->mode_config;
 611     struct drm_connector *l_entry;
 612
 613     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 614             if (l_entry->encoder &&
 615                 l_entry->encoder->crtc == crtc) {
 616                     struct intel_output *intel_output = to_intel_output(l_entry);
 617                     if (intel_output->type == type)
 618                             return true;
 619             }
 620     }
 621     return false;
 622 }
 623
 624 struct drm_connector *
 625 intel_pipe_get_output (struct drm_crtc *crtc)
 626 {
 627     struct drm_device *dev = crtc->dev;
 628     struct drm_mode_config *mode_config = &dev->mode_config;
 629     struct drm_connector *l_entry, *ret = NULL;
 630
 631     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 632             if (l_entry->encoder &&
 633                 l_entry->encoder->crtc == crtc) {
 634                     ret = l_entry;
 635                     break;
 636             }
 637     }
 638     return ret;
 639 }
 640
 641 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 642 /**
 643  * Returns whether the given set of divisors are valid for a given refclk with
 644  * the given connectors.
 645  */
 646
 647 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 648 {
 649         const intel_limit_t *limit = intel_limit (crtc);
 650         struct drm_device *dev = crtc->dev;
 651
 652         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 653                 INTELPllInvalid ("p1 out of range\n");
 654         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 655                 INTELPllInvalid ("p out of range\n");
 656         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 657                 INTELPllInvalid ("m2 out of range\n");
 658         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 659                 INTELPllInvalid ("m1 out of range\n");
 660         if (clock->m1 <= clock->m2 && !IS_IGD(dev))
 661                 INTELPllInvalid ("m1 <= m2\n");
 662         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 663                 INTELPllInvalid ("m out of range\n");
 664         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 665                 INTELPllInvalid ("n out of range\n");
 666         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 667                 INTELPllInvalid ("vco out of range\n");
 668         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 669          * connector, etc., rather than just a single range.
 670          */
 671         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 672                 INTELPllInvalid ("dot out of range\n");
 673
 674         return true;
 675 }
 676
 677 static bool
 678 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 679                     int target, int refclk, intel_clock_t *best_clock)
 680
 681 {
 682         struct drm_device *dev = crtc->dev;
 683         struct drm_i915_private *dev_priv = dev->dev_private;
 684         intel_clock_t clock;
 685         int err = target;
 686
 687         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 688             (I915_READ(LVDS)) != 0) {
 689                 /*
 690                  * For LVDS, if the panel is on, just rely on its current
 691                  * settings for dual-channel.  We haven't figured out how to
 692                  * reliably set up different single/dual channel state, if we
 693                  * even can.
 694                  */
 695                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 696                     LVDS_CLKB_POWER_UP)
 697                         clock.p2 = limit->p2.p2_fast;
 698                 else
 699                         clock.p2 = limit->p2.p2_slow;
 700         } else {
 701                 if (target < limit->p2.dot_limit)
 702                         clock.p2 = limit->p2.p2_slow;
 703                 else
 704                         clock.p2 = limit->p2.p2_fast;
 705         }
 706
 707         memset (best_clock, 0, sizeof (*best_clock));
 708
 709         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 710                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 711                      clock.m1++) {
 712                         for (clock.m2 = limit->m2.min;
 713                              clock.m2 <= limit->m2.max; clock.m2++) {
 714                                 /* m1 is always 0 in IGD */
 715                                 if (clock.m2 >= clock.m1 && !IS_IGD(dev))
 716                                         break;
 717                                 for (clock.n = limit->n.min;
 718                                      clock.n <= limit->n.max; clock.n++) {
 719                                         int this_err;
 720
 721                                         intel_clock(dev, refclk, &clock);
 722
 723                                         if (!intel_PLL_is_valid(crtc, &clock))
 724                                                 continue;
 725
 726                                         this_err = abs(clock.dot - target);
 727                                         if (this_err < err) {
 728                                                 *best_clock = clock;
 729                                                 err = this_err;
 730                                         }
 731                                 }
 732                         }
 733                 }
 734         }
 735
 736         return (err != target);
 737 }
 738
 739
 740 static bool
 741 intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 742                             int target, int refclk, intel_clock_t *best_clock)
 743
 744 {
 745         struct drm_device *dev = crtc->dev;
 746         intel_clock_t clock;
 747         int err = target;
 748         bool found = false;
 749
 750         memcpy(&clock, best_clock, sizeof(intel_clock_t));
 751
 752         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 753                 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
 754                         /* m1 is always 0 in IGD */
 755                         if (clock.m2 >= clock.m1 && !IS_IGD(dev))
 756                                 break;
 757                         for (clock.n = limit->n.min; clock.n <= limit->n.max;
 758                              clock.n++) {
 759                                 int this_err;
 760
 761                                 intel_clock(dev, refclk, &clock);
 762
 763                                 if (!intel_PLL_is_valid(crtc, &clock))
 764                                         continue;
 765
 766                                 this_err = abs(clock.dot - target);
 767                                 if (this_err < err) {
 768                                         *best_clock = clock;
 769                                         err = this_err;
 770                                         found = true;
 771                                 }
 772                         }
 773                 }
 774         }
 775
 776         return found;
 777 }
 778
 779 static bool
 780 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 781                         int target, int refclk, intel_clock_t *best_clock)
 782 {
 783         struct drm_device *dev = crtc->dev;
 784         struct drm_i915_private *dev_priv = dev->dev_private;
 785         intel_clock_t clock;
 786         int max_n;
 787         bool found;
 788         /* approximately equals target * 0.00488 */
 789         int err_most = (target >> 8) + (target >> 10);
 790         found = false;
 791
 792         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 793                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 794                     LVDS_CLKB_POWER_UP)
 795                         clock.p2 = limit->p2.p2_fast;
 796                 else
 797                         clock.p2 = limit->p2.p2_slow;
 798         } else {
 799                 if (target < limit->p2.dot_limit)
 800                         clock.p2 = limit->p2.p2_slow;
 801                 else
 802                         clock.p2 = limit->p2.p2_fast;
 803         }
 804
 805         memset(best_clock, 0, sizeof(*best_clock));
 806         max_n = limit->n.max;
 807         /* based on hardware requriment prefer smaller n to precision */
 808         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 809                 /* based on hardware requirment prefere larger m1,m2 */
 810                 for (clock.m1 = limit->m1.max;
 811                      clock.m1 >= limit->m1.min; clock.m1--) {
 812                         for (clock.m2 = limit->m2.max;
 813                              clock.m2 >= limit->m2.min; clock.m2--) {
 814                                 for (clock.p1 = limit->p1.max;
 815                                      clock.p1 >= limit->p1.min; clock.p1--) {
 816                                         int this_err;
 817
 818                                         intel_clock(dev, refclk, &clock);
 819                                         if (!intel_PLL_is_valid(crtc, &clock))
 820                                                 continue;
 821                                         this_err = abs(clock.dot - target) ;
 822                                         if (this_err < err_most) {
 823                                                 *best_clock = clock;
 824                                                 err_most = this_err;
 825                                                 max_n = clock.n;
 826                                                 found = true;
 827                                         }
 828                                 }
 829                         }
 830                 }
 831         }
 832         return found;
 833 }
 834
 835 static bool
 836 intel_find_pll_igdng_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 837                       int target, int refclk, intel_clock_t *best_clock)
 838 {
 839         struct drm_device *dev = crtc->dev;
 840         intel_clock_t clock;
 841         if (target < 200000) {
 842                 clock.n = 1;
 843                 clock.p1 = 2;
 844                 clock.p2 = 10;
 845                 clock.m1 = 12;
 846                 clock.m2 = 9;
 847         } else {
 848                 clock.n = 2;
 849                 clock.p1 = 1;
 850                 clock.p2 = 10;
 851                 clock.m1 = 14;
 852                 clock.m2 = 8;
 853         }
 854         intel_clock(dev, refclk, &clock);
 855         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 856         return true;
 857 }
 858
 859 static bool
 860 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 861                         int target, int refclk, intel_clock_t *best_clock)
 862 {
 863         struct drm_device *dev = crtc->dev;
 864         struct drm_i915_private *dev_priv = dev->dev_private;
 865         intel_clock_t clock;
 866         int max_n;
 867         bool found;
 868         int err_most = 47;
 869         found = false;
 870
 871         /* eDP has only 2 clock choice, no n/m/p setting */
 872         if (HAS_eDP)
 873                 return true;
 874
 875         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
 876                 return intel_find_pll_igdng_dp(limit, crtc, target,
 877                                                refclk, best_clock);
 878
 879         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 880                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 881                     LVDS_CLKB_POWER_UP)
 882                         clock.p2 = limit->p2.p2_fast;
 883                 else
 884                         clock.p2 = limit->p2.p2_slow;
 885         } else {
 886                 if (target < limit->p2.dot_limit)
 887                         clock.p2 = limit->p2.p2_slow;
 888                 else
 889                         clock.p2 = limit->p2.p2_fast;
 890         }
 891
 892         memset(best_clock, 0, sizeof(*best_clock));
 893         max_n = limit->n.max;
 894         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 895                 /* based on hardware requriment prefer smaller n to precision */
 896                 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 897                         /* based on hardware requirment prefere larger m1,m2 */
 898                         for (clock.m1 = limit->m1.max;
 899                              clock.m1 >= limit->m1.min; clock.m1--) {
 900                                 for (clock.m2 = limit->m2.max;
 901                                      clock.m2 >= limit->m2.min; clock.m2--) {
 902                                         int this_err;
 903
 904                                         intel_clock(dev, refclk, &clock);
 905                                         if (!intel_PLL_is_valid(crtc, &clock))
 906                                                 continue;
 907                                         this_err = abs((10000 - (target*10000/clock.dot)));
 908                                         if (this_err < err_most) {
 909                                                 *best_clock = clock;
 910                                                 err_most = this_err;
 911                                                 max_n = clock.n;
 912                                                 found = true;
 913                                                 /* found on first matching */
 914                                                 goto out;
 915                                         }
 916                                 }
 917                         }
 918                 }
 919         }
 920 out:
 921         return found;
 922 }
 923
 924 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 925 static bool
 926 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 927                       int target, int refclk, intel_clock_t *best_clock)
 928 {
 929     intel_clock_t clock;
 930     if (target < 200000) {
 931         clock.p1 = 2;
 932         clock.p2 = 10;
 933         clock.n = 2;
 934         clock.m1 = 23;
 935         clock.m2 = 8;
 936     } else {
 937         clock.p1 = 1;
 938         clock.p2 = 10;
 939         clock.n = 1;
 940         clock.m1 = 14;
 941         clock.m2 = 2;
 942     }
 943     clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 944     clock.p = (clock.p1 * clock.p2);
 945     clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 946     memcpy(best_clock, &clock, sizeof(intel_clock_t));
 947     return true;
 948 }
 949
 950 void
 951 intel_wait_for_vblank(struct drm_device *dev)
 952 {
 953         /* Wait for 20ms, i.e. one cycle at 50hz. */
 954         mdelay(20);
 955 }
 956
 957 /* Parameters have changed, update FBC info */
 958 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 959 {
 960         struct drm_device *dev = crtc->dev;
 961         struct drm_i915_private *dev_priv = dev->dev_private;
 962         struct drm_framebuffer *fb = crtc->fb;
 963         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 964         struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
 965         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 966         int plane, i;
 967         u32 fbc_ctl, fbc_ctl2;
 968
 969         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
 970
 971         if (fb->pitch < dev_priv->cfb_pitch)
 972                 dev_priv->cfb_pitch = fb->pitch;
 973
 974         /* FBC_CTL wants 64B units */
 975         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
 976         dev_priv->cfb_fence = obj_priv->fence_reg;
 977         dev_priv->cfb_plane = intel_crtc->plane;
 978         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
 979
 980         /* Clear old tags */
 981         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 982                 I915_WRITE(FBC_TAG + (i * 4), 0);
 983
 984         /* Set it up... */
 985         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
 986         if (obj_priv->tiling_mode != I915_TILING_NONE)
 987                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
 988         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 989         I915_WRITE(FBC_FENCE_OFF, crtc->y);
 990
 991         /* enable it... */
 992         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
 993         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 994         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
 995         if (obj_priv->tiling_mode != I915_TILING_NONE)
 996                 fbc_ctl |= dev_priv->cfb_fence;
 997         I915_WRITE(FBC_CONTROL, fbc_ctl);
 998
 999         DRM_DEBUG("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1000                   dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1001 }
1002
1003 void i8xx_disable_fbc(struct drm_device *dev)
1004 {
1005         struct drm_i915_private *dev_priv = dev->dev_private;
1006         u32 fbc_ctl;
1007
1008         if (!I915_HAS_FBC(dev))
1009                 return;
1010
1011         /* Disable compression */
1012         fbc_ctl = I915_READ(FBC_CONTROL);
1013         fbc_ctl &= ~FBC_CTL_EN;
1014         I915_WRITE(FBC_CONTROL, fbc_ctl);
1015
1016         /* Wait for compressing bit to clear */
1017         while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING)
1018                 ; /* nothing */
1019
1020         intel_wait_for_vblank(dev);
1021
1022         DRM_DEBUG("disabled FBC\n");
1023 }
1024
1025 static bool i8xx_fbc_enabled(struct drm_crtc *crtc)
1026 {
1027         struct drm_device *dev = crtc->dev;
1028         struct drm_i915_private *dev_priv = dev->dev_private;
1029
1030         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1031 }
1032
1033 /**
1034  * intel_update_fbc - enable/disable FBC as needed
1035  * @crtc: CRTC to point the compressor at
1036  * @mode: mode in use
1037  *
1038  * Set up the framebuffer compression hardware at mode set time.  We
1039  * enable it if possible:
1040  *   - plane A only (on pre-965)
1041  *   - no pixel mulitply/line duplication
1042  *   - no alpha buffer discard
1043  *   - no dual wide
1044  *   - framebuffer <= 2048 in width, 1536 in height
1045  *
1046  * We can't assume that any compression will take place (worst case),
1047  * so the compressed buffer has to be the same size as the uncompressed
1048  * one.  It also must reside (along with the line length buffer) in
1049  * stolen memory.
1050  *
1051  * We need to enable/disable FBC on a global basis.
1052  */
1053 static void intel_update_fbc(struct drm_crtc *crtc,
1054                              struct drm_display_mode *mode)
1055 {
1056         struct drm_device *dev = crtc->dev;
1057         struct drm_i915_private *dev_priv = dev->dev_private;
1058         struct drm_framebuffer *fb = crtc->fb;
1059         struct intel_framebuffer *intel_fb;
1060         struct drm_i915_gem_object *obj_priv;
1061         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1062         int plane = intel_crtc->plane;
1063
1064         if (!i915_powersave)
1065                 return;
1066
1067         if (!crtc->fb)
1068                 return;
1069
1070         intel_fb = to_intel_framebuffer(fb);
1071         obj_priv = intel_fb->obj->driver_private;
1072
1073         /*
1074          * If FBC is already on, we just have to verify that we can
1075          * keep it that way...
1076          * Need to disable if:
1077          *   - changing FBC params (stride, fence, mode)
1078          *   - new fb is too large to fit in compressed buffer
1079          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1080          */
1081         if (intel_fb->obj->size > dev_priv->cfb_size) {
1082                 DRM_DEBUG("framebuffer too large, disabling compression\n");
1083                 goto out_disable;
1084         }
1085         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1086             (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1087                 DRM_DEBUG("mode incompatible with compression, disabling\n");
1088                 goto out_disable;
1089         }
1090         if ((mode->hdisplay > 2048) ||
1091             (mode->vdisplay > 1536)) {
1092                 DRM_DEBUG("mode too large for compression, disabling\n");
1093                 goto out_disable;
1094         }
1095         if (IS_I9XX(dev) && plane != 0) {
1096                 DRM_DEBUG("plane not 0, disabling compression\n");
1097                 goto out_disable;
1098         }
1099         if (obj_priv->tiling_mode != I915_TILING_X) {
1100                 DRM_DEBUG("framebuffer not tiled, disabling compression\n");
1101                 goto out_disable;
1102         }
1103
1104         if (i8xx_fbc_enabled(crtc)) {
1105                 /* We can re-enable it in this case, but need to update pitch */
1106                 if (fb->pitch > dev_priv->cfb_pitch)
1107                         i8xx_disable_fbc(dev);
1108                 if (obj_priv->fence_reg != dev_priv->cfb_fence)
1109                         i8xx_disable_fbc(dev);
1110                 if (plane != dev_priv->cfb_plane)
1111                         i8xx_disable_fbc(dev);
1112         }
1113
1114         if (!i8xx_fbc_enabled(crtc)) {
1115                 /* Now try to turn it back on if possible */
1116                 i8xx_enable_fbc(crtc, 500);
1117         }
1118
1119         return;
1120
1121 out_disable:
1122         DRM_DEBUG("unsupported config, disabling FBC\n");
1123         /* Multiple disables should be harmless */
1124         if (i8xx_fbc_enabled(crtc))
1125                 i8xx_disable_fbc(dev);
1126 }
1127
1128 static int
1129 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1130                     struct drm_framebuffer *old_fb)
1131 {
1132         struct drm_device *dev = crtc->dev;
1133         struct drm_i915_private *dev_priv = dev->dev_private;
1134         struct drm_i915_master_private *master_priv;
1135         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1136         struct intel_framebuffer *intel_fb;
1137         struct drm_i915_gem_object *obj_priv;
1138         struct drm_gem_object *obj;
1139         int pipe = intel_crtc->pipe;
1140         int plane = intel_crtc->plane;
1141         unsigned long Start, Offset;
1142         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1143         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1144         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1145         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1146         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1147         u32 dspcntr, alignment;
1148         int ret;
1149
1150         /* no fb bound */
1151         if (!crtc->fb) {
1152                 DRM_DEBUG("No FB bound\n");
1153                 return 0;
1154         }
1155
1156         switch (plane) {
1157         case 0:
1158         case 1:
1159                 break;
1160         default:
1161                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1162                 return -EINVAL;
1163         }
1164
1165         intel_fb = to_intel_framebuffer(crtc->fb);
1166         obj = intel_fb->obj;
1167         obj_priv = obj->driver_private;
1168
1169         switch (obj_priv->tiling_mode) {
1170         case I915_TILING_NONE:
1171                 alignment = 64 * 1024;
1172                 break;
1173         case I915_TILING_X:
1174                 /* pin() will align the object as required by fence */
1175                 alignment = 0;
1176                 break;
1177         case I915_TILING_Y:
1178                 /* FIXME: Is this true? */
1179                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1180                 return -EINVAL;
1181         default:
1182                 BUG();
1183         }
1184
1185         mutex_lock(&dev->struct_mutex);
1186         ret = i915_gem_object_pin(obj, alignment);
1187         if (ret != 0) {
1188                 mutex_unlock(&dev->struct_mutex);
1189                 return ret;
1190         }
1191
1192         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
1193         if (ret != 0) {
1194                 i915_gem_object_unpin(obj);
1195                 mutex_unlock(&dev->struct_mutex);
1196                 return ret;
1197         }
1198
1199         /* Pre-i965 needs to install a fence for tiled scan-out */
1200         if (!IS_I965G(dev) &&
1201             obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1202             obj_priv->tiling_mode != I915_TILING_NONE) {
1203                 ret = i915_gem_object_get_fence_reg(obj);
1204                 if (ret != 0) {
1205                         i915_gem_object_unpin(obj);
1206                         mutex_unlock(&dev->struct_mutex);
1207                         return ret;
1208                 }
1209         }
1210
1211         dspcntr = I915_READ(dspcntr_reg);
1212         /* Mask out pixel format bits in case we change it */
1213         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1214         switch (crtc->fb->bits_per_pixel) {
1215         case 8:
1216                 dspcntr |= DISPPLANE_8BPP;
1217                 break;
1218         case 16:
1219                 if (crtc->fb->depth == 15)
1220                         dspcntr |= DISPPLANE_15_16BPP;
1221                 else
1222                         dspcntr |= DISPPLANE_16BPP;
1223                 break;
1224         case 24:
1225         case 32:
1226                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1227                 break;
1228         default:
1229                 DRM_ERROR("Unknown color depth\n");
1230                 i915_gem_object_unpin(obj);
1231                 mutex_unlock(&dev->struct_mutex);
1232                 return -EINVAL;
1233         }
1234         if (IS_I965G(dev)) {
1235                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1236                         dspcntr |= DISPPLANE_TILED;
1237                 else
1238                         dspcntr &= ~DISPPLANE_TILED;
1239         }
1240
1241         if (IS_IGDNG(dev))
1242                 /* must disable */
1243                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1244
1245         I915_WRITE(dspcntr_reg, dspcntr);
1246
1247         Start = obj_priv->gtt_offset;
1248         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1249
1250         DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1251         I915_WRITE(dspstride, crtc->fb->pitch);
1252         if (IS_I965G(dev)) {
1253                 I915_WRITE(dspbase, Offset);
1254                 I915_READ(dspbase);
1255                 I915_WRITE(dspsurf, Start);
1256                 I915_READ(dspsurf);
1257                 I915_WRITE(dsptileoff, (y << 16) | x);
1258         } else {
1259                 I915_WRITE(dspbase, Start + Offset);
1260                 I915_READ(dspbase);
1261         }
1262
1263         intel_wait_for_vblank(dev);
1264
1265         if (old_fb) {
1266                 intel_fb = to_intel_framebuffer(old_fb);
1267                 obj_priv = intel_fb->obj->driver_private;
1268                 i915_gem_object_unpin(intel_fb->obj);
1269         }
1270         intel_increase_pllclock(crtc, true);
1271
1272         mutex_unlock(&dev->struct_mutex);
1273
1274         if (!dev->primary->master)
1275                 return 0;
1276
1277         master_priv = dev->primary->master->driver_priv;
1278         if (!master_priv->sarea_priv)
1279                 return 0;
1280
1281         if (pipe) {
1282                 master_priv->sarea_priv->pipeB_x = x;
1283                 master_priv->sarea_priv->pipeB_y = y;
1284         } else {
1285                 master_priv->sarea_priv->pipeA_x = x;
1286                 master_priv->sarea_priv->pipeA_y = y;
1287         }
1288
1289         if (I915_HAS_FBC(dev) && (IS_I965G(dev) || plane == 0))
1290                 intel_update_fbc(crtc, &crtc->mode);
1291
1292         return 0;
1293 }
1294
1295 /* Disable the VGA plane that we never use */
1296 static void i915_disable_vga (struct drm_device *dev)
1297 {
1298         struct drm_i915_private *dev_priv = dev->dev_private;
1299         u8 sr1;
1300         u32 vga_reg;
1301
1302         if (IS_IGDNG(dev))
1303                 vga_reg = CPU_VGACNTRL;
1304         else
1305                 vga_reg = VGACNTRL;
1306
1307         if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1308                 return;
1309
1310         I915_WRITE8(VGA_SR_INDEX, 1);
1311         sr1 = I915_READ8(VGA_SR_DATA);
1312         I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1313         udelay(100);
1314
1315         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1316 }
1317
1318 static void igdng_disable_pll_edp (struct drm_crtc *crtc)
1319 {
1320         struct drm_device *dev = crtc->dev;
1321         struct drm_i915_private *dev_priv = dev->dev_private;
1322         u32 dpa_ctl;
1323
1324         DRM_DEBUG("\n");
1325         dpa_ctl = I915_READ(DP_A);
1326         dpa_ctl &= ~DP_PLL_ENABLE;
1327         I915_WRITE(DP_A, dpa_ctl);
1328 }
1329
1330 static void igdng_enable_pll_edp (struct drm_crtc *crtc)
1331 {
1332         struct drm_device *dev = crtc->dev;
1333         struct drm_i915_private *dev_priv = dev->dev_private;
1334         u32 dpa_ctl;
1335
1336         dpa_ctl = I915_READ(DP_A);
1337         dpa_ctl |= DP_PLL_ENABLE;
1338         I915_WRITE(DP_A, dpa_ctl);
1339         udelay(200);
1340 }
1341
1342
1343 static void igdng_set_pll_edp (struct drm_crtc *crtc, int clock)
1344 {
1345         struct drm_device *dev = crtc->dev;
1346         struct drm_i915_private *dev_priv = dev->dev_private;
1347         u32 dpa_ctl;
1348
1349         DRM_DEBUG("eDP PLL enable for clock %d\n", clock);
1350         dpa_ctl = I915_READ(DP_A);
1351         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1352
1353         if (clock < 200000) {
1354                 u32 temp;
1355                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1356                 /* workaround for 160Mhz:
1357                    1) program 0x4600c bits 15:0 = 0x8124
1358                    2) program 0x46010 bit 0 = 1
1359                    3) program 0x46034 bit 24 = 1
1360                    4) program 0x64000 bit 14 = 1
1361                    */
1362                 temp = I915_READ(0x4600c);
1363                 temp &= 0xffff0000;
1364                 I915_WRITE(0x4600c, temp | 0x8124);
1365
1366                 temp = I915_READ(0x46010);
1367                 I915_WRITE(0x46010, temp | 1);
1368
1369                 temp = I915_READ(0x46034);
1370                 I915_WRITE(0x46034, temp | (1 << 24));
1371         } else {
1372                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1373         }
1374         I915_WRITE(DP_A, dpa_ctl);
1375
1376         udelay(500);
1377 }
1378
1379 static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1380 {
1381         struct drm_device *dev = crtc->dev;
1382         struct drm_i915_private *dev_priv = dev->dev_private;
1383         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1384         int pipe = intel_crtc->pipe;
1385         int plane = intel_crtc->plane;
1386         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1387         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1388         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1389         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1390         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1391         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1392         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1393         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1394         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1395         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1396         int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1397         int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1398         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1399         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1400         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1401         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1402         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1403         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1404         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1405         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1406         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1407         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1408         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1409         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1410         u32 temp;
1411         int tries = 5, j, n;
1412
1413         /* XXX: When our outputs are all unaware of DPMS modes other than off
1414          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1415          */
1416         switch (mode) {
1417         case DRM_MODE_DPMS_ON:
1418         case DRM_MODE_DPMS_STANDBY:
1419         case DRM_MODE_DPMS_SUSPEND:
1420                 DRM_DEBUG("crtc %d dpms on\n", pipe);
1421                 if (HAS_eDP) {
1422                         /* enable eDP PLL */
1423                         igdng_enable_pll_edp(crtc);
1424                 } else {
1425                         /* enable PCH DPLL */
1426                         temp = I915_READ(pch_dpll_reg);
1427                         if ((temp & DPLL_VCO_ENABLE) == 0) {
1428                                 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1429                                 I915_READ(pch_dpll_reg);
1430                         }
1431
1432                         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1433                         temp = I915_READ(fdi_rx_reg);
1434                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
1435                                         FDI_SEL_PCDCLK |
1436                                         FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
1437                         I915_READ(fdi_rx_reg);
1438                         udelay(200);
1439
1440                         /* Enable CPU FDI TX PLL, always on for IGDNG */
1441                         temp = I915_READ(fdi_tx_reg);
1442                         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1443                                 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1444                                 I915_READ(fdi_tx_reg);
1445                                 udelay(100);
1446                         }
1447                 }
1448
1449                 /* Enable panel fitting for LVDS */
1450                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1451                         temp = I915_READ(pf_ctl_reg);
1452                         I915_WRITE(pf_ctl_reg, temp | PF_ENABLE);
1453
1454                         /* currently full aspect */
1455                         I915_WRITE(pf_win_pos, 0);
1456
1457                         I915_WRITE(pf_win_size,
1458                                    (dev_priv->panel_fixed_mode->hdisplay << 16) |
1459                                    (dev_priv->panel_fixed_mode->vdisplay));
1460                 }
1461
1462                 /* Enable CPU pipe */
1463                 temp = I915_READ(pipeconf_reg);
1464                 if ((temp & PIPEACONF_ENABLE) == 0) {
1465                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1466                         I915_READ(pipeconf_reg);
1467                         udelay(100);
1468                 }
1469
1470                 /* configure and enable CPU plane */
1471                 temp = I915_READ(dspcntr_reg);
1472                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1473                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1474                         /* Flush the plane changes */
1475                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1476                 }
1477
1478                 if (!HAS_eDP) {
1479                         /* enable CPU FDI TX and PCH FDI RX */
1480                         temp = I915_READ(fdi_tx_reg);
1481                         temp |= FDI_TX_ENABLE;
1482                         temp |= FDI_DP_PORT_WIDTH_X4; /* default */
1483                         temp &= ~FDI_LINK_TRAIN_NONE;
1484                         temp |= FDI_LINK_TRAIN_PATTERN_1;
1485                         I915_WRITE(fdi_tx_reg, temp);
1486                         I915_READ(fdi_tx_reg);
1487
1488                         temp = I915_READ(fdi_rx_reg);
1489                         temp &= ~FDI_LINK_TRAIN_NONE;
1490                         temp |= FDI_LINK_TRAIN_PATTERN_1;
1491                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1492                         I915_READ(fdi_rx_reg);
1493
1494                         udelay(150);
1495
1496                         /* Train FDI. */
1497                         /* umask FDI RX Interrupt symbol_lock and bit_lock bit
1498                            for train result */
1499                         temp = I915_READ(fdi_rx_imr_reg);
1500                         temp &= ~FDI_RX_SYMBOL_LOCK;
1501                         temp &= ~FDI_RX_BIT_LOCK;
1502                         I915_WRITE(fdi_rx_imr_reg, temp);
1503                         I915_READ(fdi_rx_imr_reg);
1504                         udelay(150);
1505
1506                         temp = I915_READ(fdi_rx_iir_reg);
1507                         DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1508
1509                         if ((temp & FDI_RX_BIT_LOCK) == 0) {
1510                                 for (j = 0; j < tries; j++) {
1511                                         temp = I915_READ(fdi_rx_iir_reg);
1512                                         DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1513                                         if (temp & FDI_RX_BIT_LOCK)
1514                                                 break;
1515                                         udelay(200);
1516                                 }
1517                                 if (j != tries)
1518                                         I915_WRITE(fdi_rx_iir_reg,
1519                                                         temp | FDI_RX_BIT_LOCK);
1520                                 else
1521                                         DRM_DEBUG("train 1 fail\n");
1522                         } else {
1523                                 I915_WRITE(fdi_rx_iir_reg,
1524                                                 temp | FDI_RX_BIT_LOCK);
1525                                 DRM_DEBUG("train 1 ok 2!\n");
1526                         }
1527                         temp = I915_READ(fdi_tx_reg);
1528                         temp &= ~FDI_LINK_TRAIN_NONE;
1529                         temp |= FDI_LINK_TRAIN_PATTERN_2;
1530                         I915_WRITE(fdi_tx_reg, temp);
1531
1532                         temp = I915_READ(fdi_rx_reg);
1533                         temp &= ~FDI_LINK_TRAIN_NONE;
1534                         temp |= FDI_LINK_TRAIN_PATTERN_2;
1535                         I915_WRITE(fdi_rx_reg, temp);
1536
1537                         udelay(150);
1538
1539                         temp = I915_READ(fdi_rx_iir_reg);
1540                         DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1541
1542                         if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
1543                                 for (j = 0; j < tries; j++) {
1544                                         temp = I915_READ(fdi_rx_iir_reg);
1545                                         DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1546                                         if (temp & FDI_RX_SYMBOL_LOCK)
1547                                                 break;
1548                                         udelay(200);
1549                                 }
1550                                 if (j != tries) {
1551                                         I915_WRITE(fdi_rx_iir_reg,
1552                                                         temp | FDI_RX_SYMBOL_LOCK);
1553                                         DRM_DEBUG("train 2 ok 1!\n");
1554                                 } else
1555                                         DRM_DEBUG("train 2 fail\n");
1556                         } else {
1557                                 I915_WRITE(fdi_rx_iir_reg,
1558                                                 temp | FDI_RX_SYMBOL_LOCK);
1559                                 DRM_DEBUG("train 2 ok 2!\n");
1560                         }
1561                         DRM_DEBUG("train done\n");
1562
1563                         /* set transcoder timing */
1564                         I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1565                         I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1566                         I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1567
1568                         I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1569                         I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1570                         I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1571
1572                         /* enable PCH transcoder */
1573                         temp = I915_READ(transconf_reg);
1574                         I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1575                         I915_READ(transconf_reg);
1576
1577                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1578                                 ;
1579
1580                         /* enable normal */
1581
1582                         temp = I915_READ(fdi_tx_reg);
1583                         temp &= ~FDI_LINK_TRAIN_NONE;
1584                         I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1585                                         FDI_TX_ENHANCE_FRAME_ENABLE);
1586                         I915_READ(fdi_tx_reg);
1587
1588                         temp = I915_READ(fdi_rx_reg);
1589                         temp &= ~FDI_LINK_TRAIN_NONE;
1590                         I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
1591                                         FDI_RX_ENHANCE_FRAME_ENABLE);
1592                         I915_READ(fdi_rx_reg);
1593
1594                         /* wait one idle pattern time */
1595                         udelay(100);
1596
1597                 }
1598
1599                 intel_crtc_load_lut(crtc);
1600
1601         break;
1602         case DRM_MODE_DPMS_OFF:
1603                 DRM_DEBUG("crtc %d dpms off\n", pipe);
1604
1605                 i915_disable_vga(dev);
1606
1607                 /* Disable display plane */
1608                 temp = I915_READ(dspcntr_reg);
1609                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1610                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1611                         /* Flush the plane changes */
1612                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1613                         I915_READ(dspbase_reg);
1614                 }
1615
1616                 /* disable cpu pipe, disable after all planes disabled */
1617                 temp = I915_READ(pipeconf_reg);
1618                 if ((temp & PIPEACONF_ENABLE) != 0) {
1619                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1620                         I915_READ(pipeconf_reg);
1621                         n = 0;
1622                         /* wait for cpu pipe off, pipe state */
1623                         while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
1624                                 n++;
1625                                 if (n < 60) {
1626                                         udelay(500);
1627                                         continue;
1628                                 } else {
1629                                         DRM_DEBUG("pipe %d off delay\n", pipe);
1630                                         break;
1631                                 }
1632                         }
1633                 } else
1634                         DRM_DEBUG("crtc %d is disabled\n", pipe);
1635
1636                 if (HAS_eDP) {
1637                         igdng_disable_pll_edp(crtc);
1638                 }
1639
1640                 /* disable CPU FDI tx and PCH FDI rx */
1641                 temp = I915_READ(fdi_tx_reg);
1642                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
1643                 I915_READ(fdi_tx_reg);
1644
1645                 temp = I915_READ(fdi_rx_reg);
1646                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
1647                 I915_READ(fdi_rx_reg);
1648
1649                 udelay(100);
1650
1651                 /* still set train pattern 1 */
1652                 temp = I915_READ(fdi_tx_reg);
1653                 temp &= ~FDI_LINK_TRAIN_NONE;
1654                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1655                 I915_WRITE(fdi_tx_reg, temp);
1656
1657                 temp = I915_READ(fdi_rx_reg);
1658                 temp &= ~FDI_LINK_TRAIN_NONE;
1659                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1660                 I915_WRITE(fdi_rx_reg, temp);
1661
1662                 udelay(100);
1663
1664                 /* disable PCH transcoder */
1665                 temp = I915_READ(transconf_reg);
1666                 if ((temp & TRANS_ENABLE) != 0) {
1667                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
1668                         I915_READ(transconf_reg);
1669                         n = 0;
1670                         /* wait for PCH transcoder off, transcoder state */
1671                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
1672                                 n++;
1673                                 if (n < 60) {
1674                                         udelay(500);
1675                                         continue;
1676                                 } else {
1677                                         DRM_DEBUG("transcoder %d off delay\n", pipe);
1678                                         break;
1679                                 }
1680                         }
1681                 }
1682
1683                 /* disable PCH DPLL */
1684                 temp = I915_READ(pch_dpll_reg);
1685                 if ((temp & DPLL_VCO_ENABLE) != 0) {
1686                         I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
1687                         I915_READ(pch_dpll_reg);
1688                 }
1689
1690                 temp = I915_READ(fdi_rx_reg);
1691                 if ((temp & FDI_RX_PLL_ENABLE) != 0) {
1692                         temp &= ~FDI_SEL_PCDCLK;
1693                         temp &= ~FDI_RX_PLL_ENABLE;
1694                         I915_WRITE(fdi_rx_reg, temp);
1695                         I915_READ(fdi_rx_reg);
1696                 }
1697
1698                 /* Disable CPU FDI TX PLL */
1699                 temp = I915_READ(fdi_tx_reg);
1700                 if ((temp & FDI_TX_PLL_ENABLE) != 0) {
1701                         I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
1702                         I915_READ(fdi_tx_reg);
1703                         udelay(100);
1704                 }
1705
1706                 /* Disable PF */
1707                 temp = I915_READ(pf_ctl_reg);
1708                 if ((temp & PF_ENABLE) != 0) {
1709                         I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1710                         I915_READ(pf_ctl_reg);
1711                 }
1712                 I915_WRITE(pf_win_size, 0);
1713
1714                 /* Wait for the clocks to turn off. */
1715                 udelay(150);
1716                 break;
1717         }
1718 }
1719
1720 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1721 {
1722         struct drm_device *dev = crtc->dev;
1723         struct drm_i915_private *dev_priv = dev->dev_private;
1724         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1725         int pipe = intel_crtc->pipe;
1726         int plane = intel_crtc->plane;
1727         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
1728         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1729         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1730         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1731         u32 temp;
1732
1733         /* XXX: When our outputs are all unaware of DPMS modes other than off
1734          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1735          */
1736         switch (mode) {
1737         case DRM_MODE_DPMS_ON:
1738         case DRM_MODE_DPMS_STANDBY:
1739         case DRM_MODE_DPMS_SUSPEND:
1740                 /* Enable the DPLL */
1741                 temp = I915_READ(dpll_reg);
1742                 if ((temp & DPLL_VCO_ENABLE) == 0) {
1743                         I915_WRITE(dpll_reg, temp);
1744                         I915_READ(dpll_reg);
1745                         /* Wait for the clocks to stabilize. */
1746                         udelay(150);
1747                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1748                         I915_READ(dpll_reg);
1749                         /* Wait for the clocks to stabilize. */
1750                         udelay(150);
1751                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1752                         I915_READ(dpll_reg);
1753                         /* Wait for the clocks to stabilize. */
1754                         udelay(150);
1755                 }
1756
1757                 /* Enable the pipe */
1758                 temp = I915_READ(pipeconf_reg);
1759                 if ((temp & PIPEACONF_ENABLE) == 0)
1760                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1761
1762                 /* Enable the plane */
1763                 temp = I915_READ(dspcntr_reg);
1764                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1765                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1766                         /* Flush the plane changes */
1767                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1768                 }
1769
1770                 intel_crtc_load_lut(crtc);
1771
1772                 if (I915_HAS_FBC(dev) && (IS_I965G(dev) || plane == 0))
1773                         intel_update_fbc(crtc, &crtc->mode);
1774
1775                 /* Give the overlay scaler a chance to enable if it's on this pipe */
1776                 //intel_crtc_dpms_video(crtc, true); TODO
1777                 intel_update_watermarks(dev);
1778         break;
1779         case DRM_MODE_DPMS_OFF:
1780                 intel_update_watermarks(dev);
1781                 /* Give the overlay scaler a chance to disable if it's on this pipe */
1782                 //intel_crtc_dpms_video(crtc, FALSE); TODO
1783
1784                 if (dev_priv->cfb_plane == plane)
1785                         i8xx_disable_fbc(dev);
1786
1787                 /* Disable the VGA plane that we never use */
1788                 i915_disable_vga(dev);
1789
1790                 /* Disable display plane */
1791                 temp = I915_READ(dspcntr_reg);
1792                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1793                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1794                         /* Flush the plane changes */
1795                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1796                         I915_READ(dspbase_reg);
1797                 }
1798
1799                 if (!IS_I9XX(dev)) {
1800                         /* Wait for vblank for the disable to take effect */
1801                         intel_wait_for_vblank(dev);
1802                 }
1803
1804                 /* Next, disable display pipes */
1805                 temp = I915_READ(pipeconf_reg);
1806                 if ((temp & PIPEACONF_ENABLE) != 0) {
1807                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1808                         I915_READ(pipeconf_reg);
1809                 }
1810
1811                 /* Wait for vblank for the disable to take effect. */
1812                 intel_wait_for_vblank(dev);
1813
1814                 temp = I915_READ(dpll_reg);
1815                 if ((temp & DPLL_VCO_ENABLE) != 0) {
1816                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
1817                         I915_READ(dpll_reg);
1818                 }
1819
1820                 /* Wait for the clocks to turn off. */
1821                 udelay(150);
1822                 break;
1823         }
1824 }
1825
1826 /**
1827  * Sets the power management mode of the pipe and plane.
1828  *
1829  * This code should probably grow support for turning the cursor off and back
1830  * on appropriately at the same time as we're turning the pipe off/on.
1831  */
1832 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
1833 {
1834         struct drm_device *dev = crtc->dev;
1835         struct drm_i915_master_private *master_priv;
1836         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1837         int pipe = intel_crtc->pipe;
1838         bool enabled;
1839
1840         if (IS_IGDNG(dev))
1841                 igdng_crtc_dpms(crtc, mode);
1842         else
1843                 i9xx_crtc_dpms(crtc, mode);
1844
1845         intel_crtc->dpms_mode = mode;
1846
1847         if (!dev->primary->master)
1848                 return;
1849
1850         master_priv = dev->primary->master->driver_priv;
1851         if (!master_priv->sarea_priv)
1852                 return;
1853
1854         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
1855
1856         switch (pipe) {
1857         case 0:
1858                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
1859                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
1860                 break;
1861         case 1:
1862                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
1863                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
1864                 break;
1865         default:
1866                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
1867                 break;
1868         }
1869 }
1870
1871 static void intel_crtc_prepare (struct drm_crtc *crtc)
1872 {
1873         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1874         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
1875 }
1876
1877 static void intel_crtc_commit (struct drm_crtc *crtc)
1878 {
1879         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1880         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1881 }
1882
1883 void intel_encoder_prepare (struct drm_encoder *encoder)
1884 {
1885         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1886         /* lvds has its own version of prepare see intel_lvds_prepare */
1887         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
1888 }
1889
1890 void intel_encoder_commit (struct drm_encoder *encoder)
1891 {
1892         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1893         /* lvds has its own version of commit see intel_lvds_commit */
1894         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
1895 }
1896
1897 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
1898                                   struct drm_display_mode *mode,
1899                                   struct drm_display_mode *adjusted_mode)
1900 {
1901         struct drm_device *dev = crtc->dev;
1902         if (IS_IGDNG(dev)) {
1903                 /* FDI link clock is fixed at 2.7G */
1904                 if (mode->clock * 3 > 27000 * 4)
1905                         return MODE_CLOCK_HIGH;
1906         }
1907         return true;
1908 }
1909
1910
1911 /** Returns the core display clock speed for i830 - i945 */
1912 static int intel_get_core_clock_speed(struct drm_device *dev)
1913 {
1914
1915         /* Core clock values taken from the published datasheets.
1916          * The 830 may go up to 166 Mhz, which we should check.
1917          */
1918         if (IS_I945G(dev))
1919                 return 400000;
1920         else if (IS_I915G(dev))
1921                 return 333000;
1922         else if (IS_I945GM(dev) || IS_845G(dev) || IS_IGDGM(dev))
1923                 return 200000;
1924         else if (IS_I915GM(dev)) {
1925                 u16 gcfgc = 0;
1926
1927                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
1928
1929                 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
1930                         return 133000;
1931                 else {
1932                         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
1933                         case GC_DISPLAY_CLOCK_333_MHZ:
1934                                 return 333000;
1935                         default:
1936                         case GC_DISPLAY_CLOCK_190_200_MHZ:
1937                                 return 190000;
1938                         }
1939                 }
1940         } else if (IS_I865G(dev))
1941                 return 266000;
1942         else if (IS_I855(dev)) {
1943                 u16 hpllcc = 0;
1944                 /* Assume that the hardware is in the high speed state.  This
1945                  * should be the default.
1946                  */
1947                 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
1948                 case GC_CLOCK_133_200:
1949                 case GC_CLOCK_100_200:
1950                         return 200000;
1951                 case GC_CLOCK_166_250:
1952                         return 250000;
1953                 case GC_CLOCK_100_133:
1954                         return 133000;
1955                 }
1956         } else /* 852, 830 */
1957                 return 133000;
1958
1959         return 0; /* Silence gcc warning */
1960 }
1961
1962 /**
1963  * Return the pipe currently connected to the panel fitter,
1964  * or -1 if the panel fitter is not present or not in use
1965  */
1966 static int intel_panel_fitter_pipe (struct drm_device *dev)
1967 {
1968         struct drm_i915_private *dev_priv = dev->dev_private;
1969         u32  pfit_control;
1970
1971         /* i830 doesn't have a panel fitter */
1972         if (IS_I830(dev))
1973                 return -1;
1974
1975         pfit_control = I915_READ(PFIT_CONTROL);
1976
1977         /* See if the panel fitter is in use */
1978         if ((pfit_control & PFIT_ENABLE) == 0)
1979                 return -1;
1980
1981         /* 965 can place panel fitter on either pipe */
1982         if (IS_I965G(dev))
1983                 return (pfit_control >> 29) & 0x3;
1984
1985         /* older chips can only use pipe 1 */
1986         return 1;
1987 }
1988
1989 struct fdi_m_n {
1990         u32        tu;
1991         u32        gmch_m;
1992         u32        gmch_n;
1993         u32        link_m;
1994         u32        link_n;
1995 };
1996
1997 static void
1998 fdi_reduce_ratio(u32 *num, u32 *den)
1999 {
2000         while (*num > 0xffffff || *den > 0xffffff) {
2001                 *num >>= 1;
2002                 *den >>= 1;
2003         }
2004 }
2005
2006 #define DATA_N 0x800000
2007 #define LINK_N 0x80000
2008
2009 static void
2010 igdng_compute_m_n(int bytes_per_pixel, int nlanes,
2011                 int pixel_clock, int link_clock,
2012                 struct fdi_m_n *m_n)
2013 {
2014         u64 temp;
2015
2016         m_n->tu = 64; /* default size */
2017
2018         temp = (u64) DATA_N * pixel_clock;
2019         temp = div_u64(temp, link_clock);
2020         m_n->gmch_m = div_u64(temp * bytes_per_pixel, nlanes);
2021         m_n->gmch_n = DATA_N;
2022         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2023
2024         temp = (u64) LINK_N * pixel_clock;
2025         m_n->link_m = div_u64(temp, link_clock);
2026         m_n->link_n = LINK_N;
2027         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2028 }
2029
2030
2031 struct intel_watermark_params {
2032         unsigned long fifo_size;
2033         unsigned long max_wm;
2034         unsigned long default_wm;
2035         unsigned long guard_size;
2036         unsigned long cacheline_size;
2037 };
2038
2039 /* IGD has different values for various configs */
2040 static struct intel_watermark_params igd_display_wm = {
2041         IGD_DISPLAY_FIFO,
2042         IGD_MAX_WM,
2043         IGD_DFT_WM,
2044         IGD_GUARD_WM,
2045         IGD_FIFO_LINE_SIZE
2046 };
2047 static struct intel_watermark_params igd_display_hplloff_wm = {
2048         IGD_DISPLAY_FIFO,
2049         IGD_MAX_WM,
2050         IGD_DFT_HPLLOFF_WM,
2051         IGD_GUARD_WM,
2052         IGD_FIFO_LINE_SIZE
2053 };
2054 static struct intel_watermark_params igd_cursor_wm = {
2055         IGD_CURSOR_FIFO,
2056         IGD_CURSOR_MAX_WM,
2057         IGD_CURSOR_DFT_WM,
2058         IGD_CURSOR_GUARD_WM,
2059         IGD_FIFO_LINE_SIZE,
2060 };
2061 static struct intel_watermark_params igd_cursor_hplloff_wm = {
2062         IGD_CURSOR_FIFO,
2063         IGD_CURSOR_MAX_WM,
2064         IGD_CURSOR_DFT_WM,
2065         IGD_CURSOR_GUARD_WM,
2066         IGD_FIFO_LINE_SIZE
2067 };
2068 static struct intel_watermark_params i945_wm_info = {
2069         I945_FIFO_SIZE,
2070         I915_MAX_WM,
2071         1,
2072         2,
2073         I915_FIFO_LINE_SIZE
2074 };
2075 static struct intel_watermark_params i915_wm_info = {
2076         I915_FIFO_SIZE,
2077         I915_MAX_WM,
2078         1,
2079         2,
2080         I915_FIFO_LINE_SIZE
2081 };
2082 static struct intel_watermark_params i855_wm_info = {
2083         I855GM_FIFO_SIZE,
2084         I915_MAX_WM,
2085         1,
2086         2,
2087         I830_FIFO_LINE_SIZE
2088 };
2089 static struct intel_watermark_params i830_wm_info = {
2090         I830_FIFO_SIZE,
2091         I915_MAX_WM,
2092         1,
2093         2,
2094         I830_FIFO_LINE_SIZE
2095 };
2096
2097 /**
2098  * intel_calculate_wm - calculate watermark level
2099  * @clock_in_khz: pixel clock
2100  * @wm: chip FIFO params
2101  * @pixel_size: display pixel size
2102  * @latency_ns: memory latency for the platform
2103  *
2104  * Calculate the watermark level (the level at which the display plane will
2105  * start fetching from memory again).  Each chip has a different display
2106  * FIFO size and allocation, so the caller needs to figure that out and pass
2107  * in the correct intel_watermark_params structure.
2108  *
2109  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2110  * on the pixel size.  When it reaches the watermark level, it'll start
2111  * fetching FIFO line sized based chunks from memory until the FIFO fills
2112  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2113  * will occur, and a display engine hang could result.
2114  */
2115 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2116                                         struct intel_watermark_params *wm,
2117                                         int pixel_size,
2118                                         unsigned long latency_ns)
2119 {
2120         long entries_required, wm_size;
2121
2122         entries_required = (clock_in_khz * pixel_size * latency_ns) / 1000000;
2123         entries_required /= wm->cacheline_size;
2124
2125         DRM_DEBUG("FIFO entries required for mode: %d\n", entries_required);
2126
2127         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2128
2129         DRM_DEBUG("FIFO watermark level: %d\n", wm_size);
2130
2131         /* Don't promote wm_size to unsigned... */
2132         if (wm_size > (long)wm->max_wm)
2133                 wm_size = wm->max_wm;
2134         if (wm_size <= 0)
2135                 wm_size = wm->default_wm;
2136         return wm_size;
2137 }
2138
2139 struct cxsr_latency {
2140         int is_desktop;
2141         unsigned long fsb_freq;
2142         unsigned long mem_freq;
2143         unsigned long display_sr;
2144         unsigned long display_hpll_disable;
2145         unsigned long cursor_sr;
2146         unsigned long cursor_hpll_disable;
2147 };
2148
2149 static struct cxsr_latency cxsr_latency_table[] = {
2150         {1, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2151         {1, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2152         {1, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2153
2154         {1, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2155         {1, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2156         {1, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2157
2158         {1, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2159         {1, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2160         {1, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2161
2162         {0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2163         {0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2164         {0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2165
2166         {0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2167         {0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2168         {0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2169
2170         {0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2171         {0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2172         {0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2173 };
2174
2175 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
2176                                                    int mem)
2177 {
2178         int i;
2179         struct cxsr_latency *latency;
2180
2181         if (fsb == 0 || mem == 0)
2182                 return NULL;
2183
2184         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2185                 latency = &cxsr_latency_table[i];
2186                 if (is_desktop == latency->is_desktop &&
2187                         fsb == latency->fsb_freq && mem == latency->mem_freq)
2188                         break;
2189         }
2190         if (i >= ARRAY_SIZE(cxsr_latency_table)) {
2191                 DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
2192                 return NULL;
2193         }
2194         return latency;
2195 }
2196
2197 static void igd_disable_cxsr(struct drm_device *dev)
2198 {
2199         struct drm_i915_private *dev_priv = dev->dev_private;
2200         u32 reg;
2201
2202         /* deactivate cxsr */
2203         reg = I915_READ(DSPFW3);
2204         reg &= ~(IGD_SELF_REFRESH_EN);
2205         I915_WRITE(DSPFW3, reg);
2206         DRM_INFO("Big FIFO is disabled\n");
2207 }
2208
2209 static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
2210                             int pixel_size)
2211 {
2212         struct drm_i915_private *dev_priv = dev->dev_private;
2213         u32 reg;
2214         unsigned long wm;
2215         struct cxsr_latency *latency;
2216
2217         latency = intel_get_cxsr_latency(IS_IGDG(dev), dev_priv->fsb_freq,
2218                 dev_priv->mem_freq);
2219         if (!latency) {
2220                 DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
2221                 igd_disable_cxsr(dev);
2222                 return;
2223         }
2224
2225         /* Display SR */
2226         wm = intel_calculate_wm(clock, &igd_display_wm, pixel_size,
2227                                 latency->display_sr);
2228         reg = I915_READ(DSPFW1);
2229         reg &= 0x7fffff;
2230         reg |= wm << 23;
2231         I915_WRITE(DSPFW1, reg);
2232         DRM_DEBUG("DSPFW1 register is %x\n", reg);
2233
2234         /* cursor SR */
2235         wm = intel_calculate_wm(clock, &igd_cursor_wm, pixel_size,
2236                                 latency->cursor_sr);
2237         reg = I915_READ(DSPFW3);
2238         reg &= ~(0x3f << 24);
2239         reg |= (wm & 0x3f) << 24;
2240         I915_WRITE(DSPFW3, reg);
2241
2242         /* Display HPLL off SR */
2243         wm = intel_calculate_wm(clock, &igd_display_hplloff_wm,
2244                 latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
2245         reg = I915_READ(DSPFW3);
2246         reg &= 0xfffffe00;
2247         reg |= wm & 0x1ff;
2248         I915_WRITE(DSPFW3, reg);
2249
2250         /* cursor HPLL off SR */
2251         wm = intel_calculate_wm(clock, &igd_cursor_hplloff_wm, pixel_size,
2252                                 latency->cursor_hpll_disable);
2253         reg = I915_READ(DSPFW3);
2254         reg &= ~(0x3f << 16);
2255         reg |= (wm & 0x3f) << 16;
2256         I915_WRITE(DSPFW3, reg);
2257         DRM_DEBUG("DSPFW3 register is %x\n", reg);
2258
2259         /* activate cxsr */
2260         reg = I915_READ(DSPFW3);
2261         reg |= IGD_SELF_REFRESH_EN;
2262         I915_WRITE(DSPFW3, reg);
2263
2264         DRM_INFO("Big FIFO is enabled\n");
2265
2266         return;
2267 }
2268
2269 /*
2270  * Latency for FIFO fetches is dependent on several factors:
2271  *   - memory configuration (speed, channels)
2272  *   - chipset
2273  *   - current MCH state
2274  * It can be fairly high in some situations, so here we assume a fairly
2275  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2276  * set this value too high, the FIFO will fetch frequently to stay full)
2277  * and power consumption (set it too low to save power and we might see
2278  * FIFO underruns and display "flicker").
2279  *
2280  * A value of 5us seems to be a good balance; safe for very low end
2281  * platforms but not overly aggressive on lower latency configs.
2282  */
2283 const static int latency_ns = 5000;
2284
2285 static int intel_get_fifo_size(struct drm_device *dev, int plane)
2286 {
2287         struct drm_i915_private *dev_priv = dev->dev_private;
2288         uint32_t dsparb = I915_READ(DSPARB);
2289         int size;
2290
2291         if (IS_I9XX(dev)) {
2292                 if (plane == 0)
2293                         size = dsparb & 0x7f;
2294                 else
2295                         size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2296                                 (dsparb & 0x7f);
2297         } else if (IS_I85X(dev)) {
2298                 if (plane == 0)
2299                         size = dsparb & 0x1ff;
2300                 else
2301                         size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2302                                 (dsparb & 0x1ff);
2303                 size >>= 1; /* Convert to cachelines */
2304         } else if (IS_845G(dev)) {
2305                 size = dsparb & 0x7f;
2306                 size >>= 2; /* Convert to cachelines */
2307         } else {
2308                 size = dsparb & 0x7f;
2309                 size >>= 1; /* Convert to cachelines */
2310         }
2311
2312         DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
2313                   size);
2314
2315         return size;
2316 }
2317
2318 static void g4x_update_wm(struct drm_device *dev)
2319 {
2320         struct drm_i915_private *dev_priv = dev->dev_private;
2321         u32 fw_blc_self = I915_READ(FW_BLC_SELF);
2322
2323         if (i915_powersave)
2324                 fw_blc_self |= FW_BLC_SELF_EN;
2325         else
2326                 fw_blc_self &= ~FW_BLC_SELF_EN;
2327         I915_WRITE(FW_BLC_SELF, fw_blc_self);
2328 }
2329
2330 static void i965_update_wm(struct drm_device *dev)
2331 {
2332         struct drm_i915_private *dev_priv = dev->dev_private;
2333
2334         DRM_DEBUG("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 8\n");
2335
2336         /* 965 has limitations... */
2337         I915_WRITE(DSPFW1, (8 << 16) | (8 << 8) | (8 << 0));
2338         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
2339 }
2340
2341 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2342                            int planeb_clock, int sr_hdisplay, int pixel_size)
2343 {
2344         struct drm_i915_private *dev_priv = dev->dev_private;
2345         uint32_t fwater_lo;
2346         uint32_t fwater_hi;
2347         int total_size, cacheline_size, cwm, srwm = 1;
2348         int planea_wm, planeb_wm;
2349         struct intel_watermark_params planea_params, planeb_params;
2350         unsigned long line_time_us;
2351         int sr_clock, sr_entries = 0;
2352
2353         /* Create copies of the base settings for each pipe */
2354         if (IS_I965GM(dev) || IS_I945GM(dev))
2355                 planea_params = planeb_params = i945_wm_info;
2356         else if (IS_I9XX(dev))
2357                 planea_params = planeb_params = i915_wm_info;
2358         else
2359                 planea_params = planeb_params = i855_wm_info;
2360
2361         /* Grab a couple of global values before we overwrite them */
2362         total_size = planea_params.fifo_size;
2363         cacheline_size = planea_params.cacheline_size;
2364
2365         /* Update per-plane FIFO sizes */
2366         planea_params.fifo_size = intel_get_fifo_size(dev, 0);
2367         planeb_params.fifo_size = intel_get_fifo_size(dev, 1);
2368
2369         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
2370                                        pixel_size, latency_ns);
2371         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
2372                                        pixel_size, latency_ns);
2373         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2374
2375         /*
2376          * Overlay gets an aggressive default since video jitter is bad.
2377          */
2378         cwm = 2;
2379
2380         /* Calc sr entries for one plane configs */
2381         if (HAS_FW_BLC(dev) && sr_hdisplay &&
2382             (!planea_clock || !planeb_clock)) {
2383                 /* self-refresh has much higher latency */
2384                 const static int sr_latency_ns = 6000;
2385
2386                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2387                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2388
2389                 /* Use ns/us then divide to preserve precision */
2390                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2391                               pixel_size * sr_hdisplay) / 1000;
2392                 sr_entries = roundup(sr_entries / cacheline_size, 1);
2393                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2394                 srwm = total_size - sr_entries;
2395                 if (srwm < 0)
2396                         srwm = 1;
2397                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f));
2398         }
2399
2400         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2401                   planea_wm, planeb_wm, cwm, srwm);
2402
2403         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
2404         fwater_hi = (cwm & 0x1f);
2405
2406         /* Set request length to 8 cachelines per fetch */
2407         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
2408         fwater_hi = fwater_hi | (1 << 8);
2409
2410         I915_WRITE(FW_BLC, fwater_lo);
2411         I915_WRITE(FW_BLC2, fwater_hi);
2412 }
2413
2414 static void i830_update_wm(struct drm_device *dev, int planea_clock,
2415                            int pixel_size)
2416 {
2417         struct drm_i915_private *dev_priv = dev->dev_private;
2418         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
2419         int planea_wm;
2420
2421         i830_wm_info.fifo_size = intel_get_fifo_size(dev, 0);
2422
2423         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
2424                                        pixel_size, latency_ns);
2425         fwater_lo |= (3<<8) | planea_wm;
2426
2427         DRM_DEBUG("Setting FIFO watermarks - A: %d\n", planea_wm);
2428
2429         I915_WRITE(FW_BLC, fwater_lo);
2430 }
2431
2432 /**
2433  * intel_update_watermarks - update FIFO watermark values based on current modes
2434  *
2435  * Calculate watermark values for the various WM regs based on current mode
2436  * and plane configuration.
2437  *
2438  * There are several cases to deal with here:
2439  *   - normal (i.e. non-self-refresh)
2440  *   - self-refresh (SR) mode
2441  *   - lines are large relative to FIFO size (buffer can hold up to 2)
2442  *   - lines are small relative to FIFO size (buffer can hold more than 2
2443  *     lines), so need to account for TLB latency
2444  *
2445  *   The normal calculation is:
2446  *     watermark = dotclock * bytes per pixel * latency
2447  *   where latency is platform & configuration dependent (we assume pessimal
2448  *   values here).
2449  *
2450  *   The SR calculation is:
2451  *     watermark = (trunc(latency/line time)+1) * surface width *
2452  *       bytes per pixel
2453  *   where
2454  *     line time = htotal / dotclock
2455  *   and latency is assumed to be high, as above.
2456  *
2457  * The final value programmed to the register should always be rounded up,
2458  * and include an extra 2 entries to account for clock crossings.
2459  *
2460  * We don't use the sprite, so we can ignore that.  And on Crestline we have
2461  * to set the non-SR watermarks to 8.
2462   */
2463 static void intel_update_watermarks(struct drm_device *dev)
2464 {
2465         struct drm_crtc *crtc;
2466         struct intel_crtc *intel_crtc;
2467         int sr_hdisplay = 0;
2468         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
2469         int enabled = 0, pixel_size = 0;
2470
2471         /* Get the clock config from both planes */
2472         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2473                 intel_crtc = to_intel_crtc(crtc);
2474                 if (crtc->enabled) {
2475                         enabled++;
2476                         if (intel_crtc->plane == 0) {
2477                                 DRM_DEBUG("plane A (pipe %d) clock: %d\n",
2478                                           intel_crtc->pipe, crtc->mode.clock);
2479                                 planea_clock = crtc->mode.clock;
2480                         } else {
2481                                 DRM_DEBUG("plane B (pipe %d) clock: %d\n",
2482                                           intel_crtc->pipe, crtc->mode.clock);
2483                                 planeb_clock = crtc->mode.clock;
2484                         }
2485                         sr_hdisplay = crtc->mode.hdisplay;
2486                         sr_clock = crtc->mode.clock;
2487                         if (crtc->fb)
2488                                 pixel_size = crtc->fb->bits_per_pixel / 8;
2489                         else
2490                                 pixel_size = 4; /* by default */
2491                 }
2492         }
2493
2494         if (enabled <= 0)
2495                 return;
2496
2497         /* Single plane configs can enable self refresh */
2498         if (enabled == 1 && IS_IGD(dev))
2499                 igd_enable_cxsr(dev, sr_clock, pixel_size);
2500         else if (IS_IGD(dev))
2501                 igd_disable_cxsr(dev);
2502
2503         if (IS_G4X(dev))
2504                 g4x_update_wm(dev);
2505         else if (IS_I965G(dev))
2506                 i965_update_wm(dev);
2507         else if (IS_I9XX(dev) || IS_MOBILE(dev))
2508                 i9xx_update_wm(dev, planea_clock, planeb_clock, sr_hdisplay,
2509                                pixel_size);
2510         else
2511                 i830_update_wm(dev, planea_clock, pixel_size);
2512 }
2513
2514 static int intel_crtc_mode_set(struct drm_crtc *crtc,
2515                                struct drm_display_mode *mode,
2516                                struct drm_display_mode *adjusted_mode,
2517                                int x, int y,
2518                                struct drm_framebuffer *old_fb)
2519 {
2520         struct drm_device *dev = crtc->dev;
2521         struct drm_i915_private *dev_priv = dev->dev_private;
2522         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2523         int pipe = intel_crtc->pipe;
2524         int plane = intel_crtc->plane;
2525         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
2526         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2527         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
2528         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2529         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2530         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
2531         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
2532         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
2533         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
2534         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
2535         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
2536         int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
2537         int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
2538         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
2539         int refclk, num_outputs = 0;
2540         intel_clock_t clock, reduced_clock;
2541         u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
2542         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
2543         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
2544         bool is_edp = false;
2545         struct drm_mode_config *mode_config = &dev->mode_config;
2546         struct drm_connector *connector;
2547         const intel_limit_t *limit;
2548         int ret;
2549         struct fdi_m_n m_n = {0};
2550         int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
2551         int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
2552         int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
2553         int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
2554         int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
2555         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
2556         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
2557         int lvds_reg = LVDS;
2558         u32 temp;
2559         int sdvo_pixel_multiply;
2560         int target_clock;
2561
2562         drm_vblank_pre_modeset(dev, pipe);
2563
2564         list_for_each_entry(connector, &mode_config->connector_list, head) {
2565                 struct intel_output *intel_output = to_intel_output(connector);
2566
2567                 if (!connector->encoder || connector->encoder->crtc != crtc)
2568                         continue;
2569
2570                 switch (intel_output->type) {
2571                 case INTEL_OUTPUT_LVDS:
2572                         is_lvds = true;
2573                         break;
2574                 case INTEL_OUTPUT_SDVO:
2575                 case INTEL_OUTPUT_HDMI:
2576                         is_sdvo = true;
2577                         if (intel_output->needs_tv_clock)
2578                                 is_tv = true;
2579                         break;
2580                 case INTEL_OUTPUT_DVO:
2581                         is_dvo = true;
2582                         break;
2583                 case INTEL_OUTPUT_TVOUT:
2584                         is_tv = true;
2585                         break;
2586                 case INTEL_OUTPUT_ANALOG:
2587                         is_crt = true;
2588                         break;
2589                 case INTEL_OUTPUT_DISPLAYPORT:
2590                         is_dp = true;
2591                         break;
2592                 case INTEL_OUTPUT_EDP:
2593                         is_edp = true;
2594                         break;
2595                 }
2596
2597                 num_outputs++;
2598         }
2599
2600         if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
2601                 refclk = dev_priv->lvds_ssc_freq * 1000;
2602                 DRM_DEBUG("using SSC reference clock of %d MHz\n", refclk / 1000);
2603         } else if (IS_I9XX(dev)) {
2604                 refclk = 96000;
2605                 if (IS_IGDNG(dev))
2606                         refclk = 120000; /* 120Mhz refclk */
2607         } else {
2608                 refclk = 48000;
2609         }
2610
2611
2612         /*
2613          * Returns a set of divisors for the desired target clock with the given
2614          * refclk, or FALSE.  The returned values represent the clock equation:
2615          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
2616          */
2617         limit = intel_limit(crtc);
2618         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
2619         if (!ok) {
2620                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
2621                 drm_vblank_post_modeset(dev, pipe);
2622                 return -EINVAL;
2623         }
2624
2625         if (limit->find_reduced_pll && dev_priv->lvds_downclock_avail) {
2626                 memcpy(&reduced_clock, &clock, sizeof(intel_clock_t));
2627                 has_reduced_clock = limit->find_reduced_pll(limit, crtc,
2628                                                             (adjusted_mode->clock*3/4),
2629                                                             refclk,
2630                                                             &reduced_clock);
2631         }
2632
2633         /* SDVO TV has fixed PLL values depend on its clock range,
2634            this mirrors vbios setting. */
2635         if (is_sdvo && is_tv) {
2636                 if (adjusted_mode->clock >= 100000
2637                                 && adjusted_mode->clock < 140500) {
2638                         clock.p1 = 2;
2639                         clock.p2 = 10;
2640                         clock.n = 3;
2641                         clock.m1 = 16;
2642                         clock.m2 = 8;
2643                 } else if (adjusted_mode->clock >= 140500
2644                                 && adjusted_mode->clock <= 200000) {
2645                         clock.p1 = 1;
2646                         clock.p2 = 10;
2647                         clock.n = 6;
2648                         clock.m1 = 12;
2649                         clock.m2 = 8;
2650                 }
2651         }
2652
2653         /* FDI link */
2654         if (IS_IGDNG(dev)) {
2655                 int lane, link_bw;
2656                 /* eDP doesn't require FDI link, so just set DP M/N
2657                    according to current link config */
2658                 if (is_edp) {
2659                         struct drm_connector *edp;
2660                         target_clock = mode->clock;
2661                         edp = intel_pipe_get_output(crtc);
2662                         intel_edp_link_config(to_intel_output(edp),
2663                                         &lane, &link_bw);
2664                 } else {
2665                         /* DP over FDI requires target mode clock
2666                            instead of link clock */
2667                         if (is_dp)
2668                                 target_clock = mode->clock;
2669                         else
2670                                 target_clock = adjusted_mode->clock;
2671                         lane = 4;
2672                         link_bw = 270000;
2673                 }
2674                 igdng_compute_m_n(3, lane, target_clock,
2675                                   link_bw, &m_n);
2676         }
2677
2678         if (IS_IGD(dev)) {
2679                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
2680                 if (has_reduced_clock)
2681                         fp2 = (1 << reduced_clock.n) << 16 |
2682                                 reduced_clock.m1 << 8 | reduced_clock.m2;
2683         } else {
2684                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
2685                 if (has_reduced_clock)
2686                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
2687                                 reduced_clock.m2;
2688         }
2689
2690         if (!IS_IGDNG(dev))
2691                 dpll = DPLL_VGA_MODE_DIS;
2692
2693         if (IS_I9XX(dev)) {
2694                 if (is_lvds)
2695                         dpll |= DPLLB_MODE_LVDS;
2696                 else
2697                         dpll |= DPLLB_MODE_DAC_SERIAL;
2698                 if (is_sdvo) {
2699                         dpll |= DPLL_DVO_HIGH_SPEED;
2700                         sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
2701                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
2702                                 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
2703                         else if (IS_IGDNG(dev))
2704                                 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
2705                 }
2706                 if (is_dp)
2707                         dpll |= DPLL_DVO_HIGH_SPEED;
2708
2709                 /* compute bitmask from p1 value */
2710                 if (IS_IGD(dev))
2711                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD;
2712                 else {
2713                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2714                         /* also FPA1 */
2715                         if (IS_IGDNG(dev))
2716                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2717                         if (IS_G4X(dev) && has_reduced_clock)
2718                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2719                 }
2720                 switch (clock.p2) {
2721                 case 5:
2722                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
2723                         break;
2724                 case 7:
2725                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
2726                         break;
2727                 case 10:
2728                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
2729                         break;
2730                 case 14:
2731                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
2732                         break;
2733                 }
2734                 if (IS_I965G(dev) && !IS_IGDNG(dev))
2735                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
2736         } else {
2737                 if (is_lvds) {
2738                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2739                 } else {
2740                         if (clock.p1 == 2)
2741                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
2742                         else
2743                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2744                         if (clock.p2 == 4)
2745                                 dpll |= PLL_P2_DIVIDE_BY_4;
2746                 }
2747         }
2748
2749         if (is_sdvo && is_tv)
2750                 dpll |= PLL_REF_INPUT_TVCLKINBC;
2751         else if (is_tv)
2752                 /* XXX: just matching BIOS for now */
2753                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
2754                 dpll |= 3;
2755         else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
2756                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
2757         else
2758                 dpll |= PLL_REF_INPUT_DREFCLK;
2759
2760         /* setup pipeconf */
2761         pipeconf = I915_READ(pipeconf_reg);
2762
2763         /* Set up the display plane register */
2764         dspcntr = DISPPLANE_GAMMA_ENABLE;
2765
2766         /* IGDNG's plane is forced to pipe, bit 24 is to
2767            enable color space conversion */
2768         if (!IS_IGDNG(dev)) {
2769                 if (pipe == 0)
2770                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
2771                 else
2772                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2773         }
2774
2775         if (pipe == 0 && !IS_I965G(dev)) {
2776                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
2777                  * core speed.
2778                  *
2779                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
2780                  * pipe == 0 check?
2781                  */
2782                 if (mode->clock > intel_get_core_clock_speed(dev) * 9 / 10)
2783                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
2784                 else
2785                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
2786         }
2787
2788         dspcntr |= DISPLAY_PLANE_ENABLE;
2789         pipeconf |= PIPEACONF_ENABLE;
2790         dpll |= DPLL_VCO_ENABLE;
2791
2792
2793         /* Disable the panel fitter if it was on our pipe */
2794         if (!IS_IGDNG(dev) && intel_panel_fitter_pipe(dev) == pipe)
2795                 I915_WRITE(PFIT_CONTROL, 0);
2796
2797         DRM_DEBUG("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
2798         drm_mode_debug_printmodeline(mode);
2799
2800         /* assign to IGDNG registers */
2801         if (IS_IGDNG(dev)) {
2802                 fp_reg = pch_fp_reg;
2803                 dpll_reg = pch_dpll_reg;
2804         }
2805
2806         if (is_edp) {
2807                 igdng_disable_pll_edp(crtc);
2808         } else if ((dpll & DPLL_VCO_ENABLE)) {
2809                 I915_WRITE(fp_reg, fp);
2810                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
2811                 I915_READ(dpll_reg);
2812                 udelay(150);
2813         }
2814
2815         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
2816          * This is an exception to the general rule that mode_set doesn't turn
2817          * things on.
2818          */
2819         if (is_lvds) {
2820                 u32 lvds;
2821
2822                 if (IS_IGDNG(dev))
2823                         lvds_reg = PCH_LVDS;
2824
2825                 lvds = I915_READ(lvds_reg);
2826                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
2827                 /* Set the B0-B3 data pairs corresponding to whether we're going to
2828                  * set the DPLLs for dual-channel mode or not.
2829                  */
2830                 if (clock.p2 == 7)
2831                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
2832                 else
2833                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
2834
2835                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
2836                  * appropriately here, but we need to look more thoroughly into how
2837                  * panels behave in the two modes.
2838                  */
2839
2840                 I915_WRITE(lvds_reg, lvds);
2841                 I915_READ(lvds_reg);
2842         }
2843         if (is_dp)
2844                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
2845
2846         if (!is_edp) {
2847                 I915_WRITE(fp_reg, fp);
2848                 I915_WRITE(dpll_reg, dpll);
2849                 I915_READ(dpll_reg);
2850                 /* Wait for the clocks to stabilize. */
2851                 udelay(150);
2852
2853                 if (IS_I965G(dev) && !IS_IGDNG(dev)) {
2854                         if (is_sdvo) {
2855                                 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
2856                                 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
2857                                         ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
2858                         } else
2859                                 I915_WRITE(dpll_md_reg, 0);
2860                 } else {
2861                         /* write it again -- the BIOS does, after all */
2862                         I915_WRITE(dpll_reg, dpll);
2863                 }
2864                 I915_READ(dpll_reg);
2865                 /* Wait for the clocks to stabilize. */
2866                 udelay(150);
2867         }
2868
2869         if (is_lvds && has_reduced_clock && i915_powersave) {
2870                 I915_WRITE(fp_reg + 4, fp2);
2871                 intel_crtc->lowfreq_avail = true;
2872                 if (HAS_PIPE_CXSR(dev)) {
2873                         DRM_DEBUG("enabling CxSR downclocking\n");
2874                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
2875                 }
2876         } else {
2877                 I915_WRITE(fp_reg + 4, fp);
2878                 intel_crtc->lowfreq_avail = false;
2879                 if (HAS_PIPE_CXSR(dev)) {
2880                         DRM_DEBUG("disabling CxSR downclocking\n");
2881                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
2882                 }
2883         }
2884
2885         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
2886                    ((adjusted_mode->crtc_htotal - 1) << 16));
2887         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
2888                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
2889         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
2890                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
2891         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
2892                    ((adjusted_mode->crtc_vtotal - 1) << 16));
2893         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
2894                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
2895         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
2896                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
2897         /* pipesrc and dspsize control the size that is scaled from, which should
2898          * always be the user's requested size.
2899          */
2900         if (!IS_IGDNG(dev)) {
2901                 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
2902                                 (mode->hdisplay - 1));
2903                 I915_WRITE(dsppos_reg, 0);
2904         }
2905         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2906
2907         if (IS_IGDNG(dev)) {
2908                 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
2909                 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
2910                 I915_WRITE(link_m1_reg, m_n.link_m);
2911                 I915_WRITE(link_n1_reg, m_n.link_n);
2912
2913                 if (is_edp) {
2914                         igdng_set_pll_edp(crtc, adjusted_mode->clock);
2915                 } else {
2916                         /* enable FDI RX PLL too */
2917                         temp = I915_READ(fdi_rx_reg);
2918                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
2919                         udelay(200);
2920                 }
2921         }
2922
2923         I915_WRITE(pipeconf_reg, pipeconf);
2924         I915_READ(pipeconf_reg);
2925
2926         intel_wait_for_vblank(dev);
2927
2928         if (IS_IGDNG(dev)) {
2929                 /* enable address swizzle for tiling buffer */
2930                 temp = I915_READ(DISP_ARB_CTL);
2931                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
2932         }
2933
2934         I915_WRITE(dspcntr_reg, dspcntr);
2935
2936         /* Flush the plane changes */
2937         ret = intel_pipe_set_base(crtc, x, y, old_fb);
2938
2939         if (I915_HAS_FBC(dev) && (IS_I965G(dev) || plane == 0))
2940                 intel_update_fbc(crtc, &crtc->mode);
2941         intel_update_watermarks(dev);
2942
2943         drm_vblank_post_modeset(dev, pipe);
2944
2945         return ret;
2946 }
2947
2948 /** Loads the palette/gamma unit for the CRTC with the prepared values */
2949 void intel_crtc_load_lut(struct drm_crtc *crtc)
2950 {
2951         struct drm_device *dev = crtc->dev;
2952         struct drm_i915_private *dev_priv = dev->dev_private;
2953         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2954         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
2955         int i;
2956
2957         /* The clocks have to be on to load the palette. */
2958         if (!crtc->enabled)
2959                 return;
2960
2961         /* use legacy palette for IGDNG */
2962         if (IS_IGDNG(dev))
2963                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
2964                                                    LGC_PALETTE_B;
2965
2966         for (i = 0; i < 256; i++) {
2967                 I915_WRITE(palreg + 4 * i,
2968                            (intel_crtc->lut_r[i] << 16) |
2969                            (intel_crtc->lut_g[i] << 8) |
2970                            intel_crtc->lut_b[i]);
2971         }
2972 }
2973
2974 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
2975                                  struct drm_file *file_priv,
2976                                  uint32_t handle,
2977                                  uint32_t width, uint32_t height)
2978 {
2979         struct drm_device *dev = crtc->dev;
2980         struct drm_i915_private *dev_priv = dev->dev_private;
2981         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2982         struct drm_gem_object *bo;
2983         struct drm_i915_gem_object *obj_priv;
2984         int pipe = intel_crtc->pipe;
2985         int plane = intel_crtc->plane;
2986         uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
2987         uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
2988         uint32_t temp = I915_READ(control);
2989         size_t addr;
2990         int ret;
2991
2992         DRM_DEBUG("\n");
2993
2994         /* if we want to turn off the cursor ignore width and height */
2995         if (!handle) {
2996                 DRM_DEBUG("cursor off\n");
2997                 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
2998                         temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
2999                         temp |= CURSOR_MODE_DISABLE;
3000                 } else {
3001                         temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
3002                 }
3003                 addr = 0;
3004                 bo = NULL;
3005                 mutex_lock(&dev->struct_mutex);
3006                 goto finish;
3007         }
3008
3009         /* Currently we only support 64x64 cursors */
3010         if (width != 64 || height != 64) {
3011                 DRM_ERROR("we currently only support 64x64 cursors\n");
3012                 return -EINVAL;
3013         }
3014
3015         bo = drm_gem_object_lookup(dev, file_priv, handle);
3016         if (!bo)
3017                 return -ENOENT;
3018
3019         obj_priv = bo->driver_private;
3020
3021         if (bo->size < width * height * 4) {
3022                 DRM_ERROR("buffer is to small\n");
3023                 ret = -ENOMEM;
3024                 goto fail;
3025         }
3026
3027         /* we only need to pin inside GTT if cursor is non-phy */
3028         mutex_lock(&dev->struct_mutex);
3029         if (!dev_priv->cursor_needs_physical) {
3030                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
3031                 if (ret) {
3032                         DRM_ERROR("failed to pin cursor bo\n");
3033                         goto fail_locked;
3034                 }
3035                 addr = obj_priv->gtt_offset;
3036         } else {
3037                 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
3038                 if (ret) {
3039                         DRM_ERROR("failed to attach phys object\n");
3040                         goto fail_locked;
3041                 }
3042                 addr = obj_priv->phys_obj->handle->busaddr;
3043         }
3044
3045         if (!IS_I9XX(dev))
3046                 I915_WRITE(CURSIZE, (height << 12) | width);
3047
3048         /* Hooray for CUR*CNTR differences */
3049         if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3050                 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
3051                 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
3052                 temp |= (pipe << 28); /* Connect to correct pipe */
3053         } else {
3054                 temp &= ~(CURSOR_FORMAT_MASK);
3055                 temp |= CURSOR_ENABLE;
3056                 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
3057         }
3058
3059  finish:
3060         I915_WRITE(control, temp);
3061         I915_WRITE(base, addr);
3062
3063         if (intel_crtc->cursor_bo) {
3064                 if (dev_priv->cursor_needs_physical) {
3065                         if (intel_crtc->cursor_bo != bo)
3066                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
3067                 } else
3068                         i915_gem_object_unpin(intel_crtc->cursor_bo);
3069                 drm_gem_object_unreference(intel_crtc->cursor_bo);
3070         }
3071
3072         if (I915_HAS_FBC(dev) && (IS_I965G(dev) || plane == 0))
3073                 intel_update_fbc(crtc, &crtc->mode);
3074
3075         mutex_unlock(&dev->struct_mutex);
3076
3077         intel_crtc->cursor_addr = addr;
3078         intel_crtc->cursor_bo = bo;
3079
3080         return 0;
3081 fail:
3082         mutex_lock(&dev->struct_mutex);
3083 fail_locked:
3084         drm_gem_object_unreference(bo);
3085         mutex_unlock(&dev->struct_mutex);
3086         return ret;
3087 }
3088
3089 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
3090 {
3091         struct drm_device *dev = crtc->dev;
3092         struct drm_i915_private *dev_priv = dev->dev_private;
3093         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3094         struct intel_framebuffer *intel_fb;
3095         int pipe = intel_crtc->pipe;
3096         uint32_t temp = 0;
3097         uint32_t adder;
3098
3099         if (crtc->fb) {
3100                 intel_fb = to_intel_framebuffer(crtc->fb);
3101                 intel_mark_busy(dev, intel_fb->obj);
3102         }
3103
3104         if (x < 0) {
3105                 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
3106                 x = -x;
3107         }
3108         if (y < 0) {
3109                 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
3110                 y = -y;
3111         }
3112
3113         temp |= x << CURSOR_X_SHIFT;
3114         temp |= y << CURSOR_Y_SHIFT;
3115
3116         adder = intel_crtc->cursor_addr;
3117         I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
3118         I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
3119
3120         return 0;
3121 }
3122
3123 /** Sets the color ramps on behalf of RandR */
3124 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
3125                                  u16 blue, int regno)
3126 {
3127         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3128
3129         intel_crtc->lut_r[regno] = red >> 8;
3130         intel_crtc->lut_g[regno] = green >> 8;
3131         intel_crtc->lut_b[regno] = blue >> 8;
3132 }
3133
3134 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
3135                                  u16 *blue, uint32_t size)
3136 {
3137         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3138         int i;
3139
3140         if (size != 256)
3141                 return;
3142
3143         for (i = 0; i < 256; i++) {
3144                 intel_crtc->lut_r[i] = red[i] >> 8;
3145                 intel_crtc->lut_g[i] = green[i] >> 8;
3146                 intel_crtc->lut_b[i] = blue[i] >> 8;
3147         }
3148
3149         intel_crtc_load_lut(crtc);
3150 }
3151
3152 /**
3153  * Get a pipe with a simple mode set on it for doing load-based monitor
3154  * detection.
3155  *
3156  * It will be up to the load-detect code to adjust the pipe as appropriate for
3157  * its requirements.  The pipe will be connected to no other outputs.
3158  *
3159  * Currently this code will only succeed if there is a pipe with no outputs
3160  * configured for it.  In the future, it could choose to temporarily disable
3161  * some outputs to free up a pipe for its use.
3162  *
3163  * \return crtc, or NULL if no pipes are available.
3164  */
3165
3166 /* VESA 640x480x72Hz mode to set on the pipe */
3167 static struct drm_display_mode load_detect_mode = {
3168         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
3169                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
3170 };
3171
3172 struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
3173                                             struct drm_display_mode *mode,
3174                                             int *dpms_mode)
3175 {
3176         struct intel_crtc *intel_crtc;
3177         struct drm_crtc *possible_crtc;
3178         struct drm_crtc *supported_crtc =NULL;
3179         struct drm_encoder *encoder = &intel_output->enc;
3180         struct drm_crtc *crtc = NULL;
3181         struct drm_device *dev = encoder->dev;
3182         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3183         struct drm_crtc_helper_funcs *crtc_funcs;
3184         int i = -1;
3185
3186         /*
3187          * Algorithm gets a little messy:
3188          *   - if the connector already has an assigned crtc, use it (but make
3189          *     sure it's on first)
3190          *   - try to find the first unused crtc that can drive this connector,
3191          *     and use that if we find one
3192          *   - if there are no unused crtcs available, try to use the first
3193          *     one we found that supports the connector
3194          */
3195
3196         /* See if we already have a CRTC for this connector */
3197         if (encoder->crtc) {
3198                 crtc = encoder->crtc;
3199                 /* Make sure the crtc and connector are running */
3200                 intel_crtc = to_intel_crtc(crtc);
3201                 *dpms_mode = intel_crtc->dpms_mode;
3202                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3203                         crtc_funcs = crtc->helper_private;
3204                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3205                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3206                 }
3207                 return crtc;
3208         }
3209
3210         /* Find an unused one (if possible) */
3211         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
3212                 i++;
3213                 if (!(encoder->possible_crtcs & (1 << i)))
3214                         continue;
3215                 if (!possible_crtc->enabled) {
3216                         crtc = possible_crtc;
3217                         break;
3218                 }
3219                 if (!supported_crtc)
3220                         supported_crtc = possible_crtc;
3221         }
3222
3223         /*
3224          * If we didn't find an unused CRTC, don't use any.
3225          */
3226         if (!crtc) {
3227                 return NULL;
3228         }
3229
3230         encoder->crtc = crtc;
3231         intel_output->base.encoder = encoder;
3232         intel_output->load_detect_temp = true;
3233
3234         intel_crtc = to_intel_crtc(crtc);
3235         *dpms_mode = intel_crtc->dpms_mode;
3236
3237         if (!crtc->enabled) {
3238                 if (!mode)
3239                         mode = &load_detect_mode;
3240                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
3241         } else {
3242                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3243                         crtc_funcs = crtc->helper_private;
3244                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3245                 }
3246
3247                 /* Add this connector to the crtc */
3248                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
3249                 encoder_funcs->commit(encoder);
3250         }
3251         /* let the connector get through one full cycle before testing */
3252         intel_wait_for_vblank(dev);
3253
3254         return crtc;
3255 }
3256
3257 void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
3258 {
3259         struct drm_encoder *encoder = &intel_output->enc;
3260         struct drm_device *dev = encoder->dev;
3261         struct drm_crtc *crtc = encoder->crtc;
3262         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3263         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3264
3265         if (intel_output->load_detect_temp) {
3266                 encoder->crtc = NULL;
3267                 intel_output->base.encoder = NULL;
3268                 intel_output->load_detect_temp = false;
3269                 crtc->enabled = drm_helper_crtc_in_use(crtc);
3270                 drm_helper_disable_unused_functions(dev);
3271         }
3272
3273         /* Switch crtc and output back off if necessary */
3274         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
3275                 if (encoder->crtc == crtc)
3276                         encoder_funcs->dpms(encoder, dpms_mode);
3277                 crtc_funcs->dpms(crtc, dpms_mode);
3278         }
3279 }
3280
3281 /* Returns the clock of the currently programmed mode of the given pipe. */
3282 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
3283 {
3284         struct drm_i915_private *dev_priv = dev->dev_private;
3285         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3286         int pipe = intel_crtc->pipe;
3287         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
3288         u32 fp;
3289         intel_clock_t clock;
3290
3291         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
3292                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
3293         else
3294                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
3295
3296         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
3297         if (IS_IGD(dev)) {
3298                 clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
3299                 clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT;
3300         } else {
3301                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
3302                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
3303         }
3304
3305         if (IS_I9XX(dev)) {
3306                 if (IS_IGD(dev))
3307                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>
3308                                 DPLL_FPA01_P1_POST_DIV_SHIFT_IGD);
3309                 else
3310                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
3311                                DPLL_FPA01_P1_POST_DIV_SHIFT);
3312
3313                 switch (dpll & DPLL_MODE_MASK) {
3314                 case DPLLB_MODE_DAC_SERIAL:
3315                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
3316                                 5 : 10;
3317                         break;
3318                 case DPLLB_MODE_LVDS:
3319                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
3320                                 7 : 14;
3321                         break;
3322                 default:
3323                         DRM_DEBUG("Unknown DPLL mode %08x in programmed "
3324                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
3325                         return 0;
3326                 }
3327
3328                 /* XXX: Handle the 100Mhz refclk */
3329                 intel_clock(dev, 96000, &clock);
3330         } else {
3331                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
3332
3333                 if (is_lvds) {
3334                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
3335                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
3336                         clock.p2 = 14;
3337
3338                         if ((dpll & PLL_REF_INPUT_MASK) ==
3339                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
3340                                 /* XXX: might not be 66MHz */
3341                                 intel_clock(dev, 66000, &clock);
3342                         } else
3343                                 intel_clock(dev, 48000, &clock);
3344                 } else {
3345                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
3346                                 clock.p1 = 2;
3347                         else {
3348                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
3349                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
3350                         }
3351                         if (dpll & PLL_P2_DIVIDE_BY_4)
3352                                 clock.p2 = 4;
3353                         else
3354                                 clock.p2 = 2;
3355
3356                         intel_clock(dev, 48000, &clock);
3357                 }
3358         }
3359
3360         /* XXX: It would be nice to validate the clocks, but we can't reuse
3361          * i830PllIsValid() because it relies on the xf86_config connector
3362          * configuration being accurate, which it isn't necessarily.
3363          */
3364
3365         return clock.dot;
3366 }
3367
3368 /** Returns the currently programmed mode of the given pipe. */
3369 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
3370                                              struct drm_crtc *crtc)
3371 {
3372         struct drm_i915_private *dev_priv = dev->dev_private;
3373         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3374         int pipe = intel_crtc->pipe;
3375         struct drm_display_mode *mode;
3376         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
3377         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
3378         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
3379         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
3380
3381         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
3382         if (!mode)
3383                 return NULL;
3384
3385         mode->clock = intel_crtc_clock_get(dev, crtc);
3386         mode->hdisplay = (htot & 0xffff) + 1;
3387         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
3388         mode->hsync_start = (hsync & 0xffff) + 1;
3389         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
3390         mode->vdisplay = (vtot & 0xffff) + 1;
3391         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
3392         mode->vsync_start = (vsync & 0xffff) + 1;
3393         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
3394
3395         drm_mode_set_name(mode);
3396         drm_mode_set_crtcinfo(mode, 0);
3397
3398         return mode;
3399 }
3400
3401 #define GPU_IDLE_TIMEOUT 500 /* ms */
3402
3403 /* When this timer fires, we've been idle for awhile */
3404 static void intel_gpu_idle_timer(unsigned long arg)
3405 {
3406         struct drm_device *dev = (struct drm_device *)arg;
3407         drm_i915_private_t *dev_priv = dev->dev_private;
3408
3409         DRM_DEBUG("idle timer fired, downclocking\n");
3410
3411         dev_priv->busy = false;
3412
3413         queue_work(dev_priv->wq, &dev_priv->idle_work);
3414 }
3415
3416 void intel_increase_renderclock(struct drm_device *dev, bool schedule)
3417 {
3418         drm_i915_private_t *dev_priv = dev->dev_private;
3419
3420         if (IS_IGDNG(dev))
3421                 return;
3422
3423         if (!dev_priv->render_reclock_avail) {
3424                 DRM_DEBUG("not reclocking render clock\n");
3425                 return;
3426         }
3427
3428         /* Restore render clock frequency to original value */
3429         if (IS_G4X(dev) || IS_I9XX(dev))
3430                 pci_write_config_word(dev->pdev, GCFGC, dev_priv->orig_clock);
3431         else if (IS_I85X(dev))
3432                 pci_write_config_word(dev->pdev, HPLLCC, dev_priv->orig_clock);
3433         DRM_DEBUG("increasing render clock frequency\n");
3434
3435         /* Schedule downclock */
3436         if (schedule)
3437                 mod_timer(&dev_priv->idle_timer, jiffies +
3438                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
3439 }
3440
3441 void intel_decrease_renderclock(struct drm_device *dev)
3442 {
3443         drm_i915_private_t *dev_priv = dev->dev_private;
3444
3445         if (IS_IGDNG(dev))
3446                 return;
3447
3448         if (!dev_priv->render_reclock_avail) {
3449                 DRM_DEBUG("not reclocking render clock\n");
3450                 return;
3451         }
3452
3453         if (IS_G4X(dev)) {
3454                 u16 gcfgc;
3455
3456                 /* Adjust render clock... */
3457                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3458
3459                 /* Down to minimum... */
3460                 gcfgc &= ~GM45_GC_RENDER_CLOCK_MASK;
3461                 gcfgc |= GM45_GC_RENDER_CLOCK_266_MHZ;
3462
3463                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3464         } else if (IS_I965G(dev)) {
3465                 u16 gcfgc;
3466
3467                 /* Adjust render clock... */
3468                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3469
3470                 /* Down to minimum... */
3471                 gcfgc &= ~I965_GC_RENDER_CLOCK_MASK;
3472                 gcfgc |= I965_GC_RENDER_CLOCK_267_MHZ;
3473
3474                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3475         } else if (IS_I945G(dev) || IS_I945GM(dev)) {
3476                 u16 gcfgc;
3477
3478                 /* Adjust render clock... */
3479                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3480
3481                 /* Down to minimum... */
3482                 gcfgc &= ~I945_GC_RENDER_CLOCK_MASK;
3483                 gcfgc |= I945_GC_RENDER_CLOCK_166_MHZ;
3484
3485                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3486         } else if (IS_I915G(dev)) {
3487                 u16 gcfgc;
3488
3489                 /* Adjust render clock... */
3490                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3491
3492                 /* Down to minimum... */
3493                 gcfgc &= ~I915_GC_RENDER_CLOCK_MASK;
3494                 gcfgc |= I915_GC_RENDER_CLOCK_166_MHZ;
3495
3496                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3497         } else if (IS_I85X(dev)) {
3498                 u16 hpllcc;
3499
3500                 /* Adjust render clock... */
3501                 pci_read_config_word(dev->pdev, HPLLCC, &hpllcc);
3502
3503                 /* Up to maximum... */
3504                 hpllcc &= ~GC_CLOCK_CONTROL_MASK;
3505                 hpllcc |= GC_CLOCK_133_200;
3506
3507                 pci_write_config_word(dev->pdev, HPLLCC, hpllcc);
3508         }
3509         DRM_DEBUG("decreasing render clock frequency\n");
3510 }
3511
3512 /* Note that no increase function is needed for this - increase_renderclock()
3513  *  will also rewrite these bits
3514  */
3515 void intel_decrease_displayclock(struct drm_device *dev)
3516 {
3517         if (IS_IGDNG(dev))
3518                 return;
3519
3520         if (IS_I945G(dev) || IS_I945GM(dev) || IS_I915G(dev) ||
3521             IS_I915GM(dev)) {
3522                 u16 gcfgc;
3523
3524                 /* Adjust render clock... */
3525                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3526
3527                 /* Down to minimum... */
3528                 gcfgc &= ~0xf0;
3529                 gcfgc |= 0x80;
3530
3531                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3532         }
3533 }
3534
3535 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
3536
3537 static void intel_crtc_idle_timer(unsigned long arg)
3538 {
3539         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
3540         struct drm_crtc *crtc = &intel_crtc->base;
3541         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
3542
3543         DRM_DEBUG("idle timer fired, downclocking\n");
3544
3545         intel_crtc->busy = false;
3546
3547         queue_work(dev_priv->wq, &dev_priv->idle_work);
3548 }
3549
3550 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
3551 {
3552         struct drm_device *dev = crtc->dev;
3553         drm_i915_private_t *dev_priv = dev->dev_private;
3554         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3555         int pipe = intel_crtc->pipe;
3556         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3557         int dpll = I915_READ(dpll_reg);
3558
3559         if (IS_IGDNG(dev))
3560                 return;
3561
3562         if (!dev_priv->lvds_downclock_avail)
3563                 return;
3564
3565         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
3566                 DRM_DEBUG("upclocking LVDS\n");
3567
3568                 /* Unlock panel regs */
3569                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3570
3571                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
3572                 I915_WRITE(dpll_reg, dpll);
3573                 dpll = I915_READ(dpll_reg);
3574                 intel_wait_for_vblank(dev);
3575                 dpll = I915_READ(dpll_reg);
3576                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
3577                         DRM_DEBUG("failed to upclock LVDS!\n");
3578
3579                 /* ...and lock them again */
3580                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3581         }
3582
3583         /* Schedule downclock */
3584         if (schedule)
3585                 mod_timer(&intel_crtc->idle_timer, jiffies +
3586                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3587 }
3588
3589 static void intel_decrease_pllclock(struct drm_crtc *crtc)
3590 {
3591         struct drm_device *dev = crtc->dev;
3592         drm_i915_private_t *dev_priv = dev->dev_private;
3593         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3594         int pipe = intel_crtc->pipe;
3595         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3596         int dpll = I915_READ(dpll_reg);
3597
3598         if (IS_IGDNG(dev))
3599                 return;
3600
3601         if (!dev_priv->lvds_downclock_avail)
3602                 return;
3603
3604         /*
3605          * Since this is called by a timer, we should never get here in
3606          * the manual case.
3607          */
3608         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
3609                 DRM_DEBUG("downclocking LVDS\n");
3610
3611                 /* Unlock panel regs */
3612                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3613
3614                 dpll |= DISPLAY_RATE_SELECT_FPA1;
3615                 I915_WRITE(dpll_reg, dpll);
3616                 dpll = I915_READ(dpll_reg);
3617                 intel_wait_for_vblank(dev);
3618                 dpll = I915_READ(dpll_reg);
3619                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
3620                         DRM_DEBUG("failed to downclock LVDS!\n");
3621
3622                 /* ...and lock them again */
3623                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3624         }
3625
3626 }
3627
3628 /**
3629  * intel_idle_update - adjust clocks for idleness
3630  * @work: work struct
3631  *
3632  * Either the GPU or display (or both) went idle.  Check the busy status
3633  * here and adjust the CRTC and GPU clocks as necessary.
3634  */
3635 static void intel_idle_update(struct work_struct *work)
3636 {
3637         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
3638                                                     idle_work);
3639         struct drm_device *dev = dev_priv->dev;
3640         struct drm_crtc *crtc;
3641         struct intel_crtc *intel_crtc;
3642
3643         if (!i915_powersave)
3644                 return;
3645
3646         mutex_lock(&dev->struct_mutex);
3647
3648         /* GPU isn't processing, downclock it. */
3649         if (!dev_priv->busy) {
3650                 intel_decrease_renderclock(dev);
3651                 intel_decrease_displayclock(dev);
3652         }
3653
3654         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3655                 /* Skip inactive CRTCs */
3656                 if (!crtc->fb)
3657                         continue;
3658
3659                 intel_crtc = to_intel_crtc(crtc);
3660                 if (!intel_crtc->busy)
3661                         intel_decrease_pllclock(crtc);
3662         }
3663
3664         mutex_unlock(&dev->struct_mutex);
3665 }
3666
3667 /**
3668  * intel_mark_busy - mark the GPU and possibly the display busy
3669  * @dev: drm device
3670  * @obj: object we're operating on
3671  *
3672  * Callers can use this function to indicate that the GPU is busy processing
3673  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
3674  * buffer), we'll also mark the display as busy, so we know to increase its
3675  * clock frequency.
3676  */
3677 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
3678 {
3679         drm_i915_private_t *dev_priv = dev->dev_private;
3680         struct drm_crtc *crtc = NULL;
3681         struct intel_framebuffer *intel_fb;
3682         struct intel_crtc *intel_crtc;
3683
3684         if (!drm_core_check_feature(dev, DRIVER_MODESET))
3685                 return;
3686
3687         dev_priv->busy = true;
3688         intel_increase_renderclock(dev, true);
3689
3690         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3691                 if (!crtc->fb)
3692                         continue;
3693
3694                 intel_crtc = to_intel_crtc(crtc);
3695                 intel_fb = to_intel_framebuffer(crtc->fb);
3696                 if (intel_fb->obj == obj) {
3697                         if (!intel_crtc->busy) {
3698                                 /* Non-busy -> busy, upclock */
3699                                 intel_increase_pllclock(crtc, true);
3700                                 intel_crtc->busy = true;
3701                         } else {
3702                                 /* Busy -> busy, put off timer */
3703                                 mod_timer(&intel_crtc->idle_timer, jiffies +
3704                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3705                         }
3706                 }
3707         }
3708 }
3709
3710 static void intel_crtc_destroy(struct drm_crtc *crtc)
3711 {
3712         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3713
3714         drm_crtc_cleanup(crtc);
3715         kfree(intel_crtc);
3716 }
3717
3718 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
3719         .dpms = intel_crtc_dpms,
3720         .mode_fixup = intel_crtc_mode_fixup,
3721         .mode_set = intel_crtc_mode_set,
3722         .mode_set_base = intel_pipe_set_base,
3723         .prepare = intel_crtc_prepare,
3724         .commit = intel_crtc_commit,
3725 };
3726
3727 static const struct drm_crtc_funcs intel_crtc_funcs = {
3728         .cursor_set = intel_crtc_cursor_set,
3729         .cursor_move = intel_crtc_cursor_move,
3730         .gamma_set = intel_crtc_gamma_set,
3731         .set_config = drm_crtc_helper_set_config,
3732         .destroy = intel_crtc_destroy,
3733 };
3734
3735
3736 static void intel_crtc_init(struct drm_device *dev, int pipe)
3737 {
3738         struct intel_crtc *intel_crtc;
3739         int i;
3740
3741         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
3742         if (intel_crtc == NULL)
3743                 return;
3744
3745         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
3746
3747         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
3748         intel_crtc->pipe = pipe;
3749         intel_crtc->plane = pipe;
3750         for (i = 0; i < 256; i++) {
3751                 intel_crtc->lut_r[i] = i;
3752                 intel_crtc->lut_g[i] = i;
3753                 intel_crtc->lut_b[i] = i;
3754         }
3755
3756         /* Swap pipes & planes for FBC on pre-965 */
3757         intel_crtc->pipe = pipe;
3758         intel_crtc->plane = pipe;
3759         if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
3760                 DRM_DEBUG("swapping pipes & planes for FBC\n");
3761                 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
3762         }
3763
3764         intel_crtc->cursor_addr = 0;
3765         intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
3766         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
3767
3768         intel_crtc->busy = false;
3769
3770         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
3771                     (unsigned long)intel_crtc);
3772 }
3773
3774 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
3775                                 struct drm_file *file_priv)
3776 {
3777         drm_i915_private_t *dev_priv = dev->dev_private;
3778         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
3779         struct drm_mode_object *drmmode_obj;
3780         struct intel_crtc *crtc;
3781
3782         if (!dev_priv) {
3783                 DRM_ERROR("called with no initialization\n");
3784                 return -EINVAL;
3785         }
3786
3787         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
3788                         DRM_MODE_OBJECT_CRTC);
3789
3790         if (!drmmode_obj) {
3791                 DRM_ERROR("no such CRTC id\n");
3792                 return -EINVAL;
3793         }
3794
3795         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
3796         pipe_from_crtc_id->pipe = crtc->pipe;
3797
3798         return 0;
3799 }
3800
3801 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
3802 {
3803         struct drm_crtc *crtc = NULL;
3804
3805         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3806                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3807                 if (intel_crtc->pipe == pipe)
3808                         break;
3809         }
3810         return crtc;
3811 }
3812
3813 static int intel_connector_clones(struct drm_device *dev, int type_mask)
3814 {
3815         int index_mask = 0;
3816         struct drm_connector *connector;
3817         int entry = 0;
3818
3819         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3820                 struct intel_output *intel_output = to_intel_output(connector);
3821                 if (type_mask & intel_output->clone_mask)
3822                         index_mask |= (1 << entry);
3823                 entry++;
3824         }
3825         return index_mask;
3826 }
3827
3828
3829 static void intel_setup_outputs(struct drm_device *dev)
3830 {
3831         struct drm_i915_private *dev_priv = dev->dev_private;
3832         struct drm_connector *connector;
3833
3834         intel_crt_init(dev);
3835
3836         /* Set up integrated LVDS */
3837         if (IS_MOBILE(dev) && !IS_I830(dev))
3838                 intel_lvds_init(dev);
3839
3840         if (IS_IGDNG(dev)) {
3841                 int found;
3842
3843                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
3844                         intel_dp_init(dev, DP_A);
3845
3846                 if (I915_READ(HDMIB) & PORT_DETECTED) {
3847                         /* check SDVOB */
3848                         /* found = intel_sdvo_init(dev, HDMIB); */
3849                         found = 0;
3850                         if (!found)
3851                                 intel_hdmi_init(dev, HDMIB);
3852                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
3853                                 intel_dp_init(dev, PCH_DP_B);
3854                 }
3855
3856                 if (I915_READ(HDMIC) & PORT_DETECTED)
3857                         intel_hdmi_init(dev, HDMIC);
3858
3859                 if (I915_READ(HDMID) & PORT_DETECTED)
3860                         intel_hdmi_init(dev, HDMID);
3861
3862                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
3863                         intel_dp_init(dev, PCH_DP_C);
3864
3865                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
3866                         intel_dp_init(dev, PCH_DP_D);
3867
3868         } else if (IS_I9XX(dev)) {
3869                 bool found = false;
3870
3871                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
3872                         found = intel_sdvo_init(dev, SDVOB);
3873                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
3874                                 intel_hdmi_init(dev, SDVOB);
3875
3876                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
3877                                 intel_dp_init(dev, DP_B);
3878                 }
3879
3880                 /* Before G4X SDVOC doesn't have its own detect register */
3881
3882                 if (I915_READ(SDVOB) & SDVO_DETECTED)
3883                         found = intel_sdvo_init(dev, SDVOC);
3884
3885                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
3886
3887                         if (SUPPORTS_INTEGRATED_HDMI(dev))
3888                                 intel_hdmi_init(dev, SDVOC);
3889                         if (SUPPORTS_INTEGRATED_DP(dev))
3890                                 intel_dp_init(dev, DP_C);
3891                 }
3892
3893                 if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED))
3894                         intel_dp_init(dev, DP_D);
3895         } else
3896                 intel_dvo_init(dev);
3897
3898         if (IS_I9XX(dev) && IS_MOBILE(dev) && !IS_IGDNG(dev))
3899                 intel_tv_init(dev);
3900
3901         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3902                 struct intel_output *intel_output = to_intel_output(connector);
3903                 struct drm_encoder *encoder = &intel_output->enc;
3904
3905                 encoder->possible_crtcs = intel_output->crtc_mask;
3906                 encoder->possible_clones = intel_connector_clones(dev,
3907                                                 intel_output->clone_mask);
3908         }
3909 }
3910
3911 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
3912 {
3913         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3914         struct drm_device *dev = fb->dev;
3915
3916         if (fb->fbdev)
3917                 intelfb_remove(dev, fb);
3918
3919         drm_framebuffer_cleanup(fb);
3920         mutex_lock(&dev->struct_mutex);
3921         drm_gem_object_unreference(intel_fb->obj);
3922         mutex_unlock(&dev->struct_mutex);
3923
3924         kfree(intel_fb);
3925 }
3926
3927 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
3928                                                 struct drm_file *file_priv,
3929                                                 unsigned int *handle)
3930 {
3931         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3932         struct drm_gem_object *object = intel_fb->obj;
3933
3934         return drm_gem_handle_create(file_priv, object, handle);
3935 }
3936
3937 static const struct drm_framebuffer_funcs intel_fb_funcs = {
3938         .destroy = intel_user_framebuffer_destroy,
3939         .create_handle = intel_user_framebuffer_create_handle,
3940 };
3941
3942 int intel_framebuffer_create(struct drm_device *dev,
3943                              struct drm_mode_fb_cmd *mode_cmd,
3944                              struct drm_framebuffer **fb,
3945                              struct drm_gem_object *obj)
3946 {
3947         struct intel_framebuffer *intel_fb;
3948         int ret;
3949
3950         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
3951         if (!intel_fb)
3952                 return -ENOMEM;
3953
3954         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
3955         if (ret) {
3956                 DRM_ERROR("framebuffer init failed %d\n", ret);
3957                 return ret;
3958         }
3959
3960         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
3961
3962         intel_fb->obj = obj;
3963
3964         *fb = &intel_fb->base;
3965
3966         return 0;
3967 }
3968
3969
3970 static struct drm_framebuffer *
3971 intel_user_framebuffer_create(struct drm_device *dev,
3972                               struct drm_file *filp,
3973                               struct drm_mode_fb_cmd *mode_cmd)
3974 {
3975         struct drm_gem_object *obj;
3976         struct drm_framebuffer *fb;
3977         int ret;
3978
3979         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
3980         if (!obj)
3981                 return NULL;
3982
3983         ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
3984         if (ret) {
3985                 mutex_lock(&dev->struct_mutex);
3986                 drm_gem_object_unreference(obj);
3987                 mutex_unlock(&dev->struct_mutex);
3988                 return NULL;
3989         }
3990
3991         return fb;
3992 }
3993
3994 static const struct drm_mode_config_funcs intel_mode_funcs = {
3995         .fb_create = intel_user_framebuffer_create,
3996         .fb_changed = intelfb_probe,
3997 };
3998
3999 void intel_init_clock_gating(struct drm_device *dev)
4000 {
4001         struct drm_i915_private *dev_priv = dev->dev_private;
4002
4003         /*
4004          * Disable clock gating reported to work incorrectly according to the
4005          * specs, but enable as much else as we can.
4006          */
4007         if (IS_G4X(dev)) {
4008                 uint32_t dspclk_gate;
4009                 I915_WRITE(RENCLK_GATE_D1, 0);
4010                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4011                        GS_UNIT_CLOCK_GATE_DISABLE |
4012                        CL_UNIT_CLOCK_GATE_DISABLE);
4013                 I915_WRITE(RAMCLK_GATE_D, 0);
4014                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4015                         OVRUNIT_CLOCK_GATE_DISABLE |
4016                         OVCUNIT_CLOCK_GATE_DISABLE;
4017                 if (IS_GM45(dev))
4018                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4019                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4020         } else if (IS_I965GM(dev)) {
4021                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4022                 I915_WRITE(RENCLK_GATE_D2, 0);
4023                 I915_WRITE(DSPCLK_GATE_D, 0);
4024                 I915_WRITE(RAMCLK_GATE_D, 0);
4025                 I915_WRITE16(DEUC, 0);
4026         } else if (IS_I965G(dev)) {
4027                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4028                        I965_RCC_CLOCK_GATE_DISABLE |
4029                        I965_RCPB_CLOCK_GATE_DISABLE |
4030                        I965_ISC_CLOCK_GATE_DISABLE |
4031                        I965_FBC_CLOCK_GATE_DISABLE);
4032                 I915_WRITE(RENCLK_GATE_D2, 0);
4033         } else if (IS_I9XX(dev)) {
4034                 u32 dstate = I915_READ(D_STATE);
4035
4036                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4037                         DSTATE_DOT_CLOCK_GATING;
4038                 I915_WRITE(D_STATE, dstate);
4039         } else if (IS_I855(dev) || IS_I865G(dev)) {
4040                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4041         } else if (IS_I830(dev)) {
4042                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4043         }
4044 }
4045
4046 void intel_modeset_init(struct drm_device *dev)
4047 {
4048         struct drm_i915_private *dev_priv = dev->dev_private;
4049         int num_pipe;
4050         int i;
4051
4052         drm_mode_config_init(dev);
4053
4054         dev->mode_config.min_width = 0;
4055         dev->mode_config.min_height = 0;
4056
4057         dev->mode_config.funcs = (void *)&intel_mode_funcs;
4058
4059         if (IS_I965G(dev)) {
4060                 dev->mode_config.max_width = 8192;
4061                 dev->mode_config.max_height = 8192;
4062         } else if (IS_I9XX(dev)) {
4063                 dev->mode_config.max_width = 4096;
4064                 dev->mode_config.max_height = 4096;
4065         } else {
4066                 dev->mode_config.max_width = 2048;
4067                 dev->mode_config.max_height = 2048;
4068         }
4069
4070         /* set memory base */
4071         if (IS_I9XX(dev))
4072                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
4073         else
4074                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
4075
4076         if (IS_MOBILE(dev) || IS_I9XX(dev))
4077                 num_pipe = 2;
4078         else
4079                 num_pipe = 1;
4080         DRM_DEBUG("%d display pipe%s available.\n",
4081                   num_pipe, num_pipe > 1 ? "s" : "");
4082
4083         if (IS_I85X(dev))
4084                 pci_read_config_word(dev->pdev, HPLLCC, &dev_priv->orig_clock);
4085         else if (IS_I9XX(dev) || IS_G4X(dev))
4086                 pci_read_config_word(dev->pdev, GCFGC, &dev_priv->orig_clock);
4087
4088         for (i = 0; i < num_pipe; i++) {
4089                 intel_crtc_init(dev, i);
4090         }
4091
4092         intel_setup_outputs(dev);
4093
4094         intel_init_clock_gating(dev);
4095
4096         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
4097         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
4098                     (unsigned long)dev);
4099 }
4100
4101 void intel_modeset_cleanup(struct drm_device *dev)
4102 {
4103         struct drm_i915_private *dev_priv = dev->dev_private;
4104         struct drm_crtc *crtc;
4105         struct intel_crtc *intel_crtc;
4106
4107         mutex_lock(&dev->struct_mutex);
4108
4109         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4110                 /* Skip inactive CRTCs */
4111                 if (!crtc->fb)
4112                         continue;
4113
4114                 intel_crtc = to_intel_crtc(crtc);
4115                 intel_increase_pllclock(crtc, false);
4116                 del_timer_sync(&intel_crtc->idle_timer);
4117         }
4118
4119         intel_increase_renderclock(dev, false);
4120         del_timer_sync(&dev_priv->idle_timer);
4121
4122         mutex_unlock(&dev->struct_mutex);
4123
4124         i8xx_disable_fbc(dev);
4125         drm_mode_config_cleanup(dev);
4126 }
4127
4128
4129 /* current intel driver doesn't take advantage of encoders
4130    always give back the encoder for the connector
4131 */
4132 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
4133 {
4134         struct intel_output *intel_output = to_intel_output(connector);
4135
4136         return &intel_output->enc;
4137 }