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   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include "drmP.h"
  32 #include "intel_drv.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "intel_dp.h"
  36
  37 #include "drm_crtc_helper.h"
  38
  39 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  40
  41 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  42 static void intel_update_watermarks(struct drm_device *dev);
  43 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
  44
  45 typedef struct {
  46     /* given values */
  47     int n;
  48     int m1, m2;
  49     int p1, p2;
  50     /* derived values */
  51     int dot;
  52     int vco;
  53     int m;
  54     int p;
  55 } intel_clock_t;
  56
  57 typedef struct {
  58     int min, max;
  59 } intel_range_t;
  60
  61 typedef struct {
  62     int dot_limit;
  63     int p2_slow, p2_fast;
  64 } intel_p2_t;
  65
  66 #define INTEL_P2_NUM                  2
  67 typedef struct intel_limit intel_limit_t;
  68 struct intel_limit {
  69     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  70     intel_p2_t      p2;
  71     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  72                       int, int, intel_clock_t *);
  73     bool (* find_reduced_pll)(const intel_limit_t *, struct drm_crtc *,
  74                               int, int, intel_clock_t *);
  75 };
  76
  77 #define I8XX_DOT_MIN              25000
  78 #define I8XX_DOT_MAX             350000
  79 #define I8XX_VCO_MIN             930000
  80 #define I8XX_VCO_MAX            1400000
  81 #define I8XX_N_MIN                    3
  82 #define I8XX_N_MAX                   16
  83 #define I8XX_M_MIN                   96
  84 #define I8XX_M_MAX                  140
  85 #define I8XX_M1_MIN                  18
  86 #define I8XX_M1_MAX                  26
  87 #define I8XX_M2_MIN                   6
  88 #define I8XX_M2_MAX                  16
  89 #define I8XX_P_MIN                    4
  90 #define I8XX_P_MAX                  128
  91 #define I8XX_P1_MIN                   2
  92 #define I8XX_P1_MAX                  33
  93 #define I8XX_P1_LVDS_MIN              1
  94 #define I8XX_P1_LVDS_MAX              6
  95 #define I8XX_P2_SLOW                  4
  96 #define I8XX_P2_FAST                  2
  97 #define I8XX_P2_LVDS_SLOW             14
  98 #define I8XX_P2_LVDS_FAST             7
  99 #define I8XX_P2_SLOW_LIMIT       165000
 100
 101 #define I9XX_DOT_MIN              20000
 102 #define I9XX_DOT_MAX             400000
 103 #define I9XX_VCO_MIN            1400000
 104 #define I9XX_VCO_MAX            2800000
 105 #define IGD_VCO_MIN             1700000
 106 #define IGD_VCO_MAX             3500000
 107 #define I9XX_N_MIN                    1
 108 #define I9XX_N_MAX                    6
 109 /* IGD's Ncounter is a ring counter */
 110 #define IGD_N_MIN                     3
 111 #define IGD_N_MAX                     6
 112 #define I9XX_M_MIN                   70
 113 #define I9XX_M_MAX                  120
 114 #define IGD_M_MIN                     2
 115 #define IGD_M_MAX                   256
 116 #define I9XX_M1_MIN                  10
 117 #define I9XX_M1_MAX                  22
 118 #define I9XX_M2_MIN                   5
 119 #define I9XX_M2_MAX                   9
 120 /* IGD M1 is reserved, and must be 0 */
 121 #define IGD_M1_MIN                    0
 122 #define IGD_M1_MAX                    0
 123 #define IGD_M2_MIN                    0
 124 #define IGD_M2_MAX                    254
 125 #define I9XX_P_SDVO_DAC_MIN           5
 126 #define I9XX_P_SDVO_DAC_MAX          80
 127 #define I9XX_P_LVDS_MIN               7
 128 #define I9XX_P_LVDS_MAX              98
 129 #define IGD_P_LVDS_MIN                7
 130 #define IGD_P_LVDS_MAX               112
 131 #define I9XX_P1_MIN                   1
 132 #define I9XX_P1_MAX                   8
 133 #define I9XX_P2_SDVO_DAC_SLOW                10
 134 #define I9XX_P2_SDVO_DAC_FAST                 5
 135 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 136 #define I9XX_P2_LVDS_SLOW                    14
 137 #define I9XX_P2_LVDS_FAST                     7
 138 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 139
 140 /*The parameter is for SDVO on G4x platform*/
 141 #define G4X_DOT_SDVO_MIN           25000
 142 #define G4X_DOT_SDVO_MAX           270000
 143 #define G4X_VCO_MIN                1750000
 144 #define G4X_VCO_MAX                3500000
 145 #define G4X_N_SDVO_MIN             1
 146 #define G4X_N_SDVO_MAX             4
 147 #define G4X_M_SDVO_MIN             104
 148 #define G4X_M_SDVO_MAX             138
 149 #define G4X_M1_SDVO_MIN            17
 150 #define G4X_M1_SDVO_MAX            23
 151 #define G4X_M2_SDVO_MIN            5
 152 #define G4X_M2_SDVO_MAX            11
 153 #define G4X_P_SDVO_MIN             10
 154 #define G4X_P_SDVO_MAX             30
 155 #define G4X_P1_SDVO_MIN            1
 156 #define G4X_P1_SDVO_MAX            3
 157 #define G4X_P2_SDVO_SLOW           10
 158 #define G4X_P2_SDVO_FAST           10
 159 #define G4X_P2_SDVO_LIMIT          270000
 160
 161 /*The parameter is for HDMI_DAC on G4x platform*/
 162 #define G4X_DOT_HDMI_DAC_MIN           22000
 163 #define G4X_DOT_HDMI_DAC_MAX           400000
 164 #define G4X_N_HDMI_DAC_MIN             1
 165 #define G4X_N_HDMI_DAC_MAX             4
 166 #define G4X_M_HDMI_DAC_MIN             104
 167 #define G4X_M_HDMI_DAC_MAX             138
 168 #define G4X_M1_HDMI_DAC_MIN            16
 169 #define G4X_M1_HDMI_DAC_MAX            23
 170 #define G4X_M2_HDMI_DAC_MIN            5
 171 #define G4X_M2_HDMI_DAC_MAX            11
 172 #define G4X_P_HDMI_DAC_MIN             5
 173 #define G4X_P_HDMI_DAC_MAX             80
 174 #define G4X_P1_HDMI_DAC_MIN            1
 175 #define G4X_P1_HDMI_DAC_MAX            8
 176 #define G4X_P2_HDMI_DAC_SLOW           10
 177 #define G4X_P2_HDMI_DAC_FAST           5
 178 #define G4X_P2_HDMI_DAC_LIMIT          165000
 179
 180 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 181 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 182 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 183 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 184 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 185 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 186 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 187 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 188 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 189 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 190 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 191 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 192 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 193 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 194 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 195 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 196 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 198
 199 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 200 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 201 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 202 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 203 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 204 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 205 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 206 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 207 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 208 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 209 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 210 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 211 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 212 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 213 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 214 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 215 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 217
 218 /*The parameter is for DISPLAY PORT on G4x platform*/
 219 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 220 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 221 #define G4X_N_DISPLAY_PORT_MIN             1
 222 #define G4X_N_DISPLAY_PORT_MAX             2
 223 #define G4X_M_DISPLAY_PORT_MIN             97
 224 #define G4X_M_DISPLAY_PORT_MAX             108
 225 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 226 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 227 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 228 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 229 #define G4X_P_DISPLAY_PORT_MIN             10
 230 #define G4X_P_DISPLAY_PORT_MAX             20
 231 #define G4X_P1_DISPLAY_PORT_MIN            1
 232 #define G4X_P1_DISPLAY_PORT_MAX            2
 233 #define G4X_P2_DISPLAY_PORT_SLOW           10
 234 #define G4X_P2_DISPLAY_PORT_FAST           10
 235 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 236
 237 /* IGDNG */
 238 /* as we calculate clock using (register_value + 2) for
 239    N/M1/M2, so here the range value for them is (actual_value-2).
 240  */
 241 #define IGDNG_DOT_MIN         25000
 242 #define IGDNG_DOT_MAX         350000
 243 #define IGDNG_VCO_MIN         1760000
 244 #define IGDNG_VCO_MAX         3510000
 245 #define IGDNG_N_MIN           1
 246 #define IGDNG_N_MAX           5
 247 #define IGDNG_M_MIN           79
 248 #define IGDNG_M_MAX           118
 249 #define IGDNG_M1_MIN          12
 250 #define IGDNG_M1_MAX          23
 251 #define IGDNG_M2_MIN          5
 252 #define IGDNG_M2_MAX          9
 253 #define IGDNG_P_SDVO_DAC_MIN  5
 254 #define IGDNG_P_SDVO_DAC_MAX  80
 255 #define IGDNG_P_LVDS_MIN      28
 256 #define IGDNG_P_LVDS_MAX      112
 257 #define IGDNG_P1_MIN          1
 258 #define IGDNG_P1_MAX          8
 259 #define IGDNG_P2_SDVO_DAC_SLOW 10
 260 #define IGDNG_P2_SDVO_DAC_FAST 5
 261 #define IGDNG_P2_LVDS_SLOW    14 /* single channel */
 262 #define IGDNG_P2_LVDS_FAST    7  /* double channel */
 263 #define IGDNG_P2_DOT_LIMIT    225000 /* 225Mhz */
 264
 265 static bool
 266 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 267                     int target, int refclk, intel_clock_t *best_clock);
 268 static bool
 269 intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 270                             int target, int refclk, intel_clock_t *best_clock);
 271 static bool
 272 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 273                         int target, int refclk, intel_clock_t *best_clock);
 274 static bool
 275 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 276                         int target, int refclk, intel_clock_t *best_clock);
 277
 278 static bool
 279 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 280                       int target, int refclk, intel_clock_t *best_clock);
 281 static bool
 282 intel_find_pll_igdng_dp(const intel_limit_t *, struct drm_crtc *crtc,
 283                       int target, int refclk, intel_clock_t *best_clock);
 284
 285 static const intel_limit_t intel_limits_i8xx_dvo = {
 286         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 287         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 288         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 289         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 290         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 291         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 292         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 293         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 294         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 295                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 296         .find_pll = intel_find_best_PLL,
 297         .find_reduced_pll = intel_find_best_reduced_PLL,
 298 };
 299
 300 static const intel_limit_t intel_limits_i8xx_lvds = {
 301         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 302         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 303         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 304         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 305         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 306         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 307         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 308         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 309         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 310                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 311         .find_pll = intel_find_best_PLL,
 312         .find_reduced_pll = intel_find_best_reduced_PLL,
 313 };
 314
 315 static const intel_limit_t intel_limits_i9xx_sdvo = {
 316         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 317         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 318         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 319         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 320         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 321         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 322         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 323         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 324         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 325                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 326         .find_pll = intel_find_best_PLL,
 327         .find_reduced_pll = intel_find_best_reduced_PLL,
 328 };
 329
 330 static const intel_limit_t intel_limits_i9xx_lvds = {
 331         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 332         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 333         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 334         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 335         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 336         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 337         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 338         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 339         /* The single-channel range is 25-112Mhz, and dual-channel
 340          * is 80-224Mhz.  Prefer single channel as much as possible.
 341          */
 342         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 343                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 344         .find_pll = intel_find_best_PLL,
 345         .find_reduced_pll = intel_find_best_reduced_PLL,
 346 };
 347
 348     /* below parameter and function is for G4X Chipset Family*/
 349 static const intel_limit_t intel_limits_g4x_sdvo = {
 350         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 351         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 352         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 353         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 354         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 355         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 356         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 357         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 358         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 359                  .p2_slow = G4X_P2_SDVO_SLOW,
 360                  .p2_fast = G4X_P2_SDVO_FAST
 361         },
 362         .find_pll = intel_g4x_find_best_PLL,
 363         .find_reduced_pll = intel_g4x_find_best_PLL,
 364 };
 365
 366 static const intel_limit_t intel_limits_g4x_hdmi = {
 367         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 368         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 369         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 370         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 371         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 372         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 373         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 374         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 375         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 376                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 377                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 378         },
 379         .find_pll = intel_g4x_find_best_PLL,
 380         .find_reduced_pll = intel_g4x_find_best_PLL,
 381 };
 382
 383 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 384         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 385                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 386         .vco = { .min = G4X_VCO_MIN,
 387                  .max = G4X_VCO_MAX },
 388         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 389                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 390         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 391                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 392         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 393                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 394         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 395                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 396         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 397                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 398         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 399                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 400         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 401                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 402                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 403         },
 404         .find_pll = intel_g4x_find_best_PLL,
 405         .find_reduced_pll = intel_g4x_find_best_PLL,
 406 };
 407
 408 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 409         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 410                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 411         .vco = { .min = G4X_VCO_MIN,
 412                  .max = G4X_VCO_MAX },
 413         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 414                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 415         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 416                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 417         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 418                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 419         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 420                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 421         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 422                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 423         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 424                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 425         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 426                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 427                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 428         },
 429         .find_pll = intel_g4x_find_best_PLL,
 430         .find_reduced_pll = intel_g4x_find_best_PLL,
 431 };
 432
 433 static const intel_limit_t intel_limits_g4x_display_port = {
 434         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 435                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 436         .vco = { .min = G4X_VCO_MIN,
 437                  .max = G4X_VCO_MAX},
 438         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 439                  .max = G4X_N_DISPLAY_PORT_MAX },
 440         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 441                  .max = G4X_M_DISPLAY_PORT_MAX },
 442         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 443                  .max = G4X_M1_DISPLAY_PORT_MAX },
 444         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 445                  .max = G4X_M2_DISPLAY_PORT_MAX },
 446         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 447                  .max = G4X_P_DISPLAY_PORT_MAX },
 448         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 449                  .max = G4X_P1_DISPLAY_PORT_MAX},
 450         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 451                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 452                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 453         .find_pll = intel_find_pll_g4x_dp,
 454 };
 455
 456 static const intel_limit_t intel_limits_igd_sdvo = {
 457         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 458         .vco = { .min = IGD_VCO_MIN,            .max = IGD_VCO_MAX },
 459         .n   = { .min = IGD_N_MIN,              .max = IGD_N_MAX },
 460         .m   = { .min = IGD_M_MIN,              .max = IGD_M_MAX },
 461         .m1  = { .min = IGD_M1_MIN,             .max = IGD_M1_MAX },
 462         .m2  = { .min = IGD_M2_MIN,             .max = IGD_M2_MAX },
 463         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 464         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 465         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 466                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 467         .find_pll = intel_find_best_PLL,
 468         .find_reduced_pll = intel_find_best_reduced_PLL,
 469 };
 470
 471 static const intel_limit_t intel_limits_igd_lvds = {
 472         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 473         .vco = { .min = IGD_VCO_MIN,            .max = IGD_VCO_MAX },
 474         .n   = { .min = IGD_N_MIN,              .max = IGD_N_MAX },
 475         .m   = { .min = IGD_M_MIN,              .max = IGD_M_MAX },
 476         .m1  = { .min = IGD_M1_MIN,             .max = IGD_M1_MAX },
 477         .m2  = { .min = IGD_M2_MIN,             .max = IGD_M2_MAX },
 478         .p   = { .min = IGD_P_LVDS_MIN, .max = IGD_P_LVDS_MAX },
 479         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 480         /* IGD only supports single-channel mode. */
 481         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 482                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 483         .find_pll = intel_find_best_PLL,
 484         .find_reduced_pll = intel_find_best_reduced_PLL,
 485 };
 486
 487 static const intel_limit_t intel_limits_igdng_sdvo = {
 488         .dot = { .min = IGDNG_DOT_MIN,          .max = IGDNG_DOT_MAX },
 489         .vco = { .min = IGDNG_VCO_MIN,          .max = IGDNG_VCO_MAX },
 490         .n   = { .min = IGDNG_N_MIN,            .max = IGDNG_N_MAX },
 491         .m   = { .min = IGDNG_M_MIN,            .max = IGDNG_M_MAX },
 492         .m1  = { .min = IGDNG_M1_MIN,           .max = IGDNG_M1_MAX },
 493         .m2  = { .min = IGDNG_M2_MIN,           .max = IGDNG_M2_MAX },
 494         .p   = { .min = IGDNG_P_SDVO_DAC_MIN,   .max = IGDNG_P_SDVO_DAC_MAX },
 495         .p1  = { .min = IGDNG_P1_MIN,           .max = IGDNG_P1_MAX },
 496         .p2  = { .dot_limit = IGDNG_P2_DOT_LIMIT,
 497                  .p2_slow = IGDNG_P2_SDVO_DAC_SLOW,
 498                  .p2_fast = IGDNG_P2_SDVO_DAC_FAST },
 499         .find_pll = intel_igdng_find_best_PLL,
 500 };
 501
 502 static const intel_limit_t intel_limits_igdng_lvds = {
 503         .dot = { .min = IGDNG_DOT_MIN,          .max = IGDNG_DOT_MAX },
 504         .vco = { .min = IGDNG_VCO_MIN,          .max = IGDNG_VCO_MAX },
 505         .n   = { .min = IGDNG_N_MIN,            .max = IGDNG_N_MAX },
 506         .m   = { .min = IGDNG_M_MIN,            .max = IGDNG_M_MAX },
 507         .m1  = { .min = IGDNG_M1_MIN,           .max = IGDNG_M1_MAX },
 508         .m2  = { .min = IGDNG_M2_MIN,           .max = IGDNG_M2_MAX },
 509         .p   = { .min = IGDNG_P_LVDS_MIN,       .max = IGDNG_P_LVDS_MAX },
 510         .p1  = { .min = IGDNG_P1_MIN,           .max = IGDNG_P1_MAX },
 511         .p2  = { .dot_limit = IGDNG_P2_DOT_LIMIT,
 512                  .p2_slow = IGDNG_P2_LVDS_SLOW,
 513                  .p2_fast = IGDNG_P2_LVDS_FAST },
 514         .find_pll = intel_igdng_find_best_PLL,
 515 };
 516
 517 static const intel_limit_t *intel_igdng_limit(struct drm_crtc *crtc)
 518 {
 519         const intel_limit_t *limit;
 520         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 521                 limit = &intel_limits_igdng_lvds;
 522         else
 523                 limit = &intel_limits_igdng_sdvo;
 524
 525         return limit;
 526 }
 527
 528 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 529 {
 530         struct drm_device *dev = crtc->dev;
 531         struct drm_i915_private *dev_priv = dev->dev_private;
 532         const intel_limit_t *limit;
 533
 534         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 535                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 536                     LVDS_CLKB_POWER_UP)
 537                         /* LVDS with dual channel */
 538                         limit = &intel_limits_g4x_dual_channel_lvds;
 539                 else
 540                         /* LVDS with dual channel */
 541                         limit = &intel_limits_g4x_single_channel_lvds;
 542         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 543                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 544                 limit = &intel_limits_g4x_hdmi;
 545         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 546                 limit = &intel_limits_g4x_sdvo;
 547         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 548                 limit = &intel_limits_g4x_display_port;
 549         } else /* The option is for other outputs */
 550                 limit = &intel_limits_i9xx_sdvo;
 551
 552         return limit;
 553 }
 554
 555 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 556 {
 557         struct drm_device *dev = crtc->dev;
 558         const intel_limit_t *limit;
 559
 560         if (IS_IGDNG(dev))
 561                 limit = intel_igdng_limit(crtc);
 562         else if (IS_G4X(dev)) {
 563                 limit = intel_g4x_limit(crtc);
 564         } else if (IS_I9XX(dev) && !IS_IGD(dev)) {
 565                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 566                         limit = &intel_limits_i9xx_lvds;
 567                 else
 568                         limit = &intel_limits_i9xx_sdvo;
 569         } else if (IS_IGD(dev)) {
 570                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 571                         limit = &intel_limits_igd_lvds;
 572                 else
 573                         limit = &intel_limits_igd_sdvo;
 574         } else {
 575                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 576                         limit = &intel_limits_i8xx_lvds;
 577                 else
 578                         limit = &intel_limits_i8xx_dvo;
 579         }
 580         return limit;
 581 }
 582
 583 /* m1 is reserved as 0 in IGD, n is a ring counter */
 584 static void igd_clock(int refclk, intel_clock_t *clock)
 585 {
 586         clock->m = clock->m2 + 2;
 587         clock->p = clock->p1 * clock->p2;
 588         clock->vco = refclk * clock->m / clock->n;
 589         clock->dot = clock->vco / clock->p;
 590 }
 591
 592 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 593 {
 594         if (IS_IGD(dev)) {
 595                 igd_clock(refclk, clock);
 596                 return;
 597         }
 598         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 599         clock->p = clock->p1 * clock->p2;
 600         clock->vco = refclk * clock->m / (clock->n + 2);
 601         clock->dot = clock->vco / clock->p;
 602 }
 603
 604 /**
 605  * Returns whether any output on the specified pipe is of the specified type
 606  */
 607 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
 608 {
 609     struct drm_device *dev = crtc->dev;
 610     struct drm_mode_config *mode_config = &dev->mode_config;
 611     struct drm_connector *l_entry;
 612
 613     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 614             if (l_entry->encoder &&
 615                 l_entry->encoder->crtc == crtc) {
 616                     struct intel_output *intel_output = to_intel_output(l_entry);
 617                     if (intel_output->type == type)
 618                             return true;
 619             }
 620     }
 621     return false;
 622 }
 623
 624 struct drm_connector *
 625 intel_pipe_get_output (struct drm_crtc *crtc)
 626 {
 627     struct drm_device *dev = crtc->dev;
 628     struct drm_mode_config *mode_config = &dev->mode_config;
 629     struct drm_connector *l_entry, *ret = NULL;
 630
 631     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 632             if (l_entry->encoder &&
 633                 l_entry->encoder->crtc == crtc) {
 634                     ret = l_entry;
 635                     break;
 636             }
 637     }
 638     return ret;
 639 }
 640
 641 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 642 /**
 643  * Returns whether the given set of divisors are valid for a given refclk with
 644  * the given connectors.
 645  */
 646
 647 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 648 {
 649         const intel_limit_t *limit = intel_limit (crtc);
 650         struct drm_device *dev = crtc->dev;
 651
 652         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 653                 INTELPllInvalid ("p1 out of range\n");
 654         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 655                 INTELPllInvalid ("p out of range\n");
 656         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 657                 INTELPllInvalid ("m2 out of range\n");
 658         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 659                 INTELPllInvalid ("m1 out of range\n");
 660         if (clock->m1 <= clock->m2 && !IS_IGD(dev))
 661                 INTELPllInvalid ("m1 <= m2\n");
 662         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 663                 INTELPllInvalid ("m out of range\n");
 664         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 665                 INTELPllInvalid ("n out of range\n");
 666         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 667                 INTELPllInvalid ("vco out of range\n");
 668         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 669          * connector, etc., rather than just a single range.
 670          */
 671         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 672                 INTELPllInvalid ("dot out of range\n");
 673
 674         return true;
 675 }
 676
 677 static bool
 678 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 679                     int target, int refclk, intel_clock_t *best_clock)
 680
 681 {
 682         struct drm_device *dev = crtc->dev;
 683         struct drm_i915_private *dev_priv = dev->dev_private;
 684         intel_clock_t clock;
 685         int err = target;
 686
 687         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 688             (I915_READ(LVDS)) != 0) {
 689                 /*
 690                  * For LVDS, if the panel is on, just rely on its current
 691                  * settings for dual-channel.  We haven't figured out how to
 692                  * reliably set up different single/dual channel state, if we
 693                  * even can.
 694                  */
 695                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 696                     LVDS_CLKB_POWER_UP)
 697                         clock.p2 = limit->p2.p2_fast;
 698                 else
 699                         clock.p2 = limit->p2.p2_slow;
 700         } else {
 701                 if (target < limit->p2.dot_limit)
 702                         clock.p2 = limit->p2.p2_slow;
 703                 else
 704                         clock.p2 = limit->p2.p2_fast;
 705         }
 706
 707         memset (best_clock, 0, sizeof (*best_clock));
 708
 709         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 710                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 711                      clock.m1++) {
 712                         for (clock.m2 = limit->m2.min;
 713                              clock.m2 <= limit->m2.max; clock.m2++) {
 714                                 /* m1 is always 0 in IGD */
 715                                 if (clock.m2 >= clock.m1 && !IS_IGD(dev))
 716                                         break;
 717                                 for (clock.n = limit->n.min;
 718                                      clock.n <= limit->n.max; clock.n++) {
 719                                         int this_err;
 720
 721                                         intel_clock(dev, refclk, &clock);
 722
 723                                         if (!intel_PLL_is_valid(crtc, &clock))
 724                                                 continue;
 725
 726                                         this_err = abs(clock.dot - target);
 727                                         if (this_err < err) {
 728                                                 *best_clock = clock;
 729                                                 err = this_err;
 730                                         }
 731                                 }
 732                         }
 733                 }
 734         }
 735
 736         return (err != target);
 737 }
 738
 739
 740 static bool
 741 intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 742                             int target, int refclk, intel_clock_t *best_clock)
 743
 744 {
 745         struct drm_device *dev = crtc->dev;
 746         intel_clock_t clock;
 747         int err = target;
 748         bool found = false;
 749
 750         memcpy(&clock, best_clock, sizeof(intel_clock_t));
 751
 752         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 753                 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
 754                         /* m1 is always 0 in IGD */
 755                         if (clock.m2 >= clock.m1 && !IS_IGD(dev))
 756                                 break;
 757                         for (clock.n = limit->n.min; clock.n <= limit->n.max;
 758                              clock.n++) {
 759                                 int this_err;
 760
 761                                 intel_clock(dev, refclk, &clock);
 762
 763                                 if (!intel_PLL_is_valid(crtc, &clock))
 764                                         continue;
 765
 766                                 this_err = abs(clock.dot - target);
 767                                 if (this_err < err) {
 768                                         *best_clock = clock;
 769                                         err = this_err;
 770                                         found = true;
 771                                 }
 772                         }
 773                 }
 774         }
 775
 776         return found;
 777 }
 778
 779 static bool
 780 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 781                         int target, int refclk, intel_clock_t *best_clock)
 782 {
 783         struct drm_device *dev = crtc->dev;
 784         struct drm_i915_private *dev_priv = dev->dev_private;
 785         intel_clock_t clock;
 786         int max_n;
 787         bool found;
 788         /* approximately equals target * 0.00488 */
 789         int err_most = (target >> 8) + (target >> 10);
 790         found = false;
 791
 792         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 793                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 794                     LVDS_CLKB_POWER_UP)
 795                         clock.p2 = limit->p2.p2_fast;
 796                 else
 797                         clock.p2 = limit->p2.p2_slow;
 798         } else {
 799                 if (target < limit->p2.dot_limit)
 800                         clock.p2 = limit->p2.p2_slow;
 801                 else
 802                         clock.p2 = limit->p2.p2_fast;
 803         }
 804
 805         memset(best_clock, 0, sizeof(*best_clock));
 806         max_n = limit->n.max;
 807         /* based on hardware requriment prefer smaller n to precision */
 808         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 809                 /* based on hardware requirment prefere larger m1,m2 */
 810                 for (clock.m1 = limit->m1.max;
 811                      clock.m1 >= limit->m1.min; clock.m1--) {
 812                         for (clock.m2 = limit->m2.max;
 813                              clock.m2 >= limit->m2.min; clock.m2--) {
 814                                 for (clock.p1 = limit->p1.max;
 815                                      clock.p1 >= limit->p1.min; clock.p1--) {
 816                                         int this_err;
 817
 818                                         intel_clock(dev, refclk, &clock);
 819                                         if (!intel_PLL_is_valid(crtc, &clock))
 820                                                 continue;
 821                                         this_err = abs(clock.dot - target) ;
 822                                         if (this_err < err_most) {
 823                                                 *best_clock = clock;
 824                                                 err_most = this_err;
 825                                                 max_n = clock.n;
 826                                                 found = true;
 827                                         }
 828                                 }
 829                         }
 830                 }
 831         }
 832         return found;
 833 }
 834
 835 static bool
 836 intel_find_pll_igdng_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 837                       int target, int refclk, intel_clock_t *best_clock)
 838 {
 839         struct drm_device *dev = crtc->dev;
 840         intel_clock_t clock;
 841         if (target < 200000) {
 842                 clock.n = 1;
 843                 clock.p1 = 2;
 844                 clock.p2 = 10;
 845                 clock.m1 = 12;
 846                 clock.m2 = 9;
 847         } else {
 848                 clock.n = 2;
 849                 clock.p1 = 1;
 850                 clock.p2 = 10;
 851                 clock.m1 = 14;
 852                 clock.m2 = 8;
 853         }
 854         intel_clock(dev, refclk, &clock);
 855         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 856         return true;
 857 }
 858
 859 static bool
 860 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 861                         int target, int refclk, intel_clock_t *best_clock)
 862 {
 863         struct drm_device *dev = crtc->dev;
 864         struct drm_i915_private *dev_priv = dev->dev_private;
 865         intel_clock_t clock;
 866         int max_n;
 867         bool found;
 868         int err_most = 47;
 869         found = false;
 870
 871         /* eDP has only 2 clock choice, no n/m/p setting */
 872         if (HAS_eDP)
 873                 return true;
 874
 875         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
 876                 return intel_find_pll_igdng_dp(limit, crtc, target,
 877                                                refclk, best_clock);
 878
 879         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 880                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 881                     LVDS_CLKB_POWER_UP)
 882                         clock.p2 = limit->p2.p2_fast;
 883                 else
 884                         clock.p2 = limit->p2.p2_slow;
 885         } else {
 886                 if (target < limit->p2.dot_limit)
 887                         clock.p2 = limit->p2.p2_slow;
 888                 else
 889                         clock.p2 = limit->p2.p2_fast;
 890         }
 891
 892         memset(best_clock, 0, sizeof(*best_clock));
 893         max_n = limit->n.max;
 894         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 895                 /* based on hardware requriment prefer smaller n to precision */
 896                 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 897                         /* based on hardware requirment prefere larger m1,m2 */
 898                         for (clock.m1 = limit->m1.max;
 899                              clock.m1 >= limit->m1.min; clock.m1--) {
 900                                 for (clock.m2 = limit->m2.max;
 901                                      clock.m2 >= limit->m2.min; clock.m2--) {
 902                                         int this_err;
 903
 904                                         intel_clock(dev, refclk, &clock);
 905                                         if (!intel_PLL_is_valid(crtc, &clock))
 906                                                 continue;
 907                                         this_err = abs((10000 - (target*10000/clock.dot)));
 908                                         if (this_err < err_most) {
 909                                                 *best_clock = clock;
 910                                                 err_most = this_err;
 911                                                 max_n = clock.n;
 912                                                 found = true;
 913                                                 /* found on first matching */
 914                                                 goto out;
 915                                         }
 916                                 }
 917                         }
 918                 }
 919         }
 920 out:
 921         return found;
 922 }
 923
 924 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 925 static bool
 926 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 927                       int target, int refclk, intel_clock_t *best_clock)
 928 {
 929     intel_clock_t clock;
 930     if (target < 200000) {
 931         clock.p1 = 2;
 932         clock.p2 = 10;
 933         clock.n = 2;
 934         clock.m1 = 23;
 935         clock.m2 = 8;
 936     } else {
 937         clock.p1 = 1;
 938         clock.p2 = 10;
 939         clock.n = 1;
 940         clock.m1 = 14;
 941         clock.m2 = 2;
 942     }
 943     clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 944     clock.p = (clock.p1 * clock.p2);
 945     clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 946     memcpy(best_clock, &clock, sizeof(intel_clock_t));
 947     return true;
 948 }
 949
 950 void
 951 intel_wait_for_vblank(struct drm_device *dev)
 952 {
 953         /* Wait for 20ms, i.e. one cycle at 50hz. */
 954         mdelay(20);
 955 }
 956
 957 /* Parameters have changed, update FBC info */
 958 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 959 {
 960         struct drm_device *dev = crtc->dev;
 961         struct drm_i915_private *dev_priv = dev->dev_private;
 962         struct drm_framebuffer *fb = crtc->fb;
 963         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 964         struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
 965         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 966         int plane, i;
 967         u32 fbc_ctl, fbc_ctl2;
 968
 969         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
 970
 971         if (fb->pitch < dev_priv->cfb_pitch)
 972                 dev_priv->cfb_pitch = fb->pitch;
 973
 974         /* FBC_CTL wants 64B units */
 975         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
 976         dev_priv->cfb_fence = obj_priv->fence_reg;
 977         dev_priv->cfb_plane = intel_crtc->plane;
 978         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
 979
 980         /* Clear old tags */
 981         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 982                 I915_WRITE(FBC_TAG + (i * 4), 0);
 983
 984         /* Set it up... */
 985         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
 986         if (obj_priv->tiling_mode != I915_TILING_NONE)
 987                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
 988         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 989         I915_WRITE(FBC_FENCE_OFF, crtc->y);
 990
 991         /* enable it... */
 992         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
 993         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 994         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
 995         if (obj_priv->tiling_mode != I915_TILING_NONE)
 996                 fbc_ctl |= dev_priv->cfb_fence;
 997         I915_WRITE(FBC_CONTROL, fbc_ctl);
 998
 999         DRM_DEBUG("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1000                   dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1001 }
1002
1003 void i8xx_disable_fbc(struct drm_device *dev)
1004 {
1005         struct drm_i915_private *dev_priv = dev->dev_private;
1006         u32 fbc_ctl;
1007
1008         if (!I915_HAS_FBC(dev))
1009                 return;
1010
1011         /* Disable compression */
1012         fbc_ctl = I915_READ(FBC_CONTROL);
1013         fbc_ctl &= ~FBC_CTL_EN;
1014         I915_WRITE(FBC_CONTROL, fbc_ctl);
1015
1016         /* Wait for compressing bit to clear */
1017         while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING)
1018                 ; /* nothing */
1019
1020         intel_wait_for_vblank(dev);
1021
1022         DRM_DEBUG("disabled FBC\n");
1023 }
1024
1025 static bool i8xx_fbc_enabled(struct drm_crtc *crtc)
1026 {
1027         struct drm_device *dev = crtc->dev;
1028         struct drm_i915_private *dev_priv = dev->dev_private;
1029
1030         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1031 }
1032
1033 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1034 {
1035         struct drm_device *dev = crtc->dev;
1036         struct drm_i915_private *dev_priv = dev->dev_private;
1037         struct drm_framebuffer *fb = crtc->fb;
1038         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1039         struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
1040         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1041         int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1042                      DPFC_CTL_PLANEB);
1043         unsigned long stall_watermark = 200;
1044         u32 dpfc_ctl;
1045
1046         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1047         dev_priv->cfb_fence = obj_priv->fence_reg;
1048         dev_priv->cfb_plane = intel_crtc->plane;
1049
1050         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1051         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1052                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1053                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1054         } else {
1055                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1056         }
1057
1058         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1059         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1060                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1061                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1062         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1063
1064         /* enable it... */
1065         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1066
1067         DRM_DEBUG("enabled fbc on plane %d\n", intel_crtc->plane);
1068 }
1069
1070 void g4x_disable_fbc(struct drm_device *dev)
1071 {
1072         struct drm_i915_private *dev_priv = dev->dev_private;
1073         u32 dpfc_ctl;
1074
1075         /* Disable compression */
1076         dpfc_ctl = I915_READ(DPFC_CONTROL);
1077         dpfc_ctl &= ~DPFC_CTL_EN;
1078         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1079         intel_wait_for_vblank(dev);
1080
1081         DRM_DEBUG("disabled FBC\n");
1082 }
1083
1084 static bool g4x_fbc_enabled(struct drm_crtc *crtc)
1085 {
1086         struct drm_device *dev = crtc->dev;
1087         struct drm_i915_private *dev_priv = dev->dev_private;
1088
1089         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1090 }
1091
1092 /**
1093  * intel_update_fbc - enable/disable FBC as needed
1094  * @crtc: CRTC to point the compressor at
1095  * @mode: mode in use
1096  *
1097  * Set up the framebuffer compression hardware at mode set time.  We
1098  * enable it if possible:
1099  *   - plane A only (on pre-965)
1100  *   - no pixel mulitply/line duplication
1101  *   - no alpha buffer discard
1102  *   - no dual wide
1103  *   - framebuffer <= 2048 in width, 1536 in height
1104  *
1105  * We can't assume that any compression will take place (worst case),
1106  * so the compressed buffer has to be the same size as the uncompressed
1107  * one.  It also must reside (along with the line length buffer) in
1108  * stolen memory.
1109  *
1110  * We need to enable/disable FBC on a global basis.
1111  */
1112 static void intel_update_fbc(struct drm_crtc *crtc,
1113                              struct drm_display_mode *mode)
1114 {
1115         struct drm_device *dev = crtc->dev;
1116         struct drm_i915_private *dev_priv = dev->dev_private;
1117         struct drm_framebuffer *fb = crtc->fb;
1118         struct intel_framebuffer *intel_fb;
1119         struct drm_i915_gem_object *obj_priv;
1120         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1121         int plane = intel_crtc->plane;
1122
1123         if (!i915_powersave)
1124                 return;
1125
1126         if (!dev_priv->display.fbc_enabled ||
1127             !dev_priv->display.enable_fbc ||
1128             !dev_priv->display.disable_fbc)
1129                 return;
1130
1131         if (!crtc->fb)
1132                 return;
1133
1134         intel_fb = to_intel_framebuffer(fb);
1135         obj_priv = intel_fb->obj->driver_private;
1136
1137         /*
1138          * If FBC is already on, we just have to verify that we can
1139          * keep it that way...
1140          * Need to disable if:
1141          *   - changing FBC params (stride, fence, mode)
1142          *   - new fb is too large to fit in compressed buffer
1143          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1144          */
1145         if (intel_fb->obj->size > dev_priv->cfb_size) {
1146                 DRM_DEBUG("framebuffer too large, disabling compression\n");
1147                 goto out_disable;
1148         }
1149         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1150             (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1151                 DRM_DEBUG("mode incompatible with compression, disabling\n");
1152                 goto out_disable;
1153         }
1154         if ((mode->hdisplay > 2048) ||
1155             (mode->vdisplay > 1536)) {
1156                 DRM_DEBUG("mode too large for compression, disabling\n");
1157                 goto out_disable;
1158         }
1159         if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1160                 DRM_DEBUG("plane not 0, disabling compression\n");
1161                 goto out_disable;
1162         }
1163         if (obj_priv->tiling_mode != I915_TILING_X) {
1164                 DRM_DEBUG("framebuffer not tiled, disabling compression\n");
1165                 goto out_disable;
1166         }
1167
1168         if (dev_priv->display.fbc_enabled(crtc)) {
1169                 /* We can re-enable it in this case, but need to update pitch */
1170                 if (fb->pitch > dev_priv->cfb_pitch)
1171                         dev_priv->display.disable_fbc(dev);
1172                 if (obj_priv->fence_reg != dev_priv->cfb_fence)
1173                         dev_priv->display.disable_fbc(dev);
1174                 if (plane != dev_priv->cfb_plane)
1175                         dev_priv->display.disable_fbc(dev);
1176         }
1177
1178         if (!dev_priv->display.fbc_enabled(crtc)) {
1179                 /* Now try to turn it back on if possible */
1180                 dev_priv->display.enable_fbc(crtc, 500);
1181         }
1182
1183         return;
1184
1185 out_disable:
1186         DRM_DEBUG("unsupported config, disabling FBC\n");
1187         /* Multiple disables should be harmless */
1188         if (dev_priv->display.fbc_enabled(crtc))
1189                 dev_priv->display.disable_fbc(dev);
1190 }
1191
1192 static int
1193 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1194                     struct drm_framebuffer *old_fb)
1195 {
1196         struct drm_device *dev = crtc->dev;
1197         struct drm_i915_private *dev_priv = dev->dev_private;
1198         struct drm_i915_master_private *master_priv;
1199         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1200         struct intel_framebuffer *intel_fb;
1201         struct drm_i915_gem_object *obj_priv;
1202         struct drm_gem_object *obj;
1203         int pipe = intel_crtc->pipe;
1204         int plane = intel_crtc->plane;
1205         unsigned long Start, Offset;
1206         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1207         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1208         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1209         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1210         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1211         u32 dspcntr, alignment;
1212         int ret;
1213
1214         /* no fb bound */
1215         if (!crtc->fb) {
1216                 DRM_DEBUG("No FB bound\n");
1217                 return 0;
1218         }
1219
1220         switch (plane) {
1221         case 0:
1222         case 1:
1223                 break;
1224         default:
1225                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1226                 return -EINVAL;
1227         }
1228
1229         intel_fb = to_intel_framebuffer(crtc->fb);
1230         obj = intel_fb->obj;
1231         obj_priv = obj->driver_private;
1232
1233         switch (obj_priv->tiling_mode) {
1234         case I915_TILING_NONE:
1235                 alignment = 64 * 1024;
1236                 break;
1237         case I915_TILING_X:
1238                 /* pin() will align the object as required by fence */
1239                 alignment = 0;
1240                 break;
1241         case I915_TILING_Y:
1242                 /* FIXME: Is this true? */
1243                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1244                 return -EINVAL;
1245         default:
1246                 BUG();
1247         }
1248
1249         mutex_lock(&dev->struct_mutex);
1250         ret = i915_gem_object_pin(obj, alignment);
1251         if (ret != 0) {
1252                 mutex_unlock(&dev->struct_mutex);
1253                 return ret;
1254         }
1255
1256         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
1257         if (ret != 0) {
1258                 i915_gem_object_unpin(obj);
1259                 mutex_unlock(&dev->struct_mutex);
1260                 return ret;
1261         }
1262
1263         /* Pre-i965 needs to install a fence for tiled scan-out */
1264         if (!IS_I965G(dev) &&
1265             obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1266             obj_priv->tiling_mode != I915_TILING_NONE) {
1267                 ret = i915_gem_object_get_fence_reg(obj);
1268                 if (ret != 0) {
1269                         i915_gem_object_unpin(obj);
1270                         mutex_unlock(&dev->struct_mutex);
1271                         return ret;
1272                 }
1273         }
1274
1275         dspcntr = I915_READ(dspcntr_reg);
1276         /* Mask out pixel format bits in case we change it */
1277         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1278         switch (crtc->fb->bits_per_pixel) {
1279         case 8:
1280                 dspcntr |= DISPPLANE_8BPP;
1281                 break;
1282         case 16:
1283                 if (crtc->fb->depth == 15)
1284                         dspcntr |= DISPPLANE_15_16BPP;
1285                 else
1286                         dspcntr |= DISPPLANE_16BPP;
1287                 break;
1288         case 24:
1289         case 32:
1290                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1291                 break;
1292         default:
1293                 DRM_ERROR("Unknown color depth\n");
1294                 i915_gem_object_unpin(obj);
1295                 mutex_unlock(&dev->struct_mutex);
1296                 return -EINVAL;
1297         }
1298         if (IS_I965G(dev)) {
1299                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1300                         dspcntr |= DISPPLANE_TILED;
1301                 else
1302                         dspcntr &= ~DISPPLANE_TILED;
1303         }
1304
1305         if (IS_IGDNG(dev))
1306                 /* must disable */
1307                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1308
1309         I915_WRITE(dspcntr_reg, dspcntr);
1310
1311         Start = obj_priv->gtt_offset;
1312         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1313
1314         DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1315         I915_WRITE(dspstride, crtc->fb->pitch);
1316         if (IS_I965G(dev)) {
1317                 I915_WRITE(dspbase, Offset);
1318                 I915_READ(dspbase);
1319                 I915_WRITE(dspsurf, Start);
1320                 I915_READ(dspsurf);
1321                 I915_WRITE(dsptileoff, (y << 16) | x);
1322         } else {
1323                 I915_WRITE(dspbase, Start + Offset);
1324                 I915_READ(dspbase);
1325         }
1326
1327         if ((IS_I965G(dev) || plane == 0))
1328                 intel_update_fbc(crtc, &crtc->mode);
1329
1330         intel_wait_for_vblank(dev);
1331
1332         if (old_fb) {
1333                 intel_fb = to_intel_framebuffer(old_fb);
1334                 obj_priv = intel_fb->obj->driver_private;
1335                 i915_gem_object_unpin(intel_fb->obj);
1336         }
1337         intel_increase_pllclock(crtc, true);
1338
1339         mutex_unlock(&dev->struct_mutex);
1340
1341         if (!dev->primary->master)
1342                 return 0;
1343
1344         master_priv = dev->primary->master->driver_priv;
1345         if (!master_priv->sarea_priv)
1346                 return 0;
1347
1348         if (pipe) {
1349                 master_priv->sarea_priv->pipeB_x = x;
1350                 master_priv->sarea_priv->pipeB_y = y;
1351         } else {
1352                 master_priv->sarea_priv->pipeA_x = x;
1353                 master_priv->sarea_priv->pipeA_y = y;
1354         }
1355
1356         return 0;
1357 }
1358
1359 /* Disable the VGA plane that we never use */
1360 static void i915_disable_vga (struct drm_device *dev)
1361 {
1362         struct drm_i915_private *dev_priv = dev->dev_private;
1363         u8 sr1;
1364         u32 vga_reg;
1365
1366         if (IS_IGDNG(dev))
1367                 vga_reg = CPU_VGACNTRL;
1368         else
1369                 vga_reg = VGACNTRL;
1370
1371         if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1372                 return;
1373
1374         I915_WRITE8(VGA_SR_INDEX, 1);
1375         sr1 = I915_READ8(VGA_SR_DATA);
1376         I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1377         udelay(100);
1378
1379         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1380 }
1381
1382 static void igdng_disable_pll_edp (struct drm_crtc *crtc)
1383 {
1384         struct drm_device *dev = crtc->dev;
1385         struct drm_i915_private *dev_priv = dev->dev_private;
1386         u32 dpa_ctl;
1387
1388         DRM_DEBUG("\n");
1389         dpa_ctl = I915_READ(DP_A);
1390         dpa_ctl &= ~DP_PLL_ENABLE;
1391         I915_WRITE(DP_A, dpa_ctl);
1392 }
1393
1394 static void igdng_enable_pll_edp (struct drm_crtc *crtc)
1395 {
1396         struct drm_device *dev = crtc->dev;
1397         struct drm_i915_private *dev_priv = dev->dev_private;
1398         u32 dpa_ctl;
1399
1400         dpa_ctl = I915_READ(DP_A);
1401         dpa_ctl |= DP_PLL_ENABLE;
1402         I915_WRITE(DP_A, dpa_ctl);
1403         udelay(200);
1404 }
1405
1406
1407 static void igdng_set_pll_edp (struct drm_crtc *crtc, int clock)
1408 {
1409         struct drm_device *dev = crtc->dev;
1410         struct drm_i915_private *dev_priv = dev->dev_private;
1411         u32 dpa_ctl;
1412
1413         DRM_DEBUG("eDP PLL enable for clock %d\n", clock);
1414         dpa_ctl = I915_READ(DP_A);
1415         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1416
1417         if (clock < 200000) {
1418                 u32 temp;
1419                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1420                 /* workaround for 160Mhz:
1421                    1) program 0x4600c bits 15:0 = 0x8124
1422                    2) program 0x46010 bit 0 = 1
1423                    3) program 0x46034 bit 24 = 1
1424                    4) program 0x64000 bit 14 = 1
1425                    */
1426                 temp = I915_READ(0x4600c);
1427                 temp &= 0xffff0000;
1428                 I915_WRITE(0x4600c, temp | 0x8124);
1429
1430                 temp = I915_READ(0x46010);
1431                 I915_WRITE(0x46010, temp | 1);
1432
1433                 temp = I915_READ(0x46034);
1434                 I915_WRITE(0x46034, temp | (1 << 24));
1435         } else {
1436                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1437         }
1438         I915_WRITE(DP_A, dpa_ctl);
1439
1440         udelay(500);
1441 }
1442
1443 static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1444 {
1445         struct drm_device *dev = crtc->dev;
1446         struct drm_i915_private *dev_priv = dev->dev_private;
1447         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1448         int pipe = intel_crtc->pipe;
1449         int plane = intel_crtc->plane;
1450         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1451         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1452         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1453         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1454         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1455         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1456         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1457         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1458         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1459         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1460         int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1461         int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1462         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1463         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1464         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1465         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1466         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1467         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1468         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1469         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1470         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1471         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1472         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1473         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1474         u32 temp;
1475         int tries = 5, j, n;
1476
1477         /* XXX: When our outputs are all unaware of DPMS modes other than off
1478          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1479          */
1480         switch (mode) {
1481         case DRM_MODE_DPMS_ON:
1482         case DRM_MODE_DPMS_STANDBY:
1483         case DRM_MODE_DPMS_SUSPEND:
1484                 DRM_DEBUG("crtc %d dpms on\n", pipe);
1485                 if (HAS_eDP) {
1486                         /* enable eDP PLL */
1487                         igdng_enable_pll_edp(crtc);
1488                 } else {
1489                         /* enable PCH DPLL */
1490                         temp = I915_READ(pch_dpll_reg);
1491                         if ((temp & DPLL_VCO_ENABLE) == 0) {
1492                                 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1493                                 I915_READ(pch_dpll_reg);
1494                         }
1495
1496                         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1497                         temp = I915_READ(fdi_rx_reg);
1498                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
1499                                         FDI_SEL_PCDCLK |
1500                                         FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
1501                         I915_READ(fdi_rx_reg);
1502                         udelay(200);
1503
1504                         /* Enable CPU FDI TX PLL, always on for IGDNG */
1505                         temp = I915_READ(fdi_tx_reg);
1506                         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1507                                 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1508                                 I915_READ(fdi_tx_reg);
1509                                 udelay(100);
1510                         }
1511                 }
1512
1513                 /* Enable panel fitting for LVDS */
1514                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1515                         temp = I915_READ(pf_ctl_reg);
1516                         I915_WRITE(pf_ctl_reg, temp | PF_ENABLE);
1517
1518                         /* currently full aspect */
1519                         I915_WRITE(pf_win_pos, 0);
1520
1521                         I915_WRITE(pf_win_size,
1522                                    (dev_priv->panel_fixed_mode->hdisplay << 16) |
1523                                    (dev_priv->panel_fixed_mode->vdisplay));
1524                 }
1525
1526                 /* Enable CPU pipe */
1527                 temp = I915_READ(pipeconf_reg);
1528                 if ((temp & PIPEACONF_ENABLE) == 0) {
1529                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1530                         I915_READ(pipeconf_reg);
1531                         udelay(100);
1532                 }
1533
1534                 /* configure and enable CPU plane */
1535                 temp = I915_READ(dspcntr_reg);
1536                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1537                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1538                         /* Flush the plane changes */
1539                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1540                 }
1541
1542                 if (!HAS_eDP) {
1543                         /* enable CPU FDI TX and PCH FDI RX */
1544                         temp = I915_READ(fdi_tx_reg);
1545                         temp |= FDI_TX_ENABLE;
1546                         temp |= FDI_DP_PORT_WIDTH_X4; /* default */
1547                         temp &= ~FDI_LINK_TRAIN_NONE;
1548                         temp |= FDI_LINK_TRAIN_PATTERN_1;
1549                         I915_WRITE(fdi_tx_reg, temp);
1550                         I915_READ(fdi_tx_reg);
1551
1552                         temp = I915_READ(fdi_rx_reg);
1553                         temp &= ~FDI_LINK_TRAIN_NONE;
1554                         temp |= FDI_LINK_TRAIN_PATTERN_1;
1555                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1556                         I915_READ(fdi_rx_reg);
1557
1558                         udelay(150);
1559
1560                         /* Train FDI. */
1561                         /* umask FDI RX Interrupt symbol_lock and bit_lock bit
1562                            for train result */
1563                         temp = I915_READ(fdi_rx_imr_reg);
1564                         temp &= ~FDI_RX_SYMBOL_LOCK;
1565                         temp &= ~FDI_RX_BIT_LOCK;
1566                         I915_WRITE(fdi_rx_imr_reg, temp);
1567                         I915_READ(fdi_rx_imr_reg);
1568                         udelay(150);
1569
1570                         temp = I915_READ(fdi_rx_iir_reg);
1571                         DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1572
1573                         if ((temp & FDI_RX_BIT_LOCK) == 0) {
1574                                 for (j = 0; j < tries; j++) {
1575                                         temp = I915_READ(fdi_rx_iir_reg);
1576                                         DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1577                                         if (temp & FDI_RX_BIT_LOCK)
1578                                                 break;
1579                                         udelay(200);
1580                                 }
1581                                 if (j != tries)
1582                                         I915_WRITE(fdi_rx_iir_reg,
1583                                                         temp | FDI_RX_BIT_LOCK);
1584                                 else
1585                                         DRM_DEBUG("train 1 fail\n");
1586                         } else {
1587                                 I915_WRITE(fdi_rx_iir_reg,
1588                                                 temp | FDI_RX_BIT_LOCK);
1589                                 DRM_DEBUG("train 1 ok 2!\n");
1590                         }
1591                         temp = I915_READ(fdi_tx_reg);
1592                         temp &= ~FDI_LINK_TRAIN_NONE;
1593                         temp |= FDI_LINK_TRAIN_PATTERN_2;
1594                         I915_WRITE(fdi_tx_reg, temp);
1595
1596                         temp = I915_READ(fdi_rx_reg);
1597                         temp &= ~FDI_LINK_TRAIN_NONE;
1598                         temp |= FDI_LINK_TRAIN_PATTERN_2;
1599                         I915_WRITE(fdi_rx_reg, temp);
1600
1601                         udelay(150);
1602
1603                         temp = I915_READ(fdi_rx_iir_reg);
1604                         DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1605
1606                         if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
1607                                 for (j = 0; j < tries; j++) {
1608                                         temp = I915_READ(fdi_rx_iir_reg);
1609                                         DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1610                                         if (temp & FDI_RX_SYMBOL_LOCK)
1611                                                 break;
1612                                         udelay(200);
1613                                 }
1614                                 if (j != tries) {
1615                                         I915_WRITE(fdi_rx_iir_reg,
1616                                                         temp | FDI_RX_SYMBOL_LOCK);
1617                                         DRM_DEBUG("train 2 ok 1!\n");
1618                                 } else
1619                                         DRM_DEBUG("train 2 fail\n");
1620                         } else {
1621                                 I915_WRITE(fdi_rx_iir_reg,
1622                                                 temp | FDI_RX_SYMBOL_LOCK);
1623                                 DRM_DEBUG("train 2 ok 2!\n");
1624                         }
1625                         DRM_DEBUG("train done\n");
1626
1627                         /* set transcoder timing */
1628                         I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1629                         I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1630                         I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1631
1632                         I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1633                         I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1634                         I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1635
1636                         /* enable PCH transcoder */
1637                         temp = I915_READ(transconf_reg);
1638                         I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1639                         I915_READ(transconf_reg);
1640
1641                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1642                                 ;
1643
1644                         /* enable normal */
1645
1646                         temp = I915_READ(fdi_tx_reg);
1647                         temp &= ~FDI_LINK_TRAIN_NONE;
1648                         I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1649                                         FDI_TX_ENHANCE_FRAME_ENABLE);
1650                         I915_READ(fdi_tx_reg);
1651
1652                         temp = I915_READ(fdi_rx_reg);
1653                         temp &= ~FDI_LINK_TRAIN_NONE;
1654                         I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
1655                                         FDI_RX_ENHANCE_FRAME_ENABLE);
1656                         I915_READ(fdi_rx_reg);
1657
1658                         /* wait one idle pattern time */
1659                         udelay(100);
1660
1661                 }
1662
1663                 intel_crtc_load_lut(crtc);
1664
1665         break;
1666         case DRM_MODE_DPMS_OFF:
1667                 DRM_DEBUG("crtc %d dpms off\n", pipe);
1668
1669                 i915_disable_vga(dev);
1670
1671                 /* Disable display plane */
1672                 temp = I915_READ(dspcntr_reg);
1673                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1674                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1675                         /* Flush the plane changes */
1676                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1677                         I915_READ(dspbase_reg);
1678                 }
1679
1680                 /* disable cpu pipe, disable after all planes disabled */
1681                 temp = I915_READ(pipeconf_reg);
1682                 if ((temp & PIPEACONF_ENABLE) != 0) {
1683                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1684                         I915_READ(pipeconf_reg);
1685                         n = 0;
1686                         /* wait for cpu pipe off, pipe state */
1687                         while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
1688                                 n++;
1689                                 if (n < 60) {
1690                                         udelay(500);
1691                                         continue;
1692                                 } else {
1693                                         DRM_DEBUG("pipe %d off delay\n", pipe);
1694                                         break;
1695                                 }
1696                         }
1697                 } else
1698                         DRM_DEBUG("crtc %d is disabled\n", pipe);
1699
1700                 if (HAS_eDP) {
1701                         igdng_disable_pll_edp(crtc);
1702                 }
1703
1704                 /* disable CPU FDI tx and PCH FDI rx */
1705                 temp = I915_READ(fdi_tx_reg);
1706                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
1707                 I915_READ(fdi_tx_reg);
1708
1709                 temp = I915_READ(fdi_rx_reg);
1710                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
1711                 I915_READ(fdi_rx_reg);
1712
1713                 udelay(100);
1714
1715                 /* still set train pattern 1 */
1716                 temp = I915_READ(fdi_tx_reg);
1717                 temp &= ~FDI_LINK_TRAIN_NONE;
1718                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1719                 I915_WRITE(fdi_tx_reg, temp);
1720
1721                 temp = I915_READ(fdi_rx_reg);
1722                 temp &= ~FDI_LINK_TRAIN_NONE;
1723                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1724                 I915_WRITE(fdi_rx_reg, temp);
1725
1726                 udelay(100);
1727
1728                 /* disable PCH transcoder */
1729                 temp = I915_READ(transconf_reg);
1730                 if ((temp & TRANS_ENABLE) != 0) {
1731                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
1732                         I915_READ(transconf_reg);
1733                         n = 0;
1734                         /* wait for PCH transcoder off, transcoder state */
1735                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
1736                                 n++;
1737                                 if (n < 60) {
1738                                         udelay(500);
1739                                         continue;
1740                                 } else {
1741                                         DRM_DEBUG("transcoder %d off delay\n", pipe);
1742                                         break;
1743                                 }
1744                         }
1745                 }
1746
1747                 /* disable PCH DPLL */
1748                 temp = I915_READ(pch_dpll_reg);
1749                 if ((temp & DPLL_VCO_ENABLE) != 0) {
1750                         I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
1751                         I915_READ(pch_dpll_reg);
1752                 }
1753
1754                 temp = I915_READ(fdi_rx_reg);
1755                 if ((temp & FDI_RX_PLL_ENABLE) != 0) {
1756                         temp &= ~FDI_SEL_PCDCLK;
1757                         temp &= ~FDI_RX_PLL_ENABLE;
1758                         I915_WRITE(fdi_rx_reg, temp);
1759                         I915_READ(fdi_rx_reg);
1760                 }
1761
1762                 /* Disable CPU FDI TX PLL */
1763                 temp = I915_READ(fdi_tx_reg);
1764                 if ((temp & FDI_TX_PLL_ENABLE) != 0) {
1765                         I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
1766                         I915_READ(fdi_tx_reg);
1767                         udelay(100);
1768                 }
1769
1770                 /* Disable PF */
1771                 temp = I915_READ(pf_ctl_reg);
1772                 if ((temp & PF_ENABLE) != 0) {
1773                         I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1774                         I915_READ(pf_ctl_reg);
1775                 }
1776                 I915_WRITE(pf_win_size, 0);
1777
1778                 /* Wait for the clocks to turn off. */
1779                 udelay(150);
1780                 break;
1781         }
1782 }
1783
1784 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1785 {
1786         struct drm_device *dev = crtc->dev;
1787         struct drm_i915_private *dev_priv = dev->dev_private;
1788         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1789         int pipe = intel_crtc->pipe;
1790         int plane = intel_crtc->plane;
1791         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
1792         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1793         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1794         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1795         u32 temp;
1796
1797         /* XXX: When our outputs are all unaware of DPMS modes other than off
1798          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1799          */
1800         switch (mode) {
1801         case DRM_MODE_DPMS_ON:
1802         case DRM_MODE_DPMS_STANDBY:
1803         case DRM_MODE_DPMS_SUSPEND:
1804                 /* Enable the DPLL */
1805                 temp = I915_READ(dpll_reg);
1806                 if ((temp & DPLL_VCO_ENABLE) == 0) {
1807                         I915_WRITE(dpll_reg, temp);
1808                         I915_READ(dpll_reg);
1809                         /* Wait for the clocks to stabilize. */
1810                         udelay(150);
1811                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1812                         I915_READ(dpll_reg);
1813                         /* Wait for the clocks to stabilize. */
1814                         udelay(150);
1815                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1816                         I915_READ(dpll_reg);
1817                         /* Wait for the clocks to stabilize. */
1818                         udelay(150);
1819                 }
1820
1821                 /* Enable the pipe */
1822                 temp = I915_READ(pipeconf_reg);
1823                 if ((temp & PIPEACONF_ENABLE) == 0)
1824                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1825
1826                 /* Enable the plane */
1827                 temp = I915_READ(dspcntr_reg);
1828                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1829                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1830                         /* Flush the plane changes */
1831                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1832                 }
1833
1834                 intel_crtc_load_lut(crtc);
1835
1836                 if ((IS_I965G(dev) || plane == 0))
1837                         intel_update_fbc(crtc, &crtc->mode);
1838
1839                 /* Give the overlay scaler a chance to enable if it's on this pipe */
1840                 //intel_crtc_dpms_video(crtc, true); TODO
1841                 intel_update_watermarks(dev);
1842         break;
1843         case DRM_MODE_DPMS_OFF:
1844                 intel_update_watermarks(dev);
1845                 /* Give the overlay scaler a chance to disable if it's on this pipe */
1846                 //intel_crtc_dpms_video(crtc, FALSE); TODO
1847
1848                 if (dev_priv->cfb_plane == plane &&
1849                     dev_priv->display.disable_fbc)
1850                         dev_priv->display.disable_fbc(dev);
1851
1852                 /* Disable the VGA plane that we never use */
1853                 i915_disable_vga(dev);
1854
1855                 /* Disable display plane */
1856                 temp = I915_READ(dspcntr_reg);
1857                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1858                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1859                         /* Flush the plane changes */
1860                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1861                         I915_READ(dspbase_reg);
1862                 }
1863
1864                 if (!IS_I9XX(dev)) {
1865                         /* Wait for vblank for the disable to take effect */
1866                         intel_wait_for_vblank(dev);
1867                 }
1868
1869                 /* Next, disable display pipes */
1870                 temp = I915_READ(pipeconf_reg);
1871                 if ((temp & PIPEACONF_ENABLE) != 0) {
1872                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1873                         I915_READ(pipeconf_reg);
1874                 }
1875
1876                 /* Wait for vblank for the disable to take effect. */
1877                 intel_wait_for_vblank(dev);
1878
1879                 temp = I915_READ(dpll_reg);
1880                 if ((temp & DPLL_VCO_ENABLE) != 0) {
1881                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
1882                         I915_READ(dpll_reg);
1883                 }
1884
1885                 /* Wait for the clocks to turn off. */
1886                 udelay(150);
1887                 break;
1888         }
1889 }
1890
1891 /**
1892  * Sets the power management mode of the pipe and plane.
1893  *
1894  * This code should probably grow support for turning the cursor off and back
1895  * on appropriately at the same time as we're turning the pipe off/on.
1896  */
1897 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
1898 {
1899         struct drm_device *dev = crtc->dev;
1900         struct drm_i915_private *dev_priv = dev->dev_private;
1901         struct drm_i915_master_private *master_priv;
1902         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1903         int pipe = intel_crtc->pipe;
1904         bool enabled;
1905
1906         dev_priv->display.dpms(crtc, mode);
1907
1908         intel_crtc->dpms_mode = mode;
1909
1910         if (!dev->primary->master)
1911                 return;
1912
1913         master_priv = dev->primary->master->driver_priv;
1914         if (!master_priv->sarea_priv)
1915                 return;
1916
1917         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
1918
1919         switch (pipe) {
1920         case 0:
1921                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
1922                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
1923                 break;
1924         case 1:
1925                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
1926                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
1927                 break;
1928         default:
1929                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
1930                 break;
1931         }
1932 }
1933
1934 static void intel_crtc_prepare (struct drm_crtc *crtc)
1935 {
1936         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1937         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
1938 }
1939
1940 static void intel_crtc_commit (struct drm_crtc *crtc)
1941 {
1942         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1943         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1944 }
1945
1946 void intel_encoder_prepare (struct drm_encoder *encoder)
1947 {
1948         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1949         /* lvds has its own version of prepare see intel_lvds_prepare */
1950         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
1951 }
1952
1953 void intel_encoder_commit (struct drm_encoder *encoder)
1954 {
1955         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1956         /* lvds has its own version of commit see intel_lvds_commit */
1957         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
1958 }
1959
1960 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
1961                                   struct drm_display_mode *mode,
1962                                   struct drm_display_mode *adjusted_mode)
1963 {
1964         struct drm_device *dev = crtc->dev;
1965         if (IS_IGDNG(dev)) {
1966                 /* FDI link clock is fixed at 2.7G */
1967                 if (mode->clock * 3 > 27000 * 4)
1968                         return MODE_CLOCK_HIGH;
1969         }
1970         return true;
1971 }
1972
1973 static int i945_get_display_clock_speed(struct drm_device *dev)
1974 {
1975         return 400000;
1976 }
1977
1978 static int i915_get_display_clock_speed(struct drm_device *dev)
1979 {
1980         return 333000;
1981 }
1982
1983 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
1984 {
1985         return 200000;
1986 }
1987
1988 static int i915gm_get_display_clock_speed(struct drm_device *dev)
1989 {
1990         u16 gcfgc = 0;
1991
1992         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
1993
1994         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
1995                 return 133000;
1996         else {
1997                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
1998                 case GC_DISPLAY_CLOCK_333_MHZ:
1999                         return 333000;
2000                 default:
2001                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2002                         return 190000;
2003                 }
2004         }
2005 }
2006
2007 static int i865_get_display_clock_speed(struct drm_device *dev)
2008 {
2009         return 266000;
2010 }
2011
2012 static int i855_get_display_clock_speed(struct drm_device *dev)
2013 {
2014         u16 hpllcc = 0;
2015         /* Assume that the hardware is in the high speed state.  This
2016          * should be the default.
2017          */
2018         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2019         case GC_CLOCK_133_200:
2020         case GC_CLOCK_100_200:
2021                 return 200000;
2022         case GC_CLOCK_166_250:
2023                 return 250000;
2024         case GC_CLOCK_100_133:
2025                 return 133000;
2026         }
2027
2028         /* Shouldn't happen */
2029         return 0;
2030 }
2031
2032 static int i830_get_display_clock_speed(struct drm_device *dev)
2033 {
2034         return 133000;
2035 }
2036
2037 /**
2038  * Return the pipe currently connected to the panel fitter,
2039  * or -1 if the panel fitter is not present or not in use
2040  */
2041 static int intel_panel_fitter_pipe (struct drm_device *dev)
2042 {
2043         struct drm_i915_private *dev_priv = dev->dev_private;
2044         u32  pfit_control;
2045
2046         /* i830 doesn't have a panel fitter */
2047         if (IS_I830(dev))
2048                 return -1;
2049
2050         pfit_control = I915_READ(PFIT_CONTROL);
2051
2052         /* See if the panel fitter is in use */
2053         if ((pfit_control & PFIT_ENABLE) == 0)
2054                 return -1;
2055
2056         /* 965 can place panel fitter on either pipe */
2057         if (IS_I965G(dev))
2058                 return (pfit_control >> 29) & 0x3;
2059
2060         /* older chips can only use pipe 1 */
2061         return 1;
2062 }
2063
2064 struct fdi_m_n {
2065         u32        tu;
2066         u32        gmch_m;
2067         u32        gmch_n;
2068         u32        link_m;
2069         u32        link_n;
2070 };
2071
2072 static void
2073 fdi_reduce_ratio(u32 *num, u32 *den)
2074 {
2075         while (*num > 0xffffff || *den > 0xffffff) {
2076                 *num >>= 1;
2077                 *den >>= 1;
2078         }
2079 }
2080
2081 #define DATA_N 0x800000
2082 #define LINK_N 0x80000
2083
2084 static void
2085 igdng_compute_m_n(int bits_per_pixel, int nlanes,
2086                 int pixel_clock, int link_clock,
2087                 struct fdi_m_n *m_n)
2088 {
2089         u64 temp;
2090
2091         m_n->tu = 64; /* default size */
2092
2093         temp = (u64) DATA_N * pixel_clock;
2094         temp = div_u64(temp, link_clock);
2095         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2096         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2097         m_n->gmch_n = DATA_N;
2098         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2099
2100         temp = (u64) LINK_N * pixel_clock;
2101         m_n->link_m = div_u64(temp, link_clock);
2102         m_n->link_n = LINK_N;
2103         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2104 }
2105
2106
2107 struct intel_watermark_params {
2108         unsigned long fifo_size;
2109         unsigned long max_wm;
2110         unsigned long default_wm;
2111         unsigned long guard_size;
2112         unsigned long cacheline_size;
2113 };
2114
2115 /* IGD has different values for various configs */
2116 static struct intel_watermark_params igd_display_wm = {
2117         IGD_DISPLAY_FIFO,
2118         IGD_MAX_WM,
2119         IGD_DFT_WM,
2120         IGD_GUARD_WM,
2121         IGD_FIFO_LINE_SIZE
2122 };
2123 static struct intel_watermark_params igd_display_hplloff_wm = {
2124         IGD_DISPLAY_FIFO,
2125         IGD_MAX_WM,
2126         IGD_DFT_HPLLOFF_WM,
2127         IGD_GUARD_WM,
2128         IGD_FIFO_LINE_SIZE
2129 };
2130 static struct intel_watermark_params igd_cursor_wm = {
2131         IGD_CURSOR_FIFO,
2132         IGD_CURSOR_MAX_WM,
2133         IGD_CURSOR_DFT_WM,
2134         IGD_CURSOR_GUARD_WM,
2135         IGD_FIFO_LINE_SIZE,
2136 };
2137 static struct intel_watermark_params igd_cursor_hplloff_wm = {
2138         IGD_CURSOR_FIFO,
2139         IGD_CURSOR_MAX_WM,
2140         IGD_CURSOR_DFT_WM,
2141         IGD_CURSOR_GUARD_WM,
2142         IGD_FIFO_LINE_SIZE
2143 };
2144 static struct intel_watermark_params i945_wm_info = {
2145         I945_FIFO_SIZE,
2146         I915_MAX_WM,
2147         1,
2148         2,
2149         I915_FIFO_LINE_SIZE
2150 };
2151 static struct intel_watermark_params i915_wm_info = {
2152         I915_FIFO_SIZE,
2153         I915_MAX_WM,
2154         1,
2155         2,
2156         I915_FIFO_LINE_SIZE
2157 };
2158 static struct intel_watermark_params i855_wm_info = {
2159         I855GM_FIFO_SIZE,
2160         I915_MAX_WM,
2161         1,
2162         2,
2163         I830_FIFO_LINE_SIZE
2164 };
2165 static struct intel_watermark_params i830_wm_info = {
2166         I830_FIFO_SIZE,
2167         I915_MAX_WM,
2168         1,
2169         2,
2170         I830_FIFO_LINE_SIZE
2171 };
2172
2173 /**
2174  * intel_calculate_wm - calculate watermark level
2175  * @clock_in_khz: pixel clock
2176  * @wm: chip FIFO params
2177  * @pixel_size: display pixel size
2178  * @latency_ns: memory latency for the platform
2179  *
2180  * Calculate the watermark level (the level at which the display plane will
2181  * start fetching from memory again).  Each chip has a different display
2182  * FIFO size and allocation, so the caller needs to figure that out and pass
2183  * in the correct intel_watermark_params structure.
2184  *
2185  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2186  * on the pixel size.  When it reaches the watermark level, it'll start
2187  * fetching FIFO line sized based chunks from memory until the FIFO fills
2188  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2189  * will occur, and a display engine hang could result.
2190  */
2191 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2192                                         struct intel_watermark_params *wm,
2193                                         int pixel_size,
2194                                         unsigned long latency_ns)
2195 {
2196         long entries_required, wm_size;
2197
2198         /*
2199          * Note: we need to make sure we don't overflow for various clock &
2200          * latency values.
2201          * clocks go from a few thousand to several hundred thousand.
2202          * latency is usually a few thousand
2203          */
2204         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2205                 1000;
2206         entries_required /= wm->cacheline_size;
2207
2208         DRM_DEBUG("FIFO entries required for mode: %d\n", entries_required);
2209
2210         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2211
2212         DRM_DEBUG("FIFO watermark level: %d\n", wm_size);
2213
2214         /* Don't promote wm_size to unsigned... */
2215         if (wm_size > (long)wm->max_wm)
2216                 wm_size = wm->max_wm;
2217         if (wm_size <= 0)
2218                 wm_size = wm->default_wm;
2219         return wm_size;
2220 }
2221
2222 struct cxsr_latency {
2223         int is_desktop;
2224         unsigned long fsb_freq;
2225         unsigned long mem_freq;
2226         unsigned long display_sr;
2227         unsigned long display_hpll_disable;
2228         unsigned long cursor_sr;
2229         unsigned long cursor_hpll_disable;
2230 };
2231
2232 static struct cxsr_latency cxsr_latency_table[] = {
2233         {1, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2234         {1, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2235         {1, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2236
2237         {1, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2238         {1, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2239         {1, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2240
2241         {1, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2242         {1, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2243         {1, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2244
2245         {0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2246         {0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2247         {0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2248
2249         {0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2250         {0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2251         {0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2252
2253         {0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2254         {0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2255         {0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2256 };
2257
2258 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
2259                                                    int mem)
2260 {
2261         int i;
2262         struct cxsr_latency *latency;
2263
2264         if (fsb == 0 || mem == 0)
2265                 return NULL;
2266
2267         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2268                 latency = &cxsr_latency_table[i];
2269                 if (is_desktop == latency->is_desktop &&
2270                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2271                         return latency;
2272         }
2273
2274         DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
2275
2276         return NULL;
2277 }
2278
2279 static void igd_disable_cxsr(struct drm_device *dev)
2280 {
2281         struct drm_i915_private *dev_priv = dev->dev_private;
2282         u32 reg;
2283
2284         /* deactivate cxsr */
2285         reg = I915_READ(DSPFW3);
2286         reg &= ~(IGD_SELF_REFRESH_EN);
2287         I915_WRITE(DSPFW3, reg);
2288         DRM_INFO("Big FIFO is disabled\n");
2289 }
2290
2291 static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
2292                             int pixel_size)
2293 {
2294         struct drm_i915_private *dev_priv = dev->dev_private;
2295         u32 reg;
2296         unsigned long wm;
2297         struct cxsr_latency *latency;
2298
2299         latency = intel_get_cxsr_latency(IS_IGDG(dev), dev_priv->fsb_freq,
2300                 dev_priv->mem_freq);
2301         if (!latency) {
2302                 DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
2303                 igd_disable_cxsr(dev);
2304                 return;
2305         }
2306
2307         /* Display SR */
2308         wm = intel_calculate_wm(clock, &igd_display_wm, pixel_size,
2309                                 latency->display_sr);
2310         reg = I915_READ(DSPFW1);
2311         reg &= 0x7fffff;
2312         reg |= wm << 23;
2313         I915_WRITE(DSPFW1, reg);
2314         DRM_DEBUG("DSPFW1 register is %x\n", reg);
2315
2316         /* cursor SR */
2317         wm = intel_calculate_wm(clock, &igd_cursor_wm, pixel_size,
2318                                 latency->cursor_sr);
2319         reg = I915_READ(DSPFW3);
2320         reg &= ~(0x3f << 24);
2321         reg |= (wm & 0x3f) << 24;
2322         I915_WRITE(DSPFW3, reg);
2323
2324         /* Display HPLL off SR */
2325         wm = intel_calculate_wm(clock, &igd_display_hplloff_wm,
2326                 latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
2327         reg = I915_READ(DSPFW3);
2328         reg &= 0xfffffe00;
2329         reg |= wm & 0x1ff;
2330         I915_WRITE(DSPFW3, reg);
2331
2332         /* cursor HPLL off SR */
2333         wm = intel_calculate_wm(clock, &igd_cursor_hplloff_wm, pixel_size,
2334                                 latency->cursor_hpll_disable);
2335         reg = I915_READ(DSPFW3);
2336         reg &= ~(0x3f << 16);
2337         reg |= (wm & 0x3f) << 16;
2338         I915_WRITE(DSPFW3, reg);
2339         DRM_DEBUG("DSPFW3 register is %x\n", reg);
2340
2341         /* activate cxsr */
2342         reg = I915_READ(DSPFW3);
2343         reg |= IGD_SELF_REFRESH_EN;
2344         I915_WRITE(DSPFW3, reg);
2345
2346         DRM_INFO("Big FIFO is enabled\n");
2347
2348         return;
2349 }
2350
2351 /*
2352  * Latency for FIFO fetches is dependent on several factors:
2353  *   - memory configuration (speed, channels)
2354  *   - chipset
2355  *   - current MCH state
2356  * It can be fairly high in some situations, so here we assume a fairly
2357  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2358  * set this value too high, the FIFO will fetch frequently to stay full)
2359  * and power consumption (set it too low to save power and we might see
2360  * FIFO underruns and display "flicker").
2361  *
2362  * A value of 5us seems to be a good balance; safe for very low end
2363  * platforms but not overly aggressive on lower latency configs.
2364  */
2365 const static int latency_ns = 5000;
2366
2367 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2368 {
2369         struct drm_i915_private *dev_priv = dev->dev_private;
2370         uint32_t dsparb = I915_READ(DSPARB);
2371         int size;
2372
2373         if (plane == 0)
2374                 size = dsparb & 0x7f;
2375         else
2376                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2377                         (dsparb & 0x7f);
2378
2379         DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
2380                   size);
2381
2382         return size;
2383 }
2384
2385 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2386 {
2387         struct drm_i915_private *dev_priv = dev->dev_private;
2388         uint32_t dsparb = I915_READ(DSPARB);
2389         int size;
2390
2391         if (plane == 0)
2392                 size = dsparb & 0x1ff;
2393         else
2394                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2395                         (dsparb & 0x1ff);
2396         size >>= 1; /* Convert to cachelines */
2397
2398         DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
2399                   size);
2400
2401         return size;
2402 }
2403
2404 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2405 {
2406         struct drm_i915_private *dev_priv = dev->dev_private;
2407         uint32_t dsparb = I915_READ(DSPARB);
2408         int size;
2409
2410         size = dsparb & 0x7f;
2411         size >>= 2; /* Convert to cachelines */
2412
2413         DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
2414                   size);
2415
2416         return size;
2417 }
2418
2419 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2420 {
2421         struct drm_i915_private *dev_priv = dev->dev_private;
2422         uint32_t dsparb = I915_READ(DSPARB);
2423         int size;
2424
2425         size = dsparb & 0x7f;
2426         size >>= 1; /* Convert to cachelines */
2427
2428         DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
2429                   size);
2430
2431         return size;
2432 }
2433
2434 static void g4x_update_wm(struct drm_device *dev, int unused, int unused2,
2435                           int unused3, int unused4)
2436 {
2437         struct drm_i915_private *dev_priv = dev->dev_private;
2438         u32 fw_blc_self = I915_READ(FW_BLC_SELF);
2439
2440         if (i915_powersave)
2441                 fw_blc_self |= FW_BLC_SELF_EN;
2442         else
2443                 fw_blc_self &= ~FW_BLC_SELF_EN;
2444         I915_WRITE(FW_BLC_SELF, fw_blc_self);
2445 }
2446
2447 static void i965_update_wm(struct drm_device *dev, int unused, int unused2,
2448                            int unused3, int unused4)
2449 {
2450         struct drm_i915_private *dev_priv = dev->dev_private;
2451
2452         DRM_DEBUG("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 8\n");
2453
2454         /* 965 has limitations... */
2455         I915_WRITE(DSPFW1, (8 << 16) | (8 << 8) | (8 << 0));
2456         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
2457 }
2458
2459 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2460                            int planeb_clock, int sr_hdisplay, int pixel_size)
2461 {
2462         struct drm_i915_private *dev_priv = dev->dev_private;
2463         uint32_t fwater_lo;
2464         uint32_t fwater_hi;
2465         int total_size, cacheline_size, cwm, srwm = 1;
2466         int planea_wm, planeb_wm;
2467         struct intel_watermark_params planea_params, planeb_params;
2468         unsigned long line_time_us;
2469         int sr_clock, sr_entries = 0;
2470
2471         /* Create copies of the base settings for each pipe */
2472         if (IS_I965GM(dev) || IS_I945GM(dev))
2473                 planea_params = planeb_params = i945_wm_info;
2474         else if (IS_I9XX(dev))
2475                 planea_params = planeb_params = i915_wm_info;
2476         else
2477                 planea_params = planeb_params = i855_wm_info;
2478
2479         /* Grab a couple of global values before we overwrite them */
2480         total_size = planea_params.fifo_size;
2481         cacheline_size = planea_params.cacheline_size;
2482
2483         /* Update per-plane FIFO sizes */
2484         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2485         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
2486
2487         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
2488                                        pixel_size, latency_ns);
2489         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
2490                                        pixel_size, latency_ns);
2491         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2492
2493         /*
2494          * Overlay gets an aggressive default since video jitter is bad.
2495          */
2496         cwm = 2;
2497
2498         /* Calc sr entries for one plane configs */
2499         if (HAS_FW_BLC(dev) && sr_hdisplay &&
2500             (!planea_clock || !planeb_clock)) {
2501                 /* self-refresh has much higher latency */
2502                 const static int sr_latency_ns = 6000;
2503
2504                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2505                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2506
2507                 /* Use ns/us then divide to preserve precision */
2508                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2509                               pixel_size * sr_hdisplay) / 1000;
2510                 sr_entries = roundup(sr_entries / cacheline_size, 1);
2511                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2512                 srwm = total_size - sr_entries;
2513                 if (srwm < 0)
2514                         srwm = 1;
2515                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f));
2516         }
2517
2518         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2519                   planea_wm, planeb_wm, cwm, srwm);
2520
2521         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
2522         fwater_hi = (cwm & 0x1f);
2523
2524         /* Set request length to 8 cachelines per fetch */
2525         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
2526         fwater_hi = fwater_hi | (1 << 8);
2527
2528         I915_WRITE(FW_BLC, fwater_lo);
2529         I915_WRITE(FW_BLC2, fwater_hi);
2530 }
2531
2532 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
2533                            int unused2, int pixel_size)
2534 {
2535         struct drm_i915_private *dev_priv = dev->dev_private;
2536         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
2537         int planea_wm;
2538
2539         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2540
2541         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
2542                                        pixel_size, latency_ns);
2543         fwater_lo |= (3<<8) | planea_wm;
2544
2545         DRM_DEBUG("Setting FIFO watermarks - A: %d\n", planea_wm);
2546
2547         I915_WRITE(FW_BLC, fwater_lo);
2548 }
2549
2550 /**
2551  * intel_update_watermarks - update FIFO watermark values based on current modes
2552  *
2553  * Calculate watermark values for the various WM regs based on current mode
2554  * and plane configuration.
2555  *
2556  * There are several cases to deal with here:
2557  *   - normal (i.e. non-self-refresh)
2558  *   - self-refresh (SR) mode
2559  *   - lines are large relative to FIFO size (buffer can hold up to 2)
2560  *   - lines are small relative to FIFO size (buffer can hold more than 2
2561  *     lines), so need to account for TLB latency
2562  *
2563  *   The normal calculation is:
2564  *     watermark = dotclock * bytes per pixel * latency
2565  *   where latency is platform & configuration dependent (we assume pessimal
2566  *   values here).
2567  *
2568  *   The SR calculation is:
2569  *     watermark = (trunc(latency/line time)+1) * surface width *
2570  *       bytes per pixel
2571  *   where
2572  *     line time = htotal / dotclock
2573  *   and latency is assumed to be high, as above.
2574  *
2575  * The final value programmed to the register should always be rounded up,
2576  * and include an extra 2 entries to account for clock crossings.
2577  *
2578  * We don't use the sprite, so we can ignore that.  And on Crestline we have
2579  * to set the non-SR watermarks to 8.
2580   */
2581 static void intel_update_watermarks(struct drm_device *dev)
2582 {
2583         struct drm_i915_private *dev_priv = dev->dev_private;
2584         struct drm_crtc *crtc;
2585         struct intel_crtc *intel_crtc;
2586         int sr_hdisplay = 0;
2587         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
2588         int enabled = 0, pixel_size = 0;
2589
2590         if (!dev_priv->display.update_wm)
2591                 return;
2592
2593         /* Get the clock config from both planes */
2594         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2595                 intel_crtc = to_intel_crtc(crtc);
2596                 if (crtc->enabled) {
2597                         enabled++;
2598                         if (intel_crtc->plane == 0) {
2599                                 DRM_DEBUG("plane A (pipe %d) clock: %d\n",
2600                                           intel_crtc->pipe, crtc->mode.clock);
2601                                 planea_clock = crtc->mode.clock;
2602                         } else {
2603                                 DRM_DEBUG("plane B (pipe %d) clock: %d\n",
2604                                           intel_crtc->pipe, crtc->mode.clock);
2605                                 planeb_clock = crtc->mode.clock;
2606                         }
2607                         sr_hdisplay = crtc->mode.hdisplay;
2608                         sr_clock = crtc->mode.clock;
2609                         if (crtc->fb)
2610                                 pixel_size = crtc->fb->bits_per_pixel / 8;
2611                         else
2612                                 pixel_size = 4; /* by default */
2613                 }
2614         }
2615
2616         if (enabled <= 0)
2617                 return;
2618
2619         /* Single plane configs can enable self refresh */
2620         if (enabled == 1 && IS_IGD(dev))
2621                 igd_enable_cxsr(dev, sr_clock, pixel_size);
2622         else if (IS_IGD(dev))
2623                 igd_disable_cxsr(dev);
2624
2625         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
2626                                     sr_hdisplay, pixel_size);
2627 }
2628
2629 static int intel_crtc_mode_set(struct drm_crtc *crtc,
2630                                struct drm_display_mode *mode,
2631                                struct drm_display_mode *adjusted_mode,
2632                                int x, int y,
2633                                struct drm_framebuffer *old_fb)
2634 {
2635         struct drm_device *dev = crtc->dev;
2636         struct drm_i915_private *dev_priv = dev->dev_private;
2637         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2638         int pipe = intel_crtc->pipe;
2639         int plane = intel_crtc->plane;
2640         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
2641         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2642         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
2643         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2644         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2645         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
2646         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
2647         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
2648         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
2649         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
2650         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
2651         int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
2652         int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
2653         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
2654         int refclk, num_outputs = 0;
2655         intel_clock_t clock, reduced_clock;
2656         u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
2657         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
2658         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
2659         bool is_edp = false;
2660         struct drm_mode_config *mode_config = &dev->mode_config;
2661         struct drm_connector *connector;
2662         const intel_limit_t *limit;
2663         int ret;
2664         struct fdi_m_n m_n = {0};
2665         int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
2666         int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
2667         int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
2668         int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
2669         int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
2670         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
2671         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
2672         int lvds_reg = LVDS;
2673         u32 temp;
2674         int sdvo_pixel_multiply;
2675         int target_clock;
2676
2677         drm_vblank_pre_modeset(dev, pipe);
2678
2679         list_for_each_entry(connector, &mode_config->connector_list, head) {
2680                 struct intel_output *intel_output = to_intel_output(connector);
2681
2682                 if (!connector->encoder || connector->encoder->crtc != crtc)
2683                         continue;
2684
2685                 switch (intel_output->type) {
2686                 case INTEL_OUTPUT_LVDS:
2687                         is_lvds = true;
2688                         break;
2689                 case INTEL_OUTPUT_SDVO:
2690                 case INTEL_OUTPUT_HDMI:
2691                         is_sdvo = true;
2692                         if (intel_output->needs_tv_clock)
2693                                 is_tv = true;
2694                         break;
2695                 case INTEL_OUTPUT_DVO:
2696                         is_dvo = true;
2697                         break;
2698                 case INTEL_OUTPUT_TVOUT:
2699                         is_tv = true;
2700                         break;
2701                 case INTEL_OUTPUT_ANALOG:
2702                         is_crt = true;
2703                         break;
2704                 case INTEL_OUTPUT_DISPLAYPORT:
2705                         is_dp = true;
2706                         break;
2707                 case INTEL_OUTPUT_EDP:
2708                         is_edp = true;
2709                         break;
2710                 }
2711
2712                 num_outputs++;
2713         }
2714
2715         if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
2716                 refclk = dev_priv->lvds_ssc_freq * 1000;
2717                 DRM_DEBUG("using SSC reference clock of %d MHz\n", refclk / 1000);
2718         } else if (IS_I9XX(dev)) {
2719                 refclk = 96000;
2720                 if (IS_IGDNG(dev))
2721                         refclk = 120000; /* 120Mhz refclk */
2722         } else {
2723                 refclk = 48000;
2724         }
2725
2726
2727         /*
2728          * Returns a set of divisors for the desired target clock with the given
2729          * refclk, or FALSE.  The returned values represent the clock equation:
2730          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
2731          */
2732         limit = intel_limit(crtc);
2733         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
2734         if (!ok) {
2735                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
2736                 drm_vblank_post_modeset(dev, pipe);
2737                 return -EINVAL;
2738         }
2739
2740         if (limit->find_reduced_pll && dev_priv->lvds_downclock_avail) {
2741                 memcpy(&reduced_clock, &clock, sizeof(intel_clock_t));
2742                 has_reduced_clock = limit->find_reduced_pll(limit, crtc,
2743                                                             (adjusted_mode->clock*3/4),
2744                                                             refclk,
2745                                                             &reduced_clock);
2746         }
2747
2748         /* SDVO TV has fixed PLL values depend on its clock range,
2749            this mirrors vbios setting. */
2750         if (is_sdvo && is_tv) {
2751                 if (adjusted_mode->clock >= 100000
2752                                 && adjusted_mode->clock < 140500) {
2753                         clock.p1 = 2;
2754                         clock.p2 = 10;
2755                         clock.n = 3;
2756                         clock.m1 = 16;
2757                         clock.m2 = 8;
2758                 } else if (adjusted_mode->clock >= 140500
2759                                 && adjusted_mode->clock <= 200000) {
2760                         clock.p1 = 1;
2761                         clock.p2 = 10;
2762                         clock.n = 6;
2763                         clock.m1 = 12;
2764                         clock.m2 = 8;
2765                 }
2766         }
2767
2768         /* FDI link */
2769         if (IS_IGDNG(dev)) {
2770                 int lane, link_bw, bpp;
2771                 /* eDP doesn't require FDI link, so just set DP M/N
2772                    according to current link config */
2773                 if (is_edp) {
2774                         struct drm_connector *edp;
2775                         target_clock = mode->clock;
2776                         edp = intel_pipe_get_output(crtc);
2777                         intel_edp_link_config(to_intel_output(edp),
2778                                         &lane, &link_bw);
2779                 } else {
2780                         /* DP over FDI requires target mode clock
2781                            instead of link clock */
2782                         if (is_dp)
2783                                 target_clock = mode->clock;
2784                         else
2785                                 target_clock = adjusted_mode->clock;
2786                         lane = 4;
2787                         link_bw = 270000;
2788                 }
2789
2790                 /* determine panel color depth */
2791                 temp = I915_READ(pipeconf_reg);
2792
2793                 switch (temp & PIPE_BPC_MASK) {
2794                 case PIPE_8BPC:
2795                         bpp = 24;
2796                         break;
2797                 case PIPE_10BPC:
2798                         bpp = 30;
2799                         break;
2800                 case PIPE_6BPC:
2801                         bpp = 18;
2802                         break;
2803                 case PIPE_12BPC:
2804                         bpp = 36;
2805                         break;
2806                 default:
2807                         DRM_ERROR("unknown pipe bpc value\n");
2808                         bpp = 24;
2809                 }
2810
2811                 igdng_compute_m_n(bpp, lane, target_clock,
2812                                   link_bw, &m_n);
2813         }
2814
2815         if (IS_IGD(dev)) {
2816                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
2817                 if (has_reduced_clock)
2818                         fp2 = (1 << reduced_clock.n) << 16 |
2819                                 reduced_clock.m1 << 8 | reduced_clock.m2;
2820         } else {
2821                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
2822                 if (has_reduced_clock)
2823                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
2824                                 reduced_clock.m2;
2825         }
2826
2827         if (!IS_IGDNG(dev))
2828                 dpll = DPLL_VGA_MODE_DIS;
2829
2830         if (IS_I9XX(dev)) {
2831                 if (is_lvds)
2832                         dpll |= DPLLB_MODE_LVDS;
2833                 else
2834                         dpll |= DPLLB_MODE_DAC_SERIAL;
2835                 if (is_sdvo) {
2836                         dpll |= DPLL_DVO_HIGH_SPEED;
2837                         sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
2838                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
2839                                 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
2840                         else if (IS_IGDNG(dev))
2841                                 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
2842                 }
2843                 if (is_dp)
2844                         dpll |= DPLL_DVO_HIGH_SPEED;
2845
2846                 /* compute bitmask from p1 value */
2847                 if (IS_IGD(dev))
2848                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD;
2849                 else {
2850                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2851                         /* also FPA1 */
2852                         if (IS_IGDNG(dev))
2853                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2854                         if (IS_G4X(dev) && has_reduced_clock)
2855                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2856                 }
2857                 switch (clock.p2) {
2858                 case 5:
2859                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
2860                         break;
2861                 case 7:
2862                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
2863                         break;
2864                 case 10:
2865                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
2866                         break;
2867                 case 14:
2868                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
2869                         break;
2870                 }
2871                 if (IS_I965G(dev) && !IS_IGDNG(dev))
2872                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
2873         } else {
2874                 if (is_lvds) {
2875                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2876                 } else {
2877                         if (clock.p1 == 2)
2878                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
2879                         else
2880                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2881                         if (clock.p2 == 4)
2882                                 dpll |= PLL_P2_DIVIDE_BY_4;
2883                 }
2884         }
2885
2886         if (is_sdvo && is_tv)
2887                 dpll |= PLL_REF_INPUT_TVCLKINBC;
2888         else if (is_tv)
2889                 /* XXX: just matching BIOS for now */
2890                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
2891                 dpll |= 3;
2892         else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
2893                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
2894         else
2895                 dpll |= PLL_REF_INPUT_DREFCLK;
2896
2897         /* setup pipeconf */
2898         pipeconf = I915_READ(pipeconf_reg);
2899
2900         /* Set up the display plane register */
2901         dspcntr = DISPPLANE_GAMMA_ENABLE;
2902
2903         /* IGDNG's plane is forced to pipe, bit 24 is to
2904            enable color space conversion */
2905         if (!IS_IGDNG(dev)) {
2906                 if (pipe == 0)
2907                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
2908                 else
2909                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2910         }
2911
2912         if (pipe == 0 && !IS_I965G(dev)) {
2913                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
2914                  * core speed.
2915                  *
2916                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
2917                  * pipe == 0 check?
2918                  */
2919                 if (mode->clock >
2920                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
2921                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
2922                 else
2923                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
2924         }
2925
2926         dspcntr |= DISPLAY_PLANE_ENABLE;
2927         pipeconf |= PIPEACONF_ENABLE;
2928         dpll |= DPLL_VCO_ENABLE;
2929
2930
2931         /* Disable the panel fitter if it was on our pipe */
2932         if (!IS_IGDNG(dev) && intel_panel_fitter_pipe(dev) == pipe)
2933                 I915_WRITE(PFIT_CONTROL, 0);
2934
2935         DRM_DEBUG("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
2936         drm_mode_debug_printmodeline(mode);
2937
2938         /* assign to IGDNG registers */
2939         if (IS_IGDNG(dev)) {
2940                 fp_reg = pch_fp_reg;
2941                 dpll_reg = pch_dpll_reg;
2942         }
2943
2944         if (is_edp) {
2945                 igdng_disable_pll_edp(crtc);
2946         } else if ((dpll & DPLL_VCO_ENABLE)) {
2947                 I915_WRITE(fp_reg, fp);
2948                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
2949                 I915_READ(dpll_reg);
2950                 udelay(150);
2951         }
2952
2953         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
2954          * This is an exception to the general rule that mode_set doesn't turn
2955          * things on.
2956          */
2957         if (is_lvds) {
2958                 u32 lvds;
2959
2960                 if (IS_IGDNG(dev))
2961                         lvds_reg = PCH_LVDS;
2962
2963                 lvds = I915_READ(lvds_reg);
2964                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
2965                 /* set the corresponsding LVDS_BORDER bit */
2966                 lvds |= dev_priv->lvds_border_bits;
2967                 /* Set the B0-B3 data pairs corresponding to whether we're going to
2968                  * set the DPLLs for dual-channel mode or not.
2969                  */
2970                 if (clock.p2 == 7)
2971                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
2972                 else
2973                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
2974
2975                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
2976                  * appropriately here, but we need to look more thoroughly into how
2977                  * panels behave in the two modes.
2978                  */
2979
2980                 I915_WRITE(lvds_reg, lvds);
2981                 I915_READ(lvds_reg);
2982         }
2983         if (is_dp)
2984                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
2985
2986         if (!is_edp) {
2987                 I915_WRITE(fp_reg, fp);
2988                 I915_WRITE(dpll_reg, dpll);
2989                 I915_READ(dpll_reg);
2990                 /* Wait for the clocks to stabilize. */
2991                 udelay(150);
2992
2993                 if (IS_I965G(dev) && !IS_IGDNG(dev)) {
2994                         if (is_sdvo) {
2995                                 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
2996                                 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
2997                                         ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
2998                         } else
2999                                 I915_WRITE(dpll_md_reg, 0);
3000                 } else {
3001                         /* write it again -- the BIOS does, after all */
3002                         I915_WRITE(dpll_reg, dpll);
3003                 }
3004                 I915_READ(dpll_reg);
3005                 /* Wait for the clocks to stabilize. */
3006                 udelay(150);
3007         }
3008
3009         if (is_lvds && has_reduced_clock && i915_powersave) {
3010                 I915_WRITE(fp_reg + 4, fp2);
3011                 intel_crtc->lowfreq_avail = true;
3012                 if (HAS_PIPE_CXSR(dev)) {
3013                         DRM_DEBUG("enabling CxSR downclocking\n");
3014                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3015                 }
3016         } else {
3017                 I915_WRITE(fp_reg + 4, fp);
3018                 intel_crtc->lowfreq_avail = false;
3019                 if (HAS_PIPE_CXSR(dev)) {
3020                         DRM_DEBUG("disabling CxSR downclocking\n");
3021                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3022                 }
3023         }
3024
3025         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
3026                    ((adjusted_mode->crtc_htotal - 1) << 16));
3027         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
3028                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
3029         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
3030                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
3031         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
3032                    ((adjusted_mode->crtc_vtotal - 1) << 16));
3033         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
3034                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
3035         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
3036                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
3037         /* pipesrc and dspsize control the size that is scaled from, which should
3038          * always be the user's requested size.
3039          */
3040         if (!IS_IGDNG(dev)) {
3041                 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
3042                                 (mode->hdisplay - 1));
3043                 I915_WRITE(dsppos_reg, 0);
3044         }
3045         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3046
3047         if (IS_IGDNG(dev)) {
3048                 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
3049                 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
3050                 I915_WRITE(link_m1_reg, m_n.link_m);
3051                 I915_WRITE(link_n1_reg, m_n.link_n);
3052
3053                 if (is_edp) {
3054                         igdng_set_pll_edp(crtc, adjusted_mode->clock);
3055                 } else {
3056                         /* enable FDI RX PLL too */
3057                         temp = I915_READ(fdi_rx_reg);
3058                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
3059                         udelay(200);
3060                 }
3061         }
3062
3063         I915_WRITE(pipeconf_reg, pipeconf);
3064         I915_READ(pipeconf_reg);
3065
3066         intel_wait_for_vblank(dev);
3067
3068         if (IS_IGDNG(dev)) {
3069                 /* enable address swizzle for tiling buffer */
3070                 temp = I915_READ(DISP_ARB_CTL);
3071                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
3072         }
3073
3074         I915_WRITE(dspcntr_reg, dspcntr);
3075
3076         /* Flush the plane changes */
3077         ret = intel_pipe_set_base(crtc, x, y, old_fb);
3078
3079         if ((IS_I965G(dev) || plane == 0))
3080                 intel_update_fbc(crtc, &crtc->mode);
3081
3082         intel_update_watermarks(dev);
3083
3084         drm_vblank_post_modeset(dev, pipe);
3085
3086         return ret;
3087 }
3088
3089 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3090 void intel_crtc_load_lut(struct drm_crtc *crtc)
3091 {
3092         struct drm_device *dev = crtc->dev;
3093         struct drm_i915_private *dev_priv = dev->dev_private;
3094         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3095         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
3096         int i;
3097
3098         /* The clocks have to be on to load the palette. */
3099         if (!crtc->enabled)
3100                 return;
3101
3102         /* use legacy palette for IGDNG */
3103         if (IS_IGDNG(dev))
3104                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
3105                                                    LGC_PALETTE_B;
3106
3107         for (i = 0; i < 256; i++) {
3108                 I915_WRITE(palreg + 4 * i,
3109                            (intel_crtc->lut_r[i] << 16) |
3110                            (intel_crtc->lut_g[i] << 8) |
3111                            intel_crtc->lut_b[i]);
3112         }
3113 }
3114
3115 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3116                                  struct drm_file *file_priv,
3117                                  uint32_t handle,
3118                                  uint32_t width, uint32_t height)
3119 {
3120         struct drm_device *dev = crtc->dev;
3121         struct drm_i915_private *dev_priv = dev->dev_private;
3122         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3123         struct drm_gem_object *bo;
3124         struct drm_i915_gem_object *obj_priv;
3125         int pipe = intel_crtc->pipe;
3126         uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
3127         uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
3128         uint32_t temp = I915_READ(control);
3129         size_t addr;
3130         int ret;
3131
3132         DRM_DEBUG("\n");
3133
3134         /* if we want to turn off the cursor ignore width and height */
3135         if (!handle) {
3136                 DRM_DEBUG("cursor off\n");
3137                 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3138                         temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
3139                         temp |= CURSOR_MODE_DISABLE;
3140                 } else {
3141                         temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
3142                 }
3143                 addr = 0;
3144                 bo = NULL;
3145                 mutex_lock(&dev->struct_mutex);
3146                 goto finish;
3147         }
3148
3149         /* Currently we only support 64x64 cursors */
3150         if (width != 64 || height != 64) {
3151                 DRM_ERROR("we currently only support 64x64 cursors\n");
3152                 return -EINVAL;
3153         }
3154
3155         bo = drm_gem_object_lookup(dev, file_priv, handle);
3156         if (!bo)
3157                 return -ENOENT;
3158
3159         obj_priv = bo->driver_private;
3160
3161         if (bo->size < width * height * 4) {
3162                 DRM_ERROR("buffer is to small\n");
3163                 ret = -ENOMEM;
3164                 goto fail;
3165         }
3166
3167         /* we only need to pin inside GTT if cursor is non-phy */
3168         mutex_lock(&dev->struct_mutex);
3169         if (!dev_priv->cursor_needs_physical) {
3170                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
3171                 if (ret) {
3172                         DRM_ERROR("failed to pin cursor bo\n");
3173                         goto fail_locked;
3174                 }
3175                 addr = obj_priv->gtt_offset;
3176         } else {
3177                 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
3178                 if (ret) {
3179                         DRM_ERROR("failed to attach phys object\n");
3180                         goto fail_locked;
3181                 }
3182                 addr = obj_priv->phys_obj->handle->busaddr;
3183         }
3184
3185         if (!IS_I9XX(dev))
3186                 I915_WRITE(CURSIZE, (height << 12) | width);
3187
3188         /* Hooray for CUR*CNTR differences */
3189         if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3190                 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
3191                 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
3192                 temp |= (pipe << 28); /* Connect to correct pipe */
3193         } else {
3194                 temp &= ~(CURSOR_FORMAT_MASK);
3195                 temp |= CURSOR_ENABLE;
3196                 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
3197         }
3198
3199  finish:
3200         I915_WRITE(control, temp);
3201         I915_WRITE(base, addr);
3202
3203         if (intel_crtc->cursor_bo) {
3204                 if (dev_priv->cursor_needs_physical) {
3205                         if (intel_crtc->cursor_bo != bo)
3206                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
3207                 } else
3208                         i915_gem_object_unpin(intel_crtc->cursor_bo);
3209                 drm_gem_object_unreference(intel_crtc->cursor_bo);
3210         }
3211
3212         mutex_unlock(&dev->struct_mutex);
3213
3214         intel_crtc->cursor_addr = addr;
3215         intel_crtc->cursor_bo = bo;
3216
3217         return 0;
3218 fail:
3219         mutex_lock(&dev->struct_mutex);
3220 fail_locked:
3221         drm_gem_object_unreference(bo);
3222         mutex_unlock(&dev->struct_mutex);
3223         return ret;
3224 }
3225
3226 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
3227 {
3228         struct drm_device *dev = crtc->dev;
3229         struct drm_i915_private *dev_priv = dev->dev_private;
3230         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3231         struct intel_framebuffer *intel_fb;
3232         int pipe = intel_crtc->pipe;
3233         uint32_t temp = 0;
3234         uint32_t adder;
3235
3236         if (crtc->fb) {
3237                 intel_fb = to_intel_framebuffer(crtc->fb);
3238                 intel_mark_busy(dev, intel_fb->obj);
3239         }
3240
3241         if (x < 0) {
3242                 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
3243                 x = -x;
3244         }
3245         if (y < 0) {
3246                 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
3247                 y = -y;
3248         }
3249
3250         temp |= x << CURSOR_X_SHIFT;
3251         temp |= y << CURSOR_Y_SHIFT;
3252
3253         adder = intel_crtc->cursor_addr;
3254         I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
3255         I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
3256
3257         return 0;
3258 }
3259
3260 /** Sets the color ramps on behalf of RandR */
3261 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
3262                                  u16 blue, int regno)
3263 {
3264         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3265
3266         intel_crtc->lut_r[regno] = red >> 8;
3267         intel_crtc->lut_g[regno] = green >> 8;
3268         intel_crtc->lut_b[regno] = blue >> 8;
3269 }
3270
3271 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
3272                              u16 *blue, int regno)
3273 {
3274         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3275
3276         *red = intel_crtc->lut_r[regno] << 8;
3277         *green = intel_crtc->lut_g[regno] << 8;
3278         *blue = intel_crtc->lut_b[regno] << 8;
3279 }
3280
3281 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
3282                                  u16 *blue, uint32_t size)
3283 {
3284         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3285         int i;
3286
3287         if (size != 256)
3288                 return;
3289
3290         for (i = 0; i < 256; i++) {
3291                 intel_crtc->lut_r[i] = red[i] >> 8;
3292                 intel_crtc->lut_g[i] = green[i] >> 8;
3293                 intel_crtc->lut_b[i] = blue[i] >> 8;
3294         }
3295
3296         intel_crtc_load_lut(crtc);
3297 }
3298
3299 /**
3300  * Get a pipe with a simple mode set on it for doing load-based monitor
3301  * detection.
3302  *
3303  * It will be up to the load-detect code to adjust the pipe as appropriate for
3304  * its requirements.  The pipe will be connected to no other outputs.
3305  *
3306  * Currently this code will only succeed if there is a pipe with no outputs
3307  * configured for it.  In the future, it could choose to temporarily disable
3308  * some outputs to free up a pipe for its use.
3309  *
3310  * \return crtc, or NULL if no pipes are available.
3311  */
3312
3313 /* VESA 640x480x72Hz mode to set on the pipe */
3314 static struct drm_display_mode load_detect_mode = {
3315         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
3316                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
3317 };
3318
3319 struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
3320                                             struct drm_display_mode *mode,
3321                                             int *dpms_mode)
3322 {
3323         struct intel_crtc *intel_crtc;
3324         struct drm_crtc *possible_crtc;
3325         struct drm_crtc *supported_crtc =NULL;
3326         struct drm_encoder *encoder = &intel_output->enc;
3327         struct drm_crtc *crtc = NULL;
3328         struct drm_device *dev = encoder->dev;
3329         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3330         struct drm_crtc_helper_funcs *crtc_funcs;
3331         int i = -1;
3332
3333         /*
3334          * Algorithm gets a little messy:
3335          *   - if the connector already has an assigned crtc, use it (but make
3336          *     sure it's on first)
3337          *   - try to find the first unused crtc that can drive this connector,
3338          *     and use that if we find one
3339          *   - if there are no unused crtcs available, try to use the first
3340          *     one we found that supports the connector
3341          */
3342
3343         /* See if we already have a CRTC for this connector */
3344         if (encoder->crtc) {
3345                 crtc = encoder->crtc;
3346                 /* Make sure the crtc and connector are running */
3347                 intel_crtc = to_intel_crtc(crtc);
3348                 *dpms_mode = intel_crtc->dpms_mode;
3349                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3350                         crtc_funcs = crtc->helper_private;
3351                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3352                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3353                 }
3354                 return crtc;
3355         }
3356
3357         /* Find an unused one (if possible) */
3358         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
3359                 i++;
3360                 if (!(encoder->possible_crtcs & (1 << i)))
3361                         continue;
3362                 if (!possible_crtc->enabled) {
3363                         crtc = possible_crtc;
3364                         break;
3365                 }
3366                 if (!supported_crtc)
3367                         supported_crtc = possible_crtc;
3368         }
3369
3370         /*
3371          * If we didn't find an unused CRTC, don't use any.
3372          */
3373         if (!crtc) {
3374                 return NULL;
3375         }
3376
3377         encoder->crtc = crtc;
3378         intel_output->base.encoder = encoder;
3379         intel_output->load_detect_temp = true;
3380
3381         intel_crtc = to_intel_crtc(crtc);
3382         *dpms_mode = intel_crtc->dpms_mode;
3383
3384         if (!crtc->enabled) {
3385                 if (!mode)
3386                         mode = &load_detect_mode;
3387                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
3388         } else {
3389                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3390                         crtc_funcs = crtc->helper_private;
3391                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3392                 }
3393
3394                 /* Add this connector to the crtc */
3395                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
3396                 encoder_funcs->commit(encoder);
3397         }
3398         /* let the connector get through one full cycle before testing */
3399         intel_wait_for_vblank(dev);
3400
3401         return crtc;
3402 }
3403
3404 void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
3405 {
3406         struct drm_encoder *encoder = &intel_output->enc;
3407         struct drm_device *dev = encoder->dev;
3408         struct drm_crtc *crtc = encoder->crtc;
3409         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3410         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3411
3412         if (intel_output->load_detect_temp) {
3413                 encoder->crtc = NULL;
3414                 intel_output->base.encoder = NULL;
3415                 intel_output->load_detect_temp = false;
3416                 crtc->enabled = drm_helper_crtc_in_use(crtc);
3417                 drm_helper_disable_unused_functions(dev);
3418         }
3419
3420         /* Switch crtc and output back off if necessary */
3421         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
3422                 if (encoder->crtc == crtc)
3423                         encoder_funcs->dpms(encoder, dpms_mode);
3424                 crtc_funcs->dpms(crtc, dpms_mode);
3425         }
3426 }
3427
3428 /* Returns the clock of the currently programmed mode of the given pipe. */
3429 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
3430 {
3431         struct drm_i915_private *dev_priv = dev->dev_private;
3432         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3433         int pipe = intel_crtc->pipe;
3434         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
3435         u32 fp;
3436         intel_clock_t clock;
3437
3438         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
3439                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
3440         else
3441                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
3442
3443         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
3444         if (IS_IGD(dev)) {
3445                 clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
3446                 clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT;
3447         } else {
3448                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
3449                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
3450         }
3451
3452         if (IS_I9XX(dev)) {
3453                 if (IS_IGD(dev))
3454                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>
3455                                 DPLL_FPA01_P1_POST_DIV_SHIFT_IGD);
3456                 else
3457                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
3458                                DPLL_FPA01_P1_POST_DIV_SHIFT);
3459
3460                 switch (dpll & DPLL_MODE_MASK) {
3461                 case DPLLB_MODE_DAC_SERIAL:
3462                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
3463                                 5 : 10;
3464                         break;
3465                 case DPLLB_MODE_LVDS:
3466                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
3467                                 7 : 14;
3468                         break;
3469                 default:
3470                         DRM_DEBUG("Unknown DPLL mode %08x in programmed "
3471                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
3472                         return 0;
3473                 }
3474
3475                 /* XXX: Handle the 100Mhz refclk */
3476                 intel_clock(dev, 96000, &clock);
3477         } else {
3478                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
3479
3480                 if (is_lvds) {
3481                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
3482                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
3483                         clock.p2 = 14;
3484
3485                         if ((dpll & PLL_REF_INPUT_MASK) ==
3486                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
3487                                 /* XXX: might not be 66MHz */
3488                                 intel_clock(dev, 66000, &clock);
3489                         } else
3490                                 intel_clock(dev, 48000, &clock);
3491                 } else {
3492                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
3493                                 clock.p1 = 2;
3494                         else {
3495                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
3496                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
3497                         }
3498                         if (dpll & PLL_P2_DIVIDE_BY_4)
3499                                 clock.p2 = 4;
3500                         else
3501                                 clock.p2 = 2;
3502
3503                         intel_clock(dev, 48000, &clock);
3504                 }
3505         }
3506
3507         /* XXX: It would be nice to validate the clocks, but we can't reuse
3508          * i830PllIsValid() because it relies on the xf86_config connector
3509          * configuration being accurate, which it isn't necessarily.
3510          */
3511
3512         return clock.dot;
3513 }
3514
3515 /** Returns the currently programmed mode of the given pipe. */
3516 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
3517                                              struct drm_crtc *crtc)
3518 {
3519         struct drm_i915_private *dev_priv = dev->dev_private;
3520         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3521         int pipe = intel_crtc->pipe;
3522         struct drm_display_mode *mode;
3523         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
3524         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
3525         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
3526         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
3527
3528         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
3529         if (!mode)
3530                 return NULL;
3531
3532         mode->clock = intel_crtc_clock_get(dev, crtc);
3533         mode->hdisplay = (htot & 0xffff) + 1;
3534         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
3535         mode->hsync_start = (hsync & 0xffff) + 1;
3536         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
3537         mode->vdisplay = (vtot & 0xffff) + 1;
3538         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
3539         mode->vsync_start = (vsync & 0xffff) + 1;
3540         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
3541
3542         drm_mode_set_name(mode);
3543         drm_mode_set_crtcinfo(mode, 0);
3544
3545         return mode;
3546 }
3547
3548 #define GPU_IDLE_TIMEOUT 500 /* ms */
3549
3550 /* When this timer fires, we've been idle for awhile */
3551 static void intel_gpu_idle_timer(unsigned long arg)
3552 {
3553         struct drm_device *dev = (struct drm_device *)arg;
3554         drm_i915_private_t *dev_priv = dev->dev_private;
3555
3556         DRM_DEBUG("idle timer fired, downclocking\n");
3557
3558         dev_priv->busy = false;
3559
3560         queue_work(dev_priv->wq, &dev_priv->idle_work);
3561 }
3562
3563 void intel_increase_renderclock(struct drm_device *dev, bool schedule)
3564 {
3565         drm_i915_private_t *dev_priv = dev->dev_private;
3566
3567         if (IS_IGDNG(dev))
3568                 return;
3569
3570         if (!dev_priv->render_reclock_avail) {
3571                 DRM_DEBUG("not reclocking render clock\n");
3572                 return;
3573         }
3574
3575         /* Restore render clock frequency to original value */
3576         if (IS_G4X(dev) || IS_I9XX(dev))
3577                 pci_write_config_word(dev->pdev, GCFGC, dev_priv->orig_clock);
3578         else if (IS_I85X(dev))
3579                 pci_write_config_word(dev->pdev, HPLLCC, dev_priv->orig_clock);
3580         DRM_DEBUG("increasing render clock frequency\n");
3581
3582         /* Schedule downclock */
3583         if (schedule)
3584                 mod_timer(&dev_priv->idle_timer, jiffies +
3585                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
3586 }
3587
3588 void intel_decrease_renderclock(struct drm_device *dev)
3589 {
3590         drm_i915_private_t *dev_priv = dev->dev_private;
3591
3592         if (IS_IGDNG(dev))
3593                 return;
3594
3595         if (!dev_priv->render_reclock_avail) {
3596                 DRM_DEBUG("not reclocking render clock\n");
3597                 return;
3598         }
3599
3600         if (IS_G4X(dev)) {
3601                 u16 gcfgc;
3602
3603                 /* Adjust render clock... */
3604                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3605
3606                 /* Down to minimum... */
3607                 gcfgc &= ~GM45_GC_RENDER_CLOCK_MASK;
3608                 gcfgc |= GM45_GC_RENDER_CLOCK_266_MHZ;
3609
3610                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3611         } else if (IS_I965G(dev)) {
3612                 u16 gcfgc;
3613
3614                 /* Adjust render clock... */
3615                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3616
3617                 /* Down to minimum... */
3618                 gcfgc &= ~I965_GC_RENDER_CLOCK_MASK;
3619                 gcfgc |= I965_GC_RENDER_CLOCK_267_MHZ;
3620
3621                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3622         } else if (IS_I945G(dev) || IS_I945GM(dev)) {
3623                 u16 gcfgc;
3624
3625                 /* Adjust render clock... */
3626                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3627
3628                 /* Down to minimum... */
3629                 gcfgc &= ~I945_GC_RENDER_CLOCK_MASK;
3630                 gcfgc |= I945_GC_RENDER_CLOCK_166_MHZ;
3631
3632                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3633         } else if (IS_I915G(dev)) {
3634                 u16 gcfgc;
3635
3636                 /* Adjust render clock... */
3637                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3638
3639                 /* Down to minimum... */
3640                 gcfgc &= ~I915_GC_RENDER_CLOCK_MASK;
3641                 gcfgc |= I915_GC_RENDER_CLOCK_166_MHZ;
3642
3643                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3644         } else if (IS_I85X(dev)) {
3645                 u16 hpllcc;
3646
3647                 /* Adjust render clock... */
3648                 pci_read_config_word(dev->pdev, HPLLCC, &hpllcc);
3649
3650                 /* Up to maximum... */
3651                 hpllcc &= ~GC_CLOCK_CONTROL_MASK;
3652                 hpllcc |= GC_CLOCK_133_200;
3653
3654                 pci_write_config_word(dev->pdev, HPLLCC, hpllcc);
3655         }
3656         DRM_DEBUG("decreasing render clock frequency\n");
3657 }
3658
3659 /* Note that no increase function is needed for this - increase_renderclock()
3660  *  will also rewrite these bits
3661  */
3662 void intel_decrease_displayclock(struct drm_device *dev)
3663 {
3664         if (IS_IGDNG(dev))
3665                 return;
3666
3667         if (IS_I945G(dev) || IS_I945GM(dev) || IS_I915G(dev) ||
3668             IS_I915GM(dev)) {
3669                 u16 gcfgc;
3670
3671                 /* Adjust render clock... */
3672                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3673
3674                 /* Down to minimum... */
3675                 gcfgc &= ~0xf0;
3676                 gcfgc |= 0x80;
3677
3678                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3679         }
3680 }
3681
3682 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
3683
3684 static void intel_crtc_idle_timer(unsigned long arg)
3685 {
3686         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
3687         struct drm_crtc *crtc = &intel_crtc->base;
3688         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
3689
3690         DRM_DEBUG("idle timer fired, downclocking\n");
3691
3692         intel_crtc->busy = false;
3693
3694         queue_work(dev_priv->wq, &dev_priv->idle_work);
3695 }
3696
3697 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
3698 {
3699         struct drm_device *dev = crtc->dev;
3700         drm_i915_private_t *dev_priv = dev->dev_private;
3701         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3702         int pipe = intel_crtc->pipe;
3703         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3704         int dpll = I915_READ(dpll_reg);
3705
3706         if (IS_IGDNG(dev))
3707                 return;
3708
3709         if (!dev_priv->lvds_downclock_avail)
3710                 return;
3711
3712         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
3713                 DRM_DEBUG("upclocking LVDS\n");
3714
3715                 /* Unlock panel regs */
3716                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3717
3718                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
3719                 I915_WRITE(dpll_reg, dpll);
3720                 dpll = I915_READ(dpll_reg);
3721                 intel_wait_for_vblank(dev);
3722                 dpll = I915_READ(dpll_reg);
3723                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
3724                         DRM_DEBUG("failed to upclock LVDS!\n");
3725
3726                 /* ...and lock them again */
3727                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3728         }
3729
3730         /* Schedule downclock */
3731         if (schedule)
3732                 mod_timer(&intel_crtc->idle_timer, jiffies +
3733                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3734 }
3735
3736 static void intel_decrease_pllclock(struct drm_crtc *crtc)
3737 {
3738         struct drm_device *dev = crtc->dev;
3739         drm_i915_private_t *dev_priv = dev->dev_private;
3740         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3741         int pipe = intel_crtc->pipe;
3742         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3743         int dpll = I915_READ(dpll_reg);
3744
3745         if (IS_IGDNG(dev))
3746                 return;
3747
3748         if (!dev_priv->lvds_downclock_avail)
3749                 return;
3750
3751         /*
3752          * Since this is called by a timer, we should never get here in
3753          * the manual case.
3754          */
3755         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
3756                 DRM_DEBUG("downclocking LVDS\n");
3757
3758                 /* Unlock panel regs */
3759                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3760
3761                 dpll |= DISPLAY_RATE_SELECT_FPA1;
3762                 I915_WRITE(dpll_reg, dpll);
3763                 dpll = I915_READ(dpll_reg);
3764                 intel_wait_for_vblank(dev);
3765                 dpll = I915_READ(dpll_reg);
3766                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
3767                         DRM_DEBUG("failed to downclock LVDS!\n");
3768
3769                 /* ...and lock them again */
3770                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3771         }
3772
3773 }
3774
3775 /**
3776  * intel_idle_update - adjust clocks for idleness
3777  * @work: work struct
3778  *
3779  * Either the GPU or display (or both) went idle.  Check the busy status
3780  * here and adjust the CRTC and GPU clocks as necessary.
3781  */
3782 static void intel_idle_update(struct work_struct *work)
3783 {
3784         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
3785                                                     idle_work);
3786         struct drm_device *dev = dev_priv->dev;
3787         struct drm_crtc *crtc;
3788         struct intel_crtc *intel_crtc;
3789
3790         if (!i915_powersave)
3791                 return;
3792
3793         mutex_lock(&dev->struct_mutex);
3794
3795         /* GPU isn't processing, downclock it. */
3796         if (!dev_priv->busy) {
3797                 intel_decrease_renderclock(dev);
3798                 intel_decrease_displayclock(dev);
3799         }
3800
3801         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3802                 /* Skip inactive CRTCs */
3803                 if (!crtc->fb)
3804                         continue;
3805
3806                 intel_crtc = to_intel_crtc(crtc);
3807                 if (!intel_crtc->busy)
3808                         intel_decrease_pllclock(crtc);
3809         }
3810
3811         mutex_unlock(&dev->struct_mutex);
3812 }
3813
3814 /**
3815  * intel_mark_busy - mark the GPU and possibly the display busy
3816  * @dev: drm device
3817  * @obj: object we're operating on
3818  *
3819  * Callers can use this function to indicate that the GPU is busy processing
3820  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
3821  * buffer), we'll also mark the display as busy, so we know to increase its
3822  * clock frequency.
3823  */
3824 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
3825 {
3826         drm_i915_private_t *dev_priv = dev->dev_private;
3827         struct drm_crtc *crtc = NULL;
3828         struct intel_framebuffer *intel_fb;
3829         struct intel_crtc *intel_crtc;
3830
3831         if (!drm_core_check_feature(dev, DRIVER_MODESET))
3832                 return;
3833
3834         dev_priv->busy = true;
3835         intel_increase_renderclock(dev, true);
3836
3837         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3838                 if (!crtc->fb)
3839                         continue;
3840
3841                 intel_crtc = to_intel_crtc(crtc);
3842                 intel_fb = to_intel_framebuffer(crtc->fb);
3843                 if (intel_fb->obj == obj) {
3844                         if (!intel_crtc->busy) {
3845                                 /* Non-busy -> busy, upclock */
3846                                 intel_increase_pllclock(crtc, true);
3847                                 intel_crtc->busy = true;
3848                         } else {
3849                                 /* Busy -> busy, put off timer */
3850                                 mod_timer(&intel_crtc->idle_timer, jiffies +
3851                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3852                         }
3853                 }
3854         }
3855 }
3856
3857 static void intel_crtc_destroy(struct drm_crtc *crtc)
3858 {
3859         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3860
3861         drm_crtc_cleanup(crtc);
3862         kfree(intel_crtc);
3863 }
3864
3865 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
3866         .dpms = intel_crtc_dpms,
3867         .mode_fixup = intel_crtc_mode_fixup,
3868         .mode_set = intel_crtc_mode_set,
3869         .mode_set_base = intel_pipe_set_base,
3870         .prepare = intel_crtc_prepare,
3871         .commit = intel_crtc_commit,
3872         .load_lut = intel_crtc_load_lut,
3873 };
3874
3875 static const struct drm_crtc_funcs intel_crtc_funcs = {
3876         .cursor_set = intel_crtc_cursor_set,
3877         .cursor_move = intel_crtc_cursor_move,
3878         .gamma_set = intel_crtc_gamma_set,
3879         .set_config = drm_crtc_helper_set_config,
3880         .destroy = intel_crtc_destroy,
3881 };
3882
3883
3884 static void intel_crtc_init(struct drm_device *dev, int pipe)
3885 {
3886         struct intel_crtc *intel_crtc;
3887         int i;
3888
3889         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
3890         if (intel_crtc == NULL)
3891                 return;
3892
3893         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
3894
3895         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
3896         intel_crtc->pipe = pipe;
3897         intel_crtc->plane = pipe;
3898         for (i = 0; i < 256; i++) {
3899                 intel_crtc->lut_r[i] = i;
3900                 intel_crtc->lut_g[i] = i;
3901                 intel_crtc->lut_b[i] = i;
3902         }
3903
3904         /* Swap pipes & planes for FBC on pre-965 */
3905         intel_crtc->pipe = pipe;
3906         intel_crtc->plane = pipe;
3907         if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
3908                 DRM_DEBUG("swapping pipes & planes for FBC\n");
3909                 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
3910         }
3911
3912         intel_crtc->cursor_addr = 0;
3913         intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
3914         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
3915
3916         intel_crtc->busy = false;
3917
3918         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
3919                     (unsigned long)intel_crtc);
3920 }
3921
3922 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
3923                                 struct drm_file *file_priv)
3924 {
3925         drm_i915_private_t *dev_priv = dev->dev_private;
3926         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
3927         struct drm_mode_object *drmmode_obj;
3928         struct intel_crtc *crtc;
3929
3930         if (!dev_priv) {
3931                 DRM_ERROR("called with no initialization\n");
3932                 return -EINVAL;
3933         }
3934
3935         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
3936                         DRM_MODE_OBJECT_CRTC);
3937
3938         if (!drmmode_obj) {
3939                 DRM_ERROR("no such CRTC id\n");
3940                 return -EINVAL;
3941         }
3942
3943         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
3944         pipe_from_crtc_id->pipe = crtc->pipe;
3945
3946         return 0;
3947 }
3948
3949 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
3950 {
3951         struct drm_crtc *crtc = NULL;
3952
3953         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3954                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3955                 if (intel_crtc->pipe == pipe)
3956                         break;
3957         }
3958         return crtc;
3959 }
3960
3961 static int intel_connector_clones(struct drm_device *dev, int type_mask)
3962 {
3963         int index_mask = 0;
3964         struct drm_connector *connector;
3965         int entry = 0;
3966
3967         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3968                 struct intel_output *intel_output = to_intel_output(connector);
3969                 if (type_mask & intel_output->clone_mask)
3970                         index_mask |= (1 << entry);
3971                 entry++;
3972         }
3973         return index_mask;
3974 }
3975
3976
3977 static void intel_setup_outputs(struct drm_device *dev)
3978 {
3979         struct drm_i915_private *dev_priv = dev->dev_private;
3980         struct drm_connector *connector;
3981
3982         intel_crt_init(dev);
3983
3984         /* Set up integrated LVDS */
3985         if (IS_MOBILE(dev) && !IS_I830(dev))
3986                 intel_lvds_init(dev);
3987
3988         if (IS_IGDNG(dev)) {
3989                 int found;
3990
3991                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
3992                         intel_dp_init(dev, DP_A);
3993
3994                 if (I915_READ(HDMIB) & PORT_DETECTED) {
3995                         /* check SDVOB */
3996                         /* found = intel_sdvo_init(dev, HDMIB); */
3997                         found = 0;
3998                         if (!found)
3999                                 intel_hdmi_init(dev, HDMIB);
4000                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
4001                                 intel_dp_init(dev, PCH_DP_B);
4002                 }
4003
4004                 if (I915_READ(HDMIC) & PORT_DETECTED)
4005                         intel_hdmi_init(dev, HDMIC);
4006
4007                 if (I915_READ(HDMID) & PORT_DETECTED)
4008                         intel_hdmi_init(dev, HDMID);
4009
4010                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
4011                         intel_dp_init(dev, PCH_DP_C);
4012
4013                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
4014                         intel_dp_init(dev, PCH_DP_D);
4015
4016         } else if (IS_I9XX(dev)) {
4017                 bool found = false;
4018
4019                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4020                         found = intel_sdvo_init(dev, SDVOB);
4021                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
4022                                 intel_hdmi_init(dev, SDVOB);
4023
4024                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
4025                                 intel_dp_init(dev, DP_B);
4026                 }
4027
4028                 /* Before G4X SDVOC doesn't have its own detect register */
4029
4030                 if (I915_READ(SDVOB) & SDVO_DETECTED)
4031                         found = intel_sdvo_init(dev, SDVOC);
4032
4033                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
4034
4035                         if (SUPPORTS_INTEGRATED_HDMI(dev))
4036                                 intel_hdmi_init(dev, SDVOC);
4037                         if (SUPPORTS_INTEGRATED_DP(dev))
4038                                 intel_dp_init(dev, DP_C);
4039                 }
4040
4041                 if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED))
4042                         intel_dp_init(dev, DP_D);
4043         } else
4044                 intel_dvo_init(dev);
4045
4046         if (IS_I9XX(dev) && IS_MOBILE(dev) && !IS_IGDNG(dev))
4047                 intel_tv_init(dev);
4048
4049         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4050                 struct intel_output *intel_output = to_intel_output(connector);
4051                 struct drm_encoder *encoder = &intel_output->enc;
4052
4053                 encoder->possible_crtcs = intel_output->crtc_mask;
4054                 encoder->possible_clones = intel_connector_clones(dev,
4055                                                 intel_output->clone_mask);
4056         }
4057 }
4058
4059 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
4060 {
4061         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4062         struct drm_device *dev = fb->dev;
4063
4064         if (fb->fbdev)
4065                 intelfb_remove(dev, fb);
4066
4067         drm_framebuffer_cleanup(fb);
4068         mutex_lock(&dev->struct_mutex);
4069         drm_gem_object_unreference(intel_fb->obj);
4070         mutex_unlock(&dev->struct_mutex);
4071
4072         kfree(intel_fb);
4073 }
4074
4075 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
4076                                                 struct drm_file *file_priv,
4077                                                 unsigned int *handle)
4078 {
4079         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4080         struct drm_gem_object *object = intel_fb->obj;
4081
4082         return drm_gem_handle_create(file_priv, object, handle);
4083 }
4084
4085 static const struct drm_framebuffer_funcs intel_fb_funcs = {
4086         .destroy = intel_user_framebuffer_destroy,
4087         .create_handle = intel_user_framebuffer_create_handle,
4088 };
4089
4090 int intel_framebuffer_create(struct drm_device *dev,
4091                              struct drm_mode_fb_cmd *mode_cmd,
4092                              struct drm_framebuffer **fb,
4093                              struct drm_gem_object *obj)
4094 {
4095         struct intel_framebuffer *intel_fb;
4096         int ret;
4097
4098         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
4099         if (!intel_fb)
4100                 return -ENOMEM;
4101
4102         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
4103         if (ret) {
4104                 DRM_ERROR("framebuffer init failed %d\n", ret);
4105                 return ret;
4106         }
4107
4108         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
4109
4110         intel_fb->obj = obj;
4111
4112         *fb = &intel_fb->base;
4113
4114         return 0;
4115 }
4116
4117
4118 static struct drm_framebuffer *
4119 intel_user_framebuffer_create(struct drm_device *dev,
4120                               struct drm_file *filp,
4121                               struct drm_mode_fb_cmd *mode_cmd)
4122 {
4123         struct drm_gem_object *obj;
4124         struct drm_framebuffer *fb;
4125         int ret;
4126
4127         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
4128         if (!obj)
4129                 return NULL;
4130
4131         ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
4132         if (ret) {
4133                 mutex_lock(&dev->struct_mutex);
4134                 drm_gem_object_unreference(obj);
4135                 mutex_unlock(&dev->struct_mutex);
4136                 return NULL;
4137         }
4138
4139         return fb;
4140 }
4141
4142 static const struct drm_mode_config_funcs intel_mode_funcs = {
4143         .fb_create = intel_user_framebuffer_create,
4144         .fb_changed = intelfb_probe,
4145 };
4146
4147 void intel_init_clock_gating(struct drm_device *dev)
4148 {
4149         struct drm_i915_private *dev_priv = dev->dev_private;
4150
4151         /*
4152          * Disable clock gating reported to work incorrectly according to the
4153          * specs, but enable as much else as we can.
4154          */
4155         if (IS_IGDNG(dev)) {
4156                 return;
4157         } else if (IS_G4X(dev)) {
4158                 uint32_t dspclk_gate;
4159                 I915_WRITE(RENCLK_GATE_D1, 0);
4160                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4161                        GS_UNIT_CLOCK_GATE_DISABLE |
4162                        CL_UNIT_CLOCK_GATE_DISABLE);
4163                 I915_WRITE(RAMCLK_GATE_D, 0);
4164                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4165                         OVRUNIT_CLOCK_GATE_DISABLE |
4166                         OVCUNIT_CLOCK_GATE_DISABLE;
4167                 if (IS_GM45(dev))
4168                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4169                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4170         } else if (IS_I965GM(dev)) {
4171                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4172                 I915_WRITE(RENCLK_GATE_D2, 0);
4173                 I915_WRITE(DSPCLK_GATE_D, 0);
4174                 I915_WRITE(RAMCLK_GATE_D, 0);
4175                 I915_WRITE16(DEUC, 0);
4176         } else if (IS_I965G(dev)) {
4177                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4178                        I965_RCC_CLOCK_GATE_DISABLE |
4179                        I965_RCPB_CLOCK_GATE_DISABLE |
4180                        I965_ISC_CLOCK_GATE_DISABLE |
4181                        I965_FBC_CLOCK_GATE_DISABLE);
4182                 I915_WRITE(RENCLK_GATE_D2, 0);
4183         } else if (IS_I9XX(dev)) {
4184                 u32 dstate = I915_READ(D_STATE);
4185
4186                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4187                         DSTATE_DOT_CLOCK_GATING;
4188                 I915_WRITE(D_STATE, dstate);
4189         } else if (IS_I855(dev) || IS_I865G(dev)) {
4190                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4191         } else if (IS_I830(dev)) {
4192                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4193         }
4194 }
4195
4196 /* Set up chip specific display functions */
4197 static void intel_init_display(struct drm_device *dev)
4198 {
4199         struct drm_i915_private *dev_priv = dev->dev_private;
4200
4201         /* We always want a DPMS function */
4202         if (IS_IGDNG(dev))
4203                 dev_priv->display.dpms = igdng_crtc_dpms;
4204         else
4205                 dev_priv->display.dpms = i9xx_crtc_dpms;
4206
4207         /* Only mobile has FBC, leave pointers NULL for other chips */
4208         if (IS_MOBILE(dev)) {
4209                 if (IS_GM45(dev)) {
4210                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4211                         dev_priv->display.enable_fbc = g4x_enable_fbc;
4212                         dev_priv->display.disable_fbc = g4x_disable_fbc;
4213                 } else if (IS_I965GM(dev) || IS_I945GM(dev) || IS_I915GM(dev)) {
4214                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4215                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
4216                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
4217                 }
4218                 /* 855GM needs testing */
4219         }
4220
4221         /* Returns the core display clock speed */
4222         if (IS_I945G(dev))
4223                 dev_priv->display.get_display_clock_speed =
4224                         i945_get_display_clock_speed;
4225         else if (IS_I915G(dev))
4226                 dev_priv->display.get_display_clock_speed =
4227                         i915_get_display_clock_speed;
4228         else if (IS_I945GM(dev) || IS_845G(dev) || IS_IGDGM(dev))
4229                 dev_priv->display.get_display_clock_speed =
4230                         i9xx_misc_get_display_clock_speed;
4231         else if (IS_I915GM(dev))
4232                 dev_priv->display.get_display_clock_speed =
4233                         i915gm_get_display_clock_speed;
4234         else if (IS_I865G(dev))
4235                 dev_priv->display.get_display_clock_speed =
4236                         i865_get_display_clock_speed;
4237         else if (IS_I855(dev))
4238                 dev_priv->display.get_display_clock_speed =
4239                         i855_get_display_clock_speed;
4240         else /* 852, 830 */
4241                 dev_priv->display.get_display_clock_speed =
4242                         i830_get_display_clock_speed;
4243
4244         /* For FIFO watermark updates */
4245         if (IS_IGDNG(dev))
4246                 dev_priv->display.update_wm = NULL;
4247         else if (IS_G4X(dev))
4248                 dev_priv->display.update_wm = g4x_update_wm;
4249         else if (IS_I965G(dev))
4250                 dev_priv->display.update_wm = i965_update_wm;
4251         else if (IS_I9XX(dev) || IS_MOBILE(dev)) {
4252                 dev_priv->display.update_wm = i9xx_update_wm;
4253                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4254         } else {
4255                 if (IS_I85X(dev))
4256                         dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4257                 else if (IS_845G(dev))
4258                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
4259                 else
4260                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
4261                 dev_priv->display.update_wm = i830_update_wm;
4262         }
4263 }
4264
4265 void intel_modeset_init(struct drm_device *dev)
4266 {
4267         struct drm_i915_private *dev_priv = dev->dev_private;
4268         int num_pipe;
4269         int i;
4270
4271         drm_mode_config_init(dev);
4272
4273         dev->mode_config.min_width = 0;
4274         dev->mode_config.min_height = 0;
4275
4276         dev->mode_config.funcs = (void *)&intel_mode_funcs;
4277
4278         intel_init_display(dev);
4279
4280         if (IS_I965G(dev)) {
4281                 dev->mode_config.max_width = 8192;
4282                 dev->mode_config.max_height = 8192;
4283         } else if (IS_I9XX(dev)) {
4284                 dev->mode_config.max_width = 4096;
4285                 dev->mode_config.max_height = 4096;
4286         } else {
4287                 dev->mode_config.max_width = 2048;
4288                 dev->mode_config.max_height = 2048;
4289         }
4290
4291         /* set memory base */
4292         if (IS_I9XX(dev))
4293                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
4294         else
4295                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
4296
4297         if (IS_MOBILE(dev) || IS_I9XX(dev))
4298                 num_pipe = 2;
4299         else
4300                 num_pipe = 1;
4301         DRM_DEBUG("%d display pipe%s available.\n",
4302                   num_pipe, num_pipe > 1 ? "s" : "");
4303
4304         if (IS_I85X(dev))
4305                 pci_read_config_word(dev->pdev, HPLLCC, &dev_priv->orig_clock);
4306         else if (IS_I9XX(dev) || IS_G4X(dev))
4307                 pci_read_config_word(dev->pdev, GCFGC, &dev_priv->orig_clock);
4308
4309         for (i = 0; i < num_pipe; i++) {
4310                 intel_crtc_init(dev, i);
4311         }
4312
4313         intel_setup_outputs(dev);
4314
4315         intel_init_clock_gating(dev);
4316
4317         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
4318         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
4319                     (unsigned long)dev);
4320 }
4321
4322 void intel_modeset_cleanup(struct drm_device *dev)
4323 {
4324         struct drm_i915_private *dev_priv = dev->dev_private;
4325         struct drm_crtc *crtc;
4326         struct intel_crtc *intel_crtc;
4327
4328         mutex_lock(&dev->struct_mutex);
4329
4330         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4331                 /* Skip inactive CRTCs */
4332                 if (!crtc->fb)
4333                         continue;
4334
4335                 intel_crtc = to_intel_crtc(crtc);
4336                 intel_increase_pllclock(crtc, false);
4337                 del_timer_sync(&intel_crtc->idle_timer);
4338         }
4339
4340         intel_increase_renderclock(dev, false);
4341         del_timer_sync(&dev_priv->idle_timer);
4342
4343         mutex_unlock(&dev->struct_mutex);
4344
4345         if (dev_priv->display.disable_fbc)
4346                 dev_priv->display.disable_fbc(dev);
4347
4348         drm_mode_config_cleanup(dev);
4349 }
4350
4351
4352 /* current intel driver doesn't take advantage of encoders
4353    always give back the encoder for the connector
4354 */
4355 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
4356 {
4357         struct intel_output *intel_output = to_intel_output(connector);
4358
4359         return &intel_output->enc;
4360 }
4361
4362 /*
4363  * set vga decode state - true == enable VGA decode
4364  */
4365 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
4366 {
4367         struct drm_i915_private *dev_priv = dev->dev_private;
4368         u16 gmch_ctrl;
4369
4370         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
4371         if (state)
4372                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
4373         else
4374                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
4375         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
4376         return 0;
4377 }