SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <linux/sysrq.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "i915_drm.h"
  33 #include "i915_drv.h"
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 #define MAX_NOPID ((u32)~0)
  38
  39 /**
  40  * Interrupts that are always left unmasked.
  41  *
  42  * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
  43  * we leave them always unmasked in IMR and then control enabling them through
  44  * PIPESTAT alone.
  45  */
  46 #define I915_INTERRUPT_ENABLE_FIX                       \
  47         (I915_ASLE_INTERRUPT |                          \
  48          I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |          \
  49          I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |          \
  50          I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |  \
  51          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |  \
  52          I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  53
  54 /** Interrupts that we mask and unmask at runtime. */
  55 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT)
  56
  57 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
  58                                  PIPE_VBLANK_INTERRUPT_STATUS)
  59
  60 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
  61                                  PIPE_VBLANK_INTERRUPT_ENABLE)
  62
  63 #define DRM_I915_VBLANK_PIPE_ALL        (DRM_I915_VBLANK_PIPE_A | \
  64                                          DRM_I915_VBLANK_PIPE_B)
  65
  66 void
  67 ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  68 {
  69         if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
  70                 dev_priv->gt_irq_mask_reg &= ~mask;
  71                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  72                 (void) I915_READ(GTIMR);
  73         }
  74 }
  75
  76 static inline void
  77 ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  78 {
  79         if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
  80                 dev_priv->gt_irq_mask_reg |= mask;
  81                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  82                 (void) I915_READ(GTIMR);
  83         }
  84 }
  85
  86 /* For display hotplug interrupt */
  87 void
  88 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  89 {
  90         if ((dev_priv->irq_mask_reg & mask) != 0) {
  91                 dev_priv->irq_mask_reg &= ~mask;
  92                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
  93                 (void) I915_READ(DEIMR);
  94         }
  95 }
  96
  97 static inline void
  98 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  99 {
 100         if ((dev_priv->irq_mask_reg & mask) != mask) {
 101                 dev_priv->irq_mask_reg |= mask;
 102                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
 103                 (void) I915_READ(DEIMR);
 104         }
 105 }
 106
 107 void
 108 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
 109 {
 110         if ((dev_priv->irq_mask_reg & mask) != 0) {
 111                 dev_priv->irq_mask_reg &= ~mask;
 112                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 113                 (void) I915_READ(IMR);
 114         }
 115 }
 116
 117 static inline void
 118 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
 119 {
 120         if ((dev_priv->irq_mask_reg & mask) != mask) {
 121                 dev_priv->irq_mask_reg |= mask;
 122                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 123                 (void) I915_READ(IMR);
 124         }
 125 }
 126
 127 static inline u32
 128 i915_pipestat(int pipe)
 129 {
 130         if (pipe == 0)
 131                 return PIPEASTAT;
 132         if (pipe == 1)
 133                 return PIPEBSTAT;
 134         BUG();
 135 }
 136
 137 void
 138 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 139 {
 140         if ((dev_priv->pipestat[pipe] & mask) != mask) {
 141                 u32 reg = i915_pipestat(pipe);
 142
 143                 dev_priv->pipestat[pipe] |= mask;
 144                 /* Enable the interrupt, clear any pending status */
 145                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
 146                 (void) I915_READ(reg);
 147         }
 148 }
 149
 150 void
 151 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 152 {
 153         if ((dev_priv->pipestat[pipe] & mask) != 0) {
 154                 u32 reg = i915_pipestat(pipe);
 155
 156                 dev_priv->pipestat[pipe] &= ~mask;
 157                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
 158                 (void) I915_READ(reg);
 159         }
 160 }
 161
 162 /**
 163  * intel_enable_asle - enable ASLE interrupt for OpRegion
 164  */
 165 void intel_enable_asle (struct drm_device *dev)
 166 {
 167         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 168
 169         if (IS_IRONLAKE(dev))
 170                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 171         else
 172                 i915_enable_pipestat(dev_priv, 1,
 173                                      I915_LEGACY_BLC_EVENT_ENABLE);
 174 }
 175
 176 /**
 177  * i915_pipe_enabled - check if a pipe is enabled
 178  * @dev: DRM device
 179  * @pipe: pipe to check
 180  *
 181  * Reading certain registers when the pipe is disabled can hang the chip.
 182  * Use this routine to make sure the PLL is running and the pipe is active
 183  * before reading such registers if unsure.
 184  */
 185 static int
 186 i915_pipe_enabled(struct drm_device *dev, int pipe)
 187 {
 188         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 189         unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
 190
 191         if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
 192                 return 1;
 193
 194         return 0;
 195 }
 196
 197 /* Called from drm generic code, passed a 'crtc', which
 198  * we use as a pipe index
 199  */
 200 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 201 {
 202         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 203         unsigned long high_frame;
 204         unsigned long low_frame;
 205         u32 high1, high2, low, count;
 206
 207         high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
 208         low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
 209
 210         if (!i915_pipe_enabled(dev, pipe)) {
 211                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 212                                 "pipe %d\n", pipe);
 213                 return 0;
 214         }
 215
 216         /*
 217          * High & low register fields aren't synchronized, so make sure
 218          * we get a low value that's stable across two reads of the high
 219          * register.
 220          */
 221         do {
 222                 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 223                          PIPE_FRAME_HIGH_SHIFT);
 224                 low =  ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
 225                         PIPE_FRAME_LOW_SHIFT);
 226                 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 227                          PIPE_FRAME_HIGH_SHIFT);
 228         } while (high1 != high2);
 229
 230         count = (high1 << 8) | low;
 231
 232         return count;
 233 }
 234
 235 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 236 {
 237         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 238         int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
 239
 240         if (!i915_pipe_enabled(dev, pipe)) {
 241                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 242                                         "pipe %d\n", pipe);
 243                 return 0;
 244         }
 245
 246         return I915_READ(reg);
 247 }
 248
 249 /*
 250  * Handle hotplug events outside the interrupt handler proper.
 251  */
 252 static void i915_hotplug_work_func(struct work_struct *work)
 253 {
 254         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 255                                                     hotplug_work);
 256         struct drm_device *dev = dev_priv->dev;
 257         struct drm_mode_config *mode_config = &dev->mode_config;
 258         struct drm_connector *connector;
 259
 260         if (mode_config->num_connector) {
 261                 list_for_each_entry(connector, &mode_config->connector_list, head) {
 262                         struct intel_output *intel_output = to_intel_output(connector);
 263
 264                         if (intel_output->hot_plug)
 265                                 (*intel_output->hot_plug) (intel_output);
 266                 }
 267         }
 268         /* Just fire off a uevent and let userspace tell us what to do */
 269         drm_sysfs_hotplug_event(dev);
 270 }
 271
 272 irqreturn_t ironlake_irq_handler(struct drm_device *dev)
 273 {
 274         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 275         int ret = IRQ_NONE;
 276         u32 de_iir, gt_iir, pch_iir;
 277         u32 new_de_iir, new_gt_iir, new_pch_iir;
 278         struct drm_i915_master_private *master_priv;
 279
 280         de_iir = I915_READ(DEIIR);
 281         gt_iir = I915_READ(GTIIR);
 282         pch_iir = I915_READ(SDEIIR);
 283
 284         for (;;) {
 285                 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0)
 286                         break;
 287
 288                 ret = IRQ_HANDLED;
 289
 290                 /* should clear PCH hotplug event before clear CPU irq */
 291                 I915_WRITE(SDEIIR, pch_iir);
 292                 new_pch_iir = I915_READ(SDEIIR);
 293
 294                 I915_WRITE(DEIIR, de_iir);
 295                 new_de_iir = I915_READ(DEIIR);
 296                 I915_WRITE(GTIIR, gt_iir);
 297                 new_gt_iir = I915_READ(GTIIR);
 298
 299                 if (dev->primary->master) {
 300                         master_priv = dev->primary->master->driver_priv;
 301                         if (master_priv->sarea_priv)
 302                                 master_priv->sarea_priv->last_dispatch =
 303                                         READ_BREADCRUMB(dev_priv);
 304                 }
 305
 306                 if (gt_iir & GT_USER_INTERRUPT) {
 307                         u32 seqno = i915_get_gem_seqno(dev);
 308                         dev_priv->mm.irq_gem_seqno = seqno;
 309                         trace_i915_gem_request_complete(dev, seqno);
 310                         DRM_WAKEUP(&dev_priv->irq_queue);
 311                 }
 312
 313                 if (de_iir & DE_GSE)
 314                         ironlake_opregion_gse_intr(dev);
 315
 316                 /* check event from PCH */
 317                 if ((de_iir & DE_PCH_EVENT) &&
 318                         (pch_iir & SDE_HOTPLUG_MASK)) {
 319                         queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 320                 }
 321
 322                 de_iir = new_de_iir;
 323                 gt_iir = new_gt_iir;
 324                 pch_iir = new_pch_iir;
 325         }
 326
 327         return ret;
 328 }
 329
 330 /**
 331  * i915_error_work_func - do process context error handling work
 332  * @work: work struct
 333  *
 334  * Fire an error uevent so userspace can see that a hang or error
 335  * was detected.
 336  */
 337 static void i915_error_work_func(struct work_struct *work)
 338 {
 339         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 340                                                     error_work);
 341         struct drm_device *dev = dev_priv->dev;
 342         char *error_event[] = { "ERROR=1", NULL };
 343         char *reset_event[] = { "RESET=1", NULL };
 344         char *reset_done_event[] = { "ERROR=0", NULL };
 345
 346         DRM_DEBUG_DRIVER("generating error event\n");
 347         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 348
 349         if (atomic_read(&dev_priv->mm.wedged)) {
 350                 if (IS_I965G(dev)) {
 351                         DRM_DEBUG_DRIVER("resetting chip\n");
 352                         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
 353                         if (!i965_reset(dev, GDRST_RENDER)) {
 354                                 atomic_set(&dev_priv->mm.wedged, 0);
 355                                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
 356                         }
 357                 } else {
 358                         DRM_DEBUG_DRIVER("reboot required\n");
 359                 }
 360         }
 361 }
 362
 363 /**
 364  * i915_capture_error_state - capture an error record for later analysis
 365  * @dev: drm device
 366  *
 367  * Should be called when an error is detected (either a hang or an error
 368  * interrupt) to capture error state from the time of the error.  Fills
 369  * out a structure which becomes available in debugfs for user level tools
 370  * to pick up.
 371  */
 372 static void i915_capture_error_state(struct drm_device *dev)
 373 {
 374         struct drm_i915_private *dev_priv = dev->dev_private;
 375         struct drm_i915_error_state *error;
 376         unsigned long flags;
 377
 378         spin_lock_irqsave(&dev_priv->error_lock, flags);
 379         if (dev_priv->first_error)
 380                 goto out;
 381
 382         error = kmalloc(sizeof(*error), GFP_ATOMIC);
 383         if (!error) {
 384                 DRM_DEBUG_DRIVER("out ot memory, not capturing error state\n");
 385                 goto out;
 386         }
 387
 388         error->eir = I915_READ(EIR);
 389         error->pgtbl_er = I915_READ(PGTBL_ER);
 390         error->pipeastat = I915_READ(PIPEASTAT);
 391         error->pipebstat = I915_READ(PIPEBSTAT);
 392         error->instpm = I915_READ(INSTPM);
 393         if (!IS_I965G(dev)) {
 394                 error->ipeir = I915_READ(IPEIR);
 395                 error->ipehr = I915_READ(IPEHR);
 396                 error->instdone = I915_READ(INSTDONE);
 397                 error->acthd = I915_READ(ACTHD);
 398         } else {
 399                 error->ipeir = I915_READ(IPEIR_I965);
 400                 error->ipehr = I915_READ(IPEHR_I965);
 401                 error->instdone = I915_READ(INSTDONE_I965);
 402                 error->instps = I915_READ(INSTPS);
 403                 error->instdone1 = I915_READ(INSTDONE1);
 404                 error->acthd = I915_READ(ACTHD_I965);
 405         }
 406
 407         do_gettimeofday(&error->time);
 408
 409         dev_priv->first_error = error;
 410
 411 out:
 412         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 413 }
 414
 415 /**
 416  * i915_handle_error - handle an error interrupt
 417  * @dev: drm device
 418  *
 419  * Do some basic checking of regsiter state at error interrupt time and
 420  * dump it to the syslog.  Also call i915_capture_error_state() to make
 421  * sure we get a record and make it available in debugfs.  Fire a uevent
 422  * so userspace knows something bad happened (should trigger collection
 423  * of a ring dump etc.).
 424  */
 425 static void i915_handle_error(struct drm_device *dev, bool wedged)
 426 {
 427         struct drm_i915_private *dev_priv = dev->dev_private;
 428         u32 eir = I915_READ(EIR);
 429         u32 pipea_stats = I915_READ(PIPEASTAT);
 430         u32 pipeb_stats = I915_READ(PIPEBSTAT);
 431
 432         i915_capture_error_state(dev);
 433
 434         printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
 435                eir);
 436
 437         if (IS_G4X(dev)) {
 438                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
 439                         u32 ipeir = I915_READ(IPEIR_I965);
 440
 441                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 442                                I915_READ(IPEIR_I965));
 443                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 444                                I915_READ(IPEHR_I965));
 445                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 446                                I915_READ(INSTDONE_I965));
 447                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 448                                I915_READ(INSTPS));
 449                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 450                                I915_READ(INSTDONE1));
 451                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 452                                I915_READ(ACTHD_I965));
 453                         I915_WRITE(IPEIR_I965, ipeir);
 454                         (void)I915_READ(IPEIR_I965);
 455                 }
 456                 if (eir & GM45_ERROR_PAGE_TABLE) {
 457                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 458                         printk(KERN_ERR "page table error\n");
 459                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 460                                pgtbl_err);
 461                         I915_WRITE(PGTBL_ER, pgtbl_err);
 462                         (void)I915_READ(PGTBL_ER);
 463                 }
 464         }
 465
 466         if (IS_I9XX(dev)) {
 467                 if (eir & I915_ERROR_PAGE_TABLE) {
 468                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 469                         printk(KERN_ERR "page table error\n");
 470                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 471                                pgtbl_err);
 472                         I915_WRITE(PGTBL_ER, pgtbl_err);
 473                         (void)I915_READ(PGTBL_ER);
 474                 }
 475         }
 476
 477         if (eir & I915_ERROR_MEMORY_REFRESH) {
 478                 printk(KERN_ERR "memory refresh error\n");
 479                 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
 480                        pipea_stats);
 481                 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
 482                        pipeb_stats);
 483                 /* pipestat has already been acked */
 484         }
 485         if (eir & I915_ERROR_INSTRUCTION) {
 486                 printk(KERN_ERR "instruction error\n");
 487                 printk(KERN_ERR "  INSTPM: 0x%08x\n",
 488                        I915_READ(INSTPM));
 489                 if (!IS_I965G(dev)) {
 490                         u32 ipeir = I915_READ(IPEIR);
 491
 492                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 493                                I915_READ(IPEIR));
 494                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 495                                I915_READ(IPEHR));
 496                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 497                                I915_READ(INSTDONE));
 498                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 499                                I915_READ(ACTHD));
 500                         I915_WRITE(IPEIR, ipeir);
 501                         (void)I915_READ(IPEIR);
 502                 } else {
 503                         u32 ipeir = I915_READ(IPEIR_I965);
 504
 505                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 506                                I915_READ(IPEIR_I965));
 507                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 508                                I915_READ(IPEHR_I965));
 509                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 510                                I915_READ(INSTDONE_I965));
 511                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 512                                I915_READ(INSTPS));
 513                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 514                                I915_READ(INSTDONE1));
 515                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 516                                I915_READ(ACTHD_I965));
 517                         I915_WRITE(IPEIR_I965, ipeir);
 518                         (void)I915_READ(IPEIR_I965);
 519                 }
 520         }
 521
 522         I915_WRITE(EIR, eir);
 523         (void)I915_READ(EIR);
 524         eir = I915_READ(EIR);
 525         if (eir) {
 526                 /*
 527                  * some errors might have become stuck,
 528                  * mask them.
 529                  */
 530                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
 531                 I915_WRITE(EMR, I915_READ(EMR) | eir);
 532                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
 533         }
 534
 535         if (wedged) {
 536                 atomic_set(&dev_priv->mm.wedged, 1);
 537
 538                 /*
 539                  * Wakeup waiting processes so they don't hang
 540                  */
 541                 printk("i915: Waking up sleeping processes\n");
 542                 DRM_WAKEUP(&dev_priv->irq_queue);
 543         }
 544
 545         queue_work(dev_priv->wq, &dev_priv->error_work);
 546 }
 547
 548 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 549 {
 550         struct drm_device *dev = (struct drm_device *) arg;
 551         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 552         struct drm_i915_master_private *master_priv;
 553         u32 iir, new_iir;
 554         u32 pipea_stats, pipeb_stats;
 555         u32 vblank_status;
 556         u32 vblank_enable;
 557         int vblank = 0;
 558         unsigned long irqflags;
 559         int irq_received;
 560         int ret = IRQ_NONE;
 561
 562         atomic_inc(&dev_priv->irq_received);
 563
 564         if (IS_IRONLAKE(dev))
 565                 return ironlake_irq_handler(dev);
 566
 567         iir = I915_READ(IIR);
 568
 569         if (IS_I965G(dev)) {
 570                 vblank_status = I915_START_VBLANK_INTERRUPT_STATUS;
 571                 vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE;
 572         } else {
 573                 vblank_status = I915_VBLANK_INTERRUPT_STATUS;
 574                 vblank_enable = I915_VBLANK_INTERRUPT_ENABLE;
 575         }
 576
 577         for (;;) {
 578                 irq_received = iir != 0;
 579
 580                 /* Can't rely on pipestat interrupt bit in iir as it might
 581                  * have been cleared after the pipestat interrupt was received.
 582                  * It doesn't set the bit in iir again, but it still produces
 583                  * interrupts (for non-MSI).
 584                  */
 585                 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 586                 pipea_stats = I915_READ(PIPEASTAT);
 587                 pipeb_stats = I915_READ(PIPEBSTAT);
 588
 589                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
 590                         i915_handle_error(dev, false);
 591
 592                 /*
 593                  * Clear the PIPE(A|B)STAT regs before the IIR
 594                  */
 595                 if (pipea_stats & 0x8000ffff) {
 596                         if (pipea_stats &  PIPE_FIFO_UNDERRUN_STATUS)
 597                                 DRM_DEBUG_DRIVER("pipe a underrun\n");
 598                         I915_WRITE(PIPEASTAT, pipea_stats);
 599                         irq_received = 1;
 600                 }
 601
 602                 if (pipeb_stats & 0x8000ffff) {
 603                         if (pipeb_stats &  PIPE_FIFO_UNDERRUN_STATUS)
 604                                 DRM_DEBUG_DRIVER("pipe b underrun\n");
 605                         I915_WRITE(PIPEBSTAT, pipeb_stats);
 606                         irq_received = 1;
 607                 }
 608                 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 609
 610                 if (!irq_received)
 611                         break;
 612
 613                 ret = IRQ_HANDLED;
 614
 615                 /* Consume port.  Then clear IIR or we'll miss events */
 616                 if ((I915_HAS_HOTPLUG(dev)) &&
 617                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
 618                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
 619
 620                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
 621                                   hotplug_status);
 622                         if (hotplug_status & dev_priv->hotplug_supported_mask)
 623                                 queue_work(dev_priv->wq,
 624                                            &dev_priv->hotplug_work);
 625
 626                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
 627                         I915_READ(PORT_HOTPLUG_STAT);
 628                 }
 629
 630                 I915_WRITE(IIR, iir);
 631                 new_iir = I915_READ(IIR); /* Flush posted writes */
 632
 633                 if (dev->primary->master) {
 634                         master_priv = dev->primary->master->driver_priv;
 635                         if (master_priv->sarea_priv)
 636                                 master_priv->sarea_priv->last_dispatch =
 637                                         READ_BREADCRUMB(dev_priv);
 638                 }
 639
 640                 if (iir & I915_USER_INTERRUPT) {
 641                         u32 seqno = i915_get_gem_seqno(dev);
 642                         dev_priv->mm.irq_gem_seqno = seqno;
 643                         trace_i915_gem_request_complete(dev, seqno);
 644                         DRM_WAKEUP(&dev_priv->irq_queue);
 645                         dev_priv->hangcheck_count = 0;
 646                         mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
 647                 }
 648
 649                 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
 650                         intel_prepare_page_flip(dev, 0);
 651
 652                 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
 653                         intel_prepare_page_flip(dev, 1);
 654
 655                 if (pipea_stats & vblank_status) {
 656                         vblank++;
 657                         drm_handle_vblank(dev, 0);
 658                         intel_finish_page_flip(dev, 0);
 659                 }
 660
 661                 if (pipeb_stats & vblank_status) {
 662                         vblank++;
 663                         drm_handle_vblank(dev, 1);
 664                         intel_finish_page_flip(dev, 1);
 665                 }
 666
 667                 if ((pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
 668                     (iir & I915_ASLE_INTERRUPT))
 669                         opregion_asle_intr(dev);
 670
 671                 /* With MSI, interrupts are only generated when iir
 672                  * transitions from zero to nonzero.  If another bit got
 673                  * set while we were handling the existing iir bits, then
 674                  * we would never get another interrupt.
 675                  *
 676                  * This is fine on non-MSI as well, as if we hit this path
 677                  * we avoid exiting the interrupt handler only to generate
 678                  * another one.
 679                  *
 680                  * Note that for MSI this could cause a stray interrupt report
 681                  * if an interrupt landed in the time between writing IIR and
 682                  * the posting read.  This should be rare enough to never
 683                  * trigger the 99% of 100,000 interrupts test for disabling
 684                  * stray interrupts.
 685                  */
 686                 iir = new_iir;
 687         }
 688
 689         return ret;
 690 }
 691
 692 static int i915_emit_irq(struct drm_device * dev)
 693 {
 694         drm_i915_private_t *dev_priv = dev->dev_private;
 695         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 696         RING_LOCALS;
 697
 698         i915_kernel_lost_context(dev);
 699
 700         DRM_DEBUG_DRIVER("\n");
 701
 702         dev_priv->counter++;
 703         if (dev_priv->counter > 0x7FFFFFFFUL)
 704                 dev_priv->counter = 1;
 705         if (master_priv->sarea_priv)
 706                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
 707
 708         BEGIN_LP_RING(4);
 709         OUT_RING(MI_STORE_DWORD_INDEX);
 710         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 711         OUT_RING(dev_priv->counter);
 712         OUT_RING(MI_USER_INTERRUPT);
 713         ADVANCE_LP_RING();
 714
 715         return dev_priv->counter;
 716 }
 717
 718 void i915_user_irq_get(struct drm_device *dev)
 719 {
 720         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 721         unsigned long irqflags;
 722
 723         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 724         if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) {
 725                 if (IS_IRONLAKE(dev))
 726                         ironlake_enable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
 727                 else
 728                         i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
 729         }
 730         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 731 }
 732
 733 void i915_user_irq_put(struct drm_device *dev)
 734 {
 735         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 736         unsigned long irqflags;
 737
 738         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 739         BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
 740         if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) {
 741                 if (IS_IRONLAKE(dev))
 742                         ironlake_disable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
 743                 else
 744                         i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
 745         }
 746         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 747 }
 748
 749 void i915_trace_irq_get(struct drm_device *dev, u32 seqno)
 750 {
 751         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 752
 753         if (dev_priv->trace_irq_seqno == 0)
 754                 i915_user_irq_get(dev);
 755
 756         dev_priv->trace_irq_seqno = seqno;
 757 }
 758
 759 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
 760 {
 761         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 762         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 763         int ret = 0;
 764
 765         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
 766                   READ_BREADCRUMB(dev_priv));
 767
 768         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
 769                 if (master_priv->sarea_priv)
 770                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 771                 return 0;
 772         }
 773
 774         if (master_priv->sarea_priv)
 775                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 776
 777         i915_user_irq_get(dev);
 778         DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
 779                     READ_BREADCRUMB(dev_priv) >= irq_nr);
 780         i915_user_irq_put(dev);
 781
 782         if (ret == -EBUSY) {
 783                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
 784                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
 785         }
 786
 787         return ret;
 788 }
 789
 790 /* Needs the lock as it touches the ring.
 791  */
 792 int i915_irq_emit(struct drm_device *dev, void *data,
 793                          struct drm_file *file_priv)
 794 {
 795         drm_i915_private_t *dev_priv = dev->dev_private;
 796         drm_i915_irq_emit_t *emit = data;
 797         int result;
 798
 799         if (!dev_priv || !dev_priv->ring.virtual_start) {
 800                 DRM_ERROR("called with no initialization\n");
 801                 return -EINVAL;
 802         }
 803
 804         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 805
 806         mutex_lock(&dev->struct_mutex);
 807         result = i915_emit_irq(dev);
 808         mutex_unlock(&dev->struct_mutex);
 809
 810         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
 811                 DRM_ERROR("copy_to_user\n");
 812                 return -EFAULT;
 813         }
 814
 815         return 0;
 816 }
 817
 818 /* Doesn't need the hardware lock.
 819  */
 820 int i915_irq_wait(struct drm_device *dev, void *data,
 821                          struct drm_file *file_priv)
 822 {
 823         drm_i915_private_t *dev_priv = dev->dev_private;
 824         drm_i915_irq_wait_t *irqwait = data;
 825
 826         if (!dev_priv) {
 827                 DRM_ERROR("called with no initialization\n");
 828                 return -EINVAL;
 829         }
 830
 831         return i915_wait_irq(dev, irqwait->irq_seq);
 832 }
 833
 834 /* Called from drm generic code, passed 'crtc' which
 835  * we use as a pipe index
 836  */
 837 int i915_enable_vblank(struct drm_device *dev, int pipe)
 838 {
 839         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 840         unsigned long irqflags;
 841         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
 842         u32 pipeconf;
 843
 844         pipeconf = I915_READ(pipeconf_reg);
 845         if (!(pipeconf & PIPEACONF_ENABLE))
 846                 return -EINVAL;
 847
 848         if (IS_IRONLAKE(dev))
 849                 return 0;
 850
 851         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 852         if (IS_I965G(dev))
 853                 i915_enable_pipestat(dev_priv, pipe,
 854                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
 855         else
 856                 i915_enable_pipestat(dev_priv, pipe,
 857                                      PIPE_VBLANK_INTERRUPT_ENABLE);
 858         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 859         return 0;
 860 }
 861
 862 /* Called from drm generic code, passed 'crtc' which
 863  * we use as a pipe index
 864  */
 865 void i915_disable_vblank(struct drm_device *dev, int pipe)
 866 {
 867         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 868         unsigned long irqflags;
 869
 870         if (IS_IRONLAKE(dev))
 871                 return;
 872
 873         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 874         i915_disable_pipestat(dev_priv, pipe,
 875                               PIPE_VBLANK_INTERRUPT_ENABLE |
 876                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
 877         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 878 }
 879
 880 void i915_enable_interrupt (struct drm_device *dev)
 881 {
 882         struct drm_i915_private *dev_priv = dev->dev_private;
 883
 884         if (!IS_IRONLAKE(dev))
 885                 opregion_enable_asle(dev);
 886         dev_priv->irq_enabled = 1;
 887 }
 888
 889
 890 /* Set the vblank monitor pipe
 891  */
 892 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
 893                          struct drm_file *file_priv)
 894 {
 895         drm_i915_private_t *dev_priv = dev->dev_private;
 896
 897         if (!dev_priv) {
 898                 DRM_ERROR("called with no initialization\n");
 899                 return -EINVAL;
 900         }
 901
 902         return 0;
 903 }
 904
 905 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 906                          struct drm_file *file_priv)
 907 {
 908         drm_i915_private_t *dev_priv = dev->dev_private;
 909         drm_i915_vblank_pipe_t *pipe = data;
 910
 911         if (!dev_priv) {
 912                 DRM_ERROR("called with no initialization\n");
 913                 return -EINVAL;
 914         }
 915
 916         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
 917
 918         return 0;
 919 }
 920
 921 /**
 922  * Schedule buffer swap at given vertical blank.
 923  */
 924 int i915_vblank_swap(struct drm_device *dev, void *data,
 925                      struct drm_file *file_priv)
 926 {
 927         /* The delayed swap mechanism was fundamentally racy, and has been
 928          * removed.  The model was that the client requested a delayed flip/swap
 929          * from the kernel, then waited for vblank before continuing to perform
 930          * rendering.  The problem was that the kernel might wake the client
 931          * up before it dispatched the vblank swap (since the lock has to be
 932          * held while touching the ringbuffer), in which case the client would
 933          * clear and start the next frame before the swap occurred, and
 934          * flicker would occur in addition to likely missing the vblank.
 935          *
 936          * In the absence of this ioctl, userland falls back to a correct path
 937          * of waiting for a vblank, then dispatching the swap on its own.
 938          * Context switching to userland and back is plenty fast enough for
 939          * meeting the requirements of vblank swapping.
 940          */
 941         return -EINVAL;
 942 }
 943
 944 struct drm_i915_gem_request *i915_get_tail_request(struct drm_device *dev) {
 945         drm_i915_private_t *dev_priv = dev->dev_private;
 946         return list_entry(dev_priv->mm.request_list.prev, struct drm_i915_gem_request, list);
 947 }
 948
 949 /**
 950  * This is called when the chip hasn't reported back with completed
 951  * batchbuffers in a long time. The first time this is called we simply record
 952  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
 953  * again, we assume the chip is wedged and try to fix it.
 954  */
 955 void i915_hangcheck_elapsed(unsigned long data)
 956 {
 957         struct drm_device *dev = (struct drm_device *)data;
 958         drm_i915_private_t *dev_priv = dev->dev_private;
 959         uint32_t acthd;
 960
 961         if (!IS_I965G(dev))
 962                 acthd = I915_READ(ACTHD);
 963         else
 964                 acthd = I915_READ(ACTHD_I965);
 965
 966         /* If all work is done then ACTHD clearly hasn't advanced. */
 967         if (list_empty(&dev_priv->mm.request_list) ||
 968                        i915_seqno_passed(i915_get_gem_seqno(dev), i915_get_tail_request(dev)->seqno)) {
 969                 dev_priv->hangcheck_count = 0;
 970                 return;
 971         }
 972
 973         if (dev_priv->last_acthd == acthd && dev_priv->hangcheck_count > 0) {
 974                 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
 975                 i915_handle_error(dev, true);
 976                 return;
 977         }
 978
 979         /* Reset timer case chip hangs without another request being added */
 980         mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
 981
 982         if (acthd != dev_priv->last_acthd)
 983                 dev_priv->hangcheck_count = 0;
 984         else
 985                 dev_priv->hangcheck_count++;
 986
 987         dev_priv->last_acthd = acthd;
 988 }
 989
 990 /* drm_dma.h hooks
 991 */
 992 static void ironlake_irq_preinstall(struct drm_device *dev)
 993 {
 994         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 995
 996         I915_WRITE(HWSTAM, 0xeffe);
 997
 998         /* XXX hotplug from PCH */
 999
1000         I915_WRITE(DEIMR, 0xffffffff);
1001         I915_WRITE(DEIER, 0x0);
1002         (void) I915_READ(DEIER);
1003
1004         /* and GT */
1005         I915_WRITE(GTIMR, 0xffffffff);
1006         I915_WRITE(GTIER, 0x0);
1007         (void) I915_READ(GTIER);
1008
1009         /* south display irq */
1010         I915_WRITE(SDEIMR, 0xffffffff);
1011         I915_WRITE(SDEIER, 0x0);
1012         (void) I915_READ(SDEIER);
1013 }
1014
1015 static int ironlake_irq_postinstall(struct drm_device *dev)
1016 {
1017         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1018         /* enable kind of interrupts always enabled */
1019         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT;
1020         u32 render_mask = GT_USER_INTERRUPT;
1021         u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
1022                            SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
1023
1024         dev_priv->irq_mask_reg = ~display_mask;
1025         dev_priv->de_irq_enable_reg = display_mask;
1026
1027         /* should always can generate irq */
1028         I915_WRITE(DEIIR, I915_READ(DEIIR));
1029         I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
1030         I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
1031         (void) I915_READ(DEIER);
1032
1033         /* user interrupt should be enabled, but masked initial */
1034         dev_priv->gt_irq_mask_reg = 0xffffffff;
1035         dev_priv->gt_irq_enable_reg = render_mask;
1036
1037         I915_WRITE(GTIIR, I915_READ(GTIIR));
1038         I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
1039         I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
1040         (void) I915_READ(GTIER);
1041
1042         dev_priv->pch_irq_mask_reg = ~hotplug_mask;
1043         dev_priv->pch_irq_enable_reg = hotplug_mask;
1044
1045         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1046         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg);
1047         I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg);
1048         (void) I915_READ(SDEIER);
1049
1050         return 0;
1051 }
1052
1053 void i915_driver_irq_preinstall(struct drm_device * dev)
1054 {
1055         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1056
1057         atomic_set(&dev_priv->irq_received, 0);
1058
1059         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1060         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1061
1062         if (IS_IRONLAKE(dev)) {
1063                 ironlake_irq_preinstall(dev);
1064                 return;
1065         }
1066
1067         if (I915_HAS_HOTPLUG(dev)) {
1068                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1069                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1070         }
1071
1072         I915_WRITE(HWSTAM, 0xeffe);
1073         I915_WRITE(PIPEASTAT, 0);
1074         I915_WRITE(PIPEBSTAT, 0);
1075         I915_WRITE(IMR, 0xffffffff);
1076         I915_WRITE(IER, 0x0);
1077         (void) I915_READ(IER);
1078 }
1079
1080 int i915_driver_irq_postinstall(struct drm_device *dev)
1081 {
1082         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1083         u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1084         u32 error_mask;
1085
1086         DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
1087
1088         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1089
1090         if (IS_IRONLAKE(dev))
1091                 return ironlake_irq_postinstall(dev);
1092
1093         /* Unmask the interrupts that we always want on. */
1094         dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
1095
1096         dev_priv->pipestat[0] = 0;
1097         dev_priv->pipestat[1] = 0;
1098
1099         if (I915_HAS_HOTPLUG(dev)) {
1100                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1101
1102                 /* Leave other bits alone */
1103                 hotplug_en |= HOTPLUG_EN_MASK;
1104                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1105
1106                 dev_priv->hotplug_supported_mask = CRT_HOTPLUG_INT_STATUS |
1107                         TV_HOTPLUG_INT_STATUS | SDVOC_HOTPLUG_INT_STATUS |
1108                         SDVOB_HOTPLUG_INT_STATUS;
1109                 if (IS_G4X(dev)) {
1110                         dev_priv->hotplug_supported_mask |=
1111                                 HDMIB_HOTPLUG_INT_STATUS |
1112                                 HDMIC_HOTPLUG_INT_STATUS |
1113                                 HDMID_HOTPLUG_INT_STATUS;
1114                 }
1115                 /* Enable in IER... */
1116                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1117                 /* and unmask in IMR */
1118                 i915_enable_irq(dev_priv, I915_DISPLAY_PORT_INTERRUPT);
1119         }
1120
1121         /*
1122          * Enable some error detection, note the instruction error mask
1123          * bit is reserved, so we leave it masked.
1124          */
1125         if (IS_G4X(dev)) {
1126                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1127                                GM45_ERROR_MEM_PRIV |
1128                                GM45_ERROR_CP_PRIV |
1129                                I915_ERROR_MEMORY_REFRESH);
1130         } else {
1131                 error_mask = ~(I915_ERROR_PAGE_TABLE |
1132                                I915_ERROR_MEMORY_REFRESH);
1133         }
1134         I915_WRITE(EMR, error_mask);
1135
1136         /* Disable pipe interrupt enables, clear pending pipe status */
1137         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1138         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1139         /* Clear pending interrupt status */
1140         I915_WRITE(IIR, I915_READ(IIR));
1141
1142         I915_WRITE(IER, enable_mask);
1143         I915_WRITE(IMR, dev_priv->irq_mask_reg);
1144         (void) I915_READ(IER);
1145
1146         opregion_enable_asle(dev);
1147
1148         return 0;
1149 }
1150
1151 static void ironlake_irq_uninstall(struct drm_device *dev)
1152 {
1153         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1154         I915_WRITE(HWSTAM, 0xffffffff);
1155
1156         I915_WRITE(DEIMR, 0xffffffff);
1157         I915_WRITE(DEIER, 0x0);
1158         I915_WRITE(DEIIR, I915_READ(DEIIR));
1159
1160         I915_WRITE(GTIMR, 0xffffffff);
1161         I915_WRITE(GTIER, 0x0);
1162         I915_WRITE(GTIIR, I915_READ(GTIIR));
1163 }
1164
1165 void i915_driver_irq_uninstall(struct drm_device * dev)
1166 {
1167         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1168
1169         if (!dev_priv)
1170                 return;
1171
1172         dev_priv->vblank_pipe = 0;
1173
1174         if (IS_IRONLAKE(dev)) {
1175                 ironlake_irq_uninstall(dev);
1176                 return;
1177         }
1178
1179         if (I915_HAS_HOTPLUG(dev)) {
1180                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1181                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1182         }
1183
1184         I915_WRITE(HWSTAM, 0xffffffff);
1185         I915_WRITE(PIPEASTAT, 0);
1186         I915_WRITE(PIPEBSTAT, 0);
1187         I915_WRITE(IMR, 0xffffffff);
1188         I915_WRITE(IER, 0x0);
1189
1190         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1191         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1192         I915_WRITE(IIR, I915_READ(IIR));
1193 }