SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <linux/sysrq.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "i915_drm.h"
  33 #include "i915_drv.h"
  34 #include "intel_drv.h"
  35
  36 #define MAX_NOPID ((u32)~0)
  37
  38 /**
  39  * Interrupts that are always left unmasked.
  40  *
  41  * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
  42  * we leave them always unmasked in IMR and then control enabling them through
  43  * PIPESTAT alone.
  44  */
  45 #define I915_INTERRUPT_ENABLE_FIX (I915_ASLE_INTERRUPT |                 \
  46                                    I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
  47                                    I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \
  48                                    I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  49
  50 /** Interrupts that we mask and unmask at runtime. */
  51 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT)
  52
  53 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
  54                                  PIPE_VBLANK_INTERRUPT_STATUS)
  55
  56 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
  57                                  PIPE_VBLANK_INTERRUPT_ENABLE)
  58
  59 #define DRM_I915_VBLANK_PIPE_ALL        (DRM_I915_VBLANK_PIPE_A | \
  60                                          DRM_I915_VBLANK_PIPE_B)
  61
  62 void
  63 igdng_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  64 {
  65         if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
  66                 dev_priv->gt_irq_mask_reg &= ~mask;
  67                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  68                 (void) I915_READ(GTIMR);
  69         }
  70 }
  71
  72 static inline void
  73 igdng_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  74 {
  75         if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
  76                 dev_priv->gt_irq_mask_reg |= mask;
  77                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  78                 (void) I915_READ(GTIMR);
  79         }
  80 }
  81
  82 /* For display hotplug interrupt */
  83 void
  84 igdng_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  85 {
  86         if ((dev_priv->irq_mask_reg & mask) != 0) {
  87                 dev_priv->irq_mask_reg &= ~mask;
  88                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
  89                 (void) I915_READ(DEIMR);
  90         }
  91 }
  92
  93 static inline void
  94 igdng_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  95 {
  96         if ((dev_priv->irq_mask_reg & mask) != mask) {
  97                 dev_priv->irq_mask_reg |= mask;
  98                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
  99                 (void) I915_READ(DEIMR);
 100         }
 101 }
 102
 103 void
 104 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
 105 {
 106         if ((dev_priv->irq_mask_reg & mask) != 0) {
 107                 dev_priv->irq_mask_reg &= ~mask;
 108                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 109                 (void) I915_READ(IMR);
 110         }
 111 }
 112
 113 static inline void
 114 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
 115 {
 116         if ((dev_priv->irq_mask_reg & mask) != mask) {
 117                 dev_priv->irq_mask_reg |= mask;
 118                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 119                 (void) I915_READ(IMR);
 120         }
 121 }
 122
 123 static inline u32
 124 i915_pipestat(int pipe)
 125 {
 126         if (pipe == 0)
 127                 return PIPEASTAT;
 128         if (pipe == 1)
 129                 return PIPEBSTAT;
 130         BUG();
 131 }
 132
 133 void
 134 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 135 {
 136         if ((dev_priv->pipestat[pipe] & mask) != mask) {
 137                 u32 reg = i915_pipestat(pipe);
 138
 139                 dev_priv->pipestat[pipe] |= mask;
 140                 /* Enable the interrupt, clear any pending status */
 141                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
 142                 (void) I915_READ(reg);
 143         }
 144 }
 145
 146 void
 147 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 148 {
 149         if ((dev_priv->pipestat[pipe] & mask) != 0) {
 150                 u32 reg = i915_pipestat(pipe);
 151
 152                 dev_priv->pipestat[pipe] &= ~mask;
 153                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
 154                 (void) I915_READ(reg);
 155         }
 156 }
 157
 158 /**
 159  * i915_pipe_enabled - check if a pipe is enabled
 160  * @dev: DRM device
 161  * @pipe: pipe to check
 162  *
 163  * Reading certain registers when the pipe is disabled can hang the chip.
 164  * Use this routine to make sure the PLL is running and the pipe is active
 165  * before reading such registers if unsure.
 166  */
 167 static int
 168 i915_pipe_enabled(struct drm_device *dev, int pipe)
 169 {
 170         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 171         unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
 172
 173         if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
 174                 return 1;
 175
 176         return 0;
 177 }
 178
 179 /* Called from drm generic code, passed a 'crtc', which
 180  * we use as a pipe index
 181  */
 182 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 183 {
 184         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 185         unsigned long high_frame;
 186         unsigned long low_frame;
 187         u32 high1, high2, low, count;
 188
 189         high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
 190         low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
 191
 192         if (!i915_pipe_enabled(dev, pipe)) {
 193                 DRM_DEBUG("trying to get vblank count for disabled pipe %d\n", pipe);
 194                 return 0;
 195         }
 196
 197         /*
 198          * High & low register fields aren't synchronized, so make sure
 199          * we get a low value that's stable across two reads of the high
 200          * register.
 201          */
 202         do {
 203                 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 204                          PIPE_FRAME_HIGH_SHIFT);
 205                 low =  ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
 206                         PIPE_FRAME_LOW_SHIFT);
 207                 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 208                          PIPE_FRAME_HIGH_SHIFT);
 209         } while (high1 != high2);
 210
 211         count = (high1 << 8) | low;
 212
 213         return count;
 214 }
 215
 216 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 217 {
 218         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 219         int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
 220
 221         if (!i915_pipe_enabled(dev, pipe)) {
 222                 DRM_DEBUG("trying to get vblank count for disabled pipe %d\n", pipe);
 223                 return 0;
 224         }
 225
 226         return I915_READ(reg);
 227 }
 228
 229 /*
 230  * Handle hotplug events outside the interrupt handler proper.
 231  */
 232 static void i915_hotplug_work_func(struct work_struct *work)
 233 {
 234         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 235                                                     hotplug_work);
 236         struct drm_device *dev = dev_priv->dev;
 237         struct drm_mode_config *mode_config = &dev->mode_config;
 238         struct drm_connector *connector;
 239
 240         if (mode_config->num_connector) {
 241                 list_for_each_entry(connector, &mode_config->connector_list, head) {
 242                         struct intel_output *intel_output = to_intel_output(connector);
 243
 244                         if (intel_output->hot_plug)
 245                                 (*intel_output->hot_plug) (intel_output);
 246                 }
 247         }
 248         /* Just fire off a uevent and let userspace tell us what to do */
 249         drm_sysfs_hotplug_event(dev);
 250 }
 251
 252 irqreturn_t igdng_irq_handler(struct drm_device *dev)
 253 {
 254         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 255         int ret = IRQ_NONE;
 256         u32 de_iir, gt_iir;
 257         u32 new_de_iir, new_gt_iir;
 258         struct drm_i915_master_private *master_priv;
 259
 260         de_iir = I915_READ(DEIIR);
 261         gt_iir = I915_READ(GTIIR);
 262
 263         for (;;) {
 264                 if (de_iir == 0 && gt_iir == 0)
 265                         break;
 266
 267                 ret = IRQ_HANDLED;
 268
 269                 I915_WRITE(DEIIR, de_iir);
 270                 new_de_iir = I915_READ(DEIIR);
 271                 I915_WRITE(GTIIR, gt_iir);
 272                 new_gt_iir = I915_READ(GTIIR);
 273
 274                 if (dev->primary->master) {
 275                         master_priv = dev->primary->master->driver_priv;
 276                         if (master_priv->sarea_priv)
 277                                 master_priv->sarea_priv->last_dispatch =
 278                                         READ_BREADCRUMB(dev_priv);
 279                 }
 280
 281                 if (gt_iir & GT_USER_INTERRUPT) {
 282                         dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev);
 283                         DRM_WAKEUP(&dev_priv->irq_queue);
 284                 }
 285
 286                 de_iir = new_de_iir;
 287                 gt_iir = new_gt_iir;
 288         }
 289
 290         return ret;
 291 }
 292
 293 /**
 294  * i915_error_work_func - do process context error handling work
 295  * @work: work struct
 296  *
 297  * Fire an error uevent so userspace can see that a hang or error
 298  * was detected.
 299  */
 300 static void i915_error_work_func(struct work_struct *work)
 301 {
 302         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 303                                                     error_work);
 304         struct drm_device *dev = dev_priv->dev;
 305         char *error_event[] = { "ERROR=1", NULL };
 306         char *reset_event[] = { "RESET=1", NULL };
 307         char *reset_done_event[] = { "ERROR=0", NULL };
 308
 309         DRM_DEBUG("generating error event\n");
 310         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 311
 312         if (atomic_read(&dev_priv->mm.wedged)) {
 313                 if (IS_I965G(dev)) {
 314                         DRM_DEBUG("resetting chip\n");
 315                         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
 316                         if (!i965_reset(dev, GDRST_RENDER)) {
 317                                 atomic_set(&dev_priv->mm.wedged, 0);
 318                                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
 319                         }
 320                 } else {
 321                         printk("reboot required\n");
 322                 }
 323         }
 324 }
 325
 326 /**
 327  * i915_capture_error_state - capture an error record for later analysis
 328  * @dev: drm device
 329  *
 330  * Should be called when an error is detected (either a hang or an error
 331  * interrupt) to capture error state from the time of the error.  Fills
 332  * out a structure which becomes available in debugfs for user level tools
 333  * to pick up.
 334  */
 335 static void i915_capture_error_state(struct drm_device *dev)
 336 {
 337         struct drm_i915_private *dev_priv = dev->dev_private;
 338         struct drm_i915_error_state *error;
 339         unsigned long flags;
 340
 341         spin_lock_irqsave(&dev_priv->error_lock, flags);
 342         if (dev_priv->first_error)
 343                 goto out;
 344
 345         error = kmalloc(sizeof(*error), GFP_ATOMIC);
 346         if (!error) {
 347                 DRM_DEBUG("out ot memory, not capturing error state\n");
 348                 goto out;
 349         }
 350
 351         error->eir = I915_READ(EIR);
 352         error->pgtbl_er = I915_READ(PGTBL_ER);
 353         error->pipeastat = I915_READ(PIPEASTAT);
 354         error->pipebstat = I915_READ(PIPEBSTAT);
 355         error->instpm = I915_READ(INSTPM);
 356         if (!IS_I965G(dev)) {
 357                 error->ipeir = I915_READ(IPEIR);
 358                 error->ipehr = I915_READ(IPEHR);
 359                 error->instdone = I915_READ(INSTDONE);
 360                 error->acthd = I915_READ(ACTHD);
 361         } else {
 362                 error->ipeir = I915_READ(IPEIR_I965);
 363                 error->ipehr = I915_READ(IPEHR_I965);
 364                 error->instdone = I915_READ(INSTDONE_I965);
 365                 error->instps = I915_READ(INSTPS);
 366                 error->instdone1 = I915_READ(INSTDONE1);
 367                 error->acthd = I915_READ(ACTHD_I965);
 368         }
 369
 370         do_gettimeofday(&error->time);
 371
 372         dev_priv->first_error = error;
 373
 374 out:
 375         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 376 }
 377
 378 /**
 379  * i915_handle_error - handle an error interrupt
 380  * @dev: drm device
 381  *
 382  * Do some basic checking of regsiter state at error interrupt time and
 383  * dump it to the syslog.  Also call i915_capture_error_state() to make
 384  * sure we get a record and make it available in debugfs.  Fire a uevent
 385  * so userspace knows something bad happened (should trigger collection
 386  * of a ring dump etc.).
 387  */
 388 static void i915_handle_error(struct drm_device *dev, bool wedged)
 389 {
 390         struct drm_i915_private *dev_priv = dev->dev_private;
 391         u32 eir = I915_READ(EIR);
 392         u32 pipea_stats = I915_READ(PIPEASTAT);
 393         u32 pipeb_stats = I915_READ(PIPEBSTAT);
 394
 395         i915_capture_error_state(dev);
 396
 397         printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
 398                eir);
 399
 400         if (IS_G4X(dev)) {
 401                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
 402                         u32 ipeir = I915_READ(IPEIR_I965);
 403
 404                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 405                                I915_READ(IPEIR_I965));
 406                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 407                                I915_READ(IPEHR_I965));
 408                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 409                                I915_READ(INSTDONE_I965));
 410                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 411                                I915_READ(INSTPS));
 412                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 413                                I915_READ(INSTDONE1));
 414                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 415                                I915_READ(ACTHD_I965));
 416                         I915_WRITE(IPEIR_I965, ipeir);
 417                         (void)I915_READ(IPEIR_I965);
 418                 }
 419                 if (eir & GM45_ERROR_PAGE_TABLE) {
 420                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 421                         printk(KERN_ERR "page table error\n");
 422                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 423                                pgtbl_err);
 424                         I915_WRITE(PGTBL_ER, pgtbl_err);
 425                         (void)I915_READ(PGTBL_ER);
 426                 }
 427         }
 428
 429         if (IS_I9XX(dev)) {
 430                 if (eir & I915_ERROR_PAGE_TABLE) {
 431                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 432                         printk(KERN_ERR "page table error\n");
 433                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 434                                pgtbl_err);
 435                         I915_WRITE(PGTBL_ER, pgtbl_err);
 436                         (void)I915_READ(PGTBL_ER);
 437                 }
 438         }
 439
 440         if (eir & I915_ERROR_MEMORY_REFRESH) {
 441                 printk(KERN_ERR "memory refresh error\n");
 442                 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
 443                        pipea_stats);
 444                 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
 445                        pipeb_stats);
 446                 /* pipestat has already been acked */
 447         }
 448         if (eir & I915_ERROR_INSTRUCTION) {
 449                 printk(KERN_ERR "instruction error\n");
 450                 printk(KERN_ERR "  INSTPM: 0x%08x\n",
 451                        I915_READ(INSTPM));
 452                 if (!IS_I965G(dev)) {
 453                         u32 ipeir = I915_READ(IPEIR);
 454
 455                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 456                                I915_READ(IPEIR));
 457                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 458                                I915_READ(IPEHR));
 459                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 460                                I915_READ(INSTDONE));
 461                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 462                                I915_READ(ACTHD));
 463                         I915_WRITE(IPEIR, ipeir);
 464                         (void)I915_READ(IPEIR);
 465                 } else {
 466                         u32 ipeir = I915_READ(IPEIR_I965);
 467
 468                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 469                                I915_READ(IPEIR_I965));
 470                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 471                                I915_READ(IPEHR_I965));
 472                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 473                                I915_READ(INSTDONE_I965));
 474                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 475                                I915_READ(INSTPS));
 476                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 477                                I915_READ(INSTDONE1));
 478                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 479                                I915_READ(ACTHD_I965));
 480                         I915_WRITE(IPEIR_I965, ipeir);
 481                         (void)I915_READ(IPEIR_I965);
 482                 }
 483         }
 484
 485         I915_WRITE(EIR, eir);
 486         (void)I915_READ(EIR);
 487         eir = I915_READ(EIR);
 488         if (eir) {
 489                 /*
 490                  * some errors might have become stuck,
 491                  * mask them.
 492                  */
 493                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
 494                 I915_WRITE(EMR, I915_READ(EMR) | eir);
 495                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
 496         }
 497
 498         if (wedged) {
 499                 atomic_set(&dev_priv->mm.wedged, 1);
 500
 501                 /*
 502                  * Wakeup waiting processes so they don't hang
 503                  */
 504                 printk("i915: Waking up sleeping processes\n");
 505                 DRM_WAKEUP(&dev_priv->irq_queue);
 506         }
 507
 508         queue_work(dev_priv->wq, &dev_priv->error_work);
 509 }
 510
 511 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 512 {
 513         struct drm_device *dev = (struct drm_device *) arg;
 514         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 515         struct drm_i915_master_private *master_priv;
 516         u32 iir, new_iir;
 517         u32 pipea_stats, pipeb_stats;
 518         u32 vblank_status;
 519         u32 vblank_enable;
 520         int vblank = 0;
 521         unsigned long irqflags;
 522         int irq_received;
 523         int ret = IRQ_NONE;
 524
 525         atomic_inc(&dev_priv->irq_received);
 526
 527         if (IS_IGDNG(dev))
 528                 return igdng_irq_handler(dev);
 529
 530         iir = I915_READ(IIR);
 531
 532         if (IS_I965G(dev)) {
 533                 vblank_status = I915_START_VBLANK_INTERRUPT_STATUS;
 534                 vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE;
 535         } else {
 536                 vblank_status = I915_VBLANK_INTERRUPT_STATUS;
 537                 vblank_enable = I915_VBLANK_INTERRUPT_ENABLE;
 538         }
 539
 540         for (;;) {
 541                 irq_received = iir != 0;
 542
 543                 /* Can't rely on pipestat interrupt bit in iir as it might
 544                  * have been cleared after the pipestat interrupt was received.
 545                  * It doesn't set the bit in iir again, but it still produces
 546                  * interrupts (for non-MSI).
 547                  */
 548                 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 549                 pipea_stats = I915_READ(PIPEASTAT);
 550                 pipeb_stats = I915_READ(PIPEBSTAT);
 551
 552                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
 553                         i915_handle_error(dev, false);
 554
 555                 /*
 556                  * Clear the PIPE(A|B)STAT regs before the IIR
 557                  */
 558                 if (pipea_stats & 0x8000ffff) {
 559                         if (pipea_stats &  PIPE_FIFO_UNDERRUN_STATUS)
 560                                 DRM_DEBUG("pipe a underrun\n");
 561                         I915_WRITE(PIPEASTAT, pipea_stats);
 562                         irq_received = 1;
 563                 }
 564
 565                 if (pipeb_stats & 0x8000ffff) {
 566                         if (pipeb_stats &  PIPE_FIFO_UNDERRUN_STATUS)
 567                                 DRM_DEBUG("pipe b underrun\n");
 568                         I915_WRITE(PIPEBSTAT, pipeb_stats);
 569                         irq_received = 1;
 570                 }
 571                 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 572
 573                 if (!irq_received)
 574                         break;
 575
 576                 ret = IRQ_HANDLED;
 577
 578                 /* Consume port.  Then clear IIR or we'll miss events */
 579                 if ((I915_HAS_HOTPLUG(dev)) &&
 580                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
 581                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
 582
 583                         DRM_DEBUG("hotplug event received, stat 0x%08x\n",
 584                                   hotplug_status);
 585                         if (hotplug_status & dev_priv->hotplug_supported_mask)
 586                                 queue_work(dev_priv->wq,
 587                                            &dev_priv->hotplug_work);
 588
 589                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
 590                         I915_READ(PORT_HOTPLUG_STAT);
 591
 592                         /* EOS interrupts occurs */
 593                         if (IS_IGD(dev) &&
 594                                 (hotplug_status & CRT_EOS_INT_STATUS)) {
 595                                 u32 temp;
 596
 597                                 DRM_DEBUG("EOS interrupt occurs\n");
 598                                 /* status is already cleared */
 599                                 temp = I915_READ(ADPA);
 600                                 temp &= ~ADPA_DAC_ENABLE;
 601                                 I915_WRITE(ADPA, temp);
 602
 603                                 temp = I915_READ(PORT_HOTPLUG_EN);
 604                                 temp &= ~CRT_EOS_INT_EN;
 605                                 I915_WRITE(PORT_HOTPLUG_EN, temp);
 606
 607                                 temp = I915_READ(PORT_HOTPLUG_STAT);
 608                                 if (temp & CRT_EOS_INT_STATUS)
 609                                         I915_WRITE(PORT_HOTPLUG_STAT,
 610                                                 CRT_EOS_INT_STATUS);
 611                         }
 612                 }
 613
 614                 I915_WRITE(IIR, iir);
 615                 new_iir = I915_READ(IIR); /* Flush posted writes */
 616
 617                 if (dev->primary->master) {
 618                         master_priv = dev->primary->master->driver_priv;
 619                         if (master_priv->sarea_priv)
 620                                 master_priv->sarea_priv->last_dispatch =
 621                                         READ_BREADCRUMB(dev_priv);
 622                 }
 623
 624                 if (iir & I915_USER_INTERRUPT) {
 625                         dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev);
 626                         DRM_WAKEUP(&dev_priv->irq_queue);
 627                         dev_priv->hangcheck_count = 0;
 628                         mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
 629                 }
 630
 631                 if (pipea_stats & vblank_status) {
 632                         vblank++;
 633                         drm_handle_vblank(dev, 0);
 634                 }
 635
 636                 if (pipeb_stats & vblank_status) {
 637                         vblank++;
 638                         drm_handle_vblank(dev, 1);
 639                 }
 640
 641                 if ((pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
 642                     (iir & I915_ASLE_INTERRUPT))
 643                         opregion_asle_intr(dev);
 644
 645                 /* With MSI, interrupts are only generated when iir
 646                  * transitions from zero to nonzero.  If another bit got
 647                  * set while we were handling the existing iir bits, then
 648                  * we would never get another interrupt.
 649                  *
 650                  * This is fine on non-MSI as well, as if we hit this path
 651                  * we avoid exiting the interrupt handler only to generate
 652                  * another one.
 653                  *
 654                  * Note that for MSI this could cause a stray interrupt report
 655                  * if an interrupt landed in the time between writing IIR and
 656                  * the posting read.  This should be rare enough to never
 657                  * trigger the 99% of 100,000 interrupts test for disabling
 658                  * stray interrupts.
 659                  */
 660                 iir = new_iir;
 661         }
 662
 663         return ret;
 664 }
 665
 666 static int i915_emit_irq(struct drm_device * dev)
 667 {
 668         drm_i915_private_t *dev_priv = dev->dev_private;
 669         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 670         RING_LOCALS;
 671
 672         i915_kernel_lost_context(dev);
 673
 674         DRM_DEBUG("\n");
 675
 676         dev_priv->counter++;
 677         if (dev_priv->counter > 0x7FFFFFFFUL)
 678                 dev_priv->counter = 1;
 679         if (master_priv->sarea_priv)
 680                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
 681
 682         BEGIN_LP_RING(4);
 683         OUT_RING(MI_STORE_DWORD_INDEX);
 684         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 685         OUT_RING(dev_priv->counter);
 686         OUT_RING(MI_USER_INTERRUPT);
 687         ADVANCE_LP_RING();
 688
 689         return dev_priv->counter;
 690 }
 691
 692 void i915_user_irq_get(struct drm_device *dev)
 693 {
 694         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 695         unsigned long irqflags;
 696
 697         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 698         if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) {
 699                 if (IS_IGDNG(dev))
 700                         igdng_enable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
 701                 else
 702                         i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
 703         }
 704         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 705 }
 706
 707 void i915_user_irq_put(struct drm_device *dev)
 708 {
 709         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 710         unsigned long irqflags;
 711
 712         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 713         BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
 714         if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) {
 715                 if (IS_IGDNG(dev))
 716                         igdng_disable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
 717                 else
 718                         i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
 719         }
 720         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 721 }
 722
 723 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
 724 {
 725         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 726         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 727         int ret = 0;
 728
 729         DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr,
 730                   READ_BREADCRUMB(dev_priv));
 731
 732         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
 733                 if (master_priv->sarea_priv)
 734                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 735                 return 0;
 736         }
 737
 738         if (master_priv->sarea_priv)
 739                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 740
 741         i915_user_irq_get(dev);
 742         DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
 743                     READ_BREADCRUMB(dev_priv) >= irq_nr);
 744         i915_user_irq_put(dev);
 745
 746         if (ret == -EBUSY) {
 747                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
 748                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
 749         }
 750
 751         return ret;
 752 }
 753
 754 /* Needs the lock as it touches the ring.
 755  */
 756 int i915_irq_emit(struct drm_device *dev, void *data,
 757                          struct drm_file *file_priv)
 758 {
 759         drm_i915_private_t *dev_priv = dev->dev_private;
 760         drm_i915_irq_emit_t *emit = data;
 761         int result;
 762
 763         if (!dev_priv || !dev_priv->ring.virtual_start) {
 764                 DRM_ERROR("called with no initialization\n");
 765                 return -EINVAL;
 766         }
 767
 768         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 769
 770         mutex_lock(&dev->struct_mutex);
 771         result = i915_emit_irq(dev);
 772         mutex_unlock(&dev->struct_mutex);
 773
 774         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
 775                 DRM_ERROR("copy_to_user\n");
 776                 return -EFAULT;
 777         }
 778
 779         return 0;
 780 }
 781
 782 /* Doesn't need the hardware lock.
 783  */
 784 int i915_irq_wait(struct drm_device *dev, void *data,
 785                          struct drm_file *file_priv)
 786 {
 787         drm_i915_private_t *dev_priv = dev->dev_private;
 788         drm_i915_irq_wait_t *irqwait = data;
 789
 790         if (!dev_priv) {
 791                 DRM_ERROR("called with no initialization\n");
 792                 return -EINVAL;
 793         }
 794
 795         return i915_wait_irq(dev, irqwait->irq_seq);
 796 }
 797
 798 /* Called from drm generic code, passed 'crtc' which
 799  * we use as a pipe index
 800  */
 801 int i915_enable_vblank(struct drm_device *dev, int pipe)
 802 {
 803         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 804         unsigned long irqflags;
 805         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
 806         u32 pipeconf;
 807
 808         pipeconf = I915_READ(pipeconf_reg);
 809         if (!(pipeconf & PIPEACONF_ENABLE))
 810                 return -EINVAL;
 811
 812         if (IS_IGDNG(dev))
 813                 return 0;
 814
 815         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 816         if (IS_I965G(dev))
 817                 i915_enable_pipestat(dev_priv, pipe,
 818                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
 819         else
 820                 i915_enable_pipestat(dev_priv, pipe,
 821                                      PIPE_VBLANK_INTERRUPT_ENABLE);
 822         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 823         return 0;
 824 }
 825
 826 /* Called from drm generic code, passed 'crtc' which
 827  * we use as a pipe index
 828  */
 829 void i915_disable_vblank(struct drm_device *dev, int pipe)
 830 {
 831         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 832         unsigned long irqflags;
 833
 834         if (IS_IGDNG(dev))
 835                 return;
 836
 837         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 838         i915_disable_pipestat(dev_priv, pipe,
 839                               PIPE_VBLANK_INTERRUPT_ENABLE |
 840                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
 841         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 842 }
 843
 844 void i915_enable_interrupt (struct drm_device *dev)
 845 {
 846         struct drm_i915_private *dev_priv = dev->dev_private;
 847
 848         if (!IS_IGDNG(dev))
 849                 opregion_enable_asle(dev);
 850         dev_priv->irq_enabled = 1;
 851 }
 852
 853
 854 /* Set the vblank monitor pipe
 855  */
 856 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
 857                          struct drm_file *file_priv)
 858 {
 859         drm_i915_private_t *dev_priv = dev->dev_private;
 860
 861         if (!dev_priv) {
 862                 DRM_ERROR("called with no initialization\n");
 863                 return -EINVAL;
 864         }
 865
 866         return 0;
 867 }
 868
 869 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 870                          struct drm_file *file_priv)
 871 {
 872         drm_i915_private_t *dev_priv = dev->dev_private;
 873         drm_i915_vblank_pipe_t *pipe = data;
 874
 875         if (!dev_priv) {
 876                 DRM_ERROR("called with no initialization\n");
 877                 return -EINVAL;
 878         }
 879
 880         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
 881
 882         return 0;
 883 }
 884
 885 /**
 886  * Schedule buffer swap at given vertical blank.
 887  */
 888 int i915_vblank_swap(struct drm_device *dev, void *data,
 889                      struct drm_file *file_priv)
 890 {
 891         /* The delayed swap mechanism was fundamentally racy, and has been
 892          * removed.  The model was that the client requested a delayed flip/swap
 893          * from the kernel, then waited for vblank before continuing to perform
 894          * rendering.  The problem was that the kernel might wake the client
 895          * up before it dispatched the vblank swap (since the lock has to be
 896          * held while touching the ringbuffer), in which case the client would
 897          * clear and start the next frame before the swap occurred, and
 898          * flicker would occur in addition to likely missing the vblank.
 899          *
 900          * In the absence of this ioctl, userland falls back to a correct path
 901          * of waiting for a vblank, then dispatching the swap on its own.
 902          * Context switching to userland and back is plenty fast enough for
 903          * meeting the requirements of vblank swapping.
 904          */
 905         return -EINVAL;
 906 }
 907
 908 struct drm_i915_gem_request *i915_get_tail_request(struct drm_device *dev) {
 909         drm_i915_private_t *dev_priv = dev->dev_private;
 910         return list_entry(dev_priv->mm.request_list.prev, struct drm_i915_gem_request, list);
 911 }
 912
 913 /**
 914  * This is called when the chip hasn't reported back with completed
 915  * batchbuffers in a long time. The first time this is called we simply record
 916  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
 917  * again, we assume the chip is wedged and try to fix it.
 918  */
 919 void i915_hangcheck_elapsed(unsigned long data)
 920 {
 921         struct drm_device *dev = (struct drm_device *)data;
 922         drm_i915_private_t *dev_priv = dev->dev_private;
 923         uint32_t acthd;
 924
 925         if (!IS_I965G(dev))
 926                 acthd = I915_READ(ACTHD);
 927         else
 928                 acthd = I915_READ(ACTHD_I965);
 929
 930         /* If all work is done then ACTHD clearly hasn't advanced. */
 931         if (list_empty(&dev_priv->mm.request_list) ||
 932                        i915_seqno_passed(i915_get_gem_seqno(dev), i915_get_tail_request(dev)->seqno)) {
 933                 dev_priv->hangcheck_count = 0;
 934                 return;
 935         }
 936
 937         if (dev_priv->last_acthd == acthd && dev_priv->hangcheck_count > 0) {
 938                 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
 939                 i915_handle_error(dev, true);
 940                 return;
 941         }
 942
 943         /* Reset timer case chip hangs without another request being added */
 944         mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
 945
 946         if (acthd != dev_priv->last_acthd)
 947                 dev_priv->hangcheck_count = 0;
 948         else
 949                 dev_priv->hangcheck_count++;
 950
 951         dev_priv->last_acthd = acthd;
 952 }
 953
 954 /* drm_dma.h hooks
 955 */
 956 static void igdng_irq_preinstall(struct drm_device *dev)
 957 {
 958         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 959
 960         I915_WRITE(HWSTAM, 0xeffe);
 961
 962         /* XXX hotplug from PCH */
 963
 964         I915_WRITE(DEIMR, 0xffffffff);
 965         I915_WRITE(DEIER, 0x0);
 966         (void) I915_READ(DEIER);
 967
 968         /* and GT */
 969         I915_WRITE(GTIMR, 0xffffffff);
 970         I915_WRITE(GTIER, 0x0);
 971         (void) I915_READ(GTIER);
 972 }
 973
 974 static int igdng_irq_postinstall(struct drm_device *dev)
 975 {
 976         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 977         /* enable kind of interrupts always enabled */
 978         u32 display_mask = DE_MASTER_IRQ_CONTROL /*| DE_PCH_EVENT */;
 979         u32 render_mask = GT_USER_INTERRUPT;
 980
 981         dev_priv->irq_mask_reg = ~display_mask;
 982         dev_priv->de_irq_enable_reg = display_mask;
 983
 984         /* should always can generate irq */
 985         I915_WRITE(DEIIR, I915_READ(DEIIR));
 986         I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
 987         I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
 988         (void) I915_READ(DEIER);
 989
 990         /* user interrupt should be enabled, but masked initial */
 991         dev_priv->gt_irq_mask_reg = 0xffffffff;
 992         dev_priv->gt_irq_enable_reg = render_mask;
 993
 994         I915_WRITE(GTIIR, I915_READ(GTIIR));
 995         I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
 996         I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
 997         (void) I915_READ(GTIER);
 998
 999         return 0;
1000 }
1001
1002 void i915_driver_irq_preinstall(struct drm_device * dev)
1003 {
1004         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1005
1006         atomic_set(&dev_priv->irq_received, 0);
1007
1008         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1009         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1010
1011         if (IS_IGDNG(dev)) {
1012                 igdng_irq_preinstall(dev);
1013                 return;
1014         }
1015
1016         if (I915_HAS_HOTPLUG(dev)) {
1017                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1018                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1019         }
1020
1021         I915_WRITE(HWSTAM, 0xeffe);
1022         I915_WRITE(PIPEASTAT, 0);
1023         I915_WRITE(PIPEBSTAT, 0);
1024         I915_WRITE(IMR, 0xffffffff);
1025         I915_WRITE(IER, 0x0);
1026         (void) I915_READ(IER);
1027 }
1028
1029 int i915_driver_irq_postinstall(struct drm_device *dev)
1030 {
1031         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1032         u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1033         u32 error_mask;
1034
1035         DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
1036
1037         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1038
1039         if (IS_IGDNG(dev))
1040                 return igdng_irq_postinstall(dev);
1041
1042         /* Unmask the interrupts that we always want on. */
1043         dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
1044
1045         dev_priv->pipestat[0] = 0;
1046         dev_priv->pipestat[1] = 0;
1047
1048         if (I915_HAS_HOTPLUG(dev)) {
1049                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1050
1051                 /* Leave other bits alone */
1052                 hotplug_en |= HOTPLUG_EN_MASK;
1053                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1054
1055                 dev_priv->hotplug_supported_mask = CRT_HOTPLUG_INT_STATUS |
1056                         TV_HOTPLUG_INT_STATUS | SDVOC_HOTPLUG_INT_STATUS |
1057                         SDVOB_HOTPLUG_INT_STATUS;
1058                 if (IS_G4X(dev)) {
1059                         dev_priv->hotplug_supported_mask |=
1060                                 HDMIB_HOTPLUG_INT_STATUS |
1061                                 HDMIC_HOTPLUG_INT_STATUS |
1062                                 HDMID_HOTPLUG_INT_STATUS;
1063                 }
1064                 /* Enable in IER... */
1065                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1066                 /* and unmask in IMR */
1067                 i915_enable_irq(dev_priv, I915_DISPLAY_PORT_INTERRUPT);
1068         }
1069
1070         /*
1071          * Enable some error detection, note the instruction error mask
1072          * bit is reserved, so we leave it masked.
1073          */
1074         if (IS_G4X(dev)) {
1075                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1076                                GM45_ERROR_MEM_PRIV |
1077                                GM45_ERROR_CP_PRIV |
1078                                I915_ERROR_MEMORY_REFRESH);
1079         } else {
1080                 error_mask = ~(I915_ERROR_PAGE_TABLE |
1081                                I915_ERROR_MEMORY_REFRESH);
1082         }
1083         I915_WRITE(EMR, error_mask);
1084
1085         /* Disable pipe interrupt enables, clear pending pipe status */
1086         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1087         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1088         /* Clear pending interrupt status */
1089         I915_WRITE(IIR, I915_READ(IIR));
1090
1091         I915_WRITE(IER, enable_mask);
1092         I915_WRITE(IMR, dev_priv->irq_mask_reg);
1093         (void) I915_READ(IER);
1094
1095         opregion_enable_asle(dev);
1096
1097         return 0;
1098 }
1099
1100 static void igdng_irq_uninstall(struct drm_device *dev)
1101 {
1102         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1103         I915_WRITE(HWSTAM, 0xffffffff);
1104
1105         I915_WRITE(DEIMR, 0xffffffff);
1106         I915_WRITE(DEIER, 0x0);
1107         I915_WRITE(DEIIR, I915_READ(DEIIR));
1108
1109         I915_WRITE(GTIMR, 0xffffffff);
1110         I915_WRITE(GTIER, 0x0);
1111         I915_WRITE(GTIIR, I915_READ(GTIIR));
1112 }
1113
1114 void i915_driver_irq_uninstall(struct drm_device * dev)
1115 {
1116         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1117
1118         if (!dev_priv)
1119                 return;
1120
1121         dev_priv->vblank_pipe = 0;
1122
1123         if (IS_IGDNG(dev)) {
1124                 igdng_irq_uninstall(dev);
1125                 return;
1126         }
1127
1128         if (I915_HAS_HOTPLUG(dev)) {
1129                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1130                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1131         }
1132
1133         I915_WRITE(HWSTAM, 0xffffffff);
1134         I915_WRITE(PIPEASTAT, 0);
1135         I915_WRITE(PIPEBSTAT, 0);
1136         I915_WRITE(IMR, 0xffffffff);
1137         I915_WRITE(IER, 0x0);
1138
1139         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1140         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1141         I915_WRITE(IIR, I915_READ(IIR));
1142 }