SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "i915_drm.h"
  31 #include "i915_drv.h"
  32 #include <linux/swap.h>
  33 #include <linux/pci.h>
  34
  35 #define I915_GEM_GPU_DOMAINS    (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
  36
  37 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
  38 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
  39 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
  40 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
  41                                              int write);
  42 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
  43                                                      uint64_t offset,
  44                                                      uint64_t size);
  45 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
  46 static int i915_gem_object_get_page_list(struct drm_gem_object *obj);
  47 static void i915_gem_object_free_page_list(struct drm_gem_object *obj);
  48 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
  49 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
  50                                            unsigned alignment);
  51 static int i915_gem_object_get_fence_reg(struct drm_gem_object *obj, bool write);
  52 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
  53 static int i915_gem_evict_something(struct drm_device *dev);
  54 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
  55                                 struct drm_i915_gem_pwrite *args,
  56                                 struct drm_file *file_priv);
  57
  58 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
  59                      unsigned long end)
  60 {
  61         drm_i915_private_t *dev_priv = dev->dev_private;
  62
  63         if (start >= end ||
  64             (start & (PAGE_SIZE - 1)) != 0 ||
  65             (end & (PAGE_SIZE - 1)) != 0) {
  66                 return -EINVAL;
  67         }
  68
  69         drm_mm_init(&dev_priv->mm.gtt_space, start,
  70                     end - start);
  71
  72         dev->gtt_total = (uint32_t) (end - start);
  73
  74         return 0;
  75 }
  76
  77 int
  78 i915_gem_init_ioctl(struct drm_device *dev, void *data,
  79                     struct drm_file *file_priv)
  80 {
  81         struct drm_i915_gem_init *args = data;
  82         int ret;
  83
  84         mutex_lock(&dev->struct_mutex);
  85         ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
  86         mutex_unlock(&dev->struct_mutex);
  87
  88         return ret;
  89 }
  90
  91 int
  92 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
  93                             struct drm_file *file_priv)
  94 {
  95         struct drm_i915_gem_get_aperture *args = data;
  96
  97         if (!(dev->driver->driver_features & DRIVER_GEM))
  98                 return -ENODEV;
  99
 100         args->aper_size = dev->gtt_total;
 101         args->aper_available_size = (args->aper_size -
 102                                      atomic_read(&dev->pin_memory));
 103
 104         return 0;
 105 }
 106
 107
 108 /**
 109  * Creates a new mm object and returns a handle to it.
 110  */
 111 int
 112 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 113                       struct drm_file *file_priv)
 114 {
 115         struct drm_i915_gem_create *args = data;
 116         struct drm_gem_object *obj;
 117         int handle, ret;
 118
 119         args->size = roundup(args->size, PAGE_SIZE);
 120
 121         /* Allocate the new object */
 122         obj = drm_gem_object_alloc(dev, args->size);
 123         if (obj == NULL)
 124                 return -ENOMEM;
 125
 126         ret = drm_gem_handle_create(file_priv, obj, &handle);
 127         mutex_lock(&dev->struct_mutex);
 128         drm_gem_object_handle_unreference(obj);
 129         mutex_unlock(&dev->struct_mutex);
 130
 131         if (ret)
 132                 return ret;
 133
 134         args->handle = handle;
 135
 136         return 0;
 137 }
 138
 139 /**
 140  * Reads data from the object referenced by handle.
 141  *
 142  * On error, the contents of *data are undefined.
 143  */
 144 int
 145 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 146                      struct drm_file *file_priv)
 147 {
 148         struct drm_i915_gem_pread *args = data;
 149         struct drm_gem_object *obj;
 150         struct drm_i915_gem_object *obj_priv;
 151         ssize_t read;
 152         loff_t offset;
 153         int ret;
 154
 155         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 156         if (obj == NULL)
 157                 return -EBADF;
 158         obj_priv = obj->driver_private;
 159
 160         /* Bounds check source.
 161          *
 162          * XXX: This could use review for overflow issues...
 163          */
 164         if (args->offset > obj->size || args->size > obj->size ||
 165             args->offset + args->size > obj->size) {
 166                 drm_gem_object_unreference(obj);
 167                 return -EINVAL;
 168         }
 169
 170         mutex_lock(&dev->struct_mutex);
 171
 172         ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
 173                                                         args->size);
 174         if (ret != 0) {
 175                 drm_gem_object_unreference(obj);
 176                 mutex_unlock(&dev->struct_mutex);
 177                 return ret;
 178         }
 179
 180         offset = args->offset;
 181
 182         read = vfs_read(obj->filp, (char __user *)(uintptr_t)args->data_ptr,
 183                         args->size, &offset);
 184         if (read != args->size) {
 185                 drm_gem_object_unreference(obj);
 186                 mutex_unlock(&dev->struct_mutex);
 187                 if (read < 0)
 188                         return read;
 189                 else
 190                         return -EINVAL;
 191         }
 192
 193         drm_gem_object_unreference(obj);
 194         mutex_unlock(&dev->struct_mutex);
 195
 196         return 0;
 197 }
 198
 199 /* This is the fast write path which cannot handle
 200  * page faults in the source data
 201  */
 202
 203 static inline int
 204 fast_user_write(struct io_mapping *mapping,
 205                 loff_t page_base, int page_offset,
 206                 char __user *user_data,
 207                 int length)
 208 {
 209         char *vaddr_atomic;
 210         unsigned long unwritten;
 211
 212         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 213         unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
 214                                                       user_data, length);
 215         io_mapping_unmap_atomic(vaddr_atomic);
 216         if (unwritten)
 217                 return -EFAULT;
 218         return 0;
 219 }
 220
 221 /* Here's the write path which can sleep for
 222  * page faults
 223  */
 224
 225 static inline int
 226 slow_user_write(struct io_mapping *mapping,
 227                 loff_t page_base, int page_offset,
 228                 char __user *user_data,
 229                 int length)
 230 {
 231         char __iomem *vaddr;
 232         unsigned long unwritten;
 233
 234         vaddr = io_mapping_map_wc(mapping, page_base);
 235         if (vaddr == NULL)
 236                 return -EFAULT;
 237         unwritten = __copy_from_user(vaddr + page_offset,
 238                                      user_data, length);
 239         io_mapping_unmap(vaddr);
 240         if (unwritten)
 241                 return -EFAULT;
 242         return 0;
 243 }
 244
 245 static int
 246 i915_gem_gtt_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
 247                     struct drm_i915_gem_pwrite *args,
 248                     struct drm_file *file_priv)
 249 {
 250         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 251         drm_i915_private_t *dev_priv = dev->dev_private;
 252         ssize_t remain;
 253         loff_t offset, page_base;
 254         char __user *user_data;
 255         int page_offset, page_length;
 256         int ret;
 257
 258         user_data = (char __user *) (uintptr_t) args->data_ptr;
 259         remain = args->size;
 260         if (!access_ok(VERIFY_READ, user_data, remain))
 261                 return -EFAULT;
 262
 263
 264         mutex_lock(&dev->struct_mutex);
 265         ret = i915_gem_object_pin(obj, 0);
 266         if (ret) {
 267                 mutex_unlock(&dev->struct_mutex);
 268                 return ret;
 269         }
 270         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
 271         if (ret)
 272                 goto fail;
 273
 274         obj_priv = obj->driver_private;
 275         offset = obj_priv->gtt_offset + args->offset;
 276         obj_priv->dirty = 1;
 277
 278         while (remain > 0) {
 279                 /* Operation in this page
 280                  *
 281                  * page_base = page offset within aperture
 282                  * page_offset = offset within page
 283                  * page_length = bytes to copy for this page
 284                  */
 285                 page_base = (offset & ~(PAGE_SIZE-1));
 286                 page_offset = offset & (PAGE_SIZE-1);
 287                 page_length = remain;
 288                 if ((page_offset + remain) > PAGE_SIZE)
 289                         page_length = PAGE_SIZE - page_offset;
 290
 291                 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
 292                                        page_offset, user_data, page_length);
 293
 294                 /* If we get a fault while copying data, then (presumably) our
 295                  * source page isn't available. In this case, use the
 296                  * non-atomic function
 297                  */
 298                 if (ret) {
 299                         ret = slow_user_write (dev_priv->mm.gtt_mapping,
 300                                                page_base, page_offset,
 301                                                user_data, page_length);
 302                         if (ret)
 303                                 goto fail;
 304                 }
 305
 306                 remain -= page_length;
 307                 user_data += page_length;
 308                 offset += page_length;
 309         }
 310
 311 fail:
 312         i915_gem_object_unpin(obj);
 313         mutex_unlock(&dev->struct_mutex);
 314
 315         return ret;
 316 }
 317
 318 static int
 319 i915_gem_shmem_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
 320                       struct drm_i915_gem_pwrite *args,
 321                       struct drm_file *file_priv)
 322 {
 323         int ret;
 324         loff_t offset;
 325         ssize_t written;
 326
 327         mutex_lock(&dev->struct_mutex);
 328
 329         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
 330         if (ret) {
 331                 mutex_unlock(&dev->struct_mutex);
 332                 return ret;
 333         }
 334
 335         offset = args->offset;
 336
 337         written = vfs_write(obj->filp,
 338                             (char __user *)(uintptr_t) args->data_ptr,
 339                             args->size, &offset);
 340         if (written != args->size) {
 341                 mutex_unlock(&dev->struct_mutex);
 342                 if (written < 0)
 343                         return written;
 344                 else
 345                         return -EINVAL;
 346         }
 347
 348         mutex_unlock(&dev->struct_mutex);
 349
 350         return 0;
 351 }
 352
 353 /**
 354  * Writes data to the object referenced by handle.
 355  *
 356  * On error, the contents of the buffer that were to be modified are undefined.
 357  */
 358 int
 359 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 360                       struct drm_file *file_priv)
 361 {
 362         struct drm_i915_gem_pwrite *args = data;
 363         struct drm_gem_object *obj;
 364         struct drm_i915_gem_object *obj_priv;
 365         int ret = 0;
 366
 367         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 368         if (obj == NULL)
 369                 return -EBADF;
 370         obj_priv = obj->driver_private;
 371
 372         /* Bounds check destination.
 373          *
 374          * XXX: This could use review for overflow issues...
 375          */
 376         if (args->offset > obj->size || args->size > obj->size ||
 377             args->offset + args->size > obj->size) {
 378                 drm_gem_object_unreference(obj);
 379                 return -EINVAL;
 380         }
 381
 382         /* We can only do the GTT pwrite on untiled buffers, as otherwise
 383          * it would end up going through the fenced access, and we'll get
 384          * different detiling behavior between reading and writing.
 385          * pread/pwrite currently are reading and writing from the CPU
 386          * perspective, requiring manual detiling by the client.
 387          */
 388         if (obj_priv->phys_obj)
 389                 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
 390         else if (obj_priv->tiling_mode == I915_TILING_NONE &&
 391                  dev->gtt_total != 0)
 392                 ret = i915_gem_gtt_pwrite(dev, obj, args, file_priv);
 393         else
 394                 ret = i915_gem_shmem_pwrite(dev, obj, args, file_priv);
 395
 396 #if WATCH_PWRITE
 397         if (ret)
 398                 DRM_INFO("pwrite failed %d\n", ret);
 399 #endif
 400
 401         drm_gem_object_unreference(obj);
 402
 403         return ret;
 404 }
 405
 406 /**
 407  * Called when user space prepares to use an object with the CPU, either
 408  * through the mmap ioctl's mapping or a GTT mapping.
 409  */
 410 int
 411 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
 412                           struct drm_file *file_priv)
 413 {
 414         struct drm_i915_gem_set_domain *args = data;
 415         struct drm_gem_object *obj;
 416         uint32_t read_domains = args->read_domains;
 417         uint32_t write_domain = args->write_domain;
 418         int ret;
 419
 420         if (!(dev->driver->driver_features & DRIVER_GEM))
 421                 return -ENODEV;
 422
 423         /* Only handle setting domains to types used by the CPU. */
 424         if (write_domain & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
 425                 return -EINVAL;
 426
 427         if (read_domains & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
 428                 return -EINVAL;
 429
 430         /* Having something in the write domain implies it's in the read
 431          * domain, and only that read domain.  Enforce that in the request.
 432          */
 433         if (write_domain != 0 && read_domains != write_domain)
 434                 return -EINVAL;
 435
 436         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 437         if (obj == NULL)
 438                 return -EBADF;
 439
 440         mutex_lock(&dev->struct_mutex);
 441 #if WATCH_BUF
 442         DRM_INFO("set_domain_ioctl %p(%d), %08x %08x\n",
 443                  obj, obj->size, read_domains, write_domain);
 444 #endif
 445         if (read_domains & I915_GEM_DOMAIN_GTT) {
 446                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
 447
 448                 /* Silently promote "you're not bound, there was nothing to do"
 449                  * to success, since the client was just asking us to
 450                  * make sure everything was done.
 451                  */
 452                 if (ret == -EINVAL)
 453                         ret = 0;
 454         } else {
 455                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
 456         }
 457
 458         drm_gem_object_unreference(obj);
 459         mutex_unlock(&dev->struct_mutex);
 460         return ret;
 461 }
 462
 463 /**
 464  * Called when user space has done writes to this buffer
 465  */
 466 int
 467 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
 468                       struct drm_file *file_priv)
 469 {
 470         struct drm_i915_gem_sw_finish *args = data;
 471         struct drm_gem_object *obj;
 472         struct drm_i915_gem_object *obj_priv;
 473         int ret = 0;
 474
 475         if (!(dev->driver->driver_features & DRIVER_GEM))
 476                 return -ENODEV;
 477
 478         mutex_lock(&dev->struct_mutex);
 479         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 480         if (obj == NULL) {
 481                 mutex_unlock(&dev->struct_mutex);
 482                 return -EBADF;
 483         }
 484
 485 #if WATCH_BUF
 486         DRM_INFO("%s: sw_finish %d (%p %d)\n",
 487                  __func__, args->handle, obj, obj->size);
 488 #endif
 489         obj_priv = obj->driver_private;
 490
 491         /* Pinned buffers may be scanout, so flush the cache */
 492         if (obj_priv->pin_count)
 493                 i915_gem_object_flush_cpu_write_domain(obj);
 494
 495         drm_gem_object_unreference(obj);
 496         mutex_unlock(&dev->struct_mutex);
 497         return ret;
 498 }
 499
 500 /**
 501  * Maps the contents of an object, returning the address it is mapped
 502  * into.
 503  *
 504  * While the mapping holds a reference on the contents of the object, it doesn't
 505  * imply a ref on the object itself.
 506  */
 507 int
 508 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
 509                    struct drm_file *file_priv)
 510 {
 511         struct drm_i915_gem_mmap *args = data;
 512         struct drm_gem_object *obj;
 513         loff_t offset;
 514         unsigned long addr;
 515
 516         if (!(dev->driver->driver_features & DRIVER_GEM))
 517                 return -ENODEV;
 518
 519         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 520         if (obj == NULL)
 521                 return -EBADF;
 522
 523         offset = args->offset;
 524
 525         down_write(&current->mm->mmap_sem);
 526         addr = do_mmap(obj->filp, 0, args->size,
 527                        PROT_READ | PROT_WRITE, MAP_SHARED,
 528                        args->offset);
 529         up_write(&current->mm->mmap_sem);
 530         mutex_lock(&dev->struct_mutex);
 531         drm_gem_object_unreference(obj);
 532         mutex_unlock(&dev->struct_mutex);
 533         if (IS_ERR((void *)addr))
 534                 return addr;
 535
 536         args->addr_ptr = (uint64_t) addr;
 537
 538         return 0;
 539 }
 540
 541 /**
 542  * i915_gem_fault - fault a page into the GTT
 543  * vma: VMA in question
 544  * vmf: fault info
 545  *
 546  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
 547  * from userspace.  The fault handler takes care of binding the object to
 548  * the GTT (if needed), allocating and programming a fence register (again,
 549  * only if needed based on whether the old reg is still valid or the object
 550  * is tiled) and inserting a new PTE into the faulting process.
 551  *
 552  * Note that the faulting process may involve evicting existing objects
 553  * from the GTT and/or fence registers to make room.  So performance may
 554  * suffer if the GTT working set is large or there are few fence registers
 555  * left.
 556  */
 557 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
 558 {
 559         struct drm_gem_object *obj = vma->vm_private_data;
 560         struct drm_device *dev = obj->dev;
 561         struct drm_i915_private *dev_priv = dev->dev_private;
 562         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 563         pgoff_t page_offset;
 564         unsigned long pfn;
 565         int ret = 0;
 566         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
 567
 568         /* We don't use vmf->pgoff since that has the fake offset */
 569         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
 570                 PAGE_SHIFT;
 571
 572         /* Now bind it into the GTT if needed */
 573         mutex_lock(&dev->struct_mutex);
 574         if (!obj_priv->gtt_space) {
 575                 ret = i915_gem_object_bind_to_gtt(obj, obj_priv->gtt_alignment);
 576                 if (ret) {
 577                         mutex_unlock(&dev->struct_mutex);
 578                         return VM_FAULT_SIGBUS;
 579                 }
 580                 list_add(&obj_priv->list, &dev_priv->mm.inactive_list);
 581         }
 582
 583         /* Need a new fence register? */
 584         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
 585             obj_priv->tiling_mode != I915_TILING_NONE) {
 586                 ret = i915_gem_object_get_fence_reg(obj, write);
 587                 if (ret) {
 588                         mutex_unlock(&dev->struct_mutex);
 589                         return VM_FAULT_SIGBUS;
 590                 }
 591         }
 592
 593         pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
 594                 page_offset;
 595
 596         /* Finally, remap it using the new GTT offset */
 597         ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
 598
 599         mutex_unlock(&dev->struct_mutex);
 600
 601         switch (ret) {
 602         case -ENOMEM:
 603         case -EAGAIN:
 604                 return VM_FAULT_OOM;
 605         case -EFAULT:
 606                 return VM_FAULT_SIGBUS;
 607         default:
 608                 return VM_FAULT_NOPAGE;
 609         }
 610 }
 611
 612 /**
 613  * i915_gem_create_mmap_offset - create a fake mmap offset for an object
 614  * @obj: obj in question
 615  *
 616  * GEM memory mapping works by handing back to userspace a fake mmap offset
 617  * it can use in a subsequent mmap(2) call.  The DRM core code then looks
 618  * up the object based on the offset and sets up the various memory mapping
 619  * structures.
 620  *
 621  * This routine allocates and attaches a fake offset for @obj.
 622  */
 623 static int
 624 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
 625 {
 626         struct drm_device *dev = obj->dev;
 627         struct drm_gem_mm *mm = dev->mm_private;
 628         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 629         struct drm_map_list *list;
 630         struct drm_map *map;
 631         int ret = 0;
 632
 633         /* Set the object up for mmap'ing */
 634         list = &obj->map_list;
 635         list->map = drm_calloc(1, sizeof(struct drm_map_list),
 636                                DRM_MEM_DRIVER);
 637         if (!list->map)
 638                 return -ENOMEM;
 639
 640         map = list->map;
 641         map->type = _DRM_GEM;
 642         map->size = obj->size;
 643         map->handle = obj;
 644
 645         /* Get a DRM GEM mmap offset allocated... */
 646         list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
 647                                                     obj->size / PAGE_SIZE, 0, 0);
 648         if (!list->file_offset_node) {
 649                 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
 650                 ret = -ENOMEM;
 651                 goto out_free_list;
 652         }
 653
 654         list->file_offset_node = drm_mm_get_block(list->file_offset_node,
 655                                                   obj->size / PAGE_SIZE, 0);
 656         if (!list->file_offset_node) {
 657                 ret = -ENOMEM;
 658                 goto out_free_list;
 659         }
 660
 661         list->hash.key = list->file_offset_node->start;
 662         if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
 663                 DRM_ERROR("failed to add to map hash\n");
 664                 goto out_free_mm;
 665         }
 666
 667         /* By now we should be all set, any drm_mmap request on the offset
 668          * below will get to our mmap & fault handler */
 669         obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
 670
 671         return 0;
 672
 673 out_free_mm:
 674         drm_mm_put_block(list->file_offset_node);
 675 out_free_list:
 676         drm_free(list->map, sizeof(struct drm_map_list), DRM_MEM_DRIVER);
 677
 678         return ret;
 679 }
 680
 681 static void
 682 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
 683 {
 684         struct drm_device *dev = obj->dev;
 685         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 686         struct drm_gem_mm *mm = dev->mm_private;
 687         struct drm_map_list *list;
 688
 689         list = &obj->map_list;
 690         drm_ht_remove_item(&mm->offset_hash, &list->hash);
 691
 692         if (list->file_offset_node) {
 693                 drm_mm_put_block(list->file_offset_node);
 694                 list->file_offset_node = NULL;
 695         }
 696
 697         if (list->map) {
 698                 drm_free(list->map, sizeof(struct drm_map), DRM_MEM_DRIVER);
 699                 list->map = NULL;
 700         }
 701
 702         obj_priv->mmap_offset = 0;
 703 }
 704
 705 /**
 706  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
 707  * @obj: object to check
 708  *
 709  * Return the required GTT alignment for an object, taking into account
 710  * potential fence register mapping if needed.
 711  */
 712 static uint32_t
 713 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
 714 {
 715         struct drm_device *dev = obj->dev;
 716         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 717         int start, i;
 718
 719         /*
 720          * Minimum alignment is 4k (GTT page size), but might be greater
 721          * if a fence register is needed for the object.
 722          */
 723         if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
 724                 return 4096;
 725
 726         /*
 727          * Previous chips need to be aligned to the size of the smallest
 728          * fence register that can contain the object.
 729          */
 730         if (IS_I9XX(dev))
 731                 start = 1024*1024;
 732         else
 733                 start = 512*1024;
 734
 735         for (i = start; i < obj->size; i <<= 1)
 736                 ;
 737
 738         return i;
 739 }
 740
 741 /**
 742  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
 743  * @dev: DRM device
 744  * @data: GTT mapping ioctl data
 745  * @file_priv: GEM object info
 746  *
 747  * Simply returns the fake offset to userspace so it can mmap it.
 748  * The mmap call will end up in drm_gem_mmap(), which will set things
 749  * up so we can get faults in the handler above.
 750  *
 751  * The fault handler will take care of binding the object into the GTT
 752  * (since it may have been evicted to make room for something), allocating
 753  * a fence register, and mapping the appropriate aperture address into
 754  * userspace.
 755  */
 756 int
 757 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
 758                         struct drm_file *file_priv)
 759 {
 760         struct drm_i915_gem_mmap_gtt *args = data;
 761         struct drm_i915_private *dev_priv = dev->dev_private;
 762         struct drm_gem_object *obj;
 763         struct drm_i915_gem_object *obj_priv;
 764         int ret;
 765
 766         if (!(dev->driver->driver_features & DRIVER_GEM))
 767                 return -ENODEV;
 768
 769         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 770         if (obj == NULL)
 771                 return -EBADF;
 772
 773         mutex_lock(&dev->struct_mutex);
 774
 775         obj_priv = obj->driver_private;
 776
 777         if (!obj_priv->mmap_offset) {
 778                 ret = i915_gem_create_mmap_offset(obj);
 779                 if (ret) {
 780                         drm_gem_object_unreference(obj);
 781                         mutex_unlock(&dev->struct_mutex);
 782                         return ret;
 783                 }
 784         }
 785
 786         args->offset = obj_priv->mmap_offset;
 787
 788         obj_priv->gtt_alignment = i915_gem_get_gtt_alignment(obj);
 789
 790         /* Make sure the alignment is correct for fence regs etc */
 791         if (obj_priv->agp_mem &&
 792             (obj_priv->gtt_offset & (obj_priv->gtt_alignment - 1))) {
 793                 drm_gem_object_unreference(obj);
 794                 mutex_unlock(&dev->struct_mutex);
 795                 return -EINVAL;
 796         }
 797
 798         /*
 799          * Pull it into the GTT so that we have a page list (makes the
 800          * initial fault faster and any subsequent flushing possible).
 801          */
 802         if (!obj_priv->agp_mem) {
 803                 ret = i915_gem_object_bind_to_gtt(obj, obj_priv->gtt_alignment);
 804                 if (ret) {
 805                         drm_gem_object_unreference(obj);
 806                         mutex_unlock(&dev->struct_mutex);
 807                         return ret;
 808                 }
 809                 list_add(&obj_priv->list, &dev_priv->mm.inactive_list);
 810         }
 811
 812         drm_gem_object_unreference(obj);
 813         mutex_unlock(&dev->struct_mutex);
 814
 815         return 0;
 816 }
 817
 818 static void
 819 i915_gem_object_free_page_list(struct drm_gem_object *obj)
 820 {
 821         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 822         int page_count = obj->size / PAGE_SIZE;
 823         int i;
 824
 825         if (obj_priv->page_list == NULL)
 826                 return;
 827
 828
 829         for (i = 0; i < page_count; i++)
 830                 if (obj_priv->page_list[i] != NULL) {
 831                         if (obj_priv->dirty)
 832                                 set_page_dirty(obj_priv->page_list[i]);
 833                         mark_page_accessed(obj_priv->page_list[i]);
 834                         page_cache_release(obj_priv->page_list[i]);
 835                 }
 836         obj_priv->dirty = 0;
 837
 838         drm_free(obj_priv->page_list,
 839                  page_count * sizeof(struct page *),
 840                  DRM_MEM_DRIVER);
 841         obj_priv->page_list = NULL;
 842 }
 843
 844 static void
 845 i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
 846 {
 847         struct drm_device *dev = obj->dev;
 848         drm_i915_private_t *dev_priv = dev->dev_private;
 849         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 850
 851         /* Add a reference if we're newly entering the active list. */
 852         if (!obj_priv->active) {
 853                 drm_gem_object_reference(obj);
 854                 obj_priv->active = 1;
 855         }
 856         /* Move from whatever list we were on to the tail of execution. */
 857         list_move_tail(&obj_priv->list,
 858                        &dev_priv->mm.active_list);
 859         obj_priv->last_rendering_seqno = seqno;
 860 }
 861
 862 static void
 863 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
 864 {
 865         struct drm_device *dev = obj->dev;
 866         drm_i915_private_t *dev_priv = dev->dev_private;
 867         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 868
 869         BUG_ON(!obj_priv->active);
 870         list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
 871         obj_priv->last_rendering_seqno = 0;
 872 }
 873
 874 static void
 875 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
 876 {
 877         struct drm_device *dev = obj->dev;
 878         drm_i915_private_t *dev_priv = dev->dev_private;
 879         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 880
 881         i915_verify_inactive(dev, __FILE__, __LINE__);
 882         if (obj_priv->pin_count != 0)
 883                 list_del_init(&obj_priv->list);
 884         else
 885                 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
 886
 887         obj_priv->last_rendering_seqno = 0;
 888         if (obj_priv->active) {
 889                 obj_priv->active = 0;
 890                 drm_gem_object_unreference(obj);
 891         }
 892         i915_verify_inactive(dev, __FILE__, __LINE__);
 893 }
 894
 895 /**
 896  * Creates a new sequence number, emitting a write of it to the status page
 897  * plus an interrupt, which will trigger i915_user_interrupt_handler.
 898  *
 899  * Must be called with struct_lock held.
 900  *
 901  * Returned sequence numbers are nonzero on success.
 902  */
 903 static uint32_t
 904 i915_add_request(struct drm_device *dev, uint32_t flush_domains)
 905 {
 906         drm_i915_private_t *dev_priv = dev->dev_private;
 907         struct drm_i915_gem_request *request;
 908         uint32_t seqno;
 909         int was_empty;
 910         RING_LOCALS;
 911
 912         request = drm_calloc(1, sizeof(*request), DRM_MEM_DRIVER);
 913         if (request == NULL)
 914                 return 0;
 915
 916         /* Grab the seqno we're going to make this request be, and bump the
 917          * next (skipping 0 so it can be the reserved no-seqno value).
 918          */
 919         seqno = dev_priv->mm.next_gem_seqno;
 920         dev_priv->mm.next_gem_seqno++;
 921         if (dev_priv->mm.next_gem_seqno == 0)
 922                 dev_priv->mm.next_gem_seqno++;
 923
 924         BEGIN_LP_RING(4);
 925         OUT_RING(MI_STORE_DWORD_INDEX);
 926         OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 927         OUT_RING(seqno);
 928
 929         OUT_RING(MI_USER_INTERRUPT);
 930         ADVANCE_LP_RING();
 931
 932         DRM_DEBUG("%d\n", seqno);
 933
 934         request->seqno = seqno;
 935         request->emitted_jiffies = jiffies;
 936         was_empty = list_empty(&dev_priv->mm.request_list);
 937         list_add_tail(&request->list, &dev_priv->mm.request_list);
 938
 939         /* Associate any objects on the flushing list matching the write
 940          * domain we're flushing with our flush.
 941          */
 942         if (flush_domains != 0) {
 943                 struct drm_i915_gem_object *obj_priv, *next;
 944
 945                 list_for_each_entry_safe(obj_priv, next,
 946                                          &dev_priv->mm.flushing_list, list) {
 947                         struct drm_gem_object *obj = obj_priv->obj;
 948
 949                         if ((obj->write_domain & flush_domains) ==
 950                             obj->write_domain) {
 951                                 obj->write_domain = 0;
 952                                 i915_gem_object_move_to_active(obj, seqno);
 953                         }
 954                 }
 955
 956         }
 957
 958         if (was_empty && !dev_priv->mm.suspended)
 959                 schedule_delayed_work(&dev_priv->mm.retire_work, HZ);
 960         return seqno;
 961 }
 962
 963 /**
 964  * Command execution barrier
 965  *
 966  * Ensures that all commands in the ring are finished
 967  * before signalling the CPU
 968  */
 969 static uint32_t
 970 i915_retire_commands(struct drm_device *dev)
 971 {
 972         drm_i915_private_t *dev_priv = dev->dev_private;
 973         uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 974         uint32_t flush_domains = 0;
 975         RING_LOCALS;
 976
 977         /* The sampler always gets flushed on i965 (sigh) */
 978         if (IS_I965G(dev))
 979                 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
 980         BEGIN_LP_RING(2);
 981         OUT_RING(cmd);
 982         OUT_RING(0); /* noop */
 983         ADVANCE_LP_RING();
 984         return flush_domains;
 985 }
 986
 987 /**
 988  * Moves buffers associated only with the given active seqno from the active
 989  * to inactive list, potentially freeing them.
 990  */
 991 static void
 992 i915_gem_retire_request(struct drm_device *dev,
 993                         struct drm_i915_gem_request *request)
 994 {
 995         drm_i915_private_t *dev_priv = dev->dev_private;
 996
 997         /* Move any buffers on the active list that are no longer referenced
 998          * by the ringbuffer to the flushing/inactive lists as appropriate.
 999          */
1000         while (!list_empty(&dev_priv->mm.active_list)) {
1001                 struct drm_gem_object *obj;
1002                 struct drm_i915_gem_object *obj_priv;
1003
1004                 obj_priv = list_first_entry(&dev_priv->mm.active_list,
1005                                             struct drm_i915_gem_object,
1006                                             list);
1007                 obj = obj_priv->obj;
1008
1009                 /* If the seqno being retired doesn't match the oldest in the
1010                  * list, then the oldest in the list must still be newer than
1011                  * this seqno.
1012                  */
1013                 if (obj_priv->last_rendering_seqno != request->seqno)
1014                         return;
1015
1016 #if WATCH_LRU
1017                 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1018                          __func__, request->seqno, obj);
1019 #endif
1020
1021                 if (obj->write_domain != 0)
1022                         i915_gem_object_move_to_flushing(obj);
1023                 else
1024                         i915_gem_object_move_to_inactive(obj);
1025         }
1026 }
1027
1028 /**
1029  * Returns true if seq1 is later than seq2.
1030  */
1031 static int
1032 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1033 {
1034         return (int32_t)(seq1 - seq2) >= 0;
1035 }
1036
1037 uint32_t
1038 i915_get_gem_seqno(struct drm_device *dev)
1039 {
1040         drm_i915_private_t *dev_priv = dev->dev_private;
1041
1042         return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
1043 }
1044
1045 /**
1046  * This function clears the request list as sequence numbers are passed.
1047  */
1048 void
1049 i915_gem_retire_requests(struct drm_device *dev)
1050 {
1051         drm_i915_private_t *dev_priv = dev->dev_private;
1052         uint32_t seqno;
1053
1054         seqno = i915_get_gem_seqno(dev);
1055
1056         while (!list_empty(&dev_priv->mm.request_list)) {
1057                 struct drm_i915_gem_request *request;
1058                 uint32_t retiring_seqno;
1059
1060                 request = list_first_entry(&dev_priv->mm.request_list,
1061                                            struct drm_i915_gem_request,
1062                                            list);
1063                 retiring_seqno = request->seqno;
1064
1065                 if (i915_seqno_passed(seqno, retiring_seqno) ||
1066                     dev_priv->mm.wedged) {
1067                         i915_gem_retire_request(dev, request);
1068
1069                         list_del(&request->list);
1070                         drm_free(request, sizeof(*request), DRM_MEM_DRIVER);
1071                 } else
1072                         break;
1073         }
1074 }
1075
1076 void
1077 i915_gem_retire_work_handler(struct work_struct *work)
1078 {
1079         drm_i915_private_t *dev_priv;
1080         struct drm_device *dev;
1081
1082         dev_priv = container_of(work, drm_i915_private_t,
1083                                 mm.retire_work.work);
1084         dev = dev_priv->dev;
1085
1086         mutex_lock(&dev->struct_mutex);
1087         i915_gem_retire_requests(dev);
1088         if (!dev_priv->mm.suspended &&
1089             !list_empty(&dev_priv->mm.request_list))
1090                 schedule_delayed_work(&dev_priv->mm.retire_work, HZ);
1091         mutex_unlock(&dev->struct_mutex);
1092 }
1093
1094 /**
1095  * Waits for a sequence number to be signaled, and cleans up the
1096  * request and object lists appropriately for that event.
1097  */
1098 static int
1099 i915_wait_request(struct drm_device *dev, uint32_t seqno)
1100 {
1101         drm_i915_private_t *dev_priv = dev->dev_private;
1102         int ret = 0;
1103
1104         BUG_ON(seqno == 0);
1105
1106         if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
1107                 dev_priv->mm.waiting_gem_seqno = seqno;
1108                 i915_user_irq_get(dev);
1109                 ret = wait_event_interruptible(dev_priv->irq_queue,
1110                                                i915_seqno_passed(i915_get_gem_seqno(dev),
1111                                                                  seqno) ||
1112                                                dev_priv->mm.wedged);
1113                 i915_user_irq_put(dev);
1114                 dev_priv->mm.waiting_gem_seqno = 0;
1115         }
1116         if (dev_priv->mm.wedged)
1117                 ret = -EIO;
1118
1119         if (ret && ret != -ERESTARTSYS)
1120                 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1121                           __func__, ret, seqno, i915_get_gem_seqno(dev));
1122
1123         /* Directly dispatch request retiring.  While we have the work queue
1124          * to handle this, the waiter on a request often wants an associated
1125          * buffer to have made it to the inactive list, and we would need
1126          * a separate wait queue to handle that.
1127          */
1128         if (ret == 0)
1129                 i915_gem_retire_requests(dev);
1130
1131         return ret;
1132 }
1133
1134 static void
1135 i915_gem_flush(struct drm_device *dev,
1136                uint32_t invalidate_domains,
1137                uint32_t flush_domains)
1138 {
1139         drm_i915_private_t *dev_priv = dev->dev_private;
1140         uint32_t cmd;
1141         RING_LOCALS;
1142
1143 #if WATCH_EXEC
1144         DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
1145                   invalidate_domains, flush_domains);
1146 #endif
1147
1148         if (flush_domains & I915_GEM_DOMAIN_CPU)
1149                 drm_agp_chipset_flush(dev);
1150
1151         if ((invalidate_domains | flush_domains) & ~(I915_GEM_DOMAIN_CPU |
1152                                                      I915_GEM_DOMAIN_GTT)) {
1153                 /*
1154                  * read/write caches:
1155                  *
1156                  * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1157                  * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
1158                  * also flushed at 2d versus 3d pipeline switches.
1159                  *
1160                  * read-only caches:
1161                  *
1162                  * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1163                  * MI_READ_FLUSH is set, and is always flushed on 965.
1164                  *
1165                  * I915_GEM_DOMAIN_COMMAND may not exist?
1166                  *
1167                  * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1168                  * invalidated when MI_EXE_FLUSH is set.
1169                  *
1170                  * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1171                  * invalidated with every MI_FLUSH.
1172                  *
1173                  * TLBs:
1174                  *
1175                  * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1176                  * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1177                  * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1178                  * are flushed at any MI_FLUSH.
1179                  */
1180
1181                 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1182                 if ((invalidate_domains|flush_domains) &
1183                     I915_GEM_DOMAIN_RENDER)
1184                         cmd &= ~MI_NO_WRITE_FLUSH;
1185                 if (!IS_I965G(dev)) {
1186                         /*
1187                          * On the 965, the sampler cache always gets flushed
1188                          * and this bit is reserved.
1189                          */
1190                         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
1191                                 cmd |= MI_READ_FLUSH;
1192                 }
1193                 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
1194                         cmd |= MI_EXE_FLUSH;
1195
1196 #if WATCH_EXEC
1197                 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
1198 #endif
1199                 BEGIN_LP_RING(2);
1200                 OUT_RING(cmd);
1201                 OUT_RING(0); /* noop */
1202                 ADVANCE_LP_RING();
1203         }
1204 }
1205
1206 /**
1207  * Ensures that all rendering to the object has completed and the object is
1208  * safe to unbind from the GTT or access from the CPU.
1209  */
1210 static int
1211 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1212 {
1213         struct drm_device *dev = obj->dev;
1214         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1215         int ret;
1216
1217         /* This function only exists to support waiting for existing rendering,
1218          * not for emitting required flushes.
1219          */
1220         BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
1221
1222         /* If there is rendering queued on the buffer being evicted, wait for
1223          * it.
1224          */
1225         if (obj_priv->active) {
1226 #if WATCH_BUF
1227                 DRM_INFO("%s: object %p wait for seqno %08x\n",
1228                           __func__, obj, obj_priv->last_rendering_seqno);
1229 #endif
1230                 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
1231                 if (ret != 0)
1232                         return ret;
1233         }
1234
1235         return 0;
1236 }
1237
1238 /**
1239  * Unbinds an object from the GTT aperture.
1240  */
1241 int
1242 i915_gem_object_unbind(struct drm_gem_object *obj)
1243 {
1244         struct drm_device *dev = obj->dev;
1245         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1246         loff_t offset;
1247         int ret = 0;
1248
1249 #if WATCH_BUF
1250         DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1251         DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1252 #endif
1253         if (obj_priv->gtt_space == NULL)
1254                 return 0;
1255
1256         if (obj_priv->pin_count != 0) {
1257                 DRM_ERROR("Attempting to unbind pinned buffer\n");
1258                 return -EINVAL;
1259         }
1260
1261         /* Move the object to the CPU domain to ensure that
1262          * any possible CPU writes while it's not in the GTT
1263          * are flushed when we go to remap it. This will
1264          * also ensure that all pending GPU writes are finished
1265          * before we unbind.
1266          */
1267         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1268         if (ret) {
1269                 if (ret != -ERESTARTSYS)
1270                         DRM_ERROR("set_domain failed: %d\n", ret);
1271                 return ret;
1272         }
1273
1274         if (obj_priv->agp_mem != NULL) {
1275                 drm_unbind_agp(obj_priv->agp_mem);
1276                 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
1277                 obj_priv->agp_mem = NULL;
1278         }
1279
1280         BUG_ON(obj_priv->active);
1281
1282         /* blow away mappings if mapped through GTT */
1283         offset = ((loff_t) obj->map_list.hash.key) << PAGE_SHIFT;
1284         if (dev->dev_mapping)
1285                 unmap_mapping_range(dev->dev_mapping, offset, obj->size, 1);
1286
1287         if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
1288                 i915_gem_clear_fence_reg(obj);
1289
1290         i915_gem_object_free_page_list(obj);
1291
1292         if (obj_priv->gtt_space) {
1293                 atomic_dec(&dev->gtt_count);
1294                 atomic_sub(obj->size, &dev->gtt_memory);
1295
1296                 drm_mm_put_block(obj_priv->gtt_space);
1297                 obj_priv->gtt_space = NULL;
1298         }
1299
1300         /* Remove ourselves from the LRU list if present. */
1301         if (!list_empty(&obj_priv->list))
1302                 list_del_init(&obj_priv->list);
1303
1304         return 0;
1305 }
1306
1307 static int
1308 i915_gem_evict_something(struct drm_device *dev)
1309 {
1310         drm_i915_private_t *dev_priv = dev->dev_private;
1311         struct drm_gem_object *obj;
1312         struct drm_i915_gem_object *obj_priv;
1313         int ret = 0;
1314
1315         for (;;) {
1316                 /* If there's an inactive buffer available now, grab it
1317                  * and be done.
1318                  */
1319                 if (!list_empty(&dev_priv->mm.inactive_list)) {
1320                         obj_priv = list_first_entry(&dev_priv->mm.inactive_list,
1321                                                     struct drm_i915_gem_object,
1322                                                     list);
1323                         obj = obj_priv->obj;
1324                         BUG_ON(obj_priv->pin_count != 0);
1325 #if WATCH_LRU
1326                         DRM_INFO("%s: evicting %p\n", __func__, obj);
1327 #endif
1328                         BUG_ON(obj_priv->active);
1329
1330                         /* Wait on the rendering and unbind the buffer. */
1331                         ret = i915_gem_object_unbind(obj);
1332                         break;
1333                 }
1334
1335                 /* If we didn't get anything, but the ring is still processing
1336                  * things, wait for one of those things to finish and hopefully
1337                  * leave us a buffer to evict.
1338                  */
1339                 if (!list_empty(&dev_priv->mm.request_list)) {
1340                         struct drm_i915_gem_request *request;
1341
1342                         request = list_first_entry(&dev_priv->mm.request_list,
1343                                                    struct drm_i915_gem_request,
1344                                                    list);
1345
1346                         ret = i915_wait_request(dev, request->seqno);
1347                         if (ret)
1348                                 break;
1349
1350                         /* if waiting caused an object to become inactive,
1351                          * then loop around and wait for it. Otherwise, we
1352                          * assume that waiting freed and unbound something,
1353                          * so there should now be some space in the GTT
1354                          */
1355                         if (!list_empty(&dev_priv->mm.inactive_list))
1356                                 continue;
1357                         break;
1358                 }
1359
1360                 /* If we didn't have anything on the request list but there
1361                  * are buffers awaiting a flush, emit one and try again.
1362                  * When we wait on it, those buffers waiting for that flush
1363                  * will get moved to inactive.
1364                  */
1365                 if (!list_empty(&dev_priv->mm.flushing_list)) {
1366                         obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
1367                                                     struct drm_i915_gem_object,
1368                                                     list);
1369                         obj = obj_priv->obj;
1370
1371                         i915_gem_flush(dev,
1372                                        obj->write_domain,
1373                                        obj->write_domain);
1374                         i915_add_request(dev, obj->write_domain);
1375
1376                         obj = NULL;
1377                         continue;
1378                 }
1379
1380                 DRM_ERROR("inactive empty %d request empty %d "
1381                           "flushing empty %d\n",
1382                           list_empty(&dev_priv->mm.inactive_list),
1383                           list_empty(&dev_priv->mm.request_list),
1384                           list_empty(&dev_priv->mm.flushing_list));
1385                 /* If we didn't do any of the above, there's nothing to be done
1386                  * and we just can't fit it in.
1387                  */
1388                 return -ENOMEM;
1389         }
1390         return ret;
1391 }
1392
1393 static int
1394 i915_gem_evict_everything(struct drm_device *dev)
1395 {
1396         int ret;
1397
1398         for (;;) {
1399                 ret = i915_gem_evict_something(dev);
1400                 if (ret != 0)
1401                         break;
1402         }
1403         if (ret == -ENOMEM)
1404                 return 0;
1405         return ret;
1406 }
1407
1408 static int
1409 i915_gem_object_get_page_list(struct drm_gem_object *obj)
1410 {
1411         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1412         int page_count, i;
1413         struct address_space *mapping;
1414         struct inode *inode;
1415         struct page *page;
1416         int ret;
1417
1418         if (obj_priv->page_list)
1419                 return 0;
1420
1421         /* Get the list of pages out of our struct file.  They'll be pinned
1422          * at this point until we release them.
1423          */
1424         page_count = obj->size / PAGE_SIZE;
1425         BUG_ON(obj_priv->page_list != NULL);
1426         obj_priv->page_list = drm_calloc(page_count, sizeof(struct page *),
1427                                          DRM_MEM_DRIVER);
1428         if (obj_priv->page_list == NULL) {
1429                 DRM_ERROR("Faled to allocate page list\n");
1430                 return -ENOMEM;
1431         }
1432
1433         inode = obj->filp->f_path.dentry->d_inode;
1434         mapping = inode->i_mapping;
1435         for (i = 0; i < page_count; i++) {
1436                 page = read_mapping_page(mapping, i, NULL);
1437                 if (IS_ERR(page)) {
1438                         ret = PTR_ERR(page);
1439                         DRM_ERROR("read_mapping_page failed: %d\n", ret);
1440                         i915_gem_object_free_page_list(obj);
1441                         return ret;
1442                 }
1443                 obj_priv->page_list[i] = page;
1444         }
1445         return 0;
1446 }
1447
1448 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
1449 {
1450         struct drm_gem_object *obj = reg->obj;
1451         struct drm_device *dev = obj->dev;
1452         drm_i915_private_t *dev_priv = dev->dev_private;
1453         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1454         int regnum = obj_priv->fence_reg;
1455         uint64_t val;
1456
1457         val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
1458                     0xfffff000) << 32;
1459         val |= obj_priv->gtt_offset & 0xfffff000;
1460         val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
1461         if (obj_priv->tiling_mode == I915_TILING_Y)
1462                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
1463         val |= I965_FENCE_REG_VALID;
1464
1465         I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
1466 }
1467
1468 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
1469 {
1470         struct drm_gem_object *obj = reg->obj;
1471         struct drm_device *dev = obj->dev;
1472         drm_i915_private_t *dev_priv = dev->dev_private;
1473         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1474         int regnum = obj_priv->fence_reg;
1475         int tile_width;
1476         uint32_t val;
1477         uint32_t pitch_val;
1478
1479         if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
1480             (obj_priv->gtt_offset & (obj->size - 1))) {
1481                 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
1482                      __func__, obj_priv->gtt_offset, obj->size);
1483                 return;
1484         }
1485
1486         if (obj_priv->tiling_mode == I915_TILING_Y &&
1487             HAS_128_BYTE_Y_TILING(dev))
1488                 tile_width = 128;
1489         else
1490                 tile_width = 512;
1491
1492         /* Note: pitch better be a power of two tile widths */
1493         pitch_val = obj_priv->stride / tile_width;
1494         pitch_val = ffs(pitch_val) - 1;
1495
1496         val = obj_priv->gtt_offset;
1497         if (obj_priv->tiling_mode == I915_TILING_Y)
1498                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
1499         val |= I915_FENCE_SIZE_BITS(obj->size);
1500         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
1501         val |= I830_FENCE_REG_VALID;
1502
1503         I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
1504 }
1505
1506 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
1507 {
1508         struct drm_gem_object *obj = reg->obj;
1509         struct drm_device *dev = obj->dev;
1510         drm_i915_private_t *dev_priv = dev->dev_private;
1511         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1512         int regnum = obj_priv->fence_reg;
1513         uint32_t val;
1514         uint32_t pitch_val;
1515
1516         if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
1517             (obj_priv->gtt_offset & (obj->size - 1))) {
1518                 WARN(1, "%s: object 0x%08x not 1M or size aligned\n",
1519                      __func__, obj_priv->gtt_offset);
1520                 return;
1521         }
1522
1523         pitch_val = (obj_priv->stride / 128) - 1;
1524
1525         val = obj_priv->gtt_offset;
1526         if (obj_priv->tiling_mode == I915_TILING_Y)
1527                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
1528         val |= I830_FENCE_SIZE_BITS(obj->size);
1529         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
1530         val |= I830_FENCE_REG_VALID;
1531
1532         I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
1533
1534 }
1535
1536 /**
1537  * i915_gem_object_get_fence_reg - set up a fence reg for an object
1538  * @obj: object to map through a fence reg
1539  * @write: object is about to be written
1540  *
1541  * When mapping objects through the GTT, userspace wants to be able to write
1542  * to them without having to worry about swizzling if the object is tiled.
1543  *
1544  * This function walks the fence regs looking for a free one for @obj,
1545  * stealing one if it can't find any.
1546  *
1547  * It then sets up the reg based on the object's properties: address, pitch
1548  * and tiling format.
1549  */
1550 static int
1551 i915_gem_object_get_fence_reg(struct drm_gem_object *obj, bool write)
1552 {
1553         struct drm_device *dev = obj->dev;
1554         struct drm_i915_private *dev_priv = dev->dev_private;
1555         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1556         struct drm_i915_fence_reg *reg = NULL;
1557         int i, ret;
1558
1559         switch (obj_priv->tiling_mode) {
1560         case I915_TILING_NONE:
1561                 WARN(1, "allocating a fence for non-tiled object?\n");
1562                 break;
1563         case I915_TILING_X:
1564                 if (!obj_priv->stride)
1565                         return -EINVAL;
1566                 WARN((obj_priv->stride & (512 - 1)),
1567                      "object 0x%08x is X tiled but has non-512B pitch\n",
1568                      obj_priv->gtt_offset);
1569                 break;
1570         case I915_TILING_Y:
1571                 if (!obj_priv->stride)
1572                         return -EINVAL;
1573                 WARN((obj_priv->stride & (128 - 1)),
1574                      "object 0x%08x is Y tiled but has non-128B pitch\n",
1575                      obj_priv->gtt_offset);
1576                 break;
1577         }
1578
1579         /* First try to find a free reg */
1580         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
1581                 reg = &dev_priv->fence_regs[i];
1582                 if (!reg->obj)
1583                         break;
1584         }
1585
1586         /* None available, try to steal one or wait for a user to finish */
1587         if (i == dev_priv->num_fence_regs) {
1588                 struct drm_i915_gem_object *old_obj_priv = NULL;
1589                 loff_t offset;
1590
1591 try_again:
1592                 /* Could try to use LRU here instead... */
1593                 for (i = dev_priv->fence_reg_start;
1594                      i < dev_priv->num_fence_regs; i++) {
1595                         reg = &dev_priv->fence_regs[i];
1596                         old_obj_priv = reg->obj->driver_private;
1597                         if (!old_obj_priv->pin_count)
1598                                 break;
1599                 }
1600
1601                 /*
1602                  * Now things get ugly... we have to wait for one of the
1603                  * objects to finish before trying again.
1604                  */
1605                 if (i == dev_priv->num_fence_regs) {
1606                         ret = i915_gem_object_set_to_gtt_domain(reg->obj, 0);
1607                         if (ret) {
1608                                 WARN(ret != -ERESTARTSYS,
1609                                      "switch to GTT domain failed: %d\n", ret);
1610                                 return ret;
1611                         }
1612                         goto try_again;
1613                 }
1614
1615                 /*
1616                  * Zap this virtual mapping so we can set up a fence again
1617                  * for this object next time we need it.
1618                  */
1619                 offset = ((loff_t) reg->obj->map_list.hash.key) << PAGE_SHIFT;
1620                 if (dev->dev_mapping)
1621                         unmap_mapping_range(dev->dev_mapping, offset,
1622                                             reg->obj->size, 1);
1623                 old_obj_priv->fence_reg = I915_FENCE_REG_NONE;
1624         }
1625
1626         obj_priv->fence_reg = i;
1627         reg->obj = obj;
1628
1629         if (IS_I965G(dev))
1630                 i965_write_fence_reg(reg);
1631         else if (IS_I9XX(dev))
1632                 i915_write_fence_reg(reg);
1633         else
1634                 i830_write_fence_reg(reg);
1635
1636         return 0;
1637 }
1638
1639 /**
1640  * i915_gem_clear_fence_reg - clear out fence register info
1641  * @obj: object to clear
1642  *
1643  * Zeroes out the fence register itself and clears out the associated
1644  * data structures in dev_priv and obj_priv.
1645  */
1646 static void
1647 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
1648 {
1649         struct drm_device *dev = obj->dev;
1650         drm_i915_private_t *dev_priv = dev->dev_private;
1651         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1652
1653         if (IS_I965G(dev))
1654                 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
1655         else
1656                 I915_WRITE(FENCE_REG_830_0 + (obj_priv->fence_reg * 4), 0);
1657
1658         dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL;
1659         obj_priv->fence_reg = I915_FENCE_REG_NONE;
1660 }
1661
1662 /**
1663  * Finds free space in the GTT aperture and binds the object there.
1664  */
1665 static int
1666 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
1667 {
1668         struct drm_device *dev = obj->dev;
1669         drm_i915_private_t *dev_priv = dev->dev_private;
1670         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1671         struct drm_mm_node *free_space;
1672         int page_count, ret;
1673
1674         if (dev_priv->mm.suspended)
1675                 return -EBUSY;
1676         if (alignment == 0)
1677                 alignment = i915_gem_get_gtt_alignment(obj);
1678         if (alignment & (PAGE_SIZE - 1)) {
1679                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
1680                 return -EINVAL;
1681         }
1682
1683  search_free:
1684         free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
1685                                         obj->size, alignment, 0);
1686         if (free_space != NULL) {
1687                 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
1688                                                        alignment);
1689                 if (obj_priv->gtt_space != NULL) {
1690                         obj_priv->gtt_space->private = obj;
1691                         obj_priv->gtt_offset = obj_priv->gtt_space->start;
1692                 }
1693         }
1694         if (obj_priv->gtt_space == NULL) {
1695                 /* If the gtt is empty and we're still having trouble
1696                  * fitting our object in, we're out of memory.
1697                  */
1698 #if WATCH_LRU
1699                 DRM_INFO("%s: GTT full, evicting something\n", __func__);
1700 #endif
1701                 if (list_empty(&dev_priv->mm.inactive_list) &&
1702                     list_empty(&dev_priv->mm.flushing_list) &&
1703                     list_empty(&dev_priv->mm.active_list)) {
1704                         DRM_ERROR("GTT full, but LRU list empty\n");
1705                         return -ENOMEM;
1706                 }
1707
1708                 ret = i915_gem_evict_something(dev);
1709                 if (ret != 0) {
1710                         if (ret != -ERESTARTSYS)
1711                                 DRM_ERROR("Failed to evict a buffer %d\n", ret);
1712                         return ret;
1713                 }
1714                 goto search_free;
1715         }
1716
1717 #if WATCH_BUF
1718         DRM_INFO("Binding object of size %d at 0x%08x\n",
1719                  obj->size, obj_priv->gtt_offset);
1720 #endif
1721         ret = i915_gem_object_get_page_list(obj);
1722         if (ret) {
1723                 drm_mm_put_block(obj_priv->gtt_space);
1724                 obj_priv->gtt_space = NULL;
1725                 return ret;
1726         }
1727
1728         page_count = obj->size / PAGE_SIZE;
1729         /* Create an AGP memory structure pointing at our pages, and bind it
1730          * into the GTT.
1731          */
1732         obj_priv->agp_mem = drm_agp_bind_pages(dev,
1733                                                obj_priv->page_list,
1734                                                page_count,
1735                                                obj_priv->gtt_offset,
1736                                                obj_priv->agp_type);
1737         if (obj_priv->agp_mem == NULL) {
1738                 i915_gem_object_free_page_list(obj);
1739                 drm_mm_put_block(obj_priv->gtt_space);
1740                 obj_priv->gtt_space = NULL;
1741                 return -ENOMEM;
1742         }
1743         atomic_inc(&dev->gtt_count);
1744         atomic_add(obj->size, &dev->gtt_memory);
1745
1746         /* Assert that the object is not currently in any GPU domain. As it
1747          * wasn't in the GTT, there shouldn't be any way it could have been in
1748          * a GPU cache
1749          */
1750         BUG_ON(obj->read_domains & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
1751         BUG_ON(obj->write_domain & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
1752
1753         return 0;
1754 }
1755
1756 void
1757 i915_gem_clflush_object(struct drm_gem_object *obj)
1758 {
1759         struct drm_i915_gem_object      *obj_priv = obj->driver_private;
1760
1761         /* If we don't have a page list set up, then we're not pinned
1762          * to GPU, and we can ignore the cache flush because it'll happen
1763          * again at bind time.
1764          */
1765         if (obj_priv->page_list == NULL)
1766                 return;
1767
1768         drm_clflush_pages(obj_priv->page_list, obj->size / PAGE_SIZE);
1769 }
1770
1771 /** Flushes any GPU write domain for the object if it's dirty. */
1772 static void
1773 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
1774 {
1775         struct drm_device *dev = obj->dev;
1776         uint32_t seqno;
1777
1778         if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
1779                 return;
1780
1781         /* Queue the GPU write cache flushing we need. */
1782         i915_gem_flush(dev, 0, obj->write_domain);
1783         seqno = i915_add_request(dev, obj->write_domain);
1784         obj->write_domain = 0;
1785         i915_gem_object_move_to_active(obj, seqno);
1786 }
1787
1788 /** Flushes the GTT write domain for the object if it's dirty. */
1789 static void
1790 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
1791 {
1792         if (obj->write_domain != I915_GEM_DOMAIN_GTT)
1793                 return;
1794
1795         /* No actual flushing is required for the GTT write domain.   Writes
1796          * to it immediately go to main memory as far as we know, so there's
1797          * no chipset flush.  It also doesn't land in render cache.
1798          */
1799         obj->write_domain = 0;
1800 }
1801
1802 /** Flushes the CPU write domain for the object if it's dirty. */
1803 static void
1804 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
1805 {
1806         struct drm_device *dev = obj->dev;
1807
1808         if (obj->write_domain != I915_GEM_DOMAIN_CPU)
1809                 return;
1810
1811         i915_gem_clflush_object(obj);
1812         drm_agp_chipset_flush(dev);
1813         obj->write_domain = 0;
1814 }
1815
1816 /**
1817  * Moves a single object to the GTT read, and possibly write domain.
1818  *
1819  * This function returns when the move is complete, including waiting on
1820  * flushes to occur.
1821  */
1822 int
1823 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
1824 {
1825         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1826         int ret;
1827
1828         /* Not valid to be called on unbound objects. */
1829         if (obj_priv->gtt_space == NULL)
1830                 return -EINVAL;
1831
1832         i915_gem_object_flush_gpu_write_domain(obj);
1833         /* Wait on any GPU rendering and flushing to occur. */
1834         ret = i915_gem_object_wait_rendering(obj);
1835         if (ret != 0)
1836                 return ret;
1837
1838         /* If we're writing through the GTT domain, then CPU and GPU caches
1839          * will need to be invalidated at next use.
1840          */
1841         if (write)
1842                 obj->read_domains &= I915_GEM_DOMAIN_GTT;
1843
1844         i915_gem_object_flush_cpu_write_domain(obj);
1845
1846         /* It should now be out of any other write domains, and we can update
1847          * the domain values for our changes.
1848          */
1849         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
1850         obj->read_domains |= I915_GEM_DOMAIN_GTT;
1851         if (write) {
1852                 obj->write_domain = I915_GEM_DOMAIN_GTT;
1853                 obj_priv->dirty = 1;
1854         }
1855
1856         return 0;
1857 }
1858
1859 /**
1860  * Moves a single object to the CPU read, and possibly write domain.
1861  *
1862  * This function returns when the move is complete, including waiting on
1863  * flushes to occur.
1864  */
1865 static int
1866 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
1867 {
1868         struct drm_device *dev = obj->dev;
1869         int ret;
1870
1871         i915_gem_object_flush_gpu_write_domain(obj);
1872         /* Wait on any GPU rendering and flushing to occur. */
1873         ret = i915_gem_object_wait_rendering(obj);
1874         if (ret != 0)
1875                 return ret;
1876
1877         i915_gem_object_flush_gtt_write_domain(obj);
1878
1879         /* If we have a partially-valid cache of the object in the CPU,
1880          * finish invalidating it and free the per-page flags.
1881          */
1882         i915_gem_object_set_to_full_cpu_read_domain(obj);
1883
1884         /* Flush the CPU cache if it's still invalid. */
1885         if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
1886                 i915_gem_clflush_object(obj);
1887                 drm_agp_chipset_flush(dev);
1888
1889                 obj->read_domains |= I915_GEM_DOMAIN_CPU;
1890         }
1891
1892         /* It should now be out of any other write domains, and we can update
1893          * the domain values for our changes.
1894          */
1895         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
1896
1897         /* If we're writing through the CPU, then the GPU read domains will
1898          * need to be invalidated at next use.
1899          */
1900         if (write) {
1901                 obj->read_domains &= I915_GEM_DOMAIN_CPU;
1902                 obj->write_domain = I915_GEM_DOMAIN_CPU;
1903         }
1904
1905         return 0;
1906 }
1907
1908 /*
1909  * Set the next domain for the specified object. This
1910  * may not actually perform the necessary flushing/invaliding though,
1911  * as that may want to be batched with other set_domain operations
1912  *
1913  * This is (we hope) the only really tricky part of gem. The goal
1914  * is fairly simple -- track which caches hold bits of the object
1915  * and make sure they remain coherent. A few concrete examples may
1916  * help to explain how it works. For shorthand, we use the notation
1917  * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
1918  * a pair of read and write domain masks.
1919  *
1920  * Case 1: the batch buffer
1921  *
1922  *      1. Allocated
1923  *      2. Written by CPU
1924  *      3. Mapped to GTT
1925  *      4. Read by GPU
1926  *      5. Unmapped from GTT
1927  *      6. Freed
1928  *
1929  *      Let's take these a step at a time
1930  *
1931  *      1. Allocated
1932  *              Pages allocated from the kernel may still have
1933  *              cache contents, so we set them to (CPU, CPU) always.
1934  *      2. Written by CPU (using pwrite)
1935  *              The pwrite function calls set_domain (CPU, CPU) and
1936  *              this function does nothing (as nothing changes)
1937  *      3. Mapped by GTT
1938  *              This function asserts that the object is not
1939  *              currently in any GPU-based read or write domains
1940  *      4. Read by GPU
1941  *              i915_gem_execbuffer calls set_domain (COMMAND, 0).
1942  *              As write_domain is zero, this function adds in the
1943  *              current read domains (CPU+COMMAND, 0).
1944  *              flush_domains is set to CPU.
1945  *              invalidate_domains is set to COMMAND
1946  *              clflush is run to get data out of the CPU caches
1947  *              then i915_dev_set_domain calls i915_gem_flush to
1948  *              emit an MI_FLUSH and drm_agp_chipset_flush
1949  *      5. Unmapped from GTT
1950  *              i915_gem_object_unbind calls set_domain (CPU, CPU)
1951  *              flush_domains and invalidate_domains end up both zero
1952  *              so no flushing/invalidating happens
1953  *      6. Freed
1954  *              yay, done
1955  *
1956  * Case 2: The shared render buffer
1957  *
1958  *      1. Allocated
1959  *      2. Mapped to GTT
1960  *      3. Read/written by GPU
1961  *      4. set_domain to (CPU,CPU)
1962  *      5. Read/written by CPU
1963  *      6. Read/written by GPU
1964  *
1965  *      1. Allocated
1966  *              Same as last example, (CPU, CPU)
1967  *      2. Mapped to GTT
1968  *              Nothing changes (assertions find that it is not in the GPU)
1969  *      3. Read/written by GPU
1970  *              execbuffer calls set_domain (RENDER, RENDER)
1971  *              flush_domains gets CPU
1972  *              invalidate_domains gets GPU
1973  *              clflush (obj)
1974  *              MI_FLUSH and drm_agp_chipset_flush
1975  *      4. set_domain (CPU, CPU)
1976  *              flush_domains gets GPU
1977  *              invalidate_domains gets CPU
1978  *              wait_rendering (obj) to make sure all drawing is complete.
1979  *              This will include an MI_FLUSH to get the data from GPU
1980  *              to memory
1981  *              clflush (obj) to invalidate the CPU cache
1982  *              Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
1983  *      5. Read/written by CPU
1984  *              cache lines are loaded and dirtied
1985  *      6. Read written by GPU
1986  *              Same as last GPU access
1987  *
1988  * Case 3: The constant buffer
1989  *
1990  *      1. Allocated
1991  *      2. Written by CPU
1992  *      3. Read by GPU
1993  *      4. Updated (written) by CPU again
1994  *      5. Read by GPU
1995  *
1996  *      1. Allocated
1997  *              (CPU, CPU)
1998  *      2. Written by CPU
1999  *              (CPU, CPU)
2000  *      3. Read by GPU
2001  *              (CPU+RENDER, 0)
2002  *              flush_domains = CPU
2003  *              invalidate_domains = RENDER
2004  *              clflush (obj)
2005  *              MI_FLUSH
2006  *              drm_agp_chipset_flush
2007  *      4. Updated (written) by CPU again
2008  *              (CPU, CPU)
2009  *              flush_domains = 0 (no previous write domain)
2010  *              invalidate_domains = 0 (no new read domains)
2011  *      5. Read by GPU
2012  *              (CPU+RENDER, 0)
2013  *              flush_domains = CPU
2014  *              invalidate_domains = RENDER
2015  *              clflush (obj)
2016  *              MI_FLUSH
2017  *              drm_agp_chipset_flush
2018  */
2019 static void
2020 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
2021 {
2022         struct drm_device               *dev = obj->dev;
2023         struct drm_i915_gem_object      *obj_priv = obj->driver_private;
2024         uint32_t                        invalidate_domains = 0;
2025         uint32_t                        flush_domains = 0;
2026
2027         BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
2028         BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
2029
2030 #if WATCH_BUF
2031         DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2032                  __func__, obj,
2033                  obj->read_domains, obj->pending_read_domains,
2034                  obj->write_domain, obj->pending_write_domain);
2035 #endif
2036         /*
2037          * If the object isn't moving to a new write domain,
2038          * let the object stay in multiple read domains
2039          */
2040         if (obj->pending_write_domain == 0)
2041                 obj->pending_read_domains |= obj->read_domains;
2042         else
2043                 obj_priv->dirty = 1;
2044
2045         /*
2046          * Flush the current write domain if
2047          * the new read domains don't match. Invalidate
2048          * any read domains which differ from the old
2049          * write domain
2050          */
2051         if (obj->write_domain &&
2052             obj->write_domain != obj->pending_read_domains) {
2053                 flush_domains |= obj->write_domain;
2054                 invalidate_domains |=
2055                         obj->pending_read_domains & ~obj->write_domain;
2056         }
2057         /*
2058          * Invalidate any read caches which may have
2059          * stale data. That is, any new read domains.
2060          */
2061         invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
2062         if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
2063 #if WATCH_BUF
2064                 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
2065                          __func__, flush_domains, invalidate_domains);
2066 #endif
2067                 i915_gem_clflush_object(obj);
2068         }
2069
2070         if ((obj->pending_write_domain | flush_domains) != 0)
2071                 obj->write_domain = obj->pending_write_domain;
2072         obj->read_domains = obj->pending_read_domains;
2073
2074         dev->invalidate_domains |= invalidate_domains;
2075         dev->flush_domains |= flush_domains;
2076 #if WATCH_BUF
2077         DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
2078                  __func__,
2079                  obj->read_domains, obj->write_domain,
2080                  dev->invalidate_domains, dev->flush_domains);
2081 #endif
2082 }
2083
2084 /**
2085  * Moves the object from a partially CPU read to a full one.
2086  *
2087  * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
2088  * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
2089  */
2090 static void
2091 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
2092 {
2093         struct drm_device *dev = obj->dev;
2094         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2095
2096         if (!obj_priv->page_cpu_valid)
2097                 return;
2098
2099         /* If we're partially in the CPU read domain, finish moving it in.
2100          */
2101         if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
2102                 int i;
2103
2104                 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
2105                         if (obj_priv->page_cpu_valid[i])
2106                                 continue;
2107                         drm_clflush_pages(obj_priv->page_list + i, 1);
2108                 }
2109                 drm_agp_chipset_flush(dev);
2110         }
2111
2112         /* Free the page_cpu_valid mappings which are now stale, whether
2113          * or not we've got I915_GEM_DOMAIN_CPU.
2114          */
2115         drm_free(obj_priv->page_cpu_valid, obj->size / PAGE_SIZE,
2116                  DRM_MEM_DRIVER);
2117         obj_priv->page_cpu_valid = NULL;
2118 }
2119
2120 /**
2121  * Set the CPU read domain on a range of the object.
2122  *
2123  * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
2124  * not entirely valid.  The page_cpu_valid member of the object flags which
2125  * pages have been flushed, and will be respected by
2126  * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
2127  * of the whole object.
2128  *
2129  * This function returns when the move is complete, including waiting on
2130  * flushes to occur.
2131  */
2132 static int
2133 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
2134                                           uint64_t offset, uint64_t size)
2135 {
2136         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2137         int i, ret;
2138
2139         if (offset == 0 && size == obj->size)
2140                 return i915_gem_object_set_to_cpu_domain(obj, 0);
2141
2142         i915_gem_object_flush_gpu_write_domain(obj);
2143         /* Wait on any GPU rendering and flushing to occur. */
2144         ret = i915_gem_object_wait_rendering(obj);
2145         if (ret != 0)
2146                 return ret;
2147         i915_gem_object_flush_gtt_write_domain(obj);
2148
2149         /* If we're already fully in the CPU read domain, we're done. */
2150         if (obj_priv->page_cpu_valid == NULL &&
2151             (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
2152                 return 0;
2153
2154         /* Otherwise, create/clear the per-page CPU read domain flag if we're
2155          * newly adding I915_GEM_DOMAIN_CPU
2156          */
2157         if (obj_priv->page_cpu_valid == NULL) {
2158                 obj_priv->page_cpu_valid = drm_calloc(1, obj->size / PAGE_SIZE,
2159                                                       DRM_MEM_DRIVER);
2160                 if (obj_priv->page_cpu_valid == NULL)
2161                         return -ENOMEM;
2162         } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
2163                 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
2164
2165         /* Flush the cache on any pages that are still invalid from the CPU's
2166          * perspective.
2167          */
2168         for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
2169              i++) {
2170                 if (obj_priv->page_cpu_valid[i])
2171                         continue;
2172
2173                 drm_clflush_pages(obj_priv->page_list + i, 1);
2174
2175                 obj_priv->page_cpu_valid[i] = 1;
2176         }
2177
2178         /* It should now be out of any other write domains, and we can update
2179          * the domain values for our changes.
2180          */
2181         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2182
2183         obj->read_domains |= I915_GEM_DOMAIN_CPU;
2184
2185         return 0;
2186 }
2187
2188 /**
2189  * Pin an object to the GTT and evaluate the relocations landing in it.
2190  */
2191 static int
2192 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
2193                                  struct drm_file *file_priv,
2194                                  struct drm_i915_gem_exec_object *entry)
2195 {
2196         struct drm_device *dev = obj->dev;
2197         drm_i915_private_t *dev_priv = dev->dev_private;
2198         struct drm_i915_gem_relocation_entry reloc;
2199         struct drm_i915_gem_relocation_entry __user *relocs;
2200         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2201         int i, ret;
2202         void __iomem *reloc_page;
2203
2204         /* Choose the GTT offset for our buffer and put it there. */
2205         ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
2206         if (ret)
2207                 return ret;
2208
2209         entry->offset = obj_priv->gtt_offset;
2210
2211         relocs = (struct drm_i915_gem_relocation_entry __user *)
2212                  (uintptr_t) entry->relocs_ptr;
2213         /* Apply the relocations, using the GTT aperture to avoid cache
2214          * flushing requirements.
2215          */
2216         for (i = 0; i < entry->relocation_count; i++) {
2217                 struct drm_gem_object *target_obj;
2218                 struct drm_i915_gem_object *target_obj_priv;
2219                 uint32_t reloc_val, reloc_offset;
2220                 uint32_t __iomem *reloc_entry;
2221
2222                 ret = copy_from_user(&reloc, relocs + i, sizeof(reloc));
2223                 if (ret != 0) {
2224                         i915_gem_object_unpin(obj);
2225                         return ret;
2226                 }
2227
2228                 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
2229                                                    reloc.target_handle);
2230                 if (target_obj == NULL) {
2231                         i915_gem_object_unpin(obj);
2232                         return -EBADF;
2233                 }
2234                 target_obj_priv = target_obj->driver_private;
2235
2236                 /* The target buffer should have appeared before us in the
2237                  * exec_object list, so it should have a GTT space bound by now.
2238                  */
2239                 if (target_obj_priv->gtt_space == NULL) {
2240                         DRM_ERROR("No GTT space found for object %d\n",
2241                                   reloc.target_handle);
2242                         drm_gem_object_unreference(target_obj);
2243                         i915_gem_object_unpin(obj);
2244                         return -EINVAL;
2245                 }
2246
2247                 if (reloc.offset > obj->size - 4) {
2248                         DRM_ERROR("Relocation beyond object bounds: "
2249                                   "obj %p target %d offset %d size %d.\n",
2250                                   obj, reloc.target_handle,
2251                                   (int) reloc.offset, (int) obj->size);
2252                         drm_gem_object_unreference(target_obj);
2253                         i915_gem_object_unpin(obj);
2254                         return -EINVAL;
2255                 }
2256                 if (reloc.offset & 3) {
2257                         DRM_ERROR("Relocation not 4-byte aligned: "
2258                                   "obj %p target %d offset %d.\n",
2259                                   obj, reloc.target_handle,
2260                                   (int) reloc.offset);
2261                         drm_gem_object_unreference(target_obj);
2262                         i915_gem_object_unpin(obj);
2263                         return -EINVAL;
2264                 }
2265
2266                 if (reloc.write_domain & I915_GEM_DOMAIN_CPU ||
2267                     reloc.read_domains & I915_GEM_DOMAIN_CPU) {
2268                         DRM_ERROR("reloc with read/write CPU domains: "
2269                                   "obj %p target %d offset %d "
2270                                   "read %08x write %08x",
2271                                   obj, reloc.target_handle,
2272                                   (int) reloc.offset,
2273                                   reloc.read_domains,
2274                                   reloc.write_domain);
2275                         drm_gem_object_unreference(target_obj);
2276                         i915_gem_object_unpin(obj);
2277                         return -EINVAL;
2278                 }
2279
2280                 if (reloc.write_domain && target_obj->pending_write_domain &&
2281                     reloc.write_domain != target_obj->pending_write_domain) {
2282                         DRM_ERROR("Write domain conflict: "
2283                                   "obj %p target %d offset %d "
2284                                   "new %08x old %08x\n",
2285                                   obj, reloc.target_handle,
2286                                   (int) reloc.offset,
2287                                   reloc.write_domain,
2288                                   target_obj->pending_write_domain);
2289                         drm_gem_object_unreference(target_obj);
2290                         i915_gem_object_unpin(obj);
2291                         return -EINVAL;
2292                 }
2293
2294 #if WATCH_RELOC
2295                 DRM_INFO("%s: obj %p offset %08x target %d "
2296                          "read %08x write %08x gtt %08x "
2297                          "presumed %08x delta %08x\n",
2298                          __func__,
2299                          obj,
2300                          (int) reloc.offset,
2301                          (int) reloc.target_handle,
2302                          (int) reloc.read_domains,
2303                          (int) reloc.write_domain,
2304                          (int) target_obj_priv->gtt_offset,
2305                          (int) reloc.presumed_offset,
2306                          reloc.delta);
2307 #endif
2308
2309                 target_obj->pending_read_domains |= reloc.read_domains;
2310                 target_obj->pending_write_domain |= reloc.write_domain;
2311
2312                 /* If the relocation already has the right value in it, no
2313                  * more work needs to be done.
2314                  */
2315                 if (target_obj_priv->gtt_offset == reloc.presumed_offset) {
2316                         drm_gem_object_unreference(target_obj);
2317                         continue;
2318                 }
2319
2320                 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
2321                 if (ret != 0) {
2322                         drm_gem_object_unreference(target_obj);
2323                         i915_gem_object_unpin(obj);
2324                         return -EINVAL;
2325                 }
2326
2327                 /* Map the page containing the relocation we're going to
2328                  * perform.
2329                  */
2330                 reloc_offset = obj_priv->gtt_offset + reloc.offset;
2331                 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
2332                                                       (reloc_offset &
2333                                                        ~(PAGE_SIZE - 1)));
2334                 reloc_entry = (uint32_t __iomem *)(reloc_page +
2335                                                    (reloc_offset & (PAGE_SIZE - 1)));
2336                 reloc_val = target_obj_priv->gtt_offset + reloc.delta;
2337
2338 #if WATCH_BUF
2339                 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
2340                           obj, (unsigned int) reloc.offset,
2341                           readl(reloc_entry), reloc_val);
2342 #endif
2343                 writel(reloc_val, reloc_entry);
2344                 io_mapping_unmap_atomic(reloc_page);
2345
2346                 /* Write the updated presumed offset for this entry back out
2347                  * to the user.
2348                  */
2349                 reloc.presumed_offset = target_obj_priv->gtt_offset;
2350                 ret = copy_to_user(relocs + i, &reloc, sizeof(reloc));
2351                 if (ret != 0) {
2352                         drm_gem_object_unreference(target_obj);
2353                         i915_gem_object_unpin(obj);
2354                         return ret;
2355                 }
2356
2357                 drm_gem_object_unreference(target_obj);
2358         }
2359
2360 #if WATCH_BUF
2361         if (0)
2362                 i915_gem_dump_object(obj, 128, __func__, ~0);
2363 #endif
2364         return 0;
2365 }
2366
2367 /** Dispatch a batchbuffer to the ring
2368  */
2369 static int
2370 i915_dispatch_gem_execbuffer(struct drm_device *dev,
2371                               struct drm_i915_gem_execbuffer *exec,
2372                               uint64_t exec_offset)
2373 {
2374         drm_i915_private_t *dev_priv = dev->dev_private;
2375         struct drm_clip_rect __user *boxes = (struct drm_clip_rect __user *)
2376                                              (uintptr_t) exec->cliprects_ptr;
2377         int nbox = exec->num_cliprects;
2378         int i = 0, count;
2379         uint32_t        exec_start, exec_len;
2380         RING_LOCALS;
2381
2382         exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
2383         exec_len = (uint32_t) exec->batch_len;
2384
2385         if ((exec_start | exec_len) & 0x7) {
2386                 DRM_ERROR("alignment\n");
2387                 return -EINVAL;
2388         }
2389
2390         if (!exec_start)
2391                 return -EINVAL;
2392
2393         count = nbox ? nbox : 1;
2394
2395         for (i = 0; i < count; i++) {
2396                 if (i < nbox) {
2397                         int ret = i915_emit_box(dev, boxes, i,
2398                                                 exec->DR1, exec->DR4);
2399                         if (ret)
2400                                 return ret;
2401                 }
2402
2403                 if (IS_I830(dev) || IS_845G(dev)) {
2404                         BEGIN_LP_RING(4);
2405                         OUT_RING(MI_BATCH_BUFFER);
2406                         OUT_RING(exec_start | MI_BATCH_NON_SECURE);
2407                         OUT_RING(exec_start + exec_len - 4);
2408                         OUT_RING(0);
2409                         ADVANCE_LP_RING();
2410                 } else {
2411                         BEGIN_LP_RING(2);
2412                         if (IS_I965G(dev)) {
2413                                 OUT_RING(MI_BATCH_BUFFER_START |
2414                                          (2 << 6) |
2415                                          MI_BATCH_NON_SECURE_I965);
2416                                 OUT_RING(exec_start);
2417                         } else {
2418                                 OUT_RING(MI_BATCH_BUFFER_START |
2419                                          (2 << 6));
2420                                 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
2421                         }
2422                         ADVANCE_LP_RING();
2423                 }
2424         }
2425
2426         /* XXX breadcrumb */
2427         return 0;
2428 }
2429
2430 /* Throttle our rendering by waiting until the ring has completed our requests
2431  * emitted over 20 msec ago.
2432  *
2433  * This should get us reasonable parallelism between CPU and GPU but also
2434  * relatively low latency when blocking on a particular request to finish.
2435  */
2436 static int
2437 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
2438 {
2439         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
2440         int ret = 0;
2441         uint32_t seqno;
2442
2443         mutex_lock(&dev->struct_mutex);
2444         seqno = i915_file_priv->mm.last_gem_throttle_seqno;
2445         i915_file_priv->mm.last_gem_throttle_seqno =
2446                 i915_file_priv->mm.last_gem_seqno;
2447         if (seqno)
2448                 ret = i915_wait_request(dev, seqno);
2449         mutex_unlock(&dev->struct_mutex);
2450         return ret;
2451 }
2452
2453 int
2454 i915_gem_execbuffer(struct drm_device *dev, void *data,
2455                     struct drm_file *file_priv)
2456 {
2457         drm_i915_private_t *dev_priv = dev->dev_private;
2458         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
2459         struct drm_i915_gem_execbuffer *args = data;
2460         struct drm_i915_gem_exec_object *exec_list = NULL;
2461         struct drm_gem_object **object_list = NULL;
2462         struct drm_gem_object *batch_obj;
2463         int ret, i, pinned = 0;
2464         uint64_t exec_offset;
2465         uint32_t seqno, flush_domains;
2466         int pin_tries;
2467
2468 #if WATCH_EXEC
2469         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
2470                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
2471 #endif
2472
2473         if (args->buffer_count < 1) {
2474                 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
2475                 return -EINVAL;
2476         }
2477         /* Copy in the exec list from userland */
2478         exec_list = drm_calloc(sizeof(*exec_list), args->buffer_count,
2479                                DRM_MEM_DRIVER);
2480         object_list = drm_calloc(sizeof(*object_list), args->buffer_count,
2481                                  DRM_MEM_DRIVER);
2482         if (exec_list == NULL || object_list == NULL) {
2483                 DRM_ERROR("Failed to allocate exec or object list "
2484                           "for %d buffers\n",
2485                           args->buffer_count);
2486                 ret = -ENOMEM;
2487                 goto pre_mutex_err;
2488         }
2489         ret = copy_from_user(exec_list,
2490                              (struct drm_i915_relocation_entry __user *)
2491                              (uintptr_t) args->buffers_ptr,
2492                              sizeof(*exec_list) * args->buffer_count);
2493         if (ret != 0) {
2494                 DRM_ERROR("copy %d exec entries failed %d\n",
2495                           args->buffer_count, ret);
2496                 goto pre_mutex_err;
2497         }
2498
2499         mutex_lock(&dev->struct_mutex);
2500
2501         i915_verify_inactive(dev, __FILE__, __LINE__);
2502
2503         if (dev_priv->mm.wedged) {
2504                 DRM_ERROR("Execbuf while wedged\n");
2505                 mutex_unlock(&dev->struct_mutex);
2506                 ret = -EIO;
2507                 goto pre_mutex_err;
2508         }
2509
2510         if (dev_priv->mm.suspended) {
2511                 DRM_ERROR("Execbuf while VT-switched.\n");
2512                 mutex_unlock(&dev->struct_mutex);
2513                 ret = -EBUSY;
2514                 goto pre_mutex_err;
2515         }
2516
2517         /* Look up object handles */
2518         for (i = 0; i < args->buffer_count; i++) {
2519                 object_list[i] = drm_gem_object_lookup(dev, file_priv,
2520                                                        exec_list[i].handle);
2521                 if (object_list[i] == NULL) {
2522                         DRM_ERROR("Invalid object handle %d at index %d\n",
2523                                    exec_list[i].handle, i);
2524                         ret = -EBADF;
2525                         goto err;
2526                 }
2527         }
2528
2529         /* Pin and relocate */
2530         for (pin_tries = 0; ; pin_tries++) {
2531                 ret = 0;
2532                 for (i = 0; i < args->buffer_count; i++) {
2533                         object_list[i]->pending_read_domains = 0;
2534                         object_list[i]->pending_write_domain = 0;
2535                         ret = i915_gem_object_pin_and_relocate(object_list[i],
2536                                                                file_priv,
2537                                                                &exec_list[i]);
2538                         if (ret)
2539                                 break;
2540                         pinned = i + 1;
2541                 }
2542                 /* success */
2543                 if (ret == 0)
2544                         break;
2545
2546                 /* error other than GTT full, or we've already tried again */
2547                 if (ret != -ENOMEM || pin_tries >= 1) {
2548                         if (ret != -ERESTARTSYS)
2549                                 DRM_ERROR("Failed to pin buffers %d\n", ret);
2550                         goto err;
2551                 }
2552
2553                 /* unpin all of our buffers */
2554                 for (i = 0; i < pinned; i++)
2555                         i915_gem_object_unpin(object_list[i]);
2556                 pinned = 0;
2557
2558                 /* evict everyone we can from the aperture */
2559                 ret = i915_gem_evict_everything(dev);
2560                 if (ret)
2561                         goto err;
2562         }
2563
2564         /* Set the pending read domains for the batch buffer to COMMAND */
2565         batch_obj = object_list[args->buffer_count-1];
2566         batch_obj->pending_read_domains = I915_GEM_DOMAIN_COMMAND;
2567         batch_obj->pending_write_domain = 0;
2568
2569         i915_verify_inactive(dev, __FILE__, __LINE__);
2570
2571         /* Zero the global flush/invalidate flags. These
2572          * will be modified as new domains are computed
2573          * for each object
2574          */
2575         dev->invalidate_domains = 0;
2576         dev->flush_domains = 0;
2577
2578         for (i = 0; i < args->buffer_count; i++) {
2579                 struct drm_gem_object *obj = object_list[i];
2580
2581                 /* Compute new gpu domains and update invalidate/flush */
2582                 i915_gem_object_set_to_gpu_domain(obj);
2583         }
2584
2585         i915_verify_inactive(dev, __FILE__, __LINE__);
2586
2587         if (dev->invalidate_domains | dev->flush_domains) {
2588 #if WATCH_EXEC
2589                 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
2590                           __func__,
2591                          dev->invalidate_domains,
2592                          dev->flush_domains);
2593 #endif
2594                 i915_gem_flush(dev,
2595                                dev->invalidate_domains,
2596                                dev->flush_domains);
2597                 if (dev->flush_domains)
2598                         (void)i915_add_request(dev, dev->flush_domains);
2599         }
2600
2601         i915_verify_inactive(dev, __FILE__, __LINE__);
2602
2603 #if WATCH_COHERENCY
2604         for (i = 0; i < args->buffer_count; i++) {
2605                 i915_gem_object_check_coherency(object_list[i],
2606                                                 exec_list[i].handle);
2607         }
2608 #endif
2609
2610         exec_offset = exec_list[args->buffer_count - 1].offset;
2611
2612 #if WATCH_EXEC
2613         i915_gem_dump_object(object_list[args->buffer_count - 1],
2614                               args->batch_len,
2615                               __func__,
2616                               ~0);
2617 #endif
2618
2619         /* Exec the batchbuffer */
2620         ret = i915_dispatch_gem_execbuffer(dev, args, exec_offset);
2621         if (ret) {
2622                 DRM_ERROR("dispatch failed %d\n", ret);
2623                 goto err;
2624         }
2625
2626         /*
2627          * Ensure that the commands in the batch buffer are
2628          * finished before the interrupt fires
2629          */
2630         flush_domains = i915_retire_commands(dev);
2631
2632         i915_verify_inactive(dev, __FILE__, __LINE__);
2633
2634         /*
2635          * Get a seqno representing the execution of the current buffer,
2636          * which we can wait on.  We would like to mitigate these interrupts,
2637          * likely by only creating seqnos occasionally (so that we have
2638          * *some* interrupts representing completion of buffers that we can
2639          * wait on when trying to clear up gtt space).
2640          */
2641         seqno = i915_add_request(dev, flush_domains);
2642         BUG_ON(seqno == 0);
2643         i915_file_priv->mm.last_gem_seqno = seqno;
2644         for (i = 0; i < args->buffer_count; i++) {
2645                 struct drm_gem_object *obj = object_list[i];
2646
2647                 i915_gem_object_move_to_active(obj, seqno);
2648 #if WATCH_LRU
2649                 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
2650 #endif
2651         }
2652 #if WATCH_LRU
2653         i915_dump_lru(dev, __func__);
2654 #endif
2655
2656         i915_verify_inactive(dev, __FILE__, __LINE__);
2657
2658 err:
2659         for (i = 0; i < pinned; i++)
2660                 i915_gem_object_unpin(object_list[i]);
2661
2662         for (i = 0; i < args->buffer_count; i++)
2663                 drm_gem_object_unreference(object_list[i]);
2664
2665         mutex_unlock(&dev->struct_mutex);
2666
2667         if (!ret) {
2668                 /* Copy the new buffer offsets back to the user's exec list. */
2669                 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
2670                                    (uintptr_t) args->buffers_ptr,
2671                                    exec_list,
2672                                    sizeof(*exec_list) * args->buffer_count);
2673                 if (ret)
2674                         DRM_ERROR("failed to copy %d exec entries "
2675                                   "back to user (%d)\n",
2676                                   args->buffer_count, ret);
2677         }
2678
2679 pre_mutex_err:
2680         drm_free(object_list, sizeof(*object_list) * args->buffer_count,
2681                  DRM_MEM_DRIVER);
2682         drm_free(exec_list, sizeof(*exec_list) * args->buffer_count,
2683                  DRM_MEM_DRIVER);
2684
2685         return ret;
2686 }
2687
2688 int
2689 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
2690 {
2691         struct drm_device *dev = obj->dev;
2692         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2693         int ret;
2694
2695         i915_verify_inactive(dev, __FILE__, __LINE__);
2696         if (obj_priv->gtt_space == NULL) {
2697                 ret = i915_gem_object_bind_to_gtt(obj, alignment);
2698                 if (ret != 0) {
2699                         if (ret != -EBUSY && ret != -ERESTARTSYS)
2700                                 DRM_ERROR("Failure to bind: %d", ret);
2701                         return ret;
2702                 }
2703                 /*
2704                  * Pre-965 chips need a fence register set up in order to
2705                  * properly handle tiled surfaces.
2706                  */
2707                 if (!IS_I965G(dev) &&
2708                     obj_priv->fence_reg == I915_FENCE_REG_NONE &&
2709                     obj_priv->tiling_mode != I915_TILING_NONE)
2710                         i915_gem_object_get_fence_reg(obj, true);
2711         }
2712         obj_priv->pin_count++;
2713
2714         /* If the object is not active and not pending a flush,
2715          * remove it from the inactive list
2716          */
2717         if (obj_priv->pin_count == 1) {
2718                 atomic_inc(&dev->pin_count);
2719                 atomic_add(obj->size, &dev->pin_memory);
2720                 if (!obj_priv->active &&
2721                     (obj->write_domain & ~(I915_GEM_DOMAIN_CPU |
2722                                            I915_GEM_DOMAIN_GTT)) == 0 &&
2723                     !list_empty(&obj_priv->list))
2724                         list_del_init(&obj_priv->list);
2725         }
2726         i915_verify_inactive(dev, __FILE__, __LINE__);
2727
2728         return 0;
2729 }
2730
2731 void
2732 i915_gem_object_unpin(struct drm_gem_object *obj)
2733 {
2734         struct drm_device *dev = obj->dev;
2735         drm_i915_private_t *dev_priv = dev->dev_private;
2736         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2737
2738         i915_verify_inactive(dev, __FILE__, __LINE__);
2739         obj_priv->pin_count--;
2740         BUG_ON(obj_priv->pin_count < 0);
2741         BUG_ON(obj_priv->gtt_space == NULL);
2742
2743         /* If the object is no longer pinned, and is
2744          * neither active nor being flushed, then stick it on
2745          * the inactive list
2746          */
2747         if (obj_priv->pin_count == 0) {
2748                 if (!obj_priv->active &&
2749                     (obj->write_domain & ~(I915_GEM_DOMAIN_CPU |
2750                                            I915_GEM_DOMAIN_GTT)) == 0)
2751                         list_move_tail(&obj_priv->list,
2752                                        &dev_priv->mm.inactive_list);
2753                 atomic_dec(&dev->pin_count);
2754                 atomic_sub(obj->size, &dev->pin_memory);
2755         }
2756         i915_verify_inactive(dev, __FILE__, __LINE__);
2757 }
2758
2759 int
2760 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
2761                    struct drm_file *file_priv)
2762 {
2763         struct drm_i915_gem_pin *args = data;
2764         struct drm_gem_object *obj;
2765         struct drm_i915_gem_object *obj_priv;
2766         int ret;
2767
2768         mutex_lock(&dev->struct_mutex);
2769
2770         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2771         if (obj == NULL) {
2772                 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
2773                           args->handle);
2774                 mutex_unlock(&dev->struct_mutex);
2775                 return -EBADF;
2776         }
2777         obj_priv = obj->driver_private;
2778
2779         if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
2780                 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
2781                           args->handle);
2782                 drm_gem_object_unreference(obj);
2783                 mutex_unlock(&dev->struct_mutex);
2784                 return -EINVAL;
2785         }
2786
2787         obj_priv->user_pin_count++;
2788         obj_priv->pin_filp = file_priv;
2789         if (obj_priv->user_pin_count == 1) {
2790                 ret = i915_gem_object_pin(obj, args->alignment);
2791                 if (ret != 0) {
2792                         drm_gem_object_unreference(obj);
2793                         mutex_unlock(&dev->struct_mutex);
2794                         return ret;
2795                 }
2796         }
2797
2798         /* XXX - flush the CPU caches for pinned objects
2799          * as the X server doesn't manage domains yet
2800          */
2801         i915_gem_object_flush_cpu_write_domain(obj);
2802         args->offset = obj_priv->gtt_offset;
2803         drm_gem_object_unreference(obj);
2804         mutex_unlock(&dev->struct_mutex);
2805
2806         return 0;
2807 }
2808
2809 int
2810 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
2811                      struct drm_file *file_priv)
2812 {
2813         struct drm_i915_gem_pin *args = data;
2814         struct drm_gem_object *obj;
2815         struct drm_i915_gem_object *obj_priv;
2816
2817         mutex_lock(&dev->struct_mutex);
2818
2819         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2820         if (obj == NULL) {
2821                 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
2822                           args->handle);
2823                 mutex_unlock(&dev->struct_mutex);
2824                 return -EBADF;
2825         }
2826
2827         obj_priv = obj->driver_private;
2828         if (obj_priv->pin_filp != file_priv) {
2829                 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
2830                           args->handle);
2831                 drm_gem_object_unreference(obj);
2832                 mutex_unlock(&dev->struct_mutex);
2833                 return -EINVAL;
2834         }
2835         obj_priv->user_pin_count--;
2836         if (obj_priv->user_pin_count == 0) {
2837                 obj_priv->pin_filp = NULL;
2838                 i915_gem_object_unpin(obj);
2839         }
2840
2841         drm_gem_object_unreference(obj);
2842         mutex_unlock(&dev->struct_mutex);
2843         return 0;
2844 }
2845
2846 int
2847 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2848                     struct drm_file *file_priv)
2849 {
2850         struct drm_i915_gem_busy *args = data;
2851         struct drm_gem_object *obj;
2852         struct drm_i915_gem_object *obj_priv;
2853
2854         mutex_lock(&dev->struct_mutex);
2855         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2856         if (obj == NULL) {
2857                 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
2858                           args->handle);
2859                 mutex_unlock(&dev->struct_mutex);
2860                 return -EBADF;
2861         }
2862
2863         obj_priv = obj->driver_private;
2864         /* Don't count being on the flushing list against the object being
2865          * done.  Otherwise, a buffer left on the flushing list but not getting
2866          * flushed (because nobody's flushing that domain) won't ever return
2867          * unbusy and get reused by libdrm's bo cache.  The other expected
2868          * consumer of this interface, OpenGL's occlusion queries, also specs
2869          * that the objects get unbusy "eventually" without any interference.
2870          */
2871         args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
2872
2873         drm_gem_object_unreference(obj);
2874         mutex_unlock(&dev->struct_mutex);
2875         return 0;
2876 }
2877
2878 int
2879 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2880                         struct drm_file *file_priv)
2881 {
2882     return i915_gem_ring_throttle(dev, file_priv);
2883 }
2884
2885 int i915_gem_init_object(struct drm_gem_object *obj)
2886 {
2887         struct drm_i915_gem_object *obj_priv;
2888
2889         obj_priv = drm_calloc(1, sizeof(*obj_priv), DRM_MEM_DRIVER);
2890         if (obj_priv == NULL)
2891                 return -ENOMEM;
2892
2893         /*
2894          * We've just allocated pages from the kernel,
2895          * so they've just been written by the CPU with
2896          * zeros. They'll need to be clflushed before we
2897          * use them with the GPU.
2898          */
2899         obj->write_domain = I915_GEM_DOMAIN_CPU;
2900         obj->read_domains = I915_GEM_DOMAIN_CPU;
2901
2902         obj_priv->agp_type = AGP_USER_MEMORY;
2903
2904         obj->driver_private = obj_priv;
2905         obj_priv->obj = obj;
2906         obj_priv->fence_reg = I915_FENCE_REG_NONE;
2907         INIT_LIST_HEAD(&obj_priv->list);
2908
2909         return 0;
2910 }
2911
2912 void i915_gem_free_object(struct drm_gem_object *obj)
2913 {
2914         struct drm_device *dev = obj->dev;
2915         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2916
2917         while (obj_priv->pin_count > 0)
2918                 i915_gem_object_unpin(obj);
2919
2920         if (obj_priv->phys_obj)
2921                 i915_gem_detach_phys_object(dev, obj);
2922
2923         i915_gem_object_unbind(obj);
2924
2925         i915_gem_free_mmap_offset(obj);
2926
2927         drm_free(obj_priv->page_cpu_valid, 1, DRM_MEM_DRIVER);
2928         drm_free(obj->driver_private, 1, DRM_MEM_DRIVER);
2929 }
2930
2931 /** Unbinds all objects that are on the given buffer list. */
2932 static int
2933 i915_gem_evict_from_list(struct drm_device *dev, struct list_head *head)
2934 {
2935         struct drm_gem_object *obj;
2936         struct drm_i915_gem_object *obj_priv;
2937         int ret;
2938
2939         while (!list_empty(head)) {
2940                 obj_priv = list_first_entry(head,
2941                                             struct drm_i915_gem_object,
2942                                             list);
2943                 obj = obj_priv->obj;
2944
2945                 if (obj_priv->pin_count != 0) {
2946                         DRM_ERROR("Pinned object in unbind list\n");
2947                         mutex_unlock(&dev->struct_mutex);
2948                         return -EINVAL;
2949                 }
2950
2951                 ret = i915_gem_object_unbind(obj);
2952                 if (ret != 0) {
2953                         DRM_ERROR("Error unbinding object in LeaveVT: %d\n",
2954                                   ret);
2955                         mutex_unlock(&dev->struct_mutex);
2956                         return ret;
2957                 }
2958         }
2959
2960
2961         return 0;
2962 }
2963
2964 static int
2965 i915_gem_idle(struct drm_device *dev)
2966 {
2967         drm_i915_private_t *dev_priv = dev->dev_private;
2968         uint32_t seqno, cur_seqno, last_seqno;
2969         int stuck, ret;
2970
2971         mutex_lock(&dev->struct_mutex);
2972
2973         if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
2974                 mutex_unlock(&dev->struct_mutex);
2975                 return 0;
2976         }
2977
2978         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
2979          * We need to replace this with a semaphore, or something.
2980          */
2981         dev_priv->mm.suspended = 1;
2982
2983         /* Cancel the retire work handler, wait for it to finish if running
2984          */
2985         mutex_unlock(&dev->struct_mutex);
2986         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
2987         mutex_lock(&dev->struct_mutex);
2988
2989         i915_kernel_lost_context(dev);
2990
2991         /* Flush the GPU along with all non-CPU write domains
2992          */
2993         i915_gem_flush(dev, ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT),
2994                        ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
2995         seqno = i915_add_request(dev, ~I915_GEM_DOMAIN_CPU);
2996
2997         if (seqno == 0) {
2998                 mutex_unlock(&dev->struct_mutex);
2999                 return -ENOMEM;
3000         }
3001
3002         dev_priv->mm.waiting_gem_seqno = seqno;
3003         last_seqno = 0;
3004         stuck = 0;
3005         for (;;) {
3006                 cur_seqno = i915_get_gem_seqno(dev);
3007                 if (i915_seqno_passed(cur_seqno, seqno))
3008                         break;
3009                 if (last_seqno == cur_seqno) {
3010                         if (stuck++ > 100) {
3011                                 DRM_ERROR("hardware wedged\n");
3012                                 dev_priv->mm.wedged = 1;
3013                                 DRM_WAKEUP(&dev_priv->irq_queue);
3014                                 break;
3015                         }
3016                 }
3017                 msleep(10);
3018                 last_seqno = cur_seqno;
3019         }
3020         dev_priv->mm.waiting_gem_seqno = 0;
3021
3022         i915_gem_retire_requests(dev);
3023
3024         if (!dev_priv->mm.wedged) {
3025                 /* Active and flushing should now be empty as we've
3026                  * waited for a sequence higher than any pending execbuffer
3027                  */
3028                 WARN_ON(!list_empty(&dev_priv->mm.active_list));
3029                 WARN_ON(!list_empty(&dev_priv->mm.flushing_list));
3030                 /* Request should now be empty as we've also waited
3031                  * for the last request in the list
3032                  */
3033                 WARN_ON(!list_empty(&dev_priv->mm.request_list));
3034         }
3035
3036         /* Empty the active and flushing lists to inactive.  If there's
3037          * anything left at this point, it means that we're wedged and
3038          * nothing good's going to happen by leaving them there.  So strip
3039          * the GPU domains and just stuff them onto inactive.
3040          */
3041         while (!list_empty(&dev_priv->mm.active_list)) {
3042                 struct drm_i915_gem_object *obj_priv;
3043
3044                 obj_priv = list_first_entry(&dev_priv->mm.active_list,
3045                                             struct drm_i915_gem_object,
3046                                             list);
3047                 obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
3048                 i915_gem_object_move_to_inactive(obj_priv->obj);
3049         }
3050
3051         while (!list_empty(&dev_priv->mm.flushing_list)) {
3052                 struct drm_i915_gem_object *obj_priv;
3053
3054                 obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
3055                                             struct drm_i915_gem_object,
3056                                             list);
3057                 obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
3058                 i915_gem_object_move_to_inactive(obj_priv->obj);
3059         }
3060
3061
3062         /* Move all inactive buffers out of the GTT. */
3063         ret = i915_gem_evict_from_list(dev, &dev_priv->mm.inactive_list);
3064         WARN_ON(!list_empty(&dev_priv->mm.inactive_list));
3065         if (ret) {
3066                 mutex_unlock(&dev->struct_mutex);
3067                 return ret;
3068         }
3069
3070         i915_gem_cleanup_ringbuffer(dev);
3071         mutex_unlock(&dev->struct_mutex);
3072
3073         return 0;
3074 }
3075
3076 static int
3077 i915_gem_init_hws(struct drm_device *dev)
3078 {
3079         drm_i915_private_t *dev_priv = dev->dev_private;
3080         struct drm_gem_object *obj;
3081         struct drm_i915_gem_object *obj_priv;
3082         int ret;
3083
3084         /* If we need a physical address for the status page, it's already
3085          * initialized at driver load time.
3086          */
3087         if (!I915_NEED_GFX_HWS(dev))
3088                 return 0;
3089
3090         obj = drm_gem_object_alloc(dev, 4096);
3091         if (obj == NULL) {
3092                 DRM_ERROR("Failed to allocate status page\n");
3093                 return -ENOMEM;
3094         }
3095         obj_priv = obj->driver_private;
3096         obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
3097
3098         ret = i915_gem_object_pin(obj, 4096);
3099         if (ret != 0) {
3100                 drm_gem_object_unreference(obj);
3101                 return ret;
3102         }
3103
3104         dev_priv->status_gfx_addr = obj_priv->gtt_offset;
3105
3106         dev_priv->hw_status_page = kmap(obj_priv->page_list[0]);
3107         if (dev_priv->hw_status_page == NULL) {
3108                 DRM_ERROR("Failed to map status page.\n");
3109                 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
3110                 i915_gem_object_unpin(obj);
3111                 drm_gem_object_unreference(obj);
3112                 return -EINVAL;
3113         }
3114         dev_priv->hws_obj = obj;
3115         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
3116         I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
3117         I915_READ(HWS_PGA); /* posting read */
3118         DRM_DEBUG("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
3119
3120         return 0;
3121 }
3122
3123 static void
3124 i915_gem_cleanup_hws(struct drm_device *dev)
3125 {
3126         drm_i915_private_t *dev_priv = dev->dev_private;
3127         struct drm_gem_object *obj = dev_priv->hws_obj;
3128         struct drm_i915_gem_object *obj_priv = obj->driver_private;
3129
3130         if (dev_priv->hws_obj == NULL)
3131                 return;
3132
3133         kunmap(obj_priv->page_list[0]);
3134         i915_gem_object_unpin(obj);
3135         drm_gem_object_unreference(obj);
3136         dev_priv->hws_obj = NULL;
3137         memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
3138         dev_priv->hw_status_page = NULL;
3139
3140         /* Write high address into HWS_PGA when disabling. */
3141         I915_WRITE(HWS_PGA, 0x1ffff000);
3142 }
3143
3144 int
3145 i915_gem_init_ringbuffer(struct drm_device *dev)
3146 {
3147         drm_i915_private_t *dev_priv = dev->dev_private;
3148         struct drm_gem_object *obj;
3149         struct drm_i915_gem_object *obj_priv;
3150         drm_i915_ring_buffer_t *ring = &dev_priv->ring;
3151         int ret;
3152         u32 head;
3153
3154         ret = i915_gem_init_hws(dev);
3155         if (ret != 0)
3156                 return ret;
3157
3158         obj = drm_gem_object_alloc(dev, 128 * 1024);
3159         if (obj == NULL) {
3160                 DRM_ERROR("Failed to allocate ringbuffer\n");
3161                 i915_gem_cleanup_hws(dev);
3162                 return -ENOMEM;
3163         }
3164         obj_priv = obj->driver_private;
3165
3166         ret = i915_gem_object_pin(obj, 4096);
3167         if (ret != 0) {
3168                 drm_gem_object_unreference(obj);
3169                 i915_gem_cleanup_hws(dev);
3170                 return ret;
3171         }
3172
3173         /* Set up the kernel mapping for the ring. */
3174         ring->Size = obj->size;
3175         ring->tail_mask = obj->size - 1;
3176
3177         ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
3178         ring->map.size = obj->size;
3179         ring->map.type = 0;
3180         ring->map.flags = 0;
3181         ring->map.mtrr = 0;
3182
3183         drm_core_ioremap_wc(&ring->map, dev);
3184         if (ring->map.handle == NULL) {
3185                 DRM_ERROR("Failed to map ringbuffer.\n");
3186                 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
3187                 i915_gem_object_unpin(obj);
3188                 drm_gem_object_unreference(obj);
3189                 i915_gem_cleanup_hws(dev);
3190                 return -EINVAL;
3191         }
3192         ring->ring_obj = obj;
3193         ring->virtual_start = ring->map.handle;
3194
3195         /* Stop the ring if it's running. */
3196         I915_WRITE(PRB0_CTL, 0);
3197         I915_WRITE(PRB0_TAIL, 0);
3198         I915_WRITE(PRB0_HEAD, 0);
3199
3200         /* Initialize the ring. */
3201         I915_WRITE(PRB0_START, obj_priv->gtt_offset);
3202         head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
3203
3204         /* G45 ring initialization fails to reset head to zero */
3205         if (head != 0) {
3206                 DRM_ERROR("Ring head not reset to zero "
3207                           "ctl %08x head %08x tail %08x start %08x\n",
3208                           I915_READ(PRB0_CTL),
3209                           I915_READ(PRB0_HEAD),
3210                           I915_READ(PRB0_TAIL),
3211                           I915_READ(PRB0_START));
3212                 I915_WRITE(PRB0_HEAD, 0);
3213
3214                 DRM_ERROR("Ring head forced to zero "
3215                           "ctl %08x head %08x tail %08x start %08x\n",
3216                           I915_READ(PRB0_CTL),
3217                           I915_READ(PRB0_HEAD),
3218                           I915_READ(PRB0_TAIL),
3219                           I915_READ(PRB0_START));
3220         }
3221
3222         I915_WRITE(PRB0_CTL,
3223                    ((obj->size - 4096) & RING_NR_PAGES) |
3224                    RING_NO_REPORT |
3225                    RING_VALID);
3226
3227         head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
3228
3229         /* If the head is still not zero, the ring is dead */
3230         if (head != 0) {
3231                 DRM_ERROR("Ring initialization failed "
3232                           "ctl %08x head %08x tail %08x start %08x\n",
3233                           I915_READ(PRB0_CTL),
3234                           I915_READ(PRB0_HEAD),
3235                           I915_READ(PRB0_TAIL),
3236                           I915_READ(PRB0_START));
3237                 return -EIO;
3238         }
3239
3240         /* Update our cache of the ring state */
3241         if (!drm_core_check_feature(dev, DRIVER_MODESET))
3242                 i915_kernel_lost_context(dev);
3243         else {
3244                 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
3245                 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
3246                 ring->space = ring->head - (ring->tail + 8);
3247                 if (ring->space < 0)
3248                         ring->space += ring->Size;
3249         }
3250
3251         return 0;
3252 }
3253
3254 void
3255 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
3256 {
3257         drm_i915_private_t *dev_priv = dev->dev_private;
3258
3259         if (dev_priv->ring.ring_obj == NULL)
3260                 return;
3261
3262         drm_core_ioremapfree(&dev_priv->ring.map, dev);
3263
3264         i915_gem_object_unpin(dev_priv->ring.ring_obj);
3265         drm_gem_object_unreference(dev_priv->ring.ring_obj);
3266         dev_priv->ring.ring_obj = NULL;
3267         memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
3268
3269         i915_gem_cleanup_hws(dev);
3270 }
3271
3272 int
3273 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
3274                        struct drm_file *file_priv)
3275 {
3276         drm_i915_private_t *dev_priv = dev->dev_private;
3277         int ret;
3278
3279         if (drm_core_check_feature(dev, DRIVER_MODESET))
3280                 return 0;
3281
3282         if (dev_priv->mm.wedged) {
3283                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3284                 dev_priv->mm.wedged = 0;
3285         }
3286
3287         mutex_lock(&dev->struct_mutex);
3288         dev_priv->mm.suspended = 0;
3289
3290         ret = i915_gem_init_ringbuffer(dev);
3291         if (ret != 0)
3292                 return ret;
3293
3294         BUG_ON(!list_empty(&dev_priv->mm.active_list));
3295         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
3296         BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
3297         BUG_ON(!list_empty(&dev_priv->mm.request_list));
3298         mutex_unlock(&dev->struct_mutex);
3299
3300         drm_irq_install(dev);
3301
3302         return 0;
3303 }
3304
3305 int
3306 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
3307                        struct drm_file *file_priv)
3308 {
3309         int ret;
3310
3311         if (drm_core_check_feature(dev, DRIVER_MODESET))
3312                 return 0;
3313
3314         ret = i915_gem_idle(dev);
3315         drm_irq_uninstall(dev);
3316
3317         return ret;
3318 }
3319
3320 void
3321 i915_gem_lastclose(struct drm_device *dev)
3322 {
3323         int ret;
3324
3325         if (drm_core_check_feature(dev, DRIVER_MODESET))
3326                 return;
3327
3328         ret = i915_gem_idle(dev);
3329         if (ret)
3330                 DRM_ERROR("failed to idle hardware: %d\n", ret);
3331 }
3332
3333 void
3334 i915_gem_load(struct drm_device *dev)
3335 {
3336         drm_i915_private_t *dev_priv = dev->dev_private;
3337
3338         INIT_LIST_HEAD(&dev_priv->mm.active_list);
3339         INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
3340         INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
3341         INIT_LIST_HEAD(&dev_priv->mm.request_list);
3342         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
3343                           i915_gem_retire_work_handler);
3344         dev_priv->mm.next_gem_seqno = 1;
3345
3346         /* Old X drivers will take 0-2 for front, back, depth buffers */
3347         dev_priv->fence_reg_start = 3;
3348
3349         if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3350                 dev_priv->num_fence_regs = 16;
3351         else
3352                 dev_priv->num_fence_regs = 8;
3353
3354         i915_gem_detect_bit_6_swizzle(dev);
3355 }
3356
3357 /*
3358  * Create a physically contiguous memory object for this object
3359  * e.g. for cursor + overlay regs
3360  */
3361 int i915_gem_init_phys_object(struct drm_device *dev,
3362                               int id, int size)
3363 {
3364         drm_i915_private_t *dev_priv = dev->dev_private;
3365         struct drm_i915_gem_phys_object *phys_obj;
3366         int ret;
3367
3368         if (dev_priv->mm.phys_objs[id - 1] || !size)
3369                 return 0;
3370
3371         phys_obj = drm_calloc(1, sizeof(struct drm_i915_gem_phys_object), DRM_MEM_DRIVER);
3372         if (!phys_obj)
3373                 return -ENOMEM;
3374
3375         phys_obj->id = id;
3376
3377         phys_obj->handle = drm_pci_alloc(dev, size, 0, 0xffffffff);
3378         if (!phys_obj->handle) {
3379                 ret = -ENOMEM;
3380                 goto kfree_obj;
3381         }
3382 #ifdef CONFIG_X86
3383         set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3384 #endif
3385
3386         dev_priv->mm.phys_objs[id - 1] = phys_obj;
3387
3388         return 0;
3389 kfree_obj:
3390         drm_free(phys_obj, sizeof(struct drm_i915_gem_phys_object), DRM_MEM_DRIVER);
3391         return ret;
3392 }
3393
3394 void i915_gem_free_phys_object(struct drm_device *dev, int id)
3395 {
3396         drm_i915_private_t *dev_priv = dev->dev_private;
3397         struct drm_i915_gem_phys_object *phys_obj;
3398
3399         if (!dev_priv->mm.phys_objs[id - 1])
3400                 return;
3401
3402         phys_obj = dev_priv->mm.phys_objs[id - 1];
3403         if (phys_obj->cur_obj) {
3404                 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
3405         }
3406
3407 #ifdef CONFIG_X86
3408         set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3409 #endif
3410         drm_pci_free(dev, phys_obj->handle);
3411         kfree(phys_obj);
3412         dev_priv->mm.phys_objs[id - 1] = NULL;
3413 }
3414
3415 void i915_gem_free_all_phys_object(struct drm_device *dev)
3416 {
3417         int i;
3418
3419         for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
3420                 i915_gem_free_phys_object(dev, i);
3421 }
3422
3423 void i915_gem_detach_phys_object(struct drm_device *dev,
3424                                  struct drm_gem_object *obj)
3425 {
3426         struct drm_i915_gem_object *obj_priv;
3427         int i;
3428         int ret;
3429         int page_count;
3430
3431         obj_priv = obj->driver_private;
3432         if (!obj_priv->phys_obj)
3433                 return;
3434
3435         ret = i915_gem_object_get_page_list(obj);
3436         if (ret)
3437                 goto out;
3438
3439         page_count = obj->size / PAGE_SIZE;
3440
3441         for (i = 0; i < page_count; i++) {
3442                 char *dst = kmap_atomic(obj_priv->page_list[i], KM_USER0);
3443                 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
3444
3445                 memcpy(dst, src, PAGE_SIZE);
3446                 kunmap_atomic(dst, KM_USER0);
3447         }
3448         drm_clflush_pages(obj_priv->page_list, page_count);
3449         drm_agp_chipset_flush(dev);
3450 out:
3451         obj_priv->phys_obj->cur_obj = NULL;
3452         obj_priv->phys_obj = NULL;
3453 }
3454
3455 int
3456 i915_gem_attach_phys_object(struct drm_device *dev,
3457                             struct drm_gem_object *obj, int id)
3458 {
3459         drm_i915_private_t *dev_priv = dev->dev_private;
3460         struct drm_i915_gem_object *obj_priv;
3461         int ret = 0;
3462         int page_count;
3463         int i;
3464
3465         if (id > I915_MAX_PHYS_OBJECT)
3466                 return -EINVAL;
3467
3468         obj_priv = obj->driver_private;
3469
3470         if (obj_priv->phys_obj) {
3471                 if (obj_priv->phys_obj->id == id)
3472                         return 0;
3473                 i915_gem_detach_phys_object(dev, obj);
3474         }
3475
3476
3477         /* create a new object */
3478         if (!dev_priv->mm.phys_objs[id - 1]) {
3479                 ret = i915_gem_init_phys_object(dev, id,
3480                                                 obj->size);
3481                 if (ret) {
3482                         DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
3483                         goto out;
3484                 }
3485         }
3486
3487         /* bind to the object */
3488         obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
3489         obj_priv->phys_obj->cur_obj = obj;
3490
3491         ret = i915_gem_object_get_page_list(obj);
3492         if (ret) {
3493                 DRM_ERROR("failed to get page list\n");
3494                 goto out;
3495         }
3496
3497         page_count = obj->size / PAGE_SIZE;
3498
3499         for (i = 0; i < page_count; i++) {
3500                 char *src = kmap_atomic(obj_priv->page_list[i], KM_USER0);
3501                 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
3502
3503                 memcpy(dst, src, PAGE_SIZE);
3504                 kunmap_atomic(src, KM_USER0);
3505         }
3506
3507         return 0;
3508 out:
3509         return ret;
3510 }
3511
3512 static int
3513 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
3514                      struct drm_i915_gem_pwrite *args,
3515                      struct drm_file *file_priv)
3516 {
3517         struct drm_i915_gem_object *obj_priv = obj->driver_private;
3518         void *obj_addr;
3519         int ret;
3520         char __user *user_data;
3521
3522         user_data = (char __user *) (uintptr_t) args->data_ptr;
3523         obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
3524
3525         DRM_ERROR("obj_addr %p, %lld\n", obj_addr, args->size);
3526         ret = copy_from_user(obj_addr, user_data, args->size);
3527         if (ret)
3528                 return -EFAULT;
3529
3530         drm_agp_chipset_flush(dev);
3531         return 0;
3532 }