2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/swap.h>
35 #include <linux/pci.h>
37 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
39 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
42 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
44 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
47 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
48 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
49 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
51 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
52 static int i915_gem_evict_something(struct drm_device *dev, int min_size);
53 static int i915_gem_evict_from_inactive_list(struct drm_device *dev);
54 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
55 struct drm_i915_gem_pwrite *args,
56 struct drm_file *file_priv);
58 static LIST_HEAD(shrink_list);
59 static DEFINE_SPINLOCK(shrink_list_lock);
61 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
64 drm_i915_private_t *dev_priv = dev->dev_private;
67 (start & (PAGE_SIZE - 1)) != 0 ||
68 (end & (PAGE_SIZE - 1)) != 0) {
72 drm_mm_init(&dev_priv->mm.gtt_space, start,
75 dev->gtt_total = (uint32_t) (end - start);
81 i915_gem_init_ioctl(struct drm_device *dev, void *data,
82 struct drm_file *file_priv)
84 struct drm_i915_gem_init *args = data;
87 mutex_lock(&dev->struct_mutex);
88 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
89 mutex_unlock(&dev->struct_mutex);
95 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
96 struct drm_file *file_priv)
98 struct drm_i915_gem_get_aperture *args = data;
100 if (!(dev->driver->driver_features & DRIVER_GEM))
103 args->aper_size = dev->gtt_total;
104 args->aper_available_size = (args->aper_size -
105 atomic_read(&dev->pin_memory));
112 * Creates a new mm object and returns a handle to it.
115 i915_gem_create_ioctl(struct drm_device *dev, void *data,
116 struct drm_file *file_priv)
118 struct drm_i915_gem_create *args = data;
119 struct drm_gem_object *obj;
123 args->size = roundup(args->size, PAGE_SIZE);
125 /* Allocate the new object */
126 obj = drm_gem_object_alloc(dev, args->size);
130 ret = drm_gem_handle_create(file_priv, obj, &handle);
131 mutex_lock(&dev->struct_mutex);
132 drm_gem_object_handle_unreference(obj);
133 mutex_unlock(&dev->struct_mutex);
138 args->handle = handle;
144 fast_shmem_read(struct page **pages,
145 loff_t page_base, int page_offset,
152 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
155 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
156 kunmap_atomic(vaddr, KM_USER0);
164 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
166 drm_i915_private_t *dev_priv = obj->dev->dev_private;
167 struct drm_i915_gem_object *obj_priv = obj->driver_private;
169 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
170 obj_priv->tiling_mode != I915_TILING_NONE;
174 slow_shmem_copy(struct page *dst_page,
176 struct page *src_page,
180 char *dst_vaddr, *src_vaddr;
182 dst_vaddr = kmap_atomic(dst_page, KM_USER0);
183 if (dst_vaddr == NULL)
186 src_vaddr = kmap_atomic(src_page, KM_USER1);
187 if (src_vaddr == NULL) {
188 kunmap_atomic(dst_vaddr, KM_USER0);
192 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
194 kunmap_atomic(src_vaddr, KM_USER1);
195 kunmap_atomic(dst_vaddr, KM_USER0);
201 slow_shmem_bit17_copy(struct page *gpu_page,
203 struct page *cpu_page,
208 char *gpu_vaddr, *cpu_vaddr;
210 /* Use the unswizzled path if this page isn't affected. */
211 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
213 return slow_shmem_copy(cpu_page, cpu_offset,
214 gpu_page, gpu_offset, length);
216 return slow_shmem_copy(gpu_page, gpu_offset,
217 cpu_page, cpu_offset, length);
220 gpu_vaddr = kmap_atomic(gpu_page, KM_USER0);
221 if (gpu_vaddr == NULL)
224 cpu_vaddr = kmap_atomic(cpu_page, KM_USER1);
225 if (cpu_vaddr == NULL) {
226 kunmap_atomic(gpu_vaddr, KM_USER0);
230 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
231 * XORing with the other bits (A9 for Y, A9 and A10 for X)
234 int cacheline_end = ALIGN(gpu_offset + 1, 64);
235 int this_length = min(cacheline_end - gpu_offset, length);
236 int swizzled_gpu_offset = gpu_offset ^ 64;
239 memcpy(cpu_vaddr + cpu_offset,
240 gpu_vaddr + swizzled_gpu_offset,
243 memcpy(gpu_vaddr + swizzled_gpu_offset,
244 cpu_vaddr + cpu_offset,
247 cpu_offset += this_length;
248 gpu_offset += this_length;
249 length -= this_length;
252 kunmap_atomic(cpu_vaddr, KM_USER1);
253 kunmap_atomic(gpu_vaddr, KM_USER0);
259 * This is the fast shmem pread path, which attempts to copy_from_user directly
260 * from the backing pages of the object to the user's address space. On a
261 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
264 i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
265 struct drm_i915_gem_pread *args,
266 struct drm_file *file_priv)
268 struct drm_i915_gem_object *obj_priv = obj->driver_private;
270 loff_t offset, page_base;
271 char __user *user_data;
272 int page_offset, page_length;
275 user_data = (char __user *) (uintptr_t) args->data_ptr;
278 mutex_lock(&dev->struct_mutex);
280 ret = i915_gem_object_get_pages(obj);
284 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
289 obj_priv = obj->driver_private;
290 offset = args->offset;
293 /* Operation in this page
295 * page_base = page offset within aperture
296 * page_offset = offset within page
297 * page_length = bytes to copy for this page
299 page_base = (offset & ~(PAGE_SIZE-1));
300 page_offset = offset & (PAGE_SIZE-1);
301 page_length = remain;
302 if ((page_offset + remain) > PAGE_SIZE)
303 page_length = PAGE_SIZE - page_offset;
305 ret = fast_shmem_read(obj_priv->pages,
306 page_base, page_offset,
307 user_data, page_length);
311 remain -= page_length;
312 user_data += page_length;
313 offset += page_length;
317 i915_gem_object_put_pages(obj);
319 mutex_unlock(&dev->struct_mutex);
325 i915_gem_object_get_page_gfp_mask (struct drm_gem_object *obj)
327 return mapping_gfp_mask(obj->filp->f_path.dentry->d_inode->i_mapping);
331 i915_gem_object_set_page_gfp_mask (struct drm_gem_object *obj, gfp_t gfp)
333 mapping_set_gfp_mask(obj->filp->f_path.dentry->d_inode->i_mapping, gfp);
337 i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
341 ret = i915_gem_object_get_pages(obj);
343 /* If we've insufficient memory to map in the pages, attempt
344 * to make some space by throwing out some old buffers.
346 if (ret == -ENOMEM) {
347 struct drm_device *dev = obj->dev;
350 ret = i915_gem_evict_something(dev, obj->size);
354 gfp = i915_gem_object_get_page_gfp_mask(obj);
355 i915_gem_object_set_page_gfp_mask(obj, gfp & ~__GFP_NORETRY);
356 ret = i915_gem_object_get_pages(obj);
357 i915_gem_object_set_page_gfp_mask (obj, gfp);
364 * This is the fallback shmem pread path, which allocates temporary storage
365 * in kernel space to copy_to_user into outside of the struct_mutex, so we
366 * can copy out of the object's backing pages while holding the struct mutex
367 * and not take page faults.
370 i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
371 struct drm_i915_gem_pread *args,
372 struct drm_file *file_priv)
374 struct drm_i915_gem_object *obj_priv = obj->driver_private;
375 struct mm_struct *mm = current->mm;
376 struct page **user_pages;
378 loff_t offset, pinned_pages, i;
379 loff_t first_data_page, last_data_page, num_pages;
380 int shmem_page_index, shmem_page_offset;
381 int data_page_index, data_page_offset;
384 uint64_t data_ptr = args->data_ptr;
385 int do_bit17_swizzling;
389 /* Pin the user pages containing the data. We can't fault while
390 * holding the struct mutex, yet we want to hold it while
391 * dereferencing the user data.
393 first_data_page = data_ptr / PAGE_SIZE;
394 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
395 num_pages = last_data_page - first_data_page + 1;
397 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
398 if (user_pages == NULL)
401 down_read(&mm->mmap_sem);
402 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
403 num_pages, 1, 0, user_pages, NULL);
404 up_read(&mm->mmap_sem);
405 if (pinned_pages < num_pages) {
407 goto fail_put_user_pages;
410 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
412 mutex_lock(&dev->struct_mutex);
414 ret = i915_gem_object_get_pages_or_evict(obj);
418 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
423 obj_priv = obj->driver_private;
424 offset = args->offset;
427 /* Operation in this page
429 * shmem_page_index = page number within shmem file
430 * shmem_page_offset = offset within page in shmem file
431 * data_page_index = page number in get_user_pages return
432 * data_page_offset = offset with data_page_index page.
433 * page_length = bytes to copy for this page
435 shmem_page_index = offset / PAGE_SIZE;
436 shmem_page_offset = offset & ~PAGE_MASK;
437 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
438 data_page_offset = data_ptr & ~PAGE_MASK;
440 page_length = remain;
441 if ((shmem_page_offset + page_length) > PAGE_SIZE)
442 page_length = PAGE_SIZE - shmem_page_offset;
443 if ((data_page_offset + page_length) > PAGE_SIZE)
444 page_length = PAGE_SIZE - data_page_offset;
446 if (do_bit17_swizzling) {
447 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
449 user_pages[data_page_index],
454 ret = slow_shmem_copy(user_pages[data_page_index],
456 obj_priv->pages[shmem_page_index],
463 remain -= page_length;
464 data_ptr += page_length;
465 offset += page_length;
469 i915_gem_object_put_pages(obj);
471 mutex_unlock(&dev->struct_mutex);
473 for (i = 0; i < pinned_pages; i++) {
474 SetPageDirty(user_pages[i]);
475 page_cache_release(user_pages[i]);
477 drm_free_large(user_pages);
483 * Reads data from the object referenced by handle.
485 * On error, the contents of *data are undefined.
488 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
489 struct drm_file *file_priv)
491 struct drm_i915_gem_pread *args = data;
492 struct drm_gem_object *obj;
493 struct drm_i915_gem_object *obj_priv;
496 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
499 obj_priv = obj->driver_private;
501 /* Bounds check source.
503 * XXX: This could use review for overflow issues...
505 if (args->offset > obj->size || args->size > obj->size ||
506 args->offset + args->size > obj->size) {
507 drm_gem_object_unreference(obj);
511 if (i915_gem_object_needs_bit17_swizzle(obj)) {
512 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
514 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
516 ret = i915_gem_shmem_pread_slow(dev, obj, args,
520 drm_gem_object_unreference(obj);
525 /* This is the fast write path which cannot handle
526 * page faults in the source data
530 fast_user_write(struct io_mapping *mapping,
531 loff_t page_base, int page_offset,
532 char __user *user_data,
536 unsigned long unwritten;
538 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
539 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
541 io_mapping_unmap_atomic(vaddr_atomic);
547 /* Here's the write path which can sleep for
552 slow_kernel_write(struct io_mapping *mapping,
553 loff_t gtt_base, int gtt_offset,
554 struct page *user_page, int user_offset,
557 char *src_vaddr, *dst_vaddr;
558 unsigned long unwritten;
560 dst_vaddr = io_mapping_map_atomic_wc(mapping, gtt_base);
561 src_vaddr = kmap_atomic(user_page, KM_USER1);
562 unwritten = __copy_from_user_inatomic_nocache(dst_vaddr + gtt_offset,
563 src_vaddr + user_offset,
565 kunmap_atomic(src_vaddr, KM_USER1);
566 io_mapping_unmap_atomic(dst_vaddr);
573 fast_shmem_write(struct page **pages,
574 loff_t page_base, int page_offset,
579 unsigned long unwritten;
581 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
584 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
585 kunmap_atomic(vaddr, KM_USER0);
593 * This is the fast pwrite path, where we copy the data directly from the
594 * user into the GTT, uncached.
597 i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
598 struct drm_i915_gem_pwrite *args,
599 struct drm_file *file_priv)
601 struct drm_i915_gem_object *obj_priv = obj->driver_private;
602 drm_i915_private_t *dev_priv = dev->dev_private;
604 loff_t offset, page_base;
605 char __user *user_data;
606 int page_offset, page_length;
609 user_data = (char __user *) (uintptr_t) args->data_ptr;
611 if (!access_ok(VERIFY_READ, user_data, remain))
615 mutex_lock(&dev->struct_mutex);
616 ret = i915_gem_object_pin(obj, 0);
618 mutex_unlock(&dev->struct_mutex);
621 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
625 obj_priv = obj->driver_private;
626 offset = obj_priv->gtt_offset + args->offset;
629 /* Operation in this page
631 * page_base = page offset within aperture
632 * page_offset = offset within page
633 * page_length = bytes to copy for this page
635 page_base = (offset & ~(PAGE_SIZE-1));
636 page_offset = offset & (PAGE_SIZE-1);
637 page_length = remain;
638 if ((page_offset + remain) > PAGE_SIZE)
639 page_length = PAGE_SIZE - page_offset;
641 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
642 page_offset, user_data, page_length);
644 /* If we get a fault while copying data, then (presumably) our
645 * source page isn't available. Return the error and we'll
646 * retry in the slow path.
651 remain -= page_length;
652 user_data += page_length;
653 offset += page_length;
657 i915_gem_object_unpin(obj);
658 mutex_unlock(&dev->struct_mutex);
664 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
665 * the memory and maps it using kmap_atomic for copying.
667 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
668 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
671 i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
672 struct drm_i915_gem_pwrite *args,
673 struct drm_file *file_priv)
675 struct drm_i915_gem_object *obj_priv = obj->driver_private;
676 drm_i915_private_t *dev_priv = dev->dev_private;
678 loff_t gtt_page_base, offset;
679 loff_t first_data_page, last_data_page, num_pages;
680 loff_t pinned_pages, i;
681 struct page **user_pages;
682 struct mm_struct *mm = current->mm;
683 int gtt_page_offset, data_page_offset, data_page_index, page_length;
685 uint64_t data_ptr = args->data_ptr;
689 /* Pin the user pages containing the data. We can't fault while
690 * holding the struct mutex, and all of the pwrite implementations
691 * want to hold it while dereferencing the user data.
693 first_data_page = data_ptr / PAGE_SIZE;
694 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
695 num_pages = last_data_page - first_data_page + 1;
697 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
698 if (user_pages == NULL)
701 down_read(&mm->mmap_sem);
702 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
703 num_pages, 0, 0, user_pages, NULL);
704 up_read(&mm->mmap_sem);
705 if (pinned_pages < num_pages) {
707 goto out_unpin_pages;
710 mutex_lock(&dev->struct_mutex);
711 ret = i915_gem_object_pin(obj, 0);
715 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
717 goto out_unpin_object;
719 obj_priv = obj->driver_private;
720 offset = obj_priv->gtt_offset + args->offset;
723 /* Operation in this page
725 * gtt_page_base = page offset within aperture
726 * gtt_page_offset = offset within page in aperture
727 * data_page_index = page number in get_user_pages return
728 * data_page_offset = offset with data_page_index page.
729 * page_length = bytes to copy for this page
731 gtt_page_base = offset & PAGE_MASK;
732 gtt_page_offset = offset & ~PAGE_MASK;
733 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
734 data_page_offset = data_ptr & ~PAGE_MASK;
736 page_length = remain;
737 if ((gtt_page_offset + page_length) > PAGE_SIZE)
738 page_length = PAGE_SIZE - gtt_page_offset;
739 if ((data_page_offset + page_length) > PAGE_SIZE)
740 page_length = PAGE_SIZE - data_page_offset;
742 ret = slow_kernel_write(dev_priv->mm.gtt_mapping,
743 gtt_page_base, gtt_page_offset,
744 user_pages[data_page_index],
748 /* If we get a fault while copying data, then (presumably) our
749 * source page isn't available. Return the error and we'll
750 * retry in the slow path.
753 goto out_unpin_object;
755 remain -= page_length;
756 offset += page_length;
757 data_ptr += page_length;
761 i915_gem_object_unpin(obj);
763 mutex_unlock(&dev->struct_mutex);
765 for (i = 0; i < pinned_pages; i++)
766 page_cache_release(user_pages[i]);
767 drm_free_large(user_pages);
773 * This is the fast shmem pwrite path, which attempts to directly
774 * copy_from_user into the kmapped pages backing the object.
777 i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
778 struct drm_i915_gem_pwrite *args,
779 struct drm_file *file_priv)
781 struct drm_i915_gem_object *obj_priv = obj->driver_private;
783 loff_t offset, page_base;
784 char __user *user_data;
785 int page_offset, page_length;
788 user_data = (char __user *) (uintptr_t) args->data_ptr;
791 mutex_lock(&dev->struct_mutex);
793 ret = i915_gem_object_get_pages(obj);
797 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
801 obj_priv = obj->driver_private;
802 offset = args->offset;
806 /* Operation in this page
808 * page_base = page offset within aperture
809 * page_offset = offset within page
810 * page_length = bytes to copy for this page
812 page_base = (offset & ~(PAGE_SIZE-1));
813 page_offset = offset & (PAGE_SIZE-1);
814 page_length = remain;
815 if ((page_offset + remain) > PAGE_SIZE)
816 page_length = PAGE_SIZE - page_offset;
818 ret = fast_shmem_write(obj_priv->pages,
819 page_base, page_offset,
820 user_data, page_length);
824 remain -= page_length;
825 user_data += page_length;
826 offset += page_length;
830 i915_gem_object_put_pages(obj);
832 mutex_unlock(&dev->struct_mutex);
838 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
839 * the memory and maps it using kmap_atomic for copying.
841 * This avoids taking mmap_sem for faulting on the user's address while the
842 * struct_mutex is held.
845 i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
846 struct drm_i915_gem_pwrite *args,
847 struct drm_file *file_priv)
849 struct drm_i915_gem_object *obj_priv = obj->driver_private;
850 struct mm_struct *mm = current->mm;
851 struct page **user_pages;
853 loff_t offset, pinned_pages, i;
854 loff_t first_data_page, last_data_page, num_pages;
855 int shmem_page_index, shmem_page_offset;
856 int data_page_index, data_page_offset;
859 uint64_t data_ptr = args->data_ptr;
860 int do_bit17_swizzling;
864 /* Pin the user pages containing the data. We can't fault while
865 * holding the struct mutex, and all of the pwrite implementations
866 * want to hold it while dereferencing the user data.
868 first_data_page = data_ptr / PAGE_SIZE;
869 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
870 num_pages = last_data_page - first_data_page + 1;
872 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
873 if (user_pages == NULL)
876 down_read(&mm->mmap_sem);
877 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
878 num_pages, 0, 0, user_pages, NULL);
879 up_read(&mm->mmap_sem);
880 if (pinned_pages < num_pages) {
882 goto fail_put_user_pages;
885 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
887 mutex_lock(&dev->struct_mutex);
889 ret = i915_gem_object_get_pages_or_evict(obj);
893 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
897 obj_priv = obj->driver_private;
898 offset = args->offset;
902 /* Operation in this page
904 * shmem_page_index = page number within shmem file
905 * shmem_page_offset = offset within page in shmem file
906 * data_page_index = page number in get_user_pages return
907 * data_page_offset = offset with data_page_index page.
908 * page_length = bytes to copy for this page
910 shmem_page_index = offset / PAGE_SIZE;
911 shmem_page_offset = offset & ~PAGE_MASK;
912 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
913 data_page_offset = data_ptr & ~PAGE_MASK;
915 page_length = remain;
916 if ((shmem_page_offset + page_length) > PAGE_SIZE)
917 page_length = PAGE_SIZE - shmem_page_offset;
918 if ((data_page_offset + page_length) > PAGE_SIZE)
919 page_length = PAGE_SIZE - data_page_offset;
921 if (do_bit17_swizzling) {
922 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
924 user_pages[data_page_index],
929 ret = slow_shmem_copy(obj_priv->pages[shmem_page_index],
931 user_pages[data_page_index],
938 remain -= page_length;
939 data_ptr += page_length;
940 offset += page_length;
944 i915_gem_object_put_pages(obj);
946 mutex_unlock(&dev->struct_mutex);
948 for (i = 0; i < pinned_pages; i++)
949 page_cache_release(user_pages[i]);
950 drm_free_large(user_pages);
956 * Writes data to the object referenced by handle.
958 * On error, the contents of the buffer that were to be modified are undefined.
961 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
962 struct drm_file *file_priv)
964 struct drm_i915_gem_pwrite *args = data;
965 struct drm_gem_object *obj;
966 struct drm_i915_gem_object *obj_priv;
969 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
972 obj_priv = obj->driver_private;
974 /* Bounds check destination.
976 * XXX: This could use review for overflow issues...
978 if (args->offset > obj->size || args->size > obj->size ||
979 args->offset + args->size > obj->size) {
980 drm_gem_object_unreference(obj);
984 /* We can only do the GTT pwrite on untiled buffers, as otherwise
985 * it would end up going through the fenced access, and we'll get
986 * different detiling behavior between reading and writing.
987 * pread/pwrite currently are reading and writing from the CPU
988 * perspective, requiring manual detiling by the client.
990 if (obj_priv->phys_obj)
991 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
992 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
993 dev->gtt_total != 0) {
994 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
995 if (ret == -EFAULT) {
996 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
999 } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
1000 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
1002 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
1003 if (ret == -EFAULT) {
1004 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
1011 DRM_INFO("pwrite failed %d\n", ret);
1014 drm_gem_object_unreference(obj);
1020 * Called when user space prepares to use an object with the CPU, either
1021 * through the mmap ioctl's mapping or a GTT mapping.
1024 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1025 struct drm_file *file_priv)
1027 struct drm_i915_private *dev_priv = dev->dev_private;
1028 struct drm_i915_gem_set_domain *args = data;
1029 struct drm_gem_object *obj;
1030 struct drm_i915_gem_object *obj_priv;
1031 uint32_t read_domains = args->read_domains;
1032 uint32_t write_domain = args->write_domain;
1035 if (!(dev->driver->driver_features & DRIVER_GEM))
1038 /* Only handle setting domains to types used by the CPU. */
1039 if (write_domain & I915_GEM_GPU_DOMAINS)
1042 if (read_domains & I915_GEM_GPU_DOMAINS)
1045 /* Having something in the write domain implies it's in the read
1046 * domain, and only that read domain. Enforce that in the request.
1048 if (write_domain != 0 && read_domains != write_domain)
1051 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1054 obj_priv = obj->driver_private;
1056 mutex_lock(&dev->struct_mutex);
1058 intel_mark_busy(dev, obj);
1061 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1062 obj, obj->size, read_domains, write_domain);
1064 if (read_domains & I915_GEM_DOMAIN_GTT) {
1065 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1067 /* Update the LRU on the fence for the CPU access that's
1070 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1071 list_move_tail(&obj_priv->fence_list,
1072 &dev_priv->mm.fence_list);
1075 /* Silently promote "you're not bound, there was nothing to do"
1076 * to success, since the client was just asking us to
1077 * make sure everything was done.
1082 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1085 drm_gem_object_unreference(obj);
1086 mutex_unlock(&dev->struct_mutex);
1091 * Called when user space has done writes to this buffer
1094 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1095 struct drm_file *file_priv)
1097 struct drm_i915_gem_sw_finish *args = data;
1098 struct drm_gem_object *obj;
1099 struct drm_i915_gem_object *obj_priv;
1102 if (!(dev->driver->driver_features & DRIVER_GEM))
1105 mutex_lock(&dev->struct_mutex);
1106 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1108 mutex_unlock(&dev->struct_mutex);
1113 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1114 __func__, args->handle, obj, obj->size);
1116 obj_priv = obj->driver_private;
1118 /* Pinned buffers may be scanout, so flush the cache */
1119 if (obj_priv->pin_count)
1120 i915_gem_object_flush_cpu_write_domain(obj);
1122 drm_gem_object_unreference(obj);
1123 mutex_unlock(&dev->struct_mutex);
1128 * Maps the contents of an object, returning the address it is mapped
1131 * While the mapping holds a reference on the contents of the object, it doesn't
1132 * imply a ref on the object itself.
1135 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1136 struct drm_file *file_priv)
1138 struct drm_i915_gem_mmap *args = data;
1139 struct drm_gem_object *obj;
1143 if (!(dev->driver->driver_features & DRIVER_GEM))
1146 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1150 offset = args->offset;
1152 down_write(¤t->mm->mmap_sem);
1153 addr = do_mmap(obj->filp, 0, args->size,
1154 PROT_READ | PROT_WRITE, MAP_SHARED,
1156 up_write(¤t->mm->mmap_sem);
1157 mutex_lock(&dev->struct_mutex);
1158 drm_gem_object_unreference(obj);
1159 mutex_unlock(&dev->struct_mutex);
1160 if (IS_ERR((void *)addr))
1163 args->addr_ptr = (uint64_t) addr;
1169 * i915_gem_fault - fault a page into the GTT
1170 * vma: VMA in question
1173 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1174 * from userspace. The fault handler takes care of binding the object to
1175 * the GTT (if needed), allocating and programming a fence register (again,
1176 * only if needed based on whether the old reg is still valid or the object
1177 * is tiled) and inserting a new PTE into the faulting process.
1179 * Note that the faulting process may involve evicting existing objects
1180 * from the GTT and/or fence registers to make room. So performance may
1181 * suffer if the GTT working set is large or there are few fence registers
1184 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1186 struct drm_gem_object *obj = vma->vm_private_data;
1187 struct drm_device *dev = obj->dev;
1188 struct drm_i915_private *dev_priv = dev->dev_private;
1189 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1190 pgoff_t page_offset;
1193 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1195 /* We don't use vmf->pgoff since that has the fake offset */
1196 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1199 /* Now bind it into the GTT if needed */
1200 mutex_lock(&dev->struct_mutex);
1201 if (!obj_priv->gtt_space) {
1202 ret = i915_gem_object_bind_to_gtt(obj, 0);
1204 mutex_unlock(&dev->struct_mutex);
1205 return VM_FAULT_SIGBUS;
1207 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1209 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1211 mutex_unlock(&dev->struct_mutex);
1212 return VM_FAULT_SIGBUS;
1216 /* Need a new fence register? */
1217 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1218 ret = i915_gem_object_get_fence_reg(obj);
1220 mutex_unlock(&dev->struct_mutex);
1221 return VM_FAULT_SIGBUS;
1225 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1228 /* Finally, remap it using the new GTT offset */
1229 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1231 mutex_unlock(&dev->struct_mutex);
1236 return VM_FAULT_OOM;
1239 return VM_FAULT_SIGBUS;
1241 return VM_FAULT_NOPAGE;
1246 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1247 * @obj: obj in question
1249 * GEM memory mapping works by handing back to userspace a fake mmap offset
1250 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1251 * up the object based on the offset and sets up the various memory mapping
1254 * This routine allocates and attaches a fake offset for @obj.
1257 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1259 struct drm_device *dev = obj->dev;
1260 struct drm_gem_mm *mm = dev->mm_private;
1261 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1262 struct drm_map_list *list;
1263 struct drm_local_map *map;
1266 /* Set the object up for mmap'ing */
1267 list = &obj->map_list;
1268 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1273 map->type = _DRM_GEM;
1274 map->size = obj->size;
1277 /* Get a DRM GEM mmap offset allocated... */
1278 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1279 obj->size / PAGE_SIZE, 0, 0);
1280 if (!list->file_offset_node) {
1281 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1286 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1287 obj->size / PAGE_SIZE, 0);
1288 if (!list->file_offset_node) {
1293 list->hash.key = list->file_offset_node->start;
1294 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1295 DRM_ERROR("failed to add to map hash\n");
1299 /* By now we should be all set, any drm_mmap request on the offset
1300 * below will get to our mmap & fault handler */
1301 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1306 drm_mm_put_block(list->file_offset_node);
1314 * i915_gem_release_mmap - remove physical page mappings
1315 * @obj: obj in question
1317 * Preserve the reservation of the mmaping with the DRM core code, but
1318 * relinquish ownership of the pages back to the system.
1320 * It is vital that we remove the page mapping if we have mapped a tiled
1321 * object through the GTT and then lose the fence register due to
1322 * resource pressure. Similarly if the object has been moved out of the
1323 * aperture, than pages mapped into userspace must be revoked. Removing the
1324 * mapping will then trigger a page fault on the next user access, allowing
1325 * fixup by i915_gem_fault().
1328 i915_gem_release_mmap(struct drm_gem_object *obj)
1330 struct drm_device *dev = obj->dev;
1331 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1333 if (dev->dev_mapping)
1334 unmap_mapping_range(dev->dev_mapping,
1335 obj_priv->mmap_offset, obj->size, 1);
1339 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1341 struct drm_device *dev = obj->dev;
1342 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1343 struct drm_gem_mm *mm = dev->mm_private;
1344 struct drm_map_list *list;
1346 list = &obj->map_list;
1347 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1349 if (list->file_offset_node) {
1350 drm_mm_put_block(list->file_offset_node);
1351 list->file_offset_node = NULL;
1359 obj_priv->mmap_offset = 0;
1363 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1364 * @obj: object to check
1366 * Return the required GTT alignment for an object, taking into account
1367 * potential fence register mapping if needed.
1370 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1372 struct drm_device *dev = obj->dev;
1373 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1377 * Minimum alignment is 4k (GTT page size), but might be greater
1378 * if a fence register is needed for the object.
1380 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1384 * Previous chips need to be aligned to the size of the smallest
1385 * fence register that can contain the object.
1392 for (i = start; i < obj->size; i <<= 1)
1399 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1401 * @data: GTT mapping ioctl data
1402 * @file_priv: GEM object info
1404 * Simply returns the fake offset to userspace so it can mmap it.
1405 * The mmap call will end up in drm_gem_mmap(), which will set things
1406 * up so we can get faults in the handler above.
1408 * The fault handler will take care of binding the object into the GTT
1409 * (since it may have been evicted to make room for something), allocating
1410 * a fence register, and mapping the appropriate aperture address into
1414 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1415 struct drm_file *file_priv)
1417 struct drm_i915_gem_mmap_gtt *args = data;
1418 struct drm_i915_private *dev_priv = dev->dev_private;
1419 struct drm_gem_object *obj;
1420 struct drm_i915_gem_object *obj_priv;
1423 if (!(dev->driver->driver_features & DRIVER_GEM))
1426 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1430 mutex_lock(&dev->struct_mutex);
1432 obj_priv = obj->driver_private;
1434 if (!obj_priv->mmap_offset) {
1435 ret = i915_gem_create_mmap_offset(obj);
1437 drm_gem_object_unreference(obj);
1438 mutex_unlock(&dev->struct_mutex);
1443 args->offset = obj_priv->mmap_offset;
1446 * Pull it into the GTT so that we have a page list (makes the
1447 * initial fault faster and any subsequent flushing possible).
1449 if (!obj_priv->agp_mem) {
1450 ret = i915_gem_object_bind_to_gtt(obj, 0);
1452 drm_gem_object_unreference(obj);
1453 mutex_unlock(&dev->struct_mutex);
1456 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1459 drm_gem_object_unreference(obj);
1460 mutex_unlock(&dev->struct_mutex);
1466 i915_gem_object_put_pages(struct drm_gem_object *obj)
1468 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1469 int page_count = obj->size / PAGE_SIZE;
1472 BUG_ON(obj_priv->pages_refcount == 0);
1473 BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
1475 if (--obj_priv->pages_refcount != 0)
1478 if (obj_priv->tiling_mode != I915_TILING_NONE)
1479 i915_gem_object_save_bit_17_swizzle(obj);
1481 if (obj_priv->madv == I915_MADV_DONTNEED)
1482 obj_priv->dirty = 0;
1484 for (i = 0; i < page_count; i++) {
1485 if (obj_priv->pages[i] == NULL)
1488 if (obj_priv->dirty)
1489 set_page_dirty(obj_priv->pages[i]);
1491 if (obj_priv->madv == I915_MADV_WILLNEED)
1492 mark_page_accessed(obj_priv->pages[i]);
1494 page_cache_release(obj_priv->pages[i]);
1496 obj_priv->dirty = 0;
1498 drm_free_large(obj_priv->pages);
1499 obj_priv->pages = NULL;
1503 i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
1505 struct drm_device *dev = obj->dev;
1506 drm_i915_private_t *dev_priv = dev->dev_private;
1507 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1509 /* Add a reference if we're newly entering the active list. */
1510 if (!obj_priv->active) {
1511 drm_gem_object_reference(obj);
1512 obj_priv->active = 1;
1514 /* Move from whatever list we were on to the tail of execution. */
1515 spin_lock(&dev_priv->mm.active_list_lock);
1516 list_move_tail(&obj_priv->list,
1517 &dev_priv->mm.active_list);
1518 spin_unlock(&dev_priv->mm.active_list_lock);
1519 obj_priv->last_rendering_seqno = seqno;
1523 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1525 struct drm_device *dev = obj->dev;
1526 drm_i915_private_t *dev_priv = dev->dev_private;
1527 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1529 BUG_ON(!obj_priv->active);
1530 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1531 obj_priv->last_rendering_seqno = 0;
1534 /* Immediately discard the backing storage */
1536 i915_gem_object_truncate(struct drm_gem_object *obj)
1538 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1539 struct inode *inode;
1541 inode = obj->filp->f_path.dentry->d_inode;
1542 if (inode->i_op->truncate)
1543 inode->i_op->truncate (inode);
1545 obj_priv->madv = __I915_MADV_PURGED;
1549 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1551 return obj_priv->madv == I915_MADV_DONTNEED;
1555 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1557 struct drm_device *dev = obj->dev;
1558 drm_i915_private_t *dev_priv = dev->dev_private;
1559 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1561 i915_verify_inactive(dev, __FILE__, __LINE__);
1562 if (obj_priv->pin_count != 0)
1563 list_del_init(&obj_priv->list);
1565 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1567 obj_priv->last_rendering_seqno = 0;
1568 if (obj_priv->active) {
1569 obj_priv->active = 0;
1570 drm_gem_object_unreference(obj);
1572 i915_verify_inactive(dev, __FILE__, __LINE__);
1576 * Creates a new sequence number, emitting a write of it to the status page
1577 * plus an interrupt, which will trigger i915_user_interrupt_handler.
1579 * Must be called with struct_lock held.
1581 * Returned sequence numbers are nonzero on success.
1584 i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1585 uint32_t flush_domains)
1587 drm_i915_private_t *dev_priv = dev->dev_private;
1588 struct drm_i915_file_private *i915_file_priv = NULL;
1589 struct drm_i915_gem_request *request;
1594 if (file_priv != NULL)
1595 i915_file_priv = file_priv->driver_priv;
1597 request = kzalloc(sizeof(*request), GFP_KERNEL);
1598 if (request == NULL)
1601 /* Grab the seqno we're going to make this request be, and bump the
1602 * next (skipping 0 so it can be the reserved no-seqno value).
1604 seqno = dev_priv->mm.next_gem_seqno;
1605 dev_priv->mm.next_gem_seqno++;
1606 if (dev_priv->mm.next_gem_seqno == 0)
1607 dev_priv->mm.next_gem_seqno++;
1610 OUT_RING(MI_STORE_DWORD_INDEX);
1611 OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1614 OUT_RING(MI_USER_INTERRUPT);
1617 DRM_DEBUG("%d\n", seqno);
1619 request->seqno = seqno;
1620 request->emitted_jiffies = jiffies;
1621 was_empty = list_empty(&dev_priv->mm.request_list);
1622 list_add_tail(&request->list, &dev_priv->mm.request_list);
1623 if (i915_file_priv) {
1624 list_add_tail(&request->client_list,
1625 &i915_file_priv->mm.request_list);
1627 INIT_LIST_HEAD(&request->client_list);
1630 /* Associate any objects on the flushing list matching the write
1631 * domain we're flushing with our flush.
1633 if (flush_domains != 0) {
1634 struct drm_i915_gem_object *obj_priv, *next;
1636 list_for_each_entry_safe(obj_priv, next,
1637 &dev_priv->mm.flushing_list, list) {
1638 struct drm_gem_object *obj = obj_priv->obj;
1640 if ((obj->write_domain & flush_domains) ==
1641 obj->write_domain) {
1642 uint32_t old_write_domain = obj->write_domain;
1644 obj->write_domain = 0;
1645 i915_gem_object_move_to_active(obj, seqno);
1647 trace_i915_gem_object_change_domain(obj,
1655 if (!dev_priv->mm.suspended) {
1656 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1658 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1664 * Command execution barrier
1666 * Ensures that all commands in the ring are finished
1667 * before signalling the CPU
1670 i915_retire_commands(struct drm_device *dev)
1672 drm_i915_private_t *dev_priv = dev->dev_private;
1673 uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1674 uint32_t flush_domains = 0;
1677 /* The sampler always gets flushed on i965 (sigh) */
1679 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1682 OUT_RING(0); /* noop */
1684 return flush_domains;
1688 * Moves buffers associated only with the given active seqno from the active
1689 * to inactive list, potentially freeing them.
1692 i915_gem_retire_request(struct drm_device *dev,
1693 struct drm_i915_gem_request *request)
1695 drm_i915_private_t *dev_priv = dev->dev_private;
1697 trace_i915_gem_request_retire(dev, request->seqno);
1699 /* Move any buffers on the active list that are no longer referenced
1700 * by the ringbuffer to the flushing/inactive lists as appropriate.
1702 spin_lock(&dev_priv->mm.active_list_lock);
1703 while (!list_empty(&dev_priv->mm.active_list)) {
1704 struct drm_gem_object *obj;
1705 struct drm_i915_gem_object *obj_priv;
1707 obj_priv = list_first_entry(&dev_priv->mm.active_list,
1708 struct drm_i915_gem_object,
1710 obj = obj_priv->obj;
1712 /* If the seqno being retired doesn't match the oldest in the
1713 * list, then the oldest in the list must still be newer than
1716 if (obj_priv->last_rendering_seqno != request->seqno)
1720 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1721 __func__, request->seqno, obj);
1724 if (obj->write_domain != 0)
1725 i915_gem_object_move_to_flushing(obj);
1727 /* Take a reference on the object so it won't be
1728 * freed while the spinlock is held. The list
1729 * protection for this spinlock is safe when breaking
1730 * the lock like this since the next thing we do
1731 * is just get the head of the list again.
1733 drm_gem_object_reference(obj);
1734 i915_gem_object_move_to_inactive(obj);
1735 spin_unlock(&dev_priv->mm.active_list_lock);
1736 drm_gem_object_unreference(obj);
1737 spin_lock(&dev_priv->mm.active_list_lock);
1741 spin_unlock(&dev_priv->mm.active_list_lock);
1745 * Returns true if seq1 is later than seq2.
1748 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1750 return (int32_t)(seq1 - seq2) >= 0;
1754 i915_get_gem_seqno(struct drm_device *dev)
1756 drm_i915_private_t *dev_priv = dev->dev_private;
1758 return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
1762 * This function clears the request list as sequence numbers are passed.
1765 i915_gem_retire_requests(struct drm_device *dev)
1767 drm_i915_private_t *dev_priv = dev->dev_private;
1770 if (!dev_priv->hw_status_page)
1773 seqno = i915_get_gem_seqno(dev);
1775 while (!list_empty(&dev_priv->mm.request_list)) {
1776 struct drm_i915_gem_request *request;
1777 uint32_t retiring_seqno;
1779 request = list_first_entry(&dev_priv->mm.request_list,
1780 struct drm_i915_gem_request,
1782 retiring_seqno = request->seqno;
1784 if (i915_seqno_passed(seqno, retiring_seqno) ||
1785 atomic_read(&dev_priv->mm.wedged)) {
1786 i915_gem_retire_request(dev, request);
1788 list_del(&request->list);
1789 list_del(&request->client_list);
1797 i915_gem_retire_work_handler(struct work_struct *work)
1799 drm_i915_private_t *dev_priv;
1800 struct drm_device *dev;
1802 dev_priv = container_of(work, drm_i915_private_t,
1803 mm.retire_work.work);
1804 dev = dev_priv->dev;
1806 mutex_lock(&dev->struct_mutex);
1807 i915_gem_retire_requests(dev);
1808 if (!dev_priv->mm.suspended &&
1809 !list_empty(&dev_priv->mm.request_list))
1810 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1811 mutex_unlock(&dev->struct_mutex);
1815 * Waits for a sequence number to be signaled, and cleans up the
1816 * request and object lists appropriately for that event.
1819 i915_wait_request(struct drm_device *dev, uint32_t seqno)
1821 drm_i915_private_t *dev_priv = dev->dev_private;
1827 if (atomic_read(&dev_priv->mm.wedged))
1830 if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
1832 ier = I915_READ(DEIER) | I915_READ(GTIER);
1834 ier = I915_READ(IER);
1836 DRM_ERROR("something (likely vbetool) disabled "
1837 "interrupts, re-enabling\n");
1838 i915_driver_irq_preinstall(dev);
1839 i915_driver_irq_postinstall(dev);
1842 trace_i915_gem_request_wait_begin(dev, seqno);
1844 dev_priv->mm.waiting_gem_seqno = seqno;
1845 i915_user_irq_get(dev);
1846 ret = wait_event_interruptible(dev_priv->irq_queue,
1847 i915_seqno_passed(i915_get_gem_seqno(dev),
1849 atomic_read(&dev_priv->mm.wedged));
1850 i915_user_irq_put(dev);
1851 dev_priv->mm.waiting_gem_seqno = 0;
1853 trace_i915_gem_request_wait_end(dev, seqno);
1855 if (atomic_read(&dev_priv->mm.wedged))
1858 if (ret && ret != -ERESTARTSYS)
1859 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1860 __func__, ret, seqno, i915_get_gem_seqno(dev));
1862 /* Directly dispatch request retiring. While we have the work queue
1863 * to handle this, the waiter on a request often wants an associated
1864 * buffer to have made it to the inactive list, and we would need
1865 * a separate wait queue to handle that.
1868 i915_gem_retire_requests(dev);
1874 i915_gem_flush(struct drm_device *dev,
1875 uint32_t invalidate_domains,
1876 uint32_t flush_domains)
1878 drm_i915_private_t *dev_priv = dev->dev_private;
1883 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
1884 invalidate_domains, flush_domains);
1886 trace_i915_gem_request_flush(dev, dev_priv->mm.next_gem_seqno,
1887 invalidate_domains, flush_domains);
1889 if (flush_domains & I915_GEM_DOMAIN_CPU)
1890 drm_agp_chipset_flush(dev);
1892 if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
1894 * read/write caches:
1896 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1897 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
1898 * also flushed at 2d versus 3d pipeline switches.
1902 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1903 * MI_READ_FLUSH is set, and is always flushed on 965.
1905 * I915_GEM_DOMAIN_COMMAND may not exist?
1907 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1908 * invalidated when MI_EXE_FLUSH is set.
1910 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1911 * invalidated with every MI_FLUSH.
1915 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1916 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1917 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1918 * are flushed at any MI_FLUSH.
1921 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1922 if ((invalidate_domains|flush_domains) &
1923 I915_GEM_DOMAIN_RENDER)
1924 cmd &= ~MI_NO_WRITE_FLUSH;
1925 if (!IS_I965G(dev)) {
1927 * On the 965, the sampler cache always gets flushed
1928 * and this bit is reserved.
1930 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
1931 cmd |= MI_READ_FLUSH;
1933 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
1934 cmd |= MI_EXE_FLUSH;
1937 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
1941 OUT_RING(0); /* noop */
1947 * Ensures that all rendering to the object has completed and the object is
1948 * safe to unbind from the GTT or access from the CPU.
1951 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1953 struct drm_device *dev = obj->dev;
1954 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1957 /* This function only exists to support waiting for existing rendering,
1958 * not for emitting required flushes.
1960 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
1962 /* If there is rendering queued on the buffer being evicted, wait for
1965 if (obj_priv->active) {
1967 DRM_INFO("%s: object %p wait for seqno %08x\n",
1968 __func__, obj, obj_priv->last_rendering_seqno);
1970 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
1979 * Unbinds an object from the GTT aperture.
1982 i915_gem_object_unbind(struct drm_gem_object *obj)
1984 struct drm_device *dev = obj->dev;
1985 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1989 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1990 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1992 if (obj_priv->gtt_space == NULL)
1995 if (obj_priv->pin_count != 0) {
1996 DRM_ERROR("Attempting to unbind pinned buffer\n");
2000 /* blow away mappings if mapped through GTT */
2001 i915_gem_release_mmap(obj);
2003 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
2004 i915_gem_clear_fence_reg(obj);
2006 /* Move the object to the CPU domain to ensure that
2007 * any possible CPU writes while it's not in the GTT
2008 * are flushed when we go to remap it. This will
2009 * also ensure that all pending GPU writes are finished
2012 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2014 if (ret != -ERESTARTSYS)
2015 DRM_ERROR("set_domain failed: %d\n", ret);
2019 BUG_ON(obj_priv->active);
2021 if (obj_priv->agp_mem != NULL) {
2022 drm_unbind_agp(obj_priv->agp_mem);
2023 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
2024 obj_priv->agp_mem = NULL;
2027 i915_gem_object_put_pages(obj);
2028 BUG_ON(obj_priv->pages_refcount);
2030 if (obj_priv->gtt_space) {
2031 atomic_dec(&dev->gtt_count);
2032 atomic_sub(obj->size, &dev->gtt_memory);
2034 drm_mm_put_block(obj_priv->gtt_space);
2035 obj_priv->gtt_space = NULL;
2038 /* Remove ourselves from the LRU list if present. */
2039 if (!list_empty(&obj_priv->list))
2040 list_del_init(&obj_priv->list);
2042 if (i915_gem_object_is_purgeable(obj_priv))
2043 i915_gem_object_truncate(obj);
2045 trace_i915_gem_object_unbind(obj);
2050 static struct drm_gem_object *
2051 i915_gem_find_inactive_object(struct drm_device *dev, int min_size)
2053 drm_i915_private_t *dev_priv = dev->dev_private;
2054 struct drm_i915_gem_object *obj_priv;
2055 struct drm_gem_object *best = NULL;
2056 struct drm_gem_object *first = NULL;
2058 /* Try to find the smallest clean object */
2059 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
2060 struct drm_gem_object *obj = obj_priv->obj;
2061 if (obj->size >= min_size) {
2062 if ((!obj_priv->dirty ||
2063 i915_gem_object_is_purgeable(obj_priv)) &&
2064 (!best || obj->size < best->size)) {
2066 if (best->size == min_size)
2074 return best ? best : first;
2078 i915_gem_evict_everything(struct drm_device *dev)
2080 drm_i915_private_t *dev_priv = dev->dev_private;
2085 spin_lock(&dev_priv->mm.active_list_lock);
2086 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2087 list_empty(&dev_priv->mm.flushing_list) &&
2088 list_empty(&dev_priv->mm.active_list));
2089 spin_unlock(&dev_priv->mm.active_list_lock);
2094 /* Flush everything (on to the inactive lists) and evict */
2095 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2096 seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
2100 ret = i915_wait_request(dev, seqno);
2104 ret = i915_gem_evict_from_inactive_list(dev);
2108 spin_lock(&dev_priv->mm.active_list_lock);
2109 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2110 list_empty(&dev_priv->mm.flushing_list) &&
2111 list_empty(&dev_priv->mm.active_list));
2112 spin_unlock(&dev_priv->mm.active_list_lock);
2113 BUG_ON(!lists_empty);
2119 i915_gem_evict_something(struct drm_device *dev, int min_size)
2121 drm_i915_private_t *dev_priv = dev->dev_private;
2122 struct drm_gem_object *obj;
2126 i915_gem_retire_requests(dev);
2128 /* If there's an inactive buffer available now, grab it
2131 obj = i915_gem_find_inactive_object(dev, min_size);
2133 struct drm_i915_gem_object *obj_priv;
2136 DRM_INFO("%s: evicting %p\n", __func__, obj);
2138 obj_priv = obj->driver_private;
2139 BUG_ON(obj_priv->pin_count != 0);
2140 BUG_ON(obj_priv->active);
2142 /* Wait on the rendering and unbind the buffer. */
2143 return i915_gem_object_unbind(obj);
2146 /* If we didn't get anything, but the ring is still processing
2147 * things, wait for the next to finish and hopefully leave us
2148 * a buffer to evict.
2150 if (!list_empty(&dev_priv->mm.request_list)) {
2151 struct drm_i915_gem_request *request;
2153 request = list_first_entry(&dev_priv->mm.request_list,
2154 struct drm_i915_gem_request,
2157 ret = i915_wait_request(dev, request->seqno);
2164 /* If we didn't have anything on the request list but there
2165 * are buffers awaiting a flush, emit one and try again.
2166 * When we wait on it, those buffers waiting for that flush
2167 * will get moved to inactive.
2169 if (!list_empty(&dev_priv->mm.flushing_list)) {
2170 struct drm_i915_gem_object *obj_priv;
2172 /* Find an object that we can immediately reuse */
2173 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
2174 obj = obj_priv->obj;
2175 if (obj->size >= min_size)
2187 seqno = i915_add_request(dev, NULL, obj->write_domain);
2191 ret = i915_wait_request(dev, seqno);
2199 /* If we didn't do any of the above, there's no single buffer
2200 * large enough to swap out for the new one, so just evict
2201 * everything and start again. (This should be rare.)
2203 if (!list_empty (&dev_priv->mm.inactive_list))
2204 return i915_gem_evict_from_inactive_list(dev);
2206 return i915_gem_evict_everything(dev);
2211 i915_gem_object_get_pages(struct drm_gem_object *obj)
2213 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2215 struct address_space *mapping;
2216 struct inode *inode;
2220 if (obj_priv->pages_refcount++ != 0)
2223 /* Get the list of pages out of our struct file. They'll be pinned
2224 * at this point until we release them.
2226 page_count = obj->size / PAGE_SIZE;
2227 BUG_ON(obj_priv->pages != NULL);
2228 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
2229 if (obj_priv->pages == NULL) {
2230 obj_priv->pages_refcount--;
2234 inode = obj->filp->f_path.dentry->d_inode;
2235 mapping = inode->i_mapping;
2236 for (i = 0; i < page_count; i++) {
2237 page = read_mapping_page(mapping, i, NULL);
2239 ret = PTR_ERR(page);
2240 i915_gem_object_put_pages(obj);
2243 obj_priv->pages[i] = page;
2246 if (obj_priv->tiling_mode != I915_TILING_NONE)
2247 i915_gem_object_do_bit_17_swizzle(obj);
2252 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2254 struct drm_gem_object *obj = reg->obj;
2255 struct drm_device *dev = obj->dev;
2256 drm_i915_private_t *dev_priv = dev->dev_private;
2257 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2258 int regnum = obj_priv->fence_reg;
2261 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2263 val |= obj_priv->gtt_offset & 0xfffff000;
2264 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2265 if (obj_priv->tiling_mode == I915_TILING_Y)
2266 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2267 val |= I965_FENCE_REG_VALID;
2269 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2272 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2274 struct drm_gem_object *obj = reg->obj;
2275 struct drm_device *dev = obj->dev;
2276 drm_i915_private_t *dev_priv = dev->dev_private;
2277 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2278 int regnum = obj_priv->fence_reg;
2280 uint32_t fence_reg, val;
2283 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2284 (obj_priv->gtt_offset & (obj->size - 1))) {
2285 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2286 __func__, obj_priv->gtt_offset, obj->size);
2290 if (obj_priv->tiling_mode == I915_TILING_Y &&
2291 HAS_128_BYTE_Y_TILING(dev))
2296 /* Note: pitch better be a power of two tile widths */
2297 pitch_val = obj_priv->stride / tile_width;
2298 pitch_val = ffs(pitch_val) - 1;
2300 val = obj_priv->gtt_offset;
2301 if (obj_priv->tiling_mode == I915_TILING_Y)
2302 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2303 val |= I915_FENCE_SIZE_BITS(obj->size);
2304 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2305 val |= I830_FENCE_REG_VALID;
2308 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2310 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2311 I915_WRITE(fence_reg, val);
2314 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2316 struct drm_gem_object *obj = reg->obj;
2317 struct drm_device *dev = obj->dev;
2318 drm_i915_private_t *dev_priv = dev->dev_private;
2319 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2320 int regnum = obj_priv->fence_reg;
2323 uint32_t fence_size_bits;
2325 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
2326 (obj_priv->gtt_offset & (obj->size - 1))) {
2327 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2328 __func__, obj_priv->gtt_offset);
2332 pitch_val = obj_priv->stride / 128;
2333 pitch_val = ffs(pitch_val) - 1;
2334 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2336 val = obj_priv->gtt_offset;
2337 if (obj_priv->tiling_mode == I915_TILING_Y)
2338 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2339 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2340 WARN_ON(fence_size_bits & ~0x00000f00);
2341 val |= fence_size_bits;
2342 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2343 val |= I830_FENCE_REG_VALID;
2345 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
2349 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2350 * @obj: object to map through a fence reg
2352 * When mapping objects through the GTT, userspace wants to be able to write
2353 * to them without having to worry about swizzling if the object is tiled.
2355 * This function walks the fence regs looking for a free one for @obj,
2356 * stealing one if it can't find any.
2358 * It then sets up the reg based on the object's properties: address, pitch
2359 * and tiling format.
2362 i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
2364 struct drm_device *dev = obj->dev;
2365 struct drm_i915_private *dev_priv = dev->dev_private;
2366 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2367 struct drm_i915_fence_reg *reg = NULL;
2368 struct drm_i915_gem_object *old_obj_priv = NULL;
2371 /* Just update our place in the LRU if our fence is getting used. */
2372 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2373 list_move_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2377 switch (obj_priv->tiling_mode) {
2378 case I915_TILING_NONE:
2379 WARN(1, "allocating a fence for non-tiled object?\n");
2382 if (!obj_priv->stride)
2384 WARN((obj_priv->stride & (512 - 1)),
2385 "object 0x%08x is X tiled but has non-512B pitch\n",
2386 obj_priv->gtt_offset);
2389 if (!obj_priv->stride)
2391 WARN((obj_priv->stride & (128 - 1)),
2392 "object 0x%08x is Y tiled but has non-128B pitch\n",
2393 obj_priv->gtt_offset);
2397 /* First try to find a free reg */
2399 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2400 reg = &dev_priv->fence_regs[i];
2404 old_obj_priv = reg->obj->driver_private;
2405 if (!old_obj_priv->pin_count)
2409 /* None available, try to steal one or wait for a user to finish */
2410 if (i == dev_priv->num_fence_regs) {
2411 struct drm_gem_object *old_obj = NULL;
2416 list_for_each_entry(old_obj_priv, &dev_priv->mm.fence_list,
2418 old_obj = old_obj_priv->obj;
2420 if (old_obj_priv->pin_count)
2423 /* Take a reference, as otherwise the wait_rendering
2424 * below may cause the object to get freed out from
2427 drm_gem_object_reference(old_obj);
2429 /* i915 uses fences for GPU access to tiled buffers */
2430 if (IS_I965G(dev) || !old_obj_priv->active)
2433 /* This brings the object to the head of the LRU if it
2434 * had been written to. The only way this should
2435 * result in us waiting longer than the expected
2436 * optimal amount of time is if there was a
2437 * fence-using buffer later that was read-only.
2439 i915_gem_object_flush_gpu_write_domain(old_obj);
2440 ret = i915_gem_object_wait_rendering(old_obj);
2442 drm_gem_object_unreference(old_obj);
2450 * Zap this virtual mapping so we can set up a fence again
2451 * for this object next time we need it.
2453 i915_gem_release_mmap(old_obj);
2455 i = old_obj_priv->fence_reg;
2456 reg = &dev_priv->fence_regs[i];
2458 old_obj_priv->fence_reg = I915_FENCE_REG_NONE;
2459 list_del_init(&old_obj_priv->fence_list);
2461 drm_gem_object_unreference(old_obj);
2464 obj_priv->fence_reg = i;
2465 list_add_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2470 i965_write_fence_reg(reg);
2471 else if (IS_I9XX(dev))
2472 i915_write_fence_reg(reg);
2474 i830_write_fence_reg(reg);
2476 trace_i915_gem_object_get_fence(obj, i, obj_priv->tiling_mode);
2482 * i915_gem_clear_fence_reg - clear out fence register info
2483 * @obj: object to clear
2485 * Zeroes out the fence register itself and clears out the associated
2486 * data structures in dev_priv and obj_priv.
2489 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2491 struct drm_device *dev = obj->dev;
2492 drm_i915_private_t *dev_priv = dev->dev_private;
2493 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2496 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
2500 if (obj_priv->fence_reg < 8)
2501 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2503 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2506 I915_WRITE(fence_reg, 0);
2509 dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL;
2510 obj_priv->fence_reg = I915_FENCE_REG_NONE;
2511 list_del_init(&obj_priv->fence_list);
2515 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2516 * to the buffer to finish, and then resets the fence register.
2517 * @obj: tiled object holding a fence register.
2519 * Zeroes out the fence register itself and clears out the associated
2520 * data structures in dev_priv and obj_priv.
2523 i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2525 struct drm_device *dev = obj->dev;
2526 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2528 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2531 /* On the i915, GPU access to tiled buffers is via a fence,
2532 * therefore we must wait for any outstanding access to complete
2533 * before clearing the fence.
2535 if (!IS_I965G(dev)) {
2538 i915_gem_object_flush_gpu_write_domain(obj);
2539 i915_gem_object_flush_gtt_write_domain(obj);
2540 ret = i915_gem_object_wait_rendering(obj);
2545 i915_gem_clear_fence_reg (obj);
2551 * Finds free space in the GTT aperture and binds the object there.
2554 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2556 struct drm_device *dev = obj->dev;
2557 drm_i915_private_t *dev_priv = dev->dev_private;
2558 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2559 struct drm_mm_node *free_space;
2560 bool retry_alloc = false;
2563 if (dev_priv->mm.suspended)
2566 if (obj_priv->madv != I915_MADV_WILLNEED) {
2567 DRM_ERROR("Attempting to bind a purgeable object\n");
2572 alignment = i915_gem_get_gtt_alignment(obj);
2573 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
2574 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2579 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2580 obj->size, alignment, 0);
2581 if (free_space != NULL) {
2582 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2584 if (obj_priv->gtt_space != NULL) {
2585 obj_priv->gtt_space->private = obj;
2586 obj_priv->gtt_offset = obj_priv->gtt_space->start;
2589 if (obj_priv->gtt_space == NULL) {
2590 /* If the gtt is empty and we're still having trouble
2591 * fitting our object in, we're out of memory.
2594 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2596 ret = i915_gem_evict_something(dev, obj->size);
2604 DRM_INFO("Binding object of size %zd at 0x%08x\n",
2605 obj->size, obj_priv->gtt_offset);
2608 i915_gem_object_set_page_gfp_mask (obj,
2609 i915_gem_object_get_page_gfp_mask (obj) & ~__GFP_NORETRY);
2611 ret = i915_gem_object_get_pages(obj);
2613 i915_gem_object_set_page_gfp_mask (obj,
2614 i915_gem_object_get_page_gfp_mask (obj) | __GFP_NORETRY);
2617 drm_mm_put_block(obj_priv->gtt_space);
2618 obj_priv->gtt_space = NULL;
2620 if (ret == -ENOMEM) {
2621 /* first try to clear up some space from the GTT */
2622 ret = i915_gem_evict_something(dev, obj->size);
2624 /* now try to shrink everyone else */
2625 if (! retry_alloc) {
2639 /* Create an AGP memory structure pointing at our pages, and bind it
2642 obj_priv->agp_mem = drm_agp_bind_pages(dev,
2644 obj->size >> PAGE_SHIFT,
2645 obj_priv->gtt_offset,
2646 obj_priv->agp_type);
2647 if (obj_priv->agp_mem == NULL) {
2648 i915_gem_object_put_pages(obj);
2649 drm_mm_put_block(obj_priv->gtt_space);
2650 obj_priv->gtt_space = NULL;
2652 ret = i915_gem_evict_something(dev, obj->size);
2658 atomic_inc(&dev->gtt_count);
2659 atomic_add(obj->size, &dev->gtt_memory);
2661 /* Assert that the object is not currently in any GPU domain. As it
2662 * wasn't in the GTT, there shouldn't be any way it could have been in
2665 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2666 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
2668 trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2674 i915_gem_clflush_object(struct drm_gem_object *obj)
2676 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2678 /* If we don't have a page list set up, then we're not pinned
2679 * to GPU, and we can ignore the cache flush because it'll happen
2680 * again at bind time.
2682 if (obj_priv->pages == NULL)
2685 trace_i915_gem_object_clflush(obj);
2687 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2690 /** Flushes any GPU write domain for the object if it's dirty. */
2692 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2694 struct drm_device *dev = obj->dev;
2696 uint32_t old_write_domain;
2698 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2701 /* Queue the GPU write cache flushing we need. */
2702 old_write_domain = obj->write_domain;
2703 i915_gem_flush(dev, 0, obj->write_domain);
2704 seqno = i915_add_request(dev, NULL, obj->write_domain);
2705 obj->write_domain = 0;
2706 i915_gem_object_move_to_active(obj, seqno);
2708 trace_i915_gem_object_change_domain(obj,
2713 /** Flushes the GTT write domain for the object if it's dirty. */
2715 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2717 uint32_t old_write_domain;
2719 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2722 /* No actual flushing is required for the GTT write domain. Writes
2723 * to it immediately go to main memory as far as we know, so there's
2724 * no chipset flush. It also doesn't land in render cache.
2726 old_write_domain = obj->write_domain;
2727 obj->write_domain = 0;
2729 trace_i915_gem_object_change_domain(obj,
2734 /** Flushes the CPU write domain for the object if it's dirty. */
2736 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2738 struct drm_device *dev = obj->dev;
2739 uint32_t old_write_domain;
2741 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2744 i915_gem_clflush_object(obj);
2745 drm_agp_chipset_flush(dev);
2746 old_write_domain = obj->write_domain;
2747 obj->write_domain = 0;
2749 trace_i915_gem_object_change_domain(obj,
2755 * Moves a single object to the GTT read, and possibly write domain.
2757 * This function returns when the move is complete, including waiting on
2761 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2763 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2764 uint32_t old_write_domain, old_read_domains;
2767 /* Not valid to be called on unbound objects. */
2768 if (obj_priv->gtt_space == NULL)
2771 i915_gem_object_flush_gpu_write_domain(obj);
2772 /* Wait on any GPU rendering and flushing to occur. */
2773 ret = i915_gem_object_wait_rendering(obj);
2777 old_write_domain = obj->write_domain;
2778 old_read_domains = obj->read_domains;
2780 /* If we're writing through the GTT domain, then CPU and GPU caches
2781 * will need to be invalidated at next use.
2784 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2786 i915_gem_object_flush_cpu_write_domain(obj);
2788 /* It should now be out of any other write domains, and we can update
2789 * the domain values for our changes.
2791 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2792 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2794 obj->write_domain = I915_GEM_DOMAIN_GTT;
2795 obj_priv->dirty = 1;
2798 trace_i915_gem_object_change_domain(obj,
2806 * Moves a single object to the CPU read, and possibly write domain.
2808 * This function returns when the move is complete, including waiting on
2812 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2814 uint32_t old_write_domain, old_read_domains;
2817 i915_gem_object_flush_gpu_write_domain(obj);
2818 /* Wait on any GPU rendering and flushing to occur. */
2819 ret = i915_gem_object_wait_rendering(obj);
2823 i915_gem_object_flush_gtt_write_domain(obj);
2825 /* If we have a partially-valid cache of the object in the CPU,
2826 * finish invalidating it and free the per-page flags.
2828 i915_gem_object_set_to_full_cpu_read_domain(obj);
2830 old_write_domain = obj->write_domain;
2831 old_read_domains = obj->read_domains;
2833 /* Flush the CPU cache if it's still invalid. */
2834 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2835 i915_gem_clflush_object(obj);
2837 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2840 /* It should now be out of any other write domains, and we can update
2841 * the domain values for our changes.
2843 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2845 /* If we're writing through the CPU, then the GPU read domains will
2846 * need to be invalidated at next use.
2849 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2850 obj->write_domain = I915_GEM_DOMAIN_CPU;
2853 trace_i915_gem_object_change_domain(obj,
2861 * Set the next domain for the specified object. This
2862 * may not actually perform the necessary flushing/invaliding though,
2863 * as that may want to be batched with other set_domain operations
2865 * This is (we hope) the only really tricky part of gem. The goal
2866 * is fairly simple -- track which caches hold bits of the object
2867 * and make sure they remain coherent. A few concrete examples may
2868 * help to explain how it works. For shorthand, we use the notation
2869 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2870 * a pair of read and write domain masks.
2872 * Case 1: the batch buffer
2878 * 5. Unmapped from GTT
2881 * Let's take these a step at a time
2884 * Pages allocated from the kernel may still have
2885 * cache contents, so we set them to (CPU, CPU) always.
2886 * 2. Written by CPU (using pwrite)
2887 * The pwrite function calls set_domain (CPU, CPU) and
2888 * this function does nothing (as nothing changes)
2890 * This function asserts that the object is not
2891 * currently in any GPU-based read or write domains
2893 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2894 * As write_domain is zero, this function adds in the
2895 * current read domains (CPU+COMMAND, 0).
2896 * flush_domains is set to CPU.
2897 * invalidate_domains is set to COMMAND
2898 * clflush is run to get data out of the CPU caches
2899 * then i915_dev_set_domain calls i915_gem_flush to
2900 * emit an MI_FLUSH and drm_agp_chipset_flush
2901 * 5. Unmapped from GTT
2902 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2903 * flush_domains and invalidate_domains end up both zero
2904 * so no flushing/invalidating happens
2908 * Case 2: The shared render buffer
2912 * 3. Read/written by GPU
2913 * 4. set_domain to (CPU,CPU)
2914 * 5. Read/written by CPU
2915 * 6. Read/written by GPU
2918 * Same as last example, (CPU, CPU)
2920 * Nothing changes (assertions find that it is not in the GPU)
2921 * 3. Read/written by GPU
2922 * execbuffer calls set_domain (RENDER, RENDER)
2923 * flush_domains gets CPU
2924 * invalidate_domains gets GPU
2926 * MI_FLUSH and drm_agp_chipset_flush
2927 * 4. set_domain (CPU, CPU)
2928 * flush_domains gets GPU
2929 * invalidate_domains gets CPU
2930 * wait_rendering (obj) to make sure all drawing is complete.
2931 * This will include an MI_FLUSH to get the data from GPU
2933 * clflush (obj) to invalidate the CPU cache
2934 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
2935 * 5. Read/written by CPU
2936 * cache lines are loaded and dirtied
2937 * 6. Read written by GPU
2938 * Same as last GPU access
2940 * Case 3: The constant buffer
2945 * 4. Updated (written) by CPU again
2954 * flush_domains = CPU
2955 * invalidate_domains = RENDER
2958 * drm_agp_chipset_flush
2959 * 4. Updated (written) by CPU again
2961 * flush_domains = 0 (no previous write domain)
2962 * invalidate_domains = 0 (no new read domains)
2965 * flush_domains = CPU
2966 * invalidate_domains = RENDER
2969 * drm_agp_chipset_flush
2972 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
2974 struct drm_device *dev = obj->dev;
2975 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2976 uint32_t invalidate_domains = 0;
2977 uint32_t flush_domains = 0;
2978 uint32_t old_read_domains;
2980 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
2981 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
2983 intel_mark_busy(dev, obj);
2986 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2988 obj->read_domains, obj->pending_read_domains,
2989 obj->write_domain, obj->pending_write_domain);
2992 * If the object isn't moving to a new write domain,
2993 * let the object stay in multiple read domains
2995 if (obj->pending_write_domain == 0)
2996 obj->pending_read_domains |= obj->read_domains;
2998 obj_priv->dirty = 1;
3001 * Flush the current write domain if
3002 * the new read domains don't match. Invalidate
3003 * any read domains which differ from the old
3006 if (obj->write_domain &&
3007 obj->write_domain != obj->pending_read_domains) {
3008 flush_domains |= obj->write_domain;
3009 invalidate_domains |=
3010 obj->pending_read_domains & ~obj->write_domain;
3013 * Invalidate any read caches which may have
3014 * stale data. That is, any new read domains.
3016 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
3017 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
3019 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3020 __func__, flush_domains, invalidate_domains);
3022 i915_gem_clflush_object(obj);
3025 old_read_domains = obj->read_domains;
3027 /* The actual obj->write_domain will be updated with
3028 * pending_write_domain after we emit the accumulated flush for all
3029 * of our domain changes in execbuffers (which clears objects'
3030 * write_domains). So if we have a current write domain that we
3031 * aren't changing, set pending_write_domain to that.
3033 if (flush_domains == 0 && obj->pending_write_domain == 0)
3034 obj->pending_write_domain = obj->write_domain;
3035 obj->read_domains = obj->pending_read_domains;
3037 dev->invalidate_domains |= invalidate_domains;
3038 dev->flush_domains |= flush_domains;
3040 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3042 obj->read_domains, obj->write_domain,
3043 dev->invalidate_domains, dev->flush_domains);
3046 trace_i915_gem_object_change_domain(obj,
3052 * Moves the object from a partially CPU read to a full one.
3054 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3055 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3058 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
3060 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3062 if (!obj_priv->page_cpu_valid)
3065 /* If we're partially in the CPU read domain, finish moving it in.
3067 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3070 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3071 if (obj_priv->page_cpu_valid[i])
3073 drm_clflush_pages(obj_priv->pages + i, 1);
3077 /* Free the page_cpu_valid mappings which are now stale, whether
3078 * or not we've got I915_GEM_DOMAIN_CPU.
3080 kfree(obj_priv->page_cpu_valid);
3081 obj_priv->page_cpu_valid = NULL;
3085 * Set the CPU read domain on a range of the object.
3087 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3088 * not entirely valid. The page_cpu_valid member of the object flags which
3089 * pages have been flushed, and will be respected by
3090 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3091 * of the whole object.
3093 * This function returns when the move is complete, including waiting on
3097 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3098 uint64_t offset, uint64_t size)
3100 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3101 uint32_t old_read_domains;
3104 if (offset == 0 && size == obj->size)
3105 return i915_gem_object_set_to_cpu_domain(obj, 0);
3107 i915_gem_object_flush_gpu_write_domain(obj);
3108 /* Wait on any GPU rendering and flushing to occur. */
3109 ret = i915_gem_object_wait_rendering(obj);
3112 i915_gem_object_flush_gtt_write_domain(obj);
3114 /* If we're already fully in the CPU read domain, we're done. */
3115 if (obj_priv->page_cpu_valid == NULL &&
3116 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3119 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3120 * newly adding I915_GEM_DOMAIN_CPU
3122 if (obj_priv->page_cpu_valid == NULL) {
3123 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3125 if (obj_priv->page_cpu_valid == NULL)
3127 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3128 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
3130 /* Flush the cache on any pages that are still invalid from the CPU's
3133 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3135 if (obj_priv->page_cpu_valid[i])
3138 drm_clflush_pages(obj_priv->pages + i, 1);
3140 obj_priv->page_cpu_valid[i] = 1;
3143 /* It should now be out of any other write domains, and we can update
3144 * the domain values for our changes.
3146 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3148 old_read_domains = obj->read_domains;
3149 obj->read_domains |= I915_GEM_DOMAIN_CPU;
3151 trace_i915_gem_object_change_domain(obj,
3159 * Pin an object to the GTT and evaluate the relocations landing in it.
3162 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3163 struct drm_file *file_priv,
3164 struct drm_i915_gem_exec_object *entry,
3165 struct drm_i915_gem_relocation_entry *relocs)
3167 struct drm_device *dev = obj->dev;
3168 drm_i915_private_t *dev_priv = dev->dev_private;
3169 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3171 void __iomem *reloc_page;
3173 /* Choose the GTT offset for our buffer and put it there. */
3174 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3178 entry->offset = obj_priv->gtt_offset;
3180 /* Apply the relocations, using the GTT aperture to avoid cache
3181 * flushing requirements.
3183 for (i = 0; i < entry->relocation_count; i++) {
3184 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
3185 struct drm_gem_object *target_obj;
3186 struct drm_i915_gem_object *target_obj_priv;
3187 uint32_t reloc_val, reloc_offset;
3188 uint32_t __iomem *reloc_entry;
3190 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
3191 reloc->target_handle);
3192 if (target_obj == NULL) {
3193 i915_gem_object_unpin(obj);
3196 target_obj_priv = target_obj->driver_private;
3199 DRM_INFO("%s: obj %p offset %08x target %d "
3200 "read %08x write %08x gtt %08x "
3201 "presumed %08x delta %08x\n",
3204 (int) reloc->offset,
3205 (int) reloc->target_handle,
3206 (int) reloc->read_domains,
3207 (int) reloc->write_domain,
3208 (int) target_obj_priv->gtt_offset,
3209 (int) reloc->presumed_offset,
3213 /* The target buffer should have appeared before us in the
3214 * exec_object list, so it should have a GTT space bound by now.
3216 if (target_obj_priv->gtt_space == NULL) {
3217 DRM_ERROR("No GTT space found for object %d\n",
3218 reloc->target_handle);
3219 drm_gem_object_unreference(target_obj);
3220 i915_gem_object_unpin(obj);
3224 /* Validate that the target is in a valid r/w GPU domain */
3225 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3226 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
3227 DRM_ERROR("reloc with read/write CPU domains: "
3228 "obj %p target %d offset %d "
3229 "read %08x write %08x",
3230 obj, reloc->target_handle,
3231 (int) reloc->offset,
3232 reloc->read_domains,
3233 reloc->write_domain);
3234 drm_gem_object_unreference(target_obj);
3235 i915_gem_object_unpin(obj);
3238 if (reloc->write_domain && target_obj->pending_write_domain &&
3239 reloc->write_domain != target_obj->pending_write_domain) {
3240 DRM_ERROR("Write domain conflict: "
3241 "obj %p target %d offset %d "
3242 "new %08x old %08x\n",
3243 obj, reloc->target_handle,
3244 (int) reloc->offset,
3245 reloc->write_domain,
3246 target_obj->pending_write_domain);
3247 drm_gem_object_unreference(target_obj);
3248 i915_gem_object_unpin(obj);
3252 target_obj->pending_read_domains |= reloc->read_domains;
3253 target_obj->pending_write_domain |= reloc->write_domain;
3255 /* If the relocation already has the right value in it, no
3256 * more work needs to be done.
3258 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
3259 drm_gem_object_unreference(target_obj);
3263 /* Check that the relocation address is valid... */
3264 if (reloc->offset > obj->size - 4) {
3265 DRM_ERROR("Relocation beyond object bounds: "
3266 "obj %p target %d offset %d size %d.\n",
3267 obj, reloc->target_handle,
3268 (int) reloc->offset, (int) obj->size);
3269 drm_gem_object_unreference(target_obj);
3270 i915_gem_object_unpin(obj);
3273 if (reloc->offset & 3) {
3274 DRM_ERROR("Relocation not 4-byte aligned: "
3275 "obj %p target %d offset %d.\n",
3276 obj, reloc->target_handle,
3277 (int) reloc->offset);
3278 drm_gem_object_unreference(target_obj);
3279 i915_gem_object_unpin(obj);
3283 /* and points to somewhere within the target object. */
3284 if (reloc->delta >= target_obj->size) {
3285 DRM_ERROR("Relocation beyond target object bounds: "
3286 "obj %p target %d delta %d size %d.\n",
3287 obj, reloc->target_handle,
3288 (int) reloc->delta, (int) target_obj->size);
3289 drm_gem_object_unreference(target_obj);
3290 i915_gem_object_unpin(obj);
3294 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3296 drm_gem_object_unreference(target_obj);
3297 i915_gem_object_unpin(obj);
3301 /* Map the page containing the relocation we're going to
3304 reloc_offset = obj_priv->gtt_offset + reloc->offset;
3305 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3308 reloc_entry = (uint32_t __iomem *)(reloc_page +
3309 (reloc_offset & (PAGE_SIZE - 1)));
3310 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
3313 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3314 obj, (unsigned int) reloc->offset,
3315 readl(reloc_entry), reloc_val);
3317 writel(reloc_val, reloc_entry);
3318 io_mapping_unmap_atomic(reloc_page);
3320 /* The updated presumed offset for this entry will be
3321 * copied back out to the user.
3323 reloc->presumed_offset = target_obj_priv->gtt_offset;
3325 drm_gem_object_unreference(target_obj);
3330 i915_gem_dump_object(obj, 128, __func__, ~0);
3335 /** Dispatch a batchbuffer to the ring
3338 i915_dispatch_gem_execbuffer(struct drm_device *dev,
3339 struct drm_i915_gem_execbuffer *exec,
3340 struct drm_clip_rect *cliprects,
3341 uint64_t exec_offset)
3343 drm_i915_private_t *dev_priv = dev->dev_private;
3344 int nbox = exec->num_cliprects;
3346 uint32_t exec_start, exec_len;
3349 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3350 exec_len = (uint32_t) exec->batch_len;
3352 trace_i915_gem_request_submit(dev, dev_priv->mm.next_gem_seqno);
3354 count = nbox ? nbox : 1;
3356 for (i = 0; i < count; i++) {
3358 int ret = i915_emit_box(dev, cliprects, i,
3359 exec->DR1, exec->DR4);
3364 if (IS_I830(dev) || IS_845G(dev)) {
3366 OUT_RING(MI_BATCH_BUFFER);
3367 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3368 OUT_RING(exec_start + exec_len - 4);
3373 if (IS_I965G(dev)) {
3374 OUT_RING(MI_BATCH_BUFFER_START |
3376 MI_BATCH_NON_SECURE_I965);
3377 OUT_RING(exec_start);
3379 OUT_RING(MI_BATCH_BUFFER_START |
3381 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3387 /* XXX breadcrumb */
3391 /* Throttle our rendering by waiting until the ring has completed our requests
3392 * emitted over 20 msec ago.
3394 * Note that if we were to use the current jiffies each time around the loop,
3395 * we wouldn't escape the function with any frames outstanding if the time to
3396 * render a frame was over 20ms.
3398 * This should get us reasonable parallelism between CPU and GPU but also
3399 * relatively low latency when blocking on a particular request to finish.
3402 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3404 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3406 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3408 mutex_lock(&dev->struct_mutex);
3409 while (!list_empty(&i915_file_priv->mm.request_list)) {
3410 struct drm_i915_gem_request *request;
3412 request = list_first_entry(&i915_file_priv->mm.request_list,
3413 struct drm_i915_gem_request,
3416 if (time_after_eq(request->emitted_jiffies, recent_enough))
3419 ret = i915_wait_request(dev, request->seqno);
3423 mutex_unlock(&dev->struct_mutex);
3429 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object *exec_list,
3430 uint32_t buffer_count,
3431 struct drm_i915_gem_relocation_entry **relocs)
3433 uint32_t reloc_count = 0, reloc_index = 0, i;
3437 for (i = 0; i < buffer_count; i++) {
3438 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3440 reloc_count += exec_list[i].relocation_count;
3443 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
3444 if (*relocs == NULL)
3447 for (i = 0; i < buffer_count; i++) {
3448 struct drm_i915_gem_relocation_entry __user *user_relocs;
3450 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3452 ret = copy_from_user(&(*relocs)[reloc_index],
3454 exec_list[i].relocation_count *
3457 drm_free_large(*relocs);
3462 reloc_index += exec_list[i].relocation_count;
3469 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object *exec_list,
3470 uint32_t buffer_count,
3471 struct drm_i915_gem_relocation_entry *relocs)
3473 uint32_t reloc_count = 0, i;
3476 for (i = 0; i < buffer_count; i++) {
3477 struct drm_i915_gem_relocation_entry __user *user_relocs;
3480 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3482 unwritten = copy_to_user(user_relocs,
3483 &relocs[reloc_count],
3484 exec_list[i].relocation_count *
3492 reloc_count += exec_list[i].relocation_count;
3496 drm_free_large(relocs);
3502 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer *exec,
3503 uint64_t exec_offset)
3505 uint32_t exec_start, exec_len;
3507 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3508 exec_len = (uint32_t) exec->batch_len;
3510 if ((exec_start | exec_len) & 0x7)
3520 i915_gem_execbuffer(struct drm_device *dev, void *data,
3521 struct drm_file *file_priv)
3523 drm_i915_private_t *dev_priv = dev->dev_private;
3524 struct drm_i915_gem_execbuffer *args = data;
3525 struct drm_i915_gem_exec_object *exec_list = NULL;
3526 struct drm_gem_object **object_list = NULL;
3527 struct drm_gem_object *batch_obj;
3528 struct drm_i915_gem_object *obj_priv;
3529 struct drm_clip_rect *cliprects = NULL;
3530 struct drm_i915_gem_relocation_entry *relocs;
3531 int ret, ret2, i, pinned = 0;
3532 uint64_t exec_offset;
3533 uint32_t seqno, flush_domains, reloc_index;
3537 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3538 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3541 if (args->buffer_count < 1) {
3542 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3545 /* Copy in the exec list from userland */
3546 exec_list = drm_calloc_large(sizeof(*exec_list), args->buffer_count);
3547 object_list = drm_calloc_large(sizeof(*object_list), args->buffer_count);
3548 if (exec_list == NULL || object_list == NULL) {
3549 DRM_ERROR("Failed to allocate exec or object list "
3551 args->buffer_count);
3555 ret = copy_from_user(exec_list,
3556 (struct drm_i915_relocation_entry __user *)
3557 (uintptr_t) args->buffers_ptr,
3558 sizeof(*exec_list) * args->buffer_count);
3560 DRM_ERROR("copy %d exec entries failed %d\n",
3561 args->buffer_count, ret);
3565 if (args->num_cliprects != 0) {
3566 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3568 if (cliprects == NULL)
3571 ret = copy_from_user(cliprects,
3572 (struct drm_clip_rect __user *)
3573 (uintptr_t) args->cliprects_ptr,
3574 sizeof(*cliprects) * args->num_cliprects);
3576 DRM_ERROR("copy %d cliprects failed: %d\n",
3577 args->num_cliprects, ret);
3582 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3587 mutex_lock(&dev->struct_mutex);
3589 i915_verify_inactive(dev, __FILE__, __LINE__);
3591 if (atomic_read(&dev_priv->mm.wedged)) {
3592 DRM_ERROR("Execbuf while wedged\n");
3593 mutex_unlock(&dev->struct_mutex);
3598 if (dev_priv->mm.suspended) {
3599 DRM_ERROR("Execbuf while VT-switched.\n");
3600 mutex_unlock(&dev->struct_mutex);
3605 /* Look up object handles */
3606 for (i = 0; i < args->buffer_count; i++) {
3607 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3608 exec_list[i].handle);
3609 if (object_list[i] == NULL) {
3610 DRM_ERROR("Invalid object handle %d at index %d\n",
3611 exec_list[i].handle, i);
3616 obj_priv = object_list[i]->driver_private;
3617 if (obj_priv->in_execbuffer) {
3618 DRM_ERROR("Object %p appears more than once in object list\n",
3623 obj_priv->in_execbuffer = true;
3626 /* Pin and relocate */
3627 for (pin_tries = 0; ; pin_tries++) {
3631 for (i = 0; i < args->buffer_count; i++) {
3632 object_list[i]->pending_read_domains = 0;
3633 object_list[i]->pending_write_domain = 0;
3634 ret = i915_gem_object_pin_and_relocate(object_list[i],
3637 &relocs[reloc_index]);
3641 reloc_index += exec_list[i].relocation_count;
3647 /* error other than GTT full, or we've already tried again */
3648 if (ret != -ENOSPC || pin_tries >= 1) {
3649 if (ret != -ERESTARTSYS) {
3650 unsigned long long total_size = 0;
3651 for (i = 0; i < args->buffer_count; i++)
3652 total_size += object_list[i]->size;
3653 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes: %d\n",
3654 pinned+1, args->buffer_count,
3656 DRM_ERROR("%d objects [%d pinned], "
3657 "%d object bytes [%d pinned], "
3658 "%d/%d gtt bytes\n",
3659 atomic_read(&dev->object_count),
3660 atomic_read(&dev->pin_count),
3661 atomic_read(&dev->object_memory),
3662 atomic_read(&dev->pin_memory),
3663 atomic_read(&dev->gtt_memory),
3669 /* unpin all of our buffers */
3670 for (i = 0; i < pinned; i++)
3671 i915_gem_object_unpin(object_list[i]);
3674 /* evict everyone we can from the aperture */
3675 ret = i915_gem_evict_everything(dev);
3676 if (ret && ret != -ENOSPC)
3680 /* Set the pending read domains for the batch buffer to COMMAND */
3681 batch_obj = object_list[args->buffer_count-1];
3682 if (batch_obj->pending_write_domain) {
3683 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3687 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
3689 /* Sanity check the batch buffer, prior to moving objects */
3690 exec_offset = exec_list[args->buffer_count - 1].offset;
3691 ret = i915_gem_check_execbuffer (args, exec_offset);
3693 DRM_ERROR("execbuf with invalid offset/length\n");
3697 i915_verify_inactive(dev, __FILE__, __LINE__);
3699 /* Zero the global flush/invalidate flags. These
3700 * will be modified as new domains are computed
3703 dev->invalidate_domains = 0;
3704 dev->flush_domains = 0;
3706 for (i = 0; i < args->buffer_count; i++) {
3707 struct drm_gem_object *obj = object_list[i];
3709 /* Compute new gpu domains and update invalidate/flush */
3710 i915_gem_object_set_to_gpu_domain(obj);
3713 i915_verify_inactive(dev, __FILE__, __LINE__);
3715 if (dev->invalidate_domains | dev->flush_domains) {
3717 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3719 dev->invalidate_domains,
3720 dev->flush_domains);
3723 dev->invalidate_domains,
3724 dev->flush_domains);
3725 if (dev->flush_domains)
3726 (void)i915_add_request(dev, file_priv,
3727 dev->flush_domains);
3730 for (i = 0; i < args->buffer_count; i++) {
3731 struct drm_gem_object *obj = object_list[i];
3732 uint32_t old_write_domain = obj->write_domain;
3734 obj->write_domain = obj->pending_write_domain;
3735 trace_i915_gem_object_change_domain(obj,
3740 i915_verify_inactive(dev, __FILE__, __LINE__);
3743 for (i = 0; i < args->buffer_count; i++) {
3744 i915_gem_object_check_coherency(object_list[i],
3745 exec_list[i].handle);
3750 i915_gem_dump_object(batch_obj,
3756 /* Exec the batchbuffer */
3757 ret = i915_dispatch_gem_execbuffer(dev, args, cliprects, exec_offset);
3759 DRM_ERROR("dispatch failed %d\n", ret);
3764 * Ensure that the commands in the batch buffer are
3765 * finished before the interrupt fires
3767 flush_domains = i915_retire_commands(dev);
3769 i915_verify_inactive(dev, __FILE__, __LINE__);
3772 * Get a seqno representing the execution of the current buffer,
3773 * which we can wait on. We would like to mitigate these interrupts,
3774 * likely by only creating seqnos occasionally (so that we have
3775 * *some* interrupts representing completion of buffers that we can
3776 * wait on when trying to clear up gtt space).
3778 seqno = i915_add_request(dev, file_priv, flush_domains);
3780 for (i = 0; i < args->buffer_count; i++) {
3781 struct drm_gem_object *obj = object_list[i];
3783 i915_gem_object_move_to_active(obj, seqno);
3785 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3789 i915_dump_lru(dev, __func__);
3792 i915_verify_inactive(dev, __FILE__, __LINE__);
3795 for (i = 0; i < pinned; i++)
3796 i915_gem_object_unpin(object_list[i]);
3798 for (i = 0; i < args->buffer_count; i++) {
3799 if (object_list[i]) {
3800 obj_priv = object_list[i]->driver_private;
3801 obj_priv->in_execbuffer = false;
3803 drm_gem_object_unreference(object_list[i]);
3806 mutex_unlock(&dev->struct_mutex);
3809 /* Copy the new buffer offsets back to the user's exec list. */
3810 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
3811 (uintptr_t) args->buffers_ptr,
3813 sizeof(*exec_list) * args->buffer_count);
3816 DRM_ERROR("failed to copy %d exec entries "
3817 "back to user (%d)\n",
3818 args->buffer_count, ret);
3822 /* Copy the updated relocations out regardless of current error
3823 * state. Failure to update the relocs would mean that the next
3824 * time userland calls execbuf, it would do so with presumed offset
3825 * state that didn't match the actual object state.
3827 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
3830 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
3837 drm_free_large(object_list);
3838 drm_free_large(exec_list);
3845 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
3847 struct drm_device *dev = obj->dev;
3848 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3851 i915_verify_inactive(dev, __FILE__, __LINE__);
3852 if (obj_priv->gtt_space == NULL) {
3853 ret = i915_gem_object_bind_to_gtt(obj, alignment);
3858 * Pre-965 chips need a fence register set up in order to
3859 * properly handle tiled surfaces.
3861 if (!IS_I965G(dev) && obj_priv->tiling_mode != I915_TILING_NONE) {
3862 ret = i915_gem_object_get_fence_reg(obj);
3864 if (ret != -EBUSY && ret != -ERESTARTSYS)
3865 DRM_ERROR("Failure to install fence: %d\n",
3870 obj_priv->pin_count++;
3872 /* If the object is not active and not pending a flush,
3873 * remove it from the inactive list
3875 if (obj_priv->pin_count == 1) {
3876 atomic_inc(&dev->pin_count);
3877 atomic_add(obj->size, &dev->pin_memory);
3878 if (!obj_priv->active &&
3879 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 &&
3880 !list_empty(&obj_priv->list))
3881 list_del_init(&obj_priv->list);
3883 i915_verify_inactive(dev, __FILE__, __LINE__);
3889 i915_gem_object_unpin(struct drm_gem_object *obj)
3891 struct drm_device *dev = obj->dev;
3892 drm_i915_private_t *dev_priv = dev->dev_private;
3893 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3895 i915_verify_inactive(dev, __FILE__, __LINE__);
3896 obj_priv->pin_count--;
3897 BUG_ON(obj_priv->pin_count < 0);
3898 BUG_ON(obj_priv->gtt_space == NULL);
3900 /* If the object is no longer pinned, and is
3901 * neither active nor being flushed, then stick it on
3904 if (obj_priv->pin_count == 0) {
3905 if (!obj_priv->active &&
3906 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
3907 list_move_tail(&obj_priv->list,
3908 &dev_priv->mm.inactive_list);
3909 atomic_dec(&dev->pin_count);
3910 atomic_sub(obj->size, &dev->pin_memory);
3912 i915_verify_inactive(dev, __FILE__, __LINE__);
3916 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3917 struct drm_file *file_priv)
3919 struct drm_i915_gem_pin *args = data;
3920 struct drm_gem_object *obj;
3921 struct drm_i915_gem_object *obj_priv;
3924 mutex_lock(&dev->struct_mutex);
3926 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
3928 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
3930 mutex_unlock(&dev->struct_mutex);
3933 obj_priv = obj->driver_private;
3935 if (obj_priv->madv != I915_MADV_WILLNEED) {
3936 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3937 drm_gem_object_unreference(obj);
3938 mutex_unlock(&dev->struct_mutex);
3942 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
3943 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3945 drm_gem_object_unreference(obj);
3946 mutex_unlock(&dev->struct_mutex);
3950 obj_priv->user_pin_count++;
3951 obj_priv->pin_filp = file_priv;
3952 if (obj_priv->user_pin_count == 1) {
3953 ret = i915_gem_object_pin(obj, args->alignment);
3955 drm_gem_object_unreference(obj);
3956 mutex_unlock(&dev->struct_mutex);
3961 /* XXX - flush the CPU caches for pinned objects
3962 * as the X server doesn't manage domains yet
3964 i915_gem_object_flush_cpu_write_domain(obj);
3965 args->offset = obj_priv->gtt_offset;
3966 drm_gem_object_unreference(obj);
3967 mutex_unlock(&dev->struct_mutex);
3973 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3974 struct drm_file *file_priv)
3976 struct drm_i915_gem_pin *args = data;
3977 struct drm_gem_object *obj;
3978 struct drm_i915_gem_object *obj_priv;
3980 mutex_lock(&dev->struct_mutex);
3982 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
3984 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
3986 mutex_unlock(&dev->struct_mutex);
3990 obj_priv = obj->driver_private;
3991 if (obj_priv->pin_filp != file_priv) {
3992 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3994 drm_gem_object_unreference(obj);
3995 mutex_unlock(&dev->struct_mutex);
3998 obj_priv->user_pin_count--;
3999 if (obj_priv->user_pin_count == 0) {
4000 obj_priv->pin_filp = NULL;
4001 i915_gem_object_unpin(obj);
4004 drm_gem_object_unreference(obj);
4005 mutex_unlock(&dev->struct_mutex);
4010 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4011 struct drm_file *file_priv)
4013 struct drm_i915_gem_busy *args = data;
4014 struct drm_gem_object *obj;
4015 struct drm_i915_gem_object *obj_priv;
4017 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4019 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4024 mutex_lock(&dev->struct_mutex);
4025 /* Update the active list for the hardware's current position.
4026 * Otherwise this only updates on a delayed timer or when irqs are
4027 * actually unmasked, and our working set ends up being larger than
4030 i915_gem_retire_requests(dev);
4032 obj_priv = obj->driver_private;
4033 /* Don't count being on the flushing list against the object being
4034 * done. Otherwise, a buffer left on the flushing list but not getting
4035 * flushed (because nobody's flushing that domain) won't ever return
4036 * unbusy and get reused by libdrm's bo cache. The other expected
4037 * consumer of this interface, OpenGL's occlusion queries, also specs
4038 * that the objects get unbusy "eventually" without any interference.
4040 args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
4042 drm_gem_object_unreference(obj);
4043 mutex_unlock(&dev->struct_mutex);
4048 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4049 struct drm_file *file_priv)
4051 return i915_gem_ring_throttle(dev, file_priv);
4055 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4056 struct drm_file *file_priv)
4058 struct drm_i915_gem_madvise *args = data;
4059 struct drm_gem_object *obj;
4060 struct drm_i915_gem_object *obj_priv;
4062 switch (args->madv) {
4063 case I915_MADV_DONTNEED:
4064 case I915_MADV_WILLNEED:
4070 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4072 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4077 mutex_lock(&dev->struct_mutex);
4078 obj_priv = obj->driver_private;
4080 if (obj_priv->pin_count) {
4081 drm_gem_object_unreference(obj);
4082 mutex_unlock(&dev->struct_mutex);
4084 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4088 if (obj_priv->madv != __I915_MADV_PURGED)
4089 obj_priv->madv = args->madv;
4091 /* if the object is no longer bound, discard its backing storage */
4092 if (i915_gem_object_is_purgeable(obj_priv) &&
4093 obj_priv->gtt_space == NULL)
4094 i915_gem_object_truncate(obj);
4096 args->retained = obj_priv->madv != __I915_MADV_PURGED;
4098 drm_gem_object_unreference(obj);
4099 mutex_unlock(&dev->struct_mutex);
4104 int i915_gem_init_object(struct drm_gem_object *obj)
4106 struct drm_i915_gem_object *obj_priv;
4108 obj_priv = kzalloc(sizeof(*obj_priv), GFP_KERNEL);
4109 if (obj_priv == NULL)
4113 * We've just allocated pages from the kernel,
4114 * so they've just been written by the CPU with
4115 * zeros. They'll need to be clflushed before we
4116 * use them with the GPU.
4118 obj->write_domain = I915_GEM_DOMAIN_CPU;
4119 obj->read_domains = I915_GEM_DOMAIN_CPU;
4121 obj_priv->agp_type = AGP_USER_MEMORY;
4123 obj->driver_private = obj_priv;
4124 obj_priv->obj = obj;
4125 obj_priv->fence_reg = I915_FENCE_REG_NONE;
4126 INIT_LIST_HEAD(&obj_priv->list);
4127 INIT_LIST_HEAD(&obj_priv->fence_list);
4128 obj_priv->madv = I915_MADV_WILLNEED;
4130 trace_i915_gem_object_create(obj);
4135 void i915_gem_free_object(struct drm_gem_object *obj)
4137 struct drm_device *dev = obj->dev;
4138 struct drm_i915_gem_object *obj_priv = obj->driver_private;
4140 trace_i915_gem_object_destroy(obj);
4142 while (obj_priv->pin_count > 0)
4143 i915_gem_object_unpin(obj);
4145 if (obj_priv->phys_obj)
4146 i915_gem_detach_phys_object(dev, obj);
4148 i915_gem_object_unbind(obj);
4150 if (obj_priv->mmap_offset)
4151 i915_gem_free_mmap_offset(obj);
4153 kfree(obj_priv->page_cpu_valid);
4154 kfree(obj_priv->bit_17);
4155 kfree(obj->driver_private);
4158 /** Unbinds all inactive objects. */
4160 i915_gem_evict_from_inactive_list(struct drm_device *dev)
4162 drm_i915_private_t *dev_priv = dev->dev_private;
4164 while (!list_empty(&dev_priv->mm.inactive_list)) {
4165 struct drm_gem_object *obj;
4168 obj = list_first_entry(&dev_priv->mm.inactive_list,
4169 struct drm_i915_gem_object,
4172 ret = i915_gem_object_unbind(obj);
4174 DRM_ERROR("Error unbinding object: %d\n", ret);
4183 i915_gem_idle(struct drm_device *dev)
4185 drm_i915_private_t *dev_priv = dev->dev_private;
4186 uint32_t seqno, cur_seqno, last_seqno;
4189 mutex_lock(&dev->struct_mutex);
4191 if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
4192 mutex_unlock(&dev->struct_mutex);
4196 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4197 * We need to replace this with a semaphore, or something.
4199 dev_priv->mm.suspended = 1;
4200 del_timer(&dev_priv->hangcheck_timer);
4202 /* Cancel the retire work handler, wait for it to finish if running
4204 mutex_unlock(&dev->struct_mutex);
4205 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4206 mutex_lock(&dev->struct_mutex);
4208 i915_kernel_lost_context(dev);
4210 /* Flush the GPU along with all non-CPU write domains
4212 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
4213 seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
4216 mutex_unlock(&dev->struct_mutex);
4220 dev_priv->mm.waiting_gem_seqno = seqno;
4224 cur_seqno = i915_get_gem_seqno(dev);
4225 if (i915_seqno_passed(cur_seqno, seqno))
4227 if (last_seqno == cur_seqno) {
4228 if (stuck++ > 100) {
4229 DRM_ERROR("hardware wedged\n");
4230 atomic_set(&dev_priv->mm.wedged, 1);
4231 DRM_WAKEUP(&dev_priv->irq_queue);
4236 last_seqno = cur_seqno;
4238 dev_priv->mm.waiting_gem_seqno = 0;
4240 i915_gem_retire_requests(dev);
4242 spin_lock(&dev_priv->mm.active_list_lock);
4243 if (!atomic_read(&dev_priv->mm.wedged)) {
4244 /* Active and flushing should now be empty as we've
4245 * waited for a sequence higher than any pending execbuffer
4247 WARN_ON(!list_empty(&dev_priv->mm.active_list));
4248 WARN_ON(!list_empty(&dev_priv->mm.flushing_list));
4249 /* Request should now be empty as we've also waited
4250 * for the last request in the list
4252 WARN_ON(!list_empty(&dev_priv->mm.request_list));
4255 /* Empty the active and flushing lists to inactive. If there's
4256 * anything left at this point, it means that we're wedged and
4257 * nothing good's going to happen by leaving them there. So strip
4258 * the GPU domains and just stuff them onto inactive.
4260 while (!list_empty(&dev_priv->mm.active_list)) {
4261 struct drm_gem_object *obj;
4262 uint32_t old_write_domain;
4264 obj = list_first_entry(&dev_priv->mm.active_list,
4265 struct drm_i915_gem_object,
4267 old_write_domain = obj->write_domain;
4268 obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
4269 i915_gem_object_move_to_inactive(obj);
4271 trace_i915_gem_object_change_domain(obj,
4275 spin_unlock(&dev_priv->mm.active_list_lock);
4277 while (!list_empty(&dev_priv->mm.flushing_list)) {
4278 struct drm_gem_object *obj;
4279 uint32_t old_write_domain;
4281 obj = list_first_entry(&dev_priv->mm.flushing_list,
4282 struct drm_i915_gem_object,
4284 old_write_domain = obj->write_domain;
4285 obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
4286 i915_gem_object_move_to_inactive(obj);
4288 trace_i915_gem_object_change_domain(obj,
4294 /* Move all inactive buffers out of the GTT. */
4295 ret = i915_gem_evict_from_inactive_list(dev);
4296 WARN_ON(!list_empty(&dev_priv->mm.inactive_list));
4298 mutex_unlock(&dev->struct_mutex);
4302 i915_gem_cleanup_ringbuffer(dev);
4303 mutex_unlock(&dev->struct_mutex);
4309 i915_gem_init_hws(struct drm_device *dev)
4311 drm_i915_private_t *dev_priv = dev->dev_private;
4312 struct drm_gem_object *obj;
4313 struct drm_i915_gem_object *obj_priv;
4316 /* If we need a physical address for the status page, it's already
4317 * initialized at driver load time.
4319 if (!I915_NEED_GFX_HWS(dev))
4322 obj = drm_gem_object_alloc(dev, 4096);
4324 DRM_ERROR("Failed to allocate status page\n");
4327 obj_priv = obj->driver_private;
4328 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4330 ret = i915_gem_object_pin(obj, 4096);
4332 drm_gem_object_unreference(obj);
4336 dev_priv->status_gfx_addr = obj_priv->gtt_offset;
4338 dev_priv->hw_status_page = kmap(obj_priv->pages[0]);
4339 if (dev_priv->hw_status_page == NULL) {
4340 DRM_ERROR("Failed to map status page.\n");
4341 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4342 i915_gem_object_unpin(obj);
4343 drm_gem_object_unreference(obj);
4346 dev_priv->hws_obj = obj;
4347 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
4348 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
4349 I915_READ(HWS_PGA); /* posting read */
4350 DRM_DEBUG("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
4356 i915_gem_cleanup_hws(struct drm_device *dev)
4358 drm_i915_private_t *dev_priv = dev->dev_private;
4359 struct drm_gem_object *obj;
4360 struct drm_i915_gem_object *obj_priv;
4362 if (dev_priv->hws_obj == NULL)
4365 obj = dev_priv->hws_obj;
4366 obj_priv = obj->driver_private;
4368 kunmap(obj_priv->pages[0]);
4369 i915_gem_object_unpin(obj);
4370 drm_gem_object_unreference(obj);
4371 dev_priv->hws_obj = NULL;
4373 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4374 dev_priv->hw_status_page = NULL;
4376 /* Write high address into HWS_PGA when disabling. */
4377 I915_WRITE(HWS_PGA, 0x1ffff000);
4381 i915_gem_init_ringbuffer(struct drm_device *dev)
4383 drm_i915_private_t *dev_priv = dev->dev_private;
4384 struct drm_gem_object *obj;
4385 struct drm_i915_gem_object *obj_priv;
4386 drm_i915_ring_buffer_t *ring = &dev_priv->ring;
4390 ret = i915_gem_init_hws(dev);
4394 obj = drm_gem_object_alloc(dev, 128 * 1024);
4396 DRM_ERROR("Failed to allocate ringbuffer\n");
4397 i915_gem_cleanup_hws(dev);
4400 obj_priv = obj->driver_private;
4402 ret = i915_gem_object_pin(obj, 4096);
4404 drm_gem_object_unreference(obj);
4405 i915_gem_cleanup_hws(dev);
4409 /* Set up the kernel mapping for the ring. */
4410 ring->Size = obj->size;
4412 ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
4413 ring->map.size = obj->size;
4415 ring->map.flags = 0;
4418 drm_core_ioremap_wc(&ring->map, dev);
4419 if (ring->map.handle == NULL) {
4420 DRM_ERROR("Failed to map ringbuffer.\n");
4421 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4422 i915_gem_object_unpin(obj);
4423 drm_gem_object_unreference(obj);
4424 i915_gem_cleanup_hws(dev);
4427 ring->ring_obj = obj;
4428 ring->virtual_start = ring->map.handle;
4430 /* Stop the ring if it's running. */
4431 I915_WRITE(PRB0_CTL, 0);
4432 I915_WRITE(PRB0_TAIL, 0);
4433 I915_WRITE(PRB0_HEAD, 0);
4435 /* Initialize the ring. */
4436 I915_WRITE(PRB0_START, obj_priv->gtt_offset);
4437 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4439 /* G45 ring initialization fails to reset head to zero */
4441 DRM_ERROR("Ring head not reset to zero "
4442 "ctl %08x head %08x tail %08x start %08x\n",
4443 I915_READ(PRB0_CTL),
4444 I915_READ(PRB0_HEAD),
4445 I915_READ(PRB0_TAIL),
4446 I915_READ(PRB0_START));
4447 I915_WRITE(PRB0_HEAD, 0);
4449 DRM_ERROR("Ring head forced to zero "
4450 "ctl %08x head %08x tail %08x start %08x\n",
4451 I915_READ(PRB0_CTL),
4452 I915_READ(PRB0_HEAD),
4453 I915_READ(PRB0_TAIL),
4454 I915_READ(PRB0_START));
4457 I915_WRITE(PRB0_CTL,
4458 ((obj->size - 4096) & RING_NR_PAGES) |
4462 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4464 /* If the head is still not zero, the ring is dead */
4466 DRM_ERROR("Ring initialization failed "
4467 "ctl %08x head %08x tail %08x start %08x\n",
4468 I915_READ(PRB0_CTL),
4469 I915_READ(PRB0_HEAD),
4470 I915_READ(PRB0_TAIL),
4471 I915_READ(PRB0_START));
4475 /* Update our cache of the ring state */
4476 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4477 i915_kernel_lost_context(dev);
4479 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4480 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
4481 ring->space = ring->head - (ring->tail + 8);
4482 if (ring->space < 0)
4483 ring->space += ring->Size;
4490 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4492 drm_i915_private_t *dev_priv = dev->dev_private;
4494 if (dev_priv->ring.ring_obj == NULL)
4497 drm_core_ioremapfree(&dev_priv->ring.map, dev);
4499 i915_gem_object_unpin(dev_priv->ring.ring_obj);
4500 drm_gem_object_unreference(dev_priv->ring.ring_obj);
4501 dev_priv->ring.ring_obj = NULL;
4502 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4504 i915_gem_cleanup_hws(dev);
4508 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4509 struct drm_file *file_priv)
4511 drm_i915_private_t *dev_priv = dev->dev_private;
4514 if (drm_core_check_feature(dev, DRIVER_MODESET))
4517 if (atomic_read(&dev_priv->mm.wedged)) {
4518 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4519 atomic_set(&dev_priv->mm.wedged, 0);
4522 mutex_lock(&dev->struct_mutex);
4523 dev_priv->mm.suspended = 0;
4525 ret = i915_gem_init_ringbuffer(dev);
4527 mutex_unlock(&dev->struct_mutex);
4531 spin_lock(&dev_priv->mm.active_list_lock);
4532 BUG_ON(!list_empty(&dev_priv->mm.active_list));
4533 spin_unlock(&dev_priv->mm.active_list_lock);
4535 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4536 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4537 BUG_ON(!list_empty(&dev_priv->mm.request_list));
4538 mutex_unlock(&dev->struct_mutex);
4540 drm_irq_install(dev);
4546 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4547 struct drm_file *file_priv)
4551 if (drm_core_check_feature(dev, DRIVER_MODESET))
4554 ret = i915_gem_idle(dev);
4555 drm_irq_uninstall(dev);
4561 i915_gem_lastclose(struct drm_device *dev)
4565 if (drm_core_check_feature(dev, DRIVER_MODESET))
4568 ret = i915_gem_idle(dev);
4570 DRM_ERROR("failed to idle hardware: %d\n", ret);
4574 i915_gem_load(struct drm_device *dev)
4577 drm_i915_private_t *dev_priv = dev->dev_private;
4579 spin_lock_init(&dev_priv->mm.active_list_lock);
4580 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4581 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4582 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4583 INIT_LIST_HEAD(&dev_priv->mm.request_list);
4584 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4585 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4586 i915_gem_retire_work_handler);
4587 dev_priv->mm.next_gem_seqno = 1;
4589 spin_lock(&shrink_list_lock);
4590 list_add(&dev_priv->mm.shrink_list, &shrink_list);
4591 spin_unlock(&shrink_list_lock);
4593 /* Old X drivers will take 0-2 for front, back, depth buffers */
4594 dev_priv->fence_reg_start = 3;
4596 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4597 dev_priv->num_fence_regs = 16;
4599 dev_priv->num_fence_regs = 8;
4601 /* Initialize fence registers to zero */
4602 if (IS_I965G(dev)) {
4603 for (i = 0; i < 16; i++)
4604 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4606 for (i = 0; i < 8; i++)
4607 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4608 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4609 for (i = 0; i < 8; i++)
4610 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4613 i915_gem_detect_bit_6_swizzle(dev);
4617 * Create a physically contiguous memory object for this object
4618 * e.g. for cursor + overlay regs
4620 int i915_gem_init_phys_object(struct drm_device *dev,
4623 drm_i915_private_t *dev_priv = dev->dev_private;
4624 struct drm_i915_gem_phys_object *phys_obj;
4627 if (dev_priv->mm.phys_objs[id - 1] || !size)
4630 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4636 phys_obj->handle = drm_pci_alloc(dev, size, 0, 0xffffffff);
4637 if (!phys_obj->handle) {
4642 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4645 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4653 void i915_gem_free_phys_object(struct drm_device *dev, int id)
4655 drm_i915_private_t *dev_priv = dev->dev_private;
4656 struct drm_i915_gem_phys_object *phys_obj;
4658 if (!dev_priv->mm.phys_objs[id - 1])
4661 phys_obj = dev_priv->mm.phys_objs[id - 1];
4662 if (phys_obj->cur_obj) {
4663 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4667 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4669 drm_pci_free(dev, phys_obj->handle);
4671 dev_priv->mm.phys_objs[id - 1] = NULL;
4674 void i915_gem_free_all_phys_object(struct drm_device *dev)
4678 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4679 i915_gem_free_phys_object(dev, i);
4682 void i915_gem_detach_phys_object(struct drm_device *dev,
4683 struct drm_gem_object *obj)
4685 struct drm_i915_gem_object *obj_priv;
4690 obj_priv = obj->driver_private;
4691 if (!obj_priv->phys_obj)
4694 ret = i915_gem_object_get_pages(obj);
4698 page_count = obj->size / PAGE_SIZE;
4700 for (i = 0; i < page_count; i++) {
4701 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
4702 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4704 memcpy(dst, src, PAGE_SIZE);
4705 kunmap_atomic(dst, KM_USER0);
4707 drm_clflush_pages(obj_priv->pages, page_count);
4708 drm_agp_chipset_flush(dev);
4710 i915_gem_object_put_pages(obj);
4712 obj_priv->phys_obj->cur_obj = NULL;
4713 obj_priv->phys_obj = NULL;
4717 i915_gem_attach_phys_object(struct drm_device *dev,
4718 struct drm_gem_object *obj, int id)
4720 drm_i915_private_t *dev_priv = dev->dev_private;
4721 struct drm_i915_gem_object *obj_priv;
4726 if (id > I915_MAX_PHYS_OBJECT)
4729 obj_priv = obj->driver_private;
4731 if (obj_priv->phys_obj) {
4732 if (obj_priv->phys_obj->id == id)
4734 i915_gem_detach_phys_object(dev, obj);
4738 /* create a new object */
4739 if (!dev_priv->mm.phys_objs[id - 1]) {
4740 ret = i915_gem_init_phys_object(dev, id,
4743 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
4748 /* bind to the object */
4749 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4750 obj_priv->phys_obj->cur_obj = obj;
4752 ret = i915_gem_object_get_pages(obj);
4754 DRM_ERROR("failed to get page list\n");
4758 page_count = obj->size / PAGE_SIZE;
4760 for (i = 0; i < page_count; i++) {
4761 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
4762 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4764 memcpy(dst, src, PAGE_SIZE);
4765 kunmap_atomic(src, KM_USER0);
4768 i915_gem_object_put_pages(obj);
4776 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4777 struct drm_i915_gem_pwrite *args,
4778 struct drm_file *file_priv)
4780 struct drm_i915_gem_object *obj_priv = obj->driver_private;
4783 char __user *user_data;
4785 user_data = (char __user *) (uintptr_t) args->data_ptr;
4786 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4788 DRM_DEBUG("obj_addr %p, %lld\n", obj_addr, args->size);
4789 ret = copy_from_user(obj_addr, user_data, args->size);
4793 drm_agp_chipset_flush(dev);
4797 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
4799 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
4801 /* Clean up our request list when the client is going away, so that
4802 * later retire_requests won't dereference our soon-to-be-gone
4805 mutex_lock(&dev->struct_mutex);
4806 while (!list_empty(&i915_file_priv->mm.request_list))
4807 list_del_init(i915_file_priv->mm.request_list.next);
4808 mutex_unlock(&dev->struct_mutex);
4812 i915_gem_shrink(int nr_to_scan, gfp_t gfp_mask)
4814 drm_i915_private_t *dev_priv, *next_dev;
4815 struct drm_i915_gem_object *obj_priv, *next_obj;
4817 int would_deadlock = 1;
4819 /* "fast-path" to count number of available objects */
4820 if (nr_to_scan == 0) {
4821 spin_lock(&shrink_list_lock);
4822 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4823 struct drm_device *dev = dev_priv->dev;
4825 if (mutex_trylock(&dev->struct_mutex)) {
4826 list_for_each_entry(obj_priv,
4827 &dev_priv->mm.inactive_list,
4830 mutex_unlock(&dev->struct_mutex);
4833 spin_unlock(&shrink_list_lock);
4835 return (cnt / 100) * sysctl_vfs_cache_pressure;
4838 spin_lock(&shrink_list_lock);
4840 /* first scan for clean buffers */
4841 list_for_each_entry_safe(dev_priv, next_dev,
4842 &shrink_list, mm.shrink_list) {
4843 struct drm_device *dev = dev_priv->dev;
4845 if (! mutex_trylock(&dev->struct_mutex))
4848 spin_unlock(&shrink_list_lock);
4850 i915_gem_retire_requests(dev);
4852 list_for_each_entry_safe(obj_priv, next_obj,
4853 &dev_priv->mm.inactive_list,
4855 if (i915_gem_object_is_purgeable(obj_priv)) {
4856 i915_gem_object_unbind(obj_priv->obj);
4857 if (--nr_to_scan <= 0)
4862 spin_lock(&shrink_list_lock);
4863 mutex_unlock(&dev->struct_mutex);
4867 if (nr_to_scan <= 0)
4871 /* second pass, evict/count anything still on the inactive list */
4872 list_for_each_entry_safe(dev_priv, next_dev,
4873 &shrink_list, mm.shrink_list) {
4874 struct drm_device *dev = dev_priv->dev;
4876 if (! mutex_trylock(&dev->struct_mutex))
4879 spin_unlock(&shrink_list_lock);
4881 list_for_each_entry_safe(obj_priv, next_obj,
4882 &dev_priv->mm.inactive_list,
4884 if (nr_to_scan > 0) {
4885 i915_gem_object_unbind(obj_priv->obj);
4891 spin_lock(&shrink_list_lock);
4892 mutex_unlock(&dev->struct_mutex);
4897 spin_unlock(&shrink_list_lock);
4902 return (cnt / 100) * sysctl_vfs_cache_pressure;
4907 static struct shrinker shrinker = {
4908 .shrink = i915_gem_shrink,
4909 .seeks = DEFAULT_SEEKS,
4913 i915_gem_shrinker_init(void)
4915 register_shrinker(&shrinker);
4919 i915_gem_shrinker_exit(void)
4921 unregister_shrinker(&shrinker);