2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/swap.h>
35 #include <linux/pci.h>
37 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
39 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
42 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
44 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
47 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
48 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
49 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
51 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
52 static int i915_gem_evict_something(struct drm_device *dev, int min_size);
53 static int i915_gem_evict_from_inactive_list(struct drm_device *dev);
54 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
55 struct drm_i915_gem_pwrite *args,
56 struct drm_file *file_priv);
58 static LIST_HEAD(shrink_list);
59 static DEFINE_SPINLOCK(shrink_list_lock);
61 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
64 drm_i915_private_t *dev_priv = dev->dev_private;
67 (start & (PAGE_SIZE - 1)) != 0 ||
68 (end & (PAGE_SIZE - 1)) != 0) {
72 drm_mm_init(&dev_priv->mm.gtt_space, start,
75 dev->gtt_total = (uint32_t) (end - start);
81 i915_gem_init_ioctl(struct drm_device *dev, void *data,
82 struct drm_file *file_priv)
84 struct drm_i915_gem_init *args = data;
87 mutex_lock(&dev->struct_mutex);
88 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
89 mutex_unlock(&dev->struct_mutex);
95 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
96 struct drm_file *file_priv)
98 struct drm_i915_gem_get_aperture *args = data;
100 if (!(dev->driver->driver_features & DRIVER_GEM))
103 args->aper_size = dev->gtt_total;
104 args->aper_available_size = (args->aper_size -
105 atomic_read(&dev->pin_memory));
112 * Creates a new mm object and returns a handle to it.
115 i915_gem_create_ioctl(struct drm_device *dev, void *data,
116 struct drm_file *file_priv)
118 struct drm_i915_gem_create *args = data;
119 struct drm_gem_object *obj;
123 args->size = roundup(args->size, PAGE_SIZE);
125 /* Allocate the new object */
126 obj = drm_gem_object_alloc(dev, args->size);
130 ret = drm_gem_handle_create(file_priv, obj, &handle);
131 mutex_lock(&dev->struct_mutex);
132 drm_gem_object_handle_unreference(obj);
133 mutex_unlock(&dev->struct_mutex);
138 args->handle = handle;
144 fast_shmem_read(struct page **pages,
145 loff_t page_base, int page_offset,
152 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
155 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
156 kunmap_atomic(vaddr, KM_USER0);
164 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
166 drm_i915_private_t *dev_priv = obj->dev->dev_private;
167 struct drm_i915_gem_object *obj_priv = obj->driver_private;
169 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
170 obj_priv->tiling_mode != I915_TILING_NONE;
174 slow_shmem_copy(struct page *dst_page,
176 struct page *src_page,
180 char *dst_vaddr, *src_vaddr;
182 dst_vaddr = kmap_atomic(dst_page, KM_USER0);
183 if (dst_vaddr == NULL)
186 src_vaddr = kmap_atomic(src_page, KM_USER1);
187 if (src_vaddr == NULL) {
188 kunmap_atomic(dst_vaddr, KM_USER0);
192 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
194 kunmap_atomic(src_vaddr, KM_USER1);
195 kunmap_atomic(dst_vaddr, KM_USER0);
201 slow_shmem_bit17_copy(struct page *gpu_page,
203 struct page *cpu_page,
208 char *gpu_vaddr, *cpu_vaddr;
210 /* Use the unswizzled path if this page isn't affected. */
211 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
213 return slow_shmem_copy(cpu_page, cpu_offset,
214 gpu_page, gpu_offset, length);
216 return slow_shmem_copy(gpu_page, gpu_offset,
217 cpu_page, cpu_offset, length);
220 gpu_vaddr = kmap_atomic(gpu_page, KM_USER0);
221 if (gpu_vaddr == NULL)
224 cpu_vaddr = kmap_atomic(cpu_page, KM_USER1);
225 if (cpu_vaddr == NULL) {
226 kunmap_atomic(gpu_vaddr, KM_USER0);
230 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
231 * XORing with the other bits (A9 for Y, A9 and A10 for X)
234 int cacheline_end = ALIGN(gpu_offset + 1, 64);
235 int this_length = min(cacheline_end - gpu_offset, length);
236 int swizzled_gpu_offset = gpu_offset ^ 64;
239 memcpy(cpu_vaddr + cpu_offset,
240 gpu_vaddr + swizzled_gpu_offset,
243 memcpy(gpu_vaddr + swizzled_gpu_offset,
244 cpu_vaddr + cpu_offset,
247 cpu_offset += this_length;
248 gpu_offset += this_length;
249 length -= this_length;
252 kunmap_atomic(cpu_vaddr, KM_USER1);
253 kunmap_atomic(gpu_vaddr, KM_USER0);
259 * This is the fast shmem pread path, which attempts to copy_from_user directly
260 * from the backing pages of the object to the user's address space. On a
261 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
264 i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
265 struct drm_i915_gem_pread *args,
266 struct drm_file *file_priv)
268 struct drm_i915_gem_object *obj_priv = obj->driver_private;
270 loff_t offset, page_base;
271 char __user *user_data;
272 int page_offset, page_length;
275 user_data = (char __user *) (uintptr_t) args->data_ptr;
278 mutex_lock(&dev->struct_mutex);
280 ret = i915_gem_object_get_pages(obj);
284 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
289 obj_priv = obj->driver_private;
290 offset = args->offset;
293 /* Operation in this page
295 * page_base = page offset within aperture
296 * page_offset = offset within page
297 * page_length = bytes to copy for this page
299 page_base = (offset & ~(PAGE_SIZE-1));
300 page_offset = offset & (PAGE_SIZE-1);
301 page_length = remain;
302 if ((page_offset + remain) > PAGE_SIZE)
303 page_length = PAGE_SIZE - page_offset;
305 ret = fast_shmem_read(obj_priv->pages,
306 page_base, page_offset,
307 user_data, page_length);
311 remain -= page_length;
312 user_data += page_length;
313 offset += page_length;
317 i915_gem_object_put_pages(obj);
319 mutex_unlock(&dev->struct_mutex);
325 i915_gem_object_get_page_gfp_mask (struct drm_gem_object *obj)
327 return mapping_gfp_mask(obj->filp->f_path.dentry->d_inode->i_mapping);
331 i915_gem_object_set_page_gfp_mask (struct drm_gem_object *obj, gfp_t gfp)
333 mapping_set_gfp_mask(obj->filp->f_path.dentry->d_inode->i_mapping, gfp);
337 i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
341 ret = i915_gem_object_get_pages(obj);
343 /* If we've insufficient memory to map in the pages, attempt
344 * to make some space by throwing out some old buffers.
346 if (ret == -ENOMEM) {
347 struct drm_device *dev = obj->dev;
350 ret = i915_gem_evict_something(dev, obj->size);
354 gfp = i915_gem_object_get_page_gfp_mask(obj);
355 i915_gem_object_set_page_gfp_mask(obj, gfp & ~__GFP_NORETRY);
356 ret = i915_gem_object_get_pages(obj);
357 i915_gem_object_set_page_gfp_mask (obj, gfp);
364 * This is the fallback shmem pread path, which allocates temporary storage
365 * in kernel space to copy_to_user into outside of the struct_mutex, so we
366 * can copy out of the object's backing pages while holding the struct mutex
367 * and not take page faults.
370 i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
371 struct drm_i915_gem_pread *args,
372 struct drm_file *file_priv)
374 struct drm_i915_gem_object *obj_priv = obj->driver_private;
375 struct mm_struct *mm = current->mm;
376 struct page **user_pages;
378 loff_t offset, pinned_pages, i;
379 loff_t first_data_page, last_data_page, num_pages;
380 int shmem_page_index, shmem_page_offset;
381 int data_page_index, data_page_offset;
384 uint64_t data_ptr = args->data_ptr;
385 int do_bit17_swizzling;
389 /* Pin the user pages containing the data. We can't fault while
390 * holding the struct mutex, yet we want to hold it while
391 * dereferencing the user data.
393 first_data_page = data_ptr / PAGE_SIZE;
394 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
395 num_pages = last_data_page - first_data_page + 1;
397 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
398 if (user_pages == NULL)
401 down_read(&mm->mmap_sem);
402 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
403 num_pages, 1, 0, user_pages, NULL);
404 up_read(&mm->mmap_sem);
405 if (pinned_pages < num_pages) {
407 goto fail_put_user_pages;
410 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
412 mutex_lock(&dev->struct_mutex);
414 ret = i915_gem_object_get_pages_or_evict(obj);
418 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
423 obj_priv = obj->driver_private;
424 offset = args->offset;
427 /* Operation in this page
429 * shmem_page_index = page number within shmem file
430 * shmem_page_offset = offset within page in shmem file
431 * data_page_index = page number in get_user_pages return
432 * data_page_offset = offset with data_page_index page.
433 * page_length = bytes to copy for this page
435 shmem_page_index = offset / PAGE_SIZE;
436 shmem_page_offset = offset & ~PAGE_MASK;
437 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
438 data_page_offset = data_ptr & ~PAGE_MASK;
440 page_length = remain;
441 if ((shmem_page_offset + page_length) > PAGE_SIZE)
442 page_length = PAGE_SIZE - shmem_page_offset;
443 if ((data_page_offset + page_length) > PAGE_SIZE)
444 page_length = PAGE_SIZE - data_page_offset;
446 if (do_bit17_swizzling) {
447 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
449 user_pages[data_page_index],
454 ret = slow_shmem_copy(user_pages[data_page_index],
456 obj_priv->pages[shmem_page_index],
463 remain -= page_length;
464 data_ptr += page_length;
465 offset += page_length;
469 i915_gem_object_put_pages(obj);
471 mutex_unlock(&dev->struct_mutex);
473 for (i = 0; i < pinned_pages; i++) {
474 SetPageDirty(user_pages[i]);
475 page_cache_release(user_pages[i]);
477 drm_free_large(user_pages);
483 * Reads data from the object referenced by handle.
485 * On error, the contents of *data are undefined.
488 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
489 struct drm_file *file_priv)
491 struct drm_i915_gem_pread *args = data;
492 struct drm_gem_object *obj;
493 struct drm_i915_gem_object *obj_priv;
496 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
499 obj_priv = obj->driver_private;
501 /* Bounds check source.
503 * XXX: This could use review for overflow issues...
505 if (args->offset > obj->size || args->size > obj->size ||
506 args->offset + args->size > obj->size) {
507 drm_gem_object_unreference(obj);
511 if (i915_gem_object_needs_bit17_swizzle(obj)) {
512 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
514 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
516 ret = i915_gem_shmem_pread_slow(dev, obj, args,
520 drm_gem_object_unreference(obj);
525 /* This is the fast write path which cannot handle
526 * page faults in the source data
530 fast_user_write(struct io_mapping *mapping,
531 loff_t page_base, int page_offset,
532 char __user *user_data,
536 unsigned long unwritten;
538 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
539 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
541 io_mapping_unmap_atomic(vaddr_atomic);
547 /* Here's the write path which can sleep for
552 slow_kernel_write(struct io_mapping *mapping,
553 loff_t gtt_base, int gtt_offset,
554 struct page *user_page, int user_offset,
557 char *src_vaddr, *dst_vaddr;
558 unsigned long unwritten;
560 dst_vaddr = io_mapping_map_atomic_wc(mapping, gtt_base);
561 src_vaddr = kmap_atomic(user_page, KM_USER1);
562 unwritten = __copy_from_user_inatomic_nocache(dst_vaddr + gtt_offset,
563 src_vaddr + user_offset,
565 kunmap_atomic(src_vaddr, KM_USER1);
566 io_mapping_unmap_atomic(dst_vaddr);
573 fast_shmem_write(struct page **pages,
574 loff_t page_base, int page_offset,
579 unsigned long unwritten;
581 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
584 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
585 kunmap_atomic(vaddr, KM_USER0);
593 * This is the fast pwrite path, where we copy the data directly from the
594 * user into the GTT, uncached.
597 i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
598 struct drm_i915_gem_pwrite *args,
599 struct drm_file *file_priv)
601 struct drm_i915_gem_object *obj_priv = obj->driver_private;
602 drm_i915_private_t *dev_priv = dev->dev_private;
604 loff_t offset, page_base;
605 char __user *user_data;
606 int page_offset, page_length;
609 user_data = (char __user *) (uintptr_t) args->data_ptr;
611 if (!access_ok(VERIFY_READ, user_data, remain))
615 mutex_lock(&dev->struct_mutex);
616 ret = i915_gem_object_pin(obj, 0);
618 mutex_unlock(&dev->struct_mutex);
621 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
625 obj_priv = obj->driver_private;
626 offset = obj_priv->gtt_offset + args->offset;
629 /* Operation in this page
631 * page_base = page offset within aperture
632 * page_offset = offset within page
633 * page_length = bytes to copy for this page
635 page_base = (offset & ~(PAGE_SIZE-1));
636 page_offset = offset & (PAGE_SIZE-1);
637 page_length = remain;
638 if ((page_offset + remain) > PAGE_SIZE)
639 page_length = PAGE_SIZE - page_offset;
641 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
642 page_offset, user_data, page_length);
644 /* If we get a fault while copying data, then (presumably) our
645 * source page isn't available. Return the error and we'll
646 * retry in the slow path.
651 remain -= page_length;
652 user_data += page_length;
653 offset += page_length;
657 i915_gem_object_unpin(obj);
658 mutex_unlock(&dev->struct_mutex);
664 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
665 * the memory and maps it using kmap_atomic for copying.
667 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
668 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
671 i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
672 struct drm_i915_gem_pwrite *args,
673 struct drm_file *file_priv)
675 struct drm_i915_gem_object *obj_priv = obj->driver_private;
676 drm_i915_private_t *dev_priv = dev->dev_private;
678 loff_t gtt_page_base, offset;
679 loff_t first_data_page, last_data_page, num_pages;
680 loff_t pinned_pages, i;
681 struct page **user_pages;
682 struct mm_struct *mm = current->mm;
683 int gtt_page_offset, data_page_offset, data_page_index, page_length;
685 uint64_t data_ptr = args->data_ptr;
689 /* Pin the user pages containing the data. We can't fault while
690 * holding the struct mutex, and all of the pwrite implementations
691 * want to hold it while dereferencing the user data.
693 first_data_page = data_ptr / PAGE_SIZE;
694 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
695 num_pages = last_data_page - first_data_page + 1;
697 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
698 if (user_pages == NULL)
701 down_read(&mm->mmap_sem);
702 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
703 num_pages, 0, 0, user_pages, NULL);
704 up_read(&mm->mmap_sem);
705 if (pinned_pages < num_pages) {
707 goto out_unpin_pages;
710 mutex_lock(&dev->struct_mutex);
711 ret = i915_gem_object_pin(obj, 0);
715 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
717 goto out_unpin_object;
719 obj_priv = obj->driver_private;
720 offset = obj_priv->gtt_offset + args->offset;
723 /* Operation in this page
725 * gtt_page_base = page offset within aperture
726 * gtt_page_offset = offset within page in aperture
727 * data_page_index = page number in get_user_pages return
728 * data_page_offset = offset with data_page_index page.
729 * page_length = bytes to copy for this page
731 gtt_page_base = offset & PAGE_MASK;
732 gtt_page_offset = offset & ~PAGE_MASK;
733 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
734 data_page_offset = data_ptr & ~PAGE_MASK;
736 page_length = remain;
737 if ((gtt_page_offset + page_length) > PAGE_SIZE)
738 page_length = PAGE_SIZE - gtt_page_offset;
739 if ((data_page_offset + page_length) > PAGE_SIZE)
740 page_length = PAGE_SIZE - data_page_offset;
742 ret = slow_kernel_write(dev_priv->mm.gtt_mapping,
743 gtt_page_base, gtt_page_offset,
744 user_pages[data_page_index],
748 /* If we get a fault while copying data, then (presumably) our
749 * source page isn't available. Return the error and we'll
750 * retry in the slow path.
753 goto out_unpin_object;
755 remain -= page_length;
756 offset += page_length;
757 data_ptr += page_length;
761 i915_gem_object_unpin(obj);
763 mutex_unlock(&dev->struct_mutex);
765 for (i = 0; i < pinned_pages; i++)
766 page_cache_release(user_pages[i]);
767 drm_free_large(user_pages);
773 * This is the fast shmem pwrite path, which attempts to directly
774 * copy_from_user into the kmapped pages backing the object.
777 i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
778 struct drm_i915_gem_pwrite *args,
779 struct drm_file *file_priv)
781 struct drm_i915_gem_object *obj_priv = obj->driver_private;
783 loff_t offset, page_base;
784 char __user *user_data;
785 int page_offset, page_length;
788 user_data = (char __user *) (uintptr_t) args->data_ptr;
791 mutex_lock(&dev->struct_mutex);
793 ret = i915_gem_object_get_pages(obj);
797 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
801 obj_priv = obj->driver_private;
802 offset = args->offset;
806 /* Operation in this page
808 * page_base = page offset within aperture
809 * page_offset = offset within page
810 * page_length = bytes to copy for this page
812 page_base = (offset & ~(PAGE_SIZE-1));
813 page_offset = offset & (PAGE_SIZE-1);
814 page_length = remain;
815 if ((page_offset + remain) > PAGE_SIZE)
816 page_length = PAGE_SIZE - page_offset;
818 ret = fast_shmem_write(obj_priv->pages,
819 page_base, page_offset,
820 user_data, page_length);
824 remain -= page_length;
825 user_data += page_length;
826 offset += page_length;
830 i915_gem_object_put_pages(obj);
832 mutex_unlock(&dev->struct_mutex);
838 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
839 * the memory and maps it using kmap_atomic for copying.
841 * This avoids taking mmap_sem for faulting on the user's address while the
842 * struct_mutex is held.
845 i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
846 struct drm_i915_gem_pwrite *args,
847 struct drm_file *file_priv)
849 struct drm_i915_gem_object *obj_priv = obj->driver_private;
850 struct mm_struct *mm = current->mm;
851 struct page **user_pages;
853 loff_t offset, pinned_pages, i;
854 loff_t first_data_page, last_data_page, num_pages;
855 int shmem_page_index, shmem_page_offset;
856 int data_page_index, data_page_offset;
859 uint64_t data_ptr = args->data_ptr;
860 int do_bit17_swizzling;
864 /* Pin the user pages containing the data. We can't fault while
865 * holding the struct mutex, and all of the pwrite implementations
866 * want to hold it while dereferencing the user data.
868 first_data_page = data_ptr / PAGE_SIZE;
869 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
870 num_pages = last_data_page - first_data_page + 1;
872 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
873 if (user_pages == NULL)
876 down_read(&mm->mmap_sem);
877 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
878 num_pages, 0, 0, user_pages, NULL);
879 up_read(&mm->mmap_sem);
880 if (pinned_pages < num_pages) {
882 goto fail_put_user_pages;
885 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
887 mutex_lock(&dev->struct_mutex);
889 ret = i915_gem_object_get_pages_or_evict(obj);
893 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
897 obj_priv = obj->driver_private;
898 offset = args->offset;
902 /* Operation in this page
904 * shmem_page_index = page number within shmem file
905 * shmem_page_offset = offset within page in shmem file
906 * data_page_index = page number in get_user_pages return
907 * data_page_offset = offset with data_page_index page.
908 * page_length = bytes to copy for this page
910 shmem_page_index = offset / PAGE_SIZE;
911 shmem_page_offset = offset & ~PAGE_MASK;
912 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
913 data_page_offset = data_ptr & ~PAGE_MASK;
915 page_length = remain;
916 if ((shmem_page_offset + page_length) > PAGE_SIZE)
917 page_length = PAGE_SIZE - shmem_page_offset;
918 if ((data_page_offset + page_length) > PAGE_SIZE)
919 page_length = PAGE_SIZE - data_page_offset;
921 if (do_bit17_swizzling) {
922 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
924 user_pages[data_page_index],
929 ret = slow_shmem_copy(obj_priv->pages[shmem_page_index],
931 user_pages[data_page_index],
938 remain -= page_length;
939 data_ptr += page_length;
940 offset += page_length;
944 i915_gem_object_put_pages(obj);
946 mutex_unlock(&dev->struct_mutex);
948 for (i = 0; i < pinned_pages; i++)
949 page_cache_release(user_pages[i]);
950 drm_free_large(user_pages);
956 * Writes data to the object referenced by handle.
958 * On error, the contents of the buffer that were to be modified are undefined.
961 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
962 struct drm_file *file_priv)
964 struct drm_i915_gem_pwrite *args = data;
965 struct drm_gem_object *obj;
966 struct drm_i915_gem_object *obj_priv;
969 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
972 obj_priv = obj->driver_private;
974 /* Bounds check destination.
976 * XXX: This could use review for overflow issues...
978 if (args->offset > obj->size || args->size > obj->size ||
979 args->offset + args->size > obj->size) {
980 drm_gem_object_unreference(obj);
984 /* We can only do the GTT pwrite on untiled buffers, as otherwise
985 * it would end up going through the fenced access, and we'll get
986 * different detiling behavior between reading and writing.
987 * pread/pwrite currently are reading and writing from the CPU
988 * perspective, requiring manual detiling by the client.
990 if (obj_priv->phys_obj)
991 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
992 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
993 dev->gtt_total != 0) {
994 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
995 if (ret == -EFAULT) {
996 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
999 } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
1000 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
1002 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
1003 if (ret == -EFAULT) {
1004 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
1011 DRM_INFO("pwrite failed %d\n", ret);
1014 drm_gem_object_unreference(obj);
1020 * Called when user space prepares to use an object with the CPU, either
1021 * through the mmap ioctl's mapping or a GTT mapping.
1024 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1025 struct drm_file *file_priv)
1027 struct drm_i915_private *dev_priv = dev->dev_private;
1028 struct drm_i915_gem_set_domain *args = data;
1029 struct drm_gem_object *obj;
1030 struct drm_i915_gem_object *obj_priv;
1031 uint32_t read_domains = args->read_domains;
1032 uint32_t write_domain = args->write_domain;
1035 if (!(dev->driver->driver_features & DRIVER_GEM))
1038 /* Only handle setting domains to types used by the CPU. */
1039 if (write_domain & I915_GEM_GPU_DOMAINS)
1042 if (read_domains & I915_GEM_GPU_DOMAINS)
1045 /* Having something in the write domain implies it's in the read
1046 * domain, and only that read domain. Enforce that in the request.
1048 if (write_domain != 0 && read_domains != write_domain)
1051 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1054 obj_priv = obj->driver_private;
1056 mutex_lock(&dev->struct_mutex);
1058 intel_mark_busy(dev, obj);
1061 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1062 obj, obj->size, read_domains, write_domain);
1064 if (read_domains & I915_GEM_DOMAIN_GTT) {
1065 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1067 /* Update the LRU on the fence for the CPU access that's
1070 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1071 list_move_tail(&obj_priv->fence_list,
1072 &dev_priv->mm.fence_list);
1075 /* Silently promote "you're not bound, there was nothing to do"
1076 * to success, since the client was just asking us to
1077 * make sure everything was done.
1082 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1085 drm_gem_object_unreference(obj);
1086 mutex_unlock(&dev->struct_mutex);
1091 * Called when user space has done writes to this buffer
1094 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1095 struct drm_file *file_priv)
1097 struct drm_i915_gem_sw_finish *args = data;
1098 struct drm_gem_object *obj;
1099 struct drm_i915_gem_object *obj_priv;
1102 if (!(dev->driver->driver_features & DRIVER_GEM))
1105 mutex_lock(&dev->struct_mutex);
1106 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1108 mutex_unlock(&dev->struct_mutex);
1113 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1114 __func__, args->handle, obj, obj->size);
1116 obj_priv = obj->driver_private;
1118 /* Pinned buffers may be scanout, so flush the cache */
1119 if (obj_priv->pin_count)
1120 i915_gem_object_flush_cpu_write_domain(obj);
1122 drm_gem_object_unreference(obj);
1123 mutex_unlock(&dev->struct_mutex);
1128 * Maps the contents of an object, returning the address it is mapped
1131 * While the mapping holds a reference on the contents of the object, it doesn't
1132 * imply a ref on the object itself.
1135 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1136 struct drm_file *file_priv)
1138 struct drm_i915_gem_mmap *args = data;
1139 struct drm_gem_object *obj;
1143 if (!(dev->driver->driver_features & DRIVER_GEM))
1146 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1150 offset = args->offset;
1152 down_write(¤t->mm->mmap_sem);
1153 addr = do_mmap(obj->filp, 0, args->size,
1154 PROT_READ | PROT_WRITE, MAP_SHARED,
1156 up_write(¤t->mm->mmap_sem);
1157 mutex_lock(&dev->struct_mutex);
1158 drm_gem_object_unreference(obj);
1159 mutex_unlock(&dev->struct_mutex);
1160 if (IS_ERR((void *)addr))
1163 args->addr_ptr = (uint64_t) addr;
1169 * i915_gem_fault - fault a page into the GTT
1170 * vma: VMA in question
1173 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1174 * from userspace. The fault handler takes care of binding the object to
1175 * the GTT (if needed), allocating and programming a fence register (again,
1176 * only if needed based on whether the old reg is still valid or the object
1177 * is tiled) and inserting a new PTE into the faulting process.
1179 * Note that the faulting process may involve evicting existing objects
1180 * from the GTT and/or fence registers to make room. So performance may
1181 * suffer if the GTT working set is large or there are few fence registers
1184 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1186 struct drm_gem_object *obj = vma->vm_private_data;
1187 struct drm_device *dev = obj->dev;
1188 struct drm_i915_private *dev_priv = dev->dev_private;
1189 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1190 pgoff_t page_offset;
1193 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1195 /* We don't use vmf->pgoff since that has the fake offset */
1196 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1199 /* Now bind it into the GTT if needed */
1200 mutex_lock(&dev->struct_mutex);
1201 if (!obj_priv->gtt_space) {
1202 ret = i915_gem_object_bind_to_gtt(obj, 0);
1204 mutex_unlock(&dev->struct_mutex);
1205 return VM_FAULT_SIGBUS;
1207 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1209 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1211 mutex_unlock(&dev->struct_mutex);
1212 return VM_FAULT_SIGBUS;
1216 /* Need a new fence register? */
1217 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1218 ret = i915_gem_object_get_fence_reg(obj);
1220 mutex_unlock(&dev->struct_mutex);
1221 return VM_FAULT_SIGBUS;
1225 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1228 /* Finally, remap it using the new GTT offset */
1229 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1231 mutex_unlock(&dev->struct_mutex);
1236 return VM_FAULT_OOM;
1239 return VM_FAULT_SIGBUS;
1241 return VM_FAULT_NOPAGE;
1246 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1247 * @obj: obj in question
1249 * GEM memory mapping works by handing back to userspace a fake mmap offset
1250 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1251 * up the object based on the offset and sets up the various memory mapping
1254 * This routine allocates and attaches a fake offset for @obj.
1257 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1259 struct drm_device *dev = obj->dev;
1260 struct drm_gem_mm *mm = dev->mm_private;
1261 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1262 struct drm_map_list *list;
1263 struct drm_local_map *map;
1266 /* Set the object up for mmap'ing */
1267 list = &obj->map_list;
1268 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1273 map->type = _DRM_GEM;
1274 map->size = obj->size;
1277 /* Get a DRM GEM mmap offset allocated... */
1278 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1279 obj->size / PAGE_SIZE, 0, 0);
1280 if (!list->file_offset_node) {
1281 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1286 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1287 obj->size / PAGE_SIZE, 0);
1288 if (!list->file_offset_node) {
1293 list->hash.key = list->file_offset_node->start;
1294 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1295 DRM_ERROR("failed to add to map hash\n");
1299 /* By now we should be all set, any drm_mmap request on the offset
1300 * below will get to our mmap & fault handler */
1301 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1306 drm_mm_put_block(list->file_offset_node);
1314 * i915_gem_release_mmap - remove physical page mappings
1315 * @obj: obj in question
1317 * Preserve the reservation of the mmaping with the DRM core code, but
1318 * relinquish ownership of the pages back to the system.
1320 * It is vital that we remove the page mapping if we have mapped a tiled
1321 * object through the GTT and then lose the fence register due to
1322 * resource pressure. Similarly if the object has been moved out of the
1323 * aperture, than pages mapped into userspace must be revoked. Removing the
1324 * mapping will then trigger a page fault on the next user access, allowing
1325 * fixup by i915_gem_fault().
1328 i915_gem_release_mmap(struct drm_gem_object *obj)
1330 struct drm_device *dev = obj->dev;
1331 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1333 if (dev->dev_mapping)
1334 unmap_mapping_range(dev->dev_mapping,
1335 obj_priv->mmap_offset, obj->size, 1);
1339 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1341 struct drm_device *dev = obj->dev;
1342 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1343 struct drm_gem_mm *mm = dev->mm_private;
1344 struct drm_map_list *list;
1346 list = &obj->map_list;
1347 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1349 if (list->file_offset_node) {
1350 drm_mm_put_block(list->file_offset_node);
1351 list->file_offset_node = NULL;
1359 obj_priv->mmap_offset = 0;
1363 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1364 * @obj: object to check
1366 * Return the required GTT alignment for an object, taking into account
1367 * potential fence register mapping if needed.
1370 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1372 struct drm_device *dev = obj->dev;
1373 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1377 * Minimum alignment is 4k (GTT page size), but might be greater
1378 * if a fence register is needed for the object.
1380 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1384 * Previous chips need to be aligned to the size of the smallest
1385 * fence register that can contain the object.
1392 for (i = start; i < obj->size; i <<= 1)
1399 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1401 * @data: GTT mapping ioctl data
1402 * @file_priv: GEM object info
1404 * Simply returns the fake offset to userspace so it can mmap it.
1405 * The mmap call will end up in drm_gem_mmap(), which will set things
1406 * up so we can get faults in the handler above.
1408 * The fault handler will take care of binding the object into the GTT
1409 * (since it may have been evicted to make room for something), allocating
1410 * a fence register, and mapping the appropriate aperture address into
1414 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1415 struct drm_file *file_priv)
1417 struct drm_i915_gem_mmap_gtt *args = data;
1418 struct drm_i915_private *dev_priv = dev->dev_private;
1419 struct drm_gem_object *obj;
1420 struct drm_i915_gem_object *obj_priv;
1423 if (!(dev->driver->driver_features & DRIVER_GEM))
1426 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1430 mutex_lock(&dev->struct_mutex);
1432 obj_priv = obj->driver_private;
1434 if (!obj_priv->mmap_offset) {
1435 ret = i915_gem_create_mmap_offset(obj);
1437 drm_gem_object_unreference(obj);
1438 mutex_unlock(&dev->struct_mutex);
1443 args->offset = obj_priv->mmap_offset;
1446 * Pull it into the GTT so that we have a page list (makes the
1447 * initial fault faster and any subsequent flushing possible).
1449 if (!obj_priv->agp_mem) {
1450 ret = i915_gem_object_bind_to_gtt(obj, 0);
1452 drm_gem_object_unreference(obj);
1453 mutex_unlock(&dev->struct_mutex);
1456 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1459 drm_gem_object_unreference(obj);
1460 mutex_unlock(&dev->struct_mutex);
1466 i915_gem_object_put_pages(struct drm_gem_object *obj)
1468 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1469 int page_count = obj->size / PAGE_SIZE;
1472 BUG_ON(obj_priv->pages_refcount == 0);
1474 if (--obj_priv->pages_refcount != 0)
1477 if (obj_priv->tiling_mode != I915_TILING_NONE)
1478 i915_gem_object_save_bit_17_swizzle(obj);
1480 if (obj_priv->madv == I915_MADV_DONTNEED)
1481 obj_priv->dirty = 0;
1483 for (i = 0; i < page_count; i++) {
1484 if (obj_priv->pages[i] == NULL)
1487 if (obj_priv->dirty)
1488 set_page_dirty(obj_priv->pages[i]);
1490 if (obj_priv->madv == I915_MADV_WILLNEED)
1491 mark_page_accessed(obj_priv->pages[i]);
1493 page_cache_release(obj_priv->pages[i]);
1495 obj_priv->dirty = 0;
1497 drm_free_large(obj_priv->pages);
1498 obj_priv->pages = NULL;
1502 i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
1504 struct drm_device *dev = obj->dev;
1505 drm_i915_private_t *dev_priv = dev->dev_private;
1506 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1508 /* Add a reference if we're newly entering the active list. */
1509 if (!obj_priv->active) {
1510 drm_gem_object_reference(obj);
1511 obj_priv->active = 1;
1513 /* Move from whatever list we were on to the tail of execution. */
1514 spin_lock(&dev_priv->mm.active_list_lock);
1515 list_move_tail(&obj_priv->list,
1516 &dev_priv->mm.active_list);
1517 spin_unlock(&dev_priv->mm.active_list_lock);
1518 obj_priv->last_rendering_seqno = seqno;
1522 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1524 struct drm_device *dev = obj->dev;
1525 drm_i915_private_t *dev_priv = dev->dev_private;
1526 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1528 BUG_ON(!obj_priv->active);
1529 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1530 obj_priv->last_rendering_seqno = 0;
1534 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1536 struct drm_device *dev = obj->dev;
1537 drm_i915_private_t *dev_priv = dev->dev_private;
1538 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1540 i915_verify_inactive(dev, __FILE__, __LINE__);
1541 if (obj_priv->pin_count != 0)
1542 list_del_init(&obj_priv->list);
1544 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1546 obj_priv->last_rendering_seqno = 0;
1547 if (obj_priv->active) {
1548 obj_priv->active = 0;
1549 drm_gem_object_unreference(obj);
1551 i915_verify_inactive(dev, __FILE__, __LINE__);
1555 * Creates a new sequence number, emitting a write of it to the status page
1556 * plus an interrupt, which will trigger i915_user_interrupt_handler.
1558 * Must be called with struct_lock held.
1560 * Returned sequence numbers are nonzero on success.
1563 i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1564 uint32_t flush_domains)
1566 drm_i915_private_t *dev_priv = dev->dev_private;
1567 struct drm_i915_file_private *i915_file_priv = NULL;
1568 struct drm_i915_gem_request *request;
1573 if (file_priv != NULL)
1574 i915_file_priv = file_priv->driver_priv;
1576 request = kzalloc(sizeof(*request), GFP_KERNEL);
1577 if (request == NULL)
1580 /* Grab the seqno we're going to make this request be, and bump the
1581 * next (skipping 0 so it can be the reserved no-seqno value).
1583 seqno = dev_priv->mm.next_gem_seqno;
1584 dev_priv->mm.next_gem_seqno++;
1585 if (dev_priv->mm.next_gem_seqno == 0)
1586 dev_priv->mm.next_gem_seqno++;
1589 OUT_RING(MI_STORE_DWORD_INDEX);
1590 OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1593 OUT_RING(MI_USER_INTERRUPT);
1596 DRM_DEBUG("%d\n", seqno);
1598 request->seqno = seqno;
1599 request->emitted_jiffies = jiffies;
1600 was_empty = list_empty(&dev_priv->mm.request_list);
1601 list_add_tail(&request->list, &dev_priv->mm.request_list);
1602 if (i915_file_priv) {
1603 list_add_tail(&request->client_list,
1604 &i915_file_priv->mm.request_list);
1606 INIT_LIST_HEAD(&request->client_list);
1609 /* Associate any objects on the flushing list matching the write
1610 * domain we're flushing with our flush.
1612 if (flush_domains != 0) {
1613 struct drm_i915_gem_object *obj_priv, *next;
1615 list_for_each_entry_safe(obj_priv, next,
1616 &dev_priv->mm.flushing_list, list) {
1617 struct drm_gem_object *obj = obj_priv->obj;
1619 if ((obj->write_domain & flush_domains) ==
1620 obj->write_domain) {
1621 uint32_t old_write_domain = obj->write_domain;
1623 obj->write_domain = 0;
1624 i915_gem_object_move_to_active(obj, seqno);
1626 trace_i915_gem_object_change_domain(obj,
1634 if (!dev_priv->mm.suspended) {
1635 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1637 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1643 * Command execution barrier
1645 * Ensures that all commands in the ring are finished
1646 * before signalling the CPU
1649 i915_retire_commands(struct drm_device *dev)
1651 drm_i915_private_t *dev_priv = dev->dev_private;
1652 uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1653 uint32_t flush_domains = 0;
1656 /* The sampler always gets flushed on i965 (sigh) */
1658 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1661 OUT_RING(0); /* noop */
1663 return flush_domains;
1667 * Moves buffers associated only with the given active seqno from the active
1668 * to inactive list, potentially freeing them.
1671 i915_gem_retire_request(struct drm_device *dev,
1672 struct drm_i915_gem_request *request)
1674 drm_i915_private_t *dev_priv = dev->dev_private;
1676 trace_i915_gem_request_retire(dev, request->seqno);
1678 /* Move any buffers on the active list that are no longer referenced
1679 * by the ringbuffer to the flushing/inactive lists as appropriate.
1681 spin_lock(&dev_priv->mm.active_list_lock);
1682 while (!list_empty(&dev_priv->mm.active_list)) {
1683 struct drm_gem_object *obj;
1684 struct drm_i915_gem_object *obj_priv;
1686 obj_priv = list_first_entry(&dev_priv->mm.active_list,
1687 struct drm_i915_gem_object,
1689 obj = obj_priv->obj;
1691 /* If the seqno being retired doesn't match the oldest in the
1692 * list, then the oldest in the list must still be newer than
1695 if (obj_priv->last_rendering_seqno != request->seqno)
1699 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1700 __func__, request->seqno, obj);
1703 if (obj->write_domain != 0)
1704 i915_gem_object_move_to_flushing(obj);
1706 /* Take a reference on the object so it won't be
1707 * freed while the spinlock is held. The list
1708 * protection for this spinlock is safe when breaking
1709 * the lock like this since the next thing we do
1710 * is just get the head of the list again.
1712 drm_gem_object_reference(obj);
1713 i915_gem_object_move_to_inactive(obj);
1714 spin_unlock(&dev_priv->mm.active_list_lock);
1715 drm_gem_object_unreference(obj);
1716 spin_lock(&dev_priv->mm.active_list_lock);
1720 spin_unlock(&dev_priv->mm.active_list_lock);
1724 * Returns true if seq1 is later than seq2.
1727 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1729 return (int32_t)(seq1 - seq2) >= 0;
1733 i915_get_gem_seqno(struct drm_device *dev)
1735 drm_i915_private_t *dev_priv = dev->dev_private;
1737 return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
1741 * This function clears the request list as sequence numbers are passed.
1744 i915_gem_retire_requests(struct drm_device *dev)
1746 drm_i915_private_t *dev_priv = dev->dev_private;
1749 if (!dev_priv->hw_status_page)
1752 seqno = i915_get_gem_seqno(dev);
1754 while (!list_empty(&dev_priv->mm.request_list)) {
1755 struct drm_i915_gem_request *request;
1756 uint32_t retiring_seqno;
1758 request = list_first_entry(&dev_priv->mm.request_list,
1759 struct drm_i915_gem_request,
1761 retiring_seqno = request->seqno;
1763 if (i915_seqno_passed(seqno, retiring_seqno) ||
1764 atomic_read(&dev_priv->mm.wedged)) {
1765 i915_gem_retire_request(dev, request);
1767 list_del(&request->list);
1768 list_del(&request->client_list);
1776 i915_gem_retire_work_handler(struct work_struct *work)
1778 drm_i915_private_t *dev_priv;
1779 struct drm_device *dev;
1781 dev_priv = container_of(work, drm_i915_private_t,
1782 mm.retire_work.work);
1783 dev = dev_priv->dev;
1785 mutex_lock(&dev->struct_mutex);
1786 i915_gem_retire_requests(dev);
1787 if (!dev_priv->mm.suspended &&
1788 !list_empty(&dev_priv->mm.request_list))
1789 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1790 mutex_unlock(&dev->struct_mutex);
1794 * Waits for a sequence number to be signaled, and cleans up the
1795 * request and object lists appropriately for that event.
1798 i915_wait_request(struct drm_device *dev, uint32_t seqno)
1800 drm_i915_private_t *dev_priv = dev->dev_private;
1806 if (atomic_read(&dev_priv->mm.wedged))
1809 if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
1811 ier = I915_READ(DEIER) | I915_READ(GTIER);
1813 ier = I915_READ(IER);
1815 DRM_ERROR("something (likely vbetool) disabled "
1816 "interrupts, re-enabling\n");
1817 i915_driver_irq_preinstall(dev);
1818 i915_driver_irq_postinstall(dev);
1821 trace_i915_gem_request_wait_begin(dev, seqno);
1823 dev_priv->mm.waiting_gem_seqno = seqno;
1824 i915_user_irq_get(dev);
1825 ret = wait_event_interruptible(dev_priv->irq_queue,
1826 i915_seqno_passed(i915_get_gem_seqno(dev),
1828 atomic_read(&dev_priv->mm.wedged));
1829 i915_user_irq_put(dev);
1830 dev_priv->mm.waiting_gem_seqno = 0;
1832 trace_i915_gem_request_wait_end(dev, seqno);
1834 if (atomic_read(&dev_priv->mm.wedged))
1837 if (ret && ret != -ERESTARTSYS)
1838 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1839 __func__, ret, seqno, i915_get_gem_seqno(dev));
1841 /* Directly dispatch request retiring. While we have the work queue
1842 * to handle this, the waiter on a request often wants an associated
1843 * buffer to have made it to the inactive list, and we would need
1844 * a separate wait queue to handle that.
1847 i915_gem_retire_requests(dev);
1853 i915_gem_flush(struct drm_device *dev,
1854 uint32_t invalidate_domains,
1855 uint32_t flush_domains)
1857 drm_i915_private_t *dev_priv = dev->dev_private;
1862 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
1863 invalidate_domains, flush_domains);
1865 trace_i915_gem_request_flush(dev, dev_priv->mm.next_gem_seqno,
1866 invalidate_domains, flush_domains);
1868 if (flush_domains & I915_GEM_DOMAIN_CPU)
1869 drm_agp_chipset_flush(dev);
1871 if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
1873 * read/write caches:
1875 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1876 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
1877 * also flushed at 2d versus 3d pipeline switches.
1881 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1882 * MI_READ_FLUSH is set, and is always flushed on 965.
1884 * I915_GEM_DOMAIN_COMMAND may not exist?
1886 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1887 * invalidated when MI_EXE_FLUSH is set.
1889 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1890 * invalidated with every MI_FLUSH.
1894 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1895 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1896 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1897 * are flushed at any MI_FLUSH.
1900 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1901 if ((invalidate_domains|flush_domains) &
1902 I915_GEM_DOMAIN_RENDER)
1903 cmd &= ~MI_NO_WRITE_FLUSH;
1904 if (!IS_I965G(dev)) {
1906 * On the 965, the sampler cache always gets flushed
1907 * and this bit is reserved.
1909 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
1910 cmd |= MI_READ_FLUSH;
1912 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
1913 cmd |= MI_EXE_FLUSH;
1916 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
1920 OUT_RING(0); /* noop */
1926 * Ensures that all rendering to the object has completed and the object is
1927 * safe to unbind from the GTT or access from the CPU.
1930 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1932 struct drm_device *dev = obj->dev;
1933 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1936 /* This function only exists to support waiting for existing rendering,
1937 * not for emitting required flushes.
1939 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
1941 /* If there is rendering queued on the buffer being evicted, wait for
1944 if (obj_priv->active) {
1946 DRM_INFO("%s: object %p wait for seqno %08x\n",
1947 __func__, obj, obj_priv->last_rendering_seqno);
1949 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
1958 * Unbinds an object from the GTT aperture.
1961 i915_gem_object_unbind(struct drm_gem_object *obj)
1963 struct drm_device *dev = obj->dev;
1964 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1968 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1969 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1971 if (obj_priv->gtt_space == NULL)
1974 if (obj_priv->pin_count != 0) {
1975 DRM_ERROR("Attempting to unbind pinned buffer\n");
1979 /* blow away mappings if mapped through GTT */
1980 i915_gem_release_mmap(obj);
1982 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
1983 i915_gem_clear_fence_reg(obj);
1985 /* Move the object to the CPU domain to ensure that
1986 * any possible CPU writes while it's not in the GTT
1987 * are flushed when we go to remap it. This will
1988 * also ensure that all pending GPU writes are finished
1991 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1993 if (ret != -ERESTARTSYS)
1994 DRM_ERROR("set_domain failed: %d\n", ret);
1998 BUG_ON(obj_priv->active);
2000 if (obj_priv->agp_mem != NULL) {
2001 drm_unbind_agp(obj_priv->agp_mem);
2002 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
2003 obj_priv->agp_mem = NULL;
2006 i915_gem_object_put_pages(obj);
2008 if (obj_priv->gtt_space) {
2009 atomic_dec(&dev->gtt_count);
2010 atomic_sub(obj->size, &dev->gtt_memory);
2012 drm_mm_put_block(obj_priv->gtt_space);
2013 obj_priv->gtt_space = NULL;
2016 /* Remove ourselves from the LRU list if present. */
2017 if (!list_empty(&obj_priv->list))
2018 list_del_init(&obj_priv->list);
2020 trace_i915_gem_object_unbind(obj);
2026 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
2028 return !obj_priv->dirty || obj_priv->madv == I915_MADV_DONTNEED;
2031 static struct drm_gem_object *
2032 i915_gem_find_inactive_object(struct drm_device *dev, int min_size)
2034 drm_i915_private_t *dev_priv = dev->dev_private;
2035 struct drm_i915_gem_object *obj_priv;
2036 struct drm_gem_object *best = NULL;
2037 struct drm_gem_object *first = NULL;
2039 /* Try to find the smallest clean object */
2040 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
2041 struct drm_gem_object *obj = obj_priv->obj;
2042 if (obj->size >= min_size) {
2043 if (i915_gem_object_is_purgeable(obj_priv) &&
2044 (!best || obj->size < best->size)) {
2046 if (best->size == min_size)
2054 return best ? best : first;
2058 i915_gem_evict_everything(struct drm_device *dev)
2060 drm_i915_private_t *dev_priv = dev->dev_private;
2065 DRM_INFO("GTT full, evicting everything: "
2066 "%d objects [%d pinned], "
2067 "%d object bytes [%d pinned], "
2068 "%d/%d gtt bytes\n",
2069 atomic_read(&dev->object_count),
2070 atomic_read(&dev->pin_count),
2071 atomic_read(&dev->object_memory),
2072 atomic_read(&dev->pin_memory),
2073 atomic_read(&dev->gtt_memory),
2076 spin_lock(&dev_priv->mm.active_list_lock);
2077 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2078 list_empty(&dev_priv->mm.flushing_list) &&
2079 list_empty(&dev_priv->mm.active_list));
2080 spin_unlock(&dev_priv->mm.active_list_lock);
2083 DRM_ERROR("GTT full, but lists empty!\n");
2087 /* Flush everything (on to the inactive lists) and evict */
2088 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2089 seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
2093 ret = i915_wait_request(dev, seqno);
2097 ret = i915_gem_evict_from_inactive_list(dev);
2101 spin_lock(&dev_priv->mm.active_list_lock);
2102 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2103 list_empty(&dev_priv->mm.flushing_list) &&
2104 list_empty(&dev_priv->mm.active_list));
2105 spin_unlock(&dev_priv->mm.active_list_lock);
2106 BUG_ON(!lists_empty);
2112 i915_gem_evict_something(struct drm_device *dev, int min_size)
2114 drm_i915_private_t *dev_priv = dev->dev_private;
2115 struct drm_gem_object *obj;
2116 int have_waited = 0;
2120 i915_gem_retire_requests(dev);
2122 /* If there's an inactive buffer available now, grab it
2125 obj = i915_gem_find_inactive_object(dev, min_size);
2127 struct drm_i915_gem_object *obj_priv;
2130 DRM_INFO("%s: evicting %p\n", __func__, obj);
2132 obj_priv = obj->driver_private;
2133 BUG_ON(obj_priv->pin_count != 0);
2134 BUG_ON(obj_priv->active);
2136 /* Wait on the rendering and unbind the buffer. */
2137 return i915_gem_object_unbind(obj);
2143 /* If we didn't get anything, but the ring is still processing
2144 * things, wait for the next to finish and hopefully leave us
2145 * a buffer to evict.
2147 if (!list_empty(&dev_priv->mm.request_list)) {
2148 struct drm_i915_gem_request *request;
2150 request = list_first_entry(&dev_priv->mm.request_list,
2151 struct drm_i915_gem_request,
2154 ret = i915_wait_request(dev, request->seqno);
2162 /* If we didn't have anything on the request list but there
2163 * are buffers awaiting a flush, emit one and try again.
2164 * When we wait on it, those buffers waiting for that flush
2165 * will get moved to inactive.
2167 if (!list_empty(&dev_priv->mm.flushing_list)) {
2168 struct drm_i915_gem_object *obj_priv;
2171 obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
2172 struct drm_i915_gem_object,
2174 obj = obj_priv->obj;
2179 seqno = i915_add_request(dev, NULL, obj->write_domain);
2183 ret = i915_wait_request(dev, seqno);
2191 /* If we didn't do any of the above, there's no single buffer
2192 * large enough to swap out for the new one, so just evict
2193 * everything and start again. (This should be rare.)
2195 if (!list_empty (&dev_priv->mm.inactive_list)) {
2196 DRM_INFO("GTT full, evicting inactive buffers\n");
2197 return i915_gem_evict_from_inactive_list(dev);
2199 return i915_gem_evict_everything(dev);
2204 i915_gem_object_get_pages(struct drm_gem_object *obj)
2206 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2208 struct address_space *mapping;
2209 struct inode *inode;
2213 if (obj_priv->pages_refcount++ != 0)
2216 /* Get the list of pages out of our struct file. They'll be pinned
2217 * at this point until we release them.
2219 page_count = obj->size / PAGE_SIZE;
2220 BUG_ON(obj_priv->pages != NULL);
2221 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
2222 if (obj_priv->pages == NULL) {
2223 DRM_ERROR("Failed to allocate page list\n");
2224 obj_priv->pages_refcount--;
2228 inode = obj->filp->f_path.dentry->d_inode;
2229 mapping = inode->i_mapping;
2230 for (i = 0; i < page_count; i++) {
2231 page = read_mapping_page(mapping, i, NULL);
2233 ret = PTR_ERR(page);
2234 i915_gem_object_put_pages(obj);
2237 obj_priv->pages[i] = page;
2240 if (obj_priv->tiling_mode != I915_TILING_NONE)
2241 i915_gem_object_do_bit_17_swizzle(obj);
2246 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2248 struct drm_gem_object *obj = reg->obj;
2249 struct drm_device *dev = obj->dev;
2250 drm_i915_private_t *dev_priv = dev->dev_private;
2251 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2252 int regnum = obj_priv->fence_reg;
2255 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2257 val |= obj_priv->gtt_offset & 0xfffff000;
2258 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2259 if (obj_priv->tiling_mode == I915_TILING_Y)
2260 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2261 val |= I965_FENCE_REG_VALID;
2263 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2266 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2268 struct drm_gem_object *obj = reg->obj;
2269 struct drm_device *dev = obj->dev;
2270 drm_i915_private_t *dev_priv = dev->dev_private;
2271 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2272 int regnum = obj_priv->fence_reg;
2274 uint32_t fence_reg, val;
2277 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2278 (obj_priv->gtt_offset & (obj->size - 1))) {
2279 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2280 __func__, obj_priv->gtt_offset, obj->size);
2284 if (obj_priv->tiling_mode == I915_TILING_Y &&
2285 HAS_128_BYTE_Y_TILING(dev))
2290 /* Note: pitch better be a power of two tile widths */
2291 pitch_val = obj_priv->stride / tile_width;
2292 pitch_val = ffs(pitch_val) - 1;
2294 val = obj_priv->gtt_offset;
2295 if (obj_priv->tiling_mode == I915_TILING_Y)
2296 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2297 val |= I915_FENCE_SIZE_BITS(obj->size);
2298 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2299 val |= I830_FENCE_REG_VALID;
2302 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2304 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2305 I915_WRITE(fence_reg, val);
2308 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2310 struct drm_gem_object *obj = reg->obj;
2311 struct drm_device *dev = obj->dev;
2312 drm_i915_private_t *dev_priv = dev->dev_private;
2313 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2314 int regnum = obj_priv->fence_reg;
2317 uint32_t fence_size_bits;
2319 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
2320 (obj_priv->gtt_offset & (obj->size - 1))) {
2321 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2322 __func__, obj_priv->gtt_offset);
2326 pitch_val = obj_priv->stride / 128;
2327 pitch_val = ffs(pitch_val) - 1;
2328 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2330 val = obj_priv->gtt_offset;
2331 if (obj_priv->tiling_mode == I915_TILING_Y)
2332 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2333 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2334 WARN_ON(fence_size_bits & ~0x00000f00);
2335 val |= fence_size_bits;
2336 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2337 val |= I830_FENCE_REG_VALID;
2339 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
2343 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2344 * @obj: object to map through a fence reg
2346 * When mapping objects through the GTT, userspace wants to be able to write
2347 * to them without having to worry about swizzling if the object is tiled.
2349 * This function walks the fence regs looking for a free one for @obj,
2350 * stealing one if it can't find any.
2352 * It then sets up the reg based on the object's properties: address, pitch
2353 * and tiling format.
2356 i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
2358 struct drm_device *dev = obj->dev;
2359 struct drm_i915_private *dev_priv = dev->dev_private;
2360 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2361 struct drm_i915_fence_reg *reg = NULL;
2362 struct drm_i915_gem_object *old_obj_priv = NULL;
2365 /* Just update our place in the LRU if our fence is getting used. */
2366 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2367 list_move_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2371 switch (obj_priv->tiling_mode) {
2372 case I915_TILING_NONE:
2373 WARN(1, "allocating a fence for non-tiled object?\n");
2376 if (!obj_priv->stride)
2378 WARN((obj_priv->stride & (512 - 1)),
2379 "object 0x%08x is X tiled but has non-512B pitch\n",
2380 obj_priv->gtt_offset);
2383 if (!obj_priv->stride)
2385 WARN((obj_priv->stride & (128 - 1)),
2386 "object 0x%08x is Y tiled but has non-128B pitch\n",
2387 obj_priv->gtt_offset);
2391 /* First try to find a free reg */
2393 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2394 reg = &dev_priv->fence_regs[i];
2398 old_obj_priv = reg->obj->driver_private;
2399 if (!old_obj_priv->pin_count)
2403 /* None available, try to steal one or wait for a user to finish */
2404 if (i == dev_priv->num_fence_regs) {
2405 struct drm_gem_object *old_obj = NULL;
2410 list_for_each_entry(old_obj_priv, &dev_priv->mm.fence_list,
2412 old_obj = old_obj_priv->obj;
2414 if (old_obj_priv->pin_count)
2417 /* Take a reference, as otherwise the wait_rendering
2418 * below may cause the object to get freed out from
2421 drm_gem_object_reference(old_obj);
2423 /* i915 uses fences for GPU access to tiled buffers */
2424 if (IS_I965G(dev) || !old_obj_priv->active)
2427 /* This brings the object to the head of the LRU if it
2428 * had been written to. The only way this should
2429 * result in us waiting longer than the expected
2430 * optimal amount of time is if there was a
2431 * fence-using buffer later that was read-only.
2433 i915_gem_object_flush_gpu_write_domain(old_obj);
2434 ret = i915_gem_object_wait_rendering(old_obj);
2436 drm_gem_object_unreference(old_obj);
2444 * Zap this virtual mapping so we can set up a fence again
2445 * for this object next time we need it.
2447 i915_gem_release_mmap(old_obj);
2449 i = old_obj_priv->fence_reg;
2450 reg = &dev_priv->fence_regs[i];
2452 old_obj_priv->fence_reg = I915_FENCE_REG_NONE;
2453 list_del_init(&old_obj_priv->fence_list);
2455 drm_gem_object_unreference(old_obj);
2458 obj_priv->fence_reg = i;
2459 list_add_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2464 i965_write_fence_reg(reg);
2465 else if (IS_I9XX(dev))
2466 i915_write_fence_reg(reg);
2468 i830_write_fence_reg(reg);
2470 trace_i915_gem_object_get_fence(obj, i, obj_priv->tiling_mode);
2476 * i915_gem_clear_fence_reg - clear out fence register info
2477 * @obj: object to clear
2479 * Zeroes out the fence register itself and clears out the associated
2480 * data structures in dev_priv and obj_priv.
2483 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2485 struct drm_device *dev = obj->dev;
2486 drm_i915_private_t *dev_priv = dev->dev_private;
2487 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2490 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
2494 if (obj_priv->fence_reg < 8)
2495 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2497 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2500 I915_WRITE(fence_reg, 0);
2503 dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL;
2504 obj_priv->fence_reg = I915_FENCE_REG_NONE;
2505 list_del_init(&obj_priv->fence_list);
2509 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2510 * to the buffer to finish, and then resets the fence register.
2511 * @obj: tiled object holding a fence register.
2513 * Zeroes out the fence register itself and clears out the associated
2514 * data structures in dev_priv and obj_priv.
2517 i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2519 struct drm_device *dev = obj->dev;
2520 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2522 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2525 /* On the i915, GPU access to tiled buffers is via a fence,
2526 * therefore we must wait for any outstanding access to complete
2527 * before clearing the fence.
2529 if (!IS_I965G(dev)) {
2532 i915_gem_object_flush_gpu_write_domain(obj);
2533 i915_gem_object_flush_gtt_write_domain(obj);
2534 ret = i915_gem_object_wait_rendering(obj);
2539 i915_gem_clear_fence_reg (obj);
2545 * Finds free space in the GTT aperture and binds the object there.
2548 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2550 struct drm_device *dev = obj->dev;
2551 drm_i915_private_t *dev_priv = dev->dev_private;
2552 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2553 struct drm_mm_node *free_space;
2554 bool retry_alloc = false;
2557 if (dev_priv->mm.suspended)
2560 if (obj_priv->madv == I915_MADV_DONTNEED) {
2561 DRM_ERROR("Attempting to bind a purgeable object\n");
2566 alignment = i915_gem_get_gtt_alignment(obj);
2567 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
2568 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2573 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2574 obj->size, alignment, 0);
2575 if (free_space != NULL) {
2576 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2578 if (obj_priv->gtt_space != NULL) {
2579 obj_priv->gtt_space->private = obj;
2580 obj_priv->gtt_offset = obj_priv->gtt_space->start;
2583 if (obj_priv->gtt_space == NULL) {
2584 /* If the gtt is empty and we're still having trouble
2585 * fitting our object in, we're out of memory.
2588 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2590 ret = i915_gem_evict_something(dev, obj->size);
2592 if (ret != -ERESTARTSYS)
2593 DRM_ERROR("Failed to evict a buffer %d\n", ret);
2600 DRM_INFO("Binding object of size %zd at 0x%08x\n",
2601 obj->size, obj_priv->gtt_offset);
2604 i915_gem_object_set_page_gfp_mask (obj,
2605 i915_gem_object_get_page_gfp_mask (obj) & ~__GFP_NORETRY);
2607 ret = i915_gem_object_get_pages(obj);
2609 i915_gem_object_set_page_gfp_mask (obj,
2610 i915_gem_object_get_page_gfp_mask (obj) | __GFP_NORETRY);
2613 drm_mm_put_block(obj_priv->gtt_space);
2614 obj_priv->gtt_space = NULL;
2616 if (ret == -ENOMEM) {
2617 /* first try to clear up some space from the GTT */
2618 ret = i915_gem_evict_something(dev, obj->size);
2620 if (ret != -ERESTARTSYS)
2621 DRM_ERROR("Failed to allocate space for backing pages %d\n", ret);
2623 /* now try to shrink everyone else */
2624 if (! retry_alloc) {
2638 /* Create an AGP memory structure pointing at our pages, and bind it
2641 obj_priv->agp_mem = drm_agp_bind_pages(dev,
2643 obj->size >> PAGE_SHIFT,
2644 obj_priv->gtt_offset,
2645 obj_priv->agp_type);
2646 if (obj_priv->agp_mem == NULL) {
2647 i915_gem_object_put_pages(obj);
2648 drm_mm_put_block(obj_priv->gtt_space);
2649 obj_priv->gtt_space = NULL;
2651 ret = i915_gem_evict_something(dev, obj->size);
2653 if (ret != -ERESTARTSYS)
2654 DRM_ERROR("Failed to allocate space to bind AGP: %d\n", ret);
2660 atomic_inc(&dev->gtt_count);
2661 atomic_add(obj->size, &dev->gtt_memory);
2663 /* Assert that the object is not currently in any GPU domain. As it
2664 * wasn't in the GTT, there shouldn't be any way it could have been in
2667 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2668 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
2670 trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2676 i915_gem_clflush_object(struct drm_gem_object *obj)
2678 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2680 /* If we don't have a page list set up, then we're not pinned
2681 * to GPU, and we can ignore the cache flush because it'll happen
2682 * again at bind time.
2684 if (obj_priv->pages == NULL)
2687 trace_i915_gem_object_clflush(obj);
2689 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2692 /** Flushes any GPU write domain for the object if it's dirty. */
2694 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2696 struct drm_device *dev = obj->dev;
2698 uint32_t old_write_domain;
2700 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2703 /* Queue the GPU write cache flushing we need. */
2704 old_write_domain = obj->write_domain;
2705 i915_gem_flush(dev, 0, obj->write_domain);
2706 seqno = i915_add_request(dev, NULL, obj->write_domain);
2707 obj->write_domain = 0;
2708 i915_gem_object_move_to_active(obj, seqno);
2710 trace_i915_gem_object_change_domain(obj,
2715 /** Flushes the GTT write domain for the object if it's dirty. */
2717 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2719 uint32_t old_write_domain;
2721 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2724 /* No actual flushing is required for the GTT write domain. Writes
2725 * to it immediately go to main memory as far as we know, so there's
2726 * no chipset flush. It also doesn't land in render cache.
2728 old_write_domain = obj->write_domain;
2729 obj->write_domain = 0;
2731 trace_i915_gem_object_change_domain(obj,
2736 /** Flushes the CPU write domain for the object if it's dirty. */
2738 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2740 struct drm_device *dev = obj->dev;
2741 uint32_t old_write_domain;
2743 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2746 i915_gem_clflush_object(obj);
2747 drm_agp_chipset_flush(dev);
2748 old_write_domain = obj->write_domain;
2749 obj->write_domain = 0;
2751 trace_i915_gem_object_change_domain(obj,
2757 * Moves a single object to the GTT read, and possibly write domain.
2759 * This function returns when the move is complete, including waiting on
2763 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2765 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2766 uint32_t old_write_domain, old_read_domains;
2769 /* Not valid to be called on unbound objects. */
2770 if (obj_priv->gtt_space == NULL)
2773 i915_gem_object_flush_gpu_write_domain(obj);
2774 /* Wait on any GPU rendering and flushing to occur. */
2775 ret = i915_gem_object_wait_rendering(obj);
2779 old_write_domain = obj->write_domain;
2780 old_read_domains = obj->read_domains;
2782 /* If we're writing through the GTT domain, then CPU and GPU caches
2783 * will need to be invalidated at next use.
2786 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2788 i915_gem_object_flush_cpu_write_domain(obj);
2790 /* It should now be out of any other write domains, and we can update
2791 * the domain values for our changes.
2793 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2794 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2796 obj->write_domain = I915_GEM_DOMAIN_GTT;
2797 obj_priv->dirty = 1;
2800 trace_i915_gem_object_change_domain(obj,
2808 * Moves a single object to the CPU read, and possibly write domain.
2810 * This function returns when the move is complete, including waiting on
2814 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2816 uint32_t old_write_domain, old_read_domains;
2819 i915_gem_object_flush_gpu_write_domain(obj);
2820 /* Wait on any GPU rendering and flushing to occur. */
2821 ret = i915_gem_object_wait_rendering(obj);
2825 i915_gem_object_flush_gtt_write_domain(obj);
2827 /* If we have a partially-valid cache of the object in the CPU,
2828 * finish invalidating it and free the per-page flags.
2830 i915_gem_object_set_to_full_cpu_read_domain(obj);
2832 old_write_domain = obj->write_domain;
2833 old_read_domains = obj->read_domains;
2835 /* Flush the CPU cache if it's still invalid. */
2836 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2837 i915_gem_clflush_object(obj);
2839 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2842 /* It should now be out of any other write domains, and we can update
2843 * the domain values for our changes.
2845 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2847 /* If we're writing through the CPU, then the GPU read domains will
2848 * need to be invalidated at next use.
2851 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2852 obj->write_domain = I915_GEM_DOMAIN_CPU;
2855 trace_i915_gem_object_change_domain(obj,
2863 * Set the next domain for the specified object. This
2864 * may not actually perform the necessary flushing/invaliding though,
2865 * as that may want to be batched with other set_domain operations
2867 * This is (we hope) the only really tricky part of gem. The goal
2868 * is fairly simple -- track which caches hold bits of the object
2869 * and make sure they remain coherent. A few concrete examples may
2870 * help to explain how it works. For shorthand, we use the notation
2871 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2872 * a pair of read and write domain masks.
2874 * Case 1: the batch buffer
2880 * 5. Unmapped from GTT
2883 * Let's take these a step at a time
2886 * Pages allocated from the kernel may still have
2887 * cache contents, so we set them to (CPU, CPU) always.
2888 * 2. Written by CPU (using pwrite)
2889 * The pwrite function calls set_domain (CPU, CPU) and
2890 * this function does nothing (as nothing changes)
2892 * This function asserts that the object is not
2893 * currently in any GPU-based read or write domains
2895 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2896 * As write_domain is zero, this function adds in the
2897 * current read domains (CPU+COMMAND, 0).
2898 * flush_domains is set to CPU.
2899 * invalidate_domains is set to COMMAND
2900 * clflush is run to get data out of the CPU caches
2901 * then i915_dev_set_domain calls i915_gem_flush to
2902 * emit an MI_FLUSH and drm_agp_chipset_flush
2903 * 5. Unmapped from GTT
2904 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2905 * flush_domains and invalidate_domains end up both zero
2906 * so no flushing/invalidating happens
2910 * Case 2: The shared render buffer
2914 * 3. Read/written by GPU
2915 * 4. set_domain to (CPU,CPU)
2916 * 5. Read/written by CPU
2917 * 6. Read/written by GPU
2920 * Same as last example, (CPU, CPU)
2922 * Nothing changes (assertions find that it is not in the GPU)
2923 * 3. Read/written by GPU
2924 * execbuffer calls set_domain (RENDER, RENDER)
2925 * flush_domains gets CPU
2926 * invalidate_domains gets GPU
2928 * MI_FLUSH and drm_agp_chipset_flush
2929 * 4. set_domain (CPU, CPU)
2930 * flush_domains gets GPU
2931 * invalidate_domains gets CPU
2932 * wait_rendering (obj) to make sure all drawing is complete.
2933 * This will include an MI_FLUSH to get the data from GPU
2935 * clflush (obj) to invalidate the CPU cache
2936 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
2937 * 5. Read/written by CPU
2938 * cache lines are loaded and dirtied
2939 * 6. Read written by GPU
2940 * Same as last GPU access
2942 * Case 3: The constant buffer
2947 * 4. Updated (written) by CPU again
2956 * flush_domains = CPU
2957 * invalidate_domains = RENDER
2960 * drm_agp_chipset_flush
2961 * 4. Updated (written) by CPU again
2963 * flush_domains = 0 (no previous write domain)
2964 * invalidate_domains = 0 (no new read domains)
2967 * flush_domains = CPU
2968 * invalidate_domains = RENDER
2971 * drm_agp_chipset_flush
2974 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
2976 struct drm_device *dev = obj->dev;
2977 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2978 uint32_t invalidate_domains = 0;
2979 uint32_t flush_domains = 0;
2980 uint32_t old_read_domains;
2982 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
2983 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
2985 intel_mark_busy(dev, obj);
2988 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2990 obj->read_domains, obj->pending_read_domains,
2991 obj->write_domain, obj->pending_write_domain);
2994 * If the object isn't moving to a new write domain,
2995 * let the object stay in multiple read domains
2997 if (obj->pending_write_domain == 0)
2998 obj->pending_read_domains |= obj->read_domains;
3000 obj_priv->dirty = 1;
3003 * Flush the current write domain if
3004 * the new read domains don't match. Invalidate
3005 * any read domains which differ from the old
3008 if (obj->write_domain &&
3009 obj->write_domain != obj->pending_read_domains) {
3010 flush_domains |= obj->write_domain;
3011 invalidate_domains |=
3012 obj->pending_read_domains & ~obj->write_domain;
3015 * Invalidate any read caches which may have
3016 * stale data. That is, any new read domains.
3018 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
3019 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
3021 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3022 __func__, flush_domains, invalidate_domains);
3024 i915_gem_clflush_object(obj);
3027 old_read_domains = obj->read_domains;
3029 /* The actual obj->write_domain will be updated with
3030 * pending_write_domain after we emit the accumulated flush for all
3031 * of our domain changes in execbuffers (which clears objects'
3032 * write_domains). So if we have a current write domain that we
3033 * aren't changing, set pending_write_domain to that.
3035 if (flush_domains == 0 && obj->pending_write_domain == 0)
3036 obj->pending_write_domain = obj->write_domain;
3037 obj->read_domains = obj->pending_read_domains;
3039 dev->invalidate_domains |= invalidate_domains;
3040 dev->flush_domains |= flush_domains;
3042 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3044 obj->read_domains, obj->write_domain,
3045 dev->invalidate_domains, dev->flush_domains);
3048 trace_i915_gem_object_change_domain(obj,
3054 * Moves the object from a partially CPU read to a full one.
3056 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3057 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3060 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
3062 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3064 if (!obj_priv->page_cpu_valid)
3067 /* If we're partially in the CPU read domain, finish moving it in.
3069 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3072 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3073 if (obj_priv->page_cpu_valid[i])
3075 drm_clflush_pages(obj_priv->pages + i, 1);
3079 /* Free the page_cpu_valid mappings which are now stale, whether
3080 * or not we've got I915_GEM_DOMAIN_CPU.
3082 kfree(obj_priv->page_cpu_valid);
3083 obj_priv->page_cpu_valid = NULL;
3087 * Set the CPU read domain on a range of the object.
3089 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3090 * not entirely valid. The page_cpu_valid member of the object flags which
3091 * pages have been flushed, and will be respected by
3092 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3093 * of the whole object.
3095 * This function returns when the move is complete, including waiting on
3099 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3100 uint64_t offset, uint64_t size)
3102 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3103 uint32_t old_read_domains;
3106 if (offset == 0 && size == obj->size)
3107 return i915_gem_object_set_to_cpu_domain(obj, 0);
3109 i915_gem_object_flush_gpu_write_domain(obj);
3110 /* Wait on any GPU rendering and flushing to occur. */
3111 ret = i915_gem_object_wait_rendering(obj);
3114 i915_gem_object_flush_gtt_write_domain(obj);
3116 /* If we're already fully in the CPU read domain, we're done. */
3117 if (obj_priv->page_cpu_valid == NULL &&
3118 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3121 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3122 * newly adding I915_GEM_DOMAIN_CPU
3124 if (obj_priv->page_cpu_valid == NULL) {
3125 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3127 if (obj_priv->page_cpu_valid == NULL)
3129 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3130 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
3132 /* Flush the cache on any pages that are still invalid from the CPU's
3135 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3137 if (obj_priv->page_cpu_valid[i])
3140 drm_clflush_pages(obj_priv->pages + i, 1);
3142 obj_priv->page_cpu_valid[i] = 1;
3145 /* It should now be out of any other write domains, and we can update
3146 * the domain values for our changes.
3148 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3150 old_read_domains = obj->read_domains;
3151 obj->read_domains |= I915_GEM_DOMAIN_CPU;
3153 trace_i915_gem_object_change_domain(obj,
3161 * Pin an object to the GTT and evaluate the relocations landing in it.
3164 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3165 struct drm_file *file_priv,
3166 struct drm_i915_gem_exec_object *entry,
3167 struct drm_i915_gem_relocation_entry *relocs)
3169 struct drm_device *dev = obj->dev;
3170 drm_i915_private_t *dev_priv = dev->dev_private;
3171 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3173 void __iomem *reloc_page;
3175 /* Choose the GTT offset for our buffer and put it there. */
3176 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3180 entry->offset = obj_priv->gtt_offset;
3182 /* Apply the relocations, using the GTT aperture to avoid cache
3183 * flushing requirements.
3185 for (i = 0; i < entry->relocation_count; i++) {
3186 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
3187 struct drm_gem_object *target_obj;
3188 struct drm_i915_gem_object *target_obj_priv;
3189 uint32_t reloc_val, reloc_offset;
3190 uint32_t __iomem *reloc_entry;
3192 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
3193 reloc->target_handle);
3194 if (target_obj == NULL) {
3195 i915_gem_object_unpin(obj);
3198 target_obj_priv = target_obj->driver_private;
3201 DRM_INFO("%s: obj %p offset %08x target %d "
3202 "read %08x write %08x gtt %08x "
3203 "presumed %08x delta %08x\n",
3206 (int) reloc->offset,
3207 (int) reloc->target_handle,
3208 (int) reloc->read_domains,
3209 (int) reloc->write_domain,
3210 (int) target_obj_priv->gtt_offset,
3211 (int) reloc->presumed_offset,
3215 /* The target buffer should have appeared before us in the
3216 * exec_object list, so it should have a GTT space bound by now.
3218 if (target_obj_priv->gtt_space == NULL) {
3219 DRM_ERROR("No GTT space found for object %d\n",
3220 reloc->target_handle);
3221 drm_gem_object_unreference(target_obj);
3222 i915_gem_object_unpin(obj);
3226 /* Validate that the target is in a valid r/w GPU domain */
3227 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3228 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
3229 DRM_ERROR("reloc with read/write CPU domains: "
3230 "obj %p target %d offset %d "
3231 "read %08x write %08x",
3232 obj, reloc->target_handle,
3233 (int) reloc->offset,
3234 reloc->read_domains,
3235 reloc->write_domain);
3236 drm_gem_object_unreference(target_obj);
3237 i915_gem_object_unpin(obj);
3240 if (reloc->write_domain && target_obj->pending_write_domain &&
3241 reloc->write_domain != target_obj->pending_write_domain) {
3242 DRM_ERROR("Write domain conflict: "
3243 "obj %p target %d offset %d "
3244 "new %08x old %08x\n",
3245 obj, reloc->target_handle,
3246 (int) reloc->offset,
3247 reloc->write_domain,
3248 target_obj->pending_write_domain);
3249 drm_gem_object_unreference(target_obj);
3250 i915_gem_object_unpin(obj);
3254 target_obj->pending_read_domains |= reloc->read_domains;
3255 target_obj->pending_write_domain |= reloc->write_domain;
3257 /* If the relocation already has the right value in it, no
3258 * more work needs to be done.
3260 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
3261 drm_gem_object_unreference(target_obj);
3265 /* Check that the relocation address is valid... */
3266 if (reloc->offset > obj->size - 4) {
3267 DRM_ERROR("Relocation beyond object bounds: "
3268 "obj %p target %d offset %d size %d.\n",
3269 obj, reloc->target_handle,
3270 (int) reloc->offset, (int) obj->size);
3271 drm_gem_object_unreference(target_obj);
3272 i915_gem_object_unpin(obj);
3275 if (reloc->offset & 3) {
3276 DRM_ERROR("Relocation not 4-byte aligned: "
3277 "obj %p target %d offset %d.\n",
3278 obj, reloc->target_handle,
3279 (int) reloc->offset);
3280 drm_gem_object_unreference(target_obj);
3281 i915_gem_object_unpin(obj);
3285 /* and points to somewhere within the target object. */
3286 if (reloc->delta >= target_obj->size) {
3287 DRM_ERROR("Relocation beyond target object bounds: "
3288 "obj %p target %d delta %d size %d.\n",
3289 obj, reloc->target_handle,
3290 (int) reloc->delta, (int) target_obj->size);
3291 drm_gem_object_unreference(target_obj);
3292 i915_gem_object_unpin(obj);
3296 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3298 drm_gem_object_unreference(target_obj);
3299 i915_gem_object_unpin(obj);
3303 /* Map the page containing the relocation we're going to
3306 reloc_offset = obj_priv->gtt_offset + reloc->offset;
3307 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3310 reloc_entry = (uint32_t __iomem *)(reloc_page +
3311 (reloc_offset & (PAGE_SIZE - 1)));
3312 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
3315 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3316 obj, (unsigned int) reloc->offset,
3317 readl(reloc_entry), reloc_val);
3319 writel(reloc_val, reloc_entry);
3320 io_mapping_unmap_atomic(reloc_page);
3322 /* The updated presumed offset for this entry will be
3323 * copied back out to the user.
3325 reloc->presumed_offset = target_obj_priv->gtt_offset;
3327 drm_gem_object_unreference(target_obj);
3332 i915_gem_dump_object(obj, 128, __func__, ~0);
3337 /** Dispatch a batchbuffer to the ring
3340 i915_dispatch_gem_execbuffer(struct drm_device *dev,
3341 struct drm_i915_gem_execbuffer *exec,
3342 struct drm_clip_rect *cliprects,
3343 uint64_t exec_offset)
3345 drm_i915_private_t *dev_priv = dev->dev_private;
3346 int nbox = exec->num_cliprects;
3348 uint32_t exec_start, exec_len;
3351 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3352 exec_len = (uint32_t) exec->batch_len;
3354 trace_i915_gem_request_submit(dev, dev_priv->mm.next_gem_seqno);
3356 count = nbox ? nbox : 1;
3358 for (i = 0; i < count; i++) {
3360 int ret = i915_emit_box(dev, cliprects, i,
3361 exec->DR1, exec->DR4);
3366 if (IS_I830(dev) || IS_845G(dev)) {
3368 OUT_RING(MI_BATCH_BUFFER);
3369 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3370 OUT_RING(exec_start + exec_len - 4);
3375 if (IS_I965G(dev)) {
3376 OUT_RING(MI_BATCH_BUFFER_START |
3378 MI_BATCH_NON_SECURE_I965);
3379 OUT_RING(exec_start);
3381 OUT_RING(MI_BATCH_BUFFER_START |
3383 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3389 /* XXX breadcrumb */
3393 /* Throttle our rendering by waiting until the ring has completed our requests
3394 * emitted over 20 msec ago.
3396 * Note that if we were to use the current jiffies each time around the loop,
3397 * we wouldn't escape the function with any frames outstanding if the time to
3398 * render a frame was over 20ms.
3400 * This should get us reasonable parallelism between CPU and GPU but also
3401 * relatively low latency when blocking on a particular request to finish.
3404 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3406 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3408 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3410 mutex_lock(&dev->struct_mutex);
3411 while (!list_empty(&i915_file_priv->mm.request_list)) {
3412 struct drm_i915_gem_request *request;
3414 request = list_first_entry(&i915_file_priv->mm.request_list,
3415 struct drm_i915_gem_request,
3418 if (time_after_eq(request->emitted_jiffies, recent_enough))
3421 ret = i915_wait_request(dev, request->seqno);
3425 mutex_unlock(&dev->struct_mutex);
3431 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object *exec_list,
3432 uint32_t buffer_count,
3433 struct drm_i915_gem_relocation_entry **relocs)
3435 uint32_t reloc_count = 0, reloc_index = 0, i;
3439 for (i = 0; i < buffer_count; i++) {
3440 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3442 reloc_count += exec_list[i].relocation_count;
3445 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
3446 if (*relocs == NULL)
3449 for (i = 0; i < buffer_count; i++) {
3450 struct drm_i915_gem_relocation_entry __user *user_relocs;
3452 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3454 ret = copy_from_user(&(*relocs)[reloc_index],
3456 exec_list[i].relocation_count *
3459 drm_free_large(*relocs);
3464 reloc_index += exec_list[i].relocation_count;
3471 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object *exec_list,
3472 uint32_t buffer_count,
3473 struct drm_i915_gem_relocation_entry *relocs)
3475 uint32_t reloc_count = 0, i;
3478 for (i = 0; i < buffer_count; i++) {
3479 struct drm_i915_gem_relocation_entry __user *user_relocs;
3482 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3484 unwritten = copy_to_user(user_relocs,
3485 &relocs[reloc_count],
3486 exec_list[i].relocation_count *
3494 reloc_count += exec_list[i].relocation_count;
3498 drm_free_large(relocs);
3504 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer *exec,
3505 uint64_t exec_offset)
3507 uint32_t exec_start, exec_len;
3509 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3510 exec_len = (uint32_t) exec->batch_len;
3512 if ((exec_start | exec_len) & 0x7)
3522 i915_gem_execbuffer(struct drm_device *dev, void *data,
3523 struct drm_file *file_priv)
3525 drm_i915_private_t *dev_priv = dev->dev_private;
3526 struct drm_i915_gem_execbuffer *args = data;
3527 struct drm_i915_gem_exec_object *exec_list = NULL;
3528 struct drm_gem_object **object_list = NULL;
3529 struct drm_gem_object *batch_obj;
3530 struct drm_i915_gem_object *obj_priv;
3531 struct drm_clip_rect *cliprects = NULL;
3532 struct drm_i915_gem_relocation_entry *relocs;
3533 int ret, ret2, i, pinned = 0;
3534 uint64_t exec_offset;
3535 uint32_t seqno, flush_domains, reloc_index;
3539 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3540 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3543 if (args->buffer_count < 1) {
3544 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3547 /* Copy in the exec list from userland */
3548 exec_list = drm_calloc_large(sizeof(*exec_list), args->buffer_count);
3549 object_list = drm_calloc_large(sizeof(*object_list), args->buffer_count);
3550 if (exec_list == NULL || object_list == NULL) {
3551 DRM_ERROR("Failed to allocate exec or object list "
3553 args->buffer_count);
3557 ret = copy_from_user(exec_list,
3558 (struct drm_i915_relocation_entry __user *)
3559 (uintptr_t) args->buffers_ptr,
3560 sizeof(*exec_list) * args->buffer_count);
3562 DRM_ERROR("copy %d exec entries failed %d\n",
3563 args->buffer_count, ret);
3567 if (args->num_cliprects != 0) {
3568 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3570 if (cliprects == NULL)
3573 ret = copy_from_user(cliprects,
3574 (struct drm_clip_rect __user *)
3575 (uintptr_t) args->cliprects_ptr,
3576 sizeof(*cliprects) * args->num_cliprects);
3578 DRM_ERROR("copy %d cliprects failed: %d\n",
3579 args->num_cliprects, ret);
3584 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3589 mutex_lock(&dev->struct_mutex);
3591 i915_verify_inactive(dev, __FILE__, __LINE__);
3593 if (atomic_read(&dev_priv->mm.wedged)) {
3594 DRM_ERROR("Execbuf while wedged\n");
3595 mutex_unlock(&dev->struct_mutex);
3600 if (dev_priv->mm.suspended) {
3601 DRM_ERROR("Execbuf while VT-switched.\n");
3602 mutex_unlock(&dev->struct_mutex);
3607 /* Look up object handles */
3608 for (i = 0; i < args->buffer_count; i++) {
3609 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3610 exec_list[i].handle);
3611 if (object_list[i] == NULL) {
3612 DRM_ERROR("Invalid object handle %d at index %d\n",
3613 exec_list[i].handle, i);
3618 obj_priv = object_list[i]->driver_private;
3619 if (obj_priv->in_execbuffer) {
3620 DRM_ERROR("Object %p appears more than once in object list\n",
3625 obj_priv->in_execbuffer = true;
3628 /* Pin and relocate */
3629 for (pin_tries = 0; ; pin_tries++) {
3633 for (i = 0; i < args->buffer_count; i++) {
3634 object_list[i]->pending_read_domains = 0;
3635 object_list[i]->pending_write_domain = 0;
3636 ret = i915_gem_object_pin_and_relocate(object_list[i],
3639 &relocs[reloc_index]);
3643 reloc_index += exec_list[i].relocation_count;
3649 /* error other than GTT full, or we've already tried again */
3650 if (ret != -ENOSPC || pin_tries >= 1) {
3651 if (ret != -ERESTARTSYS) {
3652 unsigned long long total_size = 0;
3653 for (i = 0; i < args->buffer_count; i++)
3654 total_size += object_list[i]->size;
3655 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes: %d\n",
3656 pinned+1, args->buffer_count,
3658 DRM_ERROR("%d objects [%d pinned], "
3659 "%d object bytes [%d pinned], "
3660 "%d/%d gtt bytes\n",
3661 atomic_read(&dev->object_count),
3662 atomic_read(&dev->pin_count),
3663 atomic_read(&dev->object_memory),
3664 atomic_read(&dev->pin_memory),
3665 atomic_read(&dev->gtt_memory),
3671 /* unpin all of our buffers */
3672 for (i = 0; i < pinned; i++)
3673 i915_gem_object_unpin(object_list[i]);
3676 /* evict everyone we can from the aperture */
3677 ret = i915_gem_evict_everything(dev);
3678 if (ret && ret != -ENOSPC)
3682 /* Set the pending read domains for the batch buffer to COMMAND */
3683 batch_obj = object_list[args->buffer_count-1];
3684 if (batch_obj->pending_write_domain) {
3685 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3689 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
3691 /* Sanity check the batch buffer, prior to moving objects */
3692 exec_offset = exec_list[args->buffer_count - 1].offset;
3693 ret = i915_gem_check_execbuffer (args, exec_offset);
3695 DRM_ERROR("execbuf with invalid offset/length\n");
3699 i915_verify_inactive(dev, __FILE__, __LINE__);
3701 /* Zero the global flush/invalidate flags. These
3702 * will be modified as new domains are computed
3705 dev->invalidate_domains = 0;
3706 dev->flush_domains = 0;
3708 for (i = 0; i < args->buffer_count; i++) {
3709 struct drm_gem_object *obj = object_list[i];
3711 /* Compute new gpu domains and update invalidate/flush */
3712 i915_gem_object_set_to_gpu_domain(obj);
3715 i915_verify_inactive(dev, __FILE__, __LINE__);
3717 if (dev->invalidate_domains | dev->flush_domains) {
3719 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3721 dev->invalidate_domains,
3722 dev->flush_domains);
3725 dev->invalidate_domains,
3726 dev->flush_domains);
3727 if (dev->flush_domains)
3728 (void)i915_add_request(dev, file_priv,
3729 dev->flush_domains);
3732 for (i = 0; i < args->buffer_count; i++) {
3733 struct drm_gem_object *obj = object_list[i];
3734 uint32_t old_write_domain = obj->write_domain;
3736 obj->write_domain = obj->pending_write_domain;
3737 trace_i915_gem_object_change_domain(obj,
3742 i915_verify_inactive(dev, __FILE__, __LINE__);
3745 for (i = 0; i < args->buffer_count; i++) {
3746 i915_gem_object_check_coherency(object_list[i],
3747 exec_list[i].handle);
3752 i915_gem_dump_object(batch_obj,
3758 /* Exec the batchbuffer */
3759 ret = i915_dispatch_gem_execbuffer(dev, args, cliprects, exec_offset);
3761 DRM_ERROR("dispatch failed %d\n", ret);
3766 * Ensure that the commands in the batch buffer are
3767 * finished before the interrupt fires
3769 flush_domains = i915_retire_commands(dev);
3771 i915_verify_inactive(dev, __FILE__, __LINE__);
3774 * Get a seqno representing the execution of the current buffer,
3775 * which we can wait on. We would like to mitigate these interrupts,
3776 * likely by only creating seqnos occasionally (so that we have
3777 * *some* interrupts representing completion of buffers that we can
3778 * wait on when trying to clear up gtt space).
3780 seqno = i915_add_request(dev, file_priv, flush_domains);
3782 for (i = 0; i < args->buffer_count; i++) {
3783 struct drm_gem_object *obj = object_list[i];
3785 i915_gem_object_move_to_active(obj, seqno);
3787 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3791 i915_dump_lru(dev, __func__);
3794 i915_verify_inactive(dev, __FILE__, __LINE__);
3797 for (i = 0; i < pinned; i++)
3798 i915_gem_object_unpin(object_list[i]);
3800 for (i = 0; i < args->buffer_count; i++) {
3801 if (object_list[i]) {
3802 obj_priv = object_list[i]->driver_private;
3803 obj_priv->in_execbuffer = false;
3805 drm_gem_object_unreference(object_list[i]);
3808 mutex_unlock(&dev->struct_mutex);
3811 /* Copy the new buffer offsets back to the user's exec list. */
3812 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
3813 (uintptr_t) args->buffers_ptr,
3815 sizeof(*exec_list) * args->buffer_count);
3818 DRM_ERROR("failed to copy %d exec entries "
3819 "back to user (%d)\n",
3820 args->buffer_count, ret);
3824 /* Copy the updated relocations out regardless of current error
3825 * state. Failure to update the relocs would mean that the next
3826 * time userland calls execbuf, it would do so with presumed offset
3827 * state that didn't match the actual object state.
3829 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
3832 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
3839 drm_free_large(object_list);
3840 drm_free_large(exec_list);
3847 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
3849 struct drm_device *dev = obj->dev;
3850 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3853 i915_verify_inactive(dev, __FILE__, __LINE__);
3854 if (obj_priv->gtt_space == NULL) {
3855 ret = i915_gem_object_bind_to_gtt(obj, alignment);
3857 if (ret != -EBUSY && ret != -ERESTARTSYS)
3858 DRM_ERROR("Failure to bind: %d\n", ret);
3863 * Pre-965 chips need a fence register set up in order to
3864 * properly handle tiled surfaces.
3866 if (!IS_I965G(dev) && obj_priv->tiling_mode != I915_TILING_NONE) {
3867 ret = i915_gem_object_get_fence_reg(obj);
3869 if (ret != -EBUSY && ret != -ERESTARTSYS)
3870 DRM_ERROR("Failure to install fence: %d\n",
3875 obj_priv->pin_count++;
3877 /* If the object is not active and not pending a flush,
3878 * remove it from the inactive list
3880 if (obj_priv->pin_count == 1) {
3881 atomic_inc(&dev->pin_count);
3882 atomic_add(obj->size, &dev->pin_memory);
3883 if (!obj_priv->active &&
3884 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 &&
3885 !list_empty(&obj_priv->list))
3886 list_del_init(&obj_priv->list);
3888 i915_verify_inactive(dev, __FILE__, __LINE__);
3894 i915_gem_object_unpin(struct drm_gem_object *obj)
3896 struct drm_device *dev = obj->dev;
3897 drm_i915_private_t *dev_priv = dev->dev_private;
3898 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3900 i915_verify_inactive(dev, __FILE__, __LINE__);
3901 obj_priv->pin_count--;
3902 BUG_ON(obj_priv->pin_count < 0);
3903 BUG_ON(obj_priv->gtt_space == NULL);
3905 /* If the object is no longer pinned, and is
3906 * neither active nor being flushed, then stick it on
3909 if (obj_priv->pin_count == 0) {
3910 if (!obj_priv->active &&
3911 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
3912 list_move_tail(&obj_priv->list,
3913 &dev_priv->mm.inactive_list);
3914 atomic_dec(&dev->pin_count);
3915 atomic_sub(obj->size, &dev->pin_memory);
3917 i915_verify_inactive(dev, __FILE__, __LINE__);
3921 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3922 struct drm_file *file_priv)
3924 struct drm_i915_gem_pin *args = data;
3925 struct drm_gem_object *obj;
3926 struct drm_i915_gem_object *obj_priv;
3929 mutex_lock(&dev->struct_mutex);
3931 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
3933 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
3935 mutex_unlock(&dev->struct_mutex);
3938 obj_priv = obj->driver_private;
3940 if (obj_priv->madv == I915_MADV_DONTNEED) {
3941 DRM_ERROR("Attempting to pin a I915_MADV_DONTNEED buffer\n");
3942 drm_gem_object_unreference(obj);
3943 mutex_unlock(&dev->struct_mutex);
3947 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
3948 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3950 drm_gem_object_unreference(obj);
3951 mutex_unlock(&dev->struct_mutex);
3955 obj_priv->user_pin_count++;
3956 obj_priv->pin_filp = file_priv;
3957 if (obj_priv->user_pin_count == 1) {
3958 ret = i915_gem_object_pin(obj, args->alignment);
3960 drm_gem_object_unreference(obj);
3961 mutex_unlock(&dev->struct_mutex);
3966 /* XXX - flush the CPU caches for pinned objects
3967 * as the X server doesn't manage domains yet
3969 i915_gem_object_flush_cpu_write_domain(obj);
3970 args->offset = obj_priv->gtt_offset;
3971 drm_gem_object_unreference(obj);
3972 mutex_unlock(&dev->struct_mutex);
3978 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3979 struct drm_file *file_priv)
3981 struct drm_i915_gem_pin *args = data;
3982 struct drm_gem_object *obj;
3983 struct drm_i915_gem_object *obj_priv;
3985 mutex_lock(&dev->struct_mutex);
3987 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
3989 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
3991 mutex_unlock(&dev->struct_mutex);
3995 obj_priv = obj->driver_private;
3996 if (obj_priv->pin_filp != file_priv) {
3997 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3999 drm_gem_object_unreference(obj);
4000 mutex_unlock(&dev->struct_mutex);
4003 obj_priv->user_pin_count--;
4004 if (obj_priv->user_pin_count == 0) {
4005 obj_priv->pin_filp = NULL;
4006 i915_gem_object_unpin(obj);
4009 drm_gem_object_unreference(obj);
4010 mutex_unlock(&dev->struct_mutex);
4015 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4016 struct drm_file *file_priv)
4018 struct drm_i915_gem_busy *args = data;
4019 struct drm_gem_object *obj;
4020 struct drm_i915_gem_object *obj_priv;
4022 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4024 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4029 mutex_lock(&dev->struct_mutex);
4030 /* Update the active list for the hardware's current position.
4031 * Otherwise this only updates on a delayed timer or when irqs are
4032 * actually unmasked, and our working set ends up being larger than
4035 i915_gem_retire_requests(dev);
4037 obj_priv = obj->driver_private;
4038 /* Don't count being on the flushing list against the object being
4039 * done. Otherwise, a buffer left on the flushing list but not getting
4040 * flushed (because nobody's flushing that domain) won't ever return
4041 * unbusy and get reused by libdrm's bo cache. The other expected
4042 * consumer of this interface, OpenGL's occlusion queries, also specs
4043 * that the objects get unbusy "eventually" without any interference.
4045 args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
4047 drm_gem_object_unreference(obj);
4048 mutex_unlock(&dev->struct_mutex);
4053 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4054 struct drm_file *file_priv)
4056 return i915_gem_ring_throttle(dev, file_priv);
4060 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4061 struct drm_file *file_priv)
4063 struct drm_i915_gem_madvise *args = data;
4064 struct drm_gem_object *obj;
4065 struct drm_i915_gem_object *obj_priv;
4067 switch (args->madv) {
4068 case I915_MADV_DONTNEED:
4069 case I915_MADV_WILLNEED:
4075 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4077 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4082 mutex_lock(&dev->struct_mutex);
4083 obj_priv = obj->driver_private;
4085 if (obj_priv->pin_count) {
4086 drm_gem_object_unreference(obj);
4087 mutex_unlock(&dev->struct_mutex);
4089 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4093 obj_priv->madv = args->madv;
4094 args->retained = obj_priv->gtt_space != NULL;
4096 drm_gem_object_unreference(obj);
4097 mutex_unlock(&dev->struct_mutex);
4102 int i915_gem_init_object(struct drm_gem_object *obj)
4104 struct drm_i915_gem_object *obj_priv;
4106 obj_priv = kzalloc(sizeof(*obj_priv), GFP_KERNEL);
4107 if (obj_priv == NULL)
4111 * We've just allocated pages from the kernel,
4112 * so they've just been written by the CPU with
4113 * zeros. They'll need to be clflushed before we
4114 * use them with the GPU.
4116 obj->write_domain = I915_GEM_DOMAIN_CPU;
4117 obj->read_domains = I915_GEM_DOMAIN_CPU;
4119 obj_priv->agp_type = AGP_USER_MEMORY;
4121 obj->driver_private = obj_priv;
4122 obj_priv->obj = obj;
4123 obj_priv->fence_reg = I915_FENCE_REG_NONE;
4124 INIT_LIST_HEAD(&obj_priv->list);
4125 INIT_LIST_HEAD(&obj_priv->fence_list);
4126 obj_priv->madv = I915_MADV_WILLNEED;
4128 trace_i915_gem_object_create(obj);
4133 void i915_gem_free_object(struct drm_gem_object *obj)
4135 struct drm_device *dev = obj->dev;
4136 struct drm_i915_gem_object *obj_priv = obj->driver_private;
4138 trace_i915_gem_object_destroy(obj);
4140 while (obj_priv->pin_count > 0)
4141 i915_gem_object_unpin(obj);
4143 if (obj_priv->phys_obj)
4144 i915_gem_detach_phys_object(dev, obj);
4146 i915_gem_object_unbind(obj);
4148 if (obj_priv->mmap_offset)
4149 i915_gem_free_mmap_offset(obj);
4151 kfree(obj_priv->page_cpu_valid);
4152 kfree(obj_priv->bit_17);
4153 kfree(obj->driver_private);
4156 /** Unbinds all inactive objects. */
4158 i915_gem_evict_from_inactive_list(struct drm_device *dev)
4160 drm_i915_private_t *dev_priv = dev->dev_private;
4162 while (!list_empty(&dev_priv->mm.inactive_list)) {
4163 struct drm_gem_object *obj;
4166 obj = list_first_entry(&dev_priv->mm.inactive_list,
4167 struct drm_i915_gem_object,
4170 ret = i915_gem_object_unbind(obj);
4172 DRM_ERROR("Error unbinding object: %d\n", ret);
4181 i915_gem_idle(struct drm_device *dev)
4183 drm_i915_private_t *dev_priv = dev->dev_private;
4184 uint32_t seqno, cur_seqno, last_seqno;
4187 mutex_lock(&dev->struct_mutex);
4189 if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
4190 mutex_unlock(&dev->struct_mutex);
4194 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4195 * We need to replace this with a semaphore, or something.
4197 dev_priv->mm.suspended = 1;
4198 del_timer(&dev_priv->hangcheck_timer);
4200 /* Cancel the retire work handler, wait for it to finish if running
4202 mutex_unlock(&dev->struct_mutex);
4203 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4204 mutex_lock(&dev->struct_mutex);
4206 i915_kernel_lost_context(dev);
4208 /* Flush the GPU along with all non-CPU write domains
4210 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
4211 seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
4214 mutex_unlock(&dev->struct_mutex);
4218 dev_priv->mm.waiting_gem_seqno = seqno;
4222 cur_seqno = i915_get_gem_seqno(dev);
4223 if (i915_seqno_passed(cur_seqno, seqno))
4225 if (last_seqno == cur_seqno) {
4226 if (stuck++ > 100) {
4227 DRM_ERROR("hardware wedged\n");
4228 atomic_set(&dev_priv->mm.wedged, 1);
4229 DRM_WAKEUP(&dev_priv->irq_queue);
4234 last_seqno = cur_seqno;
4236 dev_priv->mm.waiting_gem_seqno = 0;
4238 i915_gem_retire_requests(dev);
4240 spin_lock(&dev_priv->mm.active_list_lock);
4241 if (!atomic_read(&dev_priv->mm.wedged)) {
4242 /* Active and flushing should now be empty as we've
4243 * waited for a sequence higher than any pending execbuffer
4245 WARN_ON(!list_empty(&dev_priv->mm.active_list));
4246 WARN_ON(!list_empty(&dev_priv->mm.flushing_list));
4247 /* Request should now be empty as we've also waited
4248 * for the last request in the list
4250 WARN_ON(!list_empty(&dev_priv->mm.request_list));
4253 /* Empty the active and flushing lists to inactive. If there's
4254 * anything left at this point, it means that we're wedged and
4255 * nothing good's going to happen by leaving them there. So strip
4256 * the GPU domains and just stuff them onto inactive.
4258 while (!list_empty(&dev_priv->mm.active_list)) {
4259 struct drm_gem_object *obj;
4260 uint32_t old_write_domain;
4262 obj = list_first_entry(&dev_priv->mm.active_list,
4263 struct drm_i915_gem_object,
4265 old_write_domain = obj->write_domain;
4266 obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
4267 i915_gem_object_move_to_inactive(obj);
4269 trace_i915_gem_object_change_domain(obj,
4273 spin_unlock(&dev_priv->mm.active_list_lock);
4275 while (!list_empty(&dev_priv->mm.flushing_list)) {
4276 struct drm_gem_object *obj;
4277 uint32_t old_write_domain;
4279 obj = list_first_entry(&dev_priv->mm.flushing_list,
4280 struct drm_i915_gem_object,
4282 old_write_domain = obj->write_domain;
4283 obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
4284 i915_gem_object_move_to_inactive(obj);
4286 trace_i915_gem_object_change_domain(obj,
4292 /* Move all inactive buffers out of the GTT. */
4293 ret = i915_gem_evict_from_inactive_list(dev);
4294 WARN_ON(!list_empty(&dev_priv->mm.inactive_list));
4296 mutex_unlock(&dev->struct_mutex);
4300 i915_gem_cleanup_ringbuffer(dev);
4301 mutex_unlock(&dev->struct_mutex);
4307 i915_gem_init_hws(struct drm_device *dev)
4309 drm_i915_private_t *dev_priv = dev->dev_private;
4310 struct drm_gem_object *obj;
4311 struct drm_i915_gem_object *obj_priv;
4314 /* If we need a physical address for the status page, it's already
4315 * initialized at driver load time.
4317 if (!I915_NEED_GFX_HWS(dev))
4320 obj = drm_gem_object_alloc(dev, 4096);
4322 DRM_ERROR("Failed to allocate status page\n");
4325 obj_priv = obj->driver_private;
4326 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4328 ret = i915_gem_object_pin(obj, 4096);
4330 drm_gem_object_unreference(obj);
4334 dev_priv->status_gfx_addr = obj_priv->gtt_offset;
4336 dev_priv->hw_status_page = kmap(obj_priv->pages[0]);
4337 if (dev_priv->hw_status_page == NULL) {
4338 DRM_ERROR("Failed to map status page.\n");
4339 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4340 i915_gem_object_unpin(obj);
4341 drm_gem_object_unreference(obj);
4344 dev_priv->hws_obj = obj;
4345 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
4346 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
4347 I915_READ(HWS_PGA); /* posting read */
4348 DRM_DEBUG("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
4354 i915_gem_cleanup_hws(struct drm_device *dev)
4356 drm_i915_private_t *dev_priv = dev->dev_private;
4357 struct drm_gem_object *obj;
4358 struct drm_i915_gem_object *obj_priv;
4360 if (dev_priv->hws_obj == NULL)
4363 obj = dev_priv->hws_obj;
4364 obj_priv = obj->driver_private;
4366 kunmap(obj_priv->pages[0]);
4367 i915_gem_object_unpin(obj);
4368 drm_gem_object_unreference(obj);
4369 dev_priv->hws_obj = NULL;
4371 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4372 dev_priv->hw_status_page = NULL;
4374 /* Write high address into HWS_PGA when disabling. */
4375 I915_WRITE(HWS_PGA, 0x1ffff000);
4379 i915_gem_init_ringbuffer(struct drm_device *dev)
4381 drm_i915_private_t *dev_priv = dev->dev_private;
4382 struct drm_gem_object *obj;
4383 struct drm_i915_gem_object *obj_priv;
4384 drm_i915_ring_buffer_t *ring = &dev_priv->ring;
4388 ret = i915_gem_init_hws(dev);
4392 obj = drm_gem_object_alloc(dev, 128 * 1024);
4394 DRM_ERROR("Failed to allocate ringbuffer\n");
4395 i915_gem_cleanup_hws(dev);
4398 obj_priv = obj->driver_private;
4400 ret = i915_gem_object_pin(obj, 4096);
4402 drm_gem_object_unreference(obj);
4403 i915_gem_cleanup_hws(dev);
4407 /* Set up the kernel mapping for the ring. */
4408 ring->Size = obj->size;
4410 ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
4411 ring->map.size = obj->size;
4413 ring->map.flags = 0;
4416 drm_core_ioremap_wc(&ring->map, dev);
4417 if (ring->map.handle == NULL) {
4418 DRM_ERROR("Failed to map ringbuffer.\n");
4419 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4420 i915_gem_object_unpin(obj);
4421 drm_gem_object_unreference(obj);
4422 i915_gem_cleanup_hws(dev);
4425 ring->ring_obj = obj;
4426 ring->virtual_start = ring->map.handle;
4428 /* Stop the ring if it's running. */
4429 I915_WRITE(PRB0_CTL, 0);
4430 I915_WRITE(PRB0_TAIL, 0);
4431 I915_WRITE(PRB0_HEAD, 0);
4433 /* Initialize the ring. */
4434 I915_WRITE(PRB0_START, obj_priv->gtt_offset);
4435 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4437 /* G45 ring initialization fails to reset head to zero */
4439 DRM_ERROR("Ring head not reset to zero "
4440 "ctl %08x head %08x tail %08x start %08x\n",
4441 I915_READ(PRB0_CTL),
4442 I915_READ(PRB0_HEAD),
4443 I915_READ(PRB0_TAIL),
4444 I915_READ(PRB0_START));
4445 I915_WRITE(PRB0_HEAD, 0);
4447 DRM_ERROR("Ring head forced to zero "
4448 "ctl %08x head %08x tail %08x start %08x\n",
4449 I915_READ(PRB0_CTL),
4450 I915_READ(PRB0_HEAD),
4451 I915_READ(PRB0_TAIL),
4452 I915_READ(PRB0_START));
4455 I915_WRITE(PRB0_CTL,
4456 ((obj->size - 4096) & RING_NR_PAGES) |
4460 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4462 /* If the head is still not zero, the ring is dead */
4464 DRM_ERROR("Ring initialization failed "
4465 "ctl %08x head %08x tail %08x start %08x\n",
4466 I915_READ(PRB0_CTL),
4467 I915_READ(PRB0_HEAD),
4468 I915_READ(PRB0_TAIL),
4469 I915_READ(PRB0_START));
4473 /* Update our cache of the ring state */
4474 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4475 i915_kernel_lost_context(dev);
4477 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4478 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
4479 ring->space = ring->head - (ring->tail + 8);
4480 if (ring->space < 0)
4481 ring->space += ring->Size;
4488 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4490 drm_i915_private_t *dev_priv = dev->dev_private;
4492 if (dev_priv->ring.ring_obj == NULL)
4495 drm_core_ioremapfree(&dev_priv->ring.map, dev);
4497 i915_gem_object_unpin(dev_priv->ring.ring_obj);
4498 drm_gem_object_unreference(dev_priv->ring.ring_obj);
4499 dev_priv->ring.ring_obj = NULL;
4500 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4502 i915_gem_cleanup_hws(dev);
4506 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4507 struct drm_file *file_priv)
4509 drm_i915_private_t *dev_priv = dev->dev_private;
4512 if (drm_core_check_feature(dev, DRIVER_MODESET))
4515 if (atomic_read(&dev_priv->mm.wedged)) {
4516 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4517 atomic_set(&dev_priv->mm.wedged, 0);
4520 mutex_lock(&dev->struct_mutex);
4521 dev_priv->mm.suspended = 0;
4523 ret = i915_gem_init_ringbuffer(dev);
4525 mutex_unlock(&dev->struct_mutex);
4529 spin_lock(&dev_priv->mm.active_list_lock);
4530 BUG_ON(!list_empty(&dev_priv->mm.active_list));
4531 spin_unlock(&dev_priv->mm.active_list_lock);
4533 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4534 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4535 BUG_ON(!list_empty(&dev_priv->mm.request_list));
4536 mutex_unlock(&dev->struct_mutex);
4538 drm_irq_install(dev);
4544 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4545 struct drm_file *file_priv)
4549 if (drm_core_check_feature(dev, DRIVER_MODESET))
4552 ret = i915_gem_idle(dev);
4553 drm_irq_uninstall(dev);
4559 i915_gem_lastclose(struct drm_device *dev)
4563 if (drm_core_check_feature(dev, DRIVER_MODESET))
4566 ret = i915_gem_idle(dev);
4568 DRM_ERROR("failed to idle hardware: %d\n", ret);
4572 i915_gem_load(struct drm_device *dev)
4575 drm_i915_private_t *dev_priv = dev->dev_private;
4577 spin_lock_init(&dev_priv->mm.active_list_lock);
4578 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4579 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4580 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4581 INIT_LIST_HEAD(&dev_priv->mm.request_list);
4582 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4583 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4584 i915_gem_retire_work_handler);
4585 dev_priv->mm.next_gem_seqno = 1;
4587 spin_lock(&shrink_list_lock);
4588 list_add(&dev_priv->mm.shrink_list, &shrink_list);
4589 spin_unlock(&shrink_list_lock);
4591 /* Old X drivers will take 0-2 for front, back, depth buffers */
4592 dev_priv->fence_reg_start = 3;
4594 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4595 dev_priv->num_fence_regs = 16;
4597 dev_priv->num_fence_regs = 8;
4599 /* Initialize fence registers to zero */
4600 if (IS_I965G(dev)) {
4601 for (i = 0; i < 16; i++)
4602 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4604 for (i = 0; i < 8; i++)
4605 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4606 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4607 for (i = 0; i < 8; i++)
4608 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4611 i915_gem_detect_bit_6_swizzle(dev);
4615 * Create a physically contiguous memory object for this object
4616 * e.g. for cursor + overlay regs
4618 int i915_gem_init_phys_object(struct drm_device *dev,
4621 drm_i915_private_t *dev_priv = dev->dev_private;
4622 struct drm_i915_gem_phys_object *phys_obj;
4625 if (dev_priv->mm.phys_objs[id - 1] || !size)
4628 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4634 phys_obj->handle = drm_pci_alloc(dev, size, 0, 0xffffffff);
4635 if (!phys_obj->handle) {
4640 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4643 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4651 void i915_gem_free_phys_object(struct drm_device *dev, int id)
4653 drm_i915_private_t *dev_priv = dev->dev_private;
4654 struct drm_i915_gem_phys_object *phys_obj;
4656 if (!dev_priv->mm.phys_objs[id - 1])
4659 phys_obj = dev_priv->mm.phys_objs[id - 1];
4660 if (phys_obj->cur_obj) {
4661 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4665 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4667 drm_pci_free(dev, phys_obj->handle);
4669 dev_priv->mm.phys_objs[id - 1] = NULL;
4672 void i915_gem_free_all_phys_object(struct drm_device *dev)
4676 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4677 i915_gem_free_phys_object(dev, i);
4680 void i915_gem_detach_phys_object(struct drm_device *dev,
4681 struct drm_gem_object *obj)
4683 struct drm_i915_gem_object *obj_priv;
4688 obj_priv = obj->driver_private;
4689 if (!obj_priv->phys_obj)
4692 ret = i915_gem_object_get_pages(obj);
4696 page_count = obj->size / PAGE_SIZE;
4698 for (i = 0; i < page_count; i++) {
4699 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
4700 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4702 memcpy(dst, src, PAGE_SIZE);
4703 kunmap_atomic(dst, KM_USER0);
4705 drm_clflush_pages(obj_priv->pages, page_count);
4706 drm_agp_chipset_flush(dev);
4708 i915_gem_object_put_pages(obj);
4710 obj_priv->phys_obj->cur_obj = NULL;
4711 obj_priv->phys_obj = NULL;
4715 i915_gem_attach_phys_object(struct drm_device *dev,
4716 struct drm_gem_object *obj, int id)
4718 drm_i915_private_t *dev_priv = dev->dev_private;
4719 struct drm_i915_gem_object *obj_priv;
4724 if (id > I915_MAX_PHYS_OBJECT)
4727 obj_priv = obj->driver_private;
4729 if (obj_priv->phys_obj) {
4730 if (obj_priv->phys_obj->id == id)
4732 i915_gem_detach_phys_object(dev, obj);
4736 /* create a new object */
4737 if (!dev_priv->mm.phys_objs[id - 1]) {
4738 ret = i915_gem_init_phys_object(dev, id,
4741 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
4746 /* bind to the object */
4747 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4748 obj_priv->phys_obj->cur_obj = obj;
4750 ret = i915_gem_object_get_pages(obj);
4752 DRM_ERROR("failed to get page list\n");
4756 page_count = obj->size / PAGE_SIZE;
4758 for (i = 0; i < page_count; i++) {
4759 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
4760 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4762 memcpy(dst, src, PAGE_SIZE);
4763 kunmap_atomic(src, KM_USER0);
4766 i915_gem_object_put_pages(obj);
4774 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4775 struct drm_i915_gem_pwrite *args,
4776 struct drm_file *file_priv)
4778 struct drm_i915_gem_object *obj_priv = obj->driver_private;
4781 char __user *user_data;
4783 user_data = (char __user *) (uintptr_t) args->data_ptr;
4784 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4786 DRM_DEBUG("obj_addr %p, %lld\n", obj_addr, args->size);
4787 ret = copy_from_user(obj_addr, user_data, args->size);
4791 drm_agp_chipset_flush(dev);
4795 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
4797 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
4799 /* Clean up our request list when the client is going away, so that
4800 * later retire_requests won't dereference our soon-to-be-gone
4803 mutex_lock(&dev->struct_mutex);
4804 while (!list_empty(&i915_file_priv->mm.request_list))
4805 list_del_init(i915_file_priv->mm.request_list.next);
4806 mutex_unlock(&dev->struct_mutex);
4809 /* Immediately discard the backing storage */
4811 i915_gem_object_truncate(struct drm_gem_object *obj)
4813 struct inode *inode;
4815 inode = obj->filp->f_path.dentry->d_inode;
4817 mutex_lock(&inode->i_mutex);
4818 truncate_inode_pages(inode->i_mapping, 0);
4819 mutex_unlock(&inode->i_mutex);
4823 i915_gem_shrink(int nr_to_scan, gfp_t gfp_mask)
4825 drm_i915_private_t *dev_priv, *next_dev;
4826 struct drm_i915_gem_object *obj_priv, *next_obj;
4828 int would_deadlock = 1;
4830 /* "fast-path" to count number of available objects */
4831 if (nr_to_scan == 0) {
4832 spin_lock(&shrink_list_lock);
4833 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4834 struct drm_device *dev = dev_priv->dev;
4836 if (mutex_trylock(&dev->struct_mutex)) {
4837 list_for_each_entry(obj_priv,
4838 &dev_priv->mm.inactive_list,
4841 mutex_unlock(&dev->struct_mutex);
4844 spin_unlock(&shrink_list_lock);
4846 return (cnt / 100) * sysctl_vfs_cache_pressure;
4849 spin_lock(&shrink_list_lock);
4851 /* first scan for clean buffers */
4852 list_for_each_entry_safe(dev_priv, next_dev,
4853 &shrink_list, mm.shrink_list) {
4854 struct drm_device *dev = dev_priv->dev;
4856 if (! mutex_trylock(&dev->struct_mutex))
4859 spin_unlock(&shrink_list_lock);
4861 i915_gem_retire_requests(dev);
4863 list_for_each_entry_safe(obj_priv, next_obj,
4864 &dev_priv->mm.inactive_list,
4866 if (i915_gem_object_is_purgeable(obj_priv)) {
4867 struct drm_gem_object *obj = obj_priv->obj;
4868 i915_gem_object_unbind(obj);
4869 i915_gem_object_truncate(obj);
4871 if (--nr_to_scan <= 0)
4876 spin_lock(&shrink_list_lock);
4877 mutex_unlock(&dev->struct_mutex);
4879 if (nr_to_scan <= 0)
4883 /* second pass, evict/count anything still on the inactive list */
4884 list_for_each_entry_safe(dev_priv, next_dev,
4885 &shrink_list, mm.shrink_list) {
4886 struct drm_device *dev = dev_priv->dev;
4888 if (! mutex_trylock(&dev->struct_mutex))
4891 spin_unlock(&shrink_list_lock);
4893 list_for_each_entry_safe(obj_priv, next_obj,
4894 &dev_priv->mm.inactive_list,
4896 if (nr_to_scan > 0) {
4897 struct drm_gem_object *obj = obj_priv->obj;
4898 i915_gem_object_unbind(obj);
4899 if (i915_gem_object_is_purgeable(obj_priv))
4900 i915_gem_object_truncate(obj);
4907 spin_lock(&shrink_list_lock);
4908 mutex_unlock(&dev->struct_mutex);
4913 spin_unlock(&shrink_list_lock);
4918 return (cnt / 100) * sysctl_vfs_cache_pressure;
4923 static struct shrinker shrinker = {
4924 .shrink = i915_gem_shrink,
4925 .seeks = DEFAULT_SEEKS,
4929 i915_gem_shrinker_init(void)
4931 register_shrinker(&shrinker);
4935 i915_gem_shrinker_exit(void)
4937 unregister_shrinker(&shrinker);