2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include <linux/swap.h>
33 #include <linux/pci.h>
35 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
37 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
38 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
39 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
40 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
42 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
45 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
46 static int i915_gem_object_get_page_list(struct drm_gem_object *obj);
47 static void i915_gem_object_free_page_list(struct drm_gem_object *obj);
48 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
49 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
51 static int i915_gem_object_get_fence_reg(struct drm_gem_object *obj, bool write);
52 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
53 static int i915_gem_evict_something(struct drm_device *dev);
54 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
55 struct drm_i915_gem_pwrite *args,
56 struct drm_file *file_priv);
58 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
61 drm_i915_private_t *dev_priv = dev->dev_private;
64 (start & (PAGE_SIZE - 1)) != 0 ||
65 (end & (PAGE_SIZE - 1)) != 0) {
69 drm_mm_init(&dev_priv->mm.gtt_space, start,
72 dev->gtt_total = (uint32_t) (end - start);
78 i915_gem_init_ioctl(struct drm_device *dev, void *data,
79 struct drm_file *file_priv)
81 struct drm_i915_gem_init *args = data;
84 mutex_lock(&dev->struct_mutex);
85 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
86 mutex_unlock(&dev->struct_mutex);
92 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
93 struct drm_file *file_priv)
95 struct drm_i915_gem_get_aperture *args = data;
97 if (!(dev->driver->driver_features & DRIVER_GEM))
100 args->aper_size = dev->gtt_total;
101 args->aper_available_size = (args->aper_size -
102 atomic_read(&dev->pin_memory));
109 * Creates a new mm object and returns a handle to it.
112 i915_gem_create_ioctl(struct drm_device *dev, void *data,
113 struct drm_file *file_priv)
115 struct drm_i915_gem_create *args = data;
116 struct drm_gem_object *obj;
119 args->size = roundup(args->size, PAGE_SIZE);
121 /* Allocate the new object */
122 obj = drm_gem_object_alloc(dev, args->size);
126 ret = drm_gem_handle_create(file_priv, obj, &handle);
127 mutex_lock(&dev->struct_mutex);
128 drm_gem_object_handle_unreference(obj);
129 mutex_unlock(&dev->struct_mutex);
134 args->handle = handle;
140 * Reads data from the object referenced by handle.
142 * On error, the contents of *data are undefined.
145 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
146 struct drm_file *file_priv)
148 struct drm_i915_gem_pread *args = data;
149 struct drm_gem_object *obj;
150 struct drm_i915_gem_object *obj_priv;
155 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
158 obj_priv = obj->driver_private;
160 /* Bounds check source.
162 * XXX: This could use review for overflow issues...
164 if (args->offset > obj->size || args->size > obj->size ||
165 args->offset + args->size > obj->size) {
166 drm_gem_object_unreference(obj);
170 mutex_lock(&dev->struct_mutex);
172 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
175 drm_gem_object_unreference(obj);
176 mutex_unlock(&dev->struct_mutex);
180 offset = args->offset;
182 read = vfs_read(obj->filp, (char __user *)(uintptr_t)args->data_ptr,
183 args->size, &offset);
184 if (read != args->size) {
185 drm_gem_object_unreference(obj);
186 mutex_unlock(&dev->struct_mutex);
193 drm_gem_object_unreference(obj);
194 mutex_unlock(&dev->struct_mutex);
199 /* This is the fast write path which cannot handle
200 * page faults in the source data
204 fast_user_write(struct io_mapping *mapping,
205 loff_t page_base, int page_offset,
206 char __user *user_data,
210 unsigned long unwritten;
212 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
213 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
215 io_mapping_unmap_atomic(vaddr_atomic);
221 /* Here's the write path which can sleep for
226 slow_user_write(struct io_mapping *mapping,
227 loff_t page_base, int page_offset,
228 char __user *user_data,
232 unsigned long unwritten;
234 vaddr = io_mapping_map_wc(mapping, page_base);
237 unwritten = __copy_from_user(vaddr + page_offset,
239 io_mapping_unmap(vaddr);
246 i915_gem_gtt_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
247 struct drm_i915_gem_pwrite *args,
248 struct drm_file *file_priv)
250 struct drm_i915_gem_object *obj_priv = obj->driver_private;
251 drm_i915_private_t *dev_priv = dev->dev_private;
253 loff_t offset, page_base;
254 char __user *user_data;
255 int page_offset, page_length;
258 user_data = (char __user *) (uintptr_t) args->data_ptr;
260 if (!access_ok(VERIFY_READ, user_data, remain))
264 mutex_lock(&dev->struct_mutex);
265 ret = i915_gem_object_pin(obj, 0);
267 mutex_unlock(&dev->struct_mutex);
270 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
274 obj_priv = obj->driver_private;
275 offset = obj_priv->gtt_offset + args->offset;
279 /* Operation in this page
281 * page_base = page offset within aperture
282 * page_offset = offset within page
283 * page_length = bytes to copy for this page
285 page_base = (offset & ~(PAGE_SIZE-1));
286 page_offset = offset & (PAGE_SIZE-1);
287 page_length = remain;
288 if ((page_offset + remain) > PAGE_SIZE)
289 page_length = PAGE_SIZE - page_offset;
291 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
292 page_offset, user_data, page_length);
294 /* If we get a fault while copying data, then (presumably) our
295 * source page isn't available. In this case, use the
296 * non-atomic function
299 ret = slow_user_write (dev_priv->mm.gtt_mapping,
300 page_base, page_offset,
301 user_data, page_length);
306 remain -= page_length;
307 user_data += page_length;
308 offset += page_length;
312 i915_gem_object_unpin(obj);
313 mutex_unlock(&dev->struct_mutex);
319 i915_gem_shmem_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
320 struct drm_i915_gem_pwrite *args,
321 struct drm_file *file_priv)
327 mutex_lock(&dev->struct_mutex);
329 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
331 mutex_unlock(&dev->struct_mutex);
335 offset = args->offset;
337 written = vfs_write(obj->filp,
338 (char __user *)(uintptr_t) args->data_ptr,
339 args->size, &offset);
340 if (written != args->size) {
341 mutex_unlock(&dev->struct_mutex);
348 mutex_unlock(&dev->struct_mutex);
354 * Writes data to the object referenced by handle.
356 * On error, the contents of the buffer that were to be modified are undefined.
359 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
360 struct drm_file *file_priv)
362 struct drm_i915_gem_pwrite *args = data;
363 struct drm_gem_object *obj;
364 struct drm_i915_gem_object *obj_priv;
367 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
370 obj_priv = obj->driver_private;
372 /* Bounds check destination.
374 * XXX: This could use review for overflow issues...
376 if (args->offset > obj->size || args->size > obj->size ||
377 args->offset + args->size > obj->size) {
378 drm_gem_object_unreference(obj);
382 /* We can only do the GTT pwrite on untiled buffers, as otherwise
383 * it would end up going through the fenced access, and we'll get
384 * different detiling behavior between reading and writing.
385 * pread/pwrite currently are reading and writing from the CPU
386 * perspective, requiring manual detiling by the client.
388 if (obj_priv->phys_obj)
389 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
390 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
392 ret = i915_gem_gtt_pwrite(dev, obj, args, file_priv);
394 ret = i915_gem_shmem_pwrite(dev, obj, args, file_priv);
398 DRM_INFO("pwrite failed %d\n", ret);
401 drm_gem_object_unreference(obj);
407 * Called when user space prepares to use an object with the CPU, either
408 * through the mmap ioctl's mapping or a GTT mapping.
411 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
412 struct drm_file *file_priv)
414 struct drm_i915_gem_set_domain *args = data;
415 struct drm_gem_object *obj;
416 uint32_t read_domains = args->read_domains;
417 uint32_t write_domain = args->write_domain;
420 if (!(dev->driver->driver_features & DRIVER_GEM))
423 /* Only handle setting domains to types used by the CPU. */
424 if (write_domain & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
427 if (read_domains & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
430 /* Having something in the write domain implies it's in the read
431 * domain, and only that read domain. Enforce that in the request.
433 if (write_domain != 0 && read_domains != write_domain)
436 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
440 mutex_lock(&dev->struct_mutex);
442 DRM_INFO("set_domain_ioctl %p(%d), %08x %08x\n",
443 obj, obj->size, read_domains, write_domain);
445 if (read_domains & I915_GEM_DOMAIN_GTT) {
446 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
448 /* Silently promote "you're not bound, there was nothing to do"
449 * to success, since the client was just asking us to
450 * make sure everything was done.
455 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
458 drm_gem_object_unreference(obj);
459 mutex_unlock(&dev->struct_mutex);
464 * Called when user space has done writes to this buffer
467 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
468 struct drm_file *file_priv)
470 struct drm_i915_gem_sw_finish *args = data;
471 struct drm_gem_object *obj;
472 struct drm_i915_gem_object *obj_priv;
475 if (!(dev->driver->driver_features & DRIVER_GEM))
478 mutex_lock(&dev->struct_mutex);
479 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
481 mutex_unlock(&dev->struct_mutex);
486 DRM_INFO("%s: sw_finish %d (%p %d)\n",
487 __func__, args->handle, obj, obj->size);
489 obj_priv = obj->driver_private;
491 /* Pinned buffers may be scanout, so flush the cache */
492 if (obj_priv->pin_count)
493 i915_gem_object_flush_cpu_write_domain(obj);
495 drm_gem_object_unreference(obj);
496 mutex_unlock(&dev->struct_mutex);
501 * Maps the contents of an object, returning the address it is mapped
504 * While the mapping holds a reference on the contents of the object, it doesn't
505 * imply a ref on the object itself.
508 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
509 struct drm_file *file_priv)
511 struct drm_i915_gem_mmap *args = data;
512 struct drm_gem_object *obj;
516 if (!(dev->driver->driver_features & DRIVER_GEM))
519 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
523 offset = args->offset;
525 down_write(¤t->mm->mmap_sem);
526 addr = do_mmap(obj->filp, 0, args->size,
527 PROT_READ | PROT_WRITE, MAP_SHARED,
529 up_write(¤t->mm->mmap_sem);
530 mutex_lock(&dev->struct_mutex);
531 drm_gem_object_unreference(obj);
532 mutex_unlock(&dev->struct_mutex);
533 if (IS_ERR((void *)addr))
536 args->addr_ptr = (uint64_t) addr;
542 * i915_gem_fault - fault a page into the GTT
543 * vma: VMA in question
546 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
547 * from userspace. The fault handler takes care of binding the object to
548 * the GTT (if needed), allocating and programming a fence register (again,
549 * only if needed based on whether the old reg is still valid or the object
550 * is tiled) and inserting a new PTE into the faulting process.
552 * Note that the faulting process may involve evicting existing objects
553 * from the GTT and/or fence registers to make room. So performance may
554 * suffer if the GTT working set is large or there are few fence registers
557 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
559 struct drm_gem_object *obj = vma->vm_private_data;
560 struct drm_device *dev = obj->dev;
561 struct drm_i915_private *dev_priv = dev->dev_private;
562 struct drm_i915_gem_object *obj_priv = obj->driver_private;
566 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
568 /* We don't use vmf->pgoff since that has the fake offset */
569 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
572 /* Now bind it into the GTT if needed */
573 mutex_lock(&dev->struct_mutex);
574 if (!obj_priv->gtt_space) {
575 ret = i915_gem_object_bind_to_gtt(obj, obj_priv->gtt_alignment);
577 mutex_unlock(&dev->struct_mutex);
578 return VM_FAULT_SIGBUS;
580 list_add(&obj_priv->list, &dev_priv->mm.inactive_list);
583 /* Need a new fence register? */
584 if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
585 obj_priv->tiling_mode != I915_TILING_NONE) {
586 ret = i915_gem_object_get_fence_reg(obj, write);
588 mutex_unlock(&dev->struct_mutex);
589 return VM_FAULT_SIGBUS;
593 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
596 /* Finally, remap it using the new GTT offset */
597 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
599 mutex_unlock(&dev->struct_mutex);
606 return VM_FAULT_SIGBUS;
608 return VM_FAULT_NOPAGE;
613 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
614 * @obj: obj in question
616 * GEM memory mapping works by handing back to userspace a fake mmap offset
617 * it can use in a subsequent mmap(2) call. The DRM core code then looks
618 * up the object based on the offset and sets up the various memory mapping
621 * This routine allocates and attaches a fake offset for @obj.
624 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
626 struct drm_device *dev = obj->dev;
627 struct drm_gem_mm *mm = dev->mm_private;
628 struct drm_i915_gem_object *obj_priv = obj->driver_private;
629 struct drm_map_list *list;
633 /* Set the object up for mmap'ing */
634 list = &obj->map_list;
635 list->map = drm_calloc(1, sizeof(struct drm_map_list),
641 map->type = _DRM_GEM;
642 map->size = obj->size;
645 /* Get a DRM GEM mmap offset allocated... */
646 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
647 obj->size / PAGE_SIZE, 0, 0);
648 if (!list->file_offset_node) {
649 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
654 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
655 obj->size / PAGE_SIZE, 0);
656 if (!list->file_offset_node) {
661 list->hash.key = list->file_offset_node->start;
662 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
663 DRM_ERROR("failed to add to map hash\n");
667 /* By now we should be all set, any drm_mmap request on the offset
668 * below will get to our mmap & fault handler */
669 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
674 drm_mm_put_block(list->file_offset_node);
676 drm_free(list->map, sizeof(struct drm_map_list), DRM_MEM_DRIVER);
682 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
684 struct drm_device *dev = obj->dev;
685 struct drm_i915_gem_object *obj_priv = obj->driver_private;
686 struct drm_gem_mm *mm = dev->mm_private;
687 struct drm_map_list *list;
689 list = &obj->map_list;
690 drm_ht_remove_item(&mm->offset_hash, &list->hash);
692 if (list->file_offset_node) {
693 drm_mm_put_block(list->file_offset_node);
694 list->file_offset_node = NULL;
698 drm_free(list->map, sizeof(struct drm_map), DRM_MEM_DRIVER);
702 obj_priv->mmap_offset = 0;
706 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
707 * @obj: object to check
709 * Return the required GTT alignment for an object, taking into account
710 * potential fence register mapping if needed.
713 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
715 struct drm_device *dev = obj->dev;
716 struct drm_i915_gem_object *obj_priv = obj->driver_private;
720 * Minimum alignment is 4k (GTT page size), but might be greater
721 * if a fence register is needed for the object.
723 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
727 * Previous chips need to be aligned to the size of the smallest
728 * fence register that can contain the object.
735 for (i = start; i < obj->size; i <<= 1)
742 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
744 * @data: GTT mapping ioctl data
745 * @file_priv: GEM object info
747 * Simply returns the fake offset to userspace so it can mmap it.
748 * The mmap call will end up in drm_gem_mmap(), which will set things
749 * up so we can get faults in the handler above.
751 * The fault handler will take care of binding the object into the GTT
752 * (since it may have been evicted to make room for something), allocating
753 * a fence register, and mapping the appropriate aperture address into
757 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
758 struct drm_file *file_priv)
760 struct drm_i915_gem_mmap_gtt *args = data;
761 struct drm_i915_private *dev_priv = dev->dev_private;
762 struct drm_gem_object *obj;
763 struct drm_i915_gem_object *obj_priv;
766 if (!(dev->driver->driver_features & DRIVER_GEM))
769 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
773 mutex_lock(&dev->struct_mutex);
775 obj_priv = obj->driver_private;
777 if (!obj_priv->mmap_offset) {
778 ret = i915_gem_create_mmap_offset(obj);
780 drm_gem_object_unreference(obj);
781 mutex_unlock(&dev->struct_mutex);
786 args->offset = obj_priv->mmap_offset;
788 obj_priv->gtt_alignment = i915_gem_get_gtt_alignment(obj);
790 /* Make sure the alignment is correct for fence regs etc */
791 if (obj_priv->agp_mem &&
792 (obj_priv->gtt_offset & (obj_priv->gtt_alignment - 1))) {
793 drm_gem_object_unreference(obj);
794 mutex_unlock(&dev->struct_mutex);
799 * Pull it into the GTT so that we have a page list (makes the
800 * initial fault faster and any subsequent flushing possible).
802 if (!obj_priv->agp_mem) {
803 ret = i915_gem_object_bind_to_gtt(obj, obj_priv->gtt_alignment);
805 drm_gem_object_unreference(obj);
806 mutex_unlock(&dev->struct_mutex);
809 list_add(&obj_priv->list, &dev_priv->mm.inactive_list);
812 drm_gem_object_unreference(obj);
813 mutex_unlock(&dev->struct_mutex);
819 i915_gem_object_free_page_list(struct drm_gem_object *obj)
821 struct drm_i915_gem_object *obj_priv = obj->driver_private;
822 int page_count = obj->size / PAGE_SIZE;
825 if (obj_priv->page_list == NULL)
829 for (i = 0; i < page_count; i++)
830 if (obj_priv->page_list[i] != NULL) {
832 set_page_dirty(obj_priv->page_list[i]);
833 mark_page_accessed(obj_priv->page_list[i]);
834 page_cache_release(obj_priv->page_list[i]);
838 drm_free(obj_priv->page_list,
839 page_count * sizeof(struct page *),
841 obj_priv->page_list = NULL;
845 i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
847 struct drm_device *dev = obj->dev;
848 drm_i915_private_t *dev_priv = dev->dev_private;
849 struct drm_i915_gem_object *obj_priv = obj->driver_private;
851 /* Add a reference if we're newly entering the active list. */
852 if (!obj_priv->active) {
853 drm_gem_object_reference(obj);
854 obj_priv->active = 1;
856 /* Move from whatever list we were on to the tail of execution. */
857 list_move_tail(&obj_priv->list,
858 &dev_priv->mm.active_list);
859 obj_priv->last_rendering_seqno = seqno;
863 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
865 struct drm_device *dev = obj->dev;
866 drm_i915_private_t *dev_priv = dev->dev_private;
867 struct drm_i915_gem_object *obj_priv = obj->driver_private;
869 BUG_ON(!obj_priv->active);
870 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
871 obj_priv->last_rendering_seqno = 0;
875 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
877 struct drm_device *dev = obj->dev;
878 drm_i915_private_t *dev_priv = dev->dev_private;
879 struct drm_i915_gem_object *obj_priv = obj->driver_private;
881 i915_verify_inactive(dev, __FILE__, __LINE__);
882 if (obj_priv->pin_count != 0)
883 list_del_init(&obj_priv->list);
885 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
887 obj_priv->last_rendering_seqno = 0;
888 if (obj_priv->active) {
889 obj_priv->active = 0;
890 drm_gem_object_unreference(obj);
892 i915_verify_inactive(dev, __FILE__, __LINE__);
896 * Creates a new sequence number, emitting a write of it to the status page
897 * plus an interrupt, which will trigger i915_user_interrupt_handler.
899 * Must be called with struct_lock held.
901 * Returned sequence numbers are nonzero on success.
904 i915_add_request(struct drm_device *dev, uint32_t flush_domains)
906 drm_i915_private_t *dev_priv = dev->dev_private;
907 struct drm_i915_gem_request *request;
912 request = drm_calloc(1, sizeof(*request), DRM_MEM_DRIVER);
916 /* Grab the seqno we're going to make this request be, and bump the
917 * next (skipping 0 so it can be the reserved no-seqno value).
919 seqno = dev_priv->mm.next_gem_seqno;
920 dev_priv->mm.next_gem_seqno++;
921 if (dev_priv->mm.next_gem_seqno == 0)
922 dev_priv->mm.next_gem_seqno++;
925 OUT_RING(MI_STORE_DWORD_INDEX);
926 OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
929 OUT_RING(MI_USER_INTERRUPT);
932 DRM_DEBUG("%d\n", seqno);
934 request->seqno = seqno;
935 request->emitted_jiffies = jiffies;
936 was_empty = list_empty(&dev_priv->mm.request_list);
937 list_add_tail(&request->list, &dev_priv->mm.request_list);
939 /* Associate any objects on the flushing list matching the write
940 * domain we're flushing with our flush.
942 if (flush_domains != 0) {
943 struct drm_i915_gem_object *obj_priv, *next;
945 list_for_each_entry_safe(obj_priv, next,
946 &dev_priv->mm.flushing_list, list) {
947 struct drm_gem_object *obj = obj_priv->obj;
949 if ((obj->write_domain & flush_domains) ==
951 obj->write_domain = 0;
952 i915_gem_object_move_to_active(obj, seqno);
958 if (was_empty && !dev_priv->mm.suspended)
959 schedule_delayed_work(&dev_priv->mm.retire_work, HZ);
964 * Command execution barrier
966 * Ensures that all commands in the ring are finished
967 * before signalling the CPU
970 i915_retire_commands(struct drm_device *dev)
972 drm_i915_private_t *dev_priv = dev->dev_private;
973 uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
974 uint32_t flush_domains = 0;
977 /* The sampler always gets flushed on i965 (sigh) */
979 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
982 OUT_RING(0); /* noop */
984 return flush_domains;
988 * Moves buffers associated only with the given active seqno from the active
989 * to inactive list, potentially freeing them.
992 i915_gem_retire_request(struct drm_device *dev,
993 struct drm_i915_gem_request *request)
995 drm_i915_private_t *dev_priv = dev->dev_private;
997 /* Move any buffers on the active list that are no longer referenced
998 * by the ringbuffer to the flushing/inactive lists as appropriate.
1000 while (!list_empty(&dev_priv->mm.active_list)) {
1001 struct drm_gem_object *obj;
1002 struct drm_i915_gem_object *obj_priv;
1004 obj_priv = list_first_entry(&dev_priv->mm.active_list,
1005 struct drm_i915_gem_object,
1007 obj = obj_priv->obj;
1009 /* If the seqno being retired doesn't match the oldest in the
1010 * list, then the oldest in the list must still be newer than
1013 if (obj_priv->last_rendering_seqno != request->seqno)
1017 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1018 __func__, request->seqno, obj);
1021 if (obj->write_domain != 0)
1022 i915_gem_object_move_to_flushing(obj);
1024 i915_gem_object_move_to_inactive(obj);
1029 * Returns true if seq1 is later than seq2.
1032 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1034 return (int32_t)(seq1 - seq2) >= 0;
1038 i915_get_gem_seqno(struct drm_device *dev)
1040 drm_i915_private_t *dev_priv = dev->dev_private;
1042 return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
1046 * This function clears the request list as sequence numbers are passed.
1049 i915_gem_retire_requests(struct drm_device *dev)
1051 drm_i915_private_t *dev_priv = dev->dev_private;
1054 if (!dev_priv->hw_status_page)
1057 seqno = i915_get_gem_seqno(dev);
1059 while (!list_empty(&dev_priv->mm.request_list)) {
1060 struct drm_i915_gem_request *request;
1061 uint32_t retiring_seqno;
1063 request = list_first_entry(&dev_priv->mm.request_list,
1064 struct drm_i915_gem_request,
1066 retiring_seqno = request->seqno;
1068 if (i915_seqno_passed(seqno, retiring_seqno) ||
1069 dev_priv->mm.wedged) {
1070 i915_gem_retire_request(dev, request);
1072 list_del(&request->list);
1073 drm_free(request, sizeof(*request), DRM_MEM_DRIVER);
1080 i915_gem_retire_work_handler(struct work_struct *work)
1082 drm_i915_private_t *dev_priv;
1083 struct drm_device *dev;
1085 dev_priv = container_of(work, drm_i915_private_t,
1086 mm.retire_work.work);
1087 dev = dev_priv->dev;
1089 mutex_lock(&dev->struct_mutex);
1090 i915_gem_retire_requests(dev);
1091 if (!dev_priv->mm.suspended &&
1092 !list_empty(&dev_priv->mm.request_list))
1093 schedule_delayed_work(&dev_priv->mm.retire_work, HZ);
1094 mutex_unlock(&dev->struct_mutex);
1098 * Waits for a sequence number to be signaled, and cleans up the
1099 * request and object lists appropriately for that event.
1102 i915_wait_request(struct drm_device *dev, uint32_t seqno)
1104 drm_i915_private_t *dev_priv = dev->dev_private;
1109 if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
1110 dev_priv->mm.waiting_gem_seqno = seqno;
1111 i915_user_irq_get(dev);
1112 ret = wait_event_interruptible(dev_priv->irq_queue,
1113 i915_seqno_passed(i915_get_gem_seqno(dev),
1115 dev_priv->mm.wedged);
1116 i915_user_irq_put(dev);
1117 dev_priv->mm.waiting_gem_seqno = 0;
1119 if (dev_priv->mm.wedged)
1122 if (ret && ret != -ERESTARTSYS)
1123 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1124 __func__, ret, seqno, i915_get_gem_seqno(dev));
1126 /* Directly dispatch request retiring. While we have the work queue
1127 * to handle this, the waiter on a request often wants an associated
1128 * buffer to have made it to the inactive list, and we would need
1129 * a separate wait queue to handle that.
1132 i915_gem_retire_requests(dev);
1138 i915_gem_flush(struct drm_device *dev,
1139 uint32_t invalidate_domains,
1140 uint32_t flush_domains)
1142 drm_i915_private_t *dev_priv = dev->dev_private;
1147 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
1148 invalidate_domains, flush_domains);
1151 if (flush_domains & I915_GEM_DOMAIN_CPU)
1152 drm_agp_chipset_flush(dev);
1154 if ((invalidate_domains | flush_domains) & ~(I915_GEM_DOMAIN_CPU |
1155 I915_GEM_DOMAIN_GTT)) {
1157 * read/write caches:
1159 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1160 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
1161 * also flushed at 2d versus 3d pipeline switches.
1165 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1166 * MI_READ_FLUSH is set, and is always flushed on 965.
1168 * I915_GEM_DOMAIN_COMMAND may not exist?
1170 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1171 * invalidated when MI_EXE_FLUSH is set.
1173 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1174 * invalidated with every MI_FLUSH.
1178 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1179 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1180 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1181 * are flushed at any MI_FLUSH.
1184 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1185 if ((invalidate_domains|flush_domains) &
1186 I915_GEM_DOMAIN_RENDER)
1187 cmd &= ~MI_NO_WRITE_FLUSH;
1188 if (!IS_I965G(dev)) {
1190 * On the 965, the sampler cache always gets flushed
1191 * and this bit is reserved.
1193 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
1194 cmd |= MI_READ_FLUSH;
1196 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
1197 cmd |= MI_EXE_FLUSH;
1200 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
1204 OUT_RING(0); /* noop */
1210 * Ensures that all rendering to the object has completed and the object is
1211 * safe to unbind from the GTT or access from the CPU.
1214 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1216 struct drm_device *dev = obj->dev;
1217 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1220 /* This function only exists to support waiting for existing rendering,
1221 * not for emitting required flushes.
1223 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
1225 /* If there is rendering queued on the buffer being evicted, wait for
1228 if (obj_priv->active) {
1230 DRM_INFO("%s: object %p wait for seqno %08x\n",
1231 __func__, obj, obj_priv->last_rendering_seqno);
1233 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
1242 * Unbinds an object from the GTT aperture.
1245 i915_gem_object_unbind(struct drm_gem_object *obj)
1247 struct drm_device *dev = obj->dev;
1248 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1253 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1254 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1256 if (obj_priv->gtt_space == NULL)
1259 if (obj_priv->pin_count != 0) {
1260 DRM_ERROR("Attempting to unbind pinned buffer\n");
1264 /* Move the object to the CPU domain to ensure that
1265 * any possible CPU writes while it's not in the GTT
1266 * are flushed when we go to remap it. This will
1267 * also ensure that all pending GPU writes are finished
1270 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1272 if (ret != -ERESTARTSYS)
1273 DRM_ERROR("set_domain failed: %d\n", ret);
1277 if (obj_priv->agp_mem != NULL) {
1278 drm_unbind_agp(obj_priv->agp_mem);
1279 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
1280 obj_priv->agp_mem = NULL;
1283 BUG_ON(obj_priv->active);
1285 /* blow away mappings if mapped through GTT */
1286 offset = ((loff_t) obj->map_list.hash.key) << PAGE_SHIFT;
1287 if (dev->dev_mapping)
1288 unmap_mapping_range(dev->dev_mapping, offset, obj->size, 1);
1290 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
1291 i915_gem_clear_fence_reg(obj);
1293 i915_gem_object_free_page_list(obj);
1295 if (obj_priv->gtt_space) {
1296 atomic_dec(&dev->gtt_count);
1297 atomic_sub(obj->size, &dev->gtt_memory);
1299 drm_mm_put_block(obj_priv->gtt_space);
1300 obj_priv->gtt_space = NULL;
1303 /* Remove ourselves from the LRU list if present. */
1304 if (!list_empty(&obj_priv->list))
1305 list_del_init(&obj_priv->list);
1311 i915_gem_evict_something(struct drm_device *dev)
1313 drm_i915_private_t *dev_priv = dev->dev_private;
1314 struct drm_gem_object *obj;
1315 struct drm_i915_gem_object *obj_priv;
1319 /* If there's an inactive buffer available now, grab it
1322 if (!list_empty(&dev_priv->mm.inactive_list)) {
1323 obj_priv = list_first_entry(&dev_priv->mm.inactive_list,
1324 struct drm_i915_gem_object,
1326 obj = obj_priv->obj;
1327 BUG_ON(obj_priv->pin_count != 0);
1329 DRM_INFO("%s: evicting %p\n", __func__, obj);
1331 BUG_ON(obj_priv->active);
1333 /* Wait on the rendering and unbind the buffer. */
1334 ret = i915_gem_object_unbind(obj);
1338 /* If we didn't get anything, but the ring is still processing
1339 * things, wait for one of those things to finish and hopefully
1340 * leave us a buffer to evict.
1342 if (!list_empty(&dev_priv->mm.request_list)) {
1343 struct drm_i915_gem_request *request;
1345 request = list_first_entry(&dev_priv->mm.request_list,
1346 struct drm_i915_gem_request,
1349 ret = i915_wait_request(dev, request->seqno);
1353 /* if waiting caused an object to become inactive,
1354 * then loop around and wait for it. Otherwise, we
1355 * assume that waiting freed and unbound something,
1356 * so there should now be some space in the GTT
1358 if (!list_empty(&dev_priv->mm.inactive_list))
1363 /* If we didn't have anything on the request list but there
1364 * are buffers awaiting a flush, emit one and try again.
1365 * When we wait on it, those buffers waiting for that flush
1366 * will get moved to inactive.
1368 if (!list_empty(&dev_priv->mm.flushing_list)) {
1369 obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
1370 struct drm_i915_gem_object,
1372 obj = obj_priv->obj;
1377 i915_add_request(dev, obj->write_domain);
1383 DRM_ERROR("inactive empty %d request empty %d "
1384 "flushing empty %d\n",
1385 list_empty(&dev_priv->mm.inactive_list),
1386 list_empty(&dev_priv->mm.request_list),
1387 list_empty(&dev_priv->mm.flushing_list));
1388 /* If we didn't do any of the above, there's nothing to be done
1389 * and we just can't fit it in.
1397 i915_gem_evict_everything(struct drm_device *dev)
1402 ret = i915_gem_evict_something(dev);
1412 i915_gem_object_get_page_list(struct drm_gem_object *obj)
1414 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1416 struct address_space *mapping;
1417 struct inode *inode;
1421 if (obj_priv->page_list)
1424 /* Get the list of pages out of our struct file. They'll be pinned
1425 * at this point until we release them.
1427 page_count = obj->size / PAGE_SIZE;
1428 BUG_ON(obj_priv->page_list != NULL);
1429 obj_priv->page_list = drm_calloc(page_count, sizeof(struct page *),
1431 if (obj_priv->page_list == NULL) {
1432 DRM_ERROR("Faled to allocate page list\n");
1436 inode = obj->filp->f_path.dentry->d_inode;
1437 mapping = inode->i_mapping;
1438 for (i = 0; i < page_count; i++) {
1439 page = read_mapping_page(mapping, i, NULL);
1441 ret = PTR_ERR(page);
1442 DRM_ERROR("read_mapping_page failed: %d\n", ret);
1443 i915_gem_object_free_page_list(obj);
1446 obj_priv->page_list[i] = page;
1451 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
1453 struct drm_gem_object *obj = reg->obj;
1454 struct drm_device *dev = obj->dev;
1455 drm_i915_private_t *dev_priv = dev->dev_private;
1456 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1457 int regnum = obj_priv->fence_reg;
1460 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
1462 val |= obj_priv->gtt_offset & 0xfffff000;
1463 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
1464 if (obj_priv->tiling_mode == I915_TILING_Y)
1465 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
1466 val |= I965_FENCE_REG_VALID;
1468 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
1471 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
1473 struct drm_gem_object *obj = reg->obj;
1474 struct drm_device *dev = obj->dev;
1475 drm_i915_private_t *dev_priv = dev->dev_private;
1476 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1477 int regnum = obj_priv->fence_reg;
1482 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
1483 (obj_priv->gtt_offset & (obj->size - 1))) {
1484 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
1485 __func__, obj_priv->gtt_offset, obj->size);
1489 if (obj_priv->tiling_mode == I915_TILING_Y &&
1490 HAS_128_BYTE_Y_TILING(dev))
1495 /* Note: pitch better be a power of two tile widths */
1496 pitch_val = obj_priv->stride / tile_width;
1497 pitch_val = ffs(pitch_val) - 1;
1499 val = obj_priv->gtt_offset;
1500 if (obj_priv->tiling_mode == I915_TILING_Y)
1501 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
1502 val |= I915_FENCE_SIZE_BITS(obj->size);
1503 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
1504 val |= I830_FENCE_REG_VALID;
1506 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
1509 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
1511 struct drm_gem_object *obj = reg->obj;
1512 struct drm_device *dev = obj->dev;
1513 drm_i915_private_t *dev_priv = dev->dev_private;
1514 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1515 int regnum = obj_priv->fence_reg;
1519 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
1520 (obj_priv->gtt_offset & (obj->size - 1))) {
1521 WARN(1, "%s: object 0x%08x not 1M or size aligned\n",
1522 __func__, obj_priv->gtt_offset);
1526 pitch_val = (obj_priv->stride / 128) - 1;
1528 val = obj_priv->gtt_offset;
1529 if (obj_priv->tiling_mode == I915_TILING_Y)
1530 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
1531 val |= I830_FENCE_SIZE_BITS(obj->size);
1532 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
1533 val |= I830_FENCE_REG_VALID;
1535 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
1540 * i915_gem_object_get_fence_reg - set up a fence reg for an object
1541 * @obj: object to map through a fence reg
1542 * @write: object is about to be written
1544 * When mapping objects through the GTT, userspace wants to be able to write
1545 * to them without having to worry about swizzling if the object is tiled.
1547 * This function walks the fence regs looking for a free one for @obj,
1548 * stealing one if it can't find any.
1550 * It then sets up the reg based on the object's properties: address, pitch
1551 * and tiling format.
1554 i915_gem_object_get_fence_reg(struct drm_gem_object *obj, bool write)
1556 struct drm_device *dev = obj->dev;
1557 struct drm_i915_private *dev_priv = dev->dev_private;
1558 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1559 struct drm_i915_fence_reg *reg = NULL;
1560 struct drm_i915_gem_object *old_obj_priv = NULL;
1563 switch (obj_priv->tiling_mode) {
1564 case I915_TILING_NONE:
1565 WARN(1, "allocating a fence for non-tiled object?\n");
1568 if (!obj_priv->stride)
1570 WARN((obj_priv->stride & (512 - 1)),
1571 "object 0x%08x is X tiled but has non-512B pitch\n",
1572 obj_priv->gtt_offset);
1575 if (!obj_priv->stride)
1577 WARN((obj_priv->stride & (128 - 1)),
1578 "object 0x%08x is Y tiled but has non-128B pitch\n",
1579 obj_priv->gtt_offset);
1583 /* First try to find a free reg */
1586 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
1587 reg = &dev_priv->fence_regs[i];
1591 old_obj_priv = reg->obj->driver_private;
1592 if (!old_obj_priv->pin_count)
1596 /* None available, try to steal one or wait for a user to finish */
1597 if (i == dev_priv->num_fence_regs) {
1598 uint32_t seqno = dev_priv->mm.next_gem_seqno;
1604 for (i = dev_priv->fence_reg_start;
1605 i < dev_priv->num_fence_regs; i++) {
1606 uint32_t this_seqno;
1608 reg = &dev_priv->fence_regs[i];
1609 old_obj_priv = reg->obj->driver_private;
1611 if (old_obj_priv->pin_count)
1614 /* i915 uses fences for GPU access to tiled buffers */
1615 if (IS_I965G(dev) || !old_obj_priv->active)
1618 /* find the seqno of the first available fence */
1619 this_seqno = old_obj_priv->last_rendering_seqno;
1620 if (this_seqno != 0 &&
1621 reg->obj->write_domain == 0 &&
1622 i915_seqno_passed(seqno, this_seqno))
1627 * Now things get ugly... we have to wait for one of the
1628 * objects to finish before trying again.
1630 if (i == dev_priv->num_fence_regs) {
1631 if (seqno == dev_priv->mm.next_gem_seqno) {
1633 I915_GEM_GPU_DOMAINS,
1634 I915_GEM_GPU_DOMAINS);
1635 seqno = i915_add_request(dev,
1636 I915_GEM_GPU_DOMAINS);
1641 ret = i915_wait_request(dev, seqno);
1647 BUG_ON(old_obj_priv->active ||
1648 (reg->obj->write_domain & I915_GEM_GPU_DOMAINS));
1651 * Zap this virtual mapping so we can set up a fence again
1652 * for this object next time we need it.
1654 offset = ((loff_t) reg->obj->map_list.hash.key) << PAGE_SHIFT;
1655 if (dev->dev_mapping)
1656 unmap_mapping_range(dev->dev_mapping, offset,
1658 old_obj_priv->fence_reg = I915_FENCE_REG_NONE;
1661 obj_priv->fence_reg = i;
1665 i965_write_fence_reg(reg);
1666 else if (IS_I9XX(dev))
1667 i915_write_fence_reg(reg);
1669 i830_write_fence_reg(reg);
1675 * i915_gem_clear_fence_reg - clear out fence register info
1676 * @obj: object to clear
1678 * Zeroes out the fence register itself and clears out the associated
1679 * data structures in dev_priv and obj_priv.
1682 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
1684 struct drm_device *dev = obj->dev;
1685 drm_i915_private_t *dev_priv = dev->dev_private;
1686 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1689 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
1691 I915_WRITE(FENCE_REG_830_0 + (obj_priv->fence_reg * 4), 0);
1693 dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL;
1694 obj_priv->fence_reg = I915_FENCE_REG_NONE;
1698 * Finds free space in the GTT aperture and binds the object there.
1701 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
1703 struct drm_device *dev = obj->dev;
1704 drm_i915_private_t *dev_priv = dev->dev_private;
1705 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1706 struct drm_mm_node *free_space;
1707 int page_count, ret;
1709 if (dev_priv->mm.suspended)
1712 alignment = i915_gem_get_gtt_alignment(obj);
1713 if (alignment & (PAGE_SIZE - 1)) {
1714 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
1719 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
1720 obj->size, alignment, 0);
1721 if (free_space != NULL) {
1722 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
1724 if (obj_priv->gtt_space != NULL) {
1725 obj_priv->gtt_space->private = obj;
1726 obj_priv->gtt_offset = obj_priv->gtt_space->start;
1729 if (obj_priv->gtt_space == NULL) {
1730 /* If the gtt is empty and we're still having trouble
1731 * fitting our object in, we're out of memory.
1734 DRM_INFO("%s: GTT full, evicting something\n", __func__);
1736 if (list_empty(&dev_priv->mm.inactive_list) &&
1737 list_empty(&dev_priv->mm.flushing_list) &&
1738 list_empty(&dev_priv->mm.active_list)) {
1739 DRM_ERROR("GTT full, but LRU list empty\n");
1743 ret = i915_gem_evict_something(dev);
1745 if (ret != -ERESTARTSYS)
1746 DRM_ERROR("Failed to evict a buffer %d\n", ret);
1753 DRM_INFO("Binding object of size %d at 0x%08x\n",
1754 obj->size, obj_priv->gtt_offset);
1756 ret = i915_gem_object_get_page_list(obj);
1758 drm_mm_put_block(obj_priv->gtt_space);
1759 obj_priv->gtt_space = NULL;
1763 page_count = obj->size / PAGE_SIZE;
1764 /* Create an AGP memory structure pointing at our pages, and bind it
1767 obj_priv->agp_mem = drm_agp_bind_pages(dev,
1768 obj_priv->page_list,
1770 obj_priv->gtt_offset,
1771 obj_priv->agp_type);
1772 if (obj_priv->agp_mem == NULL) {
1773 i915_gem_object_free_page_list(obj);
1774 drm_mm_put_block(obj_priv->gtt_space);
1775 obj_priv->gtt_space = NULL;
1778 atomic_inc(&dev->gtt_count);
1779 atomic_add(obj->size, &dev->gtt_memory);
1781 /* Assert that the object is not currently in any GPU domain. As it
1782 * wasn't in the GTT, there shouldn't be any way it could have been in
1785 BUG_ON(obj->read_domains & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
1786 BUG_ON(obj->write_domain & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
1792 i915_gem_clflush_object(struct drm_gem_object *obj)
1794 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1796 /* If we don't have a page list set up, then we're not pinned
1797 * to GPU, and we can ignore the cache flush because it'll happen
1798 * again at bind time.
1800 if (obj_priv->page_list == NULL)
1803 drm_clflush_pages(obj_priv->page_list, obj->size / PAGE_SIZE);
1806 /** Flushes any GPU write domain for the object if it's dirty. */
1808 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
1810 struct drm_device *dev = obj->dev;
1813 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
1816 /* Queue the GPU write cache flushing we need. */
1817 i915_gem_flush(dev, 0, obj->write_domain);
1818 seqno = i915_add_request(dev, obj->write_domain);
1819 obj->write_domain = 0;
1820 i915_gem_object_move_to_active(obj, seqno);
1823 /** Flushes the GTT write domain for the object if it's dirty. */
1825 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
1827 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
1830 /* No actual flushing is required for the GTT write domain. Writes
1831 * to it immediately go to main memory as far as we know, so there's
1832 * no chipset flush. It also doesn't land in render cache.
1834 obj->write_domain = 0;
1837 /** Flushes the CPU write domain for the object if it's dirty. */
1839 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
1841 struct drm_device *dev = obj->dev;
1843 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
1846 i915_gem_clflush_object(obj);
1847 drm_agp_chipset_flush(dev);
1848 obj->write_domain = 0;
1852 * Moves a single object to the GTT read, and possibly write domain.
1854 * This function returns when the move is complete, including waiting on
1858 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
1860 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1863 /* Not valid to be called on unbound objects. */
1864 if (obj_priv->gtt_space == NULL)
1867 i915_gem_object_flush_gpu_write_domain(obj);
1868 /* Wait on any GPU rendering and flushing to occur. */
1869 ret = i915_gem_object_wait_rendering(obj);
1873 /* If we're writing through the GTT domain, then CPU and GPU caches
1874 * will need to be invalidated at next use.
1877 obj->read_domains &= I915_GEM_DOMAIN_GTT;
1879 i915_gem_object_flush_cpu_write_domain(obj);
1881 /* It should now be out of any other write domains, and we can update
1882 * the domain values for our changes.
1884 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
1885 obj->read_domains |= I915_GEM_DOMAIN_GTT;
1887 obj->write_domain = I915_GEM_DOMAIN_GTT;
1888 obj_priv->dirty = 1;
1895 * Moves a single object to the CPU read, and possibly write domain.
1897 * This function returns when the move is complete, including waiting on
1901 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
1903 struct drm_device *dev = obj->dev;
1906 i915_gem_object_flush_gpu_write_domain(obj);
1907 /* Wait on any GPU rendering and flushing to occur. */
1908 ret = i915_gem_object_wait_rendering(obj);
1912 i915_gem_object_flush_gtt_write_domain(obj);
1914 /* If we have a partially-valid cache of the object in the CPU,
1915 * finish invalidating it and free the per-page flags.
1917 i915_gem_object_set_to_full_cpu_read_domain(obj);
1919 /* Flush the CPU cache if it's still invalid. */
1920 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
1921 i915_gem_clflush_object(obj);
1922 drm_agp_chipset_flush(dev);
1924 obj->read_domains |= I915_GEM_DOMAIN_CPU;
1927 /* It should now be out of any other write domains, and we can update
1928 * the domain values for our changes.
1930 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
1932 /* If we're writing through the CPU, then the GPU read domains will
1933 * need to be invalidated at next use.
1936 obj->read_domains &= I915_GEM_DOMAIN_CPU;
1937 obj->write_domain = I915_GEM_DOMAIN_CPU;
1944 * Set the next domain for the specified object. This
1945 * may not actually perform the necessary flushing/invaliding though,
1946 * as that may want to be batched with other set_domain operations
1948 * This is (we hope) the only really tricky part of gem. The goal
1949 * is fairly simple -- track which caches hold bits of the object
1950 * and make sure they remain coherent. A few concrete examples may
1951 * help to explain how it works. For shorthand, we use the notation
1952 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
1953 * a pair of read and write domain masks.
1955 * Case 1: the batch buffer
1961 * 5. Unmapped from GTT
1964 * Let's take these a step at a time
1967 * Pages allocated from the kernel may still have
1968 * cache contents, so we set them to (CPU, CPU) always.
1969 * 2. Written by CPU (using pwrite)
1970 * The pwrite function calls set_domain (CPU, CPU) and
1971 * this function does nothing (as nothing changes)
1973 * This function asserts that the object is not
1974 * currently in any GPU-based read or write domains
1976 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
1977 * As write_domain is zero, this function adds in the
1978 * current read domains (CPU+COMMAND, 0).
1979 * flush_domains is set to CPU.
1980 * invalidate_domains is set to COMMAND
1981 * clflush is run to get data out of the CPU caches
1982 * then i915_dev_set_domain calls i915_gem_flush to
1983 * emit an MI_FLUSH and drm_agp_chipset_flush
1984 * 5. Unmapped from GTT
1985 * i915_gem_object_unbind calls set_domain (CPU, CPU)
1986 * flush_domains and invalidate_domains end up both zero
1987 * so no flushing/invalidating happens
1991 * Case 2: The shared render buffer
1995 * 3. Read/written by GPU
1996 * 4. set_domain to (CPU,CPU)
1997 * 5. Read/written by CPU
1998 * 6. Read/written by GPU
2001 * Same as last example, (CPU, CPU)
2003 * Nothing changes (assertions find that it is not in the GPU)
2004 * 3. Read/written by GPU
2005 * execbuffer calls set_domain (RENDER, RENDER)
2006 * flush_domains gets CPU
2007 * invalidate_domains gets GPU
2009 * MI_FLUSH and drm_agp_chipset_flush
2010 * 4. set_domain (CPU, CPU)
2011 * flush_domains gets GPU
2012 * invalidate_domains gets CPU
2013 * wait_rendering (obj) to make sure all drawing is complete.
2014 * This will include an MI_FLUSH to get the data from GPU
2016 * clflush (obj) to invalidate the CPU cache
2017 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
2018 * 5. Read/written by CPU
2019 * cache lines are loaded and dirtied
2020 * 6. Read written by GPU
2021 * Same as last GPU access
2023 * Case 3: The constant buffer
2028 * 4. Updated (written) by CPU again
2037 * flush_domains = CPU
2038 * invalidate_domains = RENDER
2041 * drm_agp_chipset_flush
2042 * 4. Updated (written) by CPU again
2044 * flush_domains = 0 (no previous write domain)
2045 * invalidate_domains = 0 (no new read domains)
2048 * flush_domains = CPU
2049 * invalidate_domains = RENDER
2052 * drm_agp_chipset_flush
2055 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
2057 struct drm_device *dev = obj->dev;
2058 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2059 uint32_t invalidate_domains = 0;
2060 uint32_t flush_domains = 0;
2062 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
2063 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
2066 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2068 obj->read_domains, obj->pending_read_domains,
2069 obj->write_domain, obj->pending_write_domain);
2072 * If the object isn't moving to a new write domain,
2073 * let the object stay in multiple read domains
2075 if (obj->pending_write_domain == 0)
2076 obj->pending_read_domains |= obj->read_domains;
2078 obj_priv->dirty = 1;
2081 * Flush the current write domain if
2082 * the new read domains don't match. Invalidate
2083 * any read domains which differ from the old
2086 if (obj->write_domain &&
2087 obj->write_domain != obj->pending_read_domains) {
2088 flush_domains |= obj->write_domain;
2089 invalidate_domains |=
2090 obj->pending_read_domains & ~obj->write_domain;
2093 * Invalidate any read caches which may have
2094 * stale data. That is, any new read domains.
2096 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
2097 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
2099 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
2100 __func__, flush_domains, invalidate_domains);
2102 i915_gem_clflush_object(obj);
2105 /* The actual obj->write_domain will be updated with
2106 * pending_write_domain after we emit the accumulated flush for all
2107 * of our domain changes in execbuffers (which clears objects'
2108 * write_domains). So if we have a current write domain that we
2109 * aren't changing, set pending_write_domain to that.
2111 if (flush_domains == 0 && obj->pending_write_domain == 0)
2112 obj->pending_write_domain = obj->write_domain;
2113 obj->read_domains = obj->pending_read_domains;
2115 dev->invalidate_domains |= invalidate_domains;
2116 dev->flush_domains |= flush_domains;
2118 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
2120 obj->read_domains, obj->write_domain,
2121 dev->invalidate_domains, dev->flush_domains);
2126 * Moves the object from a partially CPU read to a full one.
2128 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
2129 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
2132 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
2134 struct drm_device *dev = obj->dev;
2135 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2137 if (!obj_priv->page_cpu_valid)
2140 /* If we're partially in the CPU read domain, finish moving it in.
2142 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
2145 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
2146 if (obj_priv->page_cpu_valid[i])
2148 drm_clflush_pages(obj_priv->page_list + i, 1);
2150 drm_agp_chipset_flush(dev);
2153 /* Free the page_cpu_valid mappings which are now stale, whether
2154 * or not we've got I915_GEM_DOMAIN_CPU.
2156 drm_free(obj_priv->page_cpu_valid, obj->size / PAGE_SIZE,
2158 obj_priv->page_cpu_valid = NULL;
2162 * Set the CPU read domain on a range of the object.
2164 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
2165 * not entirely valid. The page_cpu_valid member of the object flags which
2166 * pages have been flushed, and will be respected by
2167 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
2168 * of the whole object.
2170 * This function returns when the move is complete, including waiting on
2174 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
2175 uint64_t offset, uint64_t size)
2177 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2180 if (offset == 0 && size == obj->size)
2181 return i915_gem_object_set_to_cpu_domain(obj, 0);
2183 i915_gem_object_flush_gpu_write_domain(obj);
2184 /* Wait on any GPU rendering and flushing to occur. */
2185 ret = i915_gem_object_wait_rendering(obj);
2188 i915_gem_object_flush_gtt_write_domain(obj);
2190 /* If we're already fully in the CPU read domain, we're done. */
2191 if (obj_priv->page_cpu_valid == NULL &&
2192 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
2195 /* Otherwise, create/clear the per-page CPU read domain flag if we're
2196 * newly adding I915_GEM_DOMAIN_CPU
2198 if (obj_priv->page_cpu_valid == NULL) {
2199 obj_priv->page_cpu_valid = drm_calloc(1, obj->size / PAGE_SIZE,
2201 if (obj_priv->page_cpu_valid == NULL)
2203 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
2204 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
2206 /* Flush the cache on any pages that are still invalid from the CPU's
2209 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
2211 if (obj_priv->page_cpu_valid[i])
2214 drm_clflush_pages(obj_priv->page_list + i, 1);
2216 obj_priv->page_cpu_valid[i] = 1;
2219 /* It should now be out of any other write domains, and we can update
2220 * the domain values for our changes.
2222 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2224 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2230 * Pin an object to the GTT and evaluate the relocations landing in it.
2233 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
2234 struct drm_file *file_priv,
2235 struct drm_i915_gem_exec_object *entry)
2237 struct drm_device *dev = obj->dev;
2238 drm_i915_private_t *dev_priv = dev->dev_private;
2239 struct drm_i915_gem_relocation_entry reloc;
2240 struct drm_i915_gem_relocation_entry __user *relocs;
2241 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2243 void __iomem *reloc_page;
2245 /* Choose the GTT offset for our buffer and put it there. */
2246 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
2250 entry->offset = obj_priv->gtt_offset;
2252 relocs = (struct drm_i915_gem_relocation_entry __user *)
2253 (uintptr_t) entry->relocs_ptr;
2254 /* Apply the relocations, using the GTT aperture to avoid cache
2255 * flushing requirements.
2257 for (i = 0; i < entry->relocation_count; i++) {
2258 struct drm_gem_object *target_obj;
2259 struct drm_i915_gem_object *target_obj_priv;
2260 uint32_t reloc_val, reloc_offset;
2261 uint32_t __iomem *reloc_entry;
2263 ret = copy_from_user(&reloc, relocs + i, sizeof(reloc));
2265 i915_gem_object_unpin(obj);
2269 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
2270 reloc.target_handle);
2271 if (target_obj == NULL) {
2272 i915_gem_object_unpin(obj);
2275 target_obj_priv = target_obj->driver_private;
2277 /* The target buffer should have appeared before us in the
2278 * exec_object list, so it should have a GTT space bound by now.
2280 if (target_obj_priv->gtt_space == NULL) {
2281 DRM_ERROR("No GTT space found for object %d\n",
2282 reloc.target_handle);
2283 drm_gem_object_unreference(target_obj);
2284 i915_gem_object_unpin(obj);
2288 if (reloc.offset > obj->size - 4) {
2289 DRM_ERROR("Relocation beyond object bounds: "
2290 "obj %p target %d offset %d size %d.\n",
2291 obj, reloc.target_handle,
2292 (int) reloc.offset, (int) obj->size);
2293 drm_gem_object_unreference(target_obj);
2294 i915_gem_object_unpin(obj);
2297 if (reloc.offset & 3) {
2298 DRM_ERROR("Relocation not 4-byte aligned: "
2299 "obj %p target %d offset %d.\n",
2300 obj, reloc.target_handle,
2301 (int) reloc.offset);
2302 drm_gem_object_unreference(target_obj);
2303 i915_gem_object_unpin(obj);
2307 if (reloc.write_domain & I915_GEM_DOMAIN_CPU ||
2308 reloc.read_domains & I915_GEM_DOMAIN_CPU) {
2309 DRM_ERROR("reloc with read/write CPU domains: "
2310 "obj %p target %d offset %d "
2311 "read %08x write %08x",
2312 obj, reloc.target_handle,
2315 reloc.write_domain);
2316 drm_gem_object_unreference(target_obj);
2317 i915_gem_object_unpin(obj);
2321 if (reloc.write_domain && target_obj->pending_write_domain &&
2322 reloc.write_domain != target_obj->pending_write_domain) {
2323 DRM_ERROR("Write domain conflict: "
2324 "obj %p target %d offset %d "
2325 "new %08x old %08x\n",
2326 obj, reloc.target_handle,
2329 target_obj->pending_write_domain);
2330 drm_gem_object_unreference(target_obj);
2331 i915_gem_object_unpin(obj);
2336 DRM_INFO("%s: obj %p offset %08x target %d "
2337 "read %08x write %08x gtt %08x "
2338 "presumed %08x delta %08x\n",
2342 (int) reloc.target_handle,
2343 (int) reloc.read_domains,
2344 (int) reloc.write_domain,
2345 (int) target_obj_priv->gtt_offset,
2346 (int) reloc.presumed_offset,
2350 target_obj->pending_read_domains |= reloc.read_domains;
2351 target_obj->pending_write_domain |= reloc.write_domain;
2353 /* If the relocation already has the right value in it, no
2354 * more work needs to be done.
2356 if (target_obj_priv->gtt_offset == reloc.presumed_offset) {
2357 drm_gem_object_unreference(target_obj);
2361 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
2363 drm_gem_object_unreference(target_obj);
2364 i915_gem_object_unpin(obj);
2368 /* Map the page containing the relocation we're going to
2371 reloc_offset = obj_priv->gtt_offset + reloc.offset;
2372 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
2375 reloc_entry = (uint32_t __iomem *)(reloc_page +
2376 (reloc_offset & (PAGE_SIZE - 1)));
2377 reloc_val = target_obj_priv->gtt_offset + reloc.delta;
2380 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
2381 obj, (unsigned int) reloc.offset,
2382 readl(reloc_entry), reloc_val);
2384 writel(reloc_val, reloc_entry);
2385 io_mapping_unmap_atomic(reloc_page);
2387 /* Write the updated presumed offset for this entry back out
2390 reloc.presumed_offset = target_obj_priv->gtt_offset;
2391 ret = copy_to_user(relocs + i, &reloc, sizeof(reloc));
2393 drm_gem_object_unreference(target_obj);
2394 i915_gem_object_unpin(obj);
2398 drm_gem_object_unreference(target_obj);
2403 i915_gem_dump_object(obj, 128, __func__, ~0);
2408 /** Dispatch a batchbuffer to the ring
2411 i915_dispatch_gem_execbuffer(struct drm_device *dev,
2412 struct drm_i915_gem_execbuffer *exec,
2413 uint64_t exec_offset)
2415 drm_i915_private_t *dev_priv = dev->dev_private;
2416 struct drm_clip_rect __user *boxes = (struct drm_clip_rect __user *)
2417 (uintptr_t) exec->cliprects_ptr;
2418 int nbox = exec->num_cliprects;
2420 uint32_t exec_start, exec_len;
2423 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
2424 exec_len = (uint32_t) exec->batch_len;
2426 if ((exec_start | exec_len) & 0x7) {
2427 DRM_ERROR("alignment\n");
2434 count = nbox ? nbox : 1;
2436 for (i = 0; i < count; i++) {
2438 int ret = i915_emit_box(dev, boxes, i,
2439 exec->DR1, exec->DR4);
2444 if (IS_I830(dev) || IS_845G(dev)) {
2446 OUT_RING(MI_BATCH_BUFFER);
2447 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
2448 OUT_RING(exec_start + exec_len - 4);
2453 if (IS_I965G(dev)) {
2454 OUT_RING(MI_BATCH_BUFFER_START |
2456 MI_BATCH_NON_SECURE_I965);
2457 OUT_RING(exec_start);
2459 OUT_RING(MI_BATCH_BUFFER_START |
2461 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
2467 /* XXX breadcrumb */
2471 /* Throttle our rendering by waiting until the ring has completed our requests
2472 * emitted over 20 msec ago.
2474 * This should get us reasonable parallelism between CPU and GPU but also
2475 * relatively low latency when blocking on a particular request to finish.
2478 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
2480 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
2484 mutex_lock(&dev->struct_mutex);
2485 seqno = i915_file_priv->mm.last_gem_throttle_seqno;
2486 i915_file_priv->mm.last_gem_throttle_seqno =
2487 i915_file_priv->mm.last_gem_seqno;
2489 ret = i915_wait_request(dev, seqno);
2490 mutex_unlock(&dev->struct_mutex);
2495 i915_gem_execbuffer(struct drm_device *dev, void *data,
2496 struct drm_file *file_priv)
2498 drm_i915_private_t *dev_priv = dev->dev_private;
2499 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
2500 struct drm_i915_gem_execbuffer *args = data;
2501 struct drm_i915_gem_exec_object *exec_list = NULL;
2502 struct drm_gem_object **object_list = NULL;
2503 struct drm_gem_object *batch_obj;
2504 struct drm_i915_gem_object *obj_priv;
2505 int ret, i, pinned = 0;
2506 uint64_t exec_offset;
2507 uint32_t seqno, flush_domains;
2511 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
2512 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
2515 if (args->buffer_count < 1) {
2516 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
2519 /* Copy in the exec list from userland */
2520 exec_list = drm_calloc(sizeof(*exec_list), args->buffer_count,
2522 object_list = drm_calloc(sizeof(*object_list), args->buffer_count,
2524 if (exec_list == NULL || object_list == NULL) {
2525 DRM_ERROR("Failed to allocate exec or object list "
2527 args->buffer_count);
2531 ret = copy_from_user(exec_list,
2532 (struct drm_i915_relocation_entry __user *)
2533 (uintptr_t) args->buffers_ptr,
2534 sizeof(*exec_list) * args->buffer_count);
2536 DRM_ERROR("copy %d exec entries failed %d\n",
2537 args->buffer_count, ret);
2541 mutex_lock(&dev->struct_mutex);
2543 i915_verify_inactive(dev, __FILE__, __LINE__);
2545 if (dev_priv->mm.wedged) {
2546 DRM_ERROR("Execbuf while wedged\n");
2547 mutex_unlock(&dev->struct_mutex);
2552 if (dev_priv->mm.suspended) {
2553 DRM_ERROR("Execbuf while VT-switched.\n");
2554 mutex_unlock(&dev->struct_mutex);
2559 /* Look up object handles */
2560 for (i = 0; i < args->buffer_count; i++) {
2561 object_list[i] = drm_gem_object_lookup(dev, file_priv,
2562 exec_list[i].handle);
2563 if (object_list[i] == NULL) {
2564 DRM_ERROR("Invalid object handle %d at index %d\n",
2565 exec_list[i].handle, i);
2570 obj_priv = object_list[i]->driver_private;
2571 if (obj_priv->in_execbuffer) {
2572 DRM_ERROR("Object %p appears more than once in object list\n",
2577 obj_priv->in_execbuffer = true;
2580 /* Pin and relocate */
2581 for (pin_tries = 0; ; pin_tries++) {
2583 for (i = 0; i < args->buffer_count; i++) {
2584 object_list[i]->pending_read_domains = 0;
2585 object_list[i]->pending_write_domain = 0;
2586 ret = i915_gem_object_pin_and_relocate(object_list[i],
2597 /* error other than GTT full, or we've already tried again */
2598 if (ret != -ENOMEM || pin_tries >= 1) {
2599 if (ret != -ERESTARTSYS)
2600 DRM_ERROR("Failed to pin buffers %d\n", ret);
2604 /* unpin all of our buffers */
2605 for (i = 0; i < pinned; i++)
2606 i915_gem_object_unpin(object_list[i]);
2609 /* evict everyone we can from the aperture */
2610 ret = i915_gem_evict_everything(dev);
2615 /* Set the pending read domains for the batch buffer to COMMAND */
2616 batch_obj = object_list[args->buffer_count-1];
2617 batch_obj->pending_read_domains = I915_GEM_DOMAIN_COMMAND;
2618 batch_obj->pending_write_domain = 0;
2620 i915_verify_inactive(dev, __FILE__, __LINE__);
2622 /* Zero the global flush/invalidate flags. These
2623 * will be modified as new domains are computed
2626 dev->invalidate_domains = 0;
2627 dev->flush_domains = 0;
2629 for (i = 0; i < args->buffer_count; i++) {
2630 struct drm_gem_object *obj = object_list[i];
2632 /* Compute new gpu domains and update invalidate/flush */
2633 i915_gem_object_set_to_gpu_domain(obj);
2636 i915_verify_inactive(dev, __FILE__, __LINE__);
2638 if (dev->invalidate_domains | dev->flush_domains) {
2640 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
2642 dev->invalidate_domains,
2643 dev->flush_domains);
2646 dev->invalidate_domains,
2647 dev->flush_domains);
2648 if (dev->flush_domains)
2649 (void)i915_add_request(dev, dev->flush_domains);
2652 for (i = 0; i < args->buffer_count; i++) {
2653 struct drm_gem_object *obj = object_list[i];
2655 obj->write_domain = obj->pending_write_domain;
2658 i915_verify_inactive(dev, __FILE__, __LINE__);
2661 for (i = 0; i < args->buffer_count; i++) {
2662 i915_gem_object_check_coherency(object_list[i],
2663 exec_list[i].handle);
2667 exec_offset = exec_list[args->buffer_count - 1].offset;
2670 i915_gem_dump_object(object_list[args->buffer_count - 1],
2676 /* Exec the batchbuffer */
2677 ret = i915_dispatch_gem_execbuffer(dev, args, exec_offset);
2679 DRM_ERROR("dispatch failed %d\n", ret);
2684 * Ensure that the commands in the batch buffer are
2685 * finished before the interrupt fires
2687 flush_domains = i915_retire_commands(dev);
2689 i915_verify_inactive(dev, __FILE__, __LINE__);
2692 * Get a seqno representing the execution of the current buffer,
2693 * which we can wait on. We would like to mitigate these interrupts,
2694 * likely by only creating seqnos occasionally (so that we have
2695 * *some* interrupts representing completion of buffers that we can
2696 * wait on when trying to clear up gtt space).
2698 seqno = i915_add_request(dev, flush_domains);
2700 i915_file_priv->mm.last_gem_seqno = seqno;
2701 for (i = 0; i < args->buffer_count; i++) {
2702 struct drm_gem_object *obj = object_list[i];
2704 i915_gem_object_move_to_active(obj, seqno);
2706 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
2710 i915_dump_lru(dev, __func__);
2713 i915_verify_inactive(dev, __FILE__, __LINE__);
2716 for (i = 0; i < pinned; i++)
2717 i915_gem_object_unpin(object_list[i]);
2719 for (i = 0; i < args->buffer_count; i++) {
2720 if (object_list[i]) {
2721 obj_priv = object_list[i]->driver_private;
2722 obj_priv->in_execbuffer = false;
2724 drm_gem_object_unreference(object_list[i]);
2727 mutex_unlock(&dev->struct_mutex);
2730 /* Copy the new buffer offsets back to the user's exec list. */
2731 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
2732 (uintptr_t) args->buffers_ptr,
2734 sizeof(*exec_list) * args->buffer_count);
2736 DRM_ERROR("failed to copy %d exec entries "
2737 "back to user (%d)\n",
2738 args->buffer_count, ret);
2742 drm_free(object_list, sizeof(*object_list) * args->buffer_count,
2744 drm_free(exec_list, sizeof(*exec_list) * args->buffer_count,
2751 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
2753 struct drm_device *dev = obj->dev;
2754 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2757 i915_verify_inactive(dev, __FILE__, __LINE__);
2758 if (obj_priv->gtt_space == NULL) {
2759 ret = i915_gem_object_bind_to_gtt(obj, alignment);
2761 if (ret != -EBUSY && ret != -ERESTARTSYS)
2762 DRM_ERROR("Failure to bind: %d\n", ret);
2767 * Pre-965 chips need a fence register set up in order to
2768 * properly handle tiled surfaces.
2770 if (!IS_I965G(dev) &&
2771 obj_priv->fence_reg == I915_FENCE_REG_NONE &&
2772 obj_priv->tiling_mode != I915_TILING_NONE) {
2773 ret = i915_gem_object_get_fence_reg(obj, true);
2775 if (ret != -EBUSY && ret != -ERESTARTSYS)
2776 DRM_ERROR("Failure to install fence: %d\n",
2781 obj_priv->pin_count++;
2783 /* If the object is not active and not pending a flush,
2784 * remove it from the inactive list
2786 if (obj_priv->pin_count == 1) {
2787 atomic_inc(&dev->pin_count);
2788 atomic_add(obj->size, &dev->pin_memory);
2789 if (!obj_priv->active &&
2790 (obj->write_domain & ~(I915_GEM_DOMAIN_CPU |
2791 I915_GEM_DOMAIN_GTT)) == 0 &&
2792 !list_empty(&obj_priv->list))
2793 list_del_init(&obj_priv->list);
2795 i915_verify_inactive(dev, __FILE__, __LINE__);
2801 i915_gem_object_unpin(struct drm_gem_object *obj)
2803 struct drm_device *dev = obj->dev;
2804 drm_i915_private_t *dev_priv = dev->dev_private;
2805 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2807 i915_verify_inactive(dev, __FILE__, __LINE__);
2808 obj_priv->pin_count--;
2809 BUG_ON(obj_priv->pin_count < 0);
2810 BUG_ON(obj_priv->gtt_space == NULL);
2812 /* If the object is no longer pinned, and is
2813 * neither active nor being flushed, then stick it on
2816 if (obj_priv->pin_count == 0) {
2817 if (!obj_priv->active &&
2818 (obj->write_domain & ~(I915_GEM_DOMAIN_CPU |
2819 I915_GEM_DOMAIN_GTT)) == 0)
2820 list_move_tail(&obj_priv->list,
2821 &dev_priv->mm.inactive_list);
2822 atomic_dec(&dev->pin_count);
2823 atomic_sub(obj->size, &dev->pin_memory);
2825 i915_verify_inactive(dev, __FILE__, __LINE__);
2829 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
2830 struct drm_file *file_priv)
2832 struct drm_i915_gem_pin *args = data;
2833 struct drm_gem_object *obj;
2834 struct drm_i915_gem_object *obj_priv;
2837 mutex_lock(&dev->struct_mutex);
2839 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2841 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
2843 mutex_unlock(&dev->struct_mutex);
2846 obj_priv = obj->driver_private;
2848 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
2849 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
2851 drm_gem_object_unreference(obj);
2852 mutex_unlock(&dev->struct_mutex);
2856 obj_priv->user_pin_count++;
2857 obj_priv->pin_filp = file_priv;
2858 if (obj_priv->user_pin_count == 1) {
2859 ret = i915_gem_object_pin(obj, args->alignment);
2861 drm_gem_object_unreference(obj);
2862 mutex_unlock(&dev->struct_mutex);
2867 /* XXX - flush the CPU caches for pinned objects
2868 * as the X server doesn't manage domains yet
2870 i915_gem_object_flush_cpu_write_domain(obj);
2871 args->offset = obj_priv->gtt_offset;
2872 drm_gem_object_unreference(obj);
2873 mutex_unlock(&dev->struct_mutex);
2879 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
2880 struct drm_file *file_priv)
2882 struct drm_i915_gem_pin *args = data;
2883 struct drm_gem_object *obj;
2884 struct drm_i915_gem_object *obj_priv;
2886 mutex_lock(&dev->struct_mutex);
2888 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2890 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
2892 mutex_unlock(&dev->struct_mutex);
2896 obj_priv = obj->driver_private;
2897 if (obj_priv->pin_filp != file_priv) {
2898 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
2900 drm_gem_object_unreference(obj);
2901 mutex_unlock(&dev->struct_mutex);
2904 obj_priv->user_pin_count--;
2905 if (obj_priv->user_pin_count == 0) {
2906 obj_priv->pin_filp = NULL;
2907 i915_gem_object_unpin(obj);
2910 drm_gem_object_unreference(obj);
2911 mutex_unlock(&dev->struct_mutex);
2916 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2917 struct drm_file *file_priv)
2919 struct drm_i915_gem_busy *args = data;
2920 struct drm_gem_object *obj;
2921 struct drm_i915_gem_object *obj_priv;
2923 mutex_lock(&dev->struct_mutex);
2924 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2926 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
2928 mutex_unlock(&dev->struct_mutex);
2932 /* Update the active list for the hardware's current position.
2933 * Otherwise this only updates on a delayed timer or when irqs are
2934 * actually unmasked, and our working set ends up being larger than
2937 i915_gem_retire_requests(dev);
2939 obj_priv = obj->driver_private;
2940 /* Don't count being on the flushing list against the object being
2941 * done. Otherwise, a buffer left on the flushing list but not getting
2942 * flushed (because nobody's flushing that domain) won't ever return
2943 * unbusy and get reused by libdrm's bo cache. The other expected
2944 * consumer of this interface, OpenGL's occlusion queries, also specs
2945 * that the objects get unbusy "eventually" without any interference.
2947 args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
2949 drm_gem_object_unreference(obj);
2950 mutex_unlock(&dev->struct_mutex);
2955 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2956 struct drm_file *file_priv)
2958 return i915_gem_ring_throttle(dev, file_priv);
2961 int i915_gem_init_object(struct drm_gem_object *obj)
2963 struct drm_i915_gem_object *obj_priv;
2965 obj_priv = drm_calloc(1, sizeof(*obj_priv), DRM_MEM_DRIVER);
2966 if (obj_priv == NULL)
2970 * We've just allocated pages from the kernel,
2971 * so they've just been written by the CPU with
2972 * zeros. They'll need to be clflushed before we
2973 * use them with the GPU.
2975 obj->write_domain = I915_GEM_DOMAIN_CPU;
2976 obj->read_domains = I915_GEM_DOMAIN_CPU;
2978 obj_priv->agp_type = AGP_USER_MEMORY;
2980 obj->driver_private = obj_priv;
2981 obj_priv->obj = obj;
2982 obj_priv->fence_reg = I915_FENCE_REG_NONE;
2983 INIT_LIST_HEAD(&obj_priv->list);
2988 void i915_gem_free_object(struct drm_gem_object *obj)
2990 struct drm_device *dev = obj->dev;
2991 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2993 while (obj_priv->pin_count > 0)
2994 i915_gem_object_unpin(obj);
2996 if (obj_priv->phys_obj)
2997 i915_gem_detach_phys_object(dev, obj);
2999 i915_gem_object_unbind(obj);
3001 i915_gem_free_mmap_offset(obj);
3003 drm_free(obj_priv->page_cpu_valid, 1, DRM_MEM_DRIVER);
3004 drm_free(obj->driver_private, 1, DRM_MEM_DRIVER);
3007 /** Unbinds all objects that are on the given buffer list. */
3009 i915_gem_evict_from_list(struct drm_device *dev, struct list_head *head)
3011 struct drm_gem_object *obj;
3012 struct drm_i915_gem_object *obj_priv;
3015 while (!list_empty(head)) {
3016 obj_priv = list_first_entry(head,
3017 struct drm_i915_gem_object,
3019 obj = obj_priv->obj;
3021 if (obj_priv->pin_count != 0) {
3022 DRM_ERROR("Pinned object in unbind list\n");
3023 mutex_unlock(&dev->struct_mutex);
3027 ret = i915_gem_object_unbind(obj);
3029 DRM_ERROR("Error unbinding object in LeaveVT: %d\n",
3031 mutex_unlock(&dev->struct_mutex);
3041 i915_gem_idle(struct drm_device *dev)
3043 drm_i915_private_t *dev_priv = dev->dev_private;
3044 uint32_t seqno, cur_seqno, last_seqno;
3047 mutex_lock(&dev->struct_mutex);
3049 if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
3050 mutex_unlock(&dev->struct_mutex);
3054 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3055 * We need to replace this with a semaphore, or something.
3057 dev_priv->mm.suspended = 1;
3059 /* Cancel the retire work handler, wait for it to finish if running
3061 mutex_unlock(&dev->struct_mutex);
3062 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3063 mutex_lock(&dev->struct_mutex);
3065 i915_kernel_lost_context(dev);
3067 /* Flush the GPU along with all non-CPU write domains
3069 i915_gem_flush(dev, ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT),
3070 ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
3071 seqno = i915_add_request(dev, ~I915_GEM_DOMAIN_CPU);
3074 mutex_unlock(&dev->struct_mutex);
3078 dev_priv->mm.waiting_gem_seqno = seqno;
3082 cur_seqno = i915_get_gem_seqno(dev);
3083 if (i915_seqno_passed(cur_seqno, seqno))
3085 if (last_seqno == cur_seqno) {
3086 if (stuck++ > 100) {
3087 DRM_ERROR("hardware wedged\n");
3088 dev_priv->mm.wedged = 1;
3089 DRM_WAKEUP(&dev_priv->irq_queue);
3094 last_seqno = cur_seqno;
3096 dev_priv->mm.waiting_gem_seqno = 0;
3098 i915_gem_retire_requests(dev);
3100 if (!dev_priv->mm.wedged) {
3101 /* Active and flushing should now be empty as we've
3102 * waited for a sequence higher than any pending execbuffer
3104 WARN_ON(!list_empty(&dev_priv->mm.active_list));
3105 WARN_ON(!list_empty(&dev_priv->mm.flushing_list));
3106 /* Request should now be empty as we've also waited
3107 * for the last request in the list
3109 WARN_ON(!list_empty(&dev_priv->mm.request_list));
3112 /* Empty the active and flushing lists to inactive. If there's
3113 * anything left at this point, it means that we're wedged and
3114 * nothing good's going to happen by leaving them there. So strip
3115 * the GPU domains and just stuff them onto inactive.
3117 while (!list_empty(&dev_priv->mm.active_list)) {
3118 struct drm_i915_gem_object *obj_priv;
3120 obj_priv = list_first_entry(&dev_priv->mm.active_list,
3121 struct drm_i915_gem_object,
3123 obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
3124 i915_gem_object_move_to_inactive(obj_priv->obj);
3127 while (!list_empty(&dev_priv->mm.flushing_list)) {
3128 struct drm_i915_gem_object *obj_priv;
3130 obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
3131 struct drm_i915_gem_object,
3133 obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
3134 i915_gem_object_move_to_inactive(obj_priv->obj);
3138 /* Move all inactive buffers out of the GTT. */
3139 ret = i915_gem_evict_from_list(dev, &dev_priv->mm.inactive_list);
3140 WARN_ON(!list_empty(&dev_priv->mm.inactive_list));
3142 mutex_unlock(&dev->struct_mutex);
3146 i915_gem_cleanup_ringbuffer(dev);
3147 mutex_unlock(&dev->struct_mutex);
3153 i915_gem_init_hws(struct drm_device *dev)
3155 drm_i915_private_t *dev_priv = dev->dev_private;
3156 struct drm_gem_object *obj;
3157 struct drm_i915_gem_object *obj_priv;
3160 /* If we need a physical address for the status page, it's already
3161 * initialized at driver load time.
3163 if (!I915_NEED_GFX_HWS(dev))
3166 obj = drm_gem_object_alloc(dev, 4096);
3168 DRM_ERROR("Failed to allocate status page\n");
3171 obj_priv = obj->driver_private;
3172 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
3174 ret = i915_gem_object_pin(obj, 4096);
3176 drm_gem_object_unreference(obj);
3180 dev_priv->status_gfx_addr = obj_priv->gtt_offset;
3182 dev_priv->hw_status_page = kmap(obj_priv->page_list[0]);
3183 if (dev_priv->hw_status_page == NULL) {
3184 DRM_ERROR("Failed to map status page.\n");
3185 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
3186 i915_gem_object_unpin(obj);
3187 drm_gem_object_unreference(obj);
3190 dev_priv->hws_obj = obj;
3191 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
3192 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
3193 I915_READ(HWS_PGA); /* posting read */
3194 DRM_DEBUG("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
3200 i915_gem_cleanup_hws(struct drm_device *dev)
3202 drm_i915_private_t *dev_priv = dev->dev_private;
3203 struct drm_gem_object *obj;
3204 struct drm_i915_gem_object *obj_priv;
3206 if (dev_priv->hws_obj == NULL)
3209 obj = dev_priv->hws_obj;
3210 obj_priv = obj->driver_private;
3212 kunmap(obj_priv->page_list[0]);
3213 i915_gem_object_unpin(obj);
3214 drm_gem_object_unreference(obj);
3215 dev_priv->hws_obj = NULL;
3217 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
3218 dev_priv->hw_status_page = NULL;
3220 /* Write high address into HWS_PGA when disabling. */
3221 I915_WRITE(HWS_PGA, 0x1ffff000);
3225 i915_gem_init_ringbuffer(struct drm_device *dev)
3227 drm_i915_private_t *dev_priv = dev->dev_private;
3228 struct drm_gem_object *obj;
3229 struct drm_i915_gem_object *obj_priv;
3230 drm_i915_ring_buffer_t *ring = &dev_priv->ring;
3234 ret = i915_gem_init_hws(dev);
3238 obj = drm_gem_object_alloc(dev, 128 * 1024);
3240 DRM_ERROR("Failed to allocate ringbuffer\n");
3241 i915_gem_cleanup_hws(dev);
3244 obj_priv = obj->driver_private;
3246 ret = i915_gem_object_pin(obj, 4096);
3248 drm_gem_object_unreference(obj);
3249 i915_gem_cleanup_hws(dev);
3253 /* Set up the kernel mapping for the ring. */
3254 ring->Size = obj->size;
3255 ring->tail_mask = obj->size - 1;
3257 ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
3258 ring->map.size = obj->size;
3260 ring->map.flags = 0;
3263 drm_core_ioremap_wc(&ring->map, dev);
3264 if (ring->map.handle == NULL) {
3265 DRM_ERROR("Failed to map ringbuffer.\n");
3266 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
3267 i915_gem_object_unpin(obj);
3268 drm_gem_object_unreference(obj);
3269 i915_gem_cleanup_hws(dev);
3272 ring->ring_obj = obj;
3273 ring->virtual_start = ring->map.handle;
3275 /* Stop the ring if it's running. */
3276 I915_WRITE(PRB0_CTL, 0);
3277 I915_WRITE(PRB0_TAIL, 0);
3278 I915_WRITE(PRB0_HEAD, 0);
3280 /* Initialize the ring. */
3281 I915_WRITE(PRB0_START, obj_priv->gtt_offset);
3282 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
3284 /* G45 ring initialization fails to reset head to zero */
3286 DRM_ERROR("Ring head not reset to zero "
3287 "ctl %08x head %08x tail %08x start %08x\n",
3288 I915_READ(PRB0_CTL),
3289 I915_READ(PRB0_HEAD),
3290 I915_READ(PRB0_TAIL),
3291 I915_READ(PRB0_START));
3292 I915_WRITE(PRB0_HEAD, 0);
3294 DRM_ERROR("Ring head forced to zero "
3295 "ctl %08x head %08x tail %08x start %08x\n",
3296 I915_READ(PRB0_CTL),
3297 I915_READ(PRB0_HEAD),
3298 I915_READ(PRB0_TAIL),
3299 I915_READ(PRB0_START));
3302 I915_WRITE(PRB0_CTL,
3303 ((obj->size - 4096) & RING_NR_PAGES) |
3307 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
3309 /* If the head is still not zero, the ring is dead */
3311 DRM_ERROR("Ring initialization failed "
3312 "ctl %08x head %08x tail %08x start %08x\n",
3313 I915_READ(PRB0_CTL),
3314 I915_READ(PRB0_HEAD),
3315 I915_READ(PRB0_TAIL),
3316 I915_READ(PRB0_START));
3320 /* Update our cache of the ring state */
3321 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3322 i915_kernel_lost_context(dev);
3324 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
3325 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
3326 ring->space = ring->head - (ring->tail + 8);
3327 if (ring->space < 0)
3328 ring->space += ring->Size;
3335 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
3337 drm_i915_private_t *dev_priv = dev->dev_private;
3339 if (dev_priv->ring.ring_obj == NULL)
3342 drm_core_ioremapfree(&dev_priv->ring.map, dev);
3344 i915_gem_object_unpin(dev_priv->ring.ring_obj);
3345 drm_gem_object_unreference(dev_priv->ring.ring_obj);
3346 dev_priv->ring.ring_obj = NULL;
3347 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
3349 i915_gem_cleanup_hws(dev);
3353 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
3354 struct drm_file *file_priv)
3356 drm_i915_private_t *dev_priv = dev->dev_private;
3359 if (drm_core_check_feature(dev, DRIVER_MODESET))
3362 if (dev_priv->mm.wedged) {
3363 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3364 dev_priv->mm.wedged = 0;
3367 mutex_lock(&dev->struct_mutex);
3368 dev_priv->mm.suspended = 0;
3370 ret = i915_gem_init_ringbuffer(dev);
3374 BUG_ON(!list_empty(&dev_priv->mm.active_list));
3375 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
3376 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
3377 BUG_ON(!list_empty(&dev_priv->mm.request_list));
3378 mutex_unlock(&dev->struct_mutex);
3380 drm_irq_install(dev);
3386 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
3387 struct drm_file *file_priv)
3391 if (drm_core_check_feature(dev, DRIVER_MODESET))
3394 ret = i915_gem_idle(dev);
3395 drm_irq_uninstall(dev);
3401 i915_gem_lastclose(struct drm_device *dev)
3405 if (drm_core_check_feature(dev, DRIVER_MODESET))
3408 ret = i915_gem_idle(dev);
3410 DRM_ERROR("failed to idle hardware: %d\n", ret);
3414 i915_gem_load(struct drm_device *dev)
3416 drm_i915_private_t *dev_priv = dev->dev_private;
3418 INIT_LIST_HEAD(&dev_priv->mm.active_list);
3419 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
3420 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
3421 INIT_LIST_HEAD(&dev_priv->mm.request_list);
3422 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
3423 i915_gem_retire_work_handler);
3424 dev_priv->mm.next_gem_seqno = 1;
3426 /* Old X drivers will take 0-2 for front, back, depth buffers */
3427 dev_priv->fence_reg_start = 3;
3429 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3430 dev_priv->num_fence_regs = 16;
3432 dev_priv->num_fence_regs = 8;
3434 i915_gem_detect_bit_6_swizzle(dev);
3438 * Create a physically contiguous memory object for this object
3439 * e.g. for cursor + overlay regs
3441 int i915_gem_init_phys_object(struct drm_device *dev,
3444 drm_i915_private_t *dev_priv = dev->dev_private;
3445 struct drm_i915_gem_phys_object *phys_obj;
3448 if (dev_priv->mm.phys_objs[id - 1] || !size)
3451 phys_obj = drm_calloc(1, sizeof(struct drm_i915_gem_phys_object), DRM_MEM_DRIVER);
3457 phys_obj->handle = drm_pci_alloc(dev, size, 0, 0xffffffff);
3458 if (!phys_obj->handle) {
3463 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3466 dev_priv->mm.phys_objs[id - 1] = phys_obj;
3470 drm_free(phys_obj, sizeof(struct drm_i915_gem_phys_object), DRM_MEM_DRIVER);
3474 void i915_gem_free_phys_object(struct drm_device *dev, int id)
3476 drm_i915_private_t *dev_priv = dev->dev_private;
3477 struct drm_i915_gem_phys_object *phys_obj;
3479 if (!dev_priv->mm.phys_objs[id - 1])
3482 phys_obj = dev_priv->mm.phys_objs[id - 1];
3483 if (phys_obj->cur_obj) {
3484 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
3488 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3490 drm_pci_free(dev, phys_obj->handle);
3492 dev_priv->mm.phys_objs[id - 1] = NULL;
3495 void i915_gem_free_all_phys_object(struct drm_device *dev)
3499 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
3500 i915_gem_free_phys_object(dev, i);
3503 void i915_gem_detach_phys_object(struct drm_device *dev,
3504 struct drm_gem_object *obj)
3506 struct drm_i915_gem_object *obj_priv;
3511 obj_priv = obj->driver_private;
3512 if (!obj_priv->phys_obj)
3515 ret = i915_gem_object_get_page_list(obj);
3519 page_count = obj->size / PAGE_SIZE;
3521 for (i = 0; i < page_count; i++) {
3522 char *dst = kmap_atomic(obj_priv->page_list[i], KM_USER0);
3523 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
3525 memcpy(dst, src, PAGE_SIZE);
3526 kunmap_atomic(dst, KM_USER0);
3528 drm_clflush_pages(obj_priv->page_list, page_count);
3529 drm_agp_chipset_flush(dev);
3531 obj_priv->phys_obj->cur_obj = NULL;
3532 obj_priv->phys_obj = NULL;
3536 i915_gem_attach_phys_object(struct drm_device *dev,
3537 struct drm_gem_object *obj, int id)
3539 drm_i915_private_t *dev_priv = dev->dev_private;
3540 struct drm_i915_gem_object *obj_priv;
3545 if (id > I915_MAX_PHYS_OBJECT)
3548 obj_priv = obj->driver_private;
3550 if (obj_priv->phys_obj) {
3551 if (obj_priv->phys_obj->id == id)
3553 i915_gem_detach_phys_object(dev, obj);
3557 /* create a new object */
3558 if (!dev_priv->mm.phys_objs[id - 1]) {
3559 ret = i915_gem_init_phys_object(dev, id,
3562 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
3567 /* bind to the object */
3568 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
3569 obj_priv->phys_obj->cur_obj = obj;
3571 ret = i915_gem_object_get_page_list(obj);
3573 DRM_ERROR("failed to get page list\n");
3577 page_count = obj->size / PAGE_SIZE;
3579 for (i = 0; i < page_count; i++) {
3580 char *src = kmap_atomic(obj_priv->page_list[i], KM_USER0);
3581 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
3583 memcpy(dst, src, PAGE_SIZE);
3584 kunmap_atomic(src, KM_USER0);
3593 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
3594 struct drm_i915_gem_pwrite *args,
3595 struct drm_file *file_priv)
3597 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3600 char __user *user_data;
3602 user_data = (char __user *) (uintptr_t) args->data_ptr;
3603 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
3605 DRM_DEBUG("obj_addr %p, %lld\n", obj_addr, args->size);
3606 ret = copy_from_user(obj_addr, user_data, args->size);
3610 drm_agp_chipset_flush(dev);