2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
38 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
39 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
40 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
41 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
43 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
46 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
47 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
48 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
50 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
51 static int i915_gem_evict_something(struct drm_device *dev, int min_size);
52 static int i915_gem_evict_from_inactive_list(struct drm_device *dev);
53 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
54 struct drm_i915_gem_pwrite *args,
55 struct drm_file *file_priv);
57 static LIST_HEAD(shrink_list);
58 static DEFINE_SPINLOCK(shrink_list_lock);
60 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
63 drm_i915_private_t *dev_priv = dev->dev_private;
66 (start & (PAGE_SIZE - 1)) != 0 ||
67 (end & (PAGE_SIZE - 1)) != 0) {
71 drm_mm_init(&dev_priv->mm.gtt_space, start,
74 dev->gtt_total = (uint32_t) (end - start);
80 i915_gem_init_ioctl(struct drm_device *dev, void *data,
81 struct drm_file *file_priv)
83 struct drm_i915_gem_init *args = data;
86 mutex_lock(&dev->struct_mutex);
87 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
88 mutex_unlock(&dev->struct_mutex);
94 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
95 struct drm_file *file_priv)
97 struct drm_i915_gem_get_aperture *args = data;
99 if (!(dev->driver->driver_features & DRIVER_GEM))
102 args->aper_size = dev->gtt_total;
103 args->aper_available_size = (args->aper_size -
104 atomic_read(&dev->pin_memory));
111 * Creates a new mm object and returns a handle to it.
114 i915_gem_create_ioctl(struct drm_device *dev, void *data,
115 struct drm_file *file_priv)
117 struct drm_i915_gem_create *args = data;
118 struct drm_gem_object *obj;
122 args->size = roundup(args->size, PAGE_SIZE);
124 /* Allocate the new object */
125 obj = i915_gem_alloc_object(dev, args->size);
129 ret = drm_gem_handle_create(file_priv, obj, &handle);
130 drm_gem_object_handle_unreference_unlocked(obj);
135 args->handle = handle;
141 fast_shmem_read(struct page **pages,
142 loff_t page_base, int page_offset,
149 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
152 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
153 kunmap_atomic(vaddr, KM_USER0);
161 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
163 drm_i915_private_t *dev_priv = obj->dev->dev_private;
164 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
166 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
167 obj_priv->tiling_mode != I915_TILING_NONE;
171 slow_shmem_copy(struct page *dst_page,
173 struct page *src_page,
177 char *dst_vaddr, *src_vaddr;
179 dst_vaddr = kmap_atomic(dst_page, KM_USER0);
180 if (dst_vaddr == NULL)
183 src_vaddr = kmap_atomic(src_page, KM_USER1);
184 if (src_vaddr == NULL) {
185 kunmap_atomic(dst_vaddr, KM_USER0);
189 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
191 kunmap_atomic(src_vaddr, KM_USER1);
192 kunmap_atomic(dst_vaddr, KM_USER0);
198 slow_shmem_bit17_copy(struct page *gpu_page,
200 struct page *cpu_page,
205 char *gpu_vaddr, *cpu_vaddr;
207 /* Use the unswizzled path if this page isn't affected. */
208 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
210 return slow_shmem_copy(cpu_page, cpu_offset,
211 gpu_page, gpu_offset, length);
213 return slow_shmem_copy(gpu_page, gpu_offset,
214 cpu_page, cpu_offset, length);
217 gpu_vaddr = kmap_atomic(gpu_page, KM_USER0);
218 if (gpu_vaddr == NULL)
221 cpu_vaddr = kmap_atomic(cpu_page, KM_USER1);
222 if (cpu_vaddr == NULL) {
223 kunmap_atomic(gpu_vaddr, KM_USER0);
227 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
228 * XORing with the other bits (A9 for Y, A9 and A10 for X)
231 int cacheline_end = ALIGN(gpu_offset + 1, 64);
232 int this_length = min(cacheline_end - gpu_offset, length);
233 int swizzled_gpu_offset = gpu_offset ^ 64;
236 memcpy(cpu_vaddr + cpu_offset,
237 gpu_vaddr + swizzled_gpu_offset,
240 memcpy(gpu_vaddr + swizzled_gpu_offset,
241 cpu_vaddr + cpu_offset,
244 cpu_offset += this_length;
245 gpu_offset += this_length;
246 length -= this_length;
249 kunmap_atomic(cpu_vaddr, KM_USER1);
250 kunmap_atomic(gpu_vaddr, KM_USER0);
256 * This is the fast shmem pread path, which attempts to copy_from_user directly
257 * from the backing pages of the object to the user's address space. On a
258 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
261 i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
262 struct drm_i915_gem_pread *args,
263 struct drm_file *file_priv)
265 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
267 loff_t offset, page_base;
268 char __user *user_data;
269 int page_offset, page_length;
272 user_data = (char __user *) (uintptr_t) args->data_ptr;
275 mutex_lock(&dev->struct_mutex);
277 ret = i915_gem_object_get_pages(obj, 0);
281 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
286 obj_priv = to_intel_bo(obj);
287 offset = args->offset;
290 /* Operation in this page
292 * page_base = page offset within aperture
293 * page_offset = offset within page
294 * page_length = bytes to copy for this page
296 page_base = (offset & ~(PAGE_SIZE-1));
297 page_offset = offset & (PAGE_SIZE-1);
298 page_length = remain;
299 if ((page_offset + remain) > PAGE_SIZE)
300 page_length = PAGE_SIZE - page_offset;
302 ret = fast_shmem_read(obj_priv->pages,
303 page_base, page_offset,
304 user_data, page_length);
308 remain -= page_length;
309 user_data += page_length;
310 offset += page_length;
314 i915_gem_object_put_pages(obj);
316 mutex_unlock(&dev->struct_mutex);
322 i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
326 ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
328 /* If we've insufficient memory to map in the pages, attempt
329 * to make some space by throwing out some old buffers.
331 if (ret == -ENOMEM) {
332 struct drm_device *dev = obj->dev;
334 ret = i915_gem_evict_something(dev, obj->size);
338 ret = i915_gem_object_get_pages(obj, 0);
345 * This is the fallback shmem pread path, which allocates temporary storage
346 * in kernel space to copy_to_user into outside of the struct_mutex, so we
347 * can copy out of the object's backing pages while holding the struct mutex
348 * and not take page faults.
351 i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
352 struct drm_i915_gem_pread *args,
353 struct drm_file *file_priv)
355 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
356 struct mm_struct *mm = current->mm;
357 struct page **user_pages;
359 loff_t offset, pinned_pages, i;
360 loff_t first_data_page, last_data_page, num_pages;
361 int shmem_page_index, shmem_page_offset;
362 int data_page_index, data_page_offset;
365 uint64_t data_ptr = args->data_ptr;
366 int do_bit17_swizzling;
370 /* Pin the user pages containing the data. We can't fault while
371 * holding the struct mutex, yet we want to hold it while
372 * dereferencing the user data.
374 first_data_page = data_ptr / PAGE_SIZE;
375 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
376 num_pages = last_data_page - first_data_page + 1;
378 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
379 if (user_pages == NULL)
382 down_read(&mm->mmap_sem);
383 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
384 num_pages, 1, 0, user_pages, NULL);
385 up_read(&mm->mmap_sem);
386 if (pinned_pages < num_pages) {
388 goto fail_put_user_pages;
391 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
393 mutex_lock(&dev->struct_mutex);
395 ret = i915_gem_object_get_pages_or_evict(obj);
399 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
404 obj_priv = to_intel_bo(obj);
405 offset = args->offset;
408 /* Operation in this page
410 * shmem_page_index = page number within shmem file
411 * shmem_page_offset = offset within page in shmem file
412 * data_page_index = page number in get_user_pages return
413 * data_page_offset = offset with data_page_index page.
414 * page_length = bytes to copy for this page
416 shmem_page_index = offset / PAGE_SIZE;
417 shmem_page_offset = offset & ~PAGE_MASK;
418 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
419 data_page_offset = data_ptr & ~PAGE_MASK;
421 page_length = remain;
422 if ((shmem_page_offset + page_length) > PAGE_SIZE)
423 page_length = PAGE_SIZE - shmem_page_offset;
424 if ((data_page_offset + page_length) > PAGE_SIZE)
425 page_length = PAGE_SIZE - data_page_offset;
427 if (do_bit17_swizzling) {
428 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
430 user_pages[data_page_index],
435 ret = slow_shmem_copy(user_pages[data_page_index],
437 obj_priv->pages[shmem_page_index],
444 remain -= page_length;
445 data_ptr += page_length;
446 offset += page_length;
450 i915_gem_object_put_pages(obj);
452 mutex_unlock(&dev->struct_mutex);
454 for (i = 0; i < pinned_pages; i++) {
455 SetPageDirty(user_pages[i]);
456 page_cache_release(user_pages[i]);
458 drm_free_large(user_pages);
464 * Reads data from the object referenced by handle.
466 * On error, the contents of *data are undefined.
469 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
470 struct drm_file *file_priv)
472 struct drm_i915_gem_pread *args = data;
473 struct drm_gem_object *obj;
474 struct drm_i915_gem_object *obj_priv;
477 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
480 obj_priv = to_intel_bo(obj);
482 /* Bounds check source.
484 * XXX: This could use review for overflow issues...
486 if (args->offset > obj->size || args->size > obj->size ||
487 args->offset + args->size > obj->size) {
488 drm_gem_object_unreference_unlocked(obj);
492 if (i915_gem_object_needs_bit17_swizzle(obj)) {
493 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
495 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
497 ret = i915_gem_shmem_pread_slow(dev, obj, args,
501 drm_gem_object_unreference_unlocked(obj);
506 /* This is the fast write path which cannot handle
507 * page faults in the source data
511 fast_user_write(struct io_mapping *mapping,
512 loff_t page_base, int page_offset,
513 char __user *user_data,
517 unsigned long unwritten;
519 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
520 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
522 io_mapping_unmap_atomic(vaddr_atomic);
528 /* Here's the write path which can sleep for
533 slow_kernel_write(struct io_mapping *mapping,
534 loff_t gtt_base, int gtt_offset,
535 struct page *user_page, int user_offset,
538 char *src_vaddr, *dst_vaddr;
539 unsigned long unwritten;
541 dst_vaddr = io_mapping_map_atomic_wc(mapping, gtt_base);
542 src_vaddr = kmap_atomic(user_page, KM_USER1);
543 unwritten = __copy_from_user_inatomic_nocache(dst_vaddr + gtt_offset,
544 src_vaddr + user_offset,
546 kunmap_atomic(src_vaddr, KM_USER1);
547 io_mapping_unmap_atomic(dst_vaddr);
554 fast_shmem_write(struct page **pages,
555 loff_t page_base, int page_offset,
560 unsigned long unwritten;
562 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
565 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
566 kunmap_atomic(vaddr, KM_USER0);
574 * This is the fast pwrite path, where we copy the data directly from the
575 * user into the GTT, uncached.
578 i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
579 struct drm_i915_gem_pwrite *args,
580 struct drm_file *file_priv)
582 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
583 drm_i915_private_t *dev_priv = dev->dev_private;
585 loff_t offset, page_base;
586 char __user *user_data;
587 int page_offset, page_length;
590 user_data = (char __user *) (uintptr_t) args->data_ptr;
592 if (!access_ok(VERIFY_READ, user_data, remain))
596 mutex_lock(&dev->struct_mutex);
597 ret = i915_gem_object_pin(obj, 0);
599 mutex_unlock(&dev->struct_mutex);
602 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
606 obj_priv = to_intel_bo(obj);
607 offset = obj_priv->gtt_offset + args->offset;
610 /* Operation in this page
612 * page_base = page offset within aperture
613 * page_offset = offset within page
614 * page_length = bytes to copy for this page
616 page_base = (offset & ~(PAGE_SIZE-1));
617 page_offset = offset & (PAGE_SIZE-1);
618 page_length = remain;
619 if ((page_offset + remain) > PAGE_SIZE)
620 page_length = PAGE_SIZE - page_offset;
622 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
623 page_offset, user_data, page_length);
625 /* If we get a fault while copying data, then (presumably) our
626 * source page isn't available. Return the error and we'll
627 * retry in the slow path.
632 remain -= page_length;
633 user_data += page_length;
634 offset += page_length;
638 i915_gem_object_unpin(obj);
639 mutex_unlock(&dev->struct_mutex);
645 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
646 * the memory and maps it using kmap_atomic for copying.
648 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
649 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
652 i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
653 struct drm_i915_gem_pwrite *args,
654 struct drm_file *file_priv)
656 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
657 drm_i915_private_t *dev_priv = dev->dev_private;
659 loff_t gtt_page_base, offset;
660 loff_t first_data_page, last_data_page, num_pages;
661 loff_t pinned_pages, i;
662 struct page **user_pages;
663 struct mm_struct *mm = current->mm;
664 int gtt_page_offset, data_page_offset, data_page_index, page_length;
666 uint64_t data_ptr = args->data_ptr;
670 /* Pin the user pages containing the data. We can't fault while
671 * holding the struct mutex, and all of the pwrite implementations
672 * want to hold it while dereferencing the user data.
674 first_data_page = data_ptr / PAGE_SIZE;
675 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
676 num_pages = last_data_page - first_data_page + 1;
678 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
679 if (user_pages == NULL)
682 down_read(&mm->mmap_sem);
683 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
684 num_pages, 0, 0, user_pages, NULL);
685 up_read(&mm->mmap_sem);
686 if (pinned_pages < num_pages) {
688 goto out_unpin_pages;
691 mutex_lock(&dev->struct_mutex);
692 ret = i915_gem_object_pin(obj, 0);
696 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
698 goto out_unpin_object;
700 obj_priv = to_intel_bo(obj);
701 offset = obj_priv->gtt_offset + args->offset;
704 /* Operation in this page
706 * gtt_page_base = page offset within aperture
707 * gtt_page_offset = offset within page in aperture
708 * data_page_index = page number in get_user_pages return
709 * data_page_offset = offset with data_page_index page.
710 * page_length = bytes to copy for this page
712 gtt_page_base = offset & PAGE_MASK;
713 gtt_page_offset = offset & ~PAGE_MASK;
714 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
715 data_page_offset = data_ptr & ~PAGE_MASK;
717 page_length = remain;
718 if ((gtt_page_offset + page_length) > PAGE_SIZE)
719 page_length = PAGE_SIZE - gtt_page_offset;
720 if ((data_page_offset + page_length) > PAGE_SIZE)
721 page_length = PAGE_SIZE - data_page_offset;
723 ret = slow_kernel_write(dev_priv->mm.gtt_mapping,
724 gtt_page_base, gtt_page_offset,
725 user_pages[data_page_index],
729 /* If we get a fault while copying data, then (presumably) our
730 * source page isn't available. Return the error and we'll
731 * retry in the slow path.
734 goto out_unpin_object;
736 remain -= page_length;
737 offset += page_length;
738 data_ptr += page_length;
742 i915_gem_object_unpin(obj);
744 mutex_unlock(&dev->struct_mutex);
746 for (i = 0; i < pinned_pages; i++)
747 page_cache_release(user_pages[i]);
748 drm_free_large(user_pages);
754 * This is the fast shmem pwrite path, which attempts to directly
755 * copy_from_user into the kmapped pages backing the object.
758 i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
759 struct drm_i915_gem_pwrite *args,
760 struct drm_file *file_priv)
762 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
764 loff_t offset, page_base;
765 char __user *user_data;
766 int page_offset, page_length;
769 user_data = (char __user *) (uintptr_t) args->data_ptr;
772 mutex_lock(&dev->struct_mutex);
774 ret = i915_gem_object_get_pages(obj, 0);
778 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
782 obj_priv = to_intel_bo(obj);
783 offset = args->offset;
787 /* Operation in this page
789 * page_base = page offset within aperture
790 * page_offset = offset within page
791 * page_length = bytes to copy for this page
793 page_base = (offset & ~(PAGE_SIZE-1));
794 page_offset = offset & (PAGE_SIZE-1);
795 page_length = remain;
796 if ((page_offset + remain) > PAGE_SIZE)
797 page_length = PAGE_SIZE - page_offset;
799 ret = fast_shmem_write(obj_priv->pages,
800 page_base, page_offset,
801 user_data, page_length);
805 remain -= page_length;
806 user_data += page_length;
807 offset += page_length;
811 i915_gem_object_put_pages(obj);
813 mutex_unlock(&dev->struct_mutex);
819 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
820 * the memory and maps it using kmap_atomic for copying.
822 * This avoids taking mmap_sem for faulting on the user's address while the
823 * struct_mutex is held.
826 i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
827 struct drm_i915_gem_pwrite *args,
828 struct drm_file *file_priv)
830 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
831 struct mm_struct *mm = current->mm;
832 struct page **user_pages;
834 loff_t offset, pinned_pages, i;
835 loff_t first_data_page, last_data_page, num_pages;
836 int shmem_page_index, shmem_page_offset;
837 int data_page_index, data_page_offset;
840 uint64_t data_ptr = args->data_ptr;
841 int do_bit17_swizzling;
845 /* Pin the user pages containing the data. We can't fault while
846 * holding the struct mutex, and all of the pwrite implementations
847 * want to hold it while dereferencing the user data.
849 first_data_page = data_ptr / PAGE_SIZE;
850 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
851 num_pages = last_data_page - first_data_page + 1;
853 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
854 if (user_pages == NULL)
857 down_read(&mm->mmap_sem);
858 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
859 num_pages, 0, 0, user_pages, NULL);
860 up_read(&mm->mmap_sem);
861 if (pinned_pages < num_pages) {
863 goto fail_put_user_pages;
866 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
868 mutex_lock(&dev->struct_mutex);
870 ret = i915_gem_object_get_pages_or_evict(obj);
874 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
878 obj_priv = to_intel_bo(obj);
879 offset = args->offset;
883 /* Operation in this page
885 * shmem_page_index = page number within shmem file
886 * shmem_page_offset = offset within page in shmem file
887 * data_page_index = page number in get_user_pages return
888 * data_page_offset = offset with data_page_index page.
889 * page_length = bytes to copy for this page
891 shmem_page_index = offset / PAGE_SIZE;
892 shmem_page_offset = offset & ~PAGE_MASK;
893 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
894 data_page_offset = data_ptr & ~PAGE_MASK;
896 page_length = remain;
897 if ((shmem_page_offset + page_length) > PAGE_SIZE)
898 page_length = PAGE_SIZE - shmem_page_offset;
899 if ((data_page_offset + page_length) > PAGE_SIZE)
900 page_length = PAGE_SIZE - data_page_offset;
902 if (do_bit17_swizzling) {
903 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
905 user_pages[data_page_index],
910 ret = slow_shmem_copy(obj_priv->pages[shmem_page_index],
912 user_pages[data_page_index],
919 remain -= page_length;
920 data_ptr += page_length;
921 offset += page_length;
925 i915_gem_object_put_pages(obj);
927 mutex_unlock(&dev->struct_mutex);
929 for (i = 0; i < pinned_pages; i++)
930 page_cache_release(user_pages[i]);
931 drm_free_large(user_pages);
937 * Writes data to the object referenced by handle.
939 * On error, the contents of the buffer that were to be modified are undefined.
942 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
943 struct drm_file *file_priv)
945 struct drm_i915_gem_pwrite *args = data;
946 struct drm_gem_object *obj;
947 struct drm_i915_gem_object *obj_priv;
950 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
953 obj_priv = to_intel_bo(obj);
955 /* Bounds check destination.
957 * XXX: This could use review for overflow issues...
959 if (args->offset > obj->size || args->size > obj->size ||
960 args->offset + args->size > obj->size) {
961 drm_gem_object_unreference_unlocked(obj);
965 /* We can only do the GTT pwrite on untiled buffers, as otherwise
966 * it would end up going through the fenced access, and we'll get
967 * different detiling behavior between reading and writing.
968 * pread/pwrite currently are reading and writing from the CPU
969 * perspective, requiring manual detiling by the client.
971 if (obj_priv->phys_obj)
972 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
973 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
974 dev->gtt_total != 0) {
975 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
976 if (ret == -EFAULT) {
977 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
980 } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
981 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
983 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
984 if (ret == -EFAULT) {
985 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
992 DRM_INFO("pwrite failed %d\n", ret);
995 drm_gem_object_unreference_unlocked(obj);
1001 * Called when user space prepares to use an object with the CPU, either
1002 * through the mmap ioctl's mapping or a GTT mapping.
1005 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1006 struct drm_file *file_priv)
1008 struct drm_i915_private *dev_priv = dev->dev_private;
1009 struct drm_i915_gem_set_domain *args = data;
1010 struct drm_gem_object *obj;
1011 struct drm_i915_gem_object *obj_priv;
1012 uint32_t read_domains = args->read_domains;
1013 uint32_t write_domain = args->write_domain;
1016 if (!(dev->driver->driver_features & DRIVER_GEM))
1019 /* Only handle setting domains to types used by the CPU. */
1020 if (write_domain & I915_GEM_GPU_DOMAINS)
1023 if (read_domains & I915_GEM_GPU_DOMAINS)
1026 /* Having something in the write domain implies it's in the read
1027 * domain, and only that read domain. Enforce that in the request.
1029 if (write_domain != 0 && read_domains != write_domain)
1032 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1035 obj_priv = to_intel_bo(obj);
1037 mutex_lock(&dev->struct_mutex);
1039 intel_mark_busy(dev, obj);
1042 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1043 obj, obj->size, read_domains, write_domain);
1045 if (read_domains & I915_GEM_DOMAIN_GTT) {
1046 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1048 /* Update the LRU on the fence for the CPU access that's
1051 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1052 struct drm_i915_fence_reg *reg =
1053 &dev_priv->fence_regs[obj_priv->fence_reg];
1054 list_move_tail(®->lru_list,
1055 &dev_priv->mm.fence_list);
1058 /* Silently promote "you're not bound, there was nothing to do"
1059 * to success, since the client was just asking us to
1060 * make sure everything was done.
1065 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1068 drm_gem_object_unreference(obj);
1069 mutex_unlock(&dev->struct_mutex);
1074 * Called when user space has done writes to this buffer
1077 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1078 struct drm_file *file_priv)
1080 struct drm_i915_gem_sw_finish *args = data;
1081 struct drm_gem_object *obj;
1082 struct drm_i915_gem_object *obj_priv;
1085 if (!(dev->driver->driver_features & DRIVER_GEM))
1088 mutex_lock(&dev->struct_mutex);
1089 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1091 mutex_unlock(&dev->struct_mutex);
1096 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1097 __func__, args->handle, obj, obj->size);
1099 obj_priv = to_intel_bo(obj);
1101 /* Pinned buffers may be scanout, so flush the cache */
1102 if (obj_priv->pin_count)
1103 i915_gem_object_flush_cpu_write_domain(obj);
1105 drm_gem_object_unreference(obj);
1106 mutex_unlock(&dev->struct_mutex);
1111 * Maps the contents of an object, returning the address it is mapped
1114 * While the mapping holds a reference on the contents of the object, it doesn't
1115 * imply a ref on the object itself.
1118 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1119 struct drm_file *file_priv)
1121 struct drm_i915_gem_mmap *args = data;
1122 struct drm_gem_object *obj;
1126 if (!(dev->driver->driver_features & DRIVER_GEM))
1129 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1133 offset = args->offset;
1135 down_write(¤t->mm->mmap_sem);
1136 addr = do_mmap(obj->filp, 0, args->size,
1137 PROT_READ | PROT_WRITE, MAP_SHARED,
1139 up_write(¤t->mm->mmap_sem);
1140 drm_gem_object_unreference_unlocked(obj);
1141 if (IS_ERR((void *)addr))
1144 args->addr_ptr = (uint64_t) addr;
1150 * i915_gem_fault - fault a page into the GTT
1151 * vma: VMA in question
1154 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1155 * from userspace. The fault handler takes care of binding the object to
1156 * the GTT (if needed), allocating and programming a fence register (again,
1157 * only if needed based on whether the old reg is still valid or the object
1158 * is tiled) and inserting a new PTE into the faulting process.
1160 * Note that the faulting process may involve evicting existing objects
1161 * from the GTT and/or fence registers to make room. So performance may
1162 * suffer if the GTT working set is large or there are few fence registers
1165 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1167 struct drm_gem_object *obj = vma->vm_private_data;
1168 struct drm_device *dev = obj->dev;
1169 struct drm_i915_private *dev_priv = dev->dev_private;
1170 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1171 pgoff_t page_offset;
1174 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1176 /* We don't use vmf->pgoff since that has the fake offset */
1177 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1180 /* Now bind it into the GTT if needed */
1181 mutex_lock(&dev->struct_mutex);
1182 if (!obj_priv->gtt_space) {
1183 ret = i915_gem_object_bind_to_gtt(obj, 0);
1187 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1189 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1194 /* Need a new fence register? */
1195 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1196 ret = i915_gem_object_get_fence_reg(obj);
1201 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1204 /* Finally, remap it using the new GTT offset */
1205 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1207 mutex_unlock(&dev->struct_mutex);
1212 return VM_FAULT_NOPAGE;
1215 return VM_FAULT_OOM;
1217 return VM_FAULT_SIGBUS;
1222 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1223 * @obj: obj in question
1225 * GEM memory mapping works by handing back to userspace a fake mmap offset
1226 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1227 * up the object based on the offset and sets up the various memory mapping
1230 * This routine allocates and attaches a fake offset for @obj.
1233 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1235 struct drm_device *dev = obj->dev;
1236 struct drm_gem_mm *mm = dev->mm_private;
1237 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1238 struct drm_map_list *list;
1239 struct drm_local_map *map;
1242 /* Set the object up for mmap'ing */
1243 list = &obj->map_list;
1244 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1249 map->type = _DRM_GEM;
1250 map->size = obj->size;
1253 /* Get a DRM GEM mmap offset allocated... */
1254 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1255 obj->size / PAGE_SIZE, 0, 0);
1256 if (!list->file_offset_node) {
1257 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1262 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1263 obj->size / PAGE_SIZE, 0);
1264 if (!list->file_offset_node) {
1269 list->hash.key = list->file_offset_node->start;
1270 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1271 DRM_ERROR("failed to add to map hash\n");
1276 /* By now we should be all set, any drm_mmap request on the offset
1277 * below will get to our mmap & fault handler */
1278 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1283 drm_mm_put_block(list->file_offset_node);
1291 * i915_gem_release_mmap - remove physical page mappings
1292 * @obj: obj in question
1294 * Preserve the reservation of the mmapping with the DRM core code, but
1295 * relinquish ownership of the pages back to the system.
1297 * It is vital that we remove the page mapping if we have mapped a tiled
1298 * object through the GTT and then lose the fence register due to
1299 * resource pressure. Similarly if the object has been moved out of the
1300 * aperture, than pages mapped into userspace must be revoked. Removing the
1301 * mapping will then trigger a page fault on the next user access, allowing
1302 * fixup by i915_gem_fault().
1305 i915_gem_release_mmap(struct drm_gem_object *obj)
1307 struct drm_device *dev = obj->dev;
1308 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1310 if (dev->dev_mapping)
1311 unmap_mapping_range(dev->dev_mapping,
1312 obj_priv->mmap_offset, obj->size, 1);
1316 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1318 struct drm_device *dev = obj->dev;
1319 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1320 struct drm_gem_mm *mm = dev->mm_private;
1321 struct drm_map_list *list;
1323 list = &obj->map_list;
1324 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1326 if (list->file_offset_node) {
1327 drm_mm_put_block(list->file_offset_node);
1328 list->file_offset_node = NULL;
1336 obj_priv->mmap_offset = 0;
1340 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1341 * @obj: object to check
1343 * Return the required GTT alignment for an object, taking into account
1344 * potential fence register mapping if needed.
1347 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1349 struct drm_device *dev = obj->dev;
1350 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1354 * Minimum alignment is 4k (GTT page size), but might be greater
1355 * if a fence register is needed for the object.
1357 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1361 * Previous chips need to be aligned to the size of the smallest
1362 * fence register that can contain the object.
1369 for (i = start; i < obj->size; i <<= 1)
1376 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1378 * @data: GTT mapping ioctl data
1379 * @file_priv: GEM object info
1381 * Simply returns the fake offset to userspace so it can mmap it.
1382 * The mmap call will end up in drm_gem_mmap(), which will set things
1383 * up so we can get faults in the handler above.
1385 * The fault handler will take care of binding the object into the GTT
1386 * (since it may have been evicted to make room for something), allocating
1387 * a fence register, and mapping the appropriate aperture address into
1391 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1392 struct drm_file *file_priv)
1394 struct drm_i915_gem_mmap_gtt *args = data;
1395 struct drm_i915_private *dev_priv = dev->dev_private;
1396 struct drm_gem_object *obj;
1397 struct drm_i915_gem_object *obj_priv;
1400 if (!(dev->driver->driver_features & DRIVER_GEM))
1403 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1407 mutex_lock(&dev->struct_mutex);
1409 obj_priv = to_intel_bo(obj);
1411 if (obj_priv->madv != I915_MADV_WILLNEED) {
1412 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1413 drm_gem_object_unreference(obj);
1414 mutex_unlock(&dev->struct_mutex);
1419 if (!obj_priv->mmap_offset) {
1420 ret = i915_gem_create_mmap_offset(obj);
1422 drm_gem_object_unreference(obj);
1423 mutex_unlock(&dev->struct_mutex);
1428 args->offset = obj_priv->mmap_offset;
1431 * Pull it into the GTT so that we have a page list (makes the
1432 * initial fault faster and any subsequent flushing possible).
1434 if (!obj_priv->agp_mem) {
1435 ret = i915_gem_object_bind_to_gtt(obj, 0);
1437 drm_gem_object_unreference(obj);
1438 mutex_unlock(&dev->struct_mutex);
1441 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1444 drm_gem_object_unreference(obj);
1445 mutex_unlock(&dev->struct_mutex);
1451 i915_gem_object_put_pages(struct drm_gem_object *obj)
1453 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1454 int page_count = obj->size / PAGE_SIZE;
1457 BUG_ON(obj_priv->pages_refcount == 0);
1458 BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
1460 if (--obj_priv->pages_refcount != 0)
1463 if (obj_priv->tiling_mode != I915_TILING_NONE)
1464 i915_gem_object_save_bit_17_swizzle(obj);
1466 if (obj_priv->madv == I915_MADV_DONTNEED)
1467 obj_priv->dirty = 0;
1469 for (i = 0; i < page_count; i++) {
1470 if (obj_priv->dirty)
1471 set_page_dirty(obj_priv->pages[i]);
1473 if (obj_priv->madv == I915_MADV_WILLNEED)
1474 mark_page_accessed(obj_priv->pages[i]);
1476 page_cache_release(obj_priv->pages[i]);
1478 obj_priv->dirty = 0;
1480 drm_free_large(obj_priv->pages);
1481 obj_priv->pages = NULL;
1485 i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno,
1486 struct intel_ring_buffer *ring)
1488 struct drm_device *dev = obj->dev;
1489 drm_i915_private_t *dev_priv = dev->dev_private;
1490 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1491 BUG_ON(ring == NULL);
1492 obj_priv->ring = ring;
1494 /* Add a reference if we're newly entering the active list. */
1495 if (!obj_priv->active) {
1496 drm_gem_object_reference(obj);
1497 obj_priv->active = 1;
1499 /* Move from whatever list we were on to the tail of execution. */
1500 spin_lock(&dev_priv->mm.active_list_lock);
1501 list_move_tail(&obj_priv->list, &ring->active_list);
1502 spin_unlock(&dev_priv->mm.active_list_lock);
1503 obj_priv->last_rendering_seqno = seqno;
1507 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1509 struct drm_device *dev = obj->dev;
1510 drm_i915_private_t *dev_priv = dev->dev_private;
1511 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1513 BUG_ON(!obj_priv->active);
1514 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1515 obj_priv->last_rendering_seqno = 0;
1518 /* Immediately discard the backing storage */
1520 i915_gem_object_truncate(struct drm_gem_object *obj)
1522 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1523 struct inode *inode;
1525 inode = obj->filp->f_path.dentry->d_inode;
1526 if (inode->i_op->truncate)
1527 inode->i_op->truncate (inode);
1529 obj_priv->madv = __I915_MADV_PURGED;
1533 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1535 return obj_priv->madv == I915_MADV_DONTNEED;
1539 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1541 struct drm_device *dev = obj->dev;
1542 drm_i915_private_t *dev_priv = dev->dev_private;
1543 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1545 i915_verify_inactive(dev, __FILE__, __LINE__);
1546 if (obj_priv->pin_count != 0)
1547 list_del_init(&obj_priv->list);
1549 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1551 BUG_ON(!list_empty(&obj_priv->gpu_write_list));
1553 obj_priv->last_rendering_seqno = 0;
1554 obj_priv->ring = NULL;
1555 if (obj_priv->active) {
1556 obj_priv->active = 0;
1557 drm_gem_object_unreference(obj);
1559 i915_verify_inactive(dev, __FILE__, __LINE__);
1563 i915_gem_process_flushing_list(struct drm_device *dev,
1564 uint32_t flush_domains, uint32_t seqno,
1565 struct intel_ring_buffer *ring)
1567 drm_i915_private_t *dev_priv = dev->dev_private;
1568 struct drm_i915_gem_object *obj_priv, *next;
1570 list_for_each_entry_safe(obj_priv, next,
1571 &dev_priv->mm.gpu_write_list,
1573 struct drm_gem_object *obj = &obj_priv->base;
1575 if ((obj->write_domain & flush_domains) ==
1576 obj->write_domain &&
1577 obj_priv->ring->ring_flag == ring->ring_flag) {
1578 uint32_t old_write_domain = obj->write_domain;
1580 obj->write_domain = 0;
1581 list_del_init(&obj_priv->gpu_write_list);
1582 i915_gem_object_move_to_active(obj, seqno, ring);
1584 /* update the fence lru list */
1585 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1586 struct drm_i915_fence_reg *reg =
1587 &dev_priv->fence_regs[obj_priv->fence_reg];
1588 list_move_tail(®->lru_list,
1589 &dev_priv->mm.fence_list);
1592 trace_i915_gem_object_change_domain(obj,
1600 i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1601 uint32_t flush_domains, struct intel_ring_buffer *ring)
1603 drm_i915_private_t *dev_priv = dev->dev_private;
1604 struct drm_i915_file_private *i915_file_priv = NULL;
1605 struct drm_i915_gem_request *request;
1609 if (file_priv != NULL)
1610 i915_file_priv = file_priv->driver_priv;
1612 request = kzalloc(sizeof(*request), GFP_KERNEL);
1613 if (request == NULL)
1616 seqno = ring->add_request(dev, ring, file_priv, flush_domains);
1618 request->seqno = seqno;
1619 request->ring = ring;
1620 request->emitted_jiffies = jiffies;
1621 was_empty = list_empty(&ring->request_list);
1622 list_add_tail(&request->list, &ring->request_list);
1624 if (i915_file_priv) {
1625 list_add_tail(&request->client_list,
1626 &i915_file_priv->mm.request_list);
1628 INIT_LIST_HEAD(&request->client_list);
1631 /* Associate any objects on the flushing list matching the write
1632 * domain we're flushing with our flush.
1634 if (flush_domains != 0)
1635 i915_gem_process_flushing_list(dev, flush_domains, seqno, ring);
1637 if (!dev_priv->mm.suspended) {
1638 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1640 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1646 * Command execution barrier
1648 * Ensures that all commands in the ring are finished
1649 * before signalling the CPU
1652 i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring)
1654 uint32_t flush_domains = 0;
1656 /* The sampler always gets flushed on i965 (sigh) */
1658 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1660 ring->flush(dev, ring,
1661 I915_GEM_DOMAIN_COMMAND, flush_domains);
1662 return flush_domains;
1666 * Moves buffers associated only with the given active seqno from the active
1667 * to inactive list, potentially freeing them.
1670 i915_gem_retire_request(struct drm_device *dev,
1671 struct drm_i915_gem_request *request)
1673 drm_i915_private_t *dev_priv = dev->dev_private;
1675 trace_i915_gem_request_retire(dev, request->seqno);
1677 /* Move any buffers on the active list that are no longer referenced
1678 * by the ringbuffer to the flushing/inactive lists as appropriate.
1680 spin_lock(&dev_priv->mm.active_list_lock);
1681 while (!list_empty(&request->ring->active_list)) {
1682 struct drm_gem_object *obj;
1683 struct drm_i915_gem_object *obj_priv;
1685 obj_priv = list_first_entry(&request->ring->active_list,
1686 struct drm_i915_gem_object,
1688 obj = &obj_priv->base;
1690 /* If the seqno being retired doesn't match the oldest in the
1691 * list, then the oldest in the list must still be newer than
1694 if (obj_priv->last_rendering_seqno != request->seqno)
1698 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1699 __func__, request->seqno, obj);
1702 if (obj->write_domain != 0)
1703 i915_gem_object_move_to_flushing(obj);
1705 /* Take a reference on the object so it won't be
1706 * freed while the spinlock is held. The list
1707 * protection for this spinlock is safe when breaking
1708 * the lock like this since the next thing we do
1709 * is just get the head of the list again.
1711 drm_gem_object_reference(obj);
1712 i915_gem_object_move_to_inactive(obj);
1713 spin_unlock(&dev_priv->mm.active_list_lock);
1714 drm_gem_object_unreference(obj);
1715 spin_lock(&dev_priv->mm.active_list_lock);
1719 spin_unlock(&dev_priv->mm.active_list_lock);
1723 * Returns true if seq1 is later than seq2.
1726 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1728 return (int32_t)(seq1 - seq2) >= 0;
1732 i915_get_gem_seqno(struct drm_device *dev,
1733 struct intel_ring_buffer *ring)
1735 return ring->get_gem_seqno(dev, ring);
1739 * This function clears the request list as sequence numbers are passed.
1742 i915_gem_retire_requests(struct drm_device *dev,
1743 struct intel_ring_buffer *ring)
1745 drm_i915_private_t *dev_priv = dev->dev_private;
1748 if (!ring->status_page.page_addr
1749 || list_empty(&ring->request_list))
1752 seqno = i915_get_gem_seqno(dev, ring);
1754 while (!list_empty(&ring->request_list)) {
1755 struct drm_i915_gem_request *request;
1756 uint32_t retiring_seqno;
1758 request = list_first_entry(&ring->request_list,
1759 struct drm_i915_gem_request,
1761 retiring_seqno = request->seqno;
1763 if (i915_seqno_passed(seqno, retiring_seqno) ||
1764 atomic_read(&dev_priv->mm.wedged)) {
1765 i915_gem_retire_request(dev, request);
1767 list_del(&request->list);
1768 list_del(&request->client_list);
1774 if (unlikely (dev_priv->trace_irq_seqno &&
1775 i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
1777 ring->user_irq_put(dev, ring);
1778 dev_priv->trace_irq_seqno = 0;
1783 i915_gem_retire_work_handler(struct work_struct *work)
1785 drm_i915_private_t *dev_priv;
1786 struct drm_device *dev;
1788 dev_priv = container_of(work, drm_i915_private_t,
1789 mm.retire_work.work);
1790 dev = dev_priv->dev;
1792 mutex_lock(&dev->struct_mutex);
1793 i915_gem_retire_requests(dev, &dev_priv->render_ring);
1796 i915_gem_retire_requests(dev, &dev_priv->bsd_ring);
1798 if (!dev_priv->mm.suspended &&
1799 (!list_empty(&dev_priv->render_ring.request_list) ||
1801 !list_empty(&dev_priv->bsd_ring.request_list))))
1802 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1803 mutex_unlock(&dev->struct_mutex);
1807 i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
1808 int interruptible, struct intel_ring_buffer *ring)
1810 drm_i915_private_t *dev_priv = dev->dev_private;
1816 if (atomic_read(&dev_priv->mm.wedged))
1819 if (!i915_seqno_passed(ring->get_gem_seqno(dev, ring), seqno)) {
1820 if (HAS_PCH_SPLIT(dev))
1821 ier = I915_READ(DEIER) | I915_READ(GTIER);
1823 ier = I915_READ(IER);
1825 DRM_ERROR("something (likely vbetool) disabled "
1826 "interrupts, re-enabling\n");
1827 i915_driver_irq_preinstall(dev);
1828 i915_driver_irq_postinstall(dev);
1831 trace_i915_gem_request_wait_begin(dev, seqno);
1833 ring->waiting_gem_seqno = seqno;
1834 ring->user_irq_get(dev, ring);
1836 ret = wait_event_interruptible(ring->irq_queue,
1838 ring->get_gem_seqno(dev, ring), seqno)
1839 || atomic_read(&dev_priv->mm.wedged));
1841 wait_event(ring->irq_queue,
1843 ring->get_gem_seqno(dev, ring), seqno)
1844 || atomic_read(&dev_priv->mm.wedged));
1846 ring->user_irq_put(dev, ring);
1847 ring->waiting_gem_seqno = 0;
1849 trace_i915_gem_request_wait_end(dev, seqno);
1851 if (atomic_read(&dev_priv->mm.wedged))
1854 if (ret && ret != -ERESTARTSYS)
1855 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1856 __func__, ret, seqno, ring->get_gem_seqno(dev, ring));
1858 /* Directly dispatch request retiring. While we have the work queue
1859 * to handle this, the waiter on a request often wants an associated
1860 * buffer to have made it to the inactive list, and we would need
1861 * a separate wait queue to handle that.
1864 i915_gem_retire_requests(dev, ring);
1870 * Waits for a sequence number to be signaled, and cleans up the
1871 * request and object lists appropriately for that event.
1874 i915_wait_request(struct drm_device *dev, uint32_t seqno,
1875 struct intel_ring_buffer *ring)
1877 return i915_do_wait_request(dev, seqno, 1, ring);
1881 i915_gem_flush(struct drm_device *dev,
1882 uint32_t invalidate_domains,
1883 uint32_t flush_domains)
1885 drm_i915_private_t *dev_priv = dev->dev_private;
1886 if (flush_domains & I915_GEM_DOMAIN_CPU)
1887 drm_agp_chipset_flush(dev);
1888 dev_priv->render_ring.flush(dev, &dev_priv->render_ring,
1893 dev_priv->bsd_ring.flush(dev, &dev_priv->bsd_ring,
1899 i915_gem_flush_ring(struct drm_device *dev,
1900 uint32_t invalidate_domains,
1901 uint32_t flush_domains,
1902 struct intel_ring_buffer *ring)
1904 if (flush_domains & I915_GEM_DOMAIN_CPU)
1905 drm_agp_chipset_flush(dev);
1906 ring->flush(dev, ring,
1912 * Ensures that all rendering to the object has completed and the object is
1913 * safe to unbind from the GTT or access from the CPU.
1916 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1918 struct drm_device *dev = obj->dev;
1919 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1922 /* This function only exists to support waiting for existing rendering,
1923 * not for emitting required flushes.
1925 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
1927 /* If there is rendering queued on the buffer being evicted, wait for
1930 if (obj_priv->active) {
1932 DRM_INFO("%s: object %p wait for seqno %08x\n",
1933 __func__, obj, obj_priv->last_rendering_seqno);
1935 ret = i915_wait_request(dev,
1936 obj_priv->last_rendering_seqno, obj_priv->ring);
1945 * Unbinds an object from the GTT aperture.
1948 i915_gem_object_unbind(struct drm_gem_object *obj)
1950 struct drm_device *dev = obj->dev;
1951 drm_i915_private_t *dev_priv = dev->dev_private;
1952 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1956 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1957 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1959 if (obj_priv->gtt_space == NULL)
1962 if (obj_priv->pin_count != 0) {
1963 DRM_ERROR("Attempting to unbind pinned buffer\n");
1967 /* blow away mappings if mapped through GTT */
1968 i915_gem_release_mmap(obj);
1970 /* Move the object to the CPU domain to ensure that
1971 * any possible CPU writes while it's not in the GTT
1972 * are flushed when we go to remap it. This will
1973 * also ensure that all pending GPU writes are finished
1976 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1978 if (ret != -ERESTARTSYS)
1979 DRM_ERROR("set_domain failed: %d\n", ret);
1983 BUG_ON(obj_priv->active);
1985 /* release the fence reg _after_ flushing */
1986 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
1987 i915_gem_clear_fence_reg(obj);
1989 if (obj_priv->agp_mem != NULL) {
1990 drm_unbind_agp(obj_priv->agp_mem);
1991 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
1992 obj_priv->agp_mem = NULL;
1995 i915_gem_object_put_pages(obj);
1996 BUG_ON(obj_priv->pages_refcount);
1998 if (obj_priv->gtt_space) {
1999 atomic_dec(&dev->gtt_count);
2000 atomic_sub(obj->size, &dev->gtt_memory);
2002 drm_mm_put_block(obj_priv->gtt_space);
2003 obj_priv->gtt_space = NULL;
2006 /* Remove ourselves from the LRU list if present. */
2007 spin_lock(&dev_priv->mm.active_list_lock);
2008 if (!list_empty(&obj_priv->list))
2009 list_del_init(&obj_priv->list);
2010 spin_unlock(&dev_priv->mm.active_list_lock);
2012 if (i915_gem_object_is_purgeable(obj_priv))
2013 i915_gem_object_truncate(obj);
2015 trace_i915_gem_object_unbind(obj);
2020 static struct drm_gem_object *
2021 i915_gem_find_inactive_object(struct drm_device *dev, int min_size)
2023 drm_i915_private_t *dev_priv = dev->dev_private;
2024 struct drm_i915_gem_object *obj_priv;
2025 struct drm_gem_object *best = NULL;
2026 struct drm_gem_object *first = NULL;
2028 /* Try to find the smallest clean object */
2029 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
2030 struct drm_gem_object *obj = &obj_priv->base;
2031 if (obj->size >= min_size) {
2032 if ((!obj_priv->dirty ||
2033 i915_gem_object_is_purgeable(obj_priv)) &&
2034 (!best || obj->size < best->size)) {
2036 if (best->size == min_size)
2044 return best ? best : first;
2048 i915_gpu_idle(struct drm_device *dev)
2050 drm_i915_private_t *dev_priv = dev->dev_private;
2052 uint32_t seqno1, seqno2;
2055 spin_lock(&dev_priv->mm.active_list_lock);
2056 lists_empty = (list_empty(&dev_priv->mm.flushing_list) &&
2057 list_empty(&dev_priv->render_ring.active_list) &&
2059 list_empty(&dev_priv->bsd_ring.active_list)));
2060 spin_unlock(&dev_priv->mm.active_list_lock);
2065 /* Flush everything onto the inactive list. */
2066 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2067 seqno1 = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS,
2068 &dev_priv->render_ring);
2071 ret = i915_wait_request(dev, seqno1, &dev_priv->render_ring);
2074 seqno2 = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS,
2075 &dev_priv->bsd_ring);
2079 ret = i915_wait_request(dev, seqno2, &dev_priv->bsd_ring);
2089 i915_gem_evict_everything(struct drm_device *dev)
2091 drm_i915_private_t *dev_priv = dev->dev_private;
2095 spin_lock(&dev_priv->mm.active_list_lock);
2096 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2097 list_empty(&dev_priv->mm.flushing_list) &&
2098 list_empty(&dev_priv->render_ring.active_list) &&
2100 || list_empty(&dev_priv->bsd_ring.active_list)));
2101 spin_unlock(&dev_priv->mm.active_list_lock);
2106 /* Flush everything (on to the inactive lists) and evict */
2107 ret = i915_gpu_idle(dev);
2111 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2113 ret = i915_gem_evict_from_inactive_list(dev);
2117 spin_lock(&dev_priv->mm.active_list_lock);
2118 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2119 list_empty(&dev_priv->mm.flushing_list) &&
2120 list_empty(&dev_priv->render_ring.active_list) &&
2122 || list_empty(&dev_priv->bsd_ring.active_list)));
2123 spin_unlock(&dev_priv->mm.active_list_lock);
2124 BUG_ON(!lists_empty);
2130 i915_gem_evict_something(struct drm_device *dev, int min_size)
2132 drm_i915_private_t *dev_priv = dev->dev_private;
2133 struct drm_gem_object *obj;
2136 struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
2137 struct intel_ring_buffer *bsd_ring = &dev_priv->bsd_ring;
2139 i915_gem_retire_requests(dev, render_ring);
2142 i915_gem_retire_requests(dev, bsd_ring);
2144 /* If there's an inactive buffer available now, grab it
2147 obj = i915_gem_find_inactive_object(dev, min_size);
2149 struct drm_i915_gem_object *obj_priv;
2152 DRM_INFO("%s: evicting %p\n", __func__, obj);
2154 obj_priv = to_intel_bo(obj);
2155 BUG_ON(obj_priv->pin_count != 0);
2156 BUG_ON(obj_priv->active);
2158 /* Wait on the rendering and unbind the buffer. */
2159 return i915_gem_object_unbind(obj);
2162 /* If we didn't get anything, but the ring is still processing
2163 * things, wait for the next to finish and hopefully leave us
2164 * a buffer to evict.
2166 if (!list_empty(&render_ring->request_list)) {
2167 struct drm_i915_gem_request *request;
2169 request = list_first_entry(&render_ring->request_list,
2170 struct drm_i915_gem_request,
2173 ret = i915_wait_request(dev,
2174 request->seqno, request->ring);
2181 if (HAS_BSD(dev) && !list_empty(&bsd_ring->request_list)) {
2182 struct drm_i915_gem_request *request;
2184 request = list_first_entry(&bsd_ring->request_list,
2185 struct drm_i915_gem_request,
2188 ret = i915_wait_request(dev,
2189 request->seqno, request->ring);
2196 /* If we didn't have anything on the request list but there
2197 * are buffers awaiting a flush, emit one and try again.
2198 * When we wait on it, those buffers waiting for that flush
2199 * will get moved to inactive.
2201 if (!list_empty(&dev_priv->mm.flushing_list)) {
2202 struct drm_i915_gem_object *obj_priv;
2204 /* Find an object that we can immediately reuse */
2205 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
2206 obj = &obj_priv->base;
2207 if (obj->size >= min_size)
2216 i915_gem_flush_ring(dev,
2220 seqno = i915_add_request(dev, NULL,
2229 /* If we didn't do any of the above, there's no single buffer
2230 * large enough to swap out for the new one, so just evict
2231 * everything and start again. (This should be rare.)
2233 if (!list_empty (&dev_priv->mm.inactive_list))
2234 return i915_gem_evict_from_inactive_list(dev);
2236 return i915_gem_evict_everything(dev);
2241 i915_gem_object_get_pages(struct drm_gem_object *obj,
2244 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2246 struct address_space *mapping;
2247 struct inode *inode;
2250 BUG_ON(obj_priv->pages_refcount
2251 == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT);
2253 if (obj_priv->pages_refcount++ != 0)
2256 /* Get the list of pages out of our struct file. They'll be pinned
2257 * at this point until we release them.
2259 page_count = obj->size / PAGE_SIZE;
2260 BUG_ON(obj_priv->pages != NULL);
2261 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
2262 if (obj_priv->pages == NULL) {
2263 obj_priv->pages_refcount--;
2267 inode = obj->filp->f_path.dentry->d_inode;
2268 mapping = inode->i_mapping;
2269 for (i = 0; i < page_count; i++) {
2270 page = read_cache_page_gfp(mapping, i,
2271 mapping_gfp_mask (mapping) |
2277 obj_priv->pages[i] = page;
2280 if (obj_priv->tiling_mode != I915_TILING_NONE)
2281 i915_gem_object_do_bit_17_swizzle(obj);
2287 page_cache_release(obj_priv->pages[i]);
2289 drm_free_large(obj_priv->pages);
2290 obj_priv->pages = NULL;
2291 obj_priv->pages_refcount--;
2292 return PTR_ERR(page);
2295 static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg)
2297 struct drm_gem_object *obj = reg->obj;
2298 struct drm_device *dev = obj->dev;
2299 drm_i915_private_t *dev_priv = dev->dev_private;
2300 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2301 int regnum = obj_priv->fence_reg;
2304 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2306 val |= obj_priv->gtt_offset & 0xfffff000;
2307 val |= (uint64_t)((obj_priv->stride / 128) - 1) <<
2308 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2310 if (obj_priv->tiling_mode == I915_TILING_Y)
2311 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2312 val |= I965_FENCE_REG_VALID;
2314 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val);
2317 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2319 struct drm_gem_object *obj = reg->obj;
2320 struct drm_device *dev = obj->dev;
2321 drm_i915_private_t *dev_priv = dev->dev_private;
2322 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2323 int regnum = obj_priv->fence_reg;
2326 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2328 val |= obj_priv->gtt_offset & 0xfffff000;
2329 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2330 if (obj_priv->tiling_mode == I915_TILING_Y)
2331 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2332 val |= I965_FENCE_REG_VALID;
2334 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2337 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2339 struct drm_gem_object *obj = reg->obj;
2340 struct drm_device *dev = obj->dev;
2341 drm_i915_private_t *dev_priv = dev->dev_private;
2342 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2343 int regnum = obj_priv->fence_reg;
2345 uint32_t fence_reg, val;
2348 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2349 (obj_priv->gtt_offset & (obj->size - 1))) {
2350 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2351 __func__, obj_priv->gtt_offset, obj->size);
2355 if (obj_priv->tiling_mode == I915_TILING_Y &&
2356 HAS_128_BYTE_Y_TILING(dev))
2361 /* Note: pitch better be a power of two tile widths */
2362 pitch_val = obj_priv->stride / tile_width;
2363 pitch_val = ffs(pitch_val) - 1;
2365 if (obj_priv->tiling_mode == I915_TILING_Y &&
2366 HAS_128_BYTE_Y_TILING(dev))
2367 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2369 WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL);
2371 val = obj_priv->gtt_offset;
2372 if (obj_priv->tiling_mode == I915_TILING_Y)
2373 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2374 val |= I915_FENCE_SIZE_BITS(obj->size);
2375 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2376 val |= I830_FENCE_REG_VALID;
2379 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2381 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2382 I915_WRITE(fence_reg, val);
2385 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2387 struct drm_gem_object *obj = reg->obj;
2388 struct drm_device *dev = obj->dev;
2389 drm_i915_private_t *dev_priv = dev->dev_private;
2390 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2391 int regnum = obj_priv->fence_reg;
2394 uint32_t fence_size_bits;
2396 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
2397 (obj_priv->gtt_offset & (obj->size - 1))) {
2398 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2399 __func__, obj_priv->gtt_offset);
2403 pitch_val = obj_priv->stride / 128;
2404 pitch_val = ffs(pitch_val) - 1;
2405 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2407 val = obj_priv->gtt_offset;
2408 if (obj_priv->tiling_mode == I915_TILING_Y)
2409 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2410 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2411 WARN_ON(fence_size_bits & ~0x00000f00);
2412 val |= fence_size_bits;
2413 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2414 val |= I830_FENCE_REG_VALID;
2416 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
2419 static int i915_find_fence_reg(struct drm_device *dev)
2421 struct drm_i915_fence_reg *reg = NULL;
2422 struct drm_i915_gem_object *obj_priv = NULL;
2423 struct drm_i915_private *dev_priv = dev->dev_private;
2424 struct drm_gem_object *obj = NULL;
2427 /* First try to find a free reg */
2429 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2430 reg = &dev_priv->fence_regs[i];
2434 obj_priv = to_intel_bo(reg->obj);
2435 if (!obj_priv->pin_count)
2442 /* None available, try to steal one or wait for a user to finish */
2443 i = I915_FENCE_REG_NONE;
2444 list_for_each_entry(reg, &dev_priv->mm.fence_list,
2447 obj_priv = to_intel_bo(obj);
2449 if (obj_priv->pin_count)
2453 i = obj_priv->fence_reg;
2457 BUG_ON(i == I915_FENCE_REG_NONE);
2459 /* We only have a reference on obj from the active list. put_fence_reg
2460 * might drop that one, causing a use-after-free in it. So hold a
2461 * private reference to obj like the other callers of put_fence_reg
2462 * (set_tiling ioctl) do. */
2463 drm_gem_object_reference(obj);
2464 ret = i915_gem_object_put_fence_reg(obj);
2465 drm_gem_object_unreference(obj);
2473 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2474 * @obj: object to map through a fence reg
2476 * When mapping objects through the GTT, userspace wants to be able to write
2477 * to them without having to worry about swizzling if the object is tiled.
2479 * This function walks the fence regs looking for a free one for @obj,
2480 * stealing one if it can't find any.
2482 * It then sets up the reg based on the object's properties: address, pitch
2483 * and tiling format.
2486 i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
2488 struct drm_device *dev = obj->dev;
2489 struct drm_i915_private *dev_priv = dev->dev_private;
2490 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2491 struct drm_i915_fence_reg *reg = NULL;
2494 /* Just update our place in the LRU if our fence is getting used. */
2495 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2496 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2497 list_move_tail(®->lru_list, &dev_priv->mm.fence_list);
2501 switch (obj_priv->tiling_mode) {
2502 case I915_TILING_NONE:
2503 WARN(1, "allocating a fence for non-tiled object?\n");
2506 if (!obj_priv->stride)
2508 WARN((obj_priv->stride & (512 - 1)),
2509 "object 0x%08x is X tiled but has non-512B pitch\n",
2510 obj_priv->gtt_offset);
2513 if (!obj_priv->stride)
2515 WARN((obj_priv->stride & (128 - 1)),
2516 "object 0x%08x is Y tiled but has non-128B pitch\n",
2517 obj_priv->gtt_offset);
2521 ret = i915_find_fence_reg(dev);
2525 obj_priv->fence_reg = ret;
2526 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2527 list_add_tail(®->lru_list, &dev_priv->mm.fence_list);
2532 sandybridge_write_fence_reg(reg);
2533 else if (IS_I965G(dev))
2534 i965_write_fence_reg(reg);
2535 else if (IS_I9XX(dev))
2536 i915_write_fence_reg(reg);
2538 i830_write_fence_reg(reg);
2540 trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg,
2541 obj_priv->tiling_mode);
2547 * i915_gem_clear_fence_reg - clear out fence register info
2548 * @obj: object to clear
2550 * Zeroes out the fence register itself and clears out the associated
2551 * data structures in dev_priv and obj_priv.
2554 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2556 struct drm_device *dev = obj->dev;
2557 drm_i915_private_t *dev_priv = dev->dev_private;
2558 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2559 struct drm_i915_fence_reg *reg =
2560 &dev_priv->fence_regs[obj_priv->fence_reg];
2563 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 +
2564 (obj_priv->fence_reg * 8), 0);
2565 } else if (IS_I965G(dev)) {
2566 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
2570 if (obj_priv->fence_reg < 8)
2571 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2573 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2576 I915_WRITE(fence_reg, 0);
2580 obj_priv->fence_reg = I915_FENCE_REG_NONE;
2581 list_del_init(®->lru_list);
2585 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2586 * to the buffer to finish, and then resets the fence register.
2587 * @obj: tiled object holding a fence register.
2589 * Zeroes out the fence register itself and clears out the associated
2590 * data structures in dev_priv and obj_priv.
2593 i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2595 struct drm_device *dev = obj->dev;
2596 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2598 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2601 /* If we've changed tiling, GTT-mappings of the object
2602 * need to re-fault to ensure that the correct fence register
2603 * setup is in place.
2605 i915_gem_release_mmap(obj);
2607 /* On the i915, GPU access to tiled buffers is via a fence,
2608 * therefore we must wait for any outstanding access to complete
2609 * before clearing the fence.
2611 if (!IS_I965G(dev)) {
2614 i915_gem_object_flush_gpu_write_domain(obj);
2615 ret = i915_gem_object_wait_rendering(obj);
2620 i915_gem_object_flush_gtt_write_domain(obj);
2621 i915_gem_clear_fence_reg (obj);
2627 * Finds free space in the GTT aperture and binds the object there.
2630 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2632 struct drm_device *dev = obj->dev;
2633 drm_i915_private_t *dev_priv = dev->dev_private;
2634 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2635 struct drm_mm_node *free_space;
2636 gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
2639 if (obj_priv->madv != I915_MADV_WILLNEED) {
2640 DRM_ERROR("Attempting to bind a purgeable object\n");
2645 alignment = i915_gem_get_gtt_alignment(obj);
2646 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
2647 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2652 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2653 obj->size, alignment, 0);
2654 if (free_space != NULL) {
2655 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2657 if (obj_priv->gtt_space != NULL) {
2658 obj_priv->gtt_space->private = obj;
2659 obj_priv->gtt_offset = obj_priv->gtt_space->start;
2662 if (obj_priv->gtt_space == NULL) {
2663 /* If the gtt is empty and we're still having trouble
2664 * fitting our object in, we're out of memory.
2667 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2669 ret = i915_gem_evict_something(dev, obj->size);
2677 DRM_INFO("Binding object of size %zd at 0x%08x\n",
2678 obj->size, obj_priv->gtt_offset);
2680 ret = i915_gem_object_get_pages(obj, gfpmask);
2682 drm_mm_put_block(obj_priv->gtt_space);
2683 obj_priv->gtt_space = NULL;
2685 if (ret == -ENOMEM) {
2686 /* first try to clear up some space from the GTT */
2687 ret = i915_gem_evict_something(dev, obj->size);
2689 /* now try to shrink everyone else */
2704 /* Create an AGP memory structure pointing at our pages, and bind it
2707 obj_priv->agp_mem = drm_agp_bind_pages(dev,
2709 obj->size >> PAGE_SHIFT,
2710 obj_priv->gtt_offset,
2711 obj_priv->agp_type);
2712 if (obj_priv->agp_mem == NULL) {
2713 i915_gem_object_put_pages(obj);
2714 drm_mm_put_block(obj_priv->gtt_space);
2715 obj_priv->gtt_space = NULL;
2717 ret = i915_gem_evict_something(dev, obj->size);
2723 atomic_inc(&dev->gtt_count);
2724 atomic_add(obj->size, &dev->gtt_memory);
2726 /* Assert that the object is not currently in any GPU domain. As it
2727 * wasn't in the GTT, there shouldn't be any way it could have been in
2730 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2731 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
2733 trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2739 i915_gem_clflush_object(struct drm_gem_object *obj)
2741 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2743 /* If we don't have a page list set up, then we're not pinned
2744 * to GPU, and we can ignore the cache flush because it'll happen
2745 * again at bind time.
2747 if (obj_priv->pages == NULL)
2750 trace_i915_gem_object_clflush(obj);
2752 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2755 /** Flushes any GPU write domain for the object if it's dirty. */
2757 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2759 struct drm_device *dev = obj->dev;
2760 uint32_t old_write_domain;
2761 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2763 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2766 /* Queue the GPU write cache flushing we need. */
2767 old_write_domain = obj->write_domain;
2768 i915_gem_flush(dev, 0, obj->write_domain);
2769 (void) i915_add_request(dev, NULL, obj->write_domain, obj_priv->ring);
2770 BUG_ON(obj->write_domain);
2772 trace_i915_gem_object_change_domain(obj,
2777 /** Flushes the GTT write domain for the object if it's dirty. */
2779 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2781 uint32_t old_write_domain;
2783 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2786 /* No actual flushing is required for the GTT write domain. Writes
2787 * to it immediately go to main memory as far as we know, so there's
2788 * no chipset flush. It also doesn't land in render cache.
2790 old_write_domain = obj->write_domain;
2791 obj->write_domain = 0;
2793 trace_i915_gem_object_change_domain(obj,
2798 /** Flushes the CPU write domain for the object if it's dirty. */
2800 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2802 struct drm_device *dev = obj->dev;
2803 uint32_t old_write_domain;
2805 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2808 i915_gem_clflush_object(obj);
2809 drm_agp_chipset_flush(dev);
2810 old_write_domain = obj->write_domain;
2811 obj->write_domain = 0;
2813 trace_i915_gem_object_change_domain(obj,
2819 i915_gem_object_flush_write_domain(struct drm_gem_object *obj)
2821 switch (obj->write_domain) {
2822 case I915_GEM_DOMAIN_GTT:
2823 i915_gem_object_flush_gtt_write_domain(obj);
2825 case I915_GEM_DOMAIN_CPU:
2826 i915_gem_object_flush_cpu_write_domain(obj);
2829 i915_gem_object_flush_gpu_write_domain(obj);
2835 * Moves a single object to the GTT read, and possibly write domain.
2837 * This function returns when the move is complete, including waiting on
2841 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2843 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2844 uint32_t old_write_domain, old_read_domains;
2847 /* Not valid to be called on unbound objects. */
2848 if (obj_priv->gtt_space == NULL)
2851 i915_gem_object_flush_gpu_write_domain(obj);
2852 /* Wait on any GPU rendering and flushing to occur. */
2853 ret = i915_gem_object_wait_rendering(obj);
2857 old_write_domain = obj->write_domain;
2858 old_read_domains = obj->read_domains;
2860 /* If we're writing through the GTT domain, then CPU and GPU caches
2861 * will need to be invalidated at next use.
2864 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2866 i915_gem_object_flush_cpu_write_domain(obj);
2868 /* It should now be out of any other write domains, and we can update
2869 * the domain values for our changes.
2871 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2872 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2874 obj->write_domain = I915_GEM_DOMAIN_GTT;
2875 obj_priv->dirty = 1;
2878 trace_i915_gem_object_change_domain(obj,
2886 * Prepare buffer for display plane. Use uninterruptible for possible flush
2887 * wait, as in modesetting process we're not supposed to be interrupted.
2890 i915_gem_object_set_to_display_plane(struct drm_gem_object *obj)
2892 struct drm_device *dev = obj->dev;
2893 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2894 uint32_t old_write_domain, old_read_domains;
2897 /* Not valid to be called on unbound objects. */
2898 if (obj_priv->gtt_space == NULL)
2901 i915_gem_object_flush_gpu_write_domain(obj);
2903 /* Wait on any GPU rendering and flushing to occur. */
2904 if (obj_priv->active) {
2906 DRM_INFO("%s: object %p wait for seqno %08x\n",
2907 __func__, obj, obj_priv->last_rendering_seqno);
2909 ret = i915_do_wait_request(dev,
2910 obj_priv->last_rendering_seqno,
2917 i915_gem_object_flush_cpu_write_domain(obj);
2919 old_write_domain = obj->write_domain;
2920 old_read_domains = obj->read_domains;
2922 /* It should now be out of any other write domains, and we can update
2923 * the domain values for our changes.
2925 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2926 obj->read_domains = I915_GEM_DOMAIN_GTT;
2927 obj->write_domain = I915_GEM_DOMAIN_GTT;
2928 obj_priv->dirty = 1;
2930 trace_i915_gem_object_change_domain(obj,
2938 * Moves a single object to the CPU read, and possibly write domain.
2940 * This function returns when the move is complete, including waiting on
2944 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2946 uint32_t old_write_domain, old_read_domains;
2949 i915_gem_object_flush_gpu_write_domain(obj);
2950 /* Wait on any GPU rendering and flushing to occur. */
2951 ret = i915_gem_object_wait_rendering(obj);
2955 i915_gem_object_flush_gtt_write_domain(obj);
2957 /* If we have a partially-valid cache of the object in the CPU,
2958 * finish invalidating it and free the per-page flags.
2960 i915_gem_object_set_to_full_cpu_read_domain(obj);
2962 old_write_domain = obj->write_domain;
2963 old_read_domains = obj->read_domains;
2965 /* Flush the CPU cache if it's still invalid. */
2966 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2967 i915_gem_clflush_object(obj);
2969 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2972 /* It should now be out of any other write domains, and we can update
2973 * the domain values for our changes.
2975 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2977 /* If we're writing through the CPU, then the GPU read domains will
2978 * need to be invalidated at next use.
2981 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2982 obj->write_domain = I915_GEM_DOMAIN_CPU;
2985 trace_i915_gem_object_change_domain(obj,
2993 * Set the next domain for the specified object. This
2994 * may not actually perform the necessary flushing/invaliding though,
2995 * as that may want to be batched with other set_domain operations
2997 * This is (we hope) the only really tricky part of gem. The goal
2998 * is fairly simple -- track which caches hold bits of the object
2999 * and make sure they remain coherent. A few concrete examples may
3000 * help to explain how it works. For shorthand, we use the notation
3001 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
3002 * a pair of read and write domain masks.
3004 * Case 1: the batch buffer
3010 * 5. Unmapped from GTT
3013 * Let's take these a step at a time
3016 * Pages allocated from the kernel may still have
3017 * cache contents, so we set them to (CPU, CPU) always.
3018 * 2. Written by CPU (using pwrite)
3019 * The pwrite function calls set_domain (CPU, CPU) and
3020 * this function does nothing (as nothing changes)
3022 * This function asserts that the object is not
3023 * currently in any GPU-based read or write domains
3025 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
3026 * As write_domain is zero, this function adds in the
3027 * current read domains (CPU+COMMAND, 0).
3028 * flush_domains is set to CPU.
3029 * invalidate_domains is set to COMMAND
3030 * clflush is run to get data out of the CPU caches
3031 * then i915_dev_set_domain calls i915_gem_flush to
3032 * emit an MI_FLUSH and drm_agp_chipset_flush
3033 * 5. Unmapped from GTT
3034 * i915_gem_object_unbind calls set_domain (CPU, CPU)
3035 * flush_domains and invalidate_domains end up both zero
3036 * so no flushing/invalidating happens
3040 * Case 2: The shared render buffer
3044 * 3. Read/written by GPU
3045 * 4. set_domain to (CPU,CPU)
3046 * 5. Read/written by CPU
3047 * 6. Read/written by GPU
3050 * Same as last example, (CPU, CPU)
3052 * Nothing changes (assertions find that it is not in the GPU)
3053 * 3. Read/written by GPU
3054 * execbuffer calls set_domain (RENDER, RENDER)
3055 * flush_domains gets CPU
3056 * invalidate_domains gets GPU
3058 * MI_FLUSH and drm_agp_chipset_flush
3059 * 4. set_domain (CPU, CPU)
3060 * flush_domains gets GPU
3061 * invalidate_domains gets CPU
3062 * wait_rendering (obj) to make sure all drawing is complete.
3063 * This will include an MI_FLUSH to get the data from GPU
3065 * clflush (obj) to invalidate the CPU cache
3066 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3067 * 5. Read/written by CPU
3068 * cache lines are loaded and dirtied
3069 * 6. Read written by GPU
3070 * Same as last GPU access
3072 * Case 3: The constant buffer
3077 * 4. Updated (written) by CPU again
3086 * flush_domains = CPU
3087 * invalidate_domains = RENDER
3090 * drm_agp_chipset_flush
3091 * 4. Updated (written) by CPU again
3093 * flush_domains = 0 (no previous write domain)
3094 * invalidate_domains = 0 (no new read domains)
3097 * flush_domains = CPU
3098 * invalidate_domains = RENDER
3101 * drm_agp_chipset_flush
3104 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
3106 struct drm_device *dev = obj->dev;
3107 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3108 uint32_t invalidate_domains = 0;
3109 uint32_t flush_domains = 0;
3110 uint32_t old_read_domains;
3112 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
3113 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
3115 intel_mark_busy(dev, obj);
3118 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
3120 obj->read_domains, obj->pending_read_domains,
3121 obj->write_domain, obj->pending_write_domain);
3124 * If the object isn't moving to a new write domain,
3125 * let the object stay in multiple read domains
3127 if (obj->pending_write_domain == 0)
3128 obj->pending_read_domains |= obj->read_domains;
3130 obj_priv->dirty = 1;
3133 * Flush the current write domain if
3134 * the new read domains don't match. Invalidate
3135 * any read domains which differ from the old
3138 if (obj->write_domain &&
3139 obj->write_domain != obj->pending_read_domains) {
3140 flush_domains |= obj->write_domain;
3141 invalidate_domains |=
3142 obj->pending_read_domains & ~obj->write_domain;
3145 * Invalidate any read caches which may have
3146 * stale data. That is, any new read domains.
3148 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
3149 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
3151 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3152 __func__, flush_domains, invalidate_domains);
3154 i915_gem_clflush_object(obj);
3157 old_read_domains = obj->read_domains;
3159 /* The actual obj->write_domain will be updated with
3160 * pending_write_domain after we emit the accumulated flush for all
3161 * of our domain changes in execbuffers (which clears objects'
3162 * write_domains). So if we have a current write domain that we
3163 * aren't changing, set pending_write_domain to that.
3165 if (flush_domains == 0 && obj->pending_write_domain == 0)
3166 obj->pending_write_domain = obj->write_domain;
3167 obj->read_domains = obj->pending_read_domains;
3169 dev->invalidate_domains |= invalidate_domains;
3170 dev->flush_domains |= flush_domains;
3172 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3174 obj->read_domains, obj->write_domain,
3175 dev->invalidate_domains, dev->flush_domains);
3178 trace_i915_gem_object_change_domain(obj,
3184 * Moves the object from a partially CPU read to a full one.
3186 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3187 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3190 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
3192 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3194 if (!obj_priv->page_cpu_valid)
3197 /* If we're partially in the CPU read domain, finish moving it in.
3199 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3202 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3203 if (obj_priv->page_cpu_valid[i])
3205 drm_clflush_pages(obj_priv->pages + i, 1);
3209 /* Free the page_cpu_valid mappings which are now stale, whether
3210 * or not we've got I915_GEM_DOMAIN_CPU.
3212 kfree(obj_priv->page_cpu_valid);
3213 obj_priv->page_cpu_valid = NULL;
3217 * Set the CPU read domain on a range of the object.
3219 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3220 * not entirely valid. The page_cpu_valid member of the object flags which
3221 * pages have been flushed, and will be respected by
3222 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3223 * of the whole object.
3225 * This function returns when the move is complete, including waiting on
3229 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3230 uint64_t offset, uint64_t size)
3232 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3233 uint32_t old_read_domains;
3236 if (offset == 0 && size == obj->size)
3237 return i915_gem_object_set_to_cpu_domain(obj, 0);
3239 i915_gem_object_flush_gpu_write_domain(obj);
3240 /* Wait on any GPU rendering and flushing to occur. */
3241 ret = i915_gem_object_wait_rendering(obj);
3244 i915_gem_object_flush_gtt_write_domain(obj);
3246 /* If we're already fully in the CPU read domain, we're done. */
3247 if (obj_priv->page_cpu_valid == NULL &&
3248 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3251 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3252 * newly adding I915_GEM_DOMAIN_CPU
3254 if (obj_priv->page_cpu_valid == NULL) {
3255 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3257 if (obj_priv->page_cpu_valid == NULL)
3259 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3260 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
3262 /* Flush the cache on any pages that are still invalid from the CPU's
3265 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3267 if (obj_priv->page_cpu_valid[i])
3270 drm_clflush_pages(obj_priv->pages + i, 1);
3272 obj_priv->page_cpu_valid[i] = 1;
3275 /* It should now be out of any other write domains, and we can update
3276 * the domain values for our changes.
3278 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3280 old_read_domains = obj->read_domains;
3281 obj->read_domains |= I915_GEM_DOMAIN_CPU;
3283 trace_i915_gem_object_change_domain(obj,
3291 * Pin an object to the GTT and evaluate the relocations landing in it.
3294 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3295 struct drm_file *file_priv,
3296 struct drm_i915_gem_exec_object2 *entry,
3297 struct drm_i915_gem_relocation_entry *relocs)
3299 struct drm_device *dev = obj->dev;
3300 drm_i915_private_t *dev_priv = dev->dev_private;
3301 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3303 void __iomem *reloc_page;
3306 need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
3307 obj_priv->tiling_mode != I915_TILING_NONE;
3309 /* Check fence reg constraints and rebind if necessary */
3311 !i915_gem_object_fence_offset_ok(obj,
3312 obj_priv->tiling_mode)) {
3313 ret = i915_gem_object_unbind(obj);
3318 /* Choose the GTT offset for our buffer and put it there. */
3319 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3324 * Pre-965 chips need a fence register set up in order to
3325 * properly handle blits to/from tiled surfaces.
3328 ret = i915_gem_object_get_fence_reg(obj);
3330 if (ret != -EBUSY && ret != -ERESTARTSYS)
3331 DRM_ERROR("Failure to install fence: %d\n",
3333 i915_gem_object_unpin(obj);
3338 entry->offset = obj_priv->gtt_offset;
3340 /* Apply the relocations, using the GTT aperture to avoid cache
3341 * flushing requirements.
3343 for (i = 0; i < entry->relocation_count; i++) {
3344 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
3345 struct drm_gem_object *target_obj;
3346 struct drm_i915_gem_object *target_obj_priv;
3347 uint32_t reloc_val, reloc_offset;
3348 uint32_t __iomem *reloc_entry;
3350 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
3351 reloc->target_handle);
3352 if (target_obj == NULL) {
3353 i915_gem_object_unpin(obj);
3356 target_obj_priv = to_intel_bo(target_obj);
3359 DRM_INFO("%s: obj %p offset %08x target %d "
3360 "read %08x write %08x gtt %08x "
3361 "presumed %08x delta %08x\n",
3364 (int) reloc->offset,
3365 (int) reloc->target_handle,
3366 (int) reloc->read_domains,
3367 (int) reloc->write_domain,
3368 (int) target_obj_priv->gtt_offset,
3369 (int) reloc->presumed_offset,
3373 /* The target buffer should have appeared before us in the
3374 * exec_object list, so it should have a GTT space bound by now.
3376 if (target_obj_priv->gtt_space == NULL) {
3377 DRM_ERROR("No GTT space found for object %d\n",
3378 reloc->target_handle);
3379 drm_gem_object_unreference(target_obj);
3380 i915_gem_object_unpin(obj);
3384 /* Validate that the target is in a valid r/w GPU domain */
3385 if (reloc->write_domain & (reloc->write_domain - 1)) {
3386 DRM_ERROR("reloc with multiple write domains: "
3387 "obj %p target %d offset %d "
3388 "read %08x write %08x",
3389 obj, reloc->target_handle,
3390 (int) reloc->offset,
3391 reloc->read_domains,
3392 reloc->write_domain);
3395 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3396 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
3397 DRM_ERROR("reloc with read/write CPU domains: "
3398 "obj %p target %d offset %d "
3399 "read %08x write %08x",
3400 obj, reloc->target_handle,
3401 (int) reloc->offset,
3402 reloc->read_domains,
3403 reloc->write_domain);
3404 drm_gem_object_unreference(target_obj);
3405 i915_gem_object_unpin(obj);
3408 if (reloc->write_domain && target_obj->pending_write_domain &&
3409 reloc->write_domain != target_obj->pending_write_domain) {
3410 DRM_ERROR("Write domain conflict: "
3411 "obj %p target %d offset %d "
3412 "new %08x old %08x\n",
3413 obj, reloc->target_handle,
3414 (int) reloc->offset,
3415 reloc->write_domain,
3416 target_obj->pending_write_domain);
3417 drm_gem_object_unreference(target_obj);
3418 i915_gem_object_unpin(obj);
3422 target_obj->pending_read_domains |= reloc->read_domains;
3423 target_obj->pending_write_domain |= reloc->write_domain;
3425 /* If the relocation already has the right value in it, no
3426 * more work needs to be done.
3428 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
3429 drm_gem_object_unreference(target_obj);
3433 /* Check that the relocation address is valid... */
3434 if (reloc->offset > obj->size - 4) {
3435 DRM_ERROR("Relocation beyond object bounds: "
3436 "obj %p target %d offset %d size %d.\n",
3437 obj, reloc->target_handle,
3438 (int) reloc->offset, (int) obj->size);
3439 drm_gem_object_unreference(target_obj);
3440 i915_gem_object_unpin(obj);
3443 if (reloc->offset & 3) {
3444 DRM_ERROR("Relocation not 4-byte aligned: "
3445 "obj %p target %d offset %d.\n",
3446 obj, reloc->target_handle,
3447 (int) reloc->offset);
3448 drm_gem_object_unreference(target_obj);
3449 i915_gem_object_unpin(obj);
3453 /* and points to somewhere within the target object. */
3454 if (reloc->delta >= target_obj->size) {
3455 DRM_ERROR("Relocation beyond target object bounds: "
3456 "obj %p target %d delta %d size %d.\n",
3457 obj, reloc->target_handle,
3458 (int) reloc->delta, (int) target_obj->size);
3459 drm_gem_object_unreference(target_obj);
3460 i915_gem_object_unpin(obj);
3464 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3466 drm_gem_object_unreference(target_obj);
3467 i915_gem_object_unpin(obj);
3471 /* Map the page containing the relocation we're going to
3474 reloc_offset = obj_priv->gtt_offset + reloc->offset;
3475 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3478 reloc_entry = (uint32_t __iomem *)(reloc_page +
3479 (reloc_offset & (PAGE_SIZE - 1)));
3480 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
3483 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3484 obj, (unsigned int) reloc->offset,
3485 readl(reloc_entry), reloc_val);
3487 writel(reloc_val, reloc_entry);
3488 io_mapping_unmap_atomic(reloc_page);
3490 /* The updated presumed offset for this entry will be
3491 * copied back out to the user.
3493 reloc->presumed_offset = target_obj_priv->gtt_offset;
3495 drm_gem_object_unreference(target_obj);
3500 i915_gem_dump_object(obj, 128, __func__, ~0);
3505 /* Throttle our rendering by waiting until the ring has completed our requests
3506 * emitted over 20 msec ago.
3508 * Note that if we were to use the current jiffies each time around the loop,
3509 * we wouldn't escape the function with any frames outstanding if the time to
3510 * render a frame was over 20ms.
3512 * This should get us reasonable parallelism between CPU and GPU but also
3513 * relatively low latency when blocking on a particular request to finish.
3516 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3518 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3520 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3522 mutex_lock(&dev->struct_mutex);
3523 while (!list_empty(&i915_file_priv->mm.request_list)) {
3524 struct drm_i915_gem_request *request;
3526 request = list_first_entry(&i915_file_priv->mm.request_list,
3527 struct drm_i915_gem_request,
3530 if (time_after_eq(request->emitted_jiffies, recent_enough))
3533 ret = i915_wait_request(dev, request->seqno, request->ring);
3537 mutex_unlock(&dev->struct_mutex);
3543 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list,
3544 uint32_t buffer_count,
3545 struct drm_i915_gem_relocation_entry **relocs)
3547 uint32_t reloc_count = 0, reloc_index = 0, i;
3551 for (i = 0; i < buffer_count; i++) {
3552 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3554 reloc_count += exec_list[i].relocation_count;
3557 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
3558 if (*relocs == NULL) {
3559 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count);
3563 for (i = 0; i < buffer_count; i++) {
3564 struct drm_i915_gem_relocation_entry __user *user_relocs;
3566 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3568 ret = copy_from_user(&(*relocs)[reloc_index],
3570 exec_list[i].relocation_count *
3573 drm_free_large(*relocs);
3578 reloc_index += exec_list[i].relocation_count;
3585 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list,
3586 uint32_t buffer_count,
3587 struct drm_i915_gem_relocation_entry *relocs)
3589 uint32_t reloc_count = 0, i;
3595 for (i = 0; i < buffer_count; i++) {
3596 struct drm_i915_gem_relocation_entry __user *user_relocs;
3599 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3601 unwritten = copy_to_user(user_relocs,
3602 &relocs[reloc_count],
3603 exec_list[i].relocation_count *
3611 reloc_count += exec_list[i].relocation_count;
3615 drm_free_large(relocs);
3621 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec,
3622 uint64_t exec_offset)
3624 uint32_t exec_start, exec_len;
3626 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3627 exec_len = (uint32_t) exec->batch_len;
3629 if ((exec_start | exec_len) & 0x7)
3639 i915_gem_wait_for_pending_flip(struct drm_device *dev,
3640 struct drm_gem_object **object_list,
3643 drm_i915_private_t *dev_priv = dev->dev_private;
3644 struct drm_i915_gem_object *obj_priv;
3649 prepare_to_wait(&dev_priv->pending_flip_queue,
3650 &wait, TASK_INTERRUPTIBLE);
3651 for (i = 0; i < count; i++) {
3652 obj_priv = to_intel_bo(object_list[i]);
3653 if (atomic_read(&obj_priv->pending_flip) > 0)
3659 if (!signal_pending(current)) {
3660 mutex_unlock(&dev->struct_mutex);
3662 mutex_lock(&dev->struct_mutex);
3668 finish_wait(&dev_priv->pending_flip_queue, &wait);
3674 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3675 struct drm_file *file_priv,
3676 struct drm_i915_gem_execbuffer2 *args,
3677 struct drm_i915_gem_exec_object2 *exec_list)
3679 drm_i915_private_t *dev_priv = dev->dev_private;
3680 struct drm_gem_object **object_list = NULL;
3681 struct drm_gem_object *batch_obj;
3682 struct drm_i915_gem_object *obj_priv;
3683 struct drm_clip_rect *cliprects = NULL;
3684 struct drm_i915_gem_relocation_entry *relocs = NULL;
3685 int ret = 0, ret2, i, pinned = 0;
3686 uint64_t exec_offset;
3687 uint32_t seqno, flush_domains, reloc_index;
3688 int pin_tries, flips;
3690 struct intel_ring_buffer *ring = NULL;
3693 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3694 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3696 if (args->flags & I915_EXEC_BSD) {
3697 if (!HAS_BSD(dev)) {
3698 DRM_ERROR("execbuf with wrong flag\n");
3701 ring = &dev_priv->bsd_ring;
3703 ring = &dev_priv->render_ring;
3707 if (args->buffer_count < 1) {
3708 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3711 object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
3712 if (object_list == NULL) {
3713 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3714 args->buffer_count);
3719 if (args->num_cliprects != 0) {
3720 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3722 if (cliprects == NULL) {
3727 ret = copy_from_user(cliprects,
3728 (struct drm_clip_rect __user *)
3729 (uintptr_t) args->cliprects_ptr,
3730 sizeof(*cliprects) * args->num_cliprects);
3732 DRM_ERROR("copy %d cliprects failed: %d\n",
3733 args->num_cliprects, ret);
3738 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3743 mutex_lock(&dev->struct_mutex);
3745 i915_verify_inactive(dev, __FILE__, __LINE__);
3747 if (atomic_read(&dev_priv->mm.wedged)) {
3748 mutex_unlock(&dev->struct_mutex);
3753 if (dev_priv->mm.suspended) {
3754 mutex_unlock(&dev->struct_mutex);
3759 /* Look up object handles */
3761 for (i = 0; i < args->buffer_count; i++) {
3762 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3763 exec_list[i].handle);
3764 if (object_list[i] == NULL) {
3765 DRM_ERROR("Invalid object handle %d at index %d\n",
3766 exec_list[i].handle, i);
3767 /* prevent error path from reading uninitialized data */
3768 args->buffer_count = i + 1;
3773 obj_priv = to_intel_bo(object_list[i]);
3774 if (obj_priv->in_execbuffer) {
3775 DRM_ERROR("Object %p appears more than once in object list\n",
3777 /* prevent error path from reading uninitialized data */
3778 args->buffer_count = i + 1;
3782 obj_priv->in_execbuffer = true;
3783 flips += atomic_read(&obj_priv->pending_flip);
3787 ret = i915_gem_wait_for_pending_flip(dev, object_list,
3788 args->buffer_count);
3793 /* Pin and relocate */
3794 for (pin_tries = 0; ; pin_tries++) {
3798 for (i = 0; i < args->buffer_count; i++) {
3799 object_list[i]->pending_read_domains = 0;
3800 object_list[i]->pending_write_domain = 0;
3801 ret = i915_gem_object_pin_and_relocate(object_list[i],
3804 &relocs[reloc_index]);
3808 reloc_index += exec_list[i].relocation_count;
3814 /* error other than GTT full, or we've already tried again */
3815 if (ret != -ENOSPC || pin_tries >= 1) {
3816 if (ret != -ERESTARTSYS) {
3817 unsigned long long total_size = 0;
3818 for (i = 0; i < args->buffer_count; i++)
3819 total_size += object_list[i]->size;
3820 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes: %d\n",
3821 pinned+1, args->buffer_count,
3823 DRM_ERROR("%d objects [%d pinned], "
3824 "%d object bytes [%d pinned], "
3825 "%d/%d gtt bytes\n",
3826 atomic_read(&dev->object_count),
3827 atomic_read(&dev->pin_count),
3828 atomic_read(&dev->object_memory),
3829 atomic_read(&dev->pin_memory),
3830 atomic_read(&dev->gtt_memory),
3836 /* unpin all of our buffers */
3837 for (i = 0; i < pinned; i++)
3838 i915_gem_object_unpin(object_list[i]);
3841 /* evict everyone we can from the aperture */
3842 ret = i915_gem_evict_everything(dev);
3843 if (ret && ret != -ENOSPC)
3847 /* Set the pending read domains for the batch buffer to COMMAND */
3848 batch_obj = object_list[args->buffer_count-1];
3849 if (batch_obj->pending_write_domain) {
3850 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3854 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
3856 /* Sanity check the batch buffer, prior to moving objects */
3857 exec_offset = exec_list[args->buffer_count - 1].offset;
3858 ret = i915_gem_check_execbuffer (args, exec_offset);
3860 DRM_ERROR("execbuf with invalid offset/length\n");
3864 i915_verify_inactive(dev, __FILE__, __LINE__);
3866 /* Zero the global flush/invalidate flags. These
3867 * will be modified as new domains are computed
3870 dev->invalidate_domains = 0;
3871 dev->flush_domains = 0;
3873 for (i = 0; i < args->buffer_count; i++) {
3874 struct drm_gem_object *obj = object_list[i];
3876 /* Compute new gpu domains and update invalidate/flush */
3877 i915_gem_object_set_to_gpu_domain(obj);
3880 i915_verify_inactive(dev, __FILE__, __LINE__);
3882 if (dev->invalidate_domains | dev->flush_domains) {
3884 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3886 dev->invalidate_domains,
3887 dev->flush_domains);
3890 dev->invalidate_domains,
3891 dev->flush_domains);
3892 if (dev->flush_domains & I915_GEM_GPU_DOMAINS) {
3893 (void)i915_add_request(dev, file_priv,
3895 &dev_priv->render_ring);
3898 (void)i915_add_request(dev, file_priv,
3900 &dev_priv->bsd_ring);
3904 for (i = 0; i < args->buffer_count; i++) {
3905 struct drm_gem_object *obj = object_list[i];
3906 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3907 uint32_t old_write_domain = obj->write_domain;
3909 obj->write_domain = obj->pending_write_domain;
3910 if (obj->write_domain)
3911 list_move_tail(&obj_priv->gpu_write_list,
3912 &dev_priv->mm.gpu_write_list);
3914 list_del_init(&obj_priv->gpu_write_list);
3916 trace_i915_gem_object_change_domain(obj,
3921 i915_verify_inactive(dev, __FILE__, __LINE__);
3924 for (i = 0; i < args->buffer_count; i++) {
3925 i915_gem_object_check_coherency(object_list[i],
3926 exec_list[i].handle);
3931 i915_gem_dump_object(batch_obj,
3937 /* Exec the batchbuffer */
3938 ret = ring->dispatch_gem_execbuffer(dev, ring, args,
3939 cliprects, exec_offset);
3941 DRM_ERROR("dispatch failed %d\n", ret);
3946 * Ensure that the commands in the batch buffer are
3947 * finished before the interrupt fires
3949 flush_domains = i915_retire_commands(dev, ring);
3951 i915_verify_inactive(dev, __FILE__, __LINE__);
3954 * Get a seqno representing the execution of the current buffer,
3955 * which we can wait on. We would like to mitigate these interrupts,
3956 * likely by only creating seqnos occasionally (so that we have
3957 * *some* interrupts representing completion of buffers that we can
3958 * wait on when trying to clear up gtt space).
3960 seqno = i915_add_request(dev, file_priv, flush_domains, ring);
3962 for (i = 0; i < args->buffer_count; i++) {
3963 struct drm_gem_object *obj = object_list[i];
3964 obj_priv = to_intel_bo(obj);
3966 i915_gem_object_move_to_active(obj, seqno, ring);
3968 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3972 i915_dump_lru(dev, __func__);
3975 i915_verify_inactive(dev, __FILE__, __LINE__);
3978 for (i = 0; i < pinned; i++)
3979 i915_gem_object_unpin(object_list[i]);
3981 for (i = 0; i < args->buffer_count; i++) {
3982 if (object_list[i]) {
3983 obj_priv = to_intel_bo(object_list[i]);
3984 obj_priv->in_execbuffer = false;
3986 drm_gem_object_unreference(object_list[i]);
3989 mutex_unlock(&dev->struct_mutex);
3992 /* Copy the updated relocations out regardless of current error
3993 * state. Failure to update the relocs would mean that the next
3994 * time userland calls execbuf, it would do so with presumed offset
3995 * state that didn't match the actual object state.
3997 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
4000 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
4006 drm_free_large(object_list);
4013 * Legacy execbuffer just creates an exec2 list from the original exec object
4014 * list array and passes it to the real function.
4017 i915_gem_execbuffer(struct drm_device *dev, void *data,
4018 struct drm_file *file_priv)
4020 struct drm_i915_gem_execbuffer *args = data;
4021 struct drm_i915_gem_execbuffer2 exec2;
4022 struct drm_i915_gem_exec_object *exec_list = NULL;
4023 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4027 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4028 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4031 if (args->buffer_count < 1) {
4032 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
4036 /* Copy in the exec list from userland */
4037 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
4038 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4039 if (exec_list == NULL || exec2_list == NULL) {
4040 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4041 args->buffer_count);
4042 drm_free_large(exec_list);
4043 drm_free_large(exec2_list);
4046 ret = copy_from_user(exec_list,
4047 (struct drm_i915_relocation_entry __user *)
4048 (uintptr_t) args->buffers_ptr,
4049 sizeof(*exec_list) * args->buffer_count);
4051 DRM_ERROR("copy %d exec entries failed %d\n",
4052 args->buffer_count, ret);
4053 drm_free_large(exec_list);
4054 drm_free_large(exec2_list);
4058 for (i = 0; i < args->buffer_count; i++) {
4059 exec2_list[i].handle = exec_list[i].handle;
4060 exec2_list[i].relocation_count = exec_list[i].relocation_count;
4061 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
4062 exec2_list[i].alignment = exec_list[i].alignment;
4063 exec2_list[i].offset = exec_list[i].offset;
4065 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
4067 exec2_list[i].flags = 0;
4070 exec2.buffers_ptr = args->buffers_ptr;
4071 exec2.buffer_count = args->buffer_count;
4072 exec2.batch_start_offset = args->batch_start_offset;
4073 exec2.batch_len = args->batch_len;
4074 exec2.DR1 = args->DR1;
4075 exec2.DR4 = args->DR4;
4076 exec2.num_cliprects = args->num_cliprects;
4077 exec2.cliprects_ptr = args->cliprects_ptr;
4078 exec2.flags = I915_EXEC_RENDER;
4080 ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
4082 /* Copy the new buffer offsets back to the user's exec list. */
4083 for (i = 0; i < args->buffer_count; i++)
4084 exec_list[i].offset = exec2_list[i].offset;
4085 /* ... and back out to userspace */
4086 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4087 (uintptr_t) args->buffers_ptr,
4089 sizeof(*exec_list) * args->buffer_count);
4092 DRM_ERROR("failed to copy %d exec entries "
4093 "back to user (%d)\n",
4094 args->buffer_count, ret);
4098 drm_free_large(exec_list);
4099 drm_free_large(exec2_list);
4104 i915_gem_execbuffer2(struct drm_device *dev, void *data,
4105 struct drm_file *file_priv)
4107 struct drm_i915_gem_execbuffer2 *args = data;
4108 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4112 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4113 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4116 if (args->buffer_count < 1) {
4117 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
4121 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4122 if (exec2_list == NULL) {
4123 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4124 args->buffer_count);
4127 ret = copy_from_user(exec2_list,
4128 (struct drm_i915_relocation_entry __user *)
4129 (uintptr_t) args->buffers_ptr,
4130 sizeof(*exec2_list) * args->buffer_count);
4132 DRM_ERROR("copy %d exec entries failed %d\n",
4133 args->buffer_count, ret);
4134 drm_free_large(exec2_list);
4138 ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
4140 /* Copy the new buffer offsets back to the user's exec list. */
4141 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4142 (uintptr_t) args->buffers_ptr,
4144 sizeof(*exec2_list) * args->buffer_count);
4147 DRM_ERROR("failed to copy %d exec entries "
4148 "back to user (%d)\n",
4149 args->buffer_count, ret);
4153 drm_free_large(exec2_list);
4158 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
4160 struct drm_device *dev = obj->dev;
4161 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4164 BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
4166 i915_verify_inactive(dev, __FILE__, __LINE__);
4168 if (obj_priv->gtt_space != NULL) {
4170 alignment = i915_gem_get_gtt_alignment(obj);
4171 if (obj_priv->gtt_offset & (alignment - 1)) {
4172 ret = i915_gem_object_unbind(obj);
4178 if (obj_priv->gtt_space == NULL) {
4179 ret = i915_gem_object_bind_to_gtt(obj, alignment);
4184 obj_priv->pin_count++;
4186 /* If the object is not active and not pending a flush,
4187 * remove it from the inactive list
4189 if (obj_priv->pin_count == 1) {
4190 atomic_inc(&dev->pin_count);
4191 atomic_add(obj->size, &dev->pin_memory);
4192 if (!obj_priv->active &&
4193 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 &&
4194 !list_empty(&obj_priv->list))
4195 list_del_init(&obj_priv->list);
4197 i915_verify_inactive(dev, __FILE__, __LINE__);
4203 i915_gem_object_unpin(struct drm_gem_object *obj)
4205 struct drm_device *dev = obj->dev;
4206 drm_i915_private_t *dev_priv = dev->dev_private;
4207 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4209 i915_verify_inactive(dev, __FILE__, __LINE__);
4210 obj_priv->pin_count--;
4211 BUG_ON(obj_priv->pin_count < 0);
4212 BUG_ON(obj_priv->gtt_space == NULL);
4214 /* If the object is no longer pinned, and is
4215 * neither active nor being flushed, then stick it on
4218 if (obj_priv->pin_count == 0) {
4219 if (!obj_priv->active &&
4220 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
4221 list_move_tail(&obj_priv->list,
4222 &dev_priv->mm.inactive_list);
4223 atomic_dec(&dev->pin_count);
4224 atomic_sub(obj->size, &dev->pin_memory);
4226 i915_verify_inactive(dev, __FILE__, __LINE__);
4230 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4231 struct drm_file *file_priv)
4233 struct drm_i915_gem_pin *args = data;
4234 struct drm_gem_object *obj;
4235 struct drm_i915_gem_object *obj_priv;
4238 mutex_lock(&dev->struct_mutex);
4240 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4242 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4244 mutex_unlock(&dev->struct_mutex);
4247 obj_priv = to_intel_bo(obj);
4249 if (obj_priv->madv != I915_MADV_WILLNEED) {
4250 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4251 drm_gem_object_unreference(obj);
4252 mutex_unlock(&dev->struct_mutex);
4256 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
4257 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4259 drm_gem_object_unreference(obj);
4260 mutex_unlock(&dev->struct_mutex);
4264 obj_priv->user_pin_count++;
4265 obj_priv->pin_filp = file_priv;
4266 if (obj_priv->user_pin_count == 1) {
4267 ret = i915_gem_object_pin(obj, args->alignment);
4269 drm_gem_object_unreference(obj);
4270 mutex_unlock(&dev->struct_mutex);
4275 /* XXX - flush the CPU caches for pinned objects
4276 * as the X server doesn't manage domains yet
4278 i915_gem_object_flush_cpu_write_domain(obj);
4279 args->offset = obj_priv->gtt_offset;
4280 drm_gem_object_unreference(obj);
4281 mutex_unlock(&dev->struct_mutex);
4287 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4288 struct drm_file *file_priv)
4290 struct drm_i915_gem_pin *args = data;
4291 struct drm_gem_object *obj;
4292 struct drm_i915_gem_object *obj_priv;
4294 mutex_lock(&dev->struct_mutex);
4296 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4298 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4300 mutex_unlock(&dev->struct_mutex);
4304 obj_priv = to_intel_bo(obj);
4305 if (obj_priv->pin_filp != file_priv) {
4306 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4308 drm_gem_object_unreference(obj);
4309 mutex_unlock(&dev->struct_mutex);
4312 obj_priv->user_pin_count--;
4313 if (obj_priv->user_pin_count == 0) {
4314 obj_priv->pin_filp = NULL;
4315 i915_gem_object_unpin(obj);
4318 drm_gem_object_unreference(obj);
4319 mutex_unlock(&dev->struct_mutex);
4324 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4325 struct drm_file *file_priv)
4327 struct drm_i915_gem_busy *args = data;
4328 struct drm_gem_object *obj;
4329 struct drm_i915_gem_object *obj_priv;
4330 drm_i915_private_t *dev_priv = dev->dev_private;
4332 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4334 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4339 mutex_lock(&dev->struct_mutex);
4340 /* Update the active list for the hardware's current position.
4341 * Otherwise this only updates on a delayed timer or when irqs are
4342 * actually unmasked, and our working set ends up being larger than
4345 i915_gem_retire_requests(dev, &dev_priv->render_ring);
4348 i915_gem_retire_requests(dev, &dev_priv->bsd_ring);
4350 obj_priv = to_intel_bo(obj);
4351 /* Don't count being on the flushing list against the object being
4352 * done. Otherwise, a buffer left on the flushing list but not getting
4353 * flushed (because nobody's flushing that domain) won't ever return
4354 * unbusy and get reused by libdrm's bo cache. The other expected
4355 * consumer of this interface, OpenGL's occlusion queries, also specs
4356 * that the objects get unbusy "eventually" without any interference.
4358 args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
4360 drm_gem_object_unreference(obj);
4361 mutex_unlock(&dev->struct_mutex);
4366 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4367 struct drm_file *file_priv)
4369 return i915_gem_ring_throttle(dev, file_priv);
4373 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4374 struct drm_file *file_priv)
4376 struct drm_i915_gem_madvise *args = data;
4377 struct drm_gem_object *obj;
4378 struct drm_i915_gem_object *obj_priv;
4380 switch (args->madv) {
4381 case I915_MADV_DONTNEED:
4382 case I915_MADV_WILLNEED:
4388 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4390 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4395 mutex_lock(&dev->struct_mutex);
4396 obj_priv = to_intel_bo(obj);
4398 if (obj_priv->pin_count) {
4399 drm_gem_object_unreference(obj);
4400 mutex_unlock(&dev->struct_mutex);
4402 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4406 if (obj_priv->madv != __I915_MADV_PURGED)
4407 obj_priv->madv = args->madv;
4409 /* if the object is no longer bound, discard its backing storage */
4410 if (i915_gem_object_is_purgeable(obj_priv) &&
4411 obj_priv->gtt_space == NULL)
4412 i915_gem_object_truncate(obj);
4414 args->retained = obj_priv->madv != __I915_MADV_PURGED;
4416 drm_gem_object_unreference(obj);
4417 mutex_unlock(&dev->struct_mutex);
4422 struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
4425 struct drm_i915_gem_object *obj;
4427 obj = kzalloc(sizeof(*obj), GFP_KERNEL);
4431 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4436 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4437 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4439 obj->agp_type = AGP_USER_MEMORY;
4440 obj->base.driver_private = NULL;
4441 obj->fence_reg = I915_FENCE_REG_NONE;
4442 INIT_LIST_HEAD(&obj->list);
4443 INIT_LIST_HEAD(&obj->gpu_write_list);
4444 obj->madv = I915_MADV_WILLNEED;
4446 trace_i915_gem_object_create(&obj->base);
4451 int i915_gem_init_object(struct drm_gem_object *obj)
4458 void i915_gem_free_object(struct drm_gem_object *obj)
4460 struct drm_device *dev = obj->dev;
4461 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4463 trace_i915_gem_object_destroy(obj);
4465 while (obj_priv->pin_count > 0)
4466 i915_gem_object_unpin(obj);
4468 if (obj_priv->phys_obj)
4469 i915_gem_detach_phys_object(dev, obj);
4471 i915_gem_object_unbind(obj);
4473 if (obj_priv->mmap_offset)
4474 i915_gem_free_mmap_offset(obj);
4476 drm_gem_object_release(obj);
4478 kfree(obj_priv->page_cpu_valid);
4479 kfree(obj_priv->bit_17);
4483 /** Unbinds all inactive objects. */
4485 i915_gem_evict_from_inactive_list(struct drm_device *dev)
4487 drm_i915_private_t *dev_priv = dev->dev_private;
4489 while (!list_empty(&dev_priv->mm.inactive_list)) {
4490 struct drm_gem_object *obj;
4493 obj = &list_first_entry(&dev_priv->mm.inactive_list,
4494 struct drm_i915_gem_object,
4497 ret = i915_gem_object_unbind(obj);
4499 DRM_ERROR("Error unbinding object: %d\n", ret);
4508 i915_gem_idle(struct drm_device *dev)
4510 drm_i915_private_t *dev_priv = dev->dev_private;
4513 mutex_lock(&dev->struct_mutex);
4515 if (dev_priv->mm.suspended ||
4516 (dev_priv->render_ring.gem_object == NULL) ||
4518 dev_priv->bsd_ring.gem_object == NULL)) {
4519 mutex_unlock(&dev->struct_mutex);
4523 ret = i915_gpu_idle(dev);
4525 mutex_unlock(&dev->struct_mutex);
4529 /* Under UMS, be paranoid and evict. */
4530 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
4531 ret = i915_gem_evict_from_inactive_list(dev);
4533 mutex_unlock(&dev->struct_mutex);
4538 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4539 * We need to replace this with a semaphore, or something.
4540 * And not confound mm.suspended!
4542 dev_priv->mm.suspended = 1;
4543 del_timer(&dev_priv->hangcheck_timer);
4545 i915_kernel_lost_context(dev);
4546 i915_gem_cleanup_ringbuffer(dev);
4548 mutex_unlock(&dev->struct_mutex);
4550 /* Cancel the retire work handler, which should be idle now. */
4551 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4557 * 965+ support PIPE_CONTROL commands, which provide finer grained control
4558 * over cache flushing.
4561 i915_gem_init_pipe_control(struct drm_device *dev)
4563 drm_i915_private_t *dev_priv = dev->dev_private;
4564 struct drm_gem_object *obj;
4565 struct drm_i915_gem_object *obj_priv;
4568 obj = i915_gem_alloc_object(dev, 4096);
4570 DRM_ERROR("Failed to allocate seqno page\n");
4574 obj_priv = to_intel_bo(obj);
4575 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4577 ret = i915_gem_object_pin(obj, 4096);
4581 dev_priv->seqno_gfx_addr = obj_priv->gtt_offset;
4582 dev_priv->seqno_page = kmap(obj_priv->pages[0]);
4583 if (dev_priv->seqno_page == NULL)
4586 dev_priv->seqno_obj = obj;
4587 memset(dev_priv->seqno_page, 0, PAGE_SIZE);
4592 i915_gem_object_unpin(obj);
4594 drm_gem_object_unreference(obj);
4601 i915_gem_cleanup_pipe_control(struct drm_device *dev)
4603 drm_i915_private_t *dev_priv = dev->dev_private;
4604 struct drm_gem_object *obj;
4605 struct drm_i915_gem_object *obj_priv;
4607 obj = dev_priv->seqno_obj;
4608 obj_priv = to_intel_bo(obj);
4609 kunmap(obj_priv->pages[0]);
4610 i915_gem_object_unpin(obj);
4611 drm_gem_object_unreference(obj);
4612 dev_priv->seqno_obj = NULL;
4614 dev_priv->seqno_page = NULL;
4618 i915_gem_init_ringbuffer(struct drm_device *dev)
4620 drm_i915_private_t *dev_priv = dev->dev_private;
4622 dev_priv->render_ring = render_ring;
4623 if (!I915_NEED_GFX_HWS(dev)) {
4624 dev_priv->render_ring.status_page.page_addr
4625 = dev_priv->status_page_dmah->vaddr;
4626 memset(dev_priv->render_ring.status_page.page_addr,
4629 if (HAS_PIPE_CONTROL(dev)) {
4630 ret = i915_gem_init_pipe_control(dev);
4634 ret = intel_init_ring_buffer(dev, &dev_priv->render_ring);
4635 if (!ret && HAS_BSD(dev)) {
4636 dev_priv->bsd_ring = bsd_ring;
4637 ret = intel_init_ring_buffer(dev, &dev_priv->bsd_ring);
4643 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4645 drm_i915_private_t *dev_priv = dev->dev_private;
4647 intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
4649 intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
4650 if (HAS_PIPE_CONTROL(dev))
4651 i915_gem_cleanup_pipe_control(dev);
4655 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4656 struct drm_file *file_priv)
4658 drm_i915_private_t *dev_priv = dev->dev_private;
4661 if (drm_core_check_feature(dev, DRIVER_MODESET))
4664 if (atomic_read(&dev_priv->mm.wedged)) {
4665 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4666 atomic_set(&dev_priv->mm.wedged, 0);
4669 mutex_lock(&dev->struct_mutex);
4670 dev_priv->mm.suspended = 0;
4672 ret = i915_gem_init_ringbuffer(dev);
4674 mutex_unlock(&dev->struct_mutex);
4678 spin_lock(&dev_priv->mm.active_list_lock);
4679 BUG_ON(!list_empty(&dev_priv->render_ring.active_list));
4680 BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.active_list));
4681 spin_unlock(&dev_priv->mm.active_list_lock);
4683 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4684 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4685 BUG_ON(!list_empty(&dev_priv->render_ring.request_list));
4686 BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.request_list));
4687 mutex_unlock(&dev->struct_mutex);
4689 drm_irq_install(dev);
4695 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4696 struct drm_file *file_priv)
4698 if (drm_core_check_feature(dev, DRIVER_MODESET))
4701 drm_irq_uninstall(dev);
4702 return i915_gem_idle(dev);
4706 i915_gem_lastclose(struct drm_device *dev)
4710 if (drm_core_check_feature(dev, DRIVER_MODESET))
4713 ret = i915_gem_idle(dev);
4715 DRM_ERROR("failed to idle hardware: %d\n", ret);
4719 i915_gem_load(struct drm_device *dev)
4722 drm_i915_private_t *dev_priv = dev->dev_private;
4724 spin_lock_init(&dev_priv->mm.active_list_lock);
4725 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4726 INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list);
4727 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4728 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4729 INIT_LIST_HEAD(&dev_priv->render_ring.active_list);
4730 INIT_LIST_HEAD(&dev_priv->render_ring.request_list);
4732 INIT_LIST_HEAD(&dev_priv->bsd_ring.active_list);
4733 INIT_LIST_HEAD(&dev_priv->bsd_ring.request_list);
4735 for (i = 0; i < 16; i++)
4736 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4737 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4738 i915_gem_retire_work_handler);
4739 spin_lock(&shrink_list_lock);
4740 list_add(&dev_priv->mm.shrink_list, &shrink_list);
4741 spin_unlock(&shrink_list_lock);
4743 /* Old X drivers will take 0-2 for front, back, depth buffers */
4744 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4745 dev_priv->fence_reg_start = 3;
4747 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4748 dev_priv->num_fence_regs = 16;
4750 dev_priv->num_fence_regs = 8;
4752 /* Initialize fence registers to zero */
4753 if (IS_I965G(dev)) {
4754 for (i = 0; i < 16; i++)
4755 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4757 for (i = 0; i < 8; i++)
4758 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4759 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4760 for (i = 0; i < 8; i++)
4761 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4763 i915_gem_detect_bit_6_swizzle(dev);
4764 init_waitqueue_head(&dev_priv->pending_flip_queue);
4768 * Create a physically contiguous memory object for this object
4769 * e.g. for cursor + overlay regs
4771 int i915_gem_init_phys_object(struct drm_device *dev,
4774 drm_i915_private_t *dev_priv = dev->dev_private;
4775 struct drm_i915_gem_phys_object *phys_obj;
4778 if (dev_priv->mm.phys_objs[id - 1] || !size)
4781 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4787 phys_obj->handle = drm_pci_alloc(dev, size, 0);
4788 if (!phys_obj->handle) {
4793 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4796 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4804 void i915_gem_free_phys_object(struct drm_device *dev, int id)
4806 drm_i915_private_t *dev_priv = dev->dev_private;
4807 struct drm_i915_gem_phys_object *phys_obj;
4809 if (!dev_priv->mm.phys_objs[id - 1])
4812 phys_obj = dev_priv->mm.phys_objs[id - 1];
4813 if (phys_obj->cur_obj) {
4814 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4818 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4820 drm_pci_free(dev, phys_obj->handle);
4822 dev_priv->mm.phys_objs[id - 1] = NULL;
4825 void i915_gem_free_all_phys_object(struct drm_device *dev)
4829 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4830 i915_gem_free_phys_object(dev, i);
4833 void i915_gem_detach_phys_object(struct drm_device *dev,
4834 struct drm_gem_object *obj)
4836 struct drm_i915_gem_object *obj_priv;
4841 obj_priv = to_intel_bo(obj);
4842 if (!obj_priv->phys_obj)
4845 ret = i915_gem_object_get_pages(obj, 0);
4849 page_count = obj->size / PAGE_SIZE;
4851 for (i = 0; i < page_count; i++) {
4852 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
4853 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4855 memcpy(dst, src, PAGE_SIZE);
4856 kunmap_atomic(dst, KM_USER0);
4858 drm_clflush_pages(obj_priv->pages, page_count);
4859 drm_agp_chipset_flush(dev);
4861 i915_gem_object_put_pages(obj);
4863 obj_priv->phys_obj->cur_obj = NULL;
4864 obj_priv->phys_obj = NULL;
4868 i915_gem_attach_phys_object(struct drm_device *dev,
4869 struct drm_gem_object *obj, int id)
4871 drm_i915_private_t *dev_priv = dev->dev_private;
4872 struct drm_i915_gem_object *obj_priv;
4877 if (id > I915_MAX_PHYS_OBJECT)
4880 obj_priv = to_intel_bo(obj);
4882 if (obj_priv->phys_obj) {
4883 if (obj_priv->phys_obj->id == id)
4885 i915_gem_detach_phys_object(dev, obj);
4889 /* create a new object */
4890 if (!dev_priv->mm.phys_objs[id - 1]) {
4891 ret = i915_gem_init_phys_object(dev, id,
4894 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
4899 /* bind to the object */
4900 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4901 obj_priv->phys_obj->cur_obj = obj;
4903 ret = i915_gem_object_get_pages(obj, 0);
4905 DRM_ERROR("failed to get page list\n");
4909 page_count = obj->size / PAGE_SIZE;
4911 for (i = 0; i < page_count; i++) {
4912 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
4913 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4915 memcpy(dst, src, PAGE_SIZE);
4916 kunmap_atomic(src, KM_USER0);
4919 i915_gem_object_put_pages(obj);
4927 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4928 struct drm_i915_gem_pwrite *args,
4929 struct drm_file *file_priv)
4931 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4934 char __user *user_data;
4936 user_data = (char __user *) (uintptr_t) args->data_ptr;
4937 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4939 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size);
4940 ret = copy_from_user(obj_addr, user_data, args->size);
4944 drm_agp_chipset_flush(dev);
4948 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
4950 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
4952 /* Clean up our request list when the client is going away, so that
4953 * later retire_requests won't dereference our soon-to-be-gone
4956 mutex_lock(&dev->struct_mutex);
4957 while (!list_empty(&i915_file_priv->mm.request_list))
4958 list_del_init(i915_file_priv->mm.request_list.next);
4959 mutex_unlock(&dev->struct_mutex);
4963 i915_gpu_is_active(struct drm_device *dev)
4965 drm_i915_private_t *dev_priv = dev->dev_private;
4968 spin_lock(&dev_priv->mm.active_list_lock);
4969 lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
4970 list_empty(&dev_priv->render_ring.active_list);
4972 lists_empty &= list_empty(&dev_priv->bsd_ring.active_list);
4973 spin_unlock(&dev_priv->mm.active_list_lock);
4975 return !lists_empty;
4979 i915_gem_shrink(int nr_to_scan, gfp_t gfp_mask)
4981 drm_i915_private_t *dev_priv, *next_dev;
4982 struct drm_i915_gem_object *obj_priv, *next_obj;
4984 int would_deadlock = 1;
4986 /* "fast-path" to count number of available objects */
4987 if (nr_to_scan == 0) {
4988 spin_lock(&shrink_list_lock);
4989 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4990 struct drm_device *dev = dev_priv->dev;
4992 if (mutex_trylock(&dev->struct_mutex)) {
4993 list_for_each_entry(obj_priv,
4994 &dev_priv->mm.inactive_list,
4997 mutex_unlock(&dev->struct_mutex);
5000 spin_unlock(&shrink_list_lock);
5002 return (cnt / 100) * sysctl_vfs_cache_pressure;
5005 spin_lock(&shrink_list_lock);
5008 /* first scan for clean buffers */
5009 list_for_each_entry_safe(dev_priv, next_dev,
5010 &shrink_list, mm.shrink_list) {
5011 struct drm_device *dev = dev_priv->dev;
5013 if (! mutex_trylock(&dev->struct_mutex))
5016 spin_unlock(&shrink_list_lock);
5017 i915_gem_retire_requests(dev, &dev_priv->render_ring);
5020 i915_gem_retire_requests(dev, &dev_priv->bsd_ring);
5022 list_for_each_entry_safe(obj_priv, next_obj,
5023 &dev_priv->mm.inactive_list,
5025 if (i915_gem_object_is_purgeable(obj_priv)) {
5026 i915_gem_object_unbind(&obj_priv->base);
5027 if (--nr_to_scan <= 0)
5032 spin_lock(&shrink_list_lock);
5033 mutex_unlock(&dev->struct_mutex);
5037 if (nr_to_scan <= 0)
5041 /* second pass, evict/count anything still on the inactive list */
5042 list_for_each_entry_safe(dev_priv, next_dev,
5043 &shrink_list, mm.shrink_list) {
5044 struct drm_device *dev = dev_priv->dev;
5046 if (! mutex_trylock(&dev->struct_mutex))
5049 spin_unlock(&shrink_list_lock);
5051 list_for_each_entry_safe(obj_priv, next_obj,
5052 &dev_priv->mm.inactive_list,
5054 if (nr_to_scan > 0) {
5055 i915_gem_object_unbind(&obj_priv->base);
5061 spin_lock(&shrink_list_lock);
5062 mutex_unlock(&dev->struct_mutex);
5071 * We are desperate for pages, so as a last resort, wait
5072 * for the GPU to finish and discard whatever we can.
5073 * This has a dramatic impact to reduce the number of
5074 * OOM-killer events whilst running the GPU aggressively.
5076 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
5077 struct drm_device *dev = dev_priv->dev;
5079 if (!mutex_trylock(&dev->struct_mutex))
5082 spin_unlock(&shrink_list_lock);
5084 if (i915_gpu_is_active(dev)) {
5089 spin_lock(&shrink_list_lock);
5090 mutex_unlock(&dev->struct_mutex);
5097 spin_unlock(&shrink_list_lock);
5102 return (cnt / 100) * sysctl_vfs_cache_pressure;
5107 static struct shrinker shrinker = {
5108 .shrink = i915_gem_shrink,
5109 .seeks = DEFAULT_SEEKS,
5113 i915_gem_shrinker_init(void)
5115 register_shrinker(&shrinker);
5119 i915_gem_shrinker_exit(void)
5121 unregister_shrinker(&shrinker);