2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/swap.h>
35 #include <linux/pci.h>
37 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
39 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
42 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
44 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
47 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
48 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
49 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
51 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
52 static int i915_gem_evict_something(struct drm_device *dev, int min_size);
53 static int i915_gem_evict_from_inactive_list(struct drm_device *dev);
54 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
55 struct drm_i915_gem_pwrite *args,
56 struct drm_file *file_priv);
58 static LIST_HEAD(shrink_list);
59 static DEFINE_SPINLOCK(shrink_list_lock);
61 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
64 drm_i915_private_t *dev_priv = dev->dev_private;
67 (start & (PAGE_SIZE - 1)) != 0 ||
68 (end & (PAGE_SIZE - 1)) != 0) {
72 drm_mm_init(&dev_priv->mm.gtt_space, start,
75 dev->gtt_total = (uint32_t) (end - start);
81 i915_gem_init_ioctl(struct drm_device *dev, void *data,
82 struct drm_file *file_priv)
84 struct drm_i915_gem_init *args = data;
87 mutex_lock(&dev->struct_mutex);
88 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
89 mutex_unlock(&dev->struct_mutex);
95 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
96 struct drm_file *file_priv)
98 struct drm_i915_gem_get_aperture *args = data;
100 if (!(dev->driver->driver_features & DRIVER_GEM))
103 args->aper_size = dev->gtt_total;
104 args->aper_available_size = (args->aper_size -
105 atomic_read(&dev->pin_memory));
112 * Creates a new mm object and returns a handle to it.
115 i915_gem_create_ioctl(struct drm_device *dev, void *data,
116 struct drm_file *file_priv)
118 struct drm_i915_gem_create *args = data;
119 struct drm_gem_object *obj;
123 args->size = roundup(args->size, PAGE_SIZE);
125 /* Allocate the new object */
126 obj = drm_gem_object_alloc(dev, args->size);
130 ret = drm_gem_handle_create(file_priv, obj, &handle);
131 drm_gem_object_handle_unreference_unlocked(obj);
136 args->handle = handle;
142 fast_shmem_read(struct page **pages,
143 loff_t page_base, int page_offset,
150 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
153 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
154 kunmap_atomic(vaddr, KM_USER0);
162 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
164 drm_i915_private_t *dev_priv = obj->dev->dev_private;
165 struct drm_i915_gem_object *obj_priv = obj->driver_private;
167 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
168 obj_priv->tiling_mode != I915_TILING_NONE;
172 slow_shmem_copy(struct page *dst_page,
174 struct page *src_page,
178 char *dst_vaddr, *src_vaddr;
180 dst_vaddr = kmap_atomic(dst_page, KM_USER0);
181 if (dst_vaddr == NULL)
184 src_vaddr = kmap_atomic(src_page, KM_USER1);
185 if (src_vaddr == NULL) {
186 kunmap_atomic(dst_vaddr, KM_USER0);
190 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
192 kunmap_atomic(src_vaddr, KM_USER1);
193 kunmap_atomic(dst_vaddr, KM_USER0);
199 slow_shmem_bit17_copy(struct page *gpu_page,
201 struct page *cpu_page,
206 char *gpu_vaddr, *cpu_vaddr;
208 /* Use the unswizzled path if this page isn't affected. */
209 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
211 return slow_shmem_copy(cpu_page, cpu_offset,
212 gpu_page, gpu_offset, length);
214 return slow_shmem_copy(gpu_page, gpu_offset,
215 cpu_page, cpu_offset, length);
218 gpu_vaddr = kmap_atomic(gpu_page, KM_USER0);
219 if (gpu_vaddr == NULL)
222 cpu_vaddr = kmap_atomic(cpu_page, KM_USER1);
223 if (cpu_vaddr == NULL) {
224 kunmap_atomic(gpu_vaddr, KM_USER0);
228 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
229 * XORing with the other bits (A9 for Y, A9 and A10 for X)
232 int cacheline_end = ALIGN(gpu_offset + 1, 64);
233 int this_length = min(cacheline_end - gpu_offset, length);
234 int swizzled_gpu_offset = gpu_offset ^ 64;
237 memcpy(cpu_vaddr + cpu_offset,
238 gpu_vaddr + swizzled_gpu_offset,
241 memcpy(gpu_vaddr + swizzled_gpu_offset,
242 cpu_vaddr + cpu_offset,
245 cpu_offset += this_length;
246 gpu_offset += this_length;
247 length -= this_length;
250 kunmap_atomic(cpu_vaddr, KM_USER1);
251 kunmap_atomic(gpu_vaddr, KM_USER0);
257 * This is the fast shmem pread path, which attempts to copy_from_user directly
258 * from the backing pages of the object to the user's address space. On a
259 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
262 i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
263 struct drm_i915_gem_pread *args,
264 struct drm_file *file_priv)
266 struct drm_i915_gem_object *obj_priv = obj->driver_private;
268 loff_t offset, page_base;
269 char __user *user_data;
270 int page_offset, page_length;
273 user_data = (char __user *) (uintptr_t) args->data_ptr;
276 mutex_lock(&dev->struct_mutex);
278 ret = i915_gem_object_get_pages(obj, 0);
282 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
287 obj_priv = obj->driver_private;
288 offset = args->offset;
291 /* Operation in this page
293 * page_base = page offset within aperture
294 * page_offset = offset within page
295 * page_length = bytes to copy for this page
297 page_base = (offset & ~(PAGE_SIZE-1));
298 page_offset = offset & (PAGE_SIZE-1);
299 page_length = remain;
300 if ((page_offset + remain) > PAGE_SIZE)
301 page_length = PAGE_SIZE - page_offset;
303 ret = fast_shmem_read(obj_priv->pages,
304 page_base, page_offset,
305 user_data, page_length);
309 remain -= page_length;
310 user_data += page_length;
311 offset += page_length;
315 i915_gem_object_put_pages(obj);
317 mutex_unlock(&dev->struct_mutex);
323 i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
327 ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
329 /* If we've insufficient memory to map in the pages, attempt
330 * to make some space by throwing out some old buffers.
332 if (ret == -ENOMEM) {
333 struct drm_device *dev = obj->dev;
335 ret = i915_gem_evict_something(dev, obj->size);
339 ret = i915_gem_object_get_pages(obj, 0);
346 * This is the fallback shmem pread path, which allocates temporary storage
347 * in kernel space to copy_to_user into outside of the struct_mutex, so we
348 * can copy out of the object's backing pages while holding the struct mutex
349 * and not take page faults.
352 i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
353 struct drm_i915_gem_pread *args,
354 struct drm_file *file_priv)
356 struct drm_i915_gem_object *obj_priv = obj->driver_private;
357 struct mm_struct *mm = current->mm;
358 struct page **user_pages;
360 loff_t offset, pinned_pages, i;
361 loff_t first_data_page, last_data_page, num_pages;
362 int shmem_page_index, shmem_page_offset;
363 int data_page_index, data_page_offset;
366 uint64_t data_ptr = args->data_ptr;
367 int do_bit17_swizzling;
371 /* Pin the user pages containing the data. We can't fault while
372 * holding the struct mutex, yet we want to hold it while
373 * dereferencing the user data.
375 first_data_page = data_ptr / PAGE_SIZE;
376 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
377 num_pages = last_data_page - first_data_page + 1;
379 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
380 if (user_pages == NULL)
383 down_read(&mm->mmap_sem);
384 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
385 num_pages, 1, 0, user_pages, NULL);
386 up_read(&mm->mmap_sem);
387 if (pinned_pages < num_pages) {
389 goto fail_put_user_pages;
392 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
394 mutex_lock(&dev->struct_mutex);
396 ret = i915_gem_object_get_pages_or_evict(obj);
400 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
405 obj_priv = obj->driver_private;
406 offset = args->offset;
409 /* Operation in this page
411 * shmem_page_index = page number within shmem file
412 * shmem_page_offset = offset within page in shmem file
413 * data_page_index = page number in get_user_pages return
414 * data_page_offset = offset with data_page_index page.
415 * page_length = bytes to copy for this page
417 shmem_page_index = offset / PAGE_SIZE;
418 shmem_page_offset = offset & ~PAGE_MASK;
419 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
420 data_page_offset = data_ptr & ~PAGE_MASK;
422 page_length = remain;
423 if ((shmem_page_offset + page_length) > PAGE_SIZE)
424 page_length = PAGE_SIZE - shmem_page_offset;
425 if ((data_page_offset + page_length) > PAGE_SIZE)
426 page_length = PAGE_SIZE - data_page_offset;
428 if (do_bit17_swizzling) {
429 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
431 user_pages[data_page_index],
436 ret = slow_shmem_copy(user_pages[data_page_index],
438 obj_priv->pages[shmem_page_index],
445 remain -= page_length;
446 data_ptr += page_length;
447 offset += page_length;
451 i915_gem_object_put_pages(obj);
453 mutex_unlock(&dev->struct_mutex);
455 for (i = 0; i < pinned_pages; i++) {
456 SetPageDirty(user_pages[i]);
457 page_cache_release(user_pages[i]);
459 drm_free_large(user_pages);
465 * Reads data from the object referenced by handle.
467 * On error, the contents of *data are undefined.
470 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
471 struct drm_file *file_priv)
473 struct drm_i915_gem_pread *args = data;
474 struct drm_gem_object *obj;
475 struct drm_i915_gem_object *obj_priv;
478 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
481 obj_priv = obj->driver_private;
483 /* Bounds check source.
485 * XXX: This could use review for overflow issues...
487 if (args->offset > obj->size || args->size > obj->size ||
488 args->offset + args->size > obj->size) {
489 drm_gem_object_unreference_unlocked(obj);
493 if (i915_gem_object_needs_bit17_swizzle(obj)) {
494 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
496 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
498 ret = i915_gem_shmem_pread_slow(dev, obj, args,
502 drm_gem_object_unreference_unlocked(obj);
507 /* This is the fast write path which cannot handle
508 * page faults in the source data
512 fast_user_write(struct io_mapping *mapping,
513 loff_t page_base, int page_offset,
514 char __user *user_data,
518 unsigned long unwritten;
520 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
521 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
523 io_mapping_unmap_atomic(vaddr_atomic);
529 /* Here's the write path which can sleep for
534 slow_kernel_write(struct io_mapping *mapping,
535 loff_t gtt_base, int gtt_offset,
536 struct page *user_page, int user_offset,
539 char *src_vaddr, *dst_vaddr;
540 unsigned long unwritten;
542 dst_vaddr = io_mapping_map_atomic_wc(mapping, gtt_base);
543 src_vaddr = kmap_atomic(user_page, KM_USER1);
544 unwritten = __copy_from_user_inatomic_nocache(dst_vaddr + gtt_offset,
545 src_vaddr + user_offset,
547 kunmap_atomic(src_vaddr, KM_USER1);
548 io_mapping_unmap_atomic(dst_vaddr);
555 fast_shmem_write(struct page **pages,
556 loff_t page_base, int page_offset,
561 unsigned long unwritten;
563 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
566 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
567 kunmap_atomic(vaddr, KM_USER0);
575 * This is the fast pwrite path, where we copy the data directly from the
576 * user into the GTT, uncached.
579 i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
580 struct drm_i915_gem_pwrite *args,
581 struct drm_file *file_priv)
583 struct drm_i915_gem_object *obj_priv = obj->driver_private;
584 drm_i915_private_t *dev_priv = dev->dev_private;
586 loff_t offset, page_base;
587 char __user *user_data;
588 int page_offset, page_length;
591 user_data = (char __user *) (uintptr_t) args->data_ptr;
593 if (!access_ok(VERIFY_READ, user_data, remain))
597 mutex_lock(&dev->struct_mutex);
598 ret = i915_gem_object_pin(obj, 0);
600 mutex_unlock(&dev->struct_mutex);
603 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
607 obj_priv = obj->driver_private;
608 offset = obj_priv->gtt_offset + args->offset;
611 /* Operation in this page
613 * page_base = page offset within aperture
614 * page_offset = offset within page
615 * page_length = bytes to copy for this page
617 page_base = (offset & ~(PAGE_SIZE-1));
618 page_offset = offset & (PAGE_SIZE-1);
619 page_length = remain;
620 if ((page_offset + remain) > PAGE_SIZE)
621 page_length = PAGE_SIZE - page_offset;
623 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
624 page_offset, user_data, page_length);
626 /* If we get a fault while copying data, then (presumably) our
627 * source page isn't available. Return the error and we'll
628 * retry in the slow path.
633 remain -= page_length;
634 user_data += page_length;
635 offset += page_length;
639 i915_gem_object_unpin(obj);
640 mutex_unlock(&dev->struct_mutex);
646 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
647 * the memory and maps it using kmap_atomic for copying.
649 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
650 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
653 i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
654 struct drm_i915_gem_pwrite *args,
655 struct drm_file *file_priv)
657 struct drm_i915_gem_object *obj_priv = obj->driver_private;
658 drm_i915_private_t *dev_priv = dev->dev_private;
660 loff_t gtt_page_base, offset;
661 loff_t first_data_page, last_data_page, num_pages;
662 loff_t pinned_pages, i;
663 struct page **user_pages;
664 struct mm_struct *mm = current->mm;
665 int gtt_page_offset, data_page_offset, data_page_index, page_length;
667 uint64_t data_ptr = args->data_ptr;
671 /* Pin the user pages containing the data. We can't fault while
672 * holding the struct mutex, and all of the pwrite implementations
673 * want to hold it while dereferencing the user data.
675 first_data_page = data_ptr / PAGE_SIZE;
676 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
677 num_pages = last_data_page - first_data_page + 1;
679 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
680 if (user_pages == NULL)
683 down_read(&mm->mmap_sem);
684 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
685 num_pages, 0, 0, user_pages, NULL);
686 up_read(&mm->mmap_sem);
687 if (pinned_pages < num_pages) {
689 goto out_unpin_pages;
692 mutex_lock(&dev->struct_mutex);
693 ret = i915_gem_object_pin(obj, 0);
697 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
699 goto out_unpin_object;
701 obj_priv = obj->driver_private;
702 offset = obj_priv->gtt_offset + args->offset;
705 /* Operation in this page
707 * gtt_page_base = page offset within aperture
708 * gtt_page_offset = offset within page in aperture
709 * data_page_index = page number in get_user_pages return
710 * data_page_offset = offset with data_page_index page.
711 * page_length = bytes to copy for this page
713 gtt_page_base = offset & PAGE_MASK;
714 gtt_page_offset = offset & ~PAGE_MASK;
715 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
716 data_page_offset = data_ptr & ~PAGE_MASK;
718 page_length = remain;
719 if ((gtt_page_offset + page_length) > PAGE_SIZE)
720 page_length = PAGE_SIZE - gtt_page_offset;
721 if ((data_page_offset + page_length) > PAGE_SIZE)
722 page_length = PAGE_SIZE - data_page_offset;
724 ret = slow_kernel_write(dev_priv->mm.gtt_mapping,
725 gtt_page_base, gtt_page_offset,
726 user_pages[data_page_index],
730 /* If we get a fault while copying data, then (presumably) our
731 * source page isn't available. Return the error and we'll
732 * retry in the slow path.
735 goto out_unpin_object;
737 remain -= page_length;
738 offset += page_length;
739 data_ptr += page_length;
743 i915_gem_object_unpin(obj);
745 mutex_unlock(&dev->struct_mutex);
747 for (i = 0; i < pinned_pages; i++)
748 page_cache_release(user_pages[i]);
749 drm_free_large(user_pages);
755 * This is the fast shmem pwrite path, which attempts to directly
756 * copy_from_user into the kmapped pages backing the object.
759 i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
760 struct drm_i915_gem_pwrite *args,
761 struct drm_file *file_priv)
763 struct drm_i915_gem_object *obj_priv = obj->driver_private;
765 loff_t offset, page_base;
766 char __user *user_data;
767 int page_offset, page_length;
770 user_data = (char __user *) (uintptr_t) args->data_ptr;
773 mutex_lock(&dev->struct_mutex);
775 ret = i915_gem_object_get_pages(obj, 0);
779 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
783 obj_priv = obj->driver_private;
784 offset = args->offset;
788 /* Operation in this page
790 * page_base = page offset within aperture
791 * page_offset = offset within page
792 * page_length = bytes to copy for this page
794 page_base = (offset & ~(PAGE_SIZE-1));
795 page_offset = offset & (PAGE_SIZE-1);
796 page_length = remain;
797 if ((page_offset + remain) > PAGE_SIZE)
798 page_length = PAGE_SIZE - page_offset;
800 ret = fast_shmem_write(obj_priv->pages,
801 page_base, page_offset,
802 user_data, page_length);
806 remain -= page_length;
807 user_data += page_length;
808 offset += page_length;
812 i915_gem_object_put_pages(obj);
814 mutex_unlock(&dev->struct_mutex);
820 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
821 * the memory and maps it using kmap_atomic for copying.
823 * This avoids taking mmap_sem for faulting on the user's address while the
824 * struct_mutex is held.
827 i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
828 struct drm_i915_gem_pwrite *args,
829 struct drm_file *file_priv)
831 struct drm_i915_gem_object *obj_priv = obj->driver_private;
832 struct mm_struct *mm = current->mm;
833 struct page **user_pages;
835 loff_t offset, pinned_pages, i;
836 loff_t first_data_page, last_data_page, num_pages;
837 int shmem_page_index, shmem_page_offset;
838 int data_page_index, data_page_offset;
841 uint64_t data_ptr = args->data_ptr;
842 int do_bit17_swizzling;
846 /* Pin the user pages containing the data. We can't fault while
847 * holding the struct mutex, and all of the pwrite implementations
848 * want to hold it while dereferencing the user data.
850 first_data_page = data_ptr / PAGE_SIZE;
851 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
852 num_pages = last_data_page - first_data_page + 1;
854 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
855 if (user_pages == NULL)
858 down_read(&mm->mmap_sem);
859 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
860 num_pages, 0, 0, user_pages, NULL);
861 up_read(&mm->mmap_sem);
862 if (pinned_pages < num_pages) {
864 goto fail_put_user_pages;
867 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
869 mutex_lock(&dev->struct_mutex);
871 ret = i915_gem_object_get_pages_or_evict(obj);
875 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
879 obj_priv = obj->driver_private;
880 offset = args->offset;
884 /* Operation in this page
886 * shmem_page_index = page number within shmem file
887 * shmem_page_offset = offset within page in shmem file
888 * data_page_index = page number in get_user_pages return
889 * data_page_offset = offset with data_page_index page.
890 * page_length = bytes to copy for this page
892 shmem_page_index = offset / PAGE_SIZE;
893 shmem_page_offset = offset & ~PAGE_MASK;
894 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
895 data_page_offset = data_ptr & ~PAGE_MASK;
897 page_length = remain;
898 if ((shmem_page_offset + page_length) > PAGE_SIZE)
899 page_length = PAGE_SIZE - shmem_page_offset;
900 if ((data_page_offset + page_length) > PAGE_SIZE)
901 page_length = PAGE_SIZE - data_page_offset;
903 if (do_bit17_swizzling) {
904 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
906 user_pages[data_page_index],
911 ret = slow_shmem_copy(obj_priv->pages[shmem_page_index],
913 user_pages[data_page_index],
920 remain -= page_length;
921 data_ptr += page_length;
922 offset += page_length;
926 i915_gem_object_put_pages(obj);
928 mutex_unlock(&dev->struct_mutex);
930 for (i = 0; i < pinned_pages; i++)
931 page_cache_release(user_pages[i]);
932 drm_free_large(user_pages);
938 * Writes data to the object referenced by handle.
940 * On error, the contents of the buffer that were to be modified are undefined.
943 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
944 struct drm_file *file_priv)
946 struct drm_i915_gem_pwrite *args = data;
947 struct drm_gem_object *obj;
948 struct drm_i915_gem_object *obj_priv;
951 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
954 obj_priv = obj->driver_private;
956 /* Bounds check destination.
958 * XXX: This could use review for overflow issues...
960 if (args->offset > obj->size || args->size > obj->size ||
961 args->offset + args->size > obj->size) {
962 drm_gem_object_unreference_unlocked(obj);
966 /* We can only do the GTT pwrite on untiled buffers, as otherwise
967 * it would end up going through the fenced access, and we'll get
968 * different detiling behavior between reading and writing.
969 * pread/pwrite currently are reading and writing from the CPU
970 * perspective, requiring manual detiling by the client.
972 if (obj_priv->phys_obj)
973 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
974 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
975 dev->gtt_total != 0) {
976 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
977 if (ret == -EFAULT) {
978 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
981 } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
982 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
984 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
985 if (ret == -EFAULT) {
986 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
993 DRM_INFO("pwrite failed %d\n", ret);
996 drm_gem_object_unreference_unlocked(obj);
1002 * Called when user space prepares to use an object with the CPU, either
1003 * through the mmap ioctl's mapping or a GTT mapping.
1006 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1007 struct drm_file *file_priv)
1009 struct drm_i915_private *dev_priv = dev->dev_private;
1010 struct drm_i915_gem_set_domain *args = data;
1011 struct drm_gem_object *obj;
1012 struct drm_i915_gem_object *obj_priv;
1013 uint32_t read_domains = args->read_domains;
1014 uint32_t write_domain = args->write_domain;
1017 if (!(dev->driver->driver_features & DRIVER_GEM))
1020 /* Only handle setting domains to types used by the CPU. */
1021 if (write_domain & I915_GEM_GPU_DOMAINS)
1024 if (read_domains & I915_GEM_GPU_DOMAINS)
1027 /* Having something in the write domain implies it's in the read
1028 * domain, and only that read domain. Enforce that in the request.
1030 if (write_domain != 0 && read_domains != write_domain)
1033 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1036 obj_priv = obj->driver_private;
1038 mutex_lock(&dev->struct_mutex);
1040 intel_mark_busy(dev, obj);
1043 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1044 obj, obj->size, read_domains, write_domain);
1046 if (read_domains & I915_GEM_DOMAIN_GTT) {
1047 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1049 /* Update the LRU on the fence for the CPU access that's
1052 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1053 list_move_tail(&obj_priv->fence_list,
1054 &dev_priv->mm.fence_list);
1057 /* Silently promote "you're not bound, there was nothing to do"
1058 * to success, since the client was just asking us to
1059 * make sure everything was done.
1064 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1067 drm_gem_object_unreference(obj);
1068 mutex_unlock(&dev->struct_mutex);
1073 * Called when user space has done writes to this buffer
1076 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1077 struct drm_file *file_priv)
1079 struct drm_i915_gem_sw_finish *args = data;
1080 struct drm_gem_object *obj;
1081 struct drm_i915_gem_object *obj_priv;
1084 if (!(dev->driver->driver_features & DRIVER_GEM))
1087 mutex_lock(&dev->struct_mutex);
1088 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1090 mutex_unlock(&dev->struct_mutex);
1095 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1096 __func__, args->handle, obj, obj->size);
1098 obj_priv = obj->driver_private;
1100 /* Pinned buffers may be scanout, so flush the cache */
1101 if (obj_priv->pin_count)
1102 i915_gem_object_flush_cpu_write_domain(obj);
1104 drm_gem_object_unreference(obj);
1105 mutex_unlock(&dev->struct_mutex);
1110 * Maps the contents of an object, returning the address it is mapped
1113 * While the mapping holds a reference on the contents of the object, it doesn't
1114 * imply a ref on the object itself.
1117 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1118 struct drm_file *file_priv)
1120 struct drm_i915_gem_mmap *args = data;
1121 struct drm_gem_object *obj;
1125 if (!(dev->driver->driver_features & DRIVER_GEM))
1128 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1132 offset = args->offset;
1134 down_write(¤t->mm->mmap_sem);
1135 addr = do_mmap(obj->filp, 0, args->size,
1136 PROT_READ | PROT_WRITE, MAP_SHARED,
1138 up_write(¤t->mm->mmap_sem);
1139 drm_gem_object_unreference_unlocked(obj);
1140 if (IS_ERR((void *)addr))
1143 args->addr_ptr = (uint64_t) addr;
1149 * i915_gem_fault - fault a page into the GTT
1150 * vma: VMA in question
1153 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1154 * from userspace. The fault handler takes care of binding the object to
1155 * the GTT (if needed), allocating and programming a fence register (again,
1156 * only if needed based on whether the old reg is still valid or the object
1157 * is tiled) and inserting a new PTE into the faulting process.
1159 * Note that the faulting process may involve evicting existing objects
1160 * from the GTT and/or fence registers to make room. So performance may
1161 * suffer if the GTT working set is large or there are few fence registers
1164 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1166 struct drm_gem_object *obj = vma->vm_private_data;
1167 struct drm_device *dev = obj->dev;
1168 struct drm_i915_private *dev_priv = dev->dev_private;
1169 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1170 pgoff_t page_offset;
1173 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1175 /* We don't use vmf->pgoff since that has the fake offset */
1176 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1179 /* Now bind it into the GTT if needed */
1180 mutex_lock(&dev->struct_mutex);
1181 if (!obj_priv->gtt_space) {
1182 ret = i915_gem_object_bind_to_gtt(obj, 0);
1186 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1188 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1193 /* Need a new fence register? */
1194 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1195 ret = i915_gem_object_get_fence_reg(obj);
1200 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1203 /* Finally, remap it using the new GTT offset */
1204 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1206 mutex_unlock(&dev->struct_mutex);
1211 return VM_FAULT_NOPAGE;
1214 return VM_FAULT_OOM;
1216 return VM_FAULT_SIGBUS;
1221 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1222 * @obj: obj in question
1224 * GEM memory mapping works by handing back to userspace a fake mmap offset
1225 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1226 * up the object based on the offset and sets up the various memory mapping
1229 * This routine allocates and attaches a fake offset for @obj.
1232 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1234 struct drm_device *dev = obj->dev;
1235 struct drm_gem_mm *mm = dev->mm_private;
1236 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1237 struct drm_map_list *list;
1238 struct drm_local_map *map;
1241 /* Set the object up for mmap'ing */
1242 list = &obj->map_list;
1243 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1248 map->type = _DRM_GEM;
1249 map->size = obj->size;
1252 /* Get a DRM GEM mmap offset allocated... */
1253 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1254 obj->size / PAGE_SIZE, 0, 0);
1255 if (!list->file_offset_node) {
1256 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1261 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1262 obj->size / PAGE_SIZE, 0);
1263 if (!list->file_offset_node) {
1268 list->hash.key = list->file_offset_node->start;
1269 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1270 DRM_ERROR("failed to add to map hash\n");
1275 /* By now we should be all set, any drm_mmap request on the offset
1276 * below will get to our mmap & fault handler */
1277 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1282 drm_mm_put_block(list->file_offset_node);
1290 * i915_gem_release_mmap - remove physical page mappings
1291 * @obj: obj in question
1293 * Preserve the reservation of the mmapping with the DRM core code, but
1294 * relinquish ownership of the pages back to the system.
1296 * It is vital that we remove the page mapping if we have mapped a tiled
1297 * object through the GTT and then lose the fence register due to
1298 * resource pressure. Similarly if the object has been moved out of the
1299 * aperture, than pages mapped into userspace must be revoked. Removing the
1300 * mapping will then trigger a page fault on the next user access, allowing
1301 * fixup by i915_gem_fault().
1304 i915_gem_release_mmap(struct drm_gem_object *obj)
1306 struct drm_device *dev = obj->dev;
1307 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1309 if (dev->dev_mapping)
1310 unmap_mapping_range(dev->dev_mapping,
1311 obj_priv->mmap_offset, obj->size, 1);
1315 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1317 struct drm_device *dev = obj->dev;
1318 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1319 struct drm_gem_mm *mm = dev->mm_private;
1320 struct drm_map_list *list;
1322 list = &obj->map_list;
1323 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1325 if (list->file_offset_node) {
1326 drm_mm_put_block(list->file_offset_node);
1327 list->file_offset_node = NULL;
1335 obj_priv->mmap_offset = 0;
1339 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1340 * @obj: object to check
1342 * Return the required GTT alignment for an object, taking into account
1343 * potential fence register mapping if needed.
1346 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1348 struct drm_device *dev = obj->dev;
1349 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1353 * Minimum alignment is 4k (GTT page size), but might be greater
1354 * if a fence register is needed for the object.
1356 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1360 * Previous chips need to be aligned to the size of the smallest
1361 * fence register that can contain the object.
1368 for (i = start; i < obj->size; i <<= 1)
1375 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1377 * @data: GTT mapping ioctl data
1378 * @file_priv: GEM object info
1380 * Simply returns the fake offset to userspace so it can mmap it.
1381 * The mmap call will end up in drm_gem_mmap(), which will set things
1382 * up so we can get faults in the handler above.
1384 * The fault handler will take care of binding the object into the GTT
1385 * (since it may have been evicted to make room for something), allocating
1386 * a fence register, and mapping the appropriate aperture address into
1390 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1391 struct drm_file *file_priv)
1393 struct drm_i915_gem_mmap_gtt *args = data;
1394 struct drm_i915_private *dev_priv = dev->dev_private;
1395 struct drm_gem_object *obj;
1396 struct drm_i915_gem_object *obj_priv;
1399 if (!(dev->driver->driver_features & DRIVER_GEM))
1402 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1406 mutex_lock(&dev->struct_mutex);
1408 obj_priv = obj->driver_private;
1410 if (obj_priv->madv != I915_MADV_WILLNEED) {
1411 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1412 drm_gem_object_unreference(obj);
1413 mutex_unlock(&dev->struct_mutex);
1418 if (!obj_priv->mmap_offset) {
1419 ret = i915_gem_create_mmap_offset(obj);
1421 drm_gem_object_unreference(obj);
1422 mutex_unlock(&dev->struct_mutex);
1427 args->offset = obj_priv->mmap_offset;
1430 * Pull it into the GTT so that we have a page list (makes the
1431 * initial fault faster and any subsequent flushing possible).
1433 if (!obj_priv->agp_mem) {
1434 ret = i915_gem_object_bind_to_gtt(obj, 0);
1436 drm_gem_object_unreference(obj);
1437 mutex_unlock(&dev->struct_mutex);
1440 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1443 drm_gem_object_unreference(obj);
1444 mutex_unlock(&dev->struct_mutex);
1450 i915_gem_object_put_pages(struct drm_gem_object *obj)
1452 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1453 int page_count = obj->size / PAGE_SIZE;
1456 BUG_ON(obj_priv->pages_refcount == 0);
1457 BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
1459 if (--obj_priv->pages_refcount != 0)
1462 if (obj_priv->tiling_mode != I915_TILING_NONE)
1463 i915_gem_object_save_bit_17_swizzle(obj);
1465 if (obj_priv->madv == I915_MADV_DONTNEED)
1466 obj_priv->dirty = 0;
1468 for (i = 0; i < page_count; i++) {
1469 if (obj_priv->pages[i] == NULL)
1472 if (obj_priv->dirty)
1473 set_page_dirty(obj_priv->pages[i]);
1475 if (obj_priv->madv == I915_MADV_WILLNEED)
1476 mark_page_accessed(obj_priv->pages[i]);
1478 page_cache_release(obj_priv->pages[i]);
1480 obj_priv->dirty = 0;
1482 drm_free_large(obj_priv->pages);
1483 obj_priv->pages = NULL;
1487 i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
1489 struct drm_device *dev = obj->dev;
1490 drm_i915_private_t *dev_priv = dev->dev_private;
1491 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1493 /* Add a reference if we're newly entering the active list. */
1494 if (!obj_priv->active) {
1495 drm_gem_object_reference(obj);
1496 obj_priv->active = 1;
1498 /* Move from whatever list we were on to the tail of execution. */
1499 spin_lock(&dev_priv->mm.active_list_lock);
1500 list_move_tail(&obj_priv->list,
1501 &dev_priv->mm.active_list);
1502 spin_unlock(&dev_priv->mm.active_list_lock);
1503 obj_priv->last_rendering_seqno = seqno;
1507 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1509 struct drm_device *dev = obj->dev;
1510 drm_i915_private_t *dev_priv = dev->dev_private;
1511 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1513 BUG_ON(!obj_priv->active);
1514 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1515 obj_priv->last_rendering_seqno = 0;
1518 /* Immediately discard the backing storage */
1520 i915_gem_object_truncate(struct drm_gem_object *obj)
1522 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1523 struct inode *inode;
1525 inode = obj->filp->f_path.dentry->d_inode;
1526 if (inode->i_op->truncate)
1527 inode->i_op->truncate (inode);
1529 obj_priv->madv = __I915_MADV_PURGED;
1533 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1535 return obj_priv->madv == I915_MADV_DONTNEED;
1539 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1541 struct drm_device *dev = obj->dev;
1542 drm_i915_private_t *dev_priv = dev->dev_private;
1543 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1545 i915_verify_inactive(dev, __FILE__, __LINE__);
1546 if (obj_priv->pin_count != 0)
1547 list_del_init(&obj_priv->list);
1549 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1551 BUG_ON(!list_empty(&obj_priv->gpu_write_list));
1553 obj_priv->last_rendering_seqno = 0;
1554 if (obj_priv->active) {
1555 obj_priv->active = 0;
1556 drm_gem_object_unreference(obj);
1558 i915_verify_inactive(dev, __FILE__, __LINE__);
1562 * Creates a new sequence number, emitting a write of it to the status page
1563 * plus an interrupt, which will trigger i915_user_interrupt_handler.
1565 * Must be called with struct_lock held.
1567 * Returned sequence numbers are nonzero on success.
1570 i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1571 uint32_t flush_domains)
1573 drm_i915_private_t *dev_priv = dev->dev_private;
1574 struct drm_i915_file_private *i915_file_priv = NULL;
1575 struct drm_i915_gem_request *request;
1580 if (file_priv != NULL)
1581 i915_file_priv = file_priv->driver_priv;
1583 request = kzalloc(sizeof(*request), GFP_KERNEL);
1584 if (request == NULL)
1587 /* Grab the seqno we're going to make this request be, and bump the
1588 * next (skipping 0 so it can be the reserved no-seqno value).
1590 seqno = dev_priv->mm.next_gem_seqno;
1591 dev_priv->mm.next_gem_seqno++;
1592 if (dev_priv->mm.next_gem_seqno == 0)
1593 dev_priv->mm.next_gem_seqno++;
1596 OUT_RING(MI_STORE_DWORD_INDEX);
1597 OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1600 OUT_RING(MI_USER_INTERRUPT);
1603 DRM_DEBUG_DRIVER("%d\n", seqno);
1605 request->seqno = seqno;
1606 request->emitted_jiffies = jiffies;
1607 was_empty = list_empty(&dev_priv->mm.request_list);
1608 list_add_tail(&request->list, &dev_priv->mm.request_list);
1609 if (i915_file_priv) {
1610 list_add_tail(&request->client_list,
1611 &i915_file_priv->mm.request_list);
1613 INIT_LIST_HEAD(&request->client_list);
1616 /* Associate any objects on the flushing list matching the write
1617 * domain we're flushing with our flush.
1619 if (flush_domains != 0) {
1620 struct drm_i915_gem_object *obj_priv, *next;
1622 list_for_each_entry_safe(obj_priv, next,
1623 &dev_priv->mm.gpu_write_list,
1625 struct drm_gem_object *obj = obj_priv->obj;
1627 if ((obj->write_domain & flush_domains) ==
1628 obj->write_domain) {
1629 uint32_t old_write_domain = obj->write_domain;
1631 obj->write_domain = 0;
1632 list_del_init(&obj_priv->gpu_write_list);
1633 i915_gem_object_move_to_active(obj, seqno);
1635 trace_i915_gem_object_change_domain(obj,
1643 if (!dev_priv->mm.suspended) {
1644 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1646 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1652 * Command execution barrier
1654 * Ensures that all commands in the ring are finished
1655 * before signalling the CPU
1658 i915_retire_commands(struct drm_device *dev)
1660 drm_i915_private_t *dev_priv = dev->dev_private;
1661 uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1662 uint32_t flush_domains = 0;
1665 /* The sampler always gets flushed on i965 (sigh) */
1667 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1670 OUT_RING(0); /* noop */
1672 return flush_domains;
1676 * Moves buffers associated only with the given active seqno from the active
1677 * to inactive list, potentially freeing them.
1680 i915_gem_retire_request(struct drm_device *dev,
1681 struct drm_i915_gem_request *request)
1683 drm_i915_private_t *dev_priv = dev->dev_private;
1685 trace_i915_gem_request_retire(dev, request->seqno);
1687 /* Move any buffers on the active list that are no longer referenced
1688 * by the ringbuffer to the flushing/inactive lists as appropriate.
1690 spin_lock(&dev_priv->mm.active_list_lock);
1691 while (!list_empty(&dev_priv->mm.active_list)) {
1692 struct drm_gem_object *obj;
1693 struct drm_i915_gem_object *obj_priv;
1695 obj_priv = list_first_entry(&dev_priv->mm.active_list,
1696 struct drm_i915_gem_object,
1698 obj = obj_priv->obj;
1700 /* If the seqno being retired doesn't match the oldest in the
1701 * list, then the oldest in the list must still be newer than
1704 if (obj_priv->last_rendering_seqno != request->seqno)
1708 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1709 __func__, request->seqno, obj);
1712 if (obj->write_domain != 0)
1713 i915_gem_object_move_to_flushing(obj);
1715 /* Take a reference on the object so it won't be
1716 * freed while the spinlock is held. The list
1717 * protection for this spinlock is safe when breaking
1718 * the lock like this since the next thing we do
1719 * is just get the head of the list again.
1721 drm_gem_object_reference(obj);
1722 i915_gem_object_move_to_inactive(obj);
1723 spin_unlock(&dev_priv->mm.active_list_lock);
1724 drm_gem_object_unreference(obj);
1725 spin_lock(&dev_priv->mm.active_list_lock);
1729 spin_unlock(&dev_priv->mm.active_list_lock);
1733 * Returns true if seq1 is later than seq2.
1736 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1738 return (int32_t)(seq1 - seq2) >= 0;
1742 i915_get_gem_seqno(struct drm_device *dev)
1744 drm_i915_private_t *dev_priv = dev->dev_private;
1746 return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
1750 * This function clears the request list as sequence numbers are passed.
1753 i915_gem_retire_requests(struct drm_device *dev)
1755 drm_i915_private_t *dev_priv = dev->dev_private;
1758 if (!dev_priv->hw_status_page || list_empty(&dev_priv->mm.request_list))
1761 seqno = i915_get_gem_seqno(dev);
1763 while (!list_empty(&dev_priv->mm.request_list)) {
1764 struct drm_i915_gem_request *request;
1765 uint32_t retiring_seqno;
1767 request = list_first_entry(&dev_priv->mm.request_list,
1768 struct drm_i915_gem_request,
1770 retiring_seqno = request->seqno;
1772 if (i915_seqno_passed(seqno, retiring_seqno) ||
1773 atomic_read(&dev_priv->mm.wedged)) {
1774 i915_gem_retire_request(dev, request);
1776 list_del(&request->list);
1777 list_del(&request->client_list);
1783 if (unlikely (dev_priv->trace_irq_seqno &&
1784 i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
1785 i915_user_irq_put(dev);
1786 dev_priv->trace_irq_seqno = 0;
1791 i915_gem_retire_work_handler(struct work_struct *work)
1793 drm_i915_private_t *dev_priv;
1794 struct drm_device *dev;
1796 dev_priv = container_of(work, drm_i915_private_t,
1797 mm.retire_work.work);
1798 dev = dev_priv->dev;
1800 mutex_lock(&dev->struct_mutex);
1801 i915_gem_retire_requests(dev);
1802 if (!dev_priv->mm.suspended &&
1803 !list_empty(&dev_priv->mm.request_list))
1804 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1805 mutex_unlock(&dev->struct_mutex);
1809 i915_do_wait_request(struct drm_device *dev, uint32_t seqno, int interruptible)
1811 drm_i915_private_t *dev_priv = dev->dev_private;
1817 if (atomic_read(&dev_priv->mm.wedged))
1820 if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
1821 if (HAS_PCH_SPLIT(dev))
1822 ier = I915_READ(DEIER) | I915_READ(GTIER);
1824 ier = I915_READ(IER);
1826 DRM_ERROR("something (likely vbetool) disabled "
1827 "interrupts, re-enabling\n");
1828 i915_driver_irq_preinstall(dev);
1829 i915_driver_irq_postinstall(dev);
1832 trace_i915_gem_request_wait_begin(dev, seqno);
1834 dev_priv->mm.waiting_gem_seqno = seqno;
1835 i915_user_irq_get(dev);
1837 ret = wait_event_interruptible(dev_priv->irq_queue,
1838 i915_seqno_passed(i915_get_gem_seqno(dev), seqno) ||
1839 atomic_read(&dev_priv->mm.wedged));
1841 wait_event(dev_priv->irq_queue,
1842 i915_seqno_passed(i915_get_gem_seqno(dev), seqno) ||
1843 atomic_read(&dev_priv->mm.wedged));
1845 i915_user_irq_put(dev);
1846 dev_priv->mm.waiting_gem_seqno = 0;
1848 trace_i915_gem_request_wait_end(dev, seqno);
1850 if (atomic_read(&dev_priv->mm.wedged))
1853 if (ret && ret != -ERESTARTSYS)
1854 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1855 __func__, ret, seqno, i915_get_gem_seqno(dev));
1857 /* Directly dispatch request retiring. While we have the work queue
1858 * to handle this, the waiter on a request often wants an associated
1859 * buffer to have made it to the inactive list, and we would need
1860 * a separate wait queue to handle that.
1863 i915_gem_retire_requests(dev);
1869 * Waits for a sequence number to be signaled, and cleans up the
1870 * request and object lists appropriately for that event.
1873 i915_wait_request(struct drm_device *dev, uint32_t seqno)
1875 return i915_do_wait_request(dev, seqno, 1);
1879 i915_gem_flush(struct drm_device *dev,
1880 uint32_t invalidate_domains,
1881 uint32_t flush_domains)
1883 drm_i915_private_t *dev_priv = dev->dev_private;
1888 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
1889 invalidate_domains, flush_domains);
1891 trace_i915_gem_request_flush(dev, dev_priv->mm.next_gem_seqno,
1892 invalidate_domains, flush_domains);
1894 if (flush_domains & I915_GEM_DOMAIN_CPU)
1895 drm_agp_chipset_flush(dev);
1897 if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
1899 * read/write caches:
1901 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1902 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
1903 * also flushed at 2d versus 3d pipeline switches.
1907 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1908 * MI_READ_FLUSH is set, and is always flushed on 965.
1910 * I915_GEM_DOMAIN_COMMAND may not exist?
1912 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1913 * invalidated when MI_EXE_FLUSH is set.
1915 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1916 * invalidated with every MI_FLUSH.
1920 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1921 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1922 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1923 * are flushed at any MI_FLUSH.
1926 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1927 if ((invalidate_domains|flush_domains) &
1928 I915_GEM_DOMAIN_RENDER)
1929 cmd &= ~MI_NO_WRITE_FLUSH;
1930 if (!IS_I965G(dev)) {
1932 * On the 965, the sampler cache always gets flushed
1933 * and this bit is reserved.
1935 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
1936 cmd |= MI_READ_FLUSH;
1938 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
1939 cmd |= MI_EXE_FLUSH;
1942 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
1952 * Ensures that all rendering to the object has completed and the object is
1953 * safe to unbind from the GTT or access from the CPU.
1956 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1958 struct drm_device *dev = obj->dev;
1959 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1962 /* This function only exists to support waiting for existing rendering,
1963 * not for emitting required flushes.
1965 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
1967 /* If there is rendering queued on the buffer being evicted, wait for
1970 if (obj_priv->active) {
1972 DRM_INFO("%s: object %p wait for seqno %08x\n",
1973 __func__, obj, obj_priv->last_rendering_seqno);
1975 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
1984 * Unbinds an object from the GTT aperture.
1987 i915_gem_object_unbind(struct drm_gem_object *obj)
1989 struct drm_device *dev = obj->dev;
1990 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1994 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1995 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1997 if (obj_priv->gtt_space == NULL)
2000 if (obj_priv->pin_count != 0) {
2001 DRM_ERROR("Attempting to unbind pinned buffer\n");
2005 /* blow away mappings if mapped through GTT */
2006 i915_gem_release_mmap(obj);
2008 /* Move the object to the CPU domain to ensure that
2009 * any possible CPU writes while it's not in the GTT
2010 * are flushed when we go to remap it. This will
2011 * also ensure that all pending GPU writes are finished
2014 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2016 if (ret != -ERESTARTSYS)
2017 DRM_ERROR("set_domain failed: %d\n", ret);
2021 BUG_ON(obj_priv->active);
2023 /* release the fence reg _after_ flushing */
2024 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
2025 i915_gem_clear_fence_reg(obj);
2027 if (obj_priv->agp_mem != NULL) {
2028 drm_unbind_agp(obj_priv->agp_mem);
2029 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
2030 obj_priv->agp_mem = NULL;
2033 i915_gem_object_put_pages(obj);
2034 BUG_ON(obj_priv->pages_refcount);
2036 if (obj_priv->gtt_space) {
2037 atomic_dec(&dev->gtt_count);
2038 atomic_sub(obj->size, &dev->gtt_memory);
2040 drm_mm_put_block(obj_priv->gtt_space);
2041 obj_priv->gtt_space = NULL;
2044 /* Remove ourselves from the LRU list if present. */
2045 if (!list_empty(&obj_priv->list))
2046 list_del_init(&obj_priv->list);
2048 if (i915_gem_object_is_purgeable(obj_priv))
2049 i915_gem_object_truncate(obj);
2051 trace_i915_gem_object_unbind(obj);
2056 static struct drm_gem_object *
2057 i915_gem_find_inactive_object(struct drm_device *dev, int min_size)
2059 drm_i915_private_t *dev_priv = dev->dev_private;
2060 struct drm_i915_gem_object *obj_priv;
2061 struct drm_gem_object *best = NULL;
2062 struct drm_gem_object *first = NULL;
2064 /* Try to find the smallest clean object */
2065 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
2066 struct drm_gem_object *obj = obj_priv->obj;
2067 if (obj->size >= min_size) {
2068 if ((!obj_priv->dirty ||
2069 i915_gem_object_is_purgeable(obj_priv)) &&
2070 (!best || obj->size < best->size)) {
2072 if (best->size == min_size)
2080 return best ? best : first;
2084 i915_gem_evict_everything(struct drm_device *dev)
2086 drm_i915_private_t *dev_priv = dev->dev_private;
2091 spin_lock(&dev_priv->mm.active_list_lock);
2092 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2093 list_empty(&dev_priv->mm.flushing_list) &&
2094 list_empty(&dev_priv->mm.active_list));
2095 spin_unlock(&dev_priv->mm.active_list_lock);
2100 /* Flush everything (on to the inactive lists) and evict */
2101 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2102 seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
2106 ret = i915_wait_request(dev, seqno);
2110 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2112 ret = i915_gem_evict_from_inactive_list(dev);
2116 spin_lock(&dev_priv->mm.active_list_lock);
2117 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2118 list_empty(&dev_priv->mm.flushing_list) &&
2119 list_empty(&dev_priv->mm.active_list));
2120 spin_unlock(&dev_priv->mm.active_list_lock);
2121 BUG_ON(!lists_empty);
2127 i915_gem_evict_something(struct drm_device *dev, int min_size)
2129 drm_i915_private_t *dev_priv = dev->dev_private;
2130 struct drm_gem_object *obj;
2134 i915_gem_retire_requests(dev);
2136 /* If there's an inactive buffer available now, grab it
2139 obj = i915_gem_find_inactive_object(dev, min_size);
2141 struct drm_i915_gem_object *obj_priv;
2144 DRM_INFO("%s: evicting %p\n", __func__, obj);
2146 obj_priv = obj->driver_private;
2147 BUG_ON(obj_priv->pin_count != 0);
2148 BUG_ON(obj_priv->active);
2150 /* Wait on the rendering and unbind the buffer. */
2151 return i915_gem_object_unbind(obj);
2154 /* If we didn't get anything, but the ring is still processing
2155 * things, wait for the next to finish and hopefully leave us
2156 * a buffer to evict.
2158 if (!list_empty(&dev_priv->mm.request_list)) {
2159 struct drm_i915_gem_request *request;
2161 request = list_first_entry(&dev_priv->mm.request_list,
2162 struct drm_i915_gem_request,
2165 ret = i915_wait_request(dev, request->seqno);
2172 /* If we didn't have anything on the request list but there
2173 * are buffers awaiting a flush, emit one and try again.
2174 * When we wait on it, those buffers waiting for that flush
2175 * will get moved to inactive.
2177 if (!list_empty(&dev_priv->mm.flushing_list)) {
2178 struct drm_i915_gem_object *obj_priv;
2180 /* Find an object that we can immediately reuse */
2181 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
2182 obj = obj_priv->obj;
2183 if (obj->size >= min_size)
2195 seqno = i915_add_request(dev, NULL, obj->write_domain);
2199 ret = i915_wait_request(dev, seqno);
2207 /* If we didn't do any of the above, there's no single buffer
2208 * large enough to swap out for the new one, so just evict
2209 * everything and start again. (This should be rare.)
2211 if (!list_empty (&dev_priv->mm.inactive_list))
2212 return i915_gem_evict_from_inactive_list(dev);
2214 return i915_gem_evict_everything(dev);
2219 i915_gem_object_get_pages(struct drm_gem_object *obj,
2222 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2224 struct address_space *mapping;
2225 struct inode *inode;
2229 if (obj_priv->pages_refcount++ != 0)
2232 /* Get the list of pages out of our struct file. They'll be pinned
2233 * at this point until we release them.
2235 page_count = obj->size / PAGE_SIZE;
2236 BUG_ON(obj_priv->pages != NULL);
2237 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
2238 if (obj_priv->pages == NULL) {
2239 obj_priv->pages_refcount--;
2243 inode = obj->filp->f_path.dentry->d_inode;
2244 mapping = inode->i_mapping;
2245 for (i = 0; i < page_count; i++) {
2246 page = read_cache_page_gfp(mapping, i,
2247 mapping_gfp_mask (mapping) |
2251 ret = PTR_ERR(page);
2252 i915_gem_object_put_pages(obj);
2255 obj_priv->pages[i] = page;
2258 if (obj_priv->tiling_mode != I915_TILING_NONE)
2259 i915_gem_object_do_bit_17_swizzle(obj);
2264 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2266 struct drm_gem_object *obj = reg->obj;
2267 struct drm_device *dev = obj->dev;
2268 drm_i915_private_t *dev_priv = dev->dev_private;
2269 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2270 int regnum = obj_priv->fence_reg;
2273 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2275 val |= obj_priv->gtt_offset & 0xfffff000;
2276 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2277 if (obj_priv->tiling_mode == I915_TILING_Y)
2278 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2279 val |= I965_FENCE_REG_VALID;
2281 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2284 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2286 struct drm_gem_object *obj = reg->obj;
2287 struct drm_device *dev = obj->dev;
2288 drm_i915_private_t *dev_priv = dev->dev_private;
2289 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2290 int regnum = obj_priv->fence_reg;
2292 uint32_t fence_reg, val;
2295 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2296 (obj_priv->gtt_offset & (obj->size - 1))) {
2297 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2298 __func__, obj_priv->gtt_offset, obj->size);
2302 if (obj_priv->tiling_mode == I915_TILING_Y &&
2303 HAS_128_BYTE_Y_TILING(dev))
2308 /* Note: pitch better be a power of two tile widths */
2309 pitch_val = obj_priv->stride / tile_width;
2310 pitch_val = ffs(pitch_val) - 1;
2312 val = obj_priv->gtt_offset;
2313 if (obj_priv->tiling_mode == I915_TILING_Y)
2314 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2315 val |= I915_FENCE_SIZE_BITS(obj->size);
2316 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2317 val |= I830_FENCE_REG_VALID;
2320 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2322 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2323 I915_WRITE(fence_reg, val);
2326 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2328 struct drm_gem_object *obj = reg->obj;
2329 struct drm_device *dev = obj->dev;
2330 drm_i915_private_t *dev_priv = dev->dev_private;
2331 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2332 int regnum = obj_priv->fence_reg;
2335 uint32_t fence_size_bits;
2337 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
2338 (obj_priv->gtt_offset & (obj->size - 1))) {
2339 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2340 __func__, obj_priv->gtt_offset);
2344 pitch_val = obj_priv->stride / 128;
2345 pitch_val = ffs(pitch_val) - 1;
2346 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2348 val = obj_priv->gtt_offset;
2349 if (obj_priv->tiling_mode == I915_TILING_Y)
2350 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2351 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2352 WARN_ON(fence_size_bits & ~0x00000f00);
2353 val |= fence_size_bits;
2354 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2355 val |= I830_FENCE_REG_VALID;
2357 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
2361 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2362 * @obj: object to map through a fence reg
2364 * When mapping objects through the GTT, userspace wants to be able to write
2365 * to them without having to worry about swizzling if the object is tiled.
2367 * This function walks the fence regs looking for a free one for @obj,
2368 * stealing one if it can't find any.
2370 * It then sets up the reg based on the object's properties: address, pitch
2371 * and tiling format.
2374 i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
2376 struct drm_device *dev = obj->dev;
2377 struct drm_i915_private *dev_priv = dev->dev_private;
2378 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2379 struct drm_i915_fence_reg *reg = NULL;
2380 struct drm_i915_gem_object *old_obj_priv = NULL;
2383 /* Just update our place in the LRU if our fence is getting used. */
2384 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2385 list_move_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2389 switch (obj_priv->tiling_mode) {
2390 case I915_TILING_NONE:
2391 WARN(1, "allocating a fence for non-tiled object?\n");
2394 if (!obj_priv->stride)
2396 WARN((obj_priv->stride & (512 - 1)),
2397 "object 0x%08x is X tiled but has non-512B pitch\n",
2398 obj_priv->gtt_offset);
2401 if (!obj_priv->stride)
2403 WARN((obj_priv->stride & (128 - 1)),
2404 "object 0x%08x is Y tiled but has non-128B pitch\n",
2405 obj_priv->gtt_offset);
2409 /* First try to find a free reg */
2411 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2412 reg = &dev_priv->fence_regs[i];
2416 old_obj_priv = reg->obj->driver_private;
2417 if (!old_obj_priv->pin_count)
2421 /* None available, try to steal one or wait for a user to finish */
2422 if (i == dev_priv->num_fence_regs) {
2423 struct drm_gem_object *old_obj = NULL;
2428 list_for_each_entry(old_obj_priv, &dev_priv->mm.fence_list,
2430 old_obj = old_obj_priv->obj;
2432 if (old_obj_priv->pin_count)
2435 /* Take a reference, as otherwise the wait_rendering
2436 * below may cause the object to get freed out from
2439 drm_gem_object_reference(old_obj);
2441 /* i915 uses fences for GPU access to tiled buffers */
2442 if (IS_I965G(dev) || !old_obj_priv->active)
2445 /* This brings the object to the head of the LRU if it
2446 * had been written to. The only way this should
2447 * result in us waiting longer than the expected
2448 * optimal amount of time is if there was a
2449 * fence-using buffer later that was read-only.
2451 i915_gem_object_flush_gpu_write_domain(old_obj);
2452 ret = i915_gem_object_wait_rendering(old_obj);
2454 drm_gem_object_unreference(old_obj);
2462 * Zap this virtual mapping so we can set up a fence again
2463 * for this object next time we need it.
2465 i915_gem_release_mmap(old_obj);
2467 i = old_obj_priv->fence_reg;
2468 reg = &dev_priv->fence_regs[i];
2470 old_obj_priv->fence_reg = I915_FENCE_REG_NONE;
2471 list_del_init(&old_obj_priv->fence_list);
2473 drm_gem_object_unreference(old_obj);
2476 obj_priv->fence_reg = i;
2477 list_add_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2482 i965_write_fence_reg(reg);
2483 else if (IS_I9XX(dev))
2484 i915_write_fence_reg(reg);
2486 i830_write_fence_reg(reg);
2488 trace_i915_gem_object_get_fence(obj, i, obj_priv->tiling_mode);
2494 * i915_gem_clear_fence_reg - clear out fence register info
2495 * @obj: object to clear
2497 * Zeroes out the fence register itself and clears out the associated
2498 * data structures in dev_priv and obj_priv.
2501 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2503 struct drm_device *dev = obj->dev;
2504 drm_i915_private_t *dev_priv = dev->dev_private;
2505 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2508 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
2512 if (obj_priv->fence_reg < 8)
2513 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2515 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2518 I915_WRITE(fence_reg, 0);
2521 dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL;
2522 obj_priv->fence_reg = I915_FENCE_REG_NONE;
2523 list_del_init(&obj_priv->fence_list);
2527 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2528 * to the buffer to finish, and then resets the fence register.
2529 * @obj: tiled object holding a fence register.
2531 * Zeroes out the fence register itself and clears out the associated
2532 * data structures in dev_priv and obj_priv.
2535 i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2537 struct drm_device *dev = obj->dev;
2538 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2540 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2543 /* If we've changed tiling, GTT-mappings of the object
2544 * need to re-fault to ensure that the correct fence register
2545 * setup is in place.
2547 i915_gem_release_mmap(obj);
2549 /* On the i915, GPU access to tiled buffers is via a fence,
2550 * therefore we must wait for any outstanding access to complete
2551 * before clearing the fence.
2553 if (!IS_I965G(dev)) {
2556 i915_gem_object_flush_gpu_write_domain(obj);
2557 ret = i915_gem_object_wait_rendering(obj);
2562 i915_gem_object_flush_gtt_write_domain(obj);
2563 i915_gem_clear_fence_reg (obj);
2569 * Finds free space in the GTT aperture and binds the object there.
2572 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2574 struct drm_device *dev = obj->dev;
2575 drm_i915_private_t *dev_priv = dev->dev_private;
2576 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2577 struct drm_mm_node *free_space;
2578 gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
2581 if (obj_priv->madv != I915_MADV_WILLNEED) {
2582 DRM_ERROR("Attempting to bind a purgeable object\n");
2587 alignment = i915_gem_get_gtt_alignment(obj);
2588 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
2589 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2594 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2595 obj->size, alignment, 0);
2596 if (free_space != NULL) {
2597 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2599 if (obj_priv->gtt_space != NULL) {
2600 obj_priv->gtt_space->private = obj;
2601 obj_priv->gtt_offset = obj_priv->gtt_space->start;
2604 if (obj_priv->gtt_space == NULL) {
2605 /* If the gtt is empty and we're still having trouble
2606 * fitting our object in, we're out of memory.
2609 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2611 ret = i915_gem_evict_something(dev, obj->size);
2619 DRM_INFO("Binding object of size %zd at 0x%08x\n",
2620 obj->size, obj_priv->gtt_offset);
2622 ret = i915_gem_object_get_pages(obj, gfpmask);
2624 drm_mm_put_block(obj_priv->gtt_space);
2625 obj_priv->gtt_space = NULL;
2627 if (ret == -ENOMEM) {
2628 /* first try to clear up some space from the GTT */
2629 ret = i915_gem_evict_something(dev, obj->size);
2631 /* now try to shrink everyone else */
2646 /* Create an AGP memory structure pointing at our pages, and bind it
2649 obj_priv->agp_mem = drm_agp_bind_pages(dev,
2651 obj->size >> PAGE_SHIFT,
2652 obj_priv->gtt_offset,
2653 obj_priv->agp_type);
2654 if (obj_priv->agp_mem == NULL) {
2655 i915_gem_object_put_pages(obj);
2656 drm_mm_put_block(obj_priv->gtt_space);
2657 obj_priv->gtt_space = NULL;
2659 ret = i915_gem_evict_something(dev, obj->size);
2665 atomic_inc(&dev->gtt_count);
2666 atomic_add(obj->size, &dev->gtt_memory);
2668 /* Assert that the object is not currently in any GPU domain. As it
2669 * wasn't in the GTT, there shouldn't be any way it could have been in
2672 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2673 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
2675 trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2681 i915_gem_clflush_object(struct drm_gem_object *obj)
2683 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2685 /* If we don't have a page list set up, then we're not pinned
2686 * to GPU, and we can ignore the cache flush because it'll happen
2687 * again at bind time.
2689 if (obj_priv->pages == NULL)
2692 trace_i915_gem_object_clflush(obj);
2694 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2697 /** Flushes any GPU write domain for the object if it's dirty. */
2699 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2701 struct drm_device *dev = obj->dev;
2703 uint32_t old_write_domain;
2705 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2708 /* Queue the GPU write cache flushing we need. */
2709 old_write_domain = obj->write_domain;
2710 i915_gem_flush(dev, 0, obj->write_domain);
2711 seqno = i915_add_request(dev, NULL, obj->write_domain);
2712 BUG_ON(obj->write_domain);
2713 i915_gem_object_move_to_active(obj, seqno);
2715 trace_i915_gem_object_change_domain(obj,
2720 /** Flushes the GTT write domain for the object if it's dirty. */
2722 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2724 uint32_t old_write_domain;
2726 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2729 /* No actual flushing is required for the GTT write domain. Writes
2730 * to it immediately go to main memory as far as we know, so there's
2731 * no chipset flush. It also doesn't land in render cache.
2733 old_write_domain = obj->write_domain;
2734 obj->write_domain = 0;
2736 trace_i915_gem_object_change_domain(obj,
2741 /** Flushes the CPU write domain for the object if it's dirty. */
2743 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2745 struct drm_device *dev = obj->dev;
2746 uint32_t old_write_domain;
2748 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2751 i915_gem_clflush_object(obj);
2752 drm_agp_chipset_flush(dev);
2753 old_write_domain = obj->write_domain;
2754 obj->write_domain = 0;
2756 trace_i915_gem_object_change_domain(obj,
2762 i915_gem_object_flush_write_domain(struct drm_gem_object *obj)
2764 switch (obj->write_domain) {
2765 case I915_GEM_DOMAIN_GTT:
2766 i915_gem_object_flush_gtt_write_domain(obj);
2768 case I915_GEM_DOMAIN_CPU:
2769 i915_gem_object_flush_cpu_write_domain(obj);
2772 i915_gem_object_flush_gpu_write_domain(obj);
2778 * Moves a single object to the GTT read, and possibly write domain.
2780 * This function returns when the move is complete, including waiting on
2784 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2786 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2787 uint32_t old_write_domain, old_read_domains;
2790 /* Not valid to be called on unbound objects. */
2791 if (obj_priv->gtt_space == NULL)
2794 i915_gem_object_flush_gpu_write_domain(obj);
2795 /* Wait on any GPU rendering and flushing to occur. */
2796 ret = i915_gem_object_wait_rendering(obj);
2800 old_write_domain = obj->write_domain;
2801 old_read_domains = obj->read_domains;
2803 /* If we're writing through the GTT domain, then CPU and GPU caches
2804 * will need to be invalidated at next use.
2807 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2809 i915_gem_object_flush_cpu_write_domain(obj);
2811 /* It should now be out of any other write domains, and we can update
2812 * the domain values for our changes.
2814 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2815 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2817 obj->write_domain = I915_GEM_DOMAIN_GTT;
2818 obj_priv->dirty = 1;
2821 trace_i915_gem_object_change_domain(obj,
2829 * Prepare buffer for display plane. Use uninterruptible for possible flush
2830 * wait, as in modesetting process we're not supposed to be interrupted.
2833 i915_gem_object_set_to_display_plane(struct drm_gem_object *obj)
2835 struct drm_device *dev = obj->dev;
2836 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2837 uint32_t old_write_domain, old_read_domains;
2840 /* Not valid to be called on unbound objects. */
2841 if (obj_priv->gtt_space == NULL)
2844 i915_gem_object_flush_gpu_write_domain(obj);
2846 /* Wait on any GPU rendering and flushing to occur. */
2847 if (obj_priv->active) {
2849 DRM_INFO("%s: object %p wait for seqno %08x\n",
2850 __func__, obj, obj_priv->last_rendering_seqno);
2852 ret = i915_do_wait_request(dev, obj_priv->last_rendering_seqno, 0);
2857 old_write_domain = obj->write_domain;
2858 old_read_domains = obj->read_domains;
2860 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2862 i915_gem_object_flush_cpu_write_domain(obj);
2864 /* It should now be out of any other write domains, and we can update
2865 * the domain values for our changes.
2867 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2868 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2869 obj->write_domain = I915_GEM_DOMAIN_GTT;
2870 obj_priv->dirty = 1;
2872 trace_i915_gem_object_change_domain(obj,
2880 * Moves a single object to the CPU read, and possibly write domain.
2882 * This function returns when the move is complete, including waiting on
2886 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2888 uint32_t old_write_domain, old_read_domains;
2891 i915_gem_object_flush_gpu_write_domain(obj);
2892 /* Wait on any GPU rendering and flushing to occur. */
2893 ret = i915_gem_object_wait_rendering(obj);
2897 i915_gem_object_flush_gtt_write_domain(obj);
2899 /* If we have a partially-valid cache of the object in the CPU,
2900 * finish invalidating it and free the per-page flags.
2902 i915_gem_object_set_to_full_cpu_read_domain(obj);
2904 old_write_domain = obj->write_domain;
2905 old_read_domains = obj->read_domains;
2907 /* Flush the CPU cache if it's still invalid. */
2908 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2909 i915_gem_clflush_object(obj);
2911 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2914 /* It should now be out of any other write domains, and we can update
2915 * the domain values for our changes.
2917 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2919 /* If we're writing through the CPU, then the GPU read domains will
2920 * need to be invalidated at next use.
2923 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2924 obj->write_domain = I915_GEM_DOMAIN_CPU;
2927 trace_i915_gem_object_change_domain(obj,
2935 * Set the next domain for the specified object. This
2936 * may not actually perform the necessary flushing/invaliding though,
2937 * as that may want to be batched with other set_domain operations
2939 * This is (we hope) the only really tricky part of gem. The goal
2940 * is fairly simple -- track which caches hold bits of the object
2941 * and make sure they remain coherent. A few concrete examples may
2942 * help to explain how it works. For shorthand, we use the notation
2943 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2944 * a pair of read and write domain masks.
2946 * Case 1: the batch buffer
2952 * 5. Unmapped from GTT
2955 * Let's take these a step at a time
2958 * Pages allocated from the kernel may still have
2959 * cache contents, so we set them to (CPU, CPU) always.
2960 * 2. Written by CPU (using pwrite)
2961 * The pwrite function calls set_domain (CPU, CPU) and
2962 * this function does nothing (as nothing changes)
2964 * This function asserts that the object is not
2965 * currently in any GPU-based read or write domains
2967 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2968 * As write_domain is zero, this function adds in the
2969 * current read domains (CPU+COMMAND, 0).
2970 * flush_domains is set to CPU.
2971 * invalidate_domains is set to COMMAND
2972 * clflush is run to get data out of the CPU caches
2973 * then i915_dev_set_domain calls i915_gem_flush to
2974 * emit an MI_FLUSH and drm_agp_chipset_flush
2975 * 5. Unmapped from GTT
2976 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2977 * flush_domains and invalidate_domains end up both zero
2978 * so no flushing/invalidating happens
2982 * Case 2: The shared render buffer
2986 * 3. Read/written by GPU
2987 * 4. set_domain to (CPU,CPU)
2988 * 5. Read/written by CPU
2989 * 6. Read/written by GPU
2992 * Same as last example, (CPU, CPU)
2994 * Nothing changes (assertions find that it is not in the GPU)
2995 * 3. Read/written by GPU
2996 * execbuffer calls set_domain (RENDER, RENDER)
2997 * flush_domains gets CPU
2998 * invalidate_domains gets GPU
3000 * MI_FLUSH and drm_agp_chipset_flush
3001 * 4. set_domain (CPU, CPU)
3002 * flush_domains gets GPU
3003 * invalidate_domains gets CPU
3004 * wait_rendering (obj) to make sure all drawing is complete.
3005 * This will include an MI_FLUSH to get the data from GPU
3007 * clflush (obj) to invalidate the CPU cache
3008 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3009 * 5. Read/written by CPU
3010 * cache lines are loaded and dirtied
3011 * 6. Read written by GPU
3012 * Same as last GPU access
3014 * Case 3: The constant buffer
3019 * 4. Updated (written) by CPU again
3028 * flush_domains = CPU
3029 * invalidate_domains = RENDER
3032 * drm_agp_chipset_flush
3033 * 4. Updated (written) by CPU again
3035 * flush_domains = 0 (no previous write domain)
3036 * invalidate_domains = 0 (no new read domains)
3039 * flush_domains = CPU
3040 * invalidate_domains = RENDER
3043 * drm_agp_chipset_flush
3046 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
3048 struct drm_device *dev = obj->dev;
3049 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3050 uint32_t invalidate_domains = 0;
3051 uint32_t flush_domains = 0;
3052 uint32_t old_read_domains;
3054 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
3055 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
3057 intel_mark_busy(dev, obj);
3060 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
3062 obj->read_domains, obj->pending_read_domains,
3063 obj->write_domain, obj->pending_write_domain);
3066 * If the object isn't moving to a new write domain,
3067 * let the object stay in multiple read domains
3069 if (obj->pending_write_domain == 0)
3070 obj->pending_read_domains |= obj->read_domains;
3072 obj_priv->dirty = 1;
3075 * Flush the current write domain if
3076 * the new read domains don't match. Invalidate
3077 * any read domains which differ from the old
3080 if (obj->write_domain &&
3081 obj->write_domain != obj->pending_read_domains) {
3082 flush_domains |= obj->write_domain;
3083 invalidate_domains |=
3084 obj->pending_read_domains & ~obj->write_domain;
3087 * Invalidate any read caches which may have
3088 * stale data. That is, any new read domains.
3090 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
3091 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
3093 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3094 __func__, flush_domains, invalidate_domains);
3096 i915_gem_clflush_object(obj);
3099 old_read_domains = obj->read_domains;
3101 /* The actual obj->write_domain will be updated with
3102 * pending_write_domain after we emit the accumulated flush for all
3103 * of our domain changes in execbuffers (which clears objects'
3104 * write_domains). So if we have a current write domain that we
3105 * aren't changing, set pending_write_domain to that.
3107 if (flush_domains == 0 && obj->pending_write_domain == 0)
3108 obj->pending_write_domain = obj->write_domain;
3109 obj->read_domains = obj->pending_read_domains;
3111 dev->invalidate_domains |= invalidate_domains;
3112 dev->flush_domains |= flush_domains;
3114 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3116 obj->read_domains, obj->write_domain,
3117 dev->invalidate_domains, dev->flush_domains);
3120 trace_i915_gem_object_change_domain(obj,
3126 * Moves the object from a partially CPU read to a full one.
3128 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3129 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3132 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
3134 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3136 if (!obj_priv->page_cpu_valid)
3139 /* If we're partially in the CPU read domain, finish moving it in.
3141 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3144 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3145 if (obj_priv->page_cpu_valid[i])
3147 drm_clflush_pages(obj_priv->pages + i, 1);
3151 /* Free the page_cpu_valid mappings which are now stale, whether
3152 * or not we've got I915_GEM_DOMAIN_CPU.
3154 kfree(obj_priv->page_cpu_valid);
3155 obj_priv->page_cpu_valid = NULL;
3159 * Set the CPU read domain on a range of the object.
3161 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3162 * not entirely valid. The page_cpu_valid member of the object flags which
3163 * pages have been flushed, and will be respected by
3164 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3165 * of the whole object.
3167 * This function returns when the move is complete, including waiting on
3171 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3172 uint64_t offset, uint64_t size)
3174 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3175 uint32_t old_read_domains;
3178 if (offset == 0 && size == obj->size)
3179 return i915_gem_object_set_to_cpu_domain(obj, 0);
3181 i915_gem_object_flush_gpu_write_domain(obj);
3182 /* Wait on any GPU rendering and flushing to occur. */
3183 ret = i915_gem_object_wait_rendering(obj);
3186 i915_gem_object_flush_gtt_write_domain(obj);
3188 /* If we're already fully in the CPU read domain, we're done. */
3189 if (obj_priv->page_cpu_valid == NULL &&
3190 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3193 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3194 * newly adding I915_GEM_DOMAIN_CPU
3196 if (obj_priv->page_cpu_valid == NULL) {
3197 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3199 if (obj_priv->page_cpu_valid == NULL)
3201 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3202 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
3204 /* Flush the cache on any pages that are still invalid from the CPU's
3207 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3209 if (obj_priv->page_cpu_valid[i])
3212 drm_clflush_pages(obj_priv->pages + i, 1);
3214 obj_priv->page_cpu_valid[i] = 1;
3217 /* It should now be out of any other write domains, and we can update
3218 * the domain values for our changes.
3220 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3222 old_read_domains = obj->read_domains;
3223 obj->read_domains |= I915_GEM_DOMAIN_CPU;
3225 trace_i915_gem_object_change_domain(obj,
3233 * Pin an object to the GTT and evaluate the relocations landing in it.
3236 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3237 struct drm_file *file_priv,
3238 struct drm_i915_gem_exec_object2 *entry,
3239 struct drm_i915_gem_relocation_entry *relocs)
3241 struct drm_device *dev = obj->dev;
3242 drm_i915_private_t *dev_priv = dev->dev_private;
3243 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3245 void __iomem *reloc_page;
3248 need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
3249 obj_priv->tiling_mode != I915_TILING_NONE;
3251 /* Check fence reg constraints and rebind if necessary */
3252 if (need_fence && !i915_gem_object_fence_offset_ok(obj,
3253 obj_priv->tiling_mode))
3254 i915_gem_object_unbind(obj);
3256 /* Choose the GTT offset for our buffer and put it there. */
3257 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3262 * Pre-965 chips need a fence register set up in order to
3263 * properly handle blits to/from tiled surfaces.
3266 ret = i915_gem_object_get_fence_reg(obj);
3268 if (ret != -EBUSY && ret != -ERESTARTSYS)
3269 DRM_ERROR("Failure to install fence: %d\n",
3271 i915_gem_object_unpin(obj);
3276 entry->offset = obj_priv->gtt_offset;
3278 /* Apply the relocations, using the GTT aperture to avoid cache
3279 * flushing requirements.
3281 for (i = 0; i < entry->relocation_count; i++) {
3282 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
3283 struct drm_gem_object *target_obj;
3284 struct drm_i915_gem_object *target_obj_priv;
3285 uint32_t reloc_val, reloc_offset;
3286 uint32_t __iomem *reloc_entry;
3288 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
3289 reloc->target_handle);
3290 if (target_obj == NULL) {
3291 i915_gem_object_unpin(obj);
3294 target_obj_priv = target_obj->driver_private;
3297 DRM_INFO("%s: obj %p offset %08x target %d "
3298 "read %08x write %08x gtt %08x "
3299 "presumed %08x delta %08x\n",
3302 (int) reloc->offset,
3303 (int) reloc->target_handle,
3304 (int) reloc->read_domains,
3305 (int) reloc->write_domain,
3306 (int) target_obj_priv->gtt_offset,
3307 (int) reloc->presumed_offset,
3311 /* The target buffer should have appeared before us in the
3312 * exec_object list, so it should have a GTT space bound by now.
3314 if (target_obj_priv->gtt_space == NULL) {
3315 DRM_ERROR("No GTT space found for object %d\n",
3316 reloc->target_handle);
3317 drm_gem_object_unreference(target_obj);
3318 i915_gem_object_unpin(obj);
3322 /* Validate that the target is in a valid r/w GPU domain */
3323 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3324 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
3325 DRM_ERROR("reloc with read/write CPU domains: "
3326 "obj %p target %d offset %d "
3327 "read %08x write %08x",
3328 obj, reloc->target_handle,
3329 (int) reloc->offset,
3330 reloc->read_domains,
3331 reloc->write_domain);
3332 drm_gem_object_unreference(target_obj);
3333 i915_gem_object_unpin(obj);
3336 if (reloc->write_domain && target_obj->pending_write_domain &&
3337 reloc->write_domain != target_obj->pending_write_domain) {
3338 DRM_ERROR("Write domain conflict: "
3339 "obj %p target %d offset %d "
3340 "new %08x old %08x\n",
3341 obj, reloc->target_handle,
3342 (int) reloc->offset,
3343 reloc->write_domain,
3344 target_obj->pending_write_domain);
3345 drm_gem_object_unreference(target_obj);
3346 i915_gem_object_unpin(obj);
3350 target_obj->pending_read_domains |= reloc->read_domains;
3351 target_obj->pending_write_domain |= reloc->write_domain;
3353 /* If the relocation already has the right value in it, no
3354 * more work needs to be done.
3356 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
3357 drm_gem_object_unreference(target_obj);
3361 /* Check that the relocation address is valid... */
3362 if (reloc->offset > obj->size - 4) {
3363 DRM_ERROR("Relocation beyond object bounds: "
3364 "obj %p target %d offset %d size %d.\n",
3365 obj, reloc->target_handle,
3366 (int) reloc->offset, (int) obj->size);
3367 drm_gem_object_unreference(target_obj);
3368 i915_gem_object_unpin(obj);
3371 if (reloc->offset & 3) {
3372 DRM_ERROR("Relocation not 4-byte aligned: "
3373 "obj %p target %d offset %d.\n",
3374 obj, reloc->target_handle,
3375 (int) reloc->offset);
3376 drm_gem_object_unreference(target_obj);
3377 i915_gem_object_unpin(obj);
3381 /* and points to somewhere within the target object. */
3382 if (reloc->delta >= target_obj->size) {
3383 DRM_ERROR("Relocation beyond target object bounds: "
3384 "obj %p target %d delta %d size %d.\n",
3385 obj, reloc->target_handle,
3386 (int) reloc->delta, (int) target_obj->size);
3387 drm_gem_object_unreference(target_obj);
3388 i915_gem_object_unpin(obj);
3392 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3394 drm_gem_object_unreference(target_obj);
3395 i915_gem_object_unpin(obj);
3399 /* Map the page containing the relocation we're going to
3402 reloc_offset = obj_priv->gtt_offset + reloc->offset;
3403 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3406 reloc_entry = (uint32_t __iomem *)(reloc_page +
3407 (reloc_offset & (PAGE_SIZE - 1)));
3408 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
3411 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3412 obj, (unsigned int) reloc->offset,
3413 readl(reloc_entry), reloc_val);
3415 writel(reloc_val, reloc_entry);
3416 io_mapping_unmap_atomic(reloc_page);
3418 /* The updated presumed offset for this entry will be
3419 * copied back out to the user.
3421 reloc->presumed_offset = target_obj_priv->gtt_offset;
3423 drm_gem_object_unreference(target_obj);
3428 i915_gem_dump_object(obj, 128, __func__, ~0);
3433 /** Dispatch a batchbuffer to the ring
3436 i915_dispatch_gem_execbuffer(struct drm_device *dev,
3437 struct drm_i915_gem_execbuffer2 *exec,
3438 struct drm_clip_rect *cliprects,
3439 uint64_t exec_offset)
3441 drm_i915_private_t *dev_priv = dev->dev_private;
3442 int nbox = exec->num_cliprects;
3444 uint32_t exec_start, exec_len;
3447 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3448 exec_len = (uint32_t) exec->batch_len;
3450 trace_i915_gem_request_submit(dev, dev_priv->mm.next_gem_seqno + 1);
3452 count = nbox ? nbox : 1;
3454 for (i = 0; i < count; i++) {
3456 int ret = i915_emit_box(dev, cliprects, i,
3457 exec->DR1, exec->DR4);
3462 if (IS_I830(dev) || IS_845G(dev)) {
3464 OUT_RING(MI_BATCH_BUFFER);
3465 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3466 OUT_RING(exec_start + exec_len - 4);
3471 if (IS_I965G(dev)) {
3472 OUT_RING(MI_BATCH_BUFFER_START |
3474 MI_BATCH_NON_SECURE_I965);
3475 OUT_RING(exec_start);
3477 OUT_RING(MI_BATCH_BUFFER_START |
3479 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3485 /* XXX breadcrumb */
3489 /* Throttle our rendering by waiting until the ring has completed our requests
3490 * emitted over 20 msec ago.
3492 * Note that if we were to use the current jiffies each time around the loop,
3493 * we wouldn't escape the function with any frames outstanding if the time to
3494 * render a frame was over 20ms.
3496 * This should get us reasonable parallelism between CPU and GPU but also
3497 * relatively low latency when blocking on a particular request to finish.
3500 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3502 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3504 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3506 mutex_lock(&dev->struct_mutex);
3507 while (!list_empty(&i915_file_priv->mm.request_list)) {
3508 struct drm_i915_gem_request *request;
3510 request = list_first_entry(&i915_file_priv->mm.request_list,
3511 struct drm_i915_gem_request,
3514 if (time_after_eq(request->emitted_jiffies, recent_enough))
3517 ret = i915_wait_request(dev, request->seqno);
3521 mutex_unlock(&dev->struct_mutex);
3527 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list,
3528 uint32_t buffer_count,
3529 struct drm_i915_gem_relocation_entry **relocs)
3531 uint32_t reloc_count = 0, reloc_index = 0, i;
3535 for (i = 0; i < buffer_count; i++) {
3536 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3538 reloc_count += exec_list[i].relocation_count;
3541 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
3542 if (*relocs == NULL) {
3543 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count);
3547 for (i = 0; i < buffer_count; i++) {
3548 struct drm_i915_gem_relocation_entry __user *user_relocs;
3550 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3552 ret = copy_from_user(&(*relocs)[reloc_index],
3554 exec_list[i].relocation_count *
3557 drm_free_large(*relocs);
3562 reloc_index += exec_list[i].relocation_count;
3569 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list,
3570 uint32_t buffer_count,
3571 struct drm_i915_gem_relocation_entry *relocs)
3573 uint32_t reloc_count = 0, i;
3579 for (i = 0; i < buffer_count; i++) {
3580 struct drm_i915_gem_relocation_entry __user *user_relocs;
3583 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3585 unwritten = copy_to_user(user_relocs,
3586 &relocs[reloc_count],
3587 exec_list[i].relocation_count *
3595 reloc_count += exec_list[i].relocation_count;
3599 drm_free_large(relocs);
3605 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec,
3606 uint64_t exec_offset)
3608 uint32_t exec_start, exec_len;
3610 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3611 exec_len = (uint32_t) exec->batch_len;
3613 if ((exec_start | exec_len) & 0x7)
3623 i915_gem_wait_for_pending_flip(struct drm_device *dev,
3624 struct drm_gem_object **object_list,
3627 drm_i915_private_t *dev_priv = dev->dev_private;
3628 struct drm_i915_gem_object *obj_priv;
3633 prepare_to_wait(&dev_priv->pending_flip_queue,
3634 &wait, TASK_INTERRUPTIBLE);
3635 for (i = 0; i < count; i++) {
3636 obj_priv = object_list[i]->driver_private;
3637 if (atomic_read(&obj_priv->pending_flip) > 0)
3643 if (!signal_pending(current)) {
3644 mutex_unlock(&dev->struct_mutex);
3646 mutex_lock(&dev->struct_mutex);
3652 finish_wait(&dev_priv->pending_flip_queue, &wait);
3658 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3659 struct drm_file *file_priv,
3660 struct drm_i915_gem_execbuffer2 *args,
3661 struct drm_i915_gem_exec_object2 *exec_list)
3663 drm_i915_private_t *dev_priv = dev->dev_private;
3664 struct drm_gem_object **object_list = NULL;
3665 struct drm_gem_object *batch_obj;
3666 struct drm_i915_gem_object *obj_priv;
3667 struct drm_clip_rect *cliprects = NULL;
3668 struct drm_i915_gem_relocation_entry *relocs = NULL;
3669 int ret = 0, ret2, i, pinned = 0;
3670 uint64_t exec_offset;
3671 uint32_t seqno, flush_domains, reloc_index;
3672 int pin_tries, flips;
3675 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3676 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3679 if (args->buffer_count < 1) {
3680 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3683 object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
3684 if (object_list == NULL) {
3685 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3686 args->buffer_count);
3691 if (args->num_cliprects != 0) {
3692 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3694 if (cliprects == NULL) {
3699 ret = copy_from_user(cliprects,
3700 (struct drm_clip_rect __user *)
3701 (uintptr_t) args->cliprects_ptr,
3702 sizeof(*cliprects) * args->num_cliprects);
3704 DRM_ERROR("copy %d cliprects failed: %d\n",
3705 args->num_cliprects, ret);
3710 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3715 mutex_lock(&dev->struct_mutex);
3717 i915_verify_inactive(dev, __FILE__, __LINE__);
3719 if (atomic_read(&dev_priv->mm.wedged)) {
3720 mutex_unlock(&dev->struct_mutex);
3725 if (dev_priv->mm.suspended) {
3726 mutex_unlock(&dev->struct_mutex);
3731 /* Look up object handles */
3733 for (i = 0; i < args->buffer_count; i++) {
3734 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3735 exec_list[i].handle);
3736 if (object_list[i] == NULL) {
3737 DRM_ERROR("Invalid object handle %d at index %d\n",
3738 exec_list[i].handle, i);
3739 /* prevent error path from reading uninitialized data */
3740 args->buffer_count = i + 1;
3745 obj_priv = object_list[i]->driver_private;
3746 if (obj_priv->in_execbuffer) {
3747 DRM_ERROR("Object %p appears more than once in object list\n",
3749 /* prevent error path from reading uninitialized data */
3750 args->buffer_count = i + 1;
3754 obj_priv->in_execbuffer = true;
3755 flips += atomic_read(&obj_priv->pending_flip);
3759 ret = i915_gem_wait_for_pending_flip(dev, object_list,
3760 args->buffer_count);
3765 /* Pin and relocate */
3766 for (pin_tries = 0; ; pin_tries++) {
3770 for (i = 0; i < args->buffer_count; i++) {
3771 object_list[i]->pending_read_domains = 0;
3772 object_list[i]->pending_write_domain = 0;
3773 ret = i915_gem_object_pin_and_relocate(object_list[i],
3776 &relocs[reloc_index]);
3780 reloc_index += exec_list[i].relocation_count;
3786 /* error other than GTT full, or we've already tried again */
3787 if (ret != -ENOSPC || pin_tries >= 1) {
3788 if (ret != -ERESTARTSYS) {
3789 unsigned long long total_size = 0;
3790 for (i = 0; i < args->buffer_count; i++)
3791 total_size += object_list[i]->size;
3792 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes: %d\n",
3793 pinned+1, args->buffer_count,
3795 DRM_ERROR("%d objects [%d pinned], "
3796 "%d object bytes [%d pinned], "
3797 "%d/%d gtt bytes\n",
3798 atomic_read(&dev->object_count),
3799 atomic_read(&dev->pin_count),
3800 atomic_read(&dev->object_memory),
3801 atomic_read(&dev->pin_memory),
3802 atomic_read(&dev->gtt_memory),
3808 /* unpin all of our buffers */
3809 for (i = 0; i < pinned; i++)
3810 i915_gem_object_unpin(object_list[i]);
3813 /* evict everyone we can from the aperture */
3814 ret = i915_gem_evict_everything(dev);
3815 if (ret && ret != -ENOSPC)
3819 /* Set the pending read domains for the batch buffer to COMMAND */
3820 batch_obj = object_list[args->buffer_count-1];
3821 if (batch_obj->pending_write_domain) {
3822 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3826 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
3828 /* Sanity check the batch buffer, prior to moving objects */
3829 exec_offset = exec_list[args->buffer_count - 1].offset;
3830 ret = i915_gem_check_execbuffer (args, exec_offset);
3832 DRM_ERROR("execbuf with invalid offset/length\n");
3836 i915_verify_inactive(dev, __FILE__, __LINE__);
3838 /* Zero the global flush/invalidate flags. These
3839 * will be modified as new domains are computed
3842 dev->invalidate_domains = 0;
3843 dev->flush_domains = 0;
3845 for (i = 0; i < args->buffer_count; i++) {
3846 struct drm_gem_object *obj = object_list[i];
3848 /* Compute new gpu domains and update invalidate/flush */
3849 i915_gem_object_set_to_gpu_domain(obj);
3852 i915_verify_inactive(dev, __FILE__, __LINE__);
3854 if (dev->invalidate_domains | dev->flush_domains) {
3856 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3858 dev->invalidate_domains,
3859 dev->flush_domains);
3862 dev->invalidate_domains,
3863 dev->flush_domains);
3864 if (dev->flush_domains & I915_GEM_GPU_DOMAINS)
3865 (void)i915_add_request(dev, file_priv,
3866 dev->flush_domains);
3869 for (i = 0; i < args->buffer_count; i++) {
3870 struct drm_gem_object *obj = object_list[i];
3871 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3872 uint32_t old_write_domain = obj->write_domain;
3874 obj->write_domain = obj->pending_write_domain;
3875 if (obj->write_domain)
3876 list_move_tail(&obj_priv->gpu_write_list,
3877 &dev_priv->mm.gpu_write_list);
3879 list_del_init(&obj_priv->gpu_write_list);
3881 trace_i915_gem_object_change_domain(obj,
3886 i915_verify_inactive(dev, __FILE__, __LINE__);
3889 for (i = 0; i < args->buffer_count; i++) {
3890 i915_gem_object_check_coherency(object_list[i],
3891 exec_list[i].handle);
3896 i915_gem_dump_object(batch_obj,
3902 /* Exec the batchbuffer */
3903 ret = i915_dispatch_gem_execbuffer(dev, args, cliprects, exec_offset);
3905 DRM_ERROR("dispatch failed %d\n", ret);
3910 * Ensure that the commands in the batch buffer are
3911 * finished before the interrupt fires
3913 flush_domains = i915_retire_commands(dev);
3915 i915_verify_inactive(dev, __FILE__, __LINE__);
3918 * Get a seqno representing the execution of the current buffer,
3919 * which we can wait on. We would like to mitigate these interrupts,
3920 * likely by only creating seqnos occasionally (so that we have
3921 * *some* interrupts representing completion of buffers that we can
3922 * wait on when trying to clear up gtt space).
3924 seqno = i915_add_request(dev, file_priv, flush_domains);
3926 for (i = 0; i < args->buffer_count; i++) {
3927 struct drm_gem_object *obj = object_list[i];
3929 i915_gem_object_move_to_active(obj, seqno);
3931 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3935 i915_dump_lru(dev, __func__);
3938 i915_verify_inactive(dev, __FILE__, __LINE__);
3941 for (i = 0; i < pinned; i++)
3942 i915_gem_object_unpin(object_list[i]);
3944 for (i = 0; i < args->buffer_count; i++) {
3945 if (object_list[i]) {
3946 obj_priv = object_list[i]->driver_private;
3947 obj_priv->in_execbuffer = false;
3949 drm_gem_object_unreference(object_list[i]);
3952 mutex_unlock(&dev->struct_mutex);
3955 /* Copy the updated relocations out regardless of current error
3956 * state. Failure to update the relocs would mean that the next
3957 * time userland calls execbuf, it would do so with presumed offset
3958 * state that didn't match the actual object state.
3960 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
3963 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
3969 drm_free_large(object_list);
3976 * Legacy execbuffer just creates an exec2 list from the original exec object
3977 * list array and passes it to the real function.
3980 i915_gem_execbuffer(struct drm_device *dev, void *data,
3981 struct drm_file *file_priv)
3983 struct drm_i915_gem_execbuffer *args = data;
3984 struct drm_i915_gem_execbuffer2 exec2;
3985 struct drm_i915_gem_exec_object *exec_list = NULL;
3986 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
3990 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3991 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3994 if (args->buffer_count < 1) {
3995 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3999 /* Copy in the exec list from userland */
4000 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
4001 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4002 if (exec_list == NULL || exec2_list == NULL) {
4003 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4004 args->buffer_count);
4005 drm_free_large(exec_list);
4006 drm_free_large(exec2_list);
4009 ret = copy_from_user(exec_list,
4010 (struct drm_i915_relocation_entry __user *)
4011 (uintptr_t) args->buffers_ptr,
4012 sizeof(*exec_list) * args->buffer_count);
4014 DRM_ERROR("copy %d exec entries failed %d\n",
4015 args->buffer_count, ret);
4016 drm_free_large(exec_list);
4017 drm_free_large(exec2_list);
4021 for (i = 0; i < args->buffer_count; i++) {
4022 exec2_list[i].handle = exec_list[i].handle;
4023 exec2_list[i].relocation_count = exec_list[i].relocation_count;
4024 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
4025 exec2_list[i].alignment = exec_list[i].alignment;
4026 exec2_list[i].offset = exec_list[i].offset;
4028 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
4030 exec2_list[i].flags = 0;
4033 exec2.buffers_ptr = args->buffers_ptr;
4034 exec2.buffer_count = args->buffer_count;
4035 exec2.batch_start_offset = args->batch_start_offset;
4036 exec2.batch_len = args->batch_len;
4037 exec2.DR1 = args->DR1;
4038 exec2.DR4 = args->DR4;
4039 exec2.num_cliprects = args->num_cliprects;
4040 exec2.cliprects_ptr = args->cliprects_ptr;
4043 ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
4045 /* Copy the new buffer offsets back to the user's exec list. */
4046 for (i = 0; i < args->buffer_count; i++)
4047 exec_list[i].offset = exec2_list[i].offset;
4048 /* ... and back out to userspace */
4049 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4050 (uintptr_t) args->buffers_ptr,
4052 sizeof(*exec_list) * args->buffer_count);
4055 DRM_ERROR("failed to copy %d exec entries "
4056 "back to user (%d)\n",
4057 args->buffer_count, ret);
4061 drm_free_large(exec_list);
4062 drm_free_large(exec2_list);
4067 i915_gem_execbuffer2(struct drm_device *dev, void *data,
4068 struct drm_file *file_priv)
4070 struct drm_i915_gem_execbuffer2 *args = data;
4071 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4075 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4076 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4079 if (args->buffer_count < 1) {
4080 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
4084 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4085 if (exec2_list == NULL) {
4086 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4087 args->buffer_count);
4090 ret = copy_from_user(exec2_list,
4091 (struct drm_i915_relocation_entry __user *)
4092 (uintptr_t) args->buffers_ptr,
4093 sizeof(*exec2_list) * args->buffer_count);
4095 DRM_ERROR("copy %d exec entries failed %d\n",
4096 args->buffer_count, ret);
4097 drm_free_large(exec2_list);
4101 ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
4103 /* Copy the new buffer offsets back to the user's exec list. */
4104 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4105 (uintptr_t) args->buffers_ptr,
4107 sizeof(*exec2_list) * args->buffer_count);
4110 DRM_ERROR("failed to copy %d exec entries "
4111 "back to user (%d)\n",
4112 args->buffer_count, ret);
4116 drm_free_large(exec2_list);
4121 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
4123 struct drm_device *dev = obj->dev;
4124 struct drm_i915_gem_object *obj_priv = obj->driver_private;
4127 i915_verify_inactive(dev, __FILE__, __LINE__);
4128 if (obj_priv->gtt_space == NULL) {
4129 ret = i915_gem_object_bind_to_gtt(obj, alignment);
4134 obj_priv->pin_count++;
4136 /* If the object is not active and not pending a flush,
4137 * remove it from the inactive list
4139 if (obj_priv->pin_count == 1) {
4140 atomic_inc(&dev->pin_count);
4141 atomic_add(obj->size, &dev->pin_memory);
4142 if (!obj_priv->active &&
4143 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 &&
4144 !list_empty(&obj_priv->list))
4145 list_del_init(&obj_priv->list);
4147 i915_verify_inactive(dev, __FILE__, __LINE__);
4153 i915_gem_object_unpin(struct drm_gem_object *obj)
4155 struct drm_device *dev = obj->dev;
4156 drm_i915_private_t *dev_priv = dev->dev_private;
4157 struct drm_i915_gem_object *obj_priv = obj->driver_private;
4159 i915_verify_inactive(dev, __FILE__, __LINE__);
4160 obj_priv->pin_count--;
4161 BUG_ON(obj_priv->pin_count < 0);
4162 BUG_ON(obj_priv->gtt_space == NULL);
4164 /* If the object is no longer pinned, and is
4165 * neither active nor being flushed, then stick it on
4168 if (obj_priv->pin_count == 0) {
4169 if (!obj_priv->active &&
4170 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
4171 list_move_tail(&obj_priv->list,
4172 &dev_priv->mm.inactive_list);
4173 atomic_dec(&dev->pin_count);
4174 atomic_sub(obj->size, &dev->pin_memory);
4176 i915_verify_inactive(dev, __FILE__, __LINE__);
4180 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4181 struct drm_file *file_priv)
4183 struct drm_i915_gem_pin *args = data;
4184 struct drm_gem_object *obj;
4185 struct drm_i915_gem_object *obj_priv;
4188 mutex_lock(&dev->struct_mutex);
4190 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4192 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4194 mutex_unlock(&dev->struct_mutex);
4197 obj_priv = obj->driver_private;
4199 if (obj_priv->madv != I915_MADV_WILLNEED) {
4200 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4201 drm_gem_object_unreference(obj);
4202 mutex_unlock(&dev->struct_mutex);
4206 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
4207 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4209 drm_gem_object_unreference(obj);
4210 mutex_unlock(&dev->struct_mutex);
4214 obj_priv->user_pin_count++;
4215 obj_priv->pin_filp = file_priv;
4216 if (obj_priv->user_pin_count == 1) {
4217 ret = i915_gem_object_pin(obj, args->alignment);
4219 drm_gem_object_unreference(obj);
4220 mutex_unlock(&dev->struct_mutex);
4225 /* XXX - flush the CPU caches for pinned objects
4226 * as the X server doesn't manage domains yet
4228 i915_gem_object_flush_cpu_write_domain(obj);
4229 args->offset = obj_priv->gtt_offset;
4230 drm_gem_object_unreference(obj);
4231 mutex_unlock(&dev->struct_mutex);
4237 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4238 struct drm_file *file_priv)
4240 struct drm_i915_gem_pin *args = data;
4241 struct drm_gem_object *obj;
4242 struct drm_i915_gem_object *obj_priv;
4244 mutex_lock(&dev->struct_mutex);
4246 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4248 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4250 mutex_unlock(&dev->struct_mutex);
4254 obj_priv = obj->driver_private;
4255 if (obj_priv->pin_filp != file_priv) {
4256 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4258 drm_gem_object_unreference(obj);
4259 mutex_unlock(&dev->struct_mutex);
4262 obj_priv->user_pin_count--;
4263 if (obj_priv->user_pin_count == 0) {
4264 obj_priv->pin_filp = NULL;
4265 i915_gem_object_unpin(obj);
4268 drm_gem_object_unreference(obj);
4269 mutex_unlock(&dev->struct_mutex);
4274 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4275 struct drm_file *file_priv)
4277 struct drm_i915_gem_busy *args = data;
4278 struct drm_gem_object *obj;
4279 struct drm_i915_gem_object *obj_priv;
4281 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4283 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4288 mutex_lock(&dev->struct_mutex);
4289 /* Update the active list for the hardware's current position.
4290 * Otherwise this only updates on a delayed timer or when irqs are
4291 * actually unmasked, and our working set ends up being larger than
4294 i915_gem_retire_requests(dev);
4296 obj_priv = obj->driver_private;
4297 /* Don't count being on the flushing list against the object being
4298 * done. Otherwise, a buffer left on the flushing list but not getting
4299 * flushed (because nobody's flushing that domain) won't ever return
4300 * unbusy and get reused by libdrm's bo cache. The other expected
4301 * consumer of this interface, OpenGL's occlusion queries, also specs
4302 * that the objects get unbusy "eventually" without any interference.
4304 args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
4306 drm_gem_object_unreference(obj);
4307 mutex_unlock(&dev->struct_mutex);
4312 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4313 struct drm_file *file_priv)
4315 return i915_gem_ring_throttle(dev, file_priv);
4319 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4320 struct drm_file *file_priv)
4322 struct drm_i915_gem_madvise *args = data;
4323 struct drm_gem_object *obj;
4324 struct drm_i915_gem_object *obj_priv;
4326 switch (args->madv) {
4327 case I915_MADV_DONTNEED:
4328 case I915_MADV_WILLNEED:
4334 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4336 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4341 mutex_lock(&dev->struct_mutex);
4342 obj_priv = obj->driver_private;
4344 if (obj_priv->pin_count) {
4345 drm_gem_object_unreference(obj);
4346 mutex_unlock(&dev->struct_mutex);
4348 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4352 if (obj_priv->madv != __I915_MADV_PURGED)
4353 obj_priv->madv = args->madv;
4355 /* if the object is no longer bound, discard its backing storage */
4356 if (i915_gem_object_is_purgeable(obj_priv) &&
4357 obj_priv->gtt_space == NULL)
4358 i915_gem_object_truncate(obj);
4360 args->retained = obj_priv->madv != __I915_MADV_PURGED;
4362 drm_gem_object_unreference(obj);
4363 mutex_unlock(&dev->struct_mutex);
4368 int i915_gem_init_object(struct drm_gem_object *obj)
4370 struct drm_i915_gem_object *obj_priv;
4372 obj_priv = kzalloc(sizeof(*obj_priv), GFP_KERNEL);
4373 if (obj_priv == NULL)
4377 * We've just allocated pages from the kernel,
4378 * so they've just been written by the CPU with
4379 * zeros. They'll need to be clflushed before we
4380 * use them with the GPU.
4382 obj->write_domain = I915_GEM_DOMAIN_CPU;
4383 obj->read_domains = I915_GEM_DOMAIN_CPU;
4385 obj_priv->agp_type = AGP_USER_MEMORY;
4387 obj->driver_private = obj_priv;
4388 obj_priv->obj = obj;
4389 obj_priv->fence_reg = I915_FENCE_REG_NONE;
4390 INIT_LIST_HEAD(&obj_priv->list);
4391 INIT_LIST_HEAD(&obj_priv->gpu_write_list);
4392 INIT_LIST_HEAD(&obj_priv->fence_list);
4393 obj_priv->madv = I915_MADV_WILLNEED;
4395 trace_i915_gem_object_create(obj);
4400 void i915_gem_free_object(struct drm_gem_object *obj)
4402 struct drm_device *dev = obj->dev;
4403 struct drm_i915_gem_object *obj_priv = obj->driver_private;
4405 trace_i915_gem_object_destroy(obj);
4407 while (obj_priv->pin_count > 0)
4408 i915_gem_object_unpin(obj);
4410 if (obj_priv->phys_obj)
4411 i915_gem_detach_phys_object(dev, obj);
4413 i915_gem_object_unbind(obj);
4415 if (obj_priv->mmap_offset)
4416 i915_gem_free_mmap_offset(obj);
4418 kfree(obj_priv->page_cpu_valid);
4419 kfree(obj_priv->bit_17);
4420 kfree(obj->driver_private);
4423 /** Unbinds all inactive objects. */
4425 i915_gem_evict_from_inactive_list(struct drm_device *dev)
4427 drm_i915_private_t *dev_priv = dev->dev_private;
4429 while (!list_empty(&dev_priv->mm.inactive_list)) {
4430 struct drm_gem_object *obj;
4433 obj = list_first_entry(&dev_priv->mm.inactive_list,
4434 struct drm_i915_gem_object,
4437 ret = i915_gem_object_unbind(obj);
4439 DRM_ERROR("Error unbinding object: %d\n", ret);
4448 i915_gpu_idle(struct drm_device *dev)
4450 drm_i915_private_t *dev_priv = dev->dev_private;
4454 spin_lock(&dev_priv->mm.active_list_lock);
4455 lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
4456 list_empty(&dev_priv->mm.active_list);
4457 spin_unlock(&dev_priv->mm.active_list_lock);
4462 /* Flush everything onto the inactive list. */
4463 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
4464 seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
4468 return i915_wait_request(dev, seqno);
4472 i915_gem_idle(struct drm_device *dev)
4474 drm_i915_private_t *dev_priv = dev->dev_private;
4477 mutex_lock(&dev->struct_mutex);
4479 if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
4480 mutex_unlock(&dev->struct_mutex);
4484 ret = i915_gpu_idle(dev);
4486 mutex_unlock(&dev->struct_mutex);
4490 /* Under UMS, be paranoid and evict. */
4491 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
4492 ret = i915_gem_evict_from_inactive_list(dev);
4494 mutex_unlock(&dev->struct_mutex);
4499 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4500 * We need to replace this with a semaphore, or something.
4501 * And not confound mm.suspended!
4503 dev_priv->mm.suspended = 1;
4504 del_timer(&dev_priv->hangcheck_timer);
4506 i915_kernel_lost_context(dev);
4507 i915_gem_cleanup_ringbuffer(dev);
4509 mutex_unlock(&dev->struct_mutex);
4511 /* Cancel the retire work handler, which should be idle now. */
4512 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4518 i915_gem_init_hws(struct drm_device *dev)
4520 drm_i915_private_t *dev_priv = dev->dev_private;
4521 struct drm_gem_object *obj;
4522 struct drm_i915_gem_object *obj_priv;
4525 /* If we need a physical address for the status page, it's already
4526 * initialized at driver load time.
4528 if (!I915_NEED_GFX_HWS(dev))
4531 obj = drm_gem_object_alloc(dev, 4096);
4533 DRM_ERROR("Failed to allocate status page\n");
4536 obj_priv = obj->driver_private;
4537 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4539 ret = i915_gem_object_pin(obj, 4096);
4541 drm_gem_object_unreference(obj);
4545 dev_priv->status_gfx_addr = obj_priv->gtt_offset;
4547 dev_priv->hw_status_page = kmap(obj_priv->pages[0]);
4548 if (dev_priv->hw_status_page == NULL) {
4549 DRM_ERROR("Failed to map status page.\n");
4550 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4551 i915_gem_object_unpin(obj);
4552 drm_gem_object_unreference(obj);
4555 dev_priv->hws_obj = obj;
4556 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
4557 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
4558 I915_READ(HWS_PGA); /* posting read */
4559 DRM_DEBUG_DRIVER("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
4565 i915_gem_cleanup_hws(struct drm_device *dev)
4567 drm_i915_private_t *dev_priv = dev->dev_private;
4568 struct drm_gem_object *obj;
4569 struct drm_i915_gem_object *obj_priv;
4571 if (dev_priv->hws_obj == NULL)
4574 obj = dev_priv->hws_obj;
4575 obj_priv = obj->driver_private;
4577 kunmap(obj_priv->pages[0]);
4578 i915_gem_object_unpin(obj);
4579 drm_gem_object_unreference(obj);
4580 dev_priv->hws_obj = NULL;
4582 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4583 dev_priv->hw_status_page = NULL;
4585 /* Write high address into HWS_PGA when disabling. */
4586 I915_WRITE(HWS_PGA, 0x1ffff000);
4590 i915_gem_init_ringbuffer(struct drm_device *dev)
4592 drm_i915_private_t *dev_priv = dev->dev_private;
4593 struct drm_gem_object *obj;
4594 struct drm_i915_gem_object *obj_priv;
4595 drm_i915_ring_buffer_t *ring = &dev_priv->ring;
4599 ret = i915_gem_init_hws(dev);
4603 obj = drm_gem_object_alloc(dev, 128 * 1024);
4605 DRM_ERROR("Failed to allocate ringbuffer\n");
4606 i915_gem_cleanup_hws(dev);
4609 obj_priv = obj->driver_private;
4611 ret = i915_gem_object_pin(obj, 4096);
4613 drm_gem_object_unreference(obj);
4614 i915_gem_cleanup_hws(dev);
4618 /* Set up the kernel mapping for the ring. */
4619 ring->Size = obj->size;
4621 ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
4622 ring->map.size = obj->size;
4624 ring->map.flags = 0;
4627 drm_core_ioremap_wc(&ring->map, dev);
4628 if (ring->map.handle == NULL) {
4629 DRM_ERROR("Failed to map ringbuffer.\n");
4630 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4631 i915_gem_object_unpin(obj);
4632 drm_gem_object_unreference(obj);
4633 i915_gem_cleanup_hws(dev);
4636 ring->ring_obj = obj;
4637 ring->virtual_start = ring->map.handle;
4639 /* Stop the ring if it's running. */
4640 I915_WRITE(PRB0_CTL, 0);
4641 I915_WRITE(PRB0_TAIL, 0);
4642 I915_WRITE(PRB0_HEAD, 0);
4644 /* Initialize the ring. */
4645 I915_WRITE(PRB0_START, obj_priv->gtt_offset);
4646 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4648 /* G45 ring initialization fails to reset head to zero */
4650 DRM_ERROR("Ring head not reset to zero "
4651 "ctl %08x head %08x tail %08x start %08x\n",
4652 I915_READ(PRB0_CTL),
4653 I915_READ(PRB0_HEAD),
4654 I915_READ(PRB0_TAIL),
4655 I915_READ(PRB0_START));
4656 I915_WRITE(PRB0_HEAD, 0);
4658 DRM_ERROR("Ring head forced to zero "
4659 "ctl %08x head %08x tail %08x start %08x\n",
4660 I915_READ(PRB0_CTL),
4661 I915_READ(PRB0_HEAD),
4662 I915_READ(PRB0_TAIL),
4663 I915_READ(PRB0_START));
4666 I915_WRITE(PRB0_CTL,
4667 ((obj->size - 4096) & RING_NR_PAGES) |
4671 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4673 /* If the head is still not zero, the ring is dead */
4675 DRM_ERROR("Ring initialization failed "
4676 "ctl %08x head %08x tail %08x start %08x\n",
4677 I915_READ(PRB0_CTL),
4678 I915_READ(PRB0_HEAD),
4679 I915_READ(PRB0_TAIL),
4680 I915_READ(PRB0_START));
4684 /* Update our cache of the ring state */
4685 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4686 i915_kernel_lost_context(dev);
4688 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4689 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
4690 ring->space = ring->head - (ring->tail + 8);
4691 if (ring->space < 0)
4692 ring->space += ring->Size;
4699 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4701 drm_i915_private_t *dev_priv = dev->dev_private;
4703 if (dev_priv->ring.ring_obj == NULL)
4706 drm_core_ioremapfree(&dev_priv->ring.map, dev);
4708 i915_gem_object_unpin(dev_priv->ring.ring_obj);
4709 drm_gem_object_unreference(dev_priv->ring.ring_obj);
4710 dev_priv->ring.ring_obj = NULL;
4711 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4713 i915_gem_cleanup_hws(dev);
4717 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4718 struct drm_file *file_priv)
4720 drm_i915_private_t *dev_priv = dev->dev_private;
4723 if (drm_core_check_feature(dev, DRIVER_MODESET))
4726 if (atomic_read(&dev_priv->mm.wedged)) {
4727 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4728 atomic_set(&dev_priv->mm.wedged, 0);
4731 mutex_lock(&dev->struct_mutex);
4732 dev_priv->mm.suspended = 0;
4734 ret = i915_gem_init_ringbuffer(dev);
4736 mutex_unlock(&dev->struct_mutex);
4740 spin_lock(&dev_priv->mm.active_list_lock);
4741 BUG_ON(!list_empty(&dev_priv->mm.active_list));
4742 spin_unlock(&dev_priv->mm.active_list_lock);
4744 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4745 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4746 BUG_ON(!list_empty(&dev_priv->mm.request_list));
4747 mutex_unlock(&dev->struct_mutex);
4749 drm_irq_install(dev);
4755 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4756 struct drm_file *file_priv)
4758 if (drm_core_check_feature(dev, DRIVER_MODESET))
4761 drm_irq_uninstall(dev);
4762 return i915_gem_idle(dev);
4766 i915_gem_lastclose(struct drm_device *dev)
4770 if (drm_core_check_feature(dev, DRIVER_MODESET))
4773 ret = i915_gem_idle(dev);
4775 DRM_ERROR("failed to idle hardware: %d\n", ret);
4779 i915_gem_load(struct drm_device *dev)
4782 drm_i915_private_t *dev_priv = dev->dev_private;
4784 spin_lock_init(&dev_priv->mm.active_list_lock);
4785 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4786 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4787 INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list);
4788 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4789 INIT_LIST_HEAD(&dev_priv->mm.request_list);
4790 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4791 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4792 i915_gem_retire_work_handler);
4793 dev_priv->mm.next_gem_seqno = 1;
4795 spin_lock(&shrink_list_lock);
4796 list_add(&dev_priv->mm.shrink_list, &shrink_list);
4797 spin_unlock(&shrink_list_lock);
4799 /* Old X drivers will take 0-2 for front, back, depth buffers */
4800 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4801 dev_priv->fence_reg_start = 3;
4803 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4804 dev_priv->num_fence_regs = 16;
4806 dev_priv->num_fence_regs = 8;
4808 /* Initialize fence registers to zero */
4809 if (IS_I965G(dev)) {
4810 for (i = 0; i < 16; i++)
4811 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4813 for (i = 0; i < 8; i++)
4814 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4815 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4816 for (i = 0; i < 8; i++)
4817 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4819 i915_gem_detect_bit_6_swizzle(dev);
4820 init_waitqueue_head(&dev_priv->pending_flip_queue);
4824 * Create a physically contiguous memory object for this object
4825 * e.g. for cursor + overlay regs
4827 int i915_gem_init_phys_object(struct drm_device *dev,
4830 drm_i915_private_t *dev_priv = dev->dev_private;
4831 struct drm_i915_gem_phys_object *phys_obj;
4834 if (dev_priv->mm.phys_objs[id - 1] || !size)
4837 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4843 phys_obj->handle = drm_pci_alloc(dev, size, 0);
4844 if (!phys_obj->handle) {
4849 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4852 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4860 void i915_gem_free_phys_object(struct drm_device *dev, int id)
4862 drm_i915_private_t *dev_priv = dev->dev_private;
4863 struct drm_i915_gem_phys_object *phys_obj;
4865 if (!dev_priv->mm.phys_objs[id - 1])
4868 phys_obj = dev_priv->mm.phys_objs[id - 1];
4869 if (phys_obj->cur_obj) {
4870 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4874 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4876 drm_pci_free(dev, phys_obj->handle);
4878 dev_priv->mm.phys_objs[id - 1] = NULL;
4881 void i915_gem_free_all_phys_object(struct drm_device *dev)
4885 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4886 i915_gem_free_phys_object(dev, i);
4889 void i915_gem_detach_phys_object(struct drm_device *dev,
4890 struct drm_gem_object *obj)
4892 struct drm_i915_gem_object *obj_priv;
4897 obj_priv = obj->driver_private;
4898 if (!obj_priv->phys_obj)
4901 ret = i915_gem_object_get_pages(obj, 0);
4905 page_count = obj->size / PAGE_SIZE;
4907 for (i = 0; i < page_count; i++) {
4908 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
4909 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4911 memcpy(dst, src, PAGE_SIZE);
4912 kunmap_atomic(dst, KM_USER0);
4914 drm_clflush_pages(obj_priv->pages, page_count);
4915 drm_agp_chipset_flush(dev);
4917 i915_gem_object_put_pages(obj);
4919 obj_priv->phys_obj->cur_obj = NULL;
4920 obj_priv->phys_obj = NULL;
4924 i915_gem_attach_phys_object(struct drm_device *dev,
4925 struct drm_gem_object *obj, int id)
4927 drm_i915_private_t *dev_priv = dev->dev_private;
4928 struct drm_i915_gem_object *obj_priv;
4933 if (id > I915_MAX_PHYS_OBJECT)
4936 obj_priv = obj->driver_private;
4938 if (obj_priv->phys_obj) {
4939 if (obj_priv->phys_obj->id == id)
4941 i915_gem_detach_phys_object(dev, obj);
4945 /* create a new object */
4946 if (!dev_priv->mm.phys_objs[id - 1]) {
4947 ret = i915_gem_init_phys_object(dev, id,
4950 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
4955 /* bind to the object */
4956 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4957 obj_priv->phys_obj->cur_obj = obj;
4959 ret = i915_gem_object_get_pages(obj, 0);
4961 DRM_ERROR("failed to get page list\n");
4965 page_count = obj->size / PAGE_SIZE;
4967 for (i = 0; i < page_count; i++) {
4968 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
4969 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4971 memcpy(dst, src, PAGE_SIZE);
4972 kunmap_atomic(src, KM_USER0);
4975 i915_gem_object_put_pages(obj);
4983 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4984 struct drm_i915_gem_pwrite *args,
4985 struct drm_file *file_priv)
4987 struct drm_i915_gem_object *obj_priv = obj->driver_private;
4990 char __user *user_data;
4992 user_data = (char __user *) (uintptr_t) args->data_ptr;
4993 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4995 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size);
4996 ret = copy_from_user(obj_addr, user_data, args->size);
5000 drm_agp_chipset_flush(dev);
5004 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
5006 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
5008 /* Clean up our request list when the client is going away, so that
5009 * later retire_requests won't dereference our soon-to-be-gone
5012 mutex_lock(&dev->struct_mutex);
5013 while (!list_empty(&i915_file_priv->mm.request_list))
5014 list_del_init(i915_file_priv->mm.request_list.next);
5015 mutex_unlock(&dev->struct_mutex);
5019 i915_gem_shrink(int nr_to_scan, gfp_t gfp_mask)
5021 drm_i915_private_t *dev_priv, *next_dev;
5022 struct drm_i915_gem_object *obj_priv, *next_obj;
5024 int would_deadlock = 1;
5026 /* "fast-path" to count number of available objects */
5027 if (nr_to_scan == 0) {
5028 spin_lock(&shrink_list_lock);
5029 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
5030 struct drm_device *dev = dev_priv->dev;
5032 if (mutex_trylock(&dev->struct_mutex)) {
5033 list_for_each_entry(obj_priv,
5034 &dev_priv->mm.inactive_list,
5037 mutex_unlock(&dev->struct_mutex);
5040 spin_unlock(&shrink_list_lock);
5042 return (cnt / 100) * sysctl_vfs_cache_pressure;
5045 spin_lock(&shrink_list_lock);
5047 /* first scan for clean buffers */
5048 list_for_each_entry_safe(dev_priv, next_dev,
5049 &shrink_list, mm.shrink_list) {
5050 struct drm_device *dev = dev_priv->dev;
5052 if (! mutex_trylock(&dev->struct_mutex))
5055 spin_unlock(&shrink_list_lock);
5057 i915_gem_retire_requests(dev);
5059 list_for_each_entry_safe(obj_priv, next_obj,
5060 &dev_priv->mm.inactive_list,
5062 if (i915_gem_object_is_purgeable(obj_priv)) {
5063 i915_gem_object_unbind(obj_priv->obj);
5064 if (--nr_to_scan <= 0)
5069 spin_lock(&shrink_list_lock);
5070 mutex_unlock(&dev->struct_mutex);
5074 if (nr_to_scan <= 0)
5078 /* second pass, evict/count anything still on the inactive list */
5079 list_for_each_entry_safe(dev_priv, next_dev,
5080 &shrink_list, mm.shrink_list) {
5081 struct drm_device *dev = dev_priv->dev;
5083 if (! mutex_trylock(&dev->struct_mutex))
5086 spin_unlock(&shrink_list_lock);
5088 list_for_each_entry_safe(obj_priv, next_obj,
5089 &dev_priv->mm.inactive_list,
5091 if (nr_to_scan > 0) {
5092 i915_gem_object_unbind(obj_priv->obj);
5098 spin_lock(&shrink_list_lock);
5099 mutex_unlock(&dev->struct_mutex);
5104 spin_unlock(&shrink_list_lock);
5109 return (cnt / 100) * sysctl_vfs_cache_pressure;
5114 static struct shrinker shrinker = {
5115 .shrink = i915_gem_shrink,
5116 .seeks = DEFAULT_SEEKS,
5120 i915_gem_shrinker_init(void)
5122 register_shrinker(&shrinker);
5126 i915_gem_shrinker_exit(void)
5128 unregister_shrinker(&shrinker);