2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/swap.h>
35 #include <linux/pci.h>
37 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
39 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
42 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
44 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
47 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
48 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
49 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
51 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
52 static int i915_gem_evict_something(struct drm_device *dev, int min_size);
53 static int i915_gem_evict_from_inactive_list(struct drm_device *dev);
54 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
55 struct drm_i915_gem_pwrite *args,
56 struct drm_file *file_priv);
58 static LIST_HEAD(shrink_list);
59 static DEFINE_SPINLOCK(shrink_list_lock);
61 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
64 drm_i915_private_t *dev_priv = dev->dev_private;
67 (start & (PAGE_SIZE - 1)) != 0 ||
68 (end & (PAGE_SIZE - 1)) != 0) {
72 drm_mm_init(&dev_priv->mm.gtt_space, start,
75 dev->gtt_total = (uint32_t) (end - start);
81 i915_gem_init_ioctl(struct drm_device *dev, void *data,
82 struct drm_file *file_priv)
84 struct drm_i915_gem_init *args = data;
87 mutex_lock(&dev->struct_mutex);
88 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
89 mutex_unlock(&dev->struct_mutex);
95 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
96 struct drm_file *file_priv)
98 struct drm_i915_gem_get_aperture *args = data;
100 if (!(dev->driver->driver_features & DRIVER_GEM))
103 args->aper_size = dev->gtt_total;
104 args->aper_available_size = (args->aper_size -
105 atomic_read(&dev->pin_memory));
112 * Creates a new mm object and returns a handle to it.
115 i915_gem_create_ioctl(struct drm_device *dev, void *data,
116 struct drm_file *file_priv)
118 struct drm_i915_gem_create *args = data;
119 struct drm_gem_object *obj;
123 args->size = roundup(args->size, PAGE_SIZE);
125 /* Allocate the new object */
126 obj = drm_gem_object_alloc(dev, args->size);
130 ret = drm_gem_handle_create(file_priv, obj, &handle);
131 mutex_lock(&dev->struct_mutex);
132 drm_gem_object_handle_unreference(obj);
133 mutex_unlock(&dev->struct_mutex);
138 args->handle = handle;
144 fast_shmem_read(struct page **pages,
145 loff_t page_base, int page_offset,
152 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
155 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
156 kunmap_atomic(vaddr, KM_USER0);
164 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
166 drm_i915_private_t *dev_priv = obj->dev->dev_private;
167 struct drm_i915_gem_object *obj_priv = obj->driver_private;
169 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
170 obj_priv->tiling_mode != I915_TILING_NONE;
174 slow_shmem_copy(struct page *dst_page,
176 struct page *src_page,
180 char *dst_vaddr, *src_vaddr;
182 dst_vaddr = kmap_atomic(dst_page, KM_USER0);
183 if (dst_vaddr == NULL)
186 src_vaddr = kmap_atomic(src_page, KM_USER1);
187 if (src_vaddr == NULL) {
188 kunmap_atomic(dst_vaddr, KM_USER0);
192 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
194 kunmap_atomic(src_vaddr, KM_USER1);
195 kunmap_atomic(dst_vaddr, KM_USER0);
201 slow_shmem_bit17_copy(struct page *gpu_page,
203 struct page *cpu_page,
208 char *gpu_vaddr, *cpu_vaddr;
210 /* Use the unswizzled path if this page isn't affected. */
211 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
213 return slow_shmem_copy(cpu_page, cpu_offset,
214 gpu_page, gpu_offset, length);
216 return slow_shmem_copy(gpu_page, gpu_offset,
217 cpu_page, cpu_offset, length);
220 gpu_vaddr = kmap_atomic(gpu_page, KM_USER0);
221 if (gpu_vaddr == NULL)
224 cpu_vaddr = kmap_atomic(cpu_page, KM_USER1);
225 if (cpu_vaddr == NULL) {
226 kunmap_atomic(gpu_vaddr, KM_USER0);
230 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
231 * XORing with the other bits (A9 for Y, A9 and A10 for X)
234 int cacheline_end = ALIGN(gpu_offset + 1, 64);
235 int this_length = min(cacheline_end - gpu_offset, length);
236 int swizzled_gpu_offset = gpu_offset ^ 64;
239 memcpy(cpu_vaddr + cpu_offset,
240 gpu_vaddr + swizzled_gpu_offset,
243 memcpy(gpu_vaddr + swizzled_gpu_offset,
244 cpu_vaddr + cpu_offset,
247 cpu_offset += this_length;
248 gpu_offset += this_length;
249 length -= this_length;
252 kunmap_atomic(cpu_vaddr, KM_USER1);
253 kunmap_atomic(gpu_vaddr, KM_USER0);
259 * This is the fast shmem pread path, which attempts to copy_from_user directly
260 * from the backing pages of the object to the user's address space. On a
261 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
264 i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
265 struct drm_i915_gem_pread *args,
266 struct drm_file *file_priv)
268 struct drm_i915_gem_object *obj_priv = obj->driver_private;
270 loff_t offset, page_base;
271 char __user *user_data;
272 int page_offset, page_length;
275 user_data = (char __user *) (uintptr_t) args->data_ptr;
278 mutex_lock(&dev->struct_mutex);
280 ret = i915_gem_object_get_pages(obj);
284 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
289 obj_priv = obj->driver_private;
290 offset = args->offset;
293 /* Operation in this page
295 * page_base = page offset within aperture
296 * page_offset = offset within page
297 * page_length = bytes to copy for this page
299 page_base = (offset & ~(PAGE_SIZE-1));
300 page_offset = offset & (PAGE_SIZE-1);
301 page_length = remain;
302 if ((page_offset + remain) > PAGE_SIZE)
303 page_length = PAGE_SIZE - page_offset;
305 ret = fast_shmem_read(obj_priv->pages,
306 page_base, page_offset,
307 user_data, page_length);
311 remain -= page_length;
312 user_data += page_length;
313 offset += page_length;
317 i915_gem_object_put_pages(obj);
319 mutex_unlock(&dev->struct_mutex);
325 i915_gem_object_get_page_gfp_mask (struct drm_gem_object *obj)
327 return mapping_gfp_mask(obj->filp->f_path.dentry->d_inode->i_mapping);
331 i915_gem_object_set_page_gfp_mask (struct drm_gem_object *obj, gfp_t gfp)
333 mapping_set_gfp_mask(obj->filp->f_path.dentry->d_inode->i_mapping, gfp);
337 i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
341 ret = i915_gem_object_get_pages(obj);
343 /* If we've insufficient memory to map in the pages, attempt
344 * to make some space by throwing out some old buffers.
346 if (ret == -ENOMEM) {
347 struct drm_device *dev = obj->dev;
350 ret = i915_gem_evict_something(dev, obj->size);
354 gfp = i915_gem_object_get_page_gfp_mask(obj);
355 i915_gem_object_set_page_gfp_mask(obj, gfp & ~__GFP_NORETRY);
356 ret = i915_gem_object_get_pages(obj);
357 i915_gem_object_set_page_gfp_mask (obj, gfp);
364 * This is the fallback shmem pread path, which allocates temporary storage
365 * in kernel space to copy_to_user into outside of the struct_mutex, so we
366 * can copy out of the object's backing pages while holding the struct mutex
367 * and not take page faults.
370 i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
371 struct drm_i915_gem_pread *args,
372 struct drm_file *file_priv)
374 struct drm_i915_gem_object *obj_priv = obj->driver_private;
375 struct mm_struct *mm = current->mm;
376 struct page **user_pages;
378 loff_t offset, pinned_pages, i;
379 loff_t first_data_page, last_data_page, num_pages;
380 int shmem_page_index, shmem_page_offset;
381 int data_page_index, data_page_offset;
384 uint64_t data_ptr = args->data_ptr;
385 int do_bit17_swizzling;
389 /* Pin the user pages containing the data. We can't fault while
390 * holding the struct mutex, yet we want to hold it while
391 * dereferencing the user data.
393 first_data_page = data_ptr / PAGE_SIZE;
394 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
395 num_pages = last_data_page - first_data_page + 1;
397 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
398 if (user_pages == NULL)
401 down_read(&mm->mmap_sem);
402 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
403 num_pages, 1, 0, user_pages, NULL);
404 up_read(&mm->mmap_sem);
405 if (pinned_pages < num_pages) {
407 goto fail_put_user_pages;
410 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
412 mutex_lock(&dev->struct_mutex);
414 ret = i915_gem_object_get_pages_or_evict(obj);
418 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
423 obj_priv = obj->driver_private;
424 offset = args->offset;
427 /* Operation in this page
429 * shmem_page_index = page number within shmem file
430 * shmem_page_offset = offset within page in shmem file
431 * data_page_index = page number in get_user_pages return
432 * data_page_offset = offset with data_page_index page.
433 * page_length = bytes to copy for this page
435 shmem_page_index = offset / PAGE_SIZE;
436 shmem_page_offset = offset & ~PAGE_MASK;
437 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
438 data_page_offset = data_ptr & ~PAGE_MASK;
440 page_length = remain;
441 if ((shmem_page_offset + page_length) > PAGE_SIZE)
442 page_length = PAGE_SIZE - shmem_page_offset;
443 if ((data_page_offset + page_length) > PAGE_SIZE)
444 page_length = PAGE_SIZE - data_page_offset;
446 if (do_bit17_swizzling) {
447 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
449 user_pages[data_page_index],
454 ret = slow_shmem_copy(user_pages[data_page_index],
456 obj_priv->pages[shmem_page_index],
463 remain -= page_length;
464 data_ptr += page_length;
465 offset += page_length;
469 i915_gem_object_put_pages(obj);
471 mutex_unlock(&dev->struct_mutex);
473 for (i = 0; i < pinned_pages; i++) {
474 SetPageDirty(user_pages[i]);
475 page_cache_release(user_pages[i]);
477 drm_free_large(user_pages);
483 * Reads data from the object referenced by handle.
485 * On error, the contents of *data are undefined.
488 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
489 struct drm_file *file_priv)
491 struct drm_i915_gem_pread *args = data;
492 struct drm_gem_object *obj;
493 struct drm_i915_gem_object *obj_priv;
496 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
499 obj_priv = obj->driver_private;
501 /* Bounds check source.
503 * XXX: This could use review for overflow issues...
505 if (args->offset > obj->size || args->size > obj->size ||
506 args->offset + args->size > obj->size) {
507 drm_gem_object_unreference(obj);
511 if (i915_gem_object_needs_bit17_swizzle(obj)) {
512 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
514 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
516 ret = i915_gem_shmem_pread_slow(dev, obj, args,
520 drm_gem_object_unreference(obj);
525 /* This is the fast write path which cannot handle
526 * page faults in the source data
530 fast_user_write(struct io_mapping *mapping,
531 loff_t page_base, int page_offset,
532 char __user *user_data,
536 unsigned long unwritten;
538 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
539 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
541 io_mapping_unmap_atomic(vaddr_atomic);
547 /* Here's the write path which can sleep for
552 slow_kernel_write(struct io_mapping *mapping,
553 loff_t gtt_base, int gtt_offset,
554 struct page *user_page, int user_offset,
557 char *src_vaddr, *dst_vaddr;
558 unsigned long unwritten;
560 dst_vaddr = io_mapping_map_atomic_wc(mapping, gtt_base);
561 src_vaddr = kmap_atomic(user_page, KM_USER1);
562 unwritten = __copy_from_user_inatomic_nocache(dst_vaddr + gtt_offset,
563 src_vaddr + user_offset,
565 kunmap_atomic(src_vaddr, KM_USER1);
566 io_mapping_unmap_atomic(dst_vaddr);
573 fast_shmem_write(struct page **pages,
574 loff_t page_base, int page_offset,
579 unsigned long unwritten;
581 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
584 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
585 kunmap_atomic(vaddr, KM_USER0);
593 * This is the fast pwrite path, where we copy the data directly from the
594 * user into the GTT, uncached.
597 i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
598 struct drm_i915_gem_pwrite *args,
599 struct drm_file *file_priv)
601 struct drm_i915_gem_object *obj_priv = obj->driver_private;
602 drm_i915_private_t *dev_priv = dev->dev_private;
604 loff_t offset, page_base;
605 char __user *user_data;
606 int page_offset, page_length;
609 user_data = (char __user *) (uintptr_t) args->data_ptr;
611 if (!access_ok(VERIFY_READ, user_data, remain))
615 mutex_lock(&dev->struct_mutex);
616 ret = i915_gem_object_pin(obj, 0);
618 mutex_unlock(&dev->struct_mutex);
621 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
625 obj_priv = obj->driver_private;
626 offset = obj_priv->gtt_offset + args->offset;
629 /* Operation in this page
631 * page_base = page offset within aperture
632 * page_offset = offset within page
633 * page_length = bytes to copy for this page
635 page_base = (offset & ~(PAGE_SIZE-1));
636 page_offset = offset & (PAGE_SIZE-1);
637 page_length = remain;
638 if ((page_offset + remain) > PAGE_SIZE)
639 page_length = PAGE_SIZE - page_offset;
641 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
642 page_offset, user_data, page_length);
644 /* If we get a fault while copying data, then (presumably) our
645 * source page isn't available. Return the error and we'll
646 * retry in the slow path.
651 remain -= page_length;
652 user_data += page_length;
653 offset += page_length;
657 i915_gem_object_unpin(obj);
658 mutex_unlock(&dev->struct_mutex);
664 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
665 * the memory and maps it using kmap_atomic for copying.
667 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
668 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
671 i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
672 struct drm_i915_gem_pwrite *args,
673 struct drm_file *file_priv)
675 struct drm_i915_gem_object *obj_priv = obj->driver_private;
676 drm_i915_private_t *dev_priv = dev->dev_private;
678 loff_t gtt_page_base, offset;
679 loff_t first_data_page, last_data_page, num_pages;
680 loff_t pinned_pages, i;
681 struct page **user_pages;
682 struct mm_struct *mm = current->mm;
683 int gtt_page_offset, data_page_offset, data_page_index, page_length;
685 uint64_t data_ptr = args->data_ptr;
689 /* Pin the user pages containing the data. We can't fault while
690 * holding the struct mutex, and all of the pwrite implementations
691 * want to hold it while dereferencing the user data.
693 first_data_page = data_ptr / PAGE_SIZE;
694 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
695 num_pages = last_data_page - first_data_page + 1;
697 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
698 if (user_pages == NULL)
701 down_read(&mm->mmap_sem);
702 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
703 num_pages, 0, 0, user_pages, NULL);
704 up_read(&mm->mmap_sem);
705 if (pinned_pages < num_pages) {
707 goto out_unpin_pages;
710 mutex_lock(&dev->struct_mutex);
711 ret = i915_gem_object_pin(obj, 0);
715 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
717 goto out_unpin_object;
719 obj_priv = obj->driver_private;
720 offset = obj_priv->gtt_offset + args->offset;
723 /* Operation in this page
725 * gtt_page_base = page offset within aperture
726 * gtt_page_offset = offset within page in aperture
727 * data_page_index = page number in get_user_pages return
728 * data_page_offset = offset with data_page_index page.
729 * page_length = bytes to copy for this page
731 gtt_page_base = offset & PAGE_MASK;
732 gtt_page_offset = offset & ~PAGE_MASK;
733 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
734 data_page_offset = data_ptr & ~PAGE_MASK;
736 page_length = remain;
737 if ((gtt_page_offset + page_length) > PAGE_SIZE)
738 page_length = PAGE_SIZE - gtt_page_offset;
739 if ((data_page_offset + page_length) > PAGE_SIZE)
740 page_length = PAGE_SIZE - data_page_offset;
742 ret = slow_kernel_write(dev_priv->mm.gtt_mapping,
743 gtt_page_base, gtt_page_offset,
744 user_pages[data_page_index],
748 /* If we get a fault while copying data, then (presumably) our
749 * source page isn't available. Return the error and we'll
750 * retry in the slow path.
753 goto out_unpin_object;
755 remain -= page_length;
756 offset += page_length;
757 data_ptr += page_length;
761 i915_gem_object_unpin(obj);
763 mutex_unlock(&dev->struct_mutex);
765 for (i = 0; i < pinned_pages; i++)
766 page_cache_release(user_pages[i]);
767 drm_free_large(user_pages);
773 * This is the fast shmem pwrite path, which attempts to directly
774 * copy_from_user into the kmapped pages backing the object.
777 i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
778 struct drm_i915_gem_pwrite *args,
779 struct drm_file *file_priv)
781 struct drm_i915_gem_object *obj_priv = obj->driver_private;
783 loff_t offset, page_base;
784 char __user *user_data;
785 int page_offset, page_length;
788 user_data = (char __user *) (uintptr_t) args->data_ptr;
791 mutex_lock(&dev->struct_mutex);
793 ret = i915_gem_object_get_pages(obj);
797 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
801 obj_priv = obj->driver_private;
802 offset = args->offset;
806 /* Operation in this page
808 * page_base = page offset within aperture
809 * page_offset = offset within page
810 * page_length = bytes to copy for this page
812 page_base = (offset & ~(PAGE_SIZE-1));
813 page_offset = offset & (PAGE_SIZE-1);
814 page_length = remain;
815 if ((page_offset + remain) > PAGE_SIZE)
816 page_length = PAGE_SIZE - page_offset;
818 ret = fast_shmem_write(obj_priv->pages,
819 page_base, page_offset,
820 user_data, page_length);
824 remain -= page_length;
825 user_data += page_length;
826 offset += page_length;
830 i915_gem_object_put_pages(obj);
832 mutex_unlock(&dev->struct_mutex);
838 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
839 * the memory and maps it using kmap_atomic for copying.
841 * This avoids taking mmap_sem for faulting on the user's address while the
842 * struct_mutex is held.
845 i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
846 struct drm_i915_gem_pwrite *args,
847 struct drm_file *file_priv)
849 struct drm_i915_gem_object *obj_priv = obj->driver_private;
850 struct mm_struct *mm = current->mm;
851 struct page **user_pages;
853 loff_t offset, pinned_pages, i;
854 loff_t first_data_page, last_data_page, num_pages;
855 int shmem_page_index, shmem_page_offset;
856 int data_page_index, data_page_offset;
859 uint64_t data_ptr = args->data_ptr;
860 int do_bit17_swizzling;
864 /* Pin the user pages containing the data. We can't fault while
865 * holding the struct mutex, and all of the pwrite implementations
866 * want to hold it while dereferencing the user data.
868 first_data_page = data_ptr / PAGE_SIZE;
869 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
870 num_pages = last_data_page - first_data_page + 1;
872 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
873 if (user_pages == NULL)
876 down_read(&mm->mmap_sem);
877 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
878 num_pages, 0, 0, user_pages, NULL);
879 up_read(&mm->mmap_sem);
880 if (pinned_pages < num_pages) {
882 goto fail_put_user_pages;
885 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
887 mutex_lock(&dev->struct_mutex);
889 ret = i915_gem_object_get_pages_or_evict(obj);
893 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
897 obj_priv = obj->driver_private;
898 offset = args->offset;
902 /* Operation in this page
904 * shmem_page_index = page number within shmem file
905 * shmem_page_offset = offset within page in shmem file
906 * data_page_index = page number in get_user_pages return
907 * data_page_offset = offset with data_page_index page.
908 * page_length = bytes to copy for this page
910 shmem_page_index = offset / PAGE_SIZE;
911 shmem_page_offset = offset & ~PAGE_MASK;
912 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
913 data_page_offset = data_ptr & ~PAGE_MASK;
915 page_length = remain;
916 if ((shmem_page_offset + page_length) > PAGE_SIZE)
917 page_length = PAGE_SIZE - shmem_page_offset;
918 if ((data_page_offset + page_length) > PAGE_SIZE)
919 page_length = PAGE_SIZE - data_page_offset;
921 if (do_bit17_swizzling) {
922 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
924 user_pages[data_page_index],
929 ret = slow_shmem_copy(obj_priv->pages[shmem_page_index],
931 user_pages[data_page_index],
938 remain -= page_length;
939 data_ptr += page_length;
940 offset += page_length;
944 i915_gem_object_put_pages(obj);
946 mutex_unlock(&dev->struct_mutex);
948 for (i = 0; i < pinned_pages; i++)
949 page_cache_release(user_pages[i]);
950 drm_free_large(user_pages);
956 * Writes data to the object referenced by handle.
958 * On error, the contents of the buffer that were to be modified are undefined.
961 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
962 struct drm_file *file_priv)
964 struct drm_i915_gem_pwrite *args = data;
965 struct drm_gem_object *obj;
966 struct drm_i915_gem_object *obj_priv;
969 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
972 obj_priv = obj->driver_private;
974 /* Bounds check destination.
976 * XXX: This could use review for overflow issues...
978 if (args->offset > obj->size || args->size > obj->size ||
979 args->offset + args->size > obj->size) {
980 drm_gem_object_unreference(obj);
984 /* We can only do the GTT pwrite on untiled buffers, as otherwise
985 * it would end up going through the fenced access, and we'll get
986 * different detiling behavior between reading and writing.
987 * pread/pwrite currently are reading and writing from the CPU
988 * perspective, requiring manual detiling by the client.
990 if (obj_priv->phys_obj)
991 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
992 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
993 dev->gtt_total != 0) {
994 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
995 if (ret == -EFAULT) {
996 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
999 } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
1000 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
1002 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
1003 if (ret == -EFAULT) {
1004 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
1011 DRM_INFO("pwrite failed %d\n", ret);
1014 drm_gem_object_unreference(obj);
1020 * Called when user space prepares to use an object with the CPU, either
1021 * through the mmap ioctl's mapping or a GTT mapping.
1024 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1025 struct drm_file *file_priv)
1027 struct drm_i915_private *dev_priv = dev->dev_private;
1028 struct drm_i915_gem_set_domain *args = data;
1029 struct drm_gem_object *obj;
1030 struct drm_i915_gem_object *obj_priv;
1031 uint32_t read_domains = args->read_domains;
1032 uint32_t write_domain = args->write_domain;
1035 if (!(dev->driver->driver_features & DRIVER_GEM))
1038 /* Only handle setting domains to types used by the CPU. */
1039 if (write_domain & I915_GEM_GPU_DOMAINS)
1042 if (read_domains & I915_GEM_GPU_DOMAINS)
1045 /* Having something in the write domain implies it's in the read
1046 * domain, and only that read domain. Enforce that in the request.
1048 if (write_domain != 0 && read_domains != write_domain)
1051 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1054 obj_priv = obj->driver_private;
1056 mutex_lock(&dev->struct_mutex);
1058 intel_mark_busy(dev, obj);
1061 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1062 obj, obj->size, read_domains, write_domain);
1064 if (read_domains & I915_GEM_DOMAIN_GTT) {
1065 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1067 /* Update the LRU on the fence for the CPU access that's
1070 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1071 list_move_tail(&obj_priv->fence_list,
1072 &dev_priv->mm.fence_list);
1075 /* Silently promote "you're not bound, there was nothing to do"
1076 * to success, since the client was just asking us to
1077 * make sure everything was done.
1082 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1085 drm_gem_object_unreference(obj);
1086 mutex_unlock(&dev->struct_mutex);
1091 * Called when user space has done writes to this buffer
1094 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1095 struct drm_file *file_priv)
1097 struct drm_i915_gem_sw_finish *args = data;
1098 struct drm_gem_object *obj;
1099 struct drm_i915_gem_object *obj_priv;
1102 if (!(dev->driver->driver_features & DRIVER_GEM))
1105 mutex_lock(&dev->struct_mutex);
1106 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1108 mutex_unlock(&dev->struct_mutex);
1113 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1114 __func__, args->handle, obj, obj->size);
1116 obj_priv = obj->driver_private;
1118 /* Pinned buffers may be scanout, so flush the cache */
1119 if (obj_priv->pin_count)
1120 i915_gem_object_flush_cpu_write_domain(obj);
1122 drm_gem_object_unreference(obj);
1123 mutex_unlock(&dev->struct_mutex);
1128 * Maps the contents of an object, returning the address it is mapped
1131 * While the mapping holds a reference on the contents of the object, it doesn't
1132 * imply a ref on the object itself.
1135 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1136 struct drm_file *file_priv)
1138 struct drm_i915_gem_mmap *args = data;
1139 struct drm_gem_object *obj;
1143 if (!(dev->driver->driver_features & DRIVER_GEM))
1146 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1150 offset = args->offset;
1152 down_write(¤t->mm->mmap_sem);
1153 addr = do_mmap(obj->filp, 0, args->size,
1154 PROT_READ | PROT_WRITE, MAP_SHARED,
1156 up_write(¤t->mm->mmap_sem);
1157 mutex_lock(&dev->struct_mutex);
1158 drm_gem_object_unreference(obj);
1159 mutex_unlock(&dev->struct_mutex);
1160 if (IS_ERR((void *)addr))
1163 args->addr_ptr = (uint64_t) addr;
1169 * i915_gem_fault - fault a page into the GTT
1170 * vma: VMA in question
1173 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1174 * from userspace. The fault handler takes care of binding the object to
1175 * the GTT (if needed), allocating and programming a fence register (again,
1176 * only if needed based on whether the old reg is still valid or the object
1177 * is tiled) and inserting a new PTE into the faulting process.
1179 * Note that the faulting process may involve evicting existing objects
1180 * from the GTT and/or fence registers to make room. So performance may
1181 * suffer if the GTT working set is large or there are few fence registers
1184 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1186 struct drm_gem_object *obj = vma->vm_private_data;
1187 struct drm_device *dev = obj->dev;
1188 struct drm_i915_private *dev_priv = dev->dev_private;
1189 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1190 pgoff_t page_offset;
1193 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1195 /* We don't use vmf->pgoff since that has the fake offset */
1196 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1199 /* Now bind it into the GTT if needed */
1200 mutex_lock(&dev->struct_mutex);
1201 if (!obj_priv->gtt_space) {
1202 ret = i915_gem_object_bind_to_gtt(obj, 0);
1204 mutex_unlock(&dev->struct_mutex);
1205 return VM_FAULT_SIGBUS;
1207 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1209 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1211 mutex_unlock(&dev->struct_mutex);
1212 return VM_FAULT_SIGBUS;
1216 /* Need a new fence register? */
1217 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1218 ret = i915_gem_object_get_fence_reg(obj);
1220 mutex_unlock(&dev->struct_mutex);
1221 return VM_FAULT_SIGBUS;
1225 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1228 /* Finally, remap it using the new GTT offset */
1229 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1231 mutex_unlock(&dev->struct_mutex);
1236 return VM_FAULT_OOM;
1239 return VM_FAULT_SIGBUS;
1241 return VM_FAULT_NOPAGE;
1246 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1247 * @obj: obj in question
1249 * GEM memory mapping works by handing back to userspace a fake mmap offset
1250 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1251 * up the object based on the offset and sets up the various memory mapping
1254 * This routine allocates and attaches a fake offset for @obj.
1257 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1259 struct drm_device *dev = obj->dev;
1260 struct drm_gem_mm *mm = dev->mm_private;
1261 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1262 struct drm_map_list *list;
1263 struct drm_local_map *map;
1266 /* Set the object up for mmap'ing */
1267 list = &obj->map_list;
1268 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1273 map->type = _DRM_GEM;
1274 map->size = obj->size;
1277 /* Get a DRM GEM mmap offset allocated... */
1278 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1279 obj->size / PAGE_SIZE, 0, 0);
1280 if (!list->file_offset_node) {
1281 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1286 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1287 obj->size / PAGE_SIZE, 0);
1288 if (!list->file_offset_node) {
1293 list->hash.key = list->file_offset_node->start;
1294 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1295 DRM_ERROR("failed to add to map hash\n");
1299 /* By now we should be all set, any drm_mmap request on the offset
1300 * below will get to our mmap & fault handler */
1301 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1306 drm_mm_put_block(list->file_offset_node);
1314 * i915_gem_release_mmap - remove physical page mappings
1315 * @obj: obj in question
1317 * Preserve the reservation of the mmaping with the DRM core code, but
1318 * relinquish ownership of the pages back to the system.
1320 * It is vital that we remove the page mapping if we have mapped a tiled
1321 * object through the GTT and then lose the fence register due to
1322 * resource pressure. Similarly if the object has been moved out of the
1323 * aperture, than pages mapped into userspace must be revoked. Removing the
1324 * mapping will then trigger a page fault on the next user access, allowing
1325 * fixup by i915_gem_fault().
1328 i915_gem_release_mmap(struct drm_gem_object *obj)
1330 struct drm_device *dev = obj->dev;
1331 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1333 if (dev->dev_mapping)
1334 unmap_mapping_range(dev->dev_mapping,
1335 obj_priv->mmap_offset, obj->size, 1);
1339 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1341 struct drm_device *dev = obj->dev;
1342 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1343 struct drm_gem_mm *mm = dev->mm_private;
1344 struct drm_map_list *list;
1346 list = &obj->map_list;
1347 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1349 if (list->file_offset_node) {
1350 drm_mm_put_block(list->file_offset_node);
1351 list->file_offset_node = NULL;
1359 obj_priv->mmap_offset = 0;
1363 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1364 * @obj: object to check
1366 * Return the required GTT alignment for an object, taking into account
1367 * potential fence register mapping if needed.
1370 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1372 struct drm_device *dev = obj->dev;
1373 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1377 * Minimum alignment is 4k (GTT page size), but might be greater
1378 * if a fence register is needed for the object.
1380 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1384 * Previous chips need to be aligned to the size of the smallest
1385 * fence register that can contain the object.
1392 for (i = start; i < obj->size; i <<= 1)
1399 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1401 * @data: GTT mapping ioctl data
1402 * @file_priv: GEM object info
1404 * Simply returns the fake offset to userspace so it can mmap it.
1405 * The mmap call will end up in drm_gem_mmap(), which will set things
1406 * up so we can get faults in the handler above.
1408 * The fault handler will take care of binding the object into the GTT
1409 * (since it may have been evicted to make room for something), allocating
1410 * a fence register, and mapping the appropriate aperture address into
1414 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1415 struct drm_file *file_priv)
1417 struct drm_i915_gem_mmap_gtt *args = data;
1418 struct drm_i915_private *dev_priv = dev->dev_private;
1419 struct drm_gem_object *obj;
1420 struct drm_i915_gem_object *obj_priv;
1423 if (!(dev->driver->driver_features & DRIVER_GEM))
1426 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1430 mutex_lock(&dev->struct_mutex);
1432 obj_priv = obj->driver_private;
1434 if (!obj_priv->mmap_offset) {
1435 ret = i915_gem_create_mmap_offset(obj);
1437 drm_gem_object_unreference(obj);
1438 mutex_unlock(&dev->struct_mutex);
1443 args->offset = obj_priv->mmap_offset;
1446 * Pull it into the GTT so that we have a page list (makes the
1447 * initial fault faster and any subsequent flushing possible).
1449 if (!obj_priv->agp_mem) {
1450 ret = i915_gem_object_bind_to_gtt(obj, 0);
1452 drm_gem_object_unreference(obj);
1453 mutex_unlock(&dev->struct_mutex);
1456 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1459 drm_gem_object_unreference(obj);
1460 mutex_unlock(&dev->struct_mutex);
1466 i915_gem_object_put_pages(struct drm_gem_object *obj)
1468 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1469 int page_count = obj->size / PAGE_SIZE;
1472 BUG_ON(obj_priv->pages_refcount == 0);
1474 if (--obj_priv->pages_refcount != 0)
1477 if (obj_priv->tiling_mode != I915_TILING_NONE)
1478 i915_gem_object_save_bit_17_swizzle(obj);
1480 if (obj_priv->madv == I915_MADV_DONTNEED)
1481 obj_priv->dirty = 0;
1483 for (i = 0; i < page_count; i++) {
1484 if (obj_priv->pages[i] == NULL)
1487 if (obj_priv->dirty)
1488 set_page_dirty(obj_priv->pages[i]);
1490 if (obj_priv->madv == I915_MADV_WILLNEED)
1491 mark_page_accessed(obj_priv->pages[i]);
1493 page_cache_release(obj_priv->pages[i]);
1495 obj_priv->dirty = 0;
1497 drm_free_large(obj_priv->pages);
1498 obj_priv->pages = NULL;
1502 i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
1504 struct drm_device *dev = obj->dev;
1505 drm_i915_private_t *dev_priv = dev->dev_private;
1506 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1508 /* Add a reference if we're newly entering the active list. */
1509 if (!obj_priv->active) {
1510 drm_gem_object_reference(obj);
1511 obj_priv->active = 1;
1513 /* Move from whatever list we were on to the tail of execution. */
1514 spin_lock(&dev_priv->mm.active_list_lock);
1515 list_move_tail(&obj_priv->list,
1516 &dev_priv->mm.active_list);
1517 spin_unlock(&dev_priv->mm.active_list_lock);
1518 obj_priv->last_rendering_seqno = seqno;
1522 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1524 struct drm_device *dev = obj->dev;
1525 drm_i915_private_t *dev_priv = dev->dev_private;
1526 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1528 BUG_ON(!obj_priv->active);
1529 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1530 obj_priv->last_rendering_seqno = 0;
1533 /* Immediately discard the backing storage */
1535 i915_gem_object_truncate(struct drm_gem_object *obj)
1537 struct inode *inode;
1539 inode = obj->filp->f_path.dentry->d_inode;
1540 if (inode->i_op->truncate)
1541 inode->i_op->truncate (inode);
1545 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1547 return obj_priv->madv == I915_MADV_DONTNEED;
1551 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1553 struct drm_device *dev = obj->dev;
1554 drm_i915_private_t *dev_priv = dev->dev_private;
1555 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1557 i915_verify_inactive(dev, __FILE__, __LINE__);
1558 if (obj_priv->pin_count != 0)
1559 list_del_init(&obj_priv->list);
1561 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1563 obj_priv->last_rendering_seqno = 0;
1564 if (obj_priv->active) {
1565 obj_priv->active = 0;
1566 drm_gem_object_unreference(obj);
1568 i915_verify_inactive(dev, __FILE__, __LINE__);
1572 * Creates a new sequence number, emitting a write of it to the status page
1573 * plus an interrupt, which will trigger i915_user_interrupt_handler.
1575 * Must be called with struct_lock held.
1577 * Returned sequence numbers are nonzero on success.
1580 i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1581 uint32_t flush_domains)
1583 drm_i915_private_t *dev_priv = dev->dev_private;
1584 struct drm_i915_file_private *i915_file_priv = NULL;
1585 struct drm_i915_gem_request *request;
1590 if (file_priv != NULL)
1591 i915_file_priv = file_priv->driver_priv;
1593 request = kzalloc(sizeof(*request), GFP_KERNEL);
1594 if (request == NULL)
1597 /* Grab the seqno we're going to make this request be, and bump the
1598 * next (skipping 0 so it can be the reserved no-seqno value).
1600 seqno = dev_priv->mm.next_gem_seqno;
1601 dev_priv->mm.next_gem_seqno++;
1602 if (dev_priv->mm.next_gem_seqno == 0)
1603 dev_priv->mm.next_gem_seqno++;
1606 OUT_RING(MI_STORE_DWORD_INDEX);
1607 OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1610 OUT_RING(MI_USER_INTERRUPT);
1613 DRM_DEBUG("%d\n", seqno);
1615 request->seqno = seqno;
1616 request->emitted_jiffies = jiffies;
1617 was_empty = list_empty(&dev_priv->mm.request_list);
1618 list_add_tail(&request->list, &dev_priv->mm.request_list);
1619 if (i915_file_priv) {
1620 list_add_tail(&request->client_list,
1621 &i915_file_priv->mm.request_list);
1623 INIT_LIST_HEAD(&request->client_list);
1626 /* Associate any objects on the flushing list matching the write
1627 * domain we're flushing with our flush.
1629 if (flush_domains != 0) {
1630 struct drm_i915_gem_object *obj_priv, *next;
1632 list_for_each_entry_safe(obj_priv, next,
1633 &dev_priv->mm.flushing_list, list) {
1634 struct drm_gem_object *obj = obj_priv->obj;
1636 if ((obj->write_domain & flush_domains) ==
1637 obj->write_domain) {
1638 uint32_t old_write_domain = obj->write_domain;
1640 obj->write_domain = 0;
1641 i915_gem_object_move_to_active(obj, seqno);
1643 trace_i915_gem_object_change_domain(obj,
1651 if (!dev_priv->mm.suspended) {
1652 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1654 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1660 * Command execution barrier
1662 * Ensures that all commands in the ring are finished
1663 * before signalling the CPU
1666 i915_retire_commands(struct drm_device *dev)
1668 drm_i915_private_t *dev_priv = dev->dev_private;
1669 uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1670 uint32_t flush_domains = 0;
1673 /* The sampler always gets flushed on i965 (sigh) */
1675 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1678 OUT_RING(0); /* noop */
1680 return flush_domains;
1684 * Moves buffers associated only with the given active seqno from the active
1685 * to inactive list, potentially freeing them.
1688 i915_gem_retire_request(struct drm_device *dev,
1689 struct drm_i915_gem_request *request)
1691 drm_i915_private_t *dev_priv = dev->dev_private;
1693 trace_i915_gem_request_retire(dev, request->seqno);
1695 /* Move any buffers on the active list that are no longer referenced
1696 * by the ringbuffer to the flushing/inactive lists as appropriate.
1698 spin_lock(&dev_priv->mm.active_list_lock);
1699 while (!list_empty(&dev_priv->mm.active_list)) {
1700 struct drm_gem_object *obj;
1701 struct drm_i915_gem_object *obj_priv;
1703 obj_priv = list_first_entry(&dev_priv->mm.active_list,
1704 struct drm_i915_gem_object,
1706 obj = obj_priv->obj;
1708 /* If the seqno being retired doesn't match the oldest in the
1709 * list, then the oldest in the list must still be newer than
1712 if (obj_priv->last_rendering_seqno != request->seqno)
1716 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1717 __func__, request->seqno, obj);
1720 if (obj->write_domain != 0)
1721 i915_gem_object_move_to_flushing(obj);
1723 /* Take a reference on the object so it won't be
1724 * freed while the spinlock is held. The list
1725 * protection for this spinlock is safe when breaking
1726 * the lock like this since the next thing we do
1727 * is just get the head of the list again.
1729 drm_gem_object_reference(obj);
1730 i915_gem_object_move_to_inactive(obj);
1731 spin_unlock(&dev_priv->mm.active_list_lock);
1732 drm_gem_object_unreference(obj);
1733 spin_lock(&dev_priv->mm.active_list_lock);
1737 spin_unlock(&dev_priv->mm.active_list_lock);
1741 * Returns true if seq1 is later than seq2.
1744 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1746 return (int32_t)(seq1 - seq2) >= 0;
1750 i915_get_gem_seqno(struct drm_device *dev)
1752 drm_i915_private_t *dev_priv = dev->dev_private;
1754 return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
1758 * This function clears the request list as sequence numbers are passed.
1761 i915_gem_retire_requests(struct drm_device *dev)
1763 drm_i915_private_t *dev_priv = dev->dev_private;
1766 if (!dev_priv->hw_status_page)
1769 seqno = i915_get_gem_seqno(dev);
1771 while (!list_empty(&dev_priv->mm.request_list)) {
1772 struct drm_i915_gem_request *request;
1773 uint32_t retiring_seqno;
1775 request = list_first_entry(&dev_priv->mm.request_list,
1776 struct drm_i915_gem_request,
1778 retiring_seqno = request->seqno;
1780 if (i915_seqno_passed(seqno, retiring_seqno) ||
1781 atomic_read(&dev_priv->mm.wedged)) {
1782 i915_gem_retire_request(dev, request);
1784 list_del(&request->list);
1785 list_del(&request->client_list);
1793 i915_gem_retire_work_handler(struct work_struct *work)
1795 drm_i915_private_t *dev_priv;
1796 struct drm_device *dev;
1798 dev_priv = container_of(work, drm_i915_private_t,
1799 mm.retire_work.work);
1800 dev = dev_priv->dev;
1802 mutex_lock(&dev->struct_mutex);
1803 i915_gem_retire_requests(dev);
1804 if (!dev_priv->mm.suspended &&
1805 !list_empty(&dev_priv->mm.request_list))
1806 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1807 mutex_unlock(&dev->struct_mutex);
1811 * Waits for a sequence number to be signaled, and cleans up the
1812 * request and object lists appropriately for that event.
1815 i915_wait_request(struct drm_device *dev, uint32_t seqno)
1817 drm_i915_private_t *dev_priv = dev->dev_private;
1823 if (atomic_read(&dev_priv->mm.wedged))
1826 if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
1828 ier = I915_READ(DEIER) | I915_READ(GTIER);
1830 ier = I915_READ(IER);
1832 DRM_ERROR("something (likely vbetool) disabled "
1833 "interrupts, re-enabling\n");
1834 i915_driver_irq_preinstall(dev);
1835 i915_driver_irq_postinstall(dev);
1838 trace_i915_gem_request_wait_begin(dev, seqno);
1840 dev_priv->mm.waiting_gem_seqno = seqno;
1841 i915_user_irq_get(dev);
1842 ret = wait_event_interruptible(dev_priv->irq_queue,
1843 i915_seqno_passed(i915_get_gem_seqno(dev),
1845 atomic_read(&dev_priv->mm.wedged));
1846 i915_user_irq_put(dev);
1847 dev_priv->mm.waiting_gem_seqno = 0;
1849 trace_i915_gem_request_wait_end(dev, seqno);
1851 if (atomic_read(&dev_priv->mm.wedged))
1854 if (ret && ret != -ERESTARTSYS)
1855 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1856 __func__, ret, seqno, i915_get_gem_seqno(dev));
1858 /* Directly dispatch request retiring. While we have the work queue
1859 * to handle this, the waiter on a request often wants an associated
1860 * buffer to have made it to the inactive list, and we would need
1861 * a separate wait queue to handle that.
1864 i915_gem_retire_requests(dev);
1870 i915_gem_flush(struct drm_device *dev,
1871 uint32_t invalidate_domains,
1872 uint32_t flush_domains)
1874 drm_i915_private_t *dev_priv = dev->dev_private;
1879 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
1880 invalidate_domains, flush_domains);
1882 trace_i915_gem_request_flush(dev, dev_priv->mm.next_gem_seqno,
1883 invalidate_domains, flush_domains);
1885 if (flush_domains & I915_GEM_DOMAIN_CPU)
1886 drm_agp_chipset_flush(dev);
1888 if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
1890 * read/write caches:
1892 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1893 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
1894 * also flushed at 2d versus 3d pipeline switches.
1898 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1899 * MI_READ_FLUSH is set, and is always flushed on 965.
1901 * I915_GEM_DOMAIN_COMMAND may not exist?
1903 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1904 * invalidated when MI_EXE_FLUSH is set.
1906 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1907 * invalidated with every MI_FLUSH.
1911 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1912 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1913 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1914 * are flushed at any MI_FLUSH.
1917 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1918 if ((invalidate_domains|flush_domains) &
1919 I915_GEM_DOMAIN_RENDER)
1920 cmd &= ~MI_NO_WRITE_FLUSH;
1921 if (!IS_I965G(dev)) {
1923 * On the 965, the sampler cache always gets flushed
1924 * and this bit is reserved.
1926 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
1927 cmd |= MI_READ_FLUSH;
1929 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
1930 cmd |= MI_EXE_FLUSH;
1933 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
1937 OUT_RING(0); /* noop */
1943 * Ensures that all rendering to the object has completed and the object is
1944 * safe to unbind from the GTT or access from the CPU.
1947 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1949 struct drm_device *dev = obj->dev;
1950 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1953 /* This function only exists to support waiting for existing rendering,
1954 * not for emitting required flushes.
1956 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
1958 /* If there is rendering queued on the buffer being evicted, wait for
1961 if (obj_priv->active) {
1963 DRM_INFO("%s: object %p wait for seqno %08x\n",
1964 __func__, obj, obj_priv->last_rendering_seqno);
1966 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
1975 * Unbinds an object from the GTT aperture.
1978 i915_gem_object_unbind(struct drm_gem_object *obj)
1980 struct drm_device *dev = obj->dev;
1981 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1985 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1986 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1988 if (obj_priv->gtt_space == NULL)
1991 if (obj_priv->pin_count != 0) {
1992 DRM_ERROR("Attempting to unbind pinned buffer\n");
1996 /* blow away mappings if mapped through GTT */
1997 i915_gem_release_mmap(obj);
1999 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
2000 i915_gem_clear_fence_reg(obj);
2002 /* Move the object to the CPU domain to ensure that
2003 * any possible CPU writes while it's not in the GTT
2004 * are flushed when we go to remap it. This will
2005 * also ensure that all pending GPU writes are finished
2008 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2010 if (ret != -ERESTARTSYS)
2011 DRM_ERROR("set_domain failed: %d\n", ret);
2015 BUG_ON(obj_priv->active);
2017 if (obj_priv->agp_mem != NULL) {
2018 drm_unbind_agp(obj_priv->agp_mem);
2019 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
2020 obj_priv->agp_mem = NULL;
2023 i915_gem_object_put_pages(obj);
2024 BUG_ON(obj_priv->pages_refcount);
2026 if (obj_priv->gtt_space) {
2027 atomic_dec(&dev->gtt_count);
2028 atomic_sub(obj->size, &dev->gtt_memory);
2030 drm_mm_put_block(obj_priv->gtt_space);
2031 obj_priv->gtt_space = NULL;
2034 /* Remove ourselves from the LRU list if present. */
2035 if (!list_empty(&obj_priv->list))
2036 list_del_init(&obj_priv->list);
2038 if (i915_gem_object_is_purgeable(obj_priv))
2039 i915_gem_object_truncate(obj);
2041 trace_i915_gem_object_unbind(obj);
2046 static struct drm_gem_object *
2047 i915_gem_find_inactive_object(struct drm_device *dev, int min_size)
2049 drm_i915_private_t *dev_priv = dev->dev_private;
2050 struct drm_i915_gem_object *obj_priv;
2051 struct drm_gem_object *best = NULL;
2052 struct drm_gem_object *first = NULL;
2054 /* Try to find the smallest clean object */
2055 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
2056 struct drm_gem_object *obj = obj_priv->obj;
2057 if (obj->size >= min_size) {
2058 if ((!obj_priv->dirty ||
2059 i915_gem_object_is_purgeable(obj_priv)) &&
2060 (!best || obj->size < best->size)) {
2062 if (best->size == min_size)
2070 return best ? best : first;
2074 i915_gem_evict_everything(struct drm_device *dev)
2076 drm_i915_private_t *dev_priv = dev->dev_private;
2081 spin_lock(&dev_priv->mm.active_list_lock);
2082 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2083 list_empty(&dev_priv->mm.flushing_list) &&
2084 list_empty(&dev_priv->mm.active_list));
2085 spin_unlock(&dev_priv->mm.active_list_lock);
2090 /* Flush everything (on to the inactive lists) and evict */
2091 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2092 seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
2096 ret = i915_wait_request(dev, seqno);
2100 ret = i915_gem_evict_from_inactive_list(dev);
2104 spin_lock(&dev_priv->mm.active_list_lock);
2105 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2106 list_empty(&dev_priv->mm.flushing_list) &&
2107 list_empty(&dev_priv->mm.active_list));
2108 spin_unlock(&dev_priv->mm.active_list_lock);
2109 BUG_ON(!lists_empty);
2115 i915_gem_evict_something(struct drm_device *dev, int min_size)
2117 drm_i915_private_t *dev_priv = dev->dev_private;
2118 struct drm_gem_object *obj;
2122 i915_gem_retire_requests(dev);
2124 /* If there's an inactive buffer available now, grab it
2127 obj = i915_gem_find_inactive_object(dev, min_size);
2129 struct drm_i915_gem_object *obj_priv;
2132 DRM_INFO("%s: evicting %p\n", __func__, obj);
2134 obj_priv = obj->driver_private;
2135 BUG_ON(obj_priv->pin_count != 0);
2136 BUG_ON(obj_priv->active);
2138 /* Wait on the rendering and unbind the buffer. */
2139 return i915_gem_object_unbind(obj);
2142 /* If we didn't get anything, but the ring is still processing
2143 * things, wait for the next to finish and hopefully leave us
2144 * a buffer to evict.
2146 if (!list_empty(&dev_priv->mm.request_list)) {
2147 struct drm_i915_gem_request *request;
2149 request = list_first_entry(&dev_priv->mm.request_list,
2150 struct drm_i915_gem_request,
2153 ret = i915_wait_request(dev, request->seqno);
2160 /* If we didn't have anything on the request list but there
2161 * are buffers awaiting a flush, emit one and try again.
2162 * When we wait on it, those buffers waiting for that flush
2163 * will get moved to inactive.
2165 if (!list_empty(&dev_priv->mm.flushing_list)) {
2166 struct drm_i915_gem_object *obj_priv;
2168 /* Find an object that we can immediately reuse */
2169 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
2170 obj = obj_priv->obj;
2171 if (obj->size >= min_size)
2183 seqno = i915_add_request(dev, NULL, obj->write_domain);
2187 ret = i915_wait_request(dev, seqno);
2195 /* If we didn't do any of the above, there's no single buffer
2196 * large enough to swap out for the new one, so just evict
2197 * everything and start again. (This should be rare.)
2199 if (!list_empty (&dev_priv->mm.inactive_list))
2200 return i915_gem_evict_from_inactive_list(dev);
2202 return i915_gem_evict_everything(dev);
2207 i915_gem_object_get_pages(struct drm_gem_object *obj)
2209 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2211 struct address_space *mapping;
2212 struct inode *inode;
2216 if (obj_priv->pages_refcount++ != 0)
2219 /* Get the list of pages out of our struct file. They'll be pinned
2220 * at this point until we release them.
2222 page_count = obj->size / PAGE_SIZE;
2223 BUG_ON(obj_priv->pages != NULL);
2224 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
2225 if (obj_priv->pages == NULL) {
2226 obj_priv->pages_refcount--;
2230 inode = obj->filp->f_path.dentry->d_inode;
2231 mapping = inode->i_mapping;
2232 for (i = 0; i < page_count; i++) {
2233 page = read_mapping_page(mapping, i, NULL);
2235 ret = PTR_ERR(page);
2236 i915_gem_object_put_pages(obj);
2239 obj_priv->pages[i] = page;
2242 if (obj_priv->tiling_mode != I915_TILING_NONE)
2243 i915_gem_object_do_bit_17_swizzle(obj);
2248 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2250 struct drm_gem_object *obj = reg->obj;
2251 struct drm_device *dev = obj->dev;
2252 drm_i915_private_t *dev_priv = dev->dev_private;
2253 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2254 int regnum = obj_priv->fence_reg;
2257 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2259 val |= obj_priv->gtt_offset & 0xfffff000;
2260 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2261 if (obj_priv->tiling_mode == I915_TILING_Y)
2262 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2263 val |= I965_FENCE_REG_VALID;
2265 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2268 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2270 struct drm_gem_object *obj = reg->obj;
2271 struct drm_device *dev = obj->dev;
2272 drm_i915_private_t *dev_priv = dev->dev_private;
2273 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2274 int regnum = obj_priv->fence_reg;
2276 uint32_t fence_reg, val;
2279 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2280 (obj_priv->gtt_offset & (obj->size - 1))) {
2281 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2282 __func__, obj_priv->gtt_offset, obj->size);
2286 if (obj_priv->tiling_mode == I915_TILING_Y &&
2287 HAS_128_BYTE_Y_TILING(dev))
2292 /* Note: pitch better be a power of two tile widths */
2293 pitch_val = obj_priv->stride / tile_width;
2294 pitch_val = ffs(pitch_val) - 1;
2296 val = obj_priv->gtt_offset;
2297 if (obj_priv->tiling_mode == I915_TILING_Y)
2298 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2299 val |= I915_FENCE_SIZE_BITS(obj->size);
2300 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2301 val |= I830_FENCE_REG_VALID;
2304 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2306 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2307 I915_WRITE(fence_reg, val);
2310 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2312 struct drm_gem_object *obj = reg->obj;
2313 struct drm_device *dev = obj->dev;
2314 drm_i915_private_t *dev_priv = dev->dev_private;
2315 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2316 int regnum = obj_priv->fence_reg;
2319 uint32_t fence_size_bits;
2321 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
2322 (obj_priv->gtt_offset & (obj->size - 1))) {
2323 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2324 __func__, obj_priv->gtt_offset);
2328 pitch_val = obj_priv->stride / 128;
2329 pitch_val = ffs(pitch_val) - 1;
2330 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2332 val = obj_priv->gtt_offset;
2333 if (obj_priv->tiling_mode == I915_TILING_Y)
2334 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2335 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2336 WARN_ON(fence_size_bits & ~0x00000f00);
2337 val |= fence_size_bits;
2338 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2339 val |= I830_FENCE_REG_VALID;
2341 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
2345 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2346 * @obj: object to map through a fence reg
2348 * When mapping objects through the GTT, userspace wants to be able to write
2349 * to them without having to worry about swizzling if the object is tiled.
2351 * This function walks the fence regs looking for a free one for @obj,
2352 * stealing one if it can't find any.
2354 * It then sets up the reg based on the object's properties: address, pitch
2355 * and tiling format.
2358 i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
2360 struct drm_device *dev = obj->dev;
2361 struct drm_i915_private *dev_priv = dev->dev_private;
2362 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2363 struct drm_i915_fence_reg *reg = NULL;
2364 struct drm_i915_gem_object *old_obj_priv = NULL;
2367 /* Just update our place in the LRU if our fence is getting used. */
2368 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2369 list_move_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2373 switch (obj_priv->tiling_mode) {
2374 case I915_TILING_NONE:
2375 WARN(1, "allocating a fence for non-tiled object?\n");
2378 if (!obj_priv->stride)
2380 WARN((obj_priv->stride & (512 - 1)),
2381 "object 0x%08x is X tiled but has non-512B pitch\n",
2382 obj_priv->gtt_offset);
2385 if (!obj_priv->stride)
2387 WARN((obj_priv->stride & (128 - 1)),
2388 "object 0x%08x is Y tiled but has non-128B pitch\n",
2389 obj_priv->gtt_offset);
2393 /* First try to find a free reg */
2395 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2396 reg = &dev_priv->fence_regs[i];
2400 old_obj_priv = reg->obj->driver_private;
2401 if (!old_obj_priv->pin_count)
2405 /* None available, try to steal one or wait for a user to finish */
2406 if (i == dev_priv->num_fence_regs) {
2407 struct drm_gem_object *old_obj = NULL;
2412 list_for_each_entry(old_obj_priv, &dev_priv->mm.fence_list,
2414 old_obj = old_obj_priv->obj;
2416 if (old_obj_priv->pin_count)
2419 /* Take a reference, as otherwise the wait_rendering
2420 * below may cause the object to get freed out from
2423 drm_gem_object_reference(old_obj);
2425 /* i915 uses fences for GPU access to tiled buffers */
2426 if (IS_I965G(dev) || !old_obj_priv->active)
2429 /* This brings the object to the head of the LRU if it
2430 * had been written to. The only way this should
2431 * result in us waiting longer than the expected
2432 * optimal amount of time is if there was a
2433 * fence-using buffer later that was read-only.
2435 i915_gem_object_flush_gpu_write_domain(old_obj);
2436 ret = i915_gem_object_wait_rendering(old_obj);
2438 drm_gem_object_unreference(old_obj);
2446 * Zap this virtual mapping so we can set up a fence again
2447 * for this object next time we need it.
2449 i915_gem_release_mmap(old_obj);
2451 i = old_obj_priv->fence_reg;
2452 reg = &dev_priv->fence_regs[i];
2454 old_obj_priv->fence_reg = I915_FENCE_REG_NONE;
2455 list_del_init(&old_obj_priv->fence_list);
2457 drm_gem_object_unreference(old_obj);
2460 obj_priv->fence_reg = i;
2461 list_add_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2466 i965_write_fence_reg(reg);
2467 else if (IS_I9XX(dev))
2468 i915_write_fence_reg(reg);
2470 i830_write_fence_reg(reg);
2472 trace_i915_gem_object_get_fence(obj, i, obj_priv->tiling_mode);
2478 * i915_gem_clear_fence_reg - clear out fence register info
2479 * @obj: object to clear
2481 * Zeroes out the fence register itself and clears out the associated
2482 * data structures in dev_priv and obj_priv.
2485 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2487 struct drm_device *dev = obj->dev;
2488 drm_i915_private_t *dev_priv = dev->dev_private;
2489 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2492 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
2496 if (obj_priv->fence_reg < 8)
2497 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2499 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2502 I915_WRITE(fence_reg, 0);
2505 dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL;
2506 obj_priv->fence_reg = I915_FENCE_REG_NONE;
2507 list_del_init(&obj_priv->fence_list);
2511 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2512 * to the buffer to finish, and then resets the fence register.
2513 * @obj: tiled object holding a fence register.
2515 * Zeroes out the fence register itself and clears out the associated
2516 * data structures in dev_priv and obj_priv.
2519 i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2521 struct drm_device *dev = obj->dev;
2522 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2524 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2527 /* On the i915, GPU access to tiled buffers is via a fence,
2528 * therefore we must wait for any outstanding access to complete
2529 * before clearing the fence.
2531 if (!IS_I965G(dev)) {
2534 i915_gem_object_flush_gpu_write_domain(obj);
2535 i915_gem_object_flush_gtt_write_domain(obj);
2536 ret = i915_gem_object_wait_rendering(obj);
2541 i915_gem_clear_fence_reg (obj);
2547 * Finds free space in the GTT aperture and binds the object there.
2550 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2552 struct drm_device *dev = obj->dev;
2553 drm_i915_private_t *dev_priv = dev->dev_private;
2554 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2555 struct drm_mm_node *free_space;
2556 bool retry_alloc = false;
2559 if (dev_priv->mm.suspended)
2562 if (obj_priv->madv == I915_MADV_DONTNEED) {
2563 DRM_ERROR("Attempting to bind a purgeable object\n");
2568 alignment = i915_gem_get_gtt_alignment(obj);
2569 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
2570 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2575 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2576 obj->size, alignment, 0);
2577 if (free_space != NULL) {
2578 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2580 if (obj_priv->gtt_space != NULL) {
2581 obj_priv->gtt_space->private = obj;
2582 obj_priv->gtt_offset = obj_priv->gtt_space->start;
2585 if (obj_priv->gtt_space == NULL) {
2586 /* If the gtt is empty and we're still having trouble
2587 * fitting our object in, we're out of memory.
2590 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2592 ret = i915_gem_evict_something(dev, obj->size);
2600 DRM_INFO("Binding object of size %zd at 0x%08x\n",
2601 obj->size, obj_priv->gtt_offset);
2604 i915_gem_object_set_page_gfp_mask (obj,
2605 i915_gem_object_get_page_gfp_mask (obj) & ~__GFP_NORETRY);
2607 ret = i915_gem_object_get_pages(obj);
2609 i915_gem_object_set_page_gfp_mask (obj,
2610 i915_gem_object_get_page_gfp_mask (obj) | __GFP_NORETRY);
2613 drm_mm_put_block(obj_priv->gtt_space);
2614 obj_priv->gtt_space = NULL;
2616 if (ret == -ENOMEM) {
2617 /* first try to clear up some space from the GTT */
2618 ret = i915_gem_evict_something(dev, obj->size);
2620 /* now try to shrink everyone else */
2621 if (! retry_alloc) {
2635 /* Create an AGP memory structure pointing at our pages, and bind it
2638 obj_priv->agp_mem = drm_agp_bind_pages(dev,
2640 obj->size >> PAGE_SHIFT,
2641 obj_priv->gtt_offset,
2642 obj_priv->agp_type);
2643 if (obj_priv->agp_mem == NULL) {
2644 i915_gem_object_put_pages(obj);
2645 drm_mm_put_block(obj_priv->gtt_space);
2646 obj_priv->gtt_space = NULL;
2648 ret = i915_gem_evict_something(dev, obj->size);
2654 atomic_inc(&dev->gtt_count);
2655 atomic_add(obj->size, &dev->gtt_memory);
2657 /* Assert that the object is not currently in any GPU domain. As it
2658 * wasn't in the GTT, there shouldn't be any way it could have been in
2661 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2662 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
2664 trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2670 i915_gem_clflush_object(struct drm_gem_object *obj)
2672 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2674 /* If we don't have a page list set up, then we're not pinned
2675 * to GPU, and we can ignore the cache flush because it'll happen
2676 * again at bind time.
2678 if (obj_priv->pages == NULL)
2681 trace_i915_gem_object_clflush(obj);
2683 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2686 /** Flushes any GPU write domain for the object if it's dirty. */
2688 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2690 struct drm_device *dev = obj->dev;
2692 uint32_t old_write_domain;
2694 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2697 /* Queue the GPU write cache flushing we need. */
2698 old_write_domain = obj->write_domain;
2699 i915_gem_flush(dev, 0, obj->write_domain);
2700 seqno = i915_add_request(dev, NULL, obj->write_domain);
2701 obj->write_domain = 0;
2702 i915_gem_object_move_to_active(obj, seqno);
2704 trace_i915_gem_object_change_domain(obj,
2709 /** Flushes the GTT write domain for the object if it's dirty. */
2711 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2713 uint32_t old_write_domain;
2715 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2718 /* No actual flushing is required for the GTT write domain. Writes
2719 * to it immediately go to main memory as far as we know, so there's
2720 * no chipset flush. It also doesn't land in render cache.
2722 old_write_domain = obj->write_domain;
2723 obj->write_domain = 0;
2725 trace_i915_gem_object_change_domain(obj,
2730 /** Flushes the CPU write domain for the object if it's dirty. */
2732 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2734 struct drm_device *dev = obj->dev;
2735 uint32_t old_write_domain;
2737 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2740 i915_gem_clflush_object(obj);
2741 drm_agp_chipset_flush(dev);
2742 old_write_domain = obj->write_domain;
2743 obj->write_domain = 0;
2745 trace_i915_gem_object_change_domain(obj,
2751 * Moves a single object to the GTT read, and possibly write domain.
2753 * This function returns when the move is complete, including waiting on
2757 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2759 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2760 uint32_t old_write_domain, old_read_domains;
2763 /* Not valid to be called on unbound objects. */
2764 if (obj_priv->gtt_space == NULL)
2767 i915_gem_object_flush_gpu_write_domain(obj);
2768 /* Wait on any GPU rendering and flushing to occur. */
2769 ret = i915_gem_object_wait_rendering(obj);
2773 old_write_domain = obj->write_domain;
2774 old_read_domains = obj->read_domains;
2776 /* If we're writing through the GTT domain, then CPU and GPU caches
2777 * will need to be invalidated at next use.
2780 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2782 i915_gem_object_flush_cpu_write_domain(obj);
2784 /* It should now be out of any other write domains, and we can update
2785 * the domain values for our changes.
2787 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2788 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2790 obj->write_domain = I915_GEM_DOMAIN_GTT;
2791 obj_priv->dirty = 1;
2794 trace_i915_gem_object_change_domain(obj,
2802 * Moves a single object to the CPU read, and possibly write domain.
2804 * This function returns when the move is complete, including waiting on
2808 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2810 uint32_t old_write_domain, old_read_domains;
2813 i915_gem_object_flush_gpu_write_domain(obj);
2814 /* Wait on any GPU rendering and flushing to occur. */
2815 ret = i915_gem_object_wait_rendering(obj);
2819 i915_gem_object_flush_gtt_write_domain(obj);
2821 /* If we have a partially-valid cache of the object in the CPU,
2822 * finish invalidating it and free the per-page flags.
2824 i915_gem_object_set_to_full_cpu_read_domain(obj);
2826 old_write_domain = obj->write_domain;
2827 old_read_domains = obj->read_domains;
2829 /* Flush the CPU cache if it's still invalid. */
2830 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2831 i915_gem_clflush_object(obj);
2833 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2836 /* It should now be out of any other write domains, and we can update
2837 * the domain values for our changes.
2839 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2841 /* If we're writing through the CPU, then the GPU read domains will
2842 * need to be invalidated at next use.
2845 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2846 obj->write_domain = I915_GEM_DOMAIN_CPU;
2849 trace_i915_gem_object_change_domain(obj,
2857 * Set the next domain for the specified object. This
2858 * may not actually perform the necessary flushing/invaliding though,
2859 * as that may want to be batched with other set_domain operations
2861 * This is (we hope) the only really tricky part of gem. The goal
2862 * is fairly simple -- track which caches hold bits of the object
2863 * and make sure they remain coherent. A few concrete examples may
2864 * help to explain how it works. For shorthand, we use the notation
2865 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2866 * a pair of read and write domain masks.
2868 * Case 1: the batch buffer
2874 * 5. Unmapped from GTT
2877 * Let's take these a step at a time
2880 * Pages allocated from the kernel may still have
2881 * cache contents, so we set them to (CPU, CPU) always.
2882 * 2. Written by CPU (using pwrite)
2883 * The pwrite function calls set_domain (CPU, CPU) and
2884 * this function does nothing (as nothing changes)
2886 * This function asserts that the object is not
2887 * currently in any GPU-based read or write domains
2889 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2890 * As write_domain is zero, this function adds in the
2891 * current read domains (CPU+COMMAND, 0).
2892 * flush_domains is set to CPU.
2893 * invalidate_domains is set to COMMAND
2894 * clflush is run to get data out of the CPU caches
2895 * then i915_dev_set_domain calls i915_gem_flush to
2896 * emit an MI_FLUSH and drm_agp_chipset_flush
2897 * 5. Unmapped from GTT
2898 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2899 * flush_domains and invalidate_domains end up both zero
2900 * so no flushing/invalidating happens
2904 * Case 2: The shared render buffer
2908 * 3. Read/written by GPU
2909 * 4. set_domain to (CPU,CPU)
2910 * 5. Read/written by CPU
2911 * 6. Read/written by GPU
2914 * Same as last example, (CPU, CPU)
2916 * Nothing changes (assertions find that it is not in the GPU)
2917 * 3. Read/written by GPU
2918 * execbuffer calls set_domain (RENDER, RENDER)
2919 * flush_domains gets CPU
2920 * invalidate_domains gets GPU
2922 * MI_FLUSH and drm_agp_chipset_flush
2923 * 4. set_domain (CPU, CPU)
2924 * flush_domains gets GPU
2925 * invalidate_domains gets CPU
2926 * wait_rendering (obj) to make sure all drawing is complete.
2927 * This will include an MI_FLUSH to get the data from GPU
2929 * clflush (obj) to invalidate the CPU cache
2930 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
2931 * 5. Read/written by CPU
2932 * cache lines are loaded and dirtied
2933 * 6. Read written by GPU
2934 * Same as last GPU access
2936 * Case 3: The constant buffer
2941 * 4. Updated (written) by CPU again
2950 * flush_domains = CPU
2951 * invalidate_domains = RENDER
2954 * drm_agp_chipset_flush
2955 * 4. Updated (written) by CPU again
2957 * flush_domains = 0 (no previous write domain)
2958 * invalidate_domains = 0 (no new read domains)
2961 * flush_domains = CPU
2962 * invalidate_domains = RENDER
2965 * drm_agp_chipset_flush
2968 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
2970 struct drm_device *dev = obj->dev;
2971 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2972 uint32_t invalidate_domains = 0;
2973 uint32_t flush_domains = 0;
2974 uint32_t old_read_domains;
2976 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
2977 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
2979 intel_mark_busy(dev, obj);
2982 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2984 obj->read_domains, obj->pending_read_domains,
2985 obj->write_domain, obj->pending_write_domain);
2988 * If the object isn't moving to a new write domain,
2989 * let the object stay in multiple read domains
2991 if (obj->pending_write_domain == 0)
2992 obj->pending_read_domains |= obj->read_domains;
2994 obj_priv->dirty = 1;
2997 * Flush the current write domain if
2998 * the new read domains don't match. Invalidate
2999 * any read domains which differ from the old
3002 if (obj->write_domain &&
3003 obj->write_domain != obj->pending_read_domains) {
3004 flush_domains |= obj->write_domain;
3005 invalidate_domains |=
3006 obj->pending_read_domains & ~obj->write_domain;
3009 * Invalidate any read caches which may have
3010 * stale data. That is, any new read domains.
3012 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
3013 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
3015 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3016 __func__, flush_domains, invalidate_domains);
3018 i915_gem_clflush_object(obj);
3021 old_read_domains = obj->read_domains;
3023 /* The actual obj->write_domain will be updated with
3024 * pending_write_domain after we emit the accumulated flush for all
3025 * of our domain changes in execbuffers (which clears objects'
3026 * write_domains). So if we have a current write domain that we
3027 * aren't changing, set pending_write_domain to that.
3029 if (flush_domains == 0 && obj->pending_write_domain == 0)
3030 obj->pending_write_domain = obj->write_domain;
3031 obj->read_domains = obj->pending_read_domains;
3033 dev->invalidate_domains |= invalidate_domains;
3034 dev->flush_domains |= flush_domains;
3036 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3038 obj->read_domains, obj->write_domain,
3039 dev->invalidate_domains, dev->flush_domains);
3042 trace_i915_gem_object_change_domain(obj,
3048 * Moves the object from a partially CPU read to a full one.
3050 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3051 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3054 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
3056 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3058 if (!obj_priv->page_cpu_valid)
3061 /* If we're partially in the CPU read domain, finish moving it in.
3063 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3066 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3067 if (obj_priv->page_cpu_valid[i])
3069 drm_clflush_pages(obj_priv->pages + i, 1);
3073 /* Free the page_cpu_valid mappings which are now stale, whether
3074 * or not we've got I915_GEM_DOMAIN_CPU.
3076 kfree(obj_priv->page_cpu_valid);
3077 obj_priv->page_cpu_valid = NULL;
3081 * Set the CPU read domain on a range of the object.
3083 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3084 * not entirely valid. The page_cpu_valid member of the object flags which
3085 * pages have been flushed, and will be respected by
3086 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3087 * of the whole object.
3089 * This function returns when the move is complete, including waiting on
3093 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3094 uint64_t offset, uint64_t size)
3096 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3097 uint32_t old_read_domains;
3100 if (offset == 0 && size == obj->size)
3101 return i915_gem_object_set_to_cpu_domain(obj, 0);
3103 i915_gem_object_flush_gpu_write_domain(obj);
3104 /* Wait on any GPU rendering and flushing to occur. */
3105 ret = i915_gem_object_wait_rendering(obj);
3108 i915_gem_object_flush_gtt_write_domain(obj);
3110 /* If we're already fully in the CPU read domain, we're done. */
3111 if (obj_priv->page_cpu_valid == NULL &&
3112 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3115 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3116 * newly adding I915_GEM_DOMAIN_CPU
3118 if (obj_priv->page_cpu_valid == NULL) {
3119 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3121 if (obj_priv->page_cpu_valid == NULL)
3123 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3124 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
3126 /* Flush the cache on any pages that are still invalid from the CPU's
3129 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3131 if (obj_priv->page_cpu_valid[i])
3134 drm_clflush_pages(obj_priv->pages + i, 1);
3136 obj_priv->page_cpu_valid[i] = 1;
3139 /* It should now be out of any other write domains, and we can update
3140 * the domain values for our changes.
3142 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3144 old_read_domains = obj->read_domains;
3145 obj->read_domains |= I915_GEM_DOMAIN_CPU;
3147 trace_i915_gem_object_change_domain(obj,
3155 * Pin an object to the GTT and evaluate the relocations landing in it.
3158 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3159 struct drm_file *file_priv,
3160 struct drm_i915_gem_exec_object *entry,
3161 struct drm_i915_gem_relocation_entry *relocs)
3163 struct drm_device *dev = obj->dev;
3164 drm_i915_private_t *dev_priv = dev->dev_private;
3165 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3167 void __iomem *reloc_page;
3169 /* Choose the GTT offset for our buffer and put it there. */
3170 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3174 entry->offset = obj_priv->gtt_offset;
3176 /* Apply the relocations, using the GTT aperture to avoid cache
3177 * flushing requirements.
3179 for (i = 0; i < entry->relocation_count; i++) {
3180 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
3181 struct drm_gem_object *target_obj;
3182 struct drm_i915_gem_object *target_obj_priv;
3183 uint32_t reloc_val, reloc_offset;
3184 uint32_t __iomem *reloc_entry;
3186 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
3187 reloc->target_handle);
3188 if (target_obj == NULL) {
3189 i915_gem_object_unpin(obj);
3192 target_obj_priv = target_obj->driver_private;
3195 DRM_INFO("%s: obj %p offset %08x target %d "
3196 "read %08x write %08x gtt %08x "
3197 "presumed %08x delta %08x\n",
3200 (int) reloc->offset,
3201 (int) reloc->target_handle,
3202 (int) reloc->read_domains,
3203 (int) reloc->write_domain,
3204 (int) target_obj_priv->gtt_offset,
3205 (int) reloc->presumed_offset,
3209 /* The target buffer should have appeared before us in the
3210 * exec_object list, so it should have a GTT space bound by now.
3212 if (target_obj_priv->gtt_space == NULL) {
3213 DRM_ERROR("No GTT space found for object %d\n",
3214 reloc->target_handle);
3215 drm_gem_object_unreference(target_obj);
3216 i915_gem_object_unpin(obj);
3220 /* Validate that the target is in a valid r/w GPU domain */
3221 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3222 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
3223 DRM_ERROR("reloc with read/write CPU domains: "
3224 "obj %p target %d offset %d "
3225 "read %08x write %08x",
3226 obj, reloc->target_handle,
3227 (int) reloc->offset,
3228 reloc->read_domains,
3229 reloc->write_domain);
3230 drm_gem_object_unreference(target_obj);
3231 i915_gem_object_unpin(obj);
3234 if (reloc->write_domain && target_obj->pending_write_domain &&
3235 reloc->write_domain != target_obj->pending_write_domain) {
3236 DRM_ERROR("Write domain conflict: "
3237 "obj %p target %d offset %d "
3238 "new %08x old %08x\n",
3239 obj, reloc->target_handle,
3240 (int) reloc->offset,
3241 reloc->write_domain,
3242 target_obj->pending_write_domain);
3243 drm_gem_object_unreference(target_obj);
3244 i915_gem_object_unpin(obj);
3248 target_obj->pending_read_domains |= reloc->read_domains;
3249 target_obj->pending_write_domain |= reloc->write_domain;
3251 /* If the relocation already has the right value in it, no
3252 * more work needs to be done.
3254 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
3255 drm_gem_object_unreference(target_obj);
3259 /* Check that the relocation address is valid... */
3260 if (reloc->offset > obj->size - 4) {
3261 DRM_ERROR("Relocation beyond object bounds: "
3262 "obj %p target %d offset %d size %d.\n",
3263 obj, reloc->target_handle,
3264 (int) reloc->offset, (int) obj->size);
3265 drm_gem_object_unreference(target_obj);
3266 i915_gem_object_unpin(obj);
3269 if (reloc->offset & 3) {
3270 DRM_ERROR("Relocation not 4-byte aligned: "
3271 "obj %p target %d offset %d.\n",
3272 obj, reloc->target_handle,
3273 (int) reloc->offset);
3274 drm_gem_object_unreference(target_obj);
3275 i915_gem_object_unpin(obj);
3279 /* and points to somewhere within the target object. */
3280 if (reloc->delta >= target_obj->size) {
3281 DRM_ERROR("Relocation beyond target object bounds: "
3282 "obj %p target %d delta %d size %d.\n",
3283 obj, reloc->target_handle,
3284 (int) reloc->delta, (int) target_obj->size);
3285 drm_gem_object_unreference(target_obj);
3286 i915_gem_object_unpin(obj);
3290 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3292 drm_gem_object_unreference(target_obj);
3293 i915_gem_object_unpin(obj);
3297 /* Map the page containing the relocation we're going to
3300 reloc_offset = obj_priv->gtt_offset + reloc->offset;
3301 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3304 reloc_entry = (uint32_t __iomem *)(reloc_page +
3305 (reloc_offset & (PAGE_SIZE - 1)));
3306 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
3309 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3310 obj, (unsigned int) reloc->offset,
3311 readl(reloc_entry), reloc_val);
3313 writel(reloc_val, reloc_entry);
3314 io_mapping_unmap_atomic(reloc_page);
3316 /* The updated presumed offset for this entry will be
3317 * copied back out to the user.
3319 reloc->presumed_offset = target_obj_priv->gtt_offset;
3321 drm_gem_object_unreference(target_obj);
3326 i915_gem_dump_object(obj, 128, __func__, ~0);
3331 /** Dispatch a batchbuffer to the ring
3334 i915_dispatch_gem_execbuffer(struct drm_device *dev,
3335 struct drm_i915_gem_execbuffer *exec,
3336 struct drm_clip_rect *cliprects,
3337 uint64_t exec_offset)
3339 drm_i915_private_t *dev_priv = dev->dev_private;
3340 int nbox = exec->num_cliprects;
3342 uint32_t exec_start, exec_len;
3345 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3346 exec_len = (uint32_t) exec->batch_len;
3348 trace_i915_gem_request_submit(dev, dev_priv->mm.next_gem_seqno);
3350 count = nbox ? nbox : 1;
3352 for (i = 0; i < count; i++) {
3354 int ret = i915_emit_box(dev, cliprects, i,
3355 exec->DR1, exec->DR4);
3360 if (IS_I830(dev) || IS_845G(dev)) {
3362 OUT_RING(MI_BATCH_BUFFER);
3363 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3364 OUT_RING(exec_start + exec_len - 4);
3369 if (IS_I965G(dev)) {
3370 OUT_RING(MI_BATCH_BUFFER_START |
3372 MI_BATCH_NON_SECURE_I965);
3373 OUT_RING(exec_start);
3375 OUT_RING(MI_BATCH_BUFFER_START |
3377 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3383 /* XXX breadcrumb */
3387 /* Throttle our rendering by waiting until the ring has completed our requests
3388 * emitted over 20 msec ago.
3390 * Note that if we were to use the current jiffies each time around the loop,
3391 * we wouldn't escape the function with any frames outstanding if the time to
3392 * render a frame was over 20ms.
3394 * This should get us reasonable parallelism between CPU and GPU but also
3395 * relatively low latency when blocking on a particular request to finish.
3398 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3400 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3402 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3404 mutex_lock(&dev->struct_mutex);
3405 while (!list_empty(&i915_file_priv->mm.request_list)) {
3406 struct drm_i915_gem_request *request;
3408 request = list_first_entry(&i915_file_priv->mm.request_list,
3409 struct drm_i915_gem_request,
3412 if (time_after_eq(request->emitted_jiffies, recent_enough))
3415 ret = i915_wait_request(dev, request->seqno);
3419 mutex_unlock(&dev->struct_mutex);
3425 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object *exec_list,
3426 uint32_t buffer_count,
3427 struct drm_i915_gem_relocation_entry **relocs)
3429 uint32_t reloc_count = 0, reloc_index = 0, i;
3433 for (i = 0; i < buffer_count; i++) {
3434 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3436 reloc_count += exec_list[i].relocation_count;
3439 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
3440 if (*relocs == NULL)
3443 for (i = 0; i < buffer_count; i++) {
3444 struct drm_i915_gem_relocation_entry __user *user_relocs;
3446 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3448 ret = copy_from_user(&(*relocs)[reloc_index],
3450 exec_list[i].relocation_count *
3453 drm_free_large(*relocs);
3458 reloc_index += exec_list[i].relocation_count;
3465 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object *exec_list,
3466 uint32_t buffer_count,
3467 struct drm_i915_gem_relocation_entry *relocs)
3469 uint32_t reloc_count = 0, i;
3472 for (i = 0; i < buffer_count; i++) {
3473 struct drm_i915_gem_relocation_entry __user *user_relocs;
3476 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3478 unwritten = copy_to_user(user_relocs,
3479 &relocs[reloc_count],
3480 exec_list[i].relocation_count *
3488 reloc_count += exec_list[i].relocation_count;
3492 drm_free_large(relocs);
3498 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer *exec,
3499 uint64_t exec_offset)
3501 uint32_t exec_start, exec_len;
3503 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3504 exec_len = (uint32_t) exec->batch_len;
3506 if ((exec_start | exec_len) & 0x7)
3516 i915_gem_execbuffer(struct drm_device *dev, void *data,
3517 struct drm_file *file_priv)
3519 drm_i915_private_t *dev_priv = dev->dev_private;
3520 struct drm_i915_gem_execbuffer *args = data;
3521 struct drm_i915_gem_exec_object *exec_list = NULL;
3522 struct drm_gem_object **object_list = NULL;
3523 struct drm_gem_object *batch_obj;
3524 struct drm_i915_gem_object *obj_priv;
3525 struct drm_clip_rect *cliprects = NULL;
3526 struct drm_i915_gem_relocation_entry *relocs;
3527 int ret, ret2, i, pinned = 0;
3528 uint64_t exec_offset;
3529 uint32_t seqno, flush_domains, reloc_index;
3533 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3534 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3537 if (args->buffer_count < 1) {
3538 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3541 /* Copy in the exec list from userland */
3542 exec_list = drm_calloc_large(sizeof(*exec_list), args->buffer_count);
3543 object_list = drm_calloc_large(sizeof(*object_list), args->buffer_count);
3544 if (exec_list == NULL || object_list == NULL) {
3545 DRM_ERROR("Failed to allocate exec or object list "
3547 args->buffer_count);
3551 ret = copy_from_user(exec_list,
3552 (struct drm_i915_relocation_entry __user *)
3553 (uintptr_t) args->buffers_ptr,
3554 sizeof(*exec_list) * args->buffer_count);
3556 DRM_ERROR("copy %d exec entries failed %d\n",
3557 args->buffer_count, ret);
3561 if (args->num_cliprects != 0) {
3562 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3564 if (cliprects == NULL)
3567 ret = copy_from_user(cliprects,
3568 (struct drm_clip_rect __user *)
3569 (uintptr_t) args->cliprects_ptr,
3570 sizeof(*cliprects) * args->num_cliprects);
3572 DRM_ERROR("copy %d cliprects failed: %d\n",
3573 args->num_cliprects, ret);
3578 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3583 mutex_lock(&dev->struct_mutex);
3585 i915_verify_inactive(dev, __FILE__, __LINE__);
3587 if (atomic_read(&dev_priv->mm.wedged)) {
3588 DRM_ERROR("Execbuf while wedged\n");
3589 mutex_unlock(&dev->struct_mutex);
3594 if (dev_priv->mm.suspended) {
3595 DRM_ERROR("Execbuf while VT-switched.\n");
3596 mutex_unlock(&dev->struct_mutex);
3601 /* Look up object handles */
3602 for (i = 0; i < args->buffer_count; i++) {
3603 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3604 exec_list[i].handle);
3605 if (object_list[i] == NULL) {
3606 DRM_ERROR("Invalid object handle %d at index %d\n",
3607 exec_list[i].handle, i);
3612 obj_priv = object_list[i]->driver_private;
3613 if (obj_priv->in_execbuffer) {
3614 DRM_ERROR("Object %p appears more than once in object list\n",
3619 obj_priv->in_execbuffer = true;
3622 /* Pin and relocate */
3623 for (pin_tries = 0; ; pin_tries++) {
3627 for (i = 0; i < args->buffer_count; i++) {
3628 object_list[i]->pending_read_domains = 0;
3629 object_list[i]->pending_write_domain = 0;
3630 ret = i915_gem_object_pin_and_relocate(object_list[i],
3633 &relocs[reloc_index]);
3637 reloc_index += exec_list[i].relocation_count;
3643 /* error other than GTT full, or we've already tried again */
3644 if (ret != -ENOSPC || pin_tries >= 1) {
3645 if (ret != -ERESTARTSYS) {
3646 unsigned long long total_size = 0;
3647 for (i = 0; i < args->buffer_count; i++)
3648 total_size += object_list[i]->size;
3649 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes: %d\n",
3650 pinned+1, args->buffer_count,
3652 DRM_ERROR("%d objects [%d pinned], "
3653 "%d object bytes [%d pinned], "
3654 "%d/%d gtt bytes\n",
3655 atomic_read(&dev->object_count),
3656 atomic_read(&dev->pin_count),
3657 atomic_read(&dev->object_memory),
3658 atomic_read(&dev->pin_memory),
3659 atomic_read(&dev->gtt_memory),
3665 /* unpin all of our buffers */
3666 for (i = 0; i < pinned; i++)
3667 i915_gem_object_unpin(object_list[i]);
3670 /* evict everyone we can from the aperture */
3671 ret = i915_gem_evict_everything(dev);
3672 if (ret && ret != -ENOSPC)
3676 /* Set the pending read domains for the batch buffer to COMMAND */
3677 batch_obj = object_list[args->buffer_count-1];
3678 if (batch_obj->pending_write_domain) {
3679 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3683 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
3685 /* Sanity check the batch buffer, prior to moving objects */
3686 exec_offset = exec_list[args->buffer_count - 1].offset;
3687 ret = i915_gem_check_execbuffer (args, exec_offset);
3689 DRM_ERROR("execbuf with invalid offset/length\n");
3693 i915_verify_inactive(dev, __FILE__, __LINE__);
3695 /* Zero the global flush/invalidate flags. These
3696 * will be modified as new domains are computed
3699 dev->invalidate_domains = 0;
3700 dev->flush_domains = 0;
3702 for (i = 0; i < args->buffer_count; i++) {
3703 struct drm_gem_object *obj = object_list[i];
3705 /* Compute new gpu domains and update invalidate/flush */
3706 i915_gem_object_set_to_gpu_domain(obj);
3709 i915_verify_inactive(dev, __FILE__, __LINE__);
3711 if (dev->invalidate_domains | dev->flush_domains) {
3713 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3715 dev->invalidate_domains,
3716 dev->flush_domains);
3719 dev->invalidate_domains,
3720 dev->flush_domains);
3721 if (dev->flush_domains)
3722 (void)i915_add_request(dev, file_priv,
3723 dev->flush_domains);
3726 for (i = 0; i < args->buffer_count; i++) {
3727 struct drm_gem_object *obj = object_list[i];
3728 uint32_t old_write_domain = obj->write_domain;
3730 obj->write_domain = obj->pending_write_domain;
3731 trace_i915_gem_object_change_domain(obj,
3736 i915_verify_inactive(dev, __FILE__, __LINE__);
3739 for (i = 0; i < args->buffer_count; i++) {
3740 i915_gem_object_check_coherency(object_list[i],
3741 exec_list[i].handle);
3746 i915_gem_dump_object(batch_obj,
3752 /* Exec the batchbuffer */
3753 ret = i915_dispatch_gem_execbuffer(dev, args, cliprects, exec_offset);
3755 DRM_ERROR("dispatch failed %d\n", ret);
3760 * Ensure that the commands in the batch buffer are
3761 * finished before the interrupt fires
3763 flush_domains = i915_retire_commands(dev);
3765 i915_verify_inactive(dev, __FILE__, __LINE__);
3768 * Get a seqno representing the execution of the current buffer,
3769 * which we can wait on. We would like to mitigate these interrupts,
3770 * likely by only creating seqnos occasionally (so that we have
3771 * *some* interrupts representing completion of buffers that we can
3772 * wait on when trying to clear up gtt space).
3774 seqno = i915_add_request(dev, file_priv, flush_domains);
3776 for (i = 0; i < args->buffer_count; i++) {
3777 struct drm_gem_object *obj = object_list[i];
3779 i915_gem_object_move_to_active(obj, seqno);
3781 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3785 i915_dump_lru(dev, __func__);
3788 i915_verify_inactive(dev, __FILE__, __LINE__);
3791 for (i = 0; i < pinned; i++)
3792 i915_gem_object_unpin(object_list[i]);
3794 for (i = 0; i < args->buffer_count; i++) {
3795 if (object_list[i]) {
3796 obj_priv = object_list[i]->driver_private;
3797 obj_priv->in_execbuffer = false;
3799 drm_gem_object_unreference(object_list[i]);
3802 mutex_unlock(&dev->struct_mutex);
3805 /* Copy the new buffer offsets back to the user's exec list. */
3806 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
3807 (uintptr_t) args->buffers_ptr,
3809 sizeof(*exec_list) * args->buffer_count);
3812 DRM_ERROR("failed to copy %d exec entries "
3813 "back to user (%d)\n",
3814 args->buffer_count, ret);
3818 /* Copy the updated relocations out regardless of current error
3819 * state. Failure to update the relocs would mean that the next
3820 * time userland calls execbuf, it would do so with presumed offset
3821 * state that didn't match the actual object state.
3823 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
3826 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
3833 drm_free_large(object_list);
3834 drm_free_large(exec_list);
3841 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
3843 struct drm_device *dev = obj->dev;
3844 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3847 i915_verify_inactive(dev, __FILE__, __LINE__);
3848 if (obj_priv->gtt_space == NULL) {
3849 ret = i915_gem_object_bind_to_gtt(obj, alignment);
3854 * Pre-965 chips need a fence register set up in order to
3855 * properly handle tiled surfaces.
3857 if (!IS_I965G(dev) && obj_priv->tiling_mode != I915_TILING_NONE) {
3858 ret = i915_gem_object_get_fence_reg(obj);
3860 if (ret != -EBUSY && ret != -ERESTARTSYS)
3861 DRM_ERROR("Failure to install fence: %d\n",
3866 obj_priv->pin_count++;
3868 /* If the object is not active and not pending a flush,
3869 * remove it from the inactive list
3871 if (obj_priv->pin_count == 1) {
3872 atomic_inc(&dev->pin_count);
3873 atomic_add(obj->size, &dev->pin_memory);
3874 if (!obj_priv->active &&
3875 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 &&
3876 !list_empty(&obj_priv->list))
3877 list_del_init(&obj_priv->list);
3879 i915_verify_inactive(dev, __FILE__, __LINE__);
3885 i915_gem_object_unpin(struct drm_gem_object *obj)
3887 struct drm_device *dev = obj->dev;
3888 drm_i915_private_t *dev_priv = dev->dev_private;
3889 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3891 i915_verify_inactive(dev, __FILE__, __LINE__);
3892 obj_priv->pin_count--;
3893 BUG_ON(obj_priv->pin_count < 0);
3894 BUG_ON(obj_priv->gtt_space == NULL);
3896 /* If the object is no longer pinned, and is
3897 * neither active nor being flushed, then stick it on
3900 if (obj_priv->pin_count == 0) {
3901 if (!obj_priv->active &&
3902 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
3903 list_move_tail(&obj_priv->list,
3904 &dev_priv->mm.inactive_list);
3905 atomic_dec(&dev->pin_count);
3906 atomic_sub(obj->size, &dev->pin_memory);
3908 i915_verify_inactive(dev, __FILE__, __LINE__);
3912 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3913 struct drm_file *file_priv)
3915 struct drm_i915_gem_pin *args = data;
3916 struct drm_gem_object *obj;
3917 struct drm_i915_gem_object *obj_priv;
3920 mutex_lock(&dev->struct_mutex);
3922 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
3924 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
3926 mutex_unlock(&dev->struct_mutex);
3929 obj_priv = obj->driver_private;
3931 if (obj_priv->madv == I915_MADV_DONTNEED) {
3932 DRM_ERROR("Attempting to pin a I915_MADV_DONTNEED buffer\n");
3933 drm_gem_object_unreference(obj);
3934 mutex_unlock(&dev->struct_mutex);
3938 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
3939 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3941 drm_gem_object_unreference(obj);
3942 mutex_unlock(&dev->struct_mutex);
3946 obj_priv->user_pin_count++;
3947 obj_priv->pin_filp = file_priv;
3948 if (obj_priv->user_pin_count == 1) {
3949 ret = i915_gem_object_pin(obj, args->alignment);
3951 drm_gem_object_unreference(obj);
3952 mutex_unlock(&dev->struct_mutex);
3957 /* XXX - flush the CPU caches for pinned objects
3958 * as the X server doesn't manage domains yet
3960 i915_gem_object_flush_cpu_write_domain(obj);
3961 args->offset = obj_priv->gtt_offset;
3962 drm_gem_object_unreference(obj);
3963 mutex_unlock(&dev->struct_mutex);
3969 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3970 struct drm_file *file_priv)
3972 struct drm_i915_gem_pin *args = data;
3973 struct drm_gem_object *obj;
3974 struct drm_i915_gem_object *obj_priv;
3976 mutex_lock(&dev->struct_mutex);
3978 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
3980 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
3982 mutex_unlock(&dev->struct_mutex);
3986 obj_priv = obj->driver_private;
3987 if (obj_priv->pin_filp != file_priv) {
3988 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3990 drm_gem_object_unreference(obj);
3991 mutex_unlock(&dev->struct_mutex);
3994 obj_priv->user_pin_count--;
3995 if (obj_priv->user_pin_count == 0) {
3996 obj_priv->pin_filp = NULL;
3997 i915_gem_object_unpin(obj);
4000 drm_gem_object_unreference(obj);
4001 mutex_unlock(&dev->struct_mutex);
4006 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4007 struct drm_file *file_priv)
4009 struct drm_i915_gem_busy *args = data;
4010 struct drm_gem_object *obj;
4011 struct drm_i915_gem_object *obj_priv;
4013 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4015 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4020 mutex_lock(&dev->struct_mutex);
4021 /* Update the active list for the hardware's current position.
4022 * Otherwise this only updates on a delayed timer or when irqs are
4023 * actually unmasked, and our working set ends up being larger than
4026 i915_gem_retire_requests(dev);
4028 obj_priv = obj->driver_private;
4029 /* Don't count being on the flushing list against the object being
4030 * done. Otherwise, a buffer left on the flushing list but not getting
4031 * flushed (because nobody's flushing that domain) won't ever return
4032 * unbusy and get reused by libdrm's bo cache. The other expected
4033 * consumer of this interface, OpenGL's occlusion queries, also specs
4034 * that the objects get unbusy "eventually" without any interference.
4036 args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
4038 drm_gem_object_unreference(obj);
4039 mutex_unlock(&dev->struct_mutex);
4044 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4045 struct drm_file *file_priv)
4047 return i915_gem_ring_throttle(dev, file_priv);
4051 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4052 struct drm_file *file_priv)
4054 struct drm_i915_gem_madvise *args = data;
4055 struct drm_gem_object *obj;
4056 struct drm_i915_gem_object *obj_priv;
4058 switch (args->madv) {
4059 case I915_MADV_DONTNEED:
4060 case I915_MADV_WILLNEED:
4066 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4068 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4073 mutex_lock(&dev->struct_mutex);
4074 obj_priv = obj->driver_private;
4076 if (obj_priv->pin_count) {
4077 drm_gem_object_unreference(obj);
4078 mutex_unlock(&dev->struct_mutex);
4080 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4084 obj_priv->madv = args->madv;
4085 args->retained = obj_priv->gtt_space != NULL;
4087 /* if the object is no longer bound, discard its backing storage */
4088 if (i915_gem_object_is_purgeable(obj_priv) &&
4089 obj_priv->gtt_space == NULL)
4090 i915_gem_object_truncate(obj);
4092 drm_gem_object_unreference(obj);
4093 mutex_unlock(&dev->struct_mutex);
4098 int i915_gem_init_object(struct drm_gem_object *obj)
4100 struct drm_i915_gem_object *obj_priv;
4102 obj_priv = kzalloc(sizeof(*obj_priv), GFP_KERNEL);
4103 if (obj_priv == NULL)
4107 * We've just allocated pages from the kernel,
4108 * so they've just been written by the CPU with
4109 * zeros. They'll need to be clflushed before we
4110 * use them with the GPU.
4112 obj->write_domain = I915_GEM_DOMAIN_CPU;
4113 obj->read_domains = I915_GEM_DOMAIN_CPU;
4115 obj_priv->agp_type = AGP_USER_MEMORY;
4117 obj->driver_private = obj_priv;
4118 obj_priv->obj = obj;
4119 obj_priv->fence_reg = I915_FENCE_REG_NONE;
4120 INIT_LIST_HEAD(&obj_priv->list);
4121 INIT_LIST_HEAD(&obj_priv->fence_list);
4122 obj_priv->madv = I915_MADV_WILLNEED;
4124 trace_i915_gem_object_create(obj);
4129 void i915_gem_free_object(struct drm_gem_object *obj)
4131 struct drm_device *dev = obj->dev;
4132 struct drm_i915_gem_object *obj_priv = obj->driver_private;
4134 trace_i915_gem_object_destroy(obj);
4136 while (obj_priv->pin_count > 0)
4137 i915_gem_object_unpin(obj);
4139 if (obj_priv->phys_obj)
4140 i915_gem_detach_phys_object(dev, obj);
4142 i915_gem_object_unbind(obj);
4144 if (obj_priv->mmap_offset)
4145 i915_gem_free_mmap_offset(obj);
4147 kfree(obj_priv->page_cpu_valid);
4148 kfree(obj_priv->bit_17);
4149 kfree(obj->driver_private);
4152 /** Unbinds all inactive objects. */
4154 i915_gem_evict_from_inactive_list(struct drm_device *dev)
4156 drm_i915_private_t *dev_priv = dev->dev_private;
4158 while (!list_empty(&dev_priv->mm.inactive_list)) {
4159 struct drm_gem_object *obj;
4162 obj = list_first_entry(&dev_priv->mm.inactive_list,
4163 struct drm_i915_gem_object,
4166 ret = i915_gem_object_unbind(obj);
4168 DRM_ERROR("Error unbinding object: %d\n", ret);
4177 i915_gem_idle(struct drm_device *dev)
4179 drm_i915_private_t *dev_priv = dev->dev_private;
4180 uint32_t seqno, cur_seqno, last_seqno;
4183 mutex_lock(&dev->struct_mutex);
4185 if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
4186 mutex_unlock(&dev->struct_mutex);
4190 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4191 * We need to replace this with a semaphore, or something.
4193 dev_priv->mm.suspended = 1;
4194 del_timer(&dev_priv->hangcheck_timer);
4196 /* Cancel the retire work handler, wait for it to finish if running
4198 mutex_unlock(&dev->struct_mutex);
4199 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4200 mutex_lock(&dev->struct_mutex);
4202 i915_kernel_lost_context(dev);
4204 /* Flush the GPU along with all non-CPU write domains
4206 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
4207 seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
4210 mutex_unlock(&dev->struct_mutex);
4214 dev_priv->mm.waiting_gem_seqno = seqno;
4218 cur_seqno = i915_get_gem_seqno(dev);
4219 if (i915_seqno_passed(cur_seqno, seqno))
4221 if (last_seqno == cur_seqno) {
4222 if (stuck++ > 100) {
4223 DRM_ERROR("hardware wedged\n");
4224 atomic_set(&dev_priv->mm.wedged, 1);
4225 DRM_WAKEUP(&dev_priv->irq_queue);
4230 last_seqno = cur_seqno;
4232 dev_priv->mm.waiting_gem_seqno = 0;
4234 i915_gem_retire_requests(dev);
4236 spin_lock(&dev_priv->mm.active_list_lock);
4237 if (!atomic_read(&dev_priv->mm.wedged)) {
4238 /* Active and flushing should now be empty as we've
4239 * waited for a sequence higher than any pending execbuffer
4241 WARN_ON(!list_empty(&dev_priv->mm.active_list));
4242 WARN_ON(!list_empty(&dev_priv->mm.flushing_list));
4243 /* Request should now be empty as we've also waited
4244 * for the last request in the list
4246 WARN_ON(!list_empty(&dev_priv->mm.request_list));
4249 /* Empty the active and flushing lists to inactive. If there's
4250 * anything left at this point, it means that we're wedged and
4251 * nothing good's going to happen by leaving them there. So strip
4252 * the GPU domains and just stuff them onto inactive.
4254 while (!list_empty(&dev_priv->mm.active_list)) {
4255 struct drm_gem_object *obj;
4256 uint32_t old_write_domain;
4258 obj = list_first_entry(&dev_priv->mm.active_list,
4259 struct drm_i915_gem_object,
4261 old_write_domain = obj->write_domain;
4262 obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
4263 i915_gem_object_move_to_inactive(obj);
4265 trace_i915_gem_object_change_domain(obj,
4269 spin_unlock(&dev_priv->mm.active_list_lock);
4271 while (!list_empty(&dev_priv->mm.flushing_list)) {
4272 struct drm_gem_object *obj;
4273 uint32_t old_write_domain;
4275 obj = list_first_entry(&dev_priv->mm.flushing_list,
4276 struct drm_i915_gem_object,
4278 old_write_domain = obj->write_domain;
4279 obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
4280 i915_gem_object_move_to_inactive(obj);
4282 trace_i915_gem_object_change_domain(obj,
4288 /* Move all inactive buffers out of the GTT. */
4289 ret = i915_gem_evict_from_inactive_list(dev);
4290 WARN_ON(!list_empty(&dev_priv->mm.inactive_list));
4292 mutex_unlock(&dev->struct_mutex);
4296 i915_gem_cleanup_ringbuffer(dev);
4297 mutex_unlock(&dev->struct_mutex);
4303 i915_gem_init_hws(struct drm_device *dev)
4305 drm_i915_private_t *dev_priv = dev->dev_private;
4306 struct drm_gem_object *obj;
4307 struct drm_i915_gem_object *obj_priv;
4310 /* If we need a physical address for the status page, it's already
4311 * initialized at driver load time.
4313 if (!I915_NEED_GFX_HWS(dev))
4316 obj = drm_gem_object_alloc(dev, 4096);
4318 DRM_ERROR("Failed to allocate status page\n");
4321 obj_priv = obj->driver_private;
4322 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4324 ret = i915_gem_object_pin(obj, 4096);
4326 drm_gem_object_unreference(obj);
4330 dev_priv->status_gfx_addr = obj_priv->gtt_offset;
4332 dev_priv->hw_status_page = kmap(obj_priv->pages[0]);
4333 if (dev_priv->hw_status_page == NULL) {
4334 DRM_ERROR("Failed to map status page.\n");
4335 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4336 i915_gem_object_unpin(obj);
4337 drm_gem_object_unreference(obj);
4340 dev_priv->hws_obj = obj;
4341 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
4342 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
4343 I915_READ(HWS_PGA); /* posting read */
4344 DRM_DEBUG("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
4350 i915_gem_cleanup_hws(struct drm_device *dev)
4352 drm_i915_private_t *dev_priv = dev->dev_private;
4353 struct drm_gem_object *obj;
4354 struct drm_i915_gem_object *obj_priv;
4356 if (dev_priv->hws_obj == NULL)
4359 obj = dev_priv->hws_obj;
4360 obj_priv = obj->driver_private;
4362 kunmap(obj_priv->pages[0]);
4363 i915_gem_object_unpin(obj);
4364 drm_gem_object_unreference(obj);
4365 dev_priv->hws_obj = NULL;
4367 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4368 dev_priv->hw_status_page = NULL;
4370 /* Write high address into HWS_PGA when disabling. */
4371 I915_WRITE(HWS_PGA, 0x1ffff000);
4375 i915_gem_init_ringbuffer(struct drm_device *dev)
4377 drm_i915_private_t *dev_priv = dev->dev_private;
4378 struct drm_gem_object *obj;
4379 struct drm_i915_gem_object *obj_priv;
4380 drm_i915_ring_buffer_t *ring = &dev_priv->ring;
4384 ret = i915_gem_init_hws(dev);
4388 obj = drm_gem_object_alloc(dev, 128 * 1024);
4390 DRM_ERROR("Failed to allocate ringbuffer\n");
4391 i915_gem_cleanup_hws(dev);
4394 obj_priv = obj->driver_private;
4396 ret = i915_gem_object_pin(obj, 4096);
4398 drm_gem_object_unreference(obj);
4399 i915_gem_cleanup_hws(dev);
4403 /* Set up the kernel mapping for the ring. */
4404 ring->Size = obj->size;
4406 ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
4407 ring->map.size = obj->size;
4409 ring->map.flags = 0;
4412 drm_core_ioremap_wc(&ring->map, dev);
4413 if (ring->map.handle == NULL) {
4414 DRM_ERROR("Failed to map ringbuffer.\n");
4415 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4416 i915_gem_object_unpin(obj);
4417 drm_gem_object_unreference(obj);
4418 i915_gem_cleanup_hws(dev);
4421 ring->ring_obj = obj;
4422 ring->virtual_start = ring->map.handle;
4424 /* Stop the ring if it's running. */
4425 I915_WRITE(PRB0_CTL, 0);
4426 I915_WRITE(PRB0_TAIL, 0);
4427 I915_WRITE(PRB0_HEAD, 0);
4429 /* Initialize the ring. */
4430 I915_WRITE(PRB0_START, obj_priv->gtt_offset);
4431 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4433 /* G45 ring initialization fails to reset head to zero */
4435 DRM_ERROR("Ring head not reset to zero "
4436 "ctl %08x head %08x tail %08x start %08x\n",
4437 I915_READ(PRB0_CTL),
4438 I915_READ(PRB0_HEAD),
4439 I915_READ(PRB0_TAIL),
4440 I915_READ(PRB0_START));
4441 I915_WRITE(PRB0_HEAD, 0);
4443 DRM_ERROR("Ring head forced to zero "
4444 "ctl %08x head %08x tail %08x start %08x\n",
4445 I915_READ(PRB0_CTL),
4446 I915_READ(PRB0_HEAD),
4447 I915_READ(PRB0_TAIL),
4448 I915_READ(PRB0_START));
4451 I915_WRITE(PRB0_CTL,
4452 ((obj->size - 4096) & RING_NR_PAGES) |
4456 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4458 /* If the head is still not zero, the ring is dead */
4460 DRM_ERROR("Ring initialization failed "
4461 "ctl %08x head %08x tail %08x start %08x\n",
4462 I915_READ(PRB0_CTL),
4463 I915_READ(PRB0_HEAD),
4464 I915_READ(PRB0_TAIL),
4465 I915_READ(PRB0_START));
4469 /* Update our cache of the ring state */
4470 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4471 i915_kernel_lost_context(dev);
4473 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4474 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
4475 ring->space = ring->head - (ring->tail + 8);
4476 if (ring->space < 0)
4477 ring->space += ring->Size;
4484 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4486 drm_i915_private_t *dev_priv = dev->dev_private;
4488 if (dev_priv->ring.ring_obj == NULL)
4491 drm_core_ioremapfree(&dev_priv->ring.map, dev);
4493 i915_gem_object_unpin(dev_priv->ring.ring_obj);
4494 drm_gem_object_unreference(dev_priv->ring.ring_obj);
4495 dev_priv->ring.ring_obj = NULL;
4496 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4498 i915_gem_cleanup_hws(dev);
4502 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4503 struct drm_file *file_priv)
4505 drm_i915_private_t *dev_priv = dev->dev_private;
4508 if (drm_core_check_feature(dev, DRIVER_MODESET))
4511 if (atomic_read(&dev_priv->mm.wedged)) {
4512 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4513 atomic_set(&dev_priv->mm.wedged, 0);
4516 mutex_lock(&dev->struct_mutex);
4517 dev_priv->mm.suspended = 0;
4519 ret = i915_gem_init_ringbuffer(dev);
4521 mutex_unlock(&dev->struct_mutex);
4525 spin_lock(&dev_priv->mm.active_list_lock);
4526 BUG_ON(!list_empty(&dev_priv->mm.active_list));
4527 spin_unlock(&dev_priv->mm.active_list_lock);
4529 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4530 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4531 BUG_ON(!list_empty(&dev_priv->mm.request_list));
4532 mutex_unlock(&dev->struct_mutex);
4534 drm_irq_install(dev);
4540 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4541 struct drm_file *file_priv)
4545 if (drm_core_check_feature(dev, DRIVER_MODESET))
4548 ret = i915_gem_idle(dev);
4549 drm_irq_uninstall(dev);
4555 i915_gem_lastclose(struct drm_device *dev)
4559 if (drm_core_check_feature(dev, DRIVER_MODESET))
4562 ret = i915_gem_idle(dev);
4564 DRM_ERROR("failed to idle hardware: %d\n", ret);
4568 i915_gem_load(struct drm_device *dev)
4571 drm_i915_private_t *dev_priv = dev->dev_private;
4573 spin_lock_init(&dev_priv->mm.active_list_lock);
4574 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4575 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4576 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4577 INIT_LIST_HEAD(&dev_priv->mm.request_list);
4578 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4579 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4580 i915_gem_retire_work_handler);
4581 dev_priv->mm.next_gem_seqno = 1;
4583 spin_lock(&shrink_list_lock);
4584 list_add(&dev_priv->mm.shrink_list, &shrink_list);
4585 spin_unlock(&shrink_list_lock);
4587 /* Old X drivers will take 0-2 for front, back, depth buffers */
4588 dev_priv->fence_reg_start = 3;
4590 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4591 dev_priv->num_fence_regs = 16;
4593 dev_priv->num_fence_regs = 8;
4595 /* Initialize fence registers to zero */
4596 if (IS_I965G(dev)) {
4597 for (i = 0; i < 16; i++)
4598 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4600 for (i = 0; i < 8; i++)
4601 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4602 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4603 for (i = 0; i < 8; i++)
4604 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4607 i915_gem_detect_bit_6_swizzle(dev);
4611 * Create a physically contiguous memory object for this object
4612 * e.g. for cursor + overlay regs
4614 int i915_gem_init_phys_object(struct drm_device *dev,
4617 drm_i915_private_t *dev_priv = dev->dev_private;
4618 struct drm_i915_gem_phys_object *phys_obj;
4621 if (dev_priv->mm.phys_objs[id - 1] || !size)
4624 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4630 phys_obj->handle = drm_pci_alloc(dev, size, 0, 0xffffffff);
4631 if (!phys_obj->handle) {
4636 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4639 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4647 void i915_gem_free_phys_object(struct drm_device *dev, int id)
4649 drm_i915_private_t *dev_priv = dev->dev_private;
4650 struct drm_i915_gem_phys_object *phys_obj;
4652 if (!dev_priv->mm.phys_objs[id - 1])
4655 phys_obj = dev_priv->mm.phys_objs[id - 1];
4656 if (phys_obj->cur_obj) {
4657 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4661 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4663 drm_pci_free(dev, phys_obj->handle);
4665 dev_priv->mm.phys_objs[id - 1] = NULL;
4668 void i915_gem_free_all_phys_object(struct drm_device *dev)
4672 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4673 i915_gem_free_phys_object(dev, i);
4676 void i915_gem_detach_phys_object(struct drm_device *dev,
4677 struct drm_gem_object *obj)
4679 struct drm_i915_gem_object *obj_priv;
4684 obj_priv = obj->driver_private;
4685 if (!obj_priv->phys_obj)
4688 ret = i915_gem_object_get_pages(obj);
4692 page_count = obj->size / PAGE_SIZE;
4694 for (i = 0; i < page_count; i++) {
4695 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
4696 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4698 memcpy(dst, src, PAGE_SIZE);
4699 kunmap_atomic(dst, KM_USER0);
4701 drm_clflush_pages(obj_priv->pages, page_count);
4702 drm_agp_chipset_flush(dev);
4704 i915_gem_object_put_pages(obj);
4706 obj_priv->phys_obj->cur_obj = NULL;
4707 obj_priv->phys_obj = NULL;
4711 i915_gem_attach_phys_object(struct drm_device *dev,
4712 struct drm_gem_object *obj, int id)
4714 drm_i915_private_t *dev_priv = dev->dev_private;
4715 struct drm_i915_gem_object *obj_priv;
4720 if (id > I915_MAX_PHYS_OBJECT)
4723 obj_priv = obj->driver_private;
4725 if (obj_priv->phys_obj) {
4726 if (obj_priv->phys_obj->id == id)
4728 i915_gem_detach_phys_object(dev, obj);
4732 /* create a new object */
4733 if (!dev_priv->mm.phys_objs[id - 1]) {
4734 ret = i915_gem_init_phys_object(dev, id,
4737 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
4742 /* bind to the object */
4743 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4744 obj_priv->phys_obj->cur_obj = obj;
4746 ret = i915_gem_object_get_pages(obj);
4748 DRM_ERROR("failed to get page list\n");
4752 page_count = obj->size / PAGE_SIZE;
4754 for (i = 0; i < page_count; i++) {
4755 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
4756 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4758 memcpy(dst, src, PAGE_SIZE);
4759 kunmap_atomic(src, KM_USER0);
4762 i915_gem_object_put_pages(obj);
4770 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4771 struct drm_i915_gem_pwrite *args,
4772 struct drm_file *file_priv)
4774 struct drm_i915_gem_object *obj_priv = obj->driver_private;
4777 char __user *user_data;
4779 user_data = (char __user *) (uintptr_t) args->data_ptr;
4780 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4782 DRM_DEBUG("obj_addr %p, %lld\n", obj_addr, args->size);
4783 ret = copy_from_user(obj_addr, user_data, args->size);
4787 drm_agp_chipset_flush(dev);
4791 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
4793 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
4795 /* Clean up our request list when the client is going away, so that
4796 * later retire_requests won't dereference our soon-to-be-gone
4799 mutex_lock(&dev->struct_mutex);
4800 while (!list_empty(&i915_file_priv->mm.request_list))
4801 list_del_init(i915_file_priv->mm.request_list.next);
4802 mutex_unlock(&dev->struct_mutex);
4806 i915_gem_shrink(int nr_to_scan, gfp_t gfp_mask)
4808 drm_i915_private_t *dev_priv, *next_dev;
4809 struct drm_i915_gem_object *obj_priv, *next_obj;
4811 int would_deadlock = 1;
4813 /* "fast-path" to count number of available objects */
4814 if (nr_to_scan == 0) {
4815 spin_lock(&shrink_list_lock);
4816 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4817 struct drm_device *dev = dev_priv->dev;
4819 if (mutex_trylock(&dev->struct_mutex)) {
4820 list_for_each_entry(obj_priv,
4821 &dev_priv->mm.inactive_list,
4824 mutex_unlock(&dev->struct_mutex);
4827 spin_unlock(&shrink_list_lock);
4829 return (cnt / 100) * sysctl_vfs_cache_pressure;
4832 spin_lock(&shrink_list_lock);
4834 /* first scan for clean buffers */
4835 list_for_each_entry_safe(dev_priv, next_dev,
4836 &shrink_list, mm.shrink_list) {
4837 struct drm_device *dev = dev_priv->dev;
4839 if (! mutex_trylock(&dev->struct_mutex))
4842 spin_unlock(&shrink_list_lock);
4844 i915_gem_retire_requests(dev);
4846 list_for_each_entry_safe(obj_priv, next_obj,
4847 &dev_priv->mm.inactive_list,
4849 if (i915_gem_object_is_purgeable(obj_priv)) {
4850 i915_gem_object_unbind(obj_priv->obj);
4851 if (--nr_to_scan <= 0)
4856 spin_lock(&shrink_list_lock);
4857 mutex_unlock(&dev->struct_mutex);
4861 if (nr_to_scan <= 0)
4865 /* second pass, evict/count anything still on the inactive list */
4866 list_for_each_entry_safe(dev_priv, next_dev,
4867 &shrink_list, mm.shrink_list) {
4868 struct drm_device *dev = dev_priv->dev;
4870 if (! mutex_trylock(&dev->struct_mutex))
4873 spin_unlock(&shrink_list_lock);
4875 list_for_each_entry_safe(obj_priv, next_obj,
4876 &dev_priv->mm.inactive_list,
4878 if (nr_to_scan > 0) {
4879 i915_gem_object_unbind(obj_priv->obj);
4885 spin_lock(&shrink_list_lock);
4886 mutex_unlock(&dev->struct_mutex);
4891 spin_unlock(&shrink_list_lock);
4896 return (cnt / 100) * sysctl_vfs_cache_pressure;
4901 static struct shrinker shrinker = {
4902 .shrink = i915_gem_shrink,
4903 .seeks = DEFAULT_SEEKS,
4907 i915_gem_shrinker_init(void)
4909 register_shrinker(&shrinker);
4913 i915_gem_shrinker_exit(void)
4915 unregister_shrinker(&shrinker);