2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "intel_drv.h"
33 #include <linux/swap.h>
34 #include <linux/pci.h>
36 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
38 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
39 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
40 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
41 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
43 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
46 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
47 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
48 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
50 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
51 static int i915_gem_evict_something(struct drm_device *dev);
52 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
53 struct drm_i915_gem_pwrite *args,
54 struct drm_file *file_priv);
56 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
59 drm_i915_private_t *dev_priv = dev->dev_private;
62 (start & (PAGE_SIZE - 1)) != 0 ||
63 (end & (PAGE_SIZE - 1)) != 0) {
67 drm_mm_init(&dev_priv->mm.gtt_space, start,
70 dev->gtt_total = (uint32_t) (end - start);
76 i915_gem_init_ioctl(struct drm_device *dev, void *data,
77 struct drm_file *file_priv)
79 struct drm_i915_gem_init *args = data;
82 mutex_lock(&dev->struct_mutex);
83 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
84 mutex_unlock(&dev->struct_mutex);
90 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
91 struct drm_file *file_priv)
93 struct drm_i915_gem_get_aperture *args = data;
95 if (!(dev->driver->driver_features & DRIVER_GEM))
98 args->aper_size = dev->gtt_total;
99 args->aper_available_size = (args->aper_size -
100 atomic_read(&dev->pin_memory));
107 * Creates a new mm object and returns a handle to it.
110 i915_gem_create_ioctl(struct drm_device *dev, void *data,
111 struct drm_file *file_priv)
113 struct drm_i915_gem_create *args = data;
114 struct drm_gem_object *obj;
118 args->size = roundup(args->size, PAGE_SIZE);
120 /* Allocate the new object */
121 obj = drm_gem_object_alloc(dev, args->size);
125 ret = drm_gem_handle_create(file_priv, obj, &handle);
126 mutex_lock(&dev->struct_mutex);
127 drm_gem_object_handle_unreference(obj);
128 mutex_unlock(&dev->struct_mutex);
133 args->handle = handle;
139 fast_shmem_read(struct page **pages,
140 loff_t page_base, int page_offset,
147 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
150 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
151 kunmap_atomic(vaddr, KM_USER0);
159 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
161 drm_i915_private_t *dev_priv = obj->dev->dev_private;
162 struct drm_i915_gem_object *obj_priv = obj->driver_private;
164 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
165 obj_priv->tiling_mode != I915_TILING_NONE;
169 slow_shmem_copy(struct page *dst_page,
171 struct page *src_page,
175 char *dst_vaddr, *src_vaddr;
177 dst_vaddr = kmap_atomic(dst_page, KM_USER0);
178 if (dst_vaddr == NULL)
181 src_vaddr = kmap_atomic(src_page, KM_USER1);
182 if (src_vaddr == NULL) {
183 kunmap_atomic(dst_vaddr, KM_USER0);
187 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
189 kunmap_atomic(src_vaddr, KM_USER1);
190 kunmap_atomic(dst_vaddr, KM_USER0);
196 slow_shmem_bit17_copy(struct page *gpu_page,
198 struct page *cpu_page,
203 char *gpu_vaddr, *cpu_vaddr;
205 /* Use the unswizzled path if this page isn't affected. */
206 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
208 return slow_shmem_copy(cpu_page, cpu_offset,
209 gpu_page, gpu_offset, length);
211 return slow_shmem_copy(gpu_page, gpu_offset,
212 cpu_page, cpu_offset, length);
215 gpu_vaddr = kmap_atomic(gpu_page, KM_USER0);
216 if (gpu_vaddr == NULL)
219 cpu_vaddr = kmap_atomic(cpu_page, KM_USER1);
220 if (cpu_vaddr == NULL) {
221 kunmap_atomic(gpu_vaddr, KM_USER0);
225 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
226 * XORing with the other bits (A9 for Y, A9 and A10 for X)
229 int cacheline_end = ALIGN(gpu_offset + 1, 64);
230 int this_length = min(cacheline_end - gpu_offset, length);
231 int swizzled_gpu_offset = gpu_offset ^ 64;
234 memcpy(cpu_vaddr + cpu_offset,
235 gpu_vaddr + swizzled_gpu_offset,
238 memcpy(gpu_vaddr + swizzled_gpu_offset,
239 cpu_vaddr + cpu_offset,
242 cpu_offset += this_length;
243 gpu_offset += this_length;
244 length -= this_length;
247 kunmap_atomic(cpu_vaddr, KM_USER1);
248 kunmap_atomic(gpu_vaddr, KM_USER0);
254 * This is the fast shmem pread path, which attempts to copy_from_user directly
255 * from the backing pages of the object to the user's address space. On a
256 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
259 i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
260 struct drm_i915_gem_pread *args,
261 struct drm_file *file_priv)
263 struct drm_i915_gem_object *obj_priv = obj->driver_private;
265 loff_t offset, page_base;
266 char __user *user_data;
267 int page_offset, page_length;
270 user_data = (char __user *) (uintptr_t) args->data_ptr;
273 mutex_lock(&dev->struct_mutex);
275 ret = i915_gem_object_get_pages(obj);
279 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
284 obj_priv = obj->driver_private;
285 offset = args->offset;
288 /* Operation in this page
290 * page_base = page offset within aperture
291 * page_offset = offset within page
292 * page_length = bytes to copy for this page
294 page_base = (offset & ~(PAGE_SIZE-1));
295 page_offset = offset & (PAGE_SIZE-1);
296 page_length = remain;
297 if ((page_offset + remain) > PAGE_SIZE)
298 page_length = PAGE_SIZE - page_offset;
300 ret = fast_shmem_read(obj_priv->pages,
301 page_base, page_offset,
302 user_data, page_length);
306 remain -= page_length;
307 user_data += page_length;
308 offset += page_length;
312 i915_gem_object_put_pages(obj);
314 mutex_unlock(&dev->struct_mutex);
320 * This is the fallback shmem pread path, which allocates temporary storage
321 * in kernel space to copy_to_user into outside of the struct_mutex, so we
322 * can copy out of the object's backing pages while holding the struct mutex
323 * and not take page faults.
326 i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
327 struct drm_i915_gem_pread *args,
328 struct drm_file *file_priv)
330 struct drm_i915_gem_object *obj_priv = obj->driver_private;
331 struct mm_struct *mm = current->mm;
332 struct page **user_pages;
334 loff_t offset, pinned_pages, i;
335 loff_t first_data_page, last_data_page, num_pages;
336 int shmem_page_index, shmem_page_offset;
337 int data_page_index, data_page_offset;
340 uint64_t data_ptr = args->data_ptr;
341 int do_bit17_swizzling;
345 /* Pin the user pages containing the data. We can't fault while
346 * holding the struct mutex, yet we want to hold it while
347 * dereferencing the user data.
349 first_data_page = data_ptr / PAGE_SIZE;
350 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
351 num_pages = last_data_page - first_data_page + 1;
353 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
354 if (user_pages == NULL)
357 down_read(&mm->mmap_sem);
358 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
359 num_pages, 1, 0, user_pages, NULL);
360 up_read(&mm->mmap_sem);
361 if (pinned_pages < num_pages) {
363 goto fail_put_user_pages;
366 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
368 mutex_lock(&dev->struct_mutex);
370 ret = i915_gem_object_get_pages(obj);
374 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
379 obj_priv = obj->driver_private;
380 offset = args->offset;
383 /* Operation in this page
385 * shmem_page_index = page number within shmem file
386 * shmem_page_offset = offset within page in shmem file
387 * data_page_index = page number in get_user_pages return
388 * data_page_offset = offset with data_page_index page.
389 * page_length = bytes to copy for this page
391 shmem_page_index = offset / PAGE_SIZE;
392 shmem_page_offset = offset & ~PAGE_MASK;
393 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
394 data_page_offset = data_ptr & ~PAGE_MASK;
396 page_length = remain;
397 if ((shmem_page_offset + page_length) > PAGE_SIZE)
398 page_length = PAGE_SIZE - shmem_page_offset;
399 if ((data_page_offset + page_length) > PAGE_SIZE)
400 page_length = PAGE_SIZE - data_page_offset;
402 if (do_bit17_swizzling) {
403 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
405 user_pages[data_page_index],
410 ret = slow_shmem_copy(user_pages[data_page_index],
412 obj_priv->pages[shmem_page_index],
419 remain -= page_length;
420 data_ptr += page_length;
421 offset += page_length;
425 i915_gem_object_put_pages(obj);
427 mutex_unlock(&dev->struct_mutex);
429 for (i = 0; i < pinned_pages; i++) {
430 SetPageDirty(user_pages[i]);
431 page_cache_release(user_pages[i]);
433 drm_free_large(user_pages);
439 * Reads data from the object referenced by handle.
441 * On error, the contents of *data are undefined.
444 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
445 struct drm_file *file_priv)
447 struct drm_i915_gem_pread *args = data;
448 struct drm_gem_object *obj;
449 struct drm_i915_gem_object *obj_priv;
452 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
455 obj_priv = obj->driver_private;
457 /* Bounds check source.
459 * XXX: This could use review for overflow issues...
461 if (args->offset > obj->size || args->size > obj->size ||
462 args->offset + args->size > obj->size) {
463 drm_gem_object_unreference(obj);
467 if (i915_gem_object_needs_bit17_swizzle(obj)) {
468 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
470 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
472 ret = i915_gem_shmem_pread_slow(dev, obj, args,
476 drm_gem_object_unreference(obj);
481 /* This is the fast write path which cannot handle
482 * page faults in the source data
486 fast_user_write(struct io_mapping *mapping,
487 loff_t page_base, int page_offset,
488 char __user *user_data,
492 unsigned long unwritten;
494 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
495 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
497 io_mapping_unmap_atomic(vaddr_atomic);
503 /* Here's the write path which can sleep for
508 slow_kernel_write(struct io_mapping *mapping,
509 loff_t gtt_base, int gtt_offset,
510 struct page *user_page, int user_offset,
513 char *src_vaddr, *dst_vaddr;
514 unsigned long unwritten;
516 dst_vaddr = io_mapping_map_atomic_wc(mapping, gtt_base);
517 src_vaddr = kmap_atomic(user_page, KM_USER1);
518 unwritten = __copy_from_user_inatomic_nocache(dst_vaddr + gtt_offset,
519 src_vaddr + user_offset,
521 kunmap_atomic(src_vaddr, KM_USER1);
522 io_mapping_unmap_atomic(dst_vaddr);
529 fast_shmem_write(struct page **pages,
530 loff_t page_base, int page_offset,
535 unsigned long unwritten;
537 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
540 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
541 kunmap_atomic(vaddr, KM_USER0);
549 * This is the fast pwrite path, where we copy the data directly from the
550 * user into the GTT, uncached.
553 i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
554 struct drm_i915_gem_pwrite *args,
555 struct drm_file *file_priv)
557 struct drm_i915_gem_object *obj_priv = obj->driver_private;
558 drm_i915_private_t *dev_priv = dev->dev_private;
560 loff_t offset, page_base;
561 char __user *user_data;
562 int page_offset, page_length;
565 user_data = (char __user *) (uintptr_t) args->data_ptr;
567 if (!access_ok(VERIFY_READ, user_data, remain))
571 mutex_lock(&dev->struct_mutex);
572 ret = i915_gem_object_pin(obj, 0);
574 mutex_unlock(&dev->struct_mutex);
577 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
581 obj_priv = obj->driver_private;
582 offset = obj_priv->gtt_offset + args->offset;
585 /* Operation in this page
587 * page_base = page offset within aperture
588 * page_offset = offset within page
589 * page_length = bytes to copy for this page
591 page_base = (offset & ~(PAGE_SIZE-1));
592 page_offset = offset & (PAGE_SIZE-1);
593 page_length = remain;
594 if ((page_offset + remain) > PAGE_SIZE)
595 page_length = PAGE_SIZE - page_offset;
597 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
598 page_offset, user_data, page_length);
600 /* If we get a fault while copying data, then (presumably) our
601 * source page isn't available. Return the error and we'll
602 * retry in the slow path.
607 remain -= page_length;
608 user_data += page_length;
609 offset += page_length;
613 i915_gem_object_unpin(obj);
614 mutex_unlock(&dev->struct_mutex);
620 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
621 * the memory and maps it using kmap_atomic for copying.
623 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
624 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
627 i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
628 struct drm_i915_gem_pwrite *args,
629 struct drm_file *file_priv)
631 struct drm_i915_gem_object *obj_priv = obj->driver_private;
632 drm_i915_private_t *dev_priv = dev->dev_private;
634 loff_t gtt_page_base, offset;
635 loff_t first_data_page, last_data_page, num_pages;
636 loff_t pinned_pages, i;
637 struct page **user_pages;
638 struct mm_struct *mm = current->mm;
639 int gtt_page_offset, data_page_offset, data_page_index, page_length;
641 uint64_t data_ptr = args->data_ptr;
645 /* Pin the user pages containing the data. We can't fault while
646 * holding the struct mutex, and all of the pwrite implementations
647 * want to hold it while dereferencing the user data.
649 first_data_page = data_ptr / PAGE_SIZE;
650 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
651 num_pages = last_data_page - first_data_page + 1;
653 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
654 if (user_pages == NULL)
657 down_read(&mm->mmap_sem);
658 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
659 num_pages, 0, 0, user_pages, NULL);
660 up_read(&mm->mmap_sem);
661 if (pinned_pages < num_pages) {
663 goto out_unpin_pages;
666 mutex_lock(&dev->struct_mutex);
667 ret = i915_gem_object_pin(obj, 0);
671 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
673 goto out_unpin_object;
675 obj_priv = obj->driver_private;
676 offset = obj_priv->gtt_offset + args->offset;
679 /* Operation in this page
681 * gtt_page_base = page offset within aperture
682 * gtt_page_offset = offset within page in aperture
683 * data_page_index = page number in get_user_pages return
684 * data_page_offset = offset with data_page_index page.
685 * page_length = bytes to copy for this page
687 gtt_page_base = offset & PAGE_MASK;
688 gtt_page_offset = offset & ~PAGE_MASK;
689 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
690 data_page_offset = data_ptr & ~PAGE_MASK;
692 page_length = remain;
693 if ((gtt_page_offset + page_length) > PAGE_SIZE)
694 page_length = PAGE_SIZE - gtt_page_offset;
695 if ((data_page_offset + page_length) > PAGE_SIZE)
696 page_length = PAGE_SIZE - data_page_offset;
698 ret = slow_kernel_write(dev_priv->mm.gtt_mapping,
699 gtt_page_base, gtt_page_offset,
700 user_pages[data_page_index],
704 /* If we get a fault while copying data, then (presumably) our
705 * source page isn't available. Return the error and we'll
706 * retry in the slow path.
709 goto out_unpin_object;
711 remain -= page_length;
712 offset += page_length;
713 data_ptr += page_length;
717 i915_gem_object_unpin(obj);
719 mutex_unlock(&dev->struct_mutex);
721 for (i = 0; i < pinned_pages; i++)
722 page_cache_release(user_pages[i]);
723 drm_free_large(user_pages);
729 * This is the fast shmem pwrite path, which attempts to directly
730 * copy_from_user into the kmapped pages backing the object.
733 i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
734 struct drm_i915_gem_pwrite *args,
735 struct drm_file *file_priv)
737 struct drm_i915_gem_object *obj_priv = obj->driver_private;
739 loff_t offset, page_base;
740 char __user *user_data;
741 int page_offset, page_length;
744 user_data = (char __user *) (uintptr_t) args->data_ptr;
747 mutex_lock(&dev->struct_mutex);
749 ret = i915_gem_object_get_pages(obj);
753 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
757 obj_priv = obj->driver_private;
758 offset = args->offset;
762 /* Operation in this page
764 * page_base = page offset within aperture
765 * page_offset = offset within page
766 * page_length = bytes to copy for this page
768 page_base = (offset & ~(PAGE_SIZE-1));
769 page_offset = offset & (PAGE_SIZE-1);
770 page_length = remain;
771 if ((page_offset + remain) > PAGE_SIZE)
772 page_length = PAGE_SIZE - page_offset;
774 ret = fast_shmem_write(obj_priv->pages,
775 page_base, page_offset,
776 user_data, page_length);
780 remain -= page_length;
781 user_data += page_length;
782 offset += page_length;
786 i915_gem_object_put_pages(obj);
788 mutex_unlock(&dev->struct_mutex);
794 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
795 * the memory and maps it using kmap_atomic for copying.
797 * This avoids taking mmap_sem for faulting on the user's address while the
798 * struct_mutex is held.
801 i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
802 struct drm_i915_gem_pwrite *args,
803 struct drm_file *file_priv)
805 struct drm_i915_gem_object *obj_priv = obj->driver_private;
806 struct mm_struct *mm = current->mm;
807 struct page **user_pages;
809 loff_t offset, pinned_pages, i;
810 loff_t first_data_page, last_data_page, num_pages;
811 int shmem_page_index, shmem_page_offset;
812 int data_page_index, data_page_offset;
815 uint64_t data_ptr = args->data_ptr;
816 int do_bit17_swizzling;
820 /* Pin the user pages containing the data. We can't fault while
821 * holding the struct mutex, and all of the pwrite implementations
822 * want to hold it while dereferencing the user data.
824 first_data_page = data_ptr / PAGE_SIZE;
825 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
826 num_pages = last_data_page - first_data_page + 1;
828 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
829 if (user_pages == NULL)
832 down_read(&mm->mmap_sem);
833 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
834 num_pages, 0, 0, user_pages, NULL);
835 up_read(&mm->mmap_sem);
836 if (pinned_pages < num_pages) {
838 goto fail_put_user_pages;
841 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
843 mutex_lock(&dev->struct_mutex);
845 ret = i915_gem_object_get_pages(obj);
849 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
853 obj_priv = obj->driver_private;
854 offset = args->offset;
858 /* Operation in this page
860 * shmem_page_index = page number within shmem file
861 * shmem_page_offset = offset within page in shmem file
862 * data_page_index = page number in get_user_pages return
863 * data_page_offset = offset with data_page_index page.
864 * page_length = bytes to copy for this page
866 shmem_page_index = offset / PAGE_SIZE;
867 shmem_page_offset = offset & ~PAGE_MASK;
868 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
869 data_page_offset = data_ptr & ~PAGE_MASK;
871 page_length = remain;
872 if ((shmem_page_offset + page_length) > PAGE_SIZE)
873 page_length = PAGE_SIZE - shmem_page_offset;
874 if ((data_page_offset + page_length) > PAGE_SIZE)
875 page_length = PAGE_SIZE - data_page_offset;
877 if (do_bit17_swizzling) {
878 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
880 user_pages[data_page_index],
885 ret = slow_shmem_copy(obj_priv->pages[shmem_page_index],
887 user_pages[data_page_index],
894 remain -= page_length;
895 data_ptr += page_length;
896 offset += page_length;
900 i915_gem_object_put_pages(obj);
902 mutex_unlock(&dev->struct_mutex);
904 for (i = 0; i < pinned_pages; i++)
905 page_cache_release(user_pages[i]);
906 drm_free_large(user_pages);
912 * Writes data to the object referenced by handle.
914 * On error, the contents of the buffer that were to be modified are undefined.
917 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
918 struct drm_file *file_priv)
920 struct drm_i915_gem_pwrite *args = data;
921 struct drm_gem_object *obj;
922 struct drm_i915_gem_object *obj_priv;
925 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
928 obj_priv = obj->driver_private;
930 /* Bounds check destination.
932 * XXX: This could use review for overflow issues...
934 if (args->offset > obj->size || args->size > obj->size ||
935 args->offset + args->size > obj->size) {
936 drm_gem_object_unreference(obj);
940 /* We can only do the GTT pwrite on untiled buffers, as otherwise
941 * it would end up going through the fenced access, and we'll get
942 * different detiling behavior between reading and writing.
943 * pread/pwrite currently are reading and writing from the CPU
944 * perspective, requiring manual detiling by the client.
946 if (obj_priv->phys_obj)
947 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
948 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
949 dev->gtt_total != 0) {
950 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
951 if (ret == -EFAULT) {
952 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
955 } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
956 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
958 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
959 if (ret == -EFAULT) {
960 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
967 DRM_INFO("pwrite failed %d\n", ret);
970 drm_gem_object_unreference(obj);
976 * Called when user space prepares to use an object with the CPU, either
977 * through the mmap ioctl's mapping or a GTT mapping.
980 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
981 struct drm_file *file_priv)
983 struct drm_i915_private *dev_priv = dev->dev_private;
984 struct drm_i915_gem_set_domain *args = data;
985 struct drm_gem_object *obj;
986 struct drm_i915_gem_object *obj_priv;
987 uint32_t read_domains = args->read_domains;
988 uint32_t write_domain = args->write_domain;
991 if (!(dev->driver->driver_features & DRIVER_GEM))
994 /* Only handle setting domains to types used by the CPU. */
995 if (write_domain & I915_GEM_GPU_DOMAINS)
998 if (read_domains & I915_GEM_GPU_DOMAINS)
1001 /* Having something in the write domain implies it's in the read
1002 * domain, and only that read domain. Enforce that in the request.
1004 if (write_domain != 0 && read_domains != write_domain)
1007 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1010 obj_priv = obj->driver_private;
1012 mutex_lock(&dev->struct_mutex);
1014 intel_mark_busy(dev, obj);
1017 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1018 obj, obj->size, read_domains, write_domain);
1020 if (read_domains & I915_GEM_DOMAIN_GTT) {
1021 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1023 /* Update the LRU on the fence for the CPU access that's
1026 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1027 list_move_tail(&obj_priv->fence_list,
1028 &dev_priv->mm.fence_list);
1031 /* Silently promote "you're not bound, there was nothing to do"
1032 * to success, since the client was just asking us to
1033 * make sure everything was done.
1038 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1041 drm_gem_object_unreference(obj);
1042 mutex_unlock(&dev->struct_mutex);
1047 * Called when user space has done writes to this buffer
1050 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1051 struct drm_file *file_priv)
1053 struct drm_i915_gem_sw_finish *args = data;
1054 struct drm_gem_object *obj;
1055 struct drm_i915_gem_object *obj_priv;
1058 if (!(dev->driver->driver_features & DRIVER_GEM))
1061 mutex_lock(&dev->struct_mutex);
1062 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1064 mutex_unlock(&dev->struct_mutex);
1069 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1070 __func__, args->handle, obj, obj->size);
1072 obj_priv = obj->driver_private;
1074 /* Pinned buffers may be scanout, so flush the cache */
1075 if (obj_priv->pin_count)
1076 i915_gem_object_flush_cpu_write_domain(obj);
1078 drm_gem_object_unreference(obj);
1079 mutex_unlock(&dev->struct_mutex);
1084 * Maps the contents of an object, returning the address it is mapped
1087 * While the mapping holds a reference on the contents of the object, it doesn't
1088 * imply a ref on the object itself.
1091 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1092 struct drm_file *file_priv)
1094 struct drm_i915_gem_mmap *args = data;
1095 struct drm_gem_object *obj;
1099 if (!(dev->driver->driver_features & DRIVER_GEM))
1102 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1106 offset = args->offset;
1108 down_write(¤t->mm->mmap_sem);
1109 addr = do_mmap(obj->filp, 0, args->size,
1110 PROT_READ | PROT_WRITE, MAP_SHARED,
1112 up_write(¤t->mm->mmap_sem);
1113 mutex_lock(&dev->struct_mutex);
1114 drm_gem_object_unreference(obj);
1115 mutex_unlock(&dev->struct_mutex);
1116 if (IS_ERR((void *)addr))
1119 args->addr_ptr = (uint64_t) addr;
1125 * i915_gem_fault - fault a page into the GTT
1126 * vma: VMA in question
1129 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1130 * from userspace. The fault handler takes care of binding the object to
1131 * the GTT (if needed), allocating and programming a fence register (again,
1132 * only if needed based on whether the old reg is still valid or the object
1133 * is tiled) and inserting a new PTE into the faulting process.
1135 * Note that the faulting process may involve evicting existing objects
1136 * from the GTT and/or fence registers to make room. So performance may
1137 * suffer if the GTT working set is large or there are few fence registers
1140 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1142 struct drm_gem_object *obj = vma->vm_private_data;
1143 struct drm_device *dev = obj->dev;
1144 struct drm_i915_private *dev_priv = dev->dev_private;
1145 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1146 pgoff_t page_offset;
1149 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1151 /* We don't use vmf->pgoff since that has the fake offset */
1152 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1155 /* Now bind it into the GTT if needed */
1156 mutex_lock(&dev->struct_mutex);
1157 if (!obj_priv->gtt_space) {
1158 ret = i915_gem_object_bind_to_gtt(obj, 0);
1160 mutex_unlock(&dev->struct_mutex);
1161 return VM_FAULT_SIGBUS;
1163 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1165 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1167 mutex_unlock(&dev->struct_mutex);
1168 return VM_FAULT_SIGBUS;
1172 /* Need a new fence register? */
1173 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1174 ret = i915_gem_object_get_fence_reg(obj);
1176 mutex_unlock(&dev->struct_mutex);
1177 return VM_FAULT_SIGBUS;
1181 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1184 /* Finally, remap it using the new GTT offset */
1185 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1187 mutex_unlock(&dev->struct_mutex);
1192 return VM_FAULT_OOM;
1195 return VM_FAULT_SIGBUS;
1197 return VM_FAULT_NOPAGE;
1202 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1203 * @obj: obj in question
1205 * GEM memory mapping works by handing back to userspace a fake mmap offset
1206 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1207 * up the object based on the offset and sets up the various memory mapping
1210 * This routine allocates and attaches a fake offset for @obj.
1213 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1215 struct drm_device *dev = obj->dev;
1216 struct drm_gem_mm *mm = dev->mm_private;
1217 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1218 struct drm_map_list *list;
1219 struct drm_local_map *map;
1222 /* Set the object up for mmap'ing */
1223 list = &obj->map_list;
1224 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1229 map->type = _DRM_GEM;
1230 map->size = obj->size;
1233 /* Get a DRM GEM mmap offset allocated... */
1234 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1235 obj->size / PAGE_SIZE, 0, 0);
1236 if (!list->file_offset_node) {
1237 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1242 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1243 obj->size / PAGE_SIZE, 0);
1244 if (!list->file_offset_node) {
1249 list->hash.key = list->file_offset_node->start;
1250 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1251 DRM_ERROR("failed to add to map hash\n");
1255 /* By now we should be all set, any drm_mmap request on the offset
1256 * below will get to our mmap & fault handler */
1257 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1262 drm_mm_put_block(list->file_offset_node);
1270 * i915_gem_release_mmap - remove physical page mappings
1271 * @obj: obj in question
1273 * Preserve the reservation of the mmaping with the DRM core code, but
1274 * relinquish ownership of the pages back to the system.
1276 * It is vital that we remove the page mapping if we have mapped a tiled
1277 * object through the GTT and then lose the fence register due to
1278 * resource pressure. Similarly if the object has been moved out of the
1279 * aperture, than pages mapped into userspace must be revoked. Removing the
1280 * mapping will then trigger a page fault on the next user access, allowing
1281 * fixup by i915_gem_fault().
1284 i915_gem_release_mmap(struct drm_gem_object *obj)
1286 struct drm_device *dev = obj->dev;
1287 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1289 if (dev->dev_mapping)
1290 unmap_mapping_range(dev->dev_mapping,
1291 obj_priv->mmap_offset, obj->size, 1);
1295 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1297 struct drm_device *dev = obj->dev;
1298 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1299 struct drm_gem_mm *mm = dev->mm_private;
1300 struct drm_map_list *list;
1302 list = &obj->map_list;
1303 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1305 if (list->file_offset_node) {
1306 drm_mm_put_block(list->file_offset_node);
1307 list->file_offset_node = NULL;
1315 obj_priv->mmap_offset = 0;
1319 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1320 * @obj: object to check
1322 * Return the required GTT alignment for an object, taking into account
1323 * potential fence register mapping if needed.
1326 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1328 struct drm_device *dev = obj->dev;
1329 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1333 * Minimum alignment is 4k (GTT page size), but might be greater
1334 * if a fence register is needed for the object.
1336 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1340 * Previous chips need to be aligned to the size of the smallest
1341 * fence register that can contain the object.
1348 for (i = start; i < obj->size; i <<= 1)
1355 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1357 * @data: GTT mapping ioctl data
1358 * @file_priv: GEM object info
1360 * Simply returns the fake offset to userspace so it can mmap it.
1361 * The mmap call will end up in drm_gem_mmap(), which will set things
1362 * up so we can get faults in the handler above.
1364 * The fault handler will take care of binding the object into the GTT
1365 * (since it may have been evicted to make room for something), allocating
1366 * a fence register, and mapping the appropriate aperture address into
1370 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1371 struct drm_file *file_priv)
1373 struct drm_i915_gem_mmap_gtt *args = data;
1374 struct drm_i915_private *dev_priv = dev->dev_private;
1375 struct drm_gem_object *obj;
1376 struct drm_i915_gem_object *obj_priv;
1379 if (!(dev->driver->driver_features & DRIVER_GEM))
1382 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1386 mutex_lock(&dev->struct_mutex);
1388 obj_priv = obj->driver_private;
1390 if (!obj_priv->mmap_offset) {
1391 ret = i915_gem_create_mmap_offset(obj);
1393 drm_gem_object_unreference(obj);
1394 mutex_unlock(&dev->struct_mutex);
1399 args->offset = obj_priv->mmap_offset;
1402 * Pull it into the GTT so that we have a page list (makes the
1403 * initial fault faster and any subsequent flushing possible).
1405 if (!obj_priv->agp_mem) {
1406 ret = i915_gem_object_bind_to_gtt(obj, 0);
1408 drm_gem_object_unreference(obj);
1409 mutex_unlock(&dev->struct_mutex);
1412 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1415 drm_gem_object_unreference(obj);
1416 mutex_unlock(&dev->struct_mutex);
1422 i915_gem_object_put_pages(struct drm_gem_object *obj)
1424 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1425 int page_count = obj->size / PAGE_SIZE;
1428 BUG_ON(obj_priv->pages_refcount == 0);
1430 if (--obj_priv->pages_refcount != 0)
1433 if (obj_priv->tiling_mode != I915_TILING_NONE)
1434 i915_gem_object_save_bit_17_swizzle(obj);
1436 for (i = 0; i < page_count; i++)
1437 if (obj_priv->pages[i] != NULL) {
1438 if (obj_priv->dirty)
1439 set_page_dirty(obj_priv->pages[i]);
1440 mark_page_accessed(obj_priv->pages[i]);
1441 page_cache_release(obj_priv->pages[i]);
1443 obj_priv->dirty = 0;
1445 drm_free_large(obj_priv->pages);
1446 obj_priv->pages = NULL;
1450 i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
1452 struct drm_device *dev = obj->dev;
1453 drm_i915_private_t *dev_priv = dev->dev_private;
1454 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1456 /* Add a reference if we're newly entering the active list. */
1457 if (!obj_priv->active) {
1458 drm_gem_object_reference(obj);
1459 obj_priv->active = 1;
1461 /* Move from whatever list we were on to the tail of execution. */
1462 spin_lock(&dev_priv->mm.active_list_lock);
1463 list_move_tail(&obj_priv->list,
1464 &dev_priv->mm.active_list);
1465 spin_unlock(&dev_priv->mm.active_list_lock);
1466 obj_priv->last_rendering_seqno = seqno;
1470 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1472 struct drm_device *dev = obj->dev;
1473 drm_i915_private_t *dev_priv = dev->dev_private;
1474 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1476 BUG_ON(!obj_priv->active);
1477 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1478 obj_priv->last_rendering_seqno = 0;
1482 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1484 struct drm_device *dev = obj->dev;
1485 drm_i915_private_t *dev_priv = dev->dev_private;
1486 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1488 i915_verify_inactive(dev, __FILE__, __LINE__);
1489 if (obj_priv->pin_count != 0)
1490 list_del_init(&obj_priv->list);
1492 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1494 obj_priv->last_rendering_seqno = 0;
1495 if (obj_priv->active) {
1496 obj_priv->active = 0;
1497 drm_gem_object_unreference(obj);
1499 i915_verify_inactive(dev, __FILE__, __LINE__);
1503 * Creates a new sequence number, emitting a write of it to the status page
1504 * plus an interrupt, which will trigger i915_user_interrupt_handler.
1506 * Must be called with struct_lock held.
1508 * Returned sequence numbers are nonzero on success.
1511 i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1512 uint32_t flush_domains)
1514 drm_i915_private_t *dev_priv = dev->dev_private;
1515 struct drm_i915_file_private *i915_file_priv = NULL;
1516 struct drm_i915_gem_request *request;
1521 if (file_priv != NULL)
1522 i915_file_priv = file_priv->driver_priv;
1524 request = kzalloc(sizeof(*request), GFP_KERNEL);
1525 if (request == NULL)
1528 /* Grab the seqno we're going to make this request be, and bump the
1529 * next (skipping 0 so it can be the reserved no-seqno value).
1531 seqno = dev_priv->mm.next_gem_seqno;
1532 dev_priv->mm.next_gem_seqno++;
1533 if (dev_priv->mm.next_gem_seqno == 0)
1534 dev_priv->mm.next_gem_seqno++;
1537 OUT_RING(MI_STORE_DWORD_INDEX);
1538 OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1541 OUT_RING(MI_USER_INTERRUPT);
1544 DRM_DEBUG("%d\n", seqno);
1546 request->seqno = seqno;
1547 request->emitted_jiffies = jiffies;
1548 was_empty = list_empty(&dev_priv->mm.request_list);
1549 list_add_tail(&request->list, &dev_priv->mm.request_list);
1550 if (i915_file_priv) {
1551 list_add_tail(&request->client_list,
1552 &i915_file_priv->mm.request_list);
1554 INIT_LIST_HEAD(&request->client_list);
1557 /* Associate any objects on the flushing list matching the write
1558 * domain we're flushing with our flush.
1560 if (flush_domains != 0) {
1561 struct drm_i915_gem_object *obj_priv, *next;
1563 list_for_each_entry_safe(obj_priv, next,
1564 &dev_priv->mm.flushing_list, list) {
1565 struct drm_gem_object *obj = obj_priv->obj;
1567 if ((obj->write_domain & flush_domains) ==
1568 obj->write_domain) {
1569 obj->write_domain = 0;
1570 i915_gem_object_move_to_active(obj, seqno);
1576 if (!dev_priv->mm.suspended) {
1577 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1579 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1585 * Command execution barrier
1587 * Ensures that all commands in the ring are finished
1588 * before signalling the CPU
1591 i915_retire_commands(struct drm_device *dev)
1593 drm_i915_private_t *dev_priv = dev->dev_private;
1594 uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1595 uint32_t flush_domains = 0;
1598 /* The sampler always gets flushed on i965 (sigh) */
1600 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1603 OUT_RING(0); /* noop */
1605 return flush_domains;
1609 * Moves buffers associated only with the given active seqno from the active
1610 * to inactive list, potentially freeing them.
1613 i915_gem_retire_request(struct drm_device *dev,
1614 struct drm_i915_gem_request *request)
1616 drm_i915_private_t *dev_priv = dev->dev_private;
1618 /* Move any buffers on the active list that are no longer referenced
1619 * by the ringbuffer to the flushing/inactive lists as appropriate.
1621 spin_lock(&dev_priv->mm.active_list_lock);
1622 while (!list_empty(&dev_priv->mm.active_list)) {
1623 struct drm_gem_object *obj;
1624 struct drm_i915_gem_object *obj_priv;
1626 obj_priv = list_first_entry(&dev_priv->mm.active_list,
1627 struct drm_i915_gem_object,
1629 obj = obj_priv->obj;
1631 /* If the seqno being retired doesn't match the oldest in the
1632 * list, then the oldest in the list must still be newer than
1635 if (obj_priv->last_rendering_seqno != request->seqno)
1639 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1640 __func__, request->seqno, obj);
1643 if (obj->write_domain != 0)
1644 i915_gem_object_move_to_flushing(obj);
1646 /* Take a reference on the object so it won't be
1647 * freed while the spinlock is held. The list
1648 * protection for this spinlock is safe when breaking
1649 * the lock like this since the next thing we do
1650 * is just get the head of the list again.
1652 drm_gem_object_reference(obj);
1653 i915_gem_object_move_to_inactive(obj);
1654 spin_unlock(&dev_priv->mm.active_list_lock);
1655 drm_gem_object_unreference(obj);
1656 spin_lock(&dev_priv->mm.active_list_lock);
1660 spin_unlock(&dev_priv->mm.active_list_lock);
1664 * Returns true if seq1 is later than seq2.
1667 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1669 return (int32_t)(seq1 - seq2) >= 0;
1673 i915_get_gem_seqno(struct drm_device *dev)
1675 drm_i915_private_t *dev_priv = dev->dev_private;
1677 return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
1681 * This function clears the request list as sequence numbers are passed.
1684 i915_gem_retire_requests(struct drm_device *dev)
1686 drm_i915_private_t *dev_priv = dev->dev_private;
1689 if (!dev_priv->hw_status_page)
1692 seqno = i915_get_gem_seqno(dev);
1694 while (!list_empty(&dev_priv->mm.request_list)) {
1695 struct drm_i915_gem_request *request;
1696 uint32_t retiring_seqno;
1698 request = list_first_entry(&dev_priv->mm.request_list,
1699 struct drm_i915_gem_request,
1701 retiring_seqno = request->seqno;
1703 if (i915_seqno_passed(seqno, retiring_seqno) ||
1704 atomic_read(&dev_priv->mm.wedged)) {
1705 i915_gem_retire_request(dev, request);
1707 list_del(&request->list);
1708 list_del(&request->client_list);
1716 i915_gem_retire_work_handler(struct work_struct *work)
1718 drm_i915_private_t *dev_priv;
1719 struct drm_device *dev;
1721 dev_priv = container_of(work, drm_i915_private_t,
1722 mm.retire_work.work);
1723 dev = dev_priv->dev;
1725 mutex_lock(&dev->struct_mutex);
1726 i915_gem_retire_requests(dev);
1727 if (!dev_priv->mm.suspended &&
1728 !list_empty(&dev_priv->mm.request_list))
1729 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1730 mutex_unlock(&dev->struct_mutex);
1734 * Waits for a sequence number to be signaled, and cleans up the
1735 * request and object lists appropriately for that event.
1738 i915_wait_request(struct drm_device *dev, uint32_t seqno)
1740 drm_i915_private_t *dev_priv = dev->dev_private;
1746 if (atomic_read(&dev_priv->mm.wedged))
1749 if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
1751 ier = I915_READ(DEIER) | I915_READ(GTIER);
1753 ier = I915_READ(IER);
1755 DRM_ERROR("something (likely vbetool) disabled "
1756 "interrupts, re-enabling\n");
1757 i915_driver_irq_preinstall(dev);
1758 i915_driver_irq_postinstall(dev);
1761 dev_priv->mm.waiting_gem_seqno = seqno;
1762 i915_user_irq_get(dev);
1763 ret = wait_event_interruptible(dev_priv->irq_queue,
1764 i915_seqno_passed(i915_get_gem_seqno(dev),
1766 atomic_read(&dev_priv->mm.wedged));
1767 i915_user_irq_put(dev);
1768 dev_priv->mm.waiting_gem_seqno = 0;
1770 if (atomic_read(&dev_priv->mm.wedged))
1773 if (ret && ret != -ERESTARTSYS)
1774 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1775 __func__, ret, seqno, i915_get_gem_seqno(dev));
1777 /* Directly dispatch request retiring. While we have the work queue
1778 * to handle this, the waiter on a request often wants an associated
1779 * buffer to have made it to the inactive list, and we would need
1780 * a separate wait queue to handle that.
1783 i915_gem_retire_requests(dev);
1789 i915_gem_flush(struct drm_device *dev,
1790 uint32_t invalidate_domains,
1791 uint32_t flush_domains)
1793 drm_i915_private_t *dev_priv = dev->dev_private;
1798 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
1799 invalidate_domains, flush_domains);
1802 if (flush_domains & I915_GEM_DOMAIN_CPU)
1803 drm_agp_chipset_flush(dev);
1805 if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
1807 * read/write caches:
1809 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1810 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
1811 * also flushed at 2d versus 3d pipeline switches.
1815 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1816 * MI_READ_FLUSH is set, and is always flushed on 965.
1818 * I915_GEM_DOMAIN_COMMAND may not exist?
1820 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1821 * invalidated when MI_EXE_FLUSH is set.
1823 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1824 * invalidated with every MI_FLUSH.
1828 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1829 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1830 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1831 * are flushed at any MI_FLUSH.
1834 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1835 if ((invalidate_domains|flush_domains) &
1836 I915_GEM_DOMAIN_RENDER)
1837 cmd &= ~MI_NO_WRITE_FLUSH;
1838 if (!IS_I965G(dev)) {
1840 * On the 965, the sampler cache always gets flushed
1841 * and this bit is reserved.
1843 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
1844 cmd |= MI_READ_FLUSH;
1846 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
1847 cmd |= MI_EXE_FLUSH;
1850 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
1854 OUT_RING(0); /* noop */
1860 * Ensures that all rendering to the object has completed and the object is
1861 * safe to unbind from the GTT or access from the CPU.
1864 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1866 struct drm_device *dev = obj->dev;
1867 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1870 /* This function only exists to support waiting for existing rendering,
1871 * not for emitting required flushes.
1873 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
1875 /* If there is rendering queued on the buffer being evicted, wait for
1878 if (obj_priv->active) {
1880 DRM_INFO("%s: object %p wait for seqno %08x\n",
1881 __func__, obj, obj_priv->last_rendering_seqno);
1883 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
1892 * Unbinds an object from the GTT aperture.
1895 i915_gem_object_unbind(struct drm_gem_object *obj)
1897 struct drm_device *dev = obj->dev;
1898 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1902 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1903 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1905 if (obj_priv->gtt_space == NULL)
1908 if (obj_priv->pin_count != 0) {
1909 DRM_ERROR("Attempting to unbind pinned buffer\n");
1913 /* blow away mappings if mapped through GTT */
1914 i915_gem_release_mmap(obj);
1916 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
1917 i915_gem_clear_fence_reg(obj);
1919 /* Move the object to the CPU domain to ensure that
1920 * any possible CPU writes while it's not in the GTT
1921 * are flushed when we go to remap it. This will
1922 * also ensure that all pending GPU writes are finished
1925 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1927 if (ret != -ERESTARTSYS)
1928 DRM_ERROR("set_domain failed: %d\n", ret);
1932 BUG_ON(obj_priv->active);
1934 if (obj_priv->agp_mem != NULL) {
1935 drm_unbind_agp(obj_priv->agp_mem);
1936 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
1937 obj_priv->agp_mem = NULL;
1940 i915_gem_object_put_pages(obj);
1942 if (obj_priv->gtt_space) {
1943 atomic_dec(&dev->gtt_count);
1944 atomic_sub(obj->size, &dev->gtt_memory);
1946 drm_mm_put_block(obj_priv->gtt_space);
1947 obj_priv->gtt_space = NULL;
1950 /* Remove ourselves from the LRU list if present. */
1951 if (!list_empty(&obj_priv->list))
1952 list_del_init(&obj_priv->list);
1958 i915_gem_evict_something(struct drm_device *dev)
1960 drm_i915_private_t *dev_priv = dev->dev_private;
1961 struct drm_gem_object *obj;
1962 struct drm_i915_gem_object *obj_priv;
1966 /* If there's an inactive buffer available now, grab it
1969 if (!list_empty(&dev_priv->mm.inactive_list)) {
1970 obj_priv = list_first_entry(&dev_priv->mm.inactive_list,
1971 struct drm_i915_gem_object,
1973 obj = obj_priv->obj;
1974 BUG_ON(obj_priv->pin_count != 0);
1976 DRM_INFO("%s: evicting %p\n", __func__, obj);
1978 BUG_ON(obj_priv->active);
1980 /* Wait on the rendering and unbind the buffer. */
1981 ret = i915_gem_object_unbind(obj);
1985 /* If we didn't get anything, but the ring is still processing
1986 * things, wait for one of those things to finish and hopefully
1987 * leave us a buffer to evict.
1989 if (!list_empty(&dev_priv->mm.request_list)) {
1990 struct drm_i915_gem_request *request;
1992 request = list_first_entry(&dev_priv->mm.request_list,
1993 struct drm_i915_gem_request,
1996 ret = i915_wait_request(dev, request->seqno);
2000 /* if waiting caused an object to become inactive,
2001 * then loop around and wait for it. Otherwise, we
2002 * assume that waiting freed and unbound something,
2003 * so there should now be some space in the GTT
2005 if (!list_empty(&dev_priv->mm.inactive_list))
2010 /* If we didn't have anything on the request list but there
2011 * are buffers awaiting a flush, emit one and try again.
2012 * When we wait on it, those buffers waiting for that flush
2013 * will get moved to inactive.
2015 if (!list_empty(&dev_priv->mm.flushing_list)) {
2016 obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
2017 struct drm_i915_gem_object,
2019 obj = obj_priv->obj;
2024 i915_add_request(dev, NULL, obj->write_domain);
2030 DRM_ERROR("inactive empty %d request empty %d "
2031 "flushing empty %d\n",
2032 list_empty(&dev_priv->mm.inactive_list),
2033 list_empty(&dev_priv->mm.request_list),
2034 list_empty(&dev_priv->mm.flushing_list));
2035 /* If we didn't do any of the above, there's nothing to be done
2036 * and we just can't fit it in.
2044 i915_gem_evict_everything(struct drm_device *dev)
2049 ret = i915_gem_evict_something(dev);
2059 i915_gem_object_get_pages(struct drm_gem_object *obj)
2061 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2063 struct address_space *mapping;
2064 struct inode *inode;
2068 if (obj_priv->pages_refcount++ != 0)
2071 /* Get the list of pages out of our struct file. They'll be pinned
2072 * at this point until we release them.
2074 page_count = obj->size / PAGE_SIZE;
2075 BUG_ON(obj_priv->pages != NULL);
2076 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
2077 if (obj_priv->pages == NULL) {
2078 DRM_ERROR("Faled to allocate page list\n");
2079 obj_priv->pages_refcount--;
2083 inode = obj->filp->f_path.dentry->d_inode;
2084 mapping = inode->i_mapping;
2085 for (i = 0; i < page_count; i++) {
2086 page = read_mapping_page(mapping, i, NULL);
2088 ret = PTR_ERR(page);
2089 DRM_ERROR("read_mapping_page failed: %d\n", ret);
2090 i915_gem_object_put_pages(obj);
2093 obj_priv->pages[i] = page;
2096 if (obj_priv->tiling_mode != I915_TILING_NONE)
2097 i915_gem_object_do_bit_17_swizzle(obj);
2102 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2104 struct drm_gem_object *obj = reg->obj;
2105 struct drm_device *dev = obj->dev;
2106 drm_i915_private_t *dev_priv = dev->dev_private;
2107 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2108 int regnum = obj_priv->fence_reg;
2111 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2113 val |= obj_priv->gtt_offset & 0xfffff000;
2114 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2115 if (obj_priv->tiling_mode == I915_TILING_Y)
2116 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2117 val |= I965_FENCE_REG_VALID;
2119 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2122 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2124 struct drm_gem_object *obj = reg->obj;
2125 struct drm_device *dev = obj->dev;
2126 drm_i915_private_t *dev_priv = dev->dev_private;
2127 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2128 int regnum = obj_priv->fence_reg;
2130 uint32_t fence_reg, val;
2133 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2134 (obj_priv->gtt_offset & (obj->size - 1))) {
2135 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2136 __func__, obj_priv->gtt_offset, obj->size);
2140 if (obj_priv->tiling_mode == I915_TILING_Y &&
2141 HAS_128_BYTE_Y_TILING(dev))
2146 /* Note: pitch better be a power of two tile widths */
2147 pitch_val = obj_priv->stride / tile_width;
2148 pitch_val = ffs(pitch_val) - 1;
2150 val = obj_priv->gtt_offset;
2151 if (obj_priv->tiling_mode == I915_TILING_Y)
2152 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2153 val |= I915_FENCE_SIZE_BITS(obj->size);
2154 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2155 val |= I830_FENCE_REG_VALID;
2158 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2160 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2161 I915_WRITE(fence_reg, val);
2164 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2166 struct drm_gem_object *obj = reg->obj;
2167 struct drm_device *dev = obj->dev;
2168 drm_i915_private_t *dev_priv = dev->dev_private;
2169 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2170 int regnum = obj_priv->fence_reg;
2173 uint32_t fence_size_bits;
2175 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
2176 (obj_priv->gtt_offset & (obj->size - 1))) {
2177 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2178 __func__, obj_priv->gtt_offset);
2182 pitch_val = obj_priv->stride / 128;
2183 pitch_val = ffs(pitch_val) - 1;
2184 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2186 val = obj_priv->gtt_offset;
2187 if (obj_priv->tiling_mode == I915_TILING_Y)
2188 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2189 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2190 WARN_ON(fence_size_bits & ~0x00000f00);
2191 val |= fence_size_bits;
2192 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2193 val |= I830_FENCE_REG_VALID;
2195 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
2199 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2200 * @obj: object to map through a fence reg
2202 * When mapping objects through the GTT, userspace wants to be able to write
2203 * to them without having to worry about swizzling if the object is tiled.
2205 * This function walks the fence regs looking for a free one for @obj,
2206 * stealing one if it can't find any.
2208 * It then sets up the reg based on the object's properties: address, pitch
2209 * and tiling format.
2212 i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
2214 struct drm_device *dev = obj->dev;
2215 struct drm_i915_private *dev_priv = dev->dev_private;
2216 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2217 struct drm_i915_fence_reg *reg = NULL;
2218 struct drm_i915_gem_object *old_obj_priv = NULL;
2221 /* Just update our place in the LRU if our fence is getting used. */
2222 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2223 list_move_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2227 switch (obj_priv->tiling_mode) {
2228 case I915_TILING_NONE:
2229 WARN(1, "allocating a fence for non-tiled object?\n");
2232 if (!obj_priv->stride)
2234 WARN((obj_priv->stride & (512 - 1)),
2235 "object 0x%08x is X tiled but has non-512B pitch\n",
2236 obj_priv->gtt_offset);
2239 if (!obj_priv->stride)
2241 WARN((obj_priv->stride & (128 - 1)),
2242 "object 0x%08x is Y tiled but has non-128B pitch\n",
2243 obj_priv->gtt_offset);
2247 /* First try to find a free reg */
2249 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2250 reg = &dev_priv->fence_regs[i];
2254 old_obj_priv = reg->obj->driver_private;
2255 if (!old_obj_priv->pin_count)
2259 /* None available, try to steal one or wait for a user to finish */
2260 if (i == dev_priv->num_fence_regs) {
2261 struct drm_gem_object *old_obj = NULL;
2266 list_for_each_entry(old_obj_priv, &dev_priv->mm.fence_list,
2268 old_obj = old_obj_priv->obj;
2270 if (old_obj_priv->pin_count)
2273 /* Take a reference, as otherwise the wait_rendering
2274 * below may cause the object to get freed out from
2277 drm_gem_object_reference(old_obj);
2279 /* i915 uses fences for GPU access to tiled buffers */
2280 if (IS_I965G(dev) || !old_obj_priv->active)
2283 /* This brings the object to the head of the LRU if it
2284 * had been written to. The only way this should
2285 * result in us waiting longer than the expected
2286 * optimal amount of time is if there was a
2287 * fence-using buffer later that was read-only.
2289 i915_gem_object_flush_gpu_write_domain(old_obj);
2290 ret = i915_gem_object_wait_rendering(old_obj);
2292 drm_gem_object_unreference(old_obj);
2300 * Zap this virtual mapping so we can set up a fence again
2301 * for this object next time we need it.
2303 i915_gem_release_mmap(old_obj);
2305 i = old_obj_priv->fence_reg;
2306 reg = &dev_priv->fence_regs[i];
2308 old_obj_priv->fence_reg = I915_FENCE_REG_NONE;
2309 list_del_init(&old_obj_priv->fence_list);
2311 drm_gem_object_unreference(old_obj);
2314 obj_priv->fence_reg = i;
2315 list_add_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2320 i965_write_fence_reg(reg);
2321 else if (IS_I9XX(dev))
2322 i915_write_fence_reg(reg);
2324 i830_write_fence_reg(reg);
2330 * i915_gem_clear_fence_reg - clear out fence register info
2331 * @obj: object to clear
2333 * Zeroes out the fence register itself and clears out the associated
2334 * data structures in dev_priv and obj_priv.
2337 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2339 struct drm_device *dev = obj->dev;
2340 drm_i915_private_t *dev_priv = dev->dev_private;
2341 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2344 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
2348 if (obj_priv->fence_reg < 8)
2349 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2351 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2354 I915_WRITE(fence_reg, 0);
2357 dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL;
2358 obj_priv->fence_reg = I915_FENCE_REG_NONE;
2359 list_del_init(&obj_priv->fence_list);
2363 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2364 * to the buffer to finish, and then resets the fence register.
2365 * @obj: tiled object holding a fence register.
2367 * Zeroes out the fence register itself and clears out the associated
2368 * data structures in dev_priv and obj_priv.
2371 i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2373 struct drm_device *dev = obj->dev;
2374 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2376 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2379 /* On the i915, GPU access to tiled buffers is via a fence,
2380 * therefore we must wait for any outstanding access to complete
2381 * before clearing the fence.
2383 if (!IS_I965G(dev)) {
2386 i915_gem_object_flush_gpu_write_domain(obj);
2387 i915_gem_object_flush_gtt_write_domain(obj);
2388 ret = i915_gem_object_wait_rendering(obj);
2393 i915_gem_clear_fence_reg (obj);
2399 * Finds free space in the GTT aperture and binds the object there.
2402 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2404 struct drm_device *dev = obj->dev;
2405 drm_i915_private_t *dev_priv = dev->dev_private;
2406 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2407 struct drm_mm_node *free_space;
2408 int page_count, ret;
2410 if (dev_priv->mm.suspended)
2413 alignment = i915_gem_get_gtt_alignment(obj);
2414 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
2415 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2420 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2421 obj->size, alignment, 0);
2422 if (free_space != NULL) {
2423 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2425 if (obj_priv->gtt_space != NULL) {
2426 obj_priv->gtt_space->private = obj;
2427 obj_priv->gtt_offset = obj_priv->gtt_space->start;
2430 if (obj_priv->gtt_space == NULL) {
2433 /* If the gtt is empty and we're still having trouble
2434 * fitting our object in, we're out of memory.
2437 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2439 spin_lock(&dev_priv->mm.active_list_lock);
2440 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2441 list_empty(&dev_priv->mm.flushing_list) &&
2442 list_empty(&dev_priv->mm.active_list));
2443 spin_unlock(&dev_priv->mm.active_list_lock);
2445 DRM_ERROR("GTT full, but LRU list empty\n");
2449 ret = i915_gem_evict_something(dev);
2451 if (ret != -ERESTARTSYS)
2452 DRM_ERROR("Failed to evict a buffer %d\n", ret);
2459 DRM_INFO("Binding object of size %zd at 0x%08x\n",
2460 obj->size, obj_priv->gtt_offset);
2462 ret = i915_gem_object_get_pages(obj);
2464 drm_mm_put_block(obj_priv->gtt_space);
2465 obj_priv->gtt_space = NULL;
2469 page_count = obj->size / PAGE_SIZE;
2470 /* Create an AGP memory structure pointing at our pages, and bind it
2473 obj_priv->agp_mem = drm_agp_bind_pages(dev,
2476 obj_priv->gtt_offset,
2477 obj_priv->agp_type);
2478 if (obj_priv->agp_mem == NULL) {
2479 i915_gem_object_put_pages(obj);
2480 drm_mm_put_block(obj_priv->gtt_space);
2481 obj_priv->gtt_space = NULL;
2484 atomic_inc(&dev->gtt_count);
2485 atomic_add(obj->size, &dev->gtt_memory);
2487 /* Assert that the object is not currently in any GPU domain. As it
2488 * wasn't in the GTT, there shouldn't be any way it could have been in
2491 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2492 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
2498 i915_gem_clflush_object(struct drm_gem_object *obj)
2500 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2502 /* If we don't have a page list set up, then we're not pinned
2503 * to GPU, and we can ignore the cache flush because it'll happen
2504 * again at bind time.
2506 if (obj_priv->pages == NULL)
2509 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2512 /** Flushes any GPU write domain for the object if it's dirty. */
2514 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2516 struct drm_device *dev = obj->dev;
2519 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2522 /* Queue the GPU write cache flushing we need. */
2523 i915_gem_flush(dev, 0, obj->write_domain);
2524 seqno = i915_add_request(dev, NULL, obj->write_domain);
2525 obj->write_domain = 0;
2526 i915_gem_object_move_to_active(obj, seqno);
2529 /** Flushes the GTT write domain for the object if it's dirty. */
2531 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2533 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2536 /* No actual flushing is required for the GTT write domain. Writes
2537 * to it immediately go to main memory as far as we know, so there's
2538 * no chipset flush. It also doesn't land in render cache.
2540 obj->write_domain = 0;
2543 /** Flushes the CPU write domain for the object if it's dirty. */
2545 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2547 struct drm_device *dev = obj->dev;
2549 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2552 i915_gem_clflush_object(obj);
2553 drm_agp_chipset_flush(dev);
2554 obj->write_domain = 0;
2558 * Moves a single object to the GTT read, and possibly write domain.
2560 * This function returns when the move is complete, including waiting on
2564 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2566 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2569 /* Not valid to be called on unbound objects. */
2570 if (obj_priv->gtt_space == NULL)
2573 i915_gem_object_flush_gpu_write_domain(obj);
2574 /* Wait on any GPU rendering and flushing to occur. */
2575 ret = i915_gem_object_wait_rendering(obj);
2579 /* If we're writing through the GTT domain, then CPU and GPU caches
2580 * will need to be invalidated at next use.
2583 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2585 i915_gem_object_flush_cpu_write_domain(obj);
2587 /* It should now be out of any other write domains, and we can update
2588 * the domain values for our changes.
2590 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2591 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2593 obj->write_domain = I915_GEM_DOMAIN_GTT;
2594 obj_priv->dirty = 1;
2601 * Moves a single object to the CPU read, and possibly write domain.
2603 * This function returns when the move is complete, including waiting on
2607 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2611 i915_gem_object_flush_gpu_write_domain(obj);
2612 /* Wait on any GPU rendering and flushing to occur. */
2613 ret = i915_gem_object_wait_rendering(obj);
2617 i915_gem_object_flush_gtt_write_domain(obj);
2619 /* If we have a partially-valid cache of the object in the CPU,
2620 * finish invalidating it and free the per-page flags.
2622 i915_gem_object_set_to_full_cpu_read_domain(obj);
2624 /* Flush the CPU cache if it's still invalid. */
2625 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2626 i915_gem_clflush_object(obj);
2628 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2631 /* It should now be out of any other write domains, and we can update
2632 * the domain values for our changes.
2634 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2636 /* If we're writing through the CPU, then the GPU read domains will
2637 * need to be invalidated at next use.
2640 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2641 obj->write_domain = I915_GEM_DOMAIN_CPU;
2648 * Set the next domain for the specified object. This
2649 * may not actually perform the necessary flushing/invaliding though,
2650 * as that may want to be batched with other set_domain operations
2652 * This is (we hope) the only really tricky part of gem. The goal
2653 * is fairly simple -- track which caches hold bits of the object
2654 * and make sure they remain coherent. A few concrete examples may
2655 * help to explain how it works. For shorthand, we use the notation
2656 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2657 * a pair of read and write domain masks.
2659 * Case 1: the batch buffer
2665 * 5. Unmapped from GTT
2668 * Let's take these a step at a time
2671 * Pages allocated from the kernel may still have
2672 * cache contents, so we set them to (CPU, CPU) always.
2673 * 2. Written by CPU (using pwrite)
2674 * The pwrite function calls set_domain (CPU, CPU) and
2675 * this function does nothing (as nothing changes)
2677 * This function asserts that the object is not
2678 * currently in any GPU-based read or write domains
2680 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2681 * As write_domain is zero, this function adds in the
2682 * current read domains (CPU+COMMAND, 0).
2683 * flush_domains is set to CPU.
2684 * invalidate_domains is set to COMMAND
2685 * clflush is run to get data out of the CPU caches
2686 * then i915_dev_set_domain calls i915_gem_flush to
2687 * emit an MI_FLUSH and drm_agp_chipset_flush
2688 * 5. Unmapped from GTT
2689 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2690 * flush_domains and invalidate_domains end up both zero
2691 * so no flushing/invalidating happens
2695 * Case 2: The shared render buffer
2699 * 3. Read/written by GPU
2700 * 4. set_domain to (CPU,CPU)
2701 * 5. Read/written by CPU
2702 * 6. Read/written by GPU
2705 * Same as last example, (CPU, CPU)
2707 * Nothing changes (assertions find that it is not in the GPU)
2708 * 3. Read/written by GPU
2709 * execbuffer calls set_domain (RENDER, RENDER)
2710 * flush_domains gets CPU
2711 * invalidate_domains gets GPU
2713 * MI_FLUSH and drm_agp_chipset_flush
2714 * 4. set_domain (CPU, CPU)
2715 * flush_domains gets GPU
2716 * invalidate_domains gets CPU
2717 * wait_rendering (obj) to make sure all drawing is complete.
2718 * This will include an MI_FLUSH to get the data from GPU
2720 * clflush (obj) to invalidate the CPU cache
2721 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
2722 * 5. Read/written by CPU
2723 * cache lines are loaded and dirtied
2724 * 6. Read written by GPU
2725 * Same as last GPU access
2727 * Case 3: The constant buffer
2732 * 4. Updated (written) by CPU again
2741 * flush_domains = CPU
2742 * invalidate_domains = RENDER
2745 * drm_agp_chipset_flush
2746 * 4. Updated (written) by CPU again
2748 * flush_domains = 0 (no previous write domain)
2749 * invalidate_domains = 0 (no new read domains)
2752 * flush_domains = CPU
2753 * invalidate_domains = RENDER
2756 * drm_agp_chipset_flush
2759 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
2761 struct drm_device *dev = obj->dev;
2762 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2763 uint32_t invalidate_domains = 0;
2764 uint32_t flush_domains = 0;
2766 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
2767 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
2769 intel_mark_busy(dev, obj);
2772 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2774 obj->read_domains, obj->pending_read_domains,
2775 obj->write_domain, obj->pending_write_domain);
2778 * If the object isn't moving to a new write domain,
2779 * let the object stay in multiple read domains
2781 if (obj->pending_write_domain == 0)
2782 obj->pending_read_domains |= obj->read_domains;
2784 obj_priv->dirty = 1;
2787 * Flush the current write domain if
2788 * the new read domains don't match. Invalidate
2789 * any read domains which differ from the old
2792 if (obj->write_domain &&
2793 obj->write_domain != obj->pending_read_domains) {
2794 flush_domains |= obj->write_domain;
2795 invalidate_domains |=
2796 obj->pending_read_domains & ~obj->write_domain;
2799 * Invalidate any read caches which may have
2800 * stale data. That is, any new read domains.
2802 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
2803 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
2805 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
2806 __func__, flush_domains, invalidate_domains);
2808 i915_gem_clflush_object(obj);
2811 /* The actual obj->write_domain will be updated with
2812 * pending_write_domain after we emit the accumulated flush for all
2813 * of our domain changes in execbuffers (which clears objects'
2814 * write_domains). So if we have a current write domain that we
2815 * aren't changing, set pending_write_domain to that.
2817 if (flush_domains == 0 && obj->pending_write_domain == 0)
2818 obj->pending_write_domain = obj->write_domain;
2819 obj->read_domains = obj->pending_read_domains;
2821 dev->invalidate_domains |= invalidate_domains;
2822 dev->flush_domains |= flush_domains;
2824 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
2826 obj->read_domains, obj->write_domain,
2827 dev->invalidate_domains, dev->flush_domains);
2832 * Moves the object from a partially CPU read to a full one.
2834 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
2835 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
2838 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
2840 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2842 if (!obj_priv->page_cpu_valid)
2845 /* If we're partially in the CPU read domain, finish moving it in.
2847 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
2850 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
2851 if (obj_priv->page_cpu_valid[i])
2853 drm_clflush_pages(obj_priv->pages + i, 1);
2857 /* Free the page_cpu_valid mappings which are now stale, whether
2858 * or not we've got I915_GEM_DOMAIN_CPU.
2860 kfree(obj_priv->page_cpu_valid);
2861 obj_priv->page_cpu_valid = NULL;
2865 * Set the CPU read domain on a range of the object.
2867 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
2868 * not entirely valid. The page_cpu_valid member of the object flags which
2869 * pages have been flushed, and will be respected by
2870 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
2871 * of the whole object.
2873 * This function returns when the move is complete, including waiting on
2877 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
2878 uint64_t offset, uint64_t size)
2880 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2883 if (offset == 0 && size == obj->size)
2884 return i915_gem_object_set_to_cpu_domain(obj, 0);
2886 i915_gem_object_flush_gpu_write_domain(obj);
2887 /* Wait on any GPU rendering and flushing to occur. */
2888 ret = i915_gem_object_wait_rendering(obj);
2891 i915_gem_object_flush_gtt_write_domain(obj);
2893 /* If we're already fully in the CPU read domain, we're done. */
2894 if (obj_priv->page_cpu_valid == NULL &&
2895 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
2898 /* Otherwise, create/clear the per-page CPU read domain flag if we're
2899 * newly adding I915_GEM_DOMAIN_CPU
2901 if (obj_priv->page_cpu_valid == NULL) {
2902 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
2904 if (obj_priv->page_cpu_valid == NULL)
2906 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
2907 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
2909 /* Flush the cache on any pages that are still invalid from the CPU's
2912 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
2914 if (obj_priv->page_cpu_valid[i])
2917 drm_clflush_pages(obj_priv->pages + i, 1);
2919 obj_priv->page_cpu_valid[i] = 1;
2922 /* It should now be out of any other write domains, and we can update
2923 * the domain values for our changes.
2925 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2927 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2933 * Pin an object to the GTT and evaluate the relocations landing in it.
2936 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
2937 struct drm_file *file_priv,
2938 struct drm_i915_gem_exec_object *entry,
2939 struct drm_i915_gem_relocation_entry *relocs)
2941 struct drm_device *dev = obj->dev;
2942 drm_i915_private_t *dev_priv = dev->dev_private;
2943 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2945 void __iomem *reloc_page;
2947 /* Choose the GTT offset for our buffer and put it there. */
2948 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
2952 entry->offset = obj_priv->gtt_offset;
2954 /* Apply the relocations, using the GTT aperture to avoid cache
2955 * flushing requirements.
2957 for (i = 0; i < entry->relocation_count; i++) {
2958 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
2959 struct drm_gem_object *target_obj;
2960 struct drm_i915_gem_object *target_obj_priv;
2961 uint32_t reloc_val, reloc_offset;
2962 uint32_t __iomem *reloc_entry;
2964 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
2965 reloc->target_handle);
2966 if (target_obj == NULL) {
2967 i915_gem_object_unpin(obj);
2970 target_obj_priv = target_obj->driver_private;
2972 /* The target buffer should have appeared before us in the
2973 * exec_object list, so it should have a GTT space bound by now.
2975 if (target_obj_priv->gtt_space == NULL) {
2976 DRM_ERROR("No GTT space found for object %d\n",
2977 reloc->target_handle);
2978 drm_gem_object_unreference(target_obj);
2979 i915_gem_object_unpin(obj);
2983 if (reloc->offset > obj->size - 4) {
2984 DRM_ERROR("Relocation beyond object bounds: "
2985 "obj %p target %d offset %d size %d.\n",
2986 obj, reloc->target_handle,
2987 (int) reloc->offset, (int) obj->size);
2988 drm_gem_object_unreference(target_obj);
2989 i915_gem_object_unpin(obj);
2992 if (reloc->offset & 3) {
2993 DRM_ERROR("Relocation not 4-byte aligned: "
2994 "obj %p target %d offset %d.\n",
2995 obj, reloc->target_handle,
2996 (int) reloc->offset);
2997 drm_gem_object_unreference(target_obj);
2998 i915_gem_object_unpin(obj);
3002 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3003 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
3004 DRM_ERROR("reloc with read/write CPU domains: "
3005 "obj %p target %d offset %d "
3006 "read %08x write %08x",
3007 obj, reloc->target_handle,
3008 (int) reloc->offset,
3009 reloc->read_domains,
3010 reloc->write_domain);
3011 drm_gem_object_unreference(target_obj);
3012 i915_gem_object_unpin(obj);
3016 if (reloc->write_domain && target_obj->pending_write_domain &&
3017 reloc->write_domain != target_obj->pending_write_domain) {
3018 DRM_ERROR("Write domain conflict: "
3019 "obj %p target %d offset %d "
3020 "new %08x old %08x\n",
3021 obj, reloc->target_handle,
3022 (int) reloc->offset,
3023 reloc->write_domain,
3024 target_obj->pending_write_domain);
3025 drm_gem_object_unreference(target_obj);
3026 i915_gem_object_unpin(obj);
3031 DRM_INFO("%s: obj %p offset %08x target %d "
3032 "read %08x write %08x gtt %08x "
3033 "presumed %08x delta %08x\n",
3036 (int) reloc->offset,
3037 (int) reloc->target_handle,
3038 (int) reloc->read_domains,
3039 (int) reloc->write_domain,
3040 (int) target_obj_priv->gtt_offset,
3041 (int) reloc->presumed_offset,
3045 target_obj->pending_read_domains |= reloc->read_domains;
3046 target_obj->pending_write_domain |= reloc->write_domain;
3048 /* If the relocation already has the right value in it, no
3049 * more work needs to be done.
3051 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
3052 drm_gem_object_unreference(target_obj);
3056 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3058 drm_gem_object_unreference(target_obj);
3059 i915_gem_object_unpin(obj);
3063 /* Map the page containing the relocation we're going to
3066 reloc_offset = obj_priv->gtt_offset + reloc->offset;
3067 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3070 reloc_entry = (uint32_t __iomem *)(reloc_page +
3071 (reloc_offset & (PAGE_SIZE - 1)));
3072 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
3075 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3076 obj, (unsigned int) reloc->offset,
3077 readl(reloc_entry), reloc_val);
3079 writel(reloc_val, reloc_entry);
3080 io_mapping_unmap_atomic(reloc_page);
3082 /* The updated presumed offset for this entry will be
3083 * copied back out to the user.
3085 reloc->presumed_offset = target_obj_priv->gtt_offset;
3087 drm_gem_object_unreference(target_obj);
3092 i915_gem_dump_object(obj, 128, __func__, ~0);
3097 /** Dispatch a batchbuffer to the ring
3100 i915_dispatch_gem_execbuffer(struct drm_device *dev,
3101 struct drm_i915_gem_execbuffer *exec,
3102 struct drm_clip_rect *cliprects,
3103 uint64_t exec_offset)
3105 drm_i915_private_t *dev_priv = dev->dev_private;
3106 int nbox = exec->num_cliprects;
3108 uint32_t exec_start, exec_len;
3111 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3112 exec_len = (uint32_t) exec->batch_len;
3114 count = nbox ? nbox : 1;
3116 for (i = 0; i < count; i++) {
3118 int ret = i915_emit_box(dev, cliprects, i,
3119 exec->DR1, exec->DR4);
3124 if (IS_I830(dev) || IS_845G(dev)) {
3126 OUT_RING(MI_BATCH_BUFFER);
3127 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3128 OUT_RING(exec_start + exec_len - 4);
3133 if (IS_I965G(dev)) {
3134 OUT_RING(MI_BATCH_BUFFER_START |
3136 MI_BATCH_NON_SECURE_I965);
3137 OUT_RING(exec_start);
3139 OUT_RING(MI_BATCH_BUFFER_START |
3141 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3147 /* XXX breadcrumb */
3151 /* Throttle our rendering by waiting until the ring has completed our requests
3152 * emitted over 20 msec ago.
3154 * Note that if we were to use the current jiffies each time around the loop,
3155 * we wouldn't escape the function with any frames outstanding if the time to
3156 * render a frame was over 20ms.
3158 * This should get us reasonable parallelism between CPU and GPU but also
3159 * relatively low latency when blocking on a particular request to finish.
3162 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3164 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3166 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3168 mutex_lock(&dev->struct_mutex);
3169 while (!list_empty(&i915_file_priv->mm.request_list)) {
3170 struct drm_i915_gem_request *request;
3172 request = list_first_entry(&i915_file_priv->mm.request_list,
3173 struct drm_i915_gem_request,
3176 if (time_after_eq(request->emitted_jiffies, recent_enough))
3179 ret = i915_wait_request(dev, request->seqno);
3183 mutex_unlock(&dev->struct_mutex);
3189 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object *exec_list,
3190 uint32_t buffer_count,
3191 struct drm_i915_gem_relocation_entry **relocs)
3193 uint32_t reloc_count = 0, reloc_index = 0, i;
3197 for (i = 0; i < buffer_count; i++) {
3198 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3200 reloc_count += exec_list[i].relocation_count;
3203 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
3204 if (*relocs == NULL)
3207 for (i = 0; i < buffer_count; i++) {
3208 struct drm_i915_gem_relocation_entry __user *user_relocs;
3210 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3212 ret = copy_from_user(&(*relocs)[reloc_index],
3214 exec_list[i].relocation_count *
3217 drm_free_large(*relocs);
3222 reloc_index += exec_list[i].relocation_count;
3229 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object *exec_list,
3230 uint32_t buffer_count,
3231 struct drm_i915_gem_relocation_entry *relocs)
3233 uint32_t reloc_count = 0, i;
3236 for (i = 0; i < buffer_count; i++) {
3237 struct drm_i915_gem_relocation_entry __user *user_relocs;
3240 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3242 unwritten = copy_to_user(user_relocs,
3243 &relocs[reloc_count],
3244 exec_list[i].relocation_count *
3252 reloc_count += exec_list[i].relocation_count;
3256 drm_free_large(relocs);
3262 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer *exec,
3263 uint64_t exec_offset)
3265 uint32_t exec_start, exec_len;
3267 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3268 exec_len = (uint32_t) exec->batch_len;
3270 if ((exec_start | exec_len) & 0x7)
3280 i915_gem_execbuffer(struct drm_device *dev, void *data,
3281 struct drm_file *file_priv)
3283 drm_i915_private_t *dev_priv = dev->dev_private;
3284 struct drm_i915_gem_execbuffer *args = data;
3285 struct drm_i915_gem_exec_object *exec_list = NULL;
3286 struct drm_gem_object **object_list = NULL;
3287 struct drm_gem_object *batch_obj;
3288 struct drm_i915_gem_object *obj_priv;
3289 struct drm_clip_rect *cliprects = NULL;
3290 struct drm_i915_gem_relocation_entry *relocs;
3291 int ret, ret2, i, pinned = 0;
3292 uint64_t exec_offset;
3293 uint32_t seqno, flush_domains, reloc_index;
3297 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3298 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3301 if (args->buffer_count < 1) {
3302 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3305 /* Copy in the exec list from userland */
3306 exec_list = drm_calloc_large(sizeof(*exec_list), args->buffer_count);
3307 object_list = drm_calloc_large(sizeof(*object_list), args->buffer_count);
3308 if (exec_list == NULL || object_list == NULL) {
3309 DRM_ERROR("Failed to allocate exec or object list "
3311 args->buffer_count);
3315 ret = copy_from_user(exec_list,
3316 (struct drm_i915_relocation_entry __user *)
3317 (uintptr_t) args->buffers_ptr,
3318 sizeof(*exec_list) * args->buffer_count);
3320 DRM_ERROR("copy %d exec entries failed %d\n",
3321 args->buffer_count, ret);
3325 if (args->num_cliprects != 0) {
3326 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3328 if (cliprects == NULL)
3331 ret = copy_from_user(cliprects,
3332 (struct drm_clip_rect __user *)
3333 (uintptr_t) args->cliprects_ptr,
3334 sizeof(*cliprects) * args->num_cliprects);
3336 DRM_ERROR("copy %d cliprects failed: %d\n",
3337 args->num_cliprects, ret);
3342 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3347 mutex_lock(&dev->struct_mutex);
3349 i915_verify_inactive(dev, __FILE__, __LINE__);
3351 if (atomic_read(&dev_priv->mm.wedged)) {
3352 DRM_ERROR("Execbuf while wedged\n");
3353 mutex_unlock(&dev->struct_mutex);
3358 if (dev_priv->mm.suspended) {
3359 DRM_ERROR("Execbuf while VT-switched.\n");
3360 mutex_unlock(&dev->struct_mutex);
3365 /* Look up object handles */
3366 for (i = 0; i < args->buffer_count; i++) {
3367 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3368 exec_list[i].handle);
3369 if (object_list[i] == NULL) {
3370 DRM_ERROR("Invalid object handle %d at index %d\n",
3371 exec_list[i].handle, i);
3376 obj_priv = object_list[i]->driver_private;
3377 if (obj_priv->in_execbuffer) {
3378 DRM_ERROR("Object %p appears more than once in object list\n",
3383 obj_priv->in_execbuffer = true;
3386 /* Pin and relocate */
3387 for (pin_tries = 0; ; pin_tries++) {
3391 for (i = 0; i < args->buffer_count; i++) {
3392 object_list[i]->pending_read_domains = 0;
3393 object_list[i]->pending_write_domain = 0;
3394 ret = i915_gem_object_pin_and_relocate(object_list[i],
3397 &relocs[reloc_index]);
3401 reloc_index += exec_list[i].relocation_count;
3407 /* error other than GTT full, or we've already tried again */
3408 if (ret != -ENOSPC || pin_tries >= 1) {
3409 if (ret != -ERESTARTSYS)
3410 DRM_ERROR("Failed to pin buffers %d\n", ret);
3414 /* unpin all of our buffers */
3415 for (i = 0; i < pinned; i++)
3416 i915_gem_object_unpin(object_list[i]);
3419 /* evict everyone we can from the aperture */
3420 ret = i915_gem_evict_everything(dev);
3425 /* Set the pending read domains for the batch buffer to COMMAND */
3426 batch_obj = object_list[args->buffer_count-1];
3427 if (batch_obj->pending_write_domain) {
3428 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3432 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
3434 /* Sanity check the batch buffer, prior to moving objects */
3435 exec_offset = exec_list[args->buffer_count - 1].offset;
3436 ret = i915_gem_check_execbuffer (args, exec_offset);
3438 DRM_ERROR("execbuf with invalid offset/length\n");
3442 i915_verify_inactive(dev, __FILE__, __LINE__);
3444 /* Zero the global flush/invalidate flags. These
3445 * will be modified as new domains are computed
3448 dev->invalidate_domains = 0;
3449 dev->flush_domains = 0;
3451 for (i = 0; i < args->buffer_count; i++) {
3452 struct drm_gem_object *obj = object_list[i];
3454 /* Compute new gpu domains and update invalidate/flush */
3455 i915_gem_object_set_to_gpu_domain(obj);
3458 i915_verify_inactive(dev, __FILE__, __LINE__);
3460 if (dev->invalidate_domains | dev->flush_domains) {
3462 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3464 dev->invalidate_domains,
3465 dev->flush_domains);
3468 dev->invalidate_domains,
3469 dev->flush_domains);
3470 if (dev->flush_domains)
3471 (void)i915_add_request(dev, file_priv,
3472 dev->flush_domains);
3475 for (i = 0; i < args->buffer_count; i++) {
3476 struct drm_gem_object *obj = object_list[i];
3478 obj->write_domain = obj->pending_write_domain;
3481 i915_verify_inactive(dev, __FILE__, __LINE__);
3484 for (i = 0; i < args->buffer_count; i++) {
3485 i915_gem_object_check_coherency(object_list[i],
3486 exec_list[i].handle);
3491 i915_gem_dump_object(batch_obj,
3497 /* Exec the batchbuffer */
3498 ret = i915_dispatch_gem_execbuffer(dev, args, cliprects, exec_offset);
3500 DRM_ERROR("dispatch failed %d\n", ret);
3505 * Ensure that the commands in the batch buffer are
3506 * finished before the interrupt fires
3508 flush_domains = i915_retire_commands(dev);
3510 i915_verify_inactive(dev, __FILE__, __LINE__);
3513 * Get a seqno representing the execution of the current buffer,
3514 * which we can wait on. We would like to mitigate these interrupts,
3515 * likely by only creating seqnos occasionally (so that we have
3516 * *some* interrupts representing completion of buffers that we can
3517 * wait on when trying to clear up gtt space).
3519 seqno = i915_add_request(dev, file_priv, flush_domains);
3521 for (i = 0; i < args->buffer_count; i++) {
3522 struct drm_gem_object *obj = object_list[i];
3524 i915_gem_object_move_to_active(obj, seqno);
3526 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3530 i915_dump_lru(dev, __func__);
3533 i915_verify_inactive(dev, __FILE__, __LINE__);
3536 for (i = 0; i < pinned; i++)
3537 i915_gem_object_unpin(object_list[i]);
3539 for (i = 0; i < args->buffer_count; i++) {
3540 if (object_list[i]) {
3541 obj_priv = object_list[i]->driver_private;
3542 obj_priv->in_execbuffer = false;
3544 drm_gem_object_unreference(object_list[i]);
3547 mutex_unlock(&dev->struct_mutex);
3550 /* Copy the new buffer offsets back to the user's exec list. */
3551 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
3552 (uintptr_t) args->buffers_ptr,
3554 sizeof(*exec_list) * args->buffer_count);
3557 DRM_ERROR("failed to copy %d exec entries "
3558 "back to user (%d)\n",
3559 args->buffer_count, ret);
3563 /* Copy the updated relocations out regardless of current error
3564 * state. Failure to update the relocs would mean that the next
3565 * time userland calls execbuf, it would do so with presumed offset
3566 * state that didn't match the actual object state.
3568 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
3571 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
3578 drm_free_large(object_list);
3579 drm_free_large(exec_list);
3586 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
3588 struct drm_device *dev = obj->dev;
3589 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3592 i915_verify_inactive(dev, __FILE__, __LINE__);
3593 if (obj_priv->gtt_space == NULL) {
3594 ret = i915_gem_object_bind_to_gtt(obj, alignment);
3596 if (ret != -EBUSY && ret != -ERESTARTSYS)
3597 DRM_ERROR("Failure to bind: %d\n", ret);
3602 * Pre-965 chips need a fence register set up in order to
3603 * properly handle tiled surfaces.
3605 if (!IS_I965G(dev) && obj_priv->tiling_mode != I915_TILING_NONE) {
3606 ret = i915_gem_object_get_fence_reg(obj);
3608 if (ret != -EBUSY && ret != -ERESTARTSYS)
3609 DRM_ERROR("Failure to install fence: %d\n",
3614 obj_priv->pin_count++;
3616 /* If the object is not active and not pending a flush,
3617 * remove it from the inactive list
3619 if (obj_priv->pin_count == 1) {
3620 atomic_inc(&dev->pin_count);
3621 atomic_add(obj->size, &dev->pin_memory);
3622 if (!obj_priv->active &&
3623 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 &&
3624 !list_empty(&obj_priv->list))
3625 list_del_init(&obj_priv->list);
3627 i915_verify_inactive(dev, __FILE__, __LINE__);
3633 i915_gem_object_unpin(struct drm_gem_object *obj)
3635 struct drm_device *dev = obj->dev;
3636 drm_i915_private_t *dev_priv = dev->dev_private;
3637 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3639 i915_verify_inactive(dev, __FILE__, __LINE__);
3640 obj_priv->pin_count--;
3641 BUG_ON(obj_priv->pin_count < 0);
3642 BUG_ON(obj_priv->gtt_space == NULL);
3644 /* If the object is no longer pinned, and is
3645 * neither active nor being flushed, then stick it on
3648 if (obj_priv->pin_count == 0) {
3649 if (!obj_priv->active &&
3650 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
3651 list_move_tail(&obj_priv->list,
3652 &dev_priv->mm.inactive_list);
3653 atomic_dec(&dev->pin_count);
3654 atomic_sub(obj->size, &dev->pin_memory);
3656 i915_verify_inactive(dev, __FILE__, __LINE__);
3660 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3661 struct drm_file *file_priv)
3663 struct drm_i915_gem_pin *args = data;
3664 struct drm_gem_object *obj;
3665 struct drm_i915_gem_object *obj_priv;
3668 mutex_lock(&dev->struct_mutex);
3670 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
3672 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
3674 mutex_unlock(&dev->struct_mutex);
3677 obj_priv = obj->driver_private;
3679 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
3680 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3682 drm_gem_object_unreference(obj);
3683 mutex_unlock(&dev->struct_mutex);
3687 obj_priv->user_pin_count++;
3688 obj_priv->pin_filp = file_priv;
3689 if (obj_priv->user_pin_count == 1) {
3690 ret = i915_gem_object_pin(obj, args->alignment);
3692 drm_gem_object_unreference(obj);
3693 mutex_unlock(&dev->struct_mutex);
3698 /* XXX - flush the CPU caches for pinned objects
3699 * as the X server doesn't manage domains yet
3701 i915_gem_object_flush_cpu_write_domain(obj);
3702 args->offset = obj_priv->gtt_offset;
3703 drm_gem_object_unreference(obj);
3704 mutex_unlock(&dev->struct_mutex);
3710 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3711 struct drm_file *file_priv)
3713 struct drm_i915_gem_pin *args = data;
3714 struct drm_gem_object *obj;
3715 struct drm_i915_gem_object *obj_priv;
3717 mutex_lock(&dev->struct_mutex);
3719 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
3721 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
3723 mutex_unlock(&dev->struct_mutex);
3727 obj_priv = obj->driver_private;
3728 if (obj_priv->pin_filp != file_priv) {
3729 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3731 drm_gem_object_unreference(obj);
3732 mutex_unlock(&dev->struct_mutex);
3735 obj_priv->user_pin_count--;
3736 if (obj_priv->user_pin_count == 0) {
3737 obj_priv->pin_filp = NULL;
3738 i915_gem_object_unpin(obj);
3741 drm_gem_object_unreference(obj);
3742 mutex_unlock(&dev->struct_mutex);
3747 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3748 struct drm_file *file_priv)
3750 struct drm_i915_gem_busy *args = data;
3751 struct drm_gem_object *obj;
3752 struct drm_i915_gem_object *obj_priv;
3754 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
3756 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
3761 mutex_lock(&dev->struct_mutex);
3762 /* Update the active list for the hardware's current position.
3763 * Otherwise this only updates on a delayed timer or when irqs are
3764 * actually unmasked, and our working set ends up being larger than
3767 i915_gem_retire_requests(dev);
3769 obj_priv = obj->driver_private;
3770 /* Don't count being on the flushing list against the object being
3771 * done. Otherwise, a buffer left on the flushing list but not getting
3772 * flushed (because nobody's flushing that domain) won't ever return
3773 * unbusy and get reused by libdrm's bo cache. The other expected
3774 * consumer of this interface, OpenGL's occlusion queries, also specs
3775 * that the objects get unbusy "eventually" without any interference.
3777 args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
3779 drm_gem_object_unreference(obj);
3780 mutex_unlock(&dev->struct_mutex);
3785 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3786 struct drm_file *file_priv)
3788 return i915_gem_ring_throttle(dev, file_priv);
3791 int i915_gem_init_object(struct drm_gem_object *obj)
3793 struct drm_i915_gem_object *obj_priv;
3795 obj_priv = kzalloc(sizeof(*obj_priv), GFP_KERNEL);
3796 if (obj_priv == NULL)
3800 * We've just allocated pages from the kernel,
3801 * so they've just been written by the CPU with
3802 * zeros. They'll need to be clflushed before we
3803 * use them with the GPU.
3805 obj->write_domain = I915_GEM_DOMAIN_CPU;
3806 obj->read_domains = I915_GEM_DOMAIN_CPU;
3808 obj_priv->agp_type = AGP_USER_MEMORY;
3810 obj->driver_private = obj_priv;
3811 obj_priv->obj = obj;
3812 obj_priv->fence_reg = I915_FENCE_REG_NONE;
3813 INIT_LIST_HEAD(&obj_priv->list);
3814 INIT_LIST_HEAD(&obj_priv->fence_list);
3819 void i915_gem_free_object(struct drm_gem_object *obj)
3821 struct drm_device *dev = obj->dev;
3822 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3824 while (obj_priv->pin_count > 0)
3825 i915_gem_object_unpin(obj);
3827 if (obj_priv->phys_obj)
3828 i915_gem_detach_phys_object(dev, obj);
3830 i915_gem_object_unbind(obj);
3832 if (obj_priv->mmap_offset)
3833 i915_gem_free_mmap_offset(obj);
3835 kfree(obj_priv->page_cpu_valid);
3836 kfree(obj_priv->bit_17);
3837 kfree(obj->driver_private);
3840 /** Unbinds all objects that are on the given buffer list. */
3842 i915_gem_evict_from_list(struct drm_device *dev, struct list_head *head)
3844 struct drm_gem_object *obj;
3845 struct drm_i915_gem_object *obj_priv;
3848 while (!list_empty(head)) {
3849 obj_priv = list_first_entry(head,
3850 struct drm_i915_gem_object,
3852 obj = obj_priv->obj;
3854 if (obj_priv->pin_count != 0) {
3855 DRM_ERROR("Pinned object in unbind list\n");
3856 mutex_unlock(&dev->struct_mutex);
3860 ret = i915_gem_object_unbind(obj);
3862 DRM_ERROR("Error unbinding object in LeaveVT: %d\n",
3864 mutex_unlock(&dev->struct_mutex);
3874 i915_gem_idle(struct drm_device *dev)
3876 drm_i915_private_t *dev_priv = dev->dev_private;
3877 uint32_t seqno, cur_seqno, last_seqno;
3880 mutex_lock(&dev->struct_mutex);
3882 if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
3883 mutex_unlock(&dev->struct_mutex);
3887 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3888 * We need to replace this with a semaphore, or something.
3890 dev_priv->mm.suspended = 1;
3891 del_timer(&dev_priv->hangcheck_timer);
3893 /* Cancel the retire work handler, wait for it to finish if running
3895 mutex_unlock(&dev->struct_mutex);
3896 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3897 mutex_lock(&dev->struct_mutex);
3899 i915_kernel_lost_context(dev);
3901 /* Flush the GPU along with all non-CPU write domains
3903 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
3904 seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
3907 mutex_unlock(&dev->struct_mutex);
3911 dev_priv->mm.waiting_gem_seqno = seqno;
3915 cur_seqno = i915_get_gem_seqno(dev);
3916 if (i915_seqno_passed(cur_seqno, seqno))
3918 if (last_seqno == cur_seqno) {
3919 if (stuck++ > 100) {
3920 DRM_ERROR("hardware wedged\n");
3921 atomic_set(&dev_priv->mm.wedged, 1);
3922 DRM_WAKEUP(&dev_priv->irq_queue);
3927 last_seqno = cur_seqno;
3929 dev_priv->mm.waiting_gem_seqno = 0;
3931 i915_gem_retire_requests(dev);
3933 spin_lock(&dev_priv->mm.active_list_lock);
3934 if (!atomic_read(&dev_priv->mm.wedged)) {
3935 /* Active and flushing should now be empty as we've
3936 * waited for a sequence higher than any pending execbuffer
3938 WARN_ON(!list_empty(&dev_priv->mm.active_list));
3939 WARN_ON(!list_empty(&dev_priv->mm.flushing_list));
3940 /* Request should now be empty as we've also waited
3941 * for the last request in the list
3943 WARN_ON(!list_empty(&dev_priv->mm.request_list));
3946 /* Empty the active and flushing lists to inactive. If there's
3947 * anything left at this point, it means that we're wedged and
3948 * nothing good's going to happen by leaving them there. So strip
3949 * the GPU domains and just stuff them onto inactive.
3951 while (!list_empty(&dev_priv->mm.active_list)) {
3952 struct drm_i915_gem_object *obj_priv;
3954 obj_priv = list_first_entry(&dev_priv->mm.active_list,
3955 struct drm_i915_gem_object,
3957 obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
3958 i915_gem_object_move_to_inactive(obj_priv->obj);
3960 spin_unlock(&dev_priv->mm.active_list_lock);
3962 while (!list_empty(&dev_priv->mm.flushing_list)) {
3963 struct drm_i915_gem_object *obj_priv;
3965 obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
3966 struct drm_i915_gem_object,
3968 obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
3969 i915_gem_object_move_to_inactive(obj_priv->obj);
3973 /* Move all inactive buffers out of the GTT. */
3974 ret = i915_gem_evict_from_list(dev, &dev_priv->mm.inactive_list);
3975 WARN_ON(!list_empty(&dev_priv->mm.inactive_list));
3977 mutex_unlock(&dev->struct_mutex);
3981 i915_gem_cleanup_ringbuffer(dev);
3982 mutex_unlock(&dev->struct_mutex);
3988 i915_gem_init_hws(struct drm_device *dev)
3990 drm_i915_private_t *dev_priv = dev->dev_private;
3991 struct drm_gem_object *obj;
3992 struct drm_i915_gem_object *obj_priv;
3995 /* If we need a physical address for the status page, it's already
3996 * initialized at driver load time.
3998 if (!I915_NEED_GFX_HWS(dev))
4001 obj = drm_gem_object_alloc(dev, 4096);
4003 DRM_ERROR("Failed to allocate status page\n");
4006 obj_priv = obj->driver_private;
4007 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4009 ret = i915_gem_object_pin(obj, 4096);
4011 drm_gem_object_unreference(obj);
4015 dev_priv->status_gfx_addr = obj_priv->gtt_offset;
4017 dev_priv->hw_status_page = kmap(obj_priv->pages[0]);
4018 if (dev_priv->hw_status_page == NULL) {
4019 DRM_ERROR("Failed to map status page.\n");
4020 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4021 i915_gem_object_unpin(obj);
4022 drm_gem_object_unreference(obj);
4025 dev_priv->hws_obj = obj;
4026 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
4027 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
4028 I915_READ(HWS_PGA); /* posting read */
4029 DRM_DEBUG("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
4035 i915_gem_cleanup_hws(struct drm_device *dev)
4037 drm_i915_private_t *dev_priv = dev->dev_private;
4038 struct drm_gem_object *obj;
4039 struct drm_i915_gem_object *obj_priv;
4041 if (dev_priv->hws_obj == NULL)
4044 obj = dev_priv->hws_obj;
4045 obj_priv = obj->driver_private;
4047 kunmap(obj_priv->pages[0]);
4048 i915_gem_object_unpin(obj);
4049 drm_gem_object_unreference(obj);
4050 dev_priv->hws_obj = NULL;
4052 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4053 dev_priv->hw_status_page = NULL;
4055 /* Write high address into HWS_PGA when disabling. */
4056 I915_WRITE(HWS_PGA, 0x1ffff000);
4060 i915_gem_init_ringbuffer(struct drm_device *dev)
4062 drm_i915_private_t *dev_priv = dev->dev_private;
4063 struct drm_gem_object *obj;
4064 struct drm_i915_gem_object *obj_priv;
4065 drm_i915_ring_buffer_t *ring = &dev_priv->ring;
4069 ret = i915_gem_init_hws(dev);
4073 obj = drm_gem_object_alloc(dev, 128 * 1024);
4075 DRM_ERROR("Failed to allocate ringbuffer\n");
4076 i915_gem_cleanup_hws(dev);
4079 obj_priv = obj->driver_private;
4081 ret = i915_gem_object_pin(obj, 4096);
4083 drm_gem_object_unreference(obj);
4084 i915_gem_cleanup_hws(dev);
4088 /* Set up the kernel mapping for the ring. */
4089 ring->Size = obj->size;
4091 ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
4092 ring->map.size = obj->size;
4094 ring->map.flags = 0;
4097 drm_core_ioremap_wc(&ring->map, dev);
4098 if (ring->map.handle == NULL) {
4099 DRM_ERROR("Failed to map ringbuffer.\n");
4100 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4101 i915_gem_object_unpin(obj);
4102 drm_gem_object_unreference(obj);
4103 i915_gem_cleanup_hws(dev);
4106 ring->ring_obj = obj;
4107 ring->virtual_start = ring->map.handle;
4109 /* Stop the ring if it's running. */
4110 I915_WRITE(PRB0_CTL, 0);
4111 I915_WRITE(PRB0_TAIL, 0);
4112 I915_WRITE(PRB0_HEAD, 0);
4114 /* Initialize the ring. */
4115 I915_WRITE(PRB0_START, obj_priv->gtt_offset);
4116 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4118 /* G45 ring initialization fails to reset head to zero */
4120 DRM_ERROR("Ring head not reset to zero "
4121 "ctl %08x head %08x tail %08x start %08x\n",
4122 I915_READ(PRB0_CTL),
4123 I915_READ(PRB0_HEAD),
4124 I915_READ(PRB0_TAIL),
4125 I915_READ(PRB0_START));
4126 I915_WRITE(PRB0_HEAD, 0);
4128 DRM_ERROR("Ring head forced to zero "
4129 "ctl %08x head %08x tail %08x start %08x\n",
4130 I915_READ(PRB0_CTL),
4131 I915_READ(PRB0_HEAD),
4132 I915_READ(PRB0_TAIL),
4133 I915_READ(PRB0_START));
4136 I915_WRITE(PRB0_CTL,
4137 ((obj->size - 4096) & RING_NR_PAGES) |
4141 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4143 /* If the head is still not zero, the ring is dead */
4145 DRM_ERROR("Ring initialization failed "
4146 "ctl %08x head %08x tail %08x start %08x\n",
4147 I915_READ(PRB0_CTL),
4148 I915_READ(PRB0_HEAD),
4149 I915_READ(PRB0_TAIL),
4150 I915_READ(PRB0_START));
4154 /* Update our cache of the ring state */
4155 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4156 i915_kernel_lost_context(dev);
4158 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4159 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
4160 ring->space = ring->head - (ring->tail + 8);
4161 if (ring->space < 0)
4162 ring->space += ring->Size;
4169 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4171 drm_i915_private_t *dev_priv = dev->dev_private;
4173 if (dev_priv->ring.ring_obj == NULL)
4176 drm_core_ioremapfree(&dev_priv->ring.map, dev);
4178 i915_gem_object_unpin(dev_priv->ring.ring_obj);
4179 drm_gem_object_unreference(dev_priv->ring.ring_obj);
4180 dev_priv->ring.ring_obj = NULL;
4181 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4183 i915_gem_cleanup_hws(dev);
4187 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4188 struct drm_file *file_priv)
4190 drm_i915_private_t *dev_priv = dev->dev_private;
4193 if (drm_core_check_feature(dev, DRIVER_MODESET))
4196 if (atomic_read(&dev_priv->mm.wedged)) {
4197 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4198 atomic_set(&dev_priv->mm.wedged, 0);
4201 mutex_lock(&dev->struct_mutex);
4202 dev_priv->mm.suspended = 0;
4204 ret = i915_gem_init_ringbuffer(dev);
4206 mutex_unlock(&dev->struct_mutex);
4210 spin_lock(&dev_priv->mm.active_list_lock);
4211 BUG_ON(!list_empty(&dev_priv->mm.active_list));
4212 spin_unlock(&dev_priv->mm.active_list_lock);
4214 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4215 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4216 BUG_ON(!list_empty(&dev_priv->mm.request_list));
4217 mutex_unlock(&dev->struct_mutex);
4219 drm_irq_install(dev);
4225 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4226 struct drm_file *file_priv)
4230 if (drm_core_check_feature(dev, DRIVER_MODESET))
4233 ret = i915_gem_idle(dev);
4234 drm_irq_uninstall(dev);
4240 i915_gem_lastclose(struct drm_device *dev)
4244 if (drm_core_check_feature(dev, DRIVER_MODESET))
4247 ret = i915_gem_idle(dev);
4249 DRM_ERROR("failed to idle hardware: %d\n", ret);
4253 i915_gem_load(struct drm_device *dev)
4256 drm_i915_private_t *dev_priv = dev->dev_private;
4258 spin_lock_init(&dev_priv->mm.active_list_lock);
4259 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4260 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4261 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4262 INIT_LIST_HEAD(&dev_priv->mm.request_list);
4263 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4264 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4265 i915_gem_retire_work_handler);
4266 dev_priv->mm.next_gem_seqno = 1;
4268 /* Old X drivers will take 0-2 for front, back, depth buffers */
4269 dev_priv->fence_reg_start = 3;
4271 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4272 dev_priv->num_fence_regs = 16;
4274 dev_priv->num_fence_regs = 8;
4276 /* Initialize fence registers to zero */
4277 if (IS_I965G(dev)) {
4278 for (i = 0; i < 16; i++)
4279 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4281 for (i = 0; i < 8; i++)
4282 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4283 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4284 for (i = 0; i < 8; i++)
4285 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4288 i915_gem_detect_bit_6_swizzle(dev);
4292 * Create a physically contiguous memory object for this object
4293 * e.g. for cursor + overlay regs
4295 int i915_gem_init_phys_object(struct drm_device *dev,
4298 drm_i915_private_t *dev_priv = dev->dev_private;
4299 struct drm_i915_gem_phys_object *phys_obj;
4302 if (dev_priv->mm.phys_objs[id - 1] || !size)
4305 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4311 phys_obj->handle = drm_pci_alloc(dev, size, 0, 0xffffffff);
4312 if (!phys_obj->handle) {
4317 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4320 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4328 void i915_gem_free_phys_object(struct drm_device *dev, int id)
4330 drm_i915_private_t *dev_priv = dev->dev_private;
4331 struct drm_i915_gem_phys_object *phys_obj;
4333 if (!dev_priv->mm.phys_objs[id - 1])
4336 phys_obj = dev_priv->mm.phys_objs[id - 1];
4337 if (phys_obj->cur_obj) {
4338 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4342 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4344 drm_pci_free(dev, phys_obj->handle);
4346 dev_priv->mm.phys_objs[id - 1] = NULL;
4349 void i915_gem_free_all_phys_object(struct drm_device *dev)
4353 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4354 i915_gem_free_phys_object(dev, i);
4357 void i915_gem_detach_phys_object(struct drm_device *dev,
4358 struct drm_gem_object *obj)
4360 struct drm_i915_gem_object *obj_priv;
4365 obj_priv = obj->driver_private;
4366 if (!obj_priv->phys_obj)
4369 ret = i915_gem_object_get_pages(obj);
4373 page_count = obj->size / PAGE_SIZE;
4375 for (i = 0; i < page_count; i++) {
4376 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
4377 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4379 memcpy(dst, src, PAGE_SIZE);
4380 kunmap_atomic(dst, KM_USER0);
4382 drm_clflush_pages(obj_priv->pages, page_count);
4383 drm_agp_chipset_flush(dev);
4385 i915_gem_object_put_pages(obj);
4387 obj_priv->phys_obj->cur_obj = NULL;
4388 obj_priv->phys_obj = NULL;
4392 i915_gem_attach_phys_object(struct drm_device *dev,
4393 struct drm_gem_object *obj, int id)
4395 drm_i915_private_t *dev_priv = dev->dev_private;
4396 struct drm_i915_gem_object *obj_priv;
4401 if (id > I915_MAX_PHYS_OBJECT)
4404 obj_priv = obj->driver_private;
4406 if (obj_priv->phys_obj) {
4407 if (obj_priv->phys_obj->id == id)
4409 i915_gem_detach_phys_object(dev, obj);
4413 /* create a new object */
4414 if (!dev_priv->mm.phys_objs[id - 1]) {
4415 ret = i915_gem_init_phys_object(dev, id,
4418 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
4423 /* bind to the object */
4424 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4425 obj_priv->phys_obj->cur_obj = obj;
4427 ret = i915_gem_object_get_pages(obj);
4429 DRM_ERROR("failed to get page list\n");
4433 page_count = obj->size / PAGE_SIZE;
4435 for (i = 0; i < page_count; i++) {
4436 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
4437 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4439 memcpy(dst, src, PAGE_SIZE);
4440 kunmap_atomic(src, KM_USER0);
4443 i915_gem_object_put_pages(obj);
4451 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4452 struct drm_i915_gem_pwrite *args,
4453 struct drm_file *file_priv)
4455 struct drm_i915_gem_object *obj_priv = obj->driver_private;
4458 char __user *user_data;
4460 user_data = (char __user *) (uintptr_t) args->data_ptr;
4461 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4463 DRM_DEBUG("obj_addr %p, %lld\n", obj_addr, args->size);
4464 ret = copy_from_user(obj_addr, user_data, args->size);
4468 drm_agp_chipset_flush(dev);
4472 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
4474 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
4476 /* Clean up our request list when the client is going away, so that
4477 * later retire_requests won't dereference our soon-to-be-gone
4480 mutex_lock(&dev->struct_mutex);
4481 while (!list_empty(&i915_file_priv->mm.request_list))
4482 list_del_init(i915_file_priv->mm.request_list.next);
4483 mutex_unlock(&dev->struct_mutex);