2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include <linux/swap.h>
33 #include <linux/pci.h>
35 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
37 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
38 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
39 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
40 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
42 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
45 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
46 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
47 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
49 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
50 static int i915_gem_evict_something(struct drm_device *dev);
51 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
52 struct drm_i915_gem_pwrite *args,
53 struct drm_file *file_priv);
55 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
58 drm_i915_private_t *dev_priv = dev->dev_private;
61 (start & (PAGE_SIZE - 1)) != 0 ||
62 (end & (PAGE_SIZE - 1)) != 0) {
66 drm_mm_init(&dev_priv->mm.gtt_space, start,
69 dev->gtt_total = (uint32_t) (end - start);
75 i915_gem_init_ioctl(struct drm_device *dev, void *data,
76 struct drm_file *file_priv)
78 struct drm_i915_gem_init *args = data;
81 mutex_lock(&dev->struct_mutex);
82 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
83 mutex_unlock(&dev->struct_mutex);
89 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
90 struct drm_file *file_priv)
92 struct drm_i915_gem_get_aperture *args = data;
94 if (!(dev->driver->driver_features & DRIVER_GEM))
97 args->aper_size = dev->gtt_total;
98 args->aper_available_size = (args->aper_size -
99 atomic_read(&dev->pin_memory));
106 * Creates a new mm object and returns a handle to it.
109 i915_gem_create_ioctl(struct drm_device *dev, void *data,
110 struct drm_file *file_priv)
112 struct drm_i915_gem_create *args = data;
113 struct drm_gem_object *obj;
116 args->size = roundup(args->size, PAGE_SIZE);
118 /* Allocate the new object */
119 obj = drm_gem_object_alloc(dev, args->size);
123 ret = drm_gem_handle_create(file_priv, obj, &handle);
124 mutex_lock(&dev->struct_mutex);
125 drm_gem_object_handle_unreference(obj);
126 mutex_unlock(&dev->struct_mutex);
131 args->handle = handle;
137 fast_shmem_read(struct page **pages,
138 loff_t page_base, int page_offset,
145 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
148 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
149 kunmap_atomic(vaddr, KM_USER0);
157 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
159 drm_i915_private_t *dev_priv = obj->dev->dev_private;
160 struct drm_i915_gem_object *obj_priv = obj->driver_private;
162 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
163 obj_priv->tiling_mode != I915_TILING_NONE;
167 slow_shmem_copy(struct page *dst_page,
169 struct page *src_page,
173 char *dst_vaddr, *src_vaddr;
175 dst_vaddr = kmap_atomic(dst_page, KM_USER0);
176 if (dst_vaddr == NULL)
179 src_vaddr = kmap_atomic(src_page, KM_USER1);
180 if (src_vaddr == NULL) {
181 kunmap_atomic(dst_vaddr, KM_USER0);
185 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
187 kunmap_atomic(src_vaddr, KM_USER1);
188 kunmap_atomic(dst_vaddr, KM_USER0);
194 slow_shmem_bit17_copy(struct page *gpu_page,
196 struct page *cpu_page,
201 char *gpu_vaddr, *cpu_vaddr;
203 /* Use the unswizzled path if this page isn't affected. */
204 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
206 return slow_shmem_copy(cpu_page, cpu_offset,
207 gpu_page, gpu_offset, length);
209 return slow_shmem_copy(gpu_page, gpu_offset,
210 cpu_page, cpu_offset, length);
213 gpu_vaddr = kmap_atomic(gpu_page, KM_USER0);
214 if (gpu_vaddr == NULL)
217 cpu_vaddr = kmap_atomic(cpu_page, KM_USER1);
218 if (cpu_vaddr == NULL) {
219 kunmap_atomic(gpu_vaddr, KM_USER0);
223 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
224 * XORing with the other bits (A9 for Y, A9 and A10 for X)
227 int cacheline_end = ALIGN(gpu_offset + 1, 64);
228 int this_length = min(cacheline_end - gpu_offset, length);
229 int swizzled_gpu_offset = gpu_offset ^ 64;
232 memcpy(cpu_vaddr + cpu_offset,
233 gpu_vaddr + swizzled_gpu_offset,
236 memcpy(gpu_vaddr + swizzled_gpu_offset,
237 cpu_vaddr + cpu_offset,
240 cpu_offset += this_length;
241 gpu_offset += this_length;
242 length -= this_length;
245 kunmap_atomic(cpu_vaddr, KM_USER1);
246 kunmap_atomic(gpu_vaddr, KM_USER0);
252 * This is the fast shmem pread path, which attempts to copy_from_user directly
253 * from the backing pages of the object to the user's address space. On a
254 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
257 i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
258 struct drm_i915_gem_pread *args,
259 struct drm_file *file_priv)
261 struct drm_i915_gem_object *obj_priv = obj->driver_private;
263 loff_t offset, page_base;
264 char __user *user_data;
265 int page_offset, page_length;
268 user_data = (char __user *) (uintptr_t) args->data_ptr;
271 mutex_lock(&dev->struct_mutex);
273 ret = i915_gem_object_get_pages(obj);
277 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
282 obj_priv = obj->driver_private;
283 offset = args->offset;
286 /* Operation in this page
288 * page_base = page offset within aperture
289 * page_offset = offset within page
290 * page_length = bytes to copy for this page
292 page_base = (offset & ~(PAGE_SIZE-1));
293 page_offset = offset & (PAGE_SIZE-1);
294 page_length = remain;
295 if ((page_offset + remain) > PAGE_SIZE)
296 page_length = PAGE_SIZE - page_offset;
298 ret = fast_shmem_read(obj_priv->pages,
299 page_base, page_offset,
300 user_data, page_length);
304 remain -= page_length;
305 user_data += page_length;
306 offset += page_length;
310 i915_gem_object_put_pages(obj);
312 mutex_unlock(&dev->struct_mutex);
318 * This is the fallback shmem pread path, which allocates temporary storage
319 * in kernel space to copy_to_user into outside of the struct_mutex, so we
320 * can copy out of the object's backing pages while holding the struct mutex
321 * and not take page faults.
324 i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
325 struct drm_i915_gem_pread *args,
326 struct drm_file *file_priv)
328 struct drm_i915_gem_object *obj_priv = obj->driver_private;
329 struct mm_struct *mm = current->mm;
330 struct page **user_pages;
332 loff_t offset, pinned_pages, i;
333 loff_t first_data_page, last_data_page, num_pages;
334 int shmem_page_index, shmem_page_offset;
335 int data_page_index, data_page_offset;
338 uint64_t data_ptr = args->data_ptr;
339 int do_bit17_swizzling;
343 /* Pin the user pages containing the data. We can't fault while
344 * holding the struct mutex, yet we want to hold it while
345 * dereferencing the user data.
347 first_data_page = data_ptr / PAGE_SIZE;
348 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
349 num_pages = last_data_page - first_data_page + 1;
351 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
352 if (user_pages == NULL)
355 down_read(&mm->mmap_sem);
356 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
357 num_pages, 1, 0, user_pages, NULL);
358 up_read(&mm->mmap_sem);
359 if (pinned_pages < num_pages) {
361 goto fail_put_user_pages;
364 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
366 mutex_lock(&dev->struct_mutex);
368 ret = i915_gem_object_get_pages(obj);
372 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
377 obj_priv = obj->driver_private;
378 offset = args->offset;
381 /* Operation in this page
383 * shmem_page_index = page number within shmem file
384 * shmem_page_offset = offset within page in shmem file
385 * data_page_index = page number in get_user_pages return
386 * data_page_offset = offset with data_page_index page.
387 * page_length = bytes to copy for this page
389 shmem_page_index = offset / PAGE_SIZE;
390 shmem_page_offset = offset & ~PAGE_MASK;
391 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
392 data_page_offset = data_ptr & ~PAGE_MASK;
394 page_length = remain;
395 if ((shmem_page_offset + page_length) > PAGE_SIZE)
396 page_length = PAGE_SIZE - shmem_page_offset;
397 if ((data_page_offset + page_length) > PAGE_SIZE)
398 page_length = PAGE_SIZE - data_page_offset;
400 if (do_bit17_swizzling) {
401 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
403 user_pages[data_page_index],
408 ret = slow_shmem_copy(user_pages[data_page_index],
410 obj_priv->pages[shmem_page_index],
417 remain -= page_length;
418 data_ptr += page_length;
419 offset += page_length;
423 i915_gem_object_put_pages(obj);
425 mutex_unlock(&dev->struct_mutex);
427 for (i = 0; i < pinned_pages; i++) {
428 SetPageDirty(user_pages[i]);
429 page_cache_release(user_pages[i]);
431 drm_free_large(user_pages);
437 * Reads data from the object referenced by handle.
439 * On error, the contents of *data are undefined.
442 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
443 struct drm_file *file_priv)
445 struct drm_i915_gem_pread *args = data;
446 struct drm_gem_object *obj;
447 struct drm_i915_gem_object *obj_priv;
450 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
453 obj_priv = obj->driver_private;
455 /* Bounds check source.
457 * XXX: This could use review for overflow issues...
459 if (args->offset > obj->size || args->size > obj->size ||
460 args->offset + args->size > obj->size) {
461 drm_gem_object_unreference(obj);
465 if (i915_gem_object_needs_bit17_swizzle(obj)) {
466 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
468 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
470 ret = i915_gem_shmem_pread_slow(dev, obj, args,
474 drm_gem_object_unreference(obj);
479 /* This is the fast write path which cannot handle
480 * page faults in the source data
484 fast_user_write(struct io_mapping *mapping,
485 loff_t page_base, int page_offset,
486 char __user *user_data,
490 unsigned long unwritten;
492 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
493 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
495 io_mapping_unmap_atomic(vaddr_atomic);
501 /* Here's the write path which can sleep for
506 slow_kernel_write(struct io_mapping *mapping,
507 loff_t gtt_base, int gtt_offset,
508 struct page *user_page, int user_offset,
511 char *src_vaddr, *dst_vaddr;
512 unsigned long unwritten;
514 dst_vaddr = io_mapping_map_atomic_wc(mapping, gtt_base);
515 src_vaddr = kmap_atomic(user_page, KM_USER1);
516 unwritten = __copy_from_user_inatomic_nocache(dst_vaddr + gtt_offset,
517 src_vaddr + user_offset,
519 kunmap_atomic(src_vaddr, KM_USER1);
520 io_mapping_unmap_atomic(dst_vaddr);
527 fast_shmem_write(struct page **pages,
528 loff_t page_base, int page_offset,
533 unsigned long unwritten;
535 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
538 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
539 kunmap_atomic(vaddr, KM_USER0);
547 * This is the fast pwrite path, where we copy the data directly from the
548 * user into the GTT, uncached.
551 i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
552 struct drm_i915_gem_pwrite *args,
553 struct drm_file *file_priv)
555 struct drm_i915_gem_object *obj_priv = obj->driver_private;
556 drm_i915_private_t *dev_priv = dev->dev_private;
558 loff_t offset, page_base;
559 char __user *user_data;
560 int page_offset, page_length;
563 user_data = (char __user *) (uintptr_t) args->data_ptr;
565 if (!access_ok(VERIFY_READ, user_data, remain))
569 mutex_lock(&dev->struct_mutex);
570 ret = i915_gem_object_pin(obj, 0);
572 mutex_unlock(&dev->struct_mutex);
575 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
579 obj_priv = obj->driver_private;
580 offset = obj_priv->gtt_offset + args->offset;
583 /* Operation in this page
585 * page_base = page offset within aperture
586 * page_offset = offset within page
587 * page_length = bytes to copy for this page
589 page_base = (offset & ~(PAGE_SIZE-1));
590 page_offset = offset & (PAGE_SIZE-1);
591 page_length = remain;
592 if ((page_offset + remain) > PAGE_SIZE)
593 page_length = PAGE_SIZE - page_offset;
595 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
596 page_offset, user_data, page_length);
598 /* If we get a fault while copying data, then (presumably) our
599 * source page isn't available. Return the error and we'll
600 * retry in the slow path.
605 remain -= page_length;
606 user_data += page_length;
607 offset += page_length;
611 i915_gem_object_unpin(obj);
612 mutex_unlock(&dev->struct_mutex);
618 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
619 * the memory and maps it using kmap_atomic for copying.
621 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
622 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
625 i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
626 struct drm_i915_gem_pwrite *args,
627 struct drm_file *file_priv)
629 struct drm_i915_gem_object *obj_priv = obj->driver_private;
630 drm_i915_private_t *dev_priv = dev->dev_private;
632 loff_t gtt_page_base, offset;
633 loff_t first_data_page, last_data_page, num_pages;
634 loff_t pinned_pages, i;
635 struct page **user_pages;
636 struct mm_struct *mm = current->mm;
637 int gtt_page_offset, data_page_offset, data_page_index, page_length;
639 uint64_t data_ptr = args->data_ptr;
643 /* Pin the user pages containing the data. We can't fault while
644 * holding the struct mutex, and all of the pwrite implementations
645 * want to hold it while dereferencing the user data.
647 first_data_page = data_ptr / PAGE_SIZE;
648 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
649 num_pages = last_data_page - first_data_page + 1;
651 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
652 if (user_pages == NULL)
655 down_read(&mm->mmap_sem);
656 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
657 num_pages, 0, 0, user_pages, NULL);
658 up_read(&mm->mmap_sem);
659 if (pinned_pages < num_pages) {
661 goto out_unpin_pages;
664 mutex_lock(&dev->struct_mutex);
665 ret = i915_gem_object_pin(obj, 0);
669 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
671 goto out_unpin_object;
673 obj_priv = obj->driver_private;
674 offset = obj_priv->gtt_offset + args->offset;
677 /* Operation in this page
679 * gtt_page_base = page offset within aperture
680 * gtt_page_offset = offset within page in aperture
681 * data_page_index = page number in get_user_pages return
682 * data_page_offset = offset with data_page_index page.
683 * page_length = bytes to copy for this page
685 gtt_page_base = offset & PAGE_MASK;
686 gtt_page_offset = offset & ~PAGE_MASK;
687 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
688 data_page_offset = data_ptr & ~PAGE_MASK;
690 page_length = remain;
691 if ((gtt_page_offset + page_length) > PAGE_SIZE)
692 page_length = PAGE_SIZE - gtt_page_offset;
693 if ((data_page_offset + page_length) > PAGE_SIZE)
694 page_length = PAGE_SIZE - data_page_offset;
696 ret = slow_kernel_write(dev_priv->mm.gtt_mapping,
697 gtt_page_base, gtt_page_offset,
698 user_pages[data_page_index],
702 /* If we get a fault while copying data, then (presumably) our
703 * source page isn't available. Return the error and we'll
704 * retry in the slow path.
707 goto out_unpin_object;
709 remain -= page_length;
710 offset += page_length;
711 data_ptr += page_length;
715 i915_gem_object_unpin(obj);
717 mutex_unlock(&dev->struct_mutex);
719 for (i = 0; i < pinned_pages; i++)
720 page_cache_release(user_pages[i]);
721 drm_free_large(user_pages);
727 * This is the fast shmem pwrite path, which attempts to directly
728 * copy_from_user into the kmapped pages backing the object.
731 i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
732 struct drm_i915_gem_pwrite *args,
733 struct drm_file *file_priv)
735 struct drm_i915_gem_object *obj_priv = obj->driver_private;
737 loff_t offset, page_base;
738 char __user *user_data;
739 int page_offset, page_length;
742 user_data = (char __user *) (uintptr_t) args->data_ptr;
745 mutex_lock(&dev->struct_mutex);
747 ret = i915_gem_object_get_pages(obj);
751 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
755 obj_priv = obj->driver_private;
756 offset = args->offset;
760 /* Operation in this page
762 * page_base = page offset within aperture
763 * page_offset = offset within page
764 * page_length = bytes to copy for this page
766 page_base = (offset & ~(PAGE_SIZE-1));
767 page_offset = offset & (PAGE_SIZE-1);
768 page_length = remain;
769 if ((page_offset + remain) > PAGE_SIZE)
770 page_length = PAGE_SIZE - page_offset;
772 ret = fast_shmem_write(obj_priv->pages,
773 page_base, page_offset,
774 user_data, page_length);
778 remain -= page_length;
779 user_data += page_length;
780 offset += page_length;
784 i915_gem_object_put_pages(obj);
786 mutex_unlock(&dev->struct_mutex);
792 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
793 * the memory and maps it using kmap_atomic for copying.
795 * This avoids taking mmap_sem for faulting on the user's address while the
796 * struct_mutex is held.
799 i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
800 struct drm_i915_gem_pwrite *args,
801 struct drm_file *file_priv)
803 struct drm_i915_gem_object *obj_priv = obj->driver_private;
804 struct mm_struct *mm = current->mm;
805 struct page **user_pages;
807 loff_t offset, pinned_pages, i;
808 loff_t first_data_page, last_data_page, num_pages;
809 int shmem_page_index, shmem_page_offset;
810 int data_page_index, data_page_offset;
813 uint64_t data_ptr = args->data_ptr;
814 int do_bit17_swizzling;
818 /* Pin the user pages containing the data. We can't fault while
819 * holding the struct mutex, and all of the pwrite implementations
820 * want to hold it while dereferencing the user data.
822 first_data_page = data_ptr / PAGE_SIZE;
823 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
824 num_pages = last_data_page - first_data_page + 1;
826 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
827 if (user_pages == NULL)
830 down_read(&mm->mmap_sem);
831 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
832 num_pages, 0, 0, user_pages, NULL);
833 up_read(&mm->mmap_sem);
834 if (pinned_pages < num_pages) {
836 goto fail_put_user_pages;
839 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
841 mutex_lock(&dev->struct_mutex);
843 ret = i915_gem_object_get_pages(obj);
847 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
851 obj_priv = obj->driver_private;
852 offset = args->offset;
856 /* Operation in this page
858 * shmem_page_index = page number within shmem file
859 * shmem_page_offset = offset within page in shmem file
860 * data_page_index = page number in get_user_pages return
861 * data_page_offset = offset with data_page_index page.
862 * page_length = bytes to copy for this page
864 shmem_page_index = offset / PAGE_SIZE;
865 shmem_page_offset = offset & ~PAGE_MASK;
866 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
867 data_page_offset = data_ptr & ~PAGE_MASK;
869 page_length = remain;
870 if ((shmem_page_offset + page_length) > PAGE_SIZE)
871 page_length = PAGE_SIZE - shmem_page_offset;
872 if ((data_page_offset + page_length) > PAGE_SIZE)
873 page_length = PAGE_SIZE - data_page_offset;
875 if (do_bit17_swizzling) {
876 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
878 user_pages[data_page_index],
883 ret = slow_shmem_copy(obj_priv->pages[shmem_page_index],
885 user_pages[data_page_index],
892 remain -= page_length;
893 data_ptr += page_length;
894 offset += page_length;
898 i915_gem_object_put_pages(obj);
900 mutex_unlock(&dev->struct_mutex);
902 for (i = 0; i < pinned_pages; i++)
903 page_cache_release(user_pages[i]);
904 drm_free_large(user_pages);
910 * Writes data to the object referenced by handle.
912 * On error, the contents of the buffer that were to be modified are undefined.
915 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
916 struct drm_file *file_priv)
918 struct drm_i915_gem_pwrite *args = data;
919 struct drm_gem_object *obj;
920 struct drm_i915_gem_object *obj_priv;
923 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
926 obj_priv = obj->driver_private;
928 /* Bounds check destination.
930 * XXX: This could use review for overflow issues...
932 if (args->offset > obj->size || args->size > obj->size ||
933 args->offset + args->size > obj->size) {
934 drm_gem_object_unreference(obj);
938 /* We can only do the GTT pwrite on untiled buffers, as otherwise
939 * it would end up going through the fenced access, and we'll get
940 * different detiling behavior between reading and writing.
941 * pread/pwrite currently are reading and writing from the CPU
942 * perspective, requiring manual detiling by the client.
944 if (obj_priv->phys_obj)
945 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
946 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
947 dev->gtt_total != 0) {
948 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
949 if (ret == -EFAULT) {
950 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
953 } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
954 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
956 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
957 if (ret == -EFAULT) {
958 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
965 DRM_INFO("pwrite failed %d\n", ret);
968 drm_gem_object_unreference(obj);
974 * Called when user space prepares to use an object with the CPU, either
975 * through the mmap ioctl's mapping or a GTT mapping.
978 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
979 struct drm_file *file_priv)
981 struct drm_i915_gem_set_domain *args = data;
982 struct drm_gem_object *obj;
983 uint32_t read_domains = args->read_domains;
984 uint32_t write_domain = args->write_domain;
987 if (!(dev->driver->driver_features & DRIVER_GEM))
990 /* Only handle setting domains to types used by the CPU. */
991 if (write_domain & I915_GEM_GPU_DOMAINS)
994 if (read_domains & I915_GEM_GPU_DOMAINS)
997 /* Having something in the write domain implies it's in the read
998 * domain, and only that read domain. Enforce that in the request.
1000 if (write_domain != 0 && read_domains != write_domain)
1003 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1007 mutex_lock(&dev->struct_mutex);
1009 DRM_INFO("set_domain_ioctl %p(%d), %08x %08x\n",
1010 obj, obj->size, read_domains, write_domain);
1012 if (read_domains & I915_GEM_DOMAIN_GTT) {
1013 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1015 /* Silently promote "you're not bound, there was nothing to do"
1016 * to success, since the client was just asking us to
1017 * make sure everything was done.
1022 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1025 drm_gem_object_unreference(obj);
1026 mutex_unlock(&dev->struct_mutex);
1031 * Called when user space has done writes to this buffer
1034 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1035 struct drm_file *file_priv)
1037 struct drm_i915_gem_sw_finish *args = data;
1038 struct drm_gem_object *obj;
1039 struct drm_i915_gem_object *obj_priv;
1042 if (!(dev->driver->driver_features & DRIVER_GEM))
1045 mutex_lock(&dev->struct_mutex);
1046 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1048 mutex_unlock(&dev->struct_mutex);
1053 DRM_INFO("%s: sw_finish %d (%p %d)\n",
1054 __func__, args->handle, obj, obj->size);
1056 obj_priv = obj->driver_private;
1058 /* Pinned buffers may be scanout, so flush the cache */
1059 if (obj_priv->pin_count)
1060 i915_gem_object_flush_cpu_write_domain(obj);
1062 drm_gem_object_unreference(obj);
1063 mutex_unlock(&dev->struct_mutex);
1068 * Maps the contents of an object, returning the address it is mapped
1071 * While the mapping holds a reference on the contents of the object, it doesn't
1072 * imply a ref on the object itself.
1075 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1076 struct drm_file *file_priv)
1078 struct drm_i915_gem_mmap *args = data;
1079 struct drm_gem_object *obj;
1083 if (!(dev->driver->driver_features & DRIVER_GEM))
1086 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1090 offset = args->offset;
1092 down_write(¤t->mm->mmap_sem);
1093 addr = do_mmap(obj->filp, 0, args->size,
1094 PROT_READ | PROT_WRITE, MAP_SHARED,
1096 up_write(¤t->mm->mmap_sem);
1097 mutex_lock(&dev->struct_mutex);
1098 drm_gem_object_unreference(obj);
1099 mutex_unlock(&dev->struct_mutex);
1100 if (IS_ERR((void *)addr))
1103 args->addr_ptr = (uint64_t) addr;
1109 * i915_gem_fault - fault a page into the GTT
1110 * vma: VMA in question
1113 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1114 * from userspace. The fault handler takes care of binding the object to
1115 * the GTT (if needed), allocating and programming a fence register (again,
1116 * only if needed based on whether the old reg is still valid or the object
1117 * is tiled) and inserting a new PTE into the faulting process.
1119 * Note that the faulting process may involve evicting existing objects
1120 * from the GTT and/or fence registers to make room. So performance may
1121 * suffer if the GTT working set is large or there are few fence registers
1124 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1126 struct drm_gem_object *obj = vma->vm_private_data;
1127 struct drm_device *dev = obj->dev;
1128 struct drm_i915_private *dev_priv = dev->dev_private;
1129 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1130 pgoff_t page_offset;
1133 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1135 /* We don't use vmf->pgoff since that has the fake offset */
1136 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1139 /* Now bind it into the GTT if needed */
1140 mutex_lock(&dev->struct_mutex);
1141 if (!obj_priv->gtt_space) {
1142 ret = i915_gem_object_bind_to_gtt(obj, obj_priv->gtt_alignment);
1144 mutex_unlock(&dev->struct_mutex);
1145 return VM_FAULT_SIGBUS;
1148 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1150 mutex_unlock(&dev->struct_mutex);
1151 return VM_FAULT_SIGBUS;
1154 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1157 /* Need a new fence register? */
1158 if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1159 obj_priv->tiling_mode != I915_TILING_NONE) {
1160 ret = i915_gem_object_get_fence_reg(obj);
1162 mutex_unlock(&dev->struct_mutex);
1163 return VM_FAULT_SIGBUS;
1167 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1170 /* Finally, remap it using the new GTT offset */
1171 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1173 mutex_unlock(&dev->struct_mutex);
1178 return VM_FAULT_OOM;
1181 return VM_FAULT_SIGBUS;
1183 return VM_FAULT_NOPAGE;
1188 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1189 * @obj: obj in question
1191 * GEM memory mapping works by handing back to userspace a fake mmap offset
1192 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1193 * up the object based on the offset and sets up the various memory mapping
1196 * This routine allocates and attaches a fake offset for @obj.
1199 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1201 struct drm_device *dev = obj->dev;
1202 struct drm_gem_mm *mm = dev->mm_private;
1203 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1204 struct drm_map_list *list;
1205 struct drm_local_map *map;
1208 /* Set the object up for mmap'ing */
1209 list = &obj->map_list;
1210 list->map = drm_calloc(1, sizeof(struct drm_map_list),
1216 map->type = _DRM_GEM;
1217 map->size = obj->size;
1220 /* Get a DRM GEM mmap offset allocated... */
1221 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1222 obj->size / PAGE_SIZE, 0, 0);
1223 if (!list->file_offset_node) {
1224 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1229 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1230 obj->size / PAGE_SIZE, 0);
1231 if (!list->file_offset_node) {
1236 list->hash.key = list->file_offset_node->start;
1237 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1238 DRM_ERROR("failed to add to map hash\n");
1242 /* By now we should be all set, any drm_mmap request on the offset
1243 * below will get to our mmap & fault handler */
1244 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1249 drm_mm_put_block(list->file_offset_node);
1251 drm_free(list->map, sizeof(struct drm_map_list), DRM_MEM_DRIVER);
1257 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1259 struct drm_device *dev = obj->dev;
1260 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1261 struct drm_gem_mm *mm = dev->mm_private;
1262 struct drm_map_list *list;
1264 list = &obj->map_list;
1265 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1267 if (list->file_offset_node) {
1268 drm_mm_put_block(list->file_offset_node);
1269 list->file_offset_node = NULL;
1273 drm_free(list->map, sizeof(struct drm_map), DRM_MEM_DRIVER);
1277 obj_priv->mmap_offset = 0;
1281 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1282 * @obj: object to check
1284 * Return the required GTT alignment for an object, taking into account
1285 * potential fence register mapping if needed.
1288 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1290 struct drm_device *dev = obj->dev;
1291 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1295 * Minimum alignment is 4k (GTT page size), but might be greater
1296 * if a fence register is needed for the object.
1298 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1302 * Previous chips need to be aligned to the size of the smallest
1303 * fence register that can contain the object.
1310 for (i = start; i < obj->size; i <<= 1)
1317 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1319 * @data: GTT mapping ioctl data
1320 * @file_priv: GEM object info
1322 * Simply returns the fake offset to userspace so it can mmap it.
1323 * The mmap call will end up in drm_gem_mmap(), which will set things
1324 * up so we can get faults in the handler above.
1326 * The fault handler will take care of binding the object into the GTT
1327 * (since it may have been evicted to make room for something), allocating
1328 * a fence register, and mapping the appropriate aperture address into
1332 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1333 struct drm_file *file_priv)
1335 struct drm_i915_gem_mmap_gtt *args = data;
1336 struct drm_i915_private *dev_priv = dev->dev_private;
1337 struct drm_gem_object *obj;
1338 struct drm_i915_gem_object *obj_priv;
1341 if (!(dev->driver->driver_features & DRIVER_GEM))
1344 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1348 mutex_lock(&dev->struct_mutex);
1350 obj_priv = obj->driver_private;
1352 if (!obj_priv->mmap_offset) {
1353 ret = i915_gem_create_mmap_offset(obj);
1355 drm_gem_object_unreference(obj);
1356 mutex_unlock(&dev->struct_mutex);
1361 args->offset = obj_priv->mmap_offset;
1363 obj_priv->gtt_alignment = i915_gem_get_gtt_alignment(obj);
1365 /* Make sure the alignment is correct for fence regs etc */
1366 if (obj_priv->agp_mem &&
1367 (obj_priv->gtt_offset & (obj_priv->gtt_alignment - 1))) {
1368 drm_gem_object_unreference(obj);
1369 mutex_unlock(&dev->struct_mutex);
1374 * Pull it into the GTT so that we have a page list (makes the
1375 * initial fault faster and any subsequent flushing possible).
1377 if (!obj_priv->agp_mem) {
1378 ret = i915_gem_object_bind_to_gtt(obj, obj_priv->gtt_alignment);
1380 drm_gem_object_unreference(obj);
1381 mutex_unlock(&dev->struct_mutex);
1384 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1387 drm_gem_object_unreference(obj);
1388 mutex_unlock(&dev->struct_mutex);
1394 i915_gem_object_put_pages(struct drm_gem_object *obj)
1396 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1397 int page_count = obj->size / PAGE_SIZE;
1400 BUG_ON(obj_priv->pages_refcount == 0);
1402 if (--obj_priv->pages_refcount != 0)
1405 if (obj_priv->tiling_mode != I915_TILING_NONE)
1406 i915_gem_object_save_bit_17_swizzle(obj);
1408 for (i = 0; i < page_count; i++)
1409 if (obj_priv->pages[i] != NULL) {
1410 if (obj_priv->dirty)
1411 set_page_dirty(obj_priv->pages[i]);
1412 mark_page_accessed(obj_priv->pages[i]);
1413 page_cache_release(obj_priv->pages[i]);
1415 obj_priv->dirty = 0;
1417 drm_free_large(obj_priv->pages);
1418 obj_priv->pages = NULL;
1422 i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
1424 struct drm_device *dev = obj->dev;
1425 drm_i915_private_t *dev_priv = dev->dev_private;
1426 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1428 /* Add a reference if we're newly entering the active list. */
1429 if (!obj_priv->active) {
1430 drm_gem_object_reference(obj);
1431 obj_priv->active = 1;
1433 /* Move from whatever list we were on to the tail of execution. */
1434 spin_lock(&dev_priv->mm.active_list_lock);
1435 list_move_tail(&obj_priv->list,
1436 &dev_priv->mm.active_list);
1437 spin_unlock(&dev_priv->mm.active_list_lock);
1438 obj_priv->last_rendering_seqno = seqno;
1442 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1444 struct drm_device *dev = obj->dev;
1445 drm_i915_private_t *dev_priv = dev->dev_private;
1446 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1448 BUG_ON(!obj_priv->active);
1449 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1450 obj_priv->last_rendering_seqno = 0;
1454 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1456 struct drm_device *dev = obj->dev;
1457 drm_i915_private_t *dev_priv = dev->dev_private;
1458 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1460 i915_verify_inactive(dev, __FILE__, __LINE__);
1461 if (obj_priv->pin_count != 0)
1462 list_del_init(&obj_priv->list);
1464 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1466 obj_priv->last_rendering_seqno = 0;
1467 if (obj_priv->active) {
1468 obj_priv->active = 0;
1469 drm_gem_object_unreference(obj);
1471 i915_verify_inactive(dev, __FILE__, __LINE__);
1475 * Creates a new sequence number, emitting a write of it to the status page
1476 * plus an interrupt, which will trigger i915_user_interrupt_handler.
1478 * Must be called with struct_lock held.
1480 * Returned sequence numbers are nonzero on success.
1483 i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1484 uint32_t flush_domains)
1486 drm_i915_private_t *dev_priv = dev->dev_private;
1487 struct drm_i915_file_private *i915_file_priv = NULL;
1488 struct drm_i915_gem_request *request;
1493 if (file_priv != NULL)
1494 i915_file_priv = file_priv->driver_priv;
1496 request = drm_calloc(1, sizeof(*request), DRM_MEM_DRIVER);
1497 if (request == NULL)
1500 /* Grab the seqno we're going to make this request be, and bump the
1501 * next (skipping 0 so it can be the reserved no-seqno value).
1503 seqno = dev_priv->mm.next_gem_seqno;
1504 dev_priv->mm.next_gem_seqno++;
1505 if (dev_priv->mm.next_gem_seqno == 0)
1506 dev_priv->mm.next_gem_seqno++;
1509 OUT_RING(MI_STORE_DWORD_INDEX);
1510 OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1513 OUT_RING(MI_USER_INTERRUPT);
1516 DRM_DEBUG("%d\n", seqno);
1518 request->seqno = seqno;
1519 request->emitted_jiffies = jiffies;
1520 was_empty = list_empty(&dev_priv->mm.request_list);
1521 list_add_tail(&request->list, &dev_priv->mm.request_list);
1522 if (i915_file_priv) {
1523 list_add_tail(&request->client_list,
1524 &i915_file_priv->mm.request_list);
1526 INIT_LIST_HEAD(&request->client_list);
1529 /* Associate any objects on the flushing list matching the write
1530 * domain we're flushing with our flush.
1532 if (flush_domains != 0) {
1533 struct drm_i915_gem_object *obj_priv, *next;
1535 list_for_each_entry_safe(obj_priv, next,
1536 &dev_priv->mm.flushing_list, list) {
1537 struct drm_gem_object *obj = obj_priv->obj;
1539 if ((obj->write_domain & flush_domains) ==
1540 obj->write_domain) {
1541 obj->write_domain = 0;
1542 i915_gem_object_move_to_active(obj, seqno);
1548 if (was_empty && !dev_priv->mm.suspended)
1549 schedule_delayed_work(&dev_priv->mm.retire_work, HZ);
1554 * Command execution barrier
1556 * Ensures that all commands in the ring are finished
1557 * before signalling the CPU
1560 i915_retire_commands(struct drm_device *dev)
1562 drm_i915_private_t *dev_priv = dev->dev_private;
1563 uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1564 uint32_t flush_domains = 0;
1567 /* The sampler always gets flushed on i965 (sigh) */
1569 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1572 OUT_RING(0); /* noop */
1574 return flush_domains;
1578 * Moves buffers associated only with the given active seqno from the active
1579 * to inactive list, potentially freeing them.
1582 i915_gem_retire_request(struct drm_device *dev,
1583 struct drm_i915_gem_request *request)
1585 drm_i915_private_t *dev_priv = dev->dev_private;
1587 /* Move any buffers on the active list that are no longer referenced
1588 * by the ringbuffer to the flushing/inactive lists as appropriate.
1590 spin_lock(&dev_priv->mm.active_list_lock);
1591 while (!list_empty(&dev_priv->mm.active_list)) {
1592 struct drm_gem_object *obj;
1593 struct drm_i915_gem_object *obj_priv;
1595 obj_priv = list_first_entry(&dev_priv->mm.active_list,
1596 struct drm_i915_gem_object,
1598 obj = obj_priv->obj;
1600 /* If the seqno being retired doesn't match the oldest in the
1601 * list, then the oldest in the list must still be newer than
1604 if (obj_priv->last_rendering_seqno != request->seqno)
1608 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1609 __func__, request->seqno, obj);
1612 if (obj->write_domain != 0)
1613 i915_gem_object_move_to_flushing(obj);
1615 /* Take a reference on the object so it won't be
1616 * freed while the spinlock is held. The list
1617 * protection for this spinlock is safe when breaking
1618 * the lock like this since the next thing we do
1619 * is just get the head of the list again.
1621 drm_gem_object_reference(obj);
1622 i915_gem_object_move_to_inactive(obj);
1623 spin_unlock(&dev_priv->mm.active_list_lock);
1624 drm_gem_object_unreference(obj);
1625 spin_lock(&dev_priv->mm.active_list_lock);
1629 spin_unlock(&dev_priv->mm.active_list_lock);
1633 * Returns true if seq1 is later than seq2.
1636 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1638 return (int32_t)(seq1 - seq2) >= 0;
1642 i915_get_gem_seqno(struct drm_device *dev)
1644 drm_i915_private_t *dev_priv = dev->dev_private;
1646 return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
1650 * This function clears the request list as sequence numbers are passed.
1653 i915_gem_retire_requests(struct drm_device *dev)
1655 drm_i915_private_t *dev_priv = dev->dev_private;
1658 if (!dev_priv->hw_status_page)
1661 seqno = i915_get_gem_seqno(dev);
1663 while (!list_empty(&dev_priv->mm.request_list)) {
1664 struct drm_i915_gem_request *request;
1665 uint32_t retiring_seqno;
1667 request = list_first_entry(&dev_priv->mm.request_list,
1668 struct drm_i915_gem_request,
1670 retiring_seqno = request->seqno;
1672 if (i915_seqno_passed(seqno, retiring_seqno) ||
1673 dev_priv->mm.wedged) {
1674 i915_gem_retire_request(dev, request);
1676 list_del(&request->list);
1677 list_del(&request->client_list);
1678 drm_free(request, sizeof(*request), DRM_MEM_DRIVER);
1685 i915_gem_retire_work_handler(struct work_struct *work)
1687 drm_i915_private_t *dev_priv;
1688 struct drm_device *dev;
1690 dev_priv = container_of(work, drm_i915_private_t,
1691 mm.retire_work.work);
1692 dev = dev_priv->dev;
1694 mutex_lock(&dev->struct_mutex);
1695 i915_gem_retire_requests(dev);
1696 if (!dev_priv->mm.suspended &&
1697 !list_empty(&dev_priv->mm.request_list))
1698 schedule_delayed_work(&dev_priv->mm.retire_work, HZ);
1699 mutex_unlock(&dev->struct_mutex);
1703 * Waits for a sequence number to be signaled, and cleans up the
1704 * request and object lists appropriately for that event.
1707 i915_wait_request(struct drm_device *dev, uint32_t seqno)
1709 drm_i915_private_t *dev_priv = dev->dev_private;
1715 if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
1717 ier = I915_READ(DEIER) | I915_READ(GTIER);
1719 ier = I915_READ(IER);
1721 DRM_ERROR("something (likely vbetool) disabled "
1722 "interrupts, re-enabling\n");
1723 i915_driver_irq_preinstall(dev);
1724 i915_driver_irq_postinstall(dev);
1727 dev_priv->mm.waiting_gem_seqno = seqno;
1728 i915_user_irq_get(dev);
1729 ret = wait_event_interruptible(dev_priv->irq_queue,
1730 i915_seqno_passed(i915_get_gem_seqno(dev),
1732 dev_priv->mm.wedged);
1733 i915_user_irq_put(dev);
1734 dev_priv->mm.waiting_gem_seqno = 0;
1736 if (dev_priv->mm.wedged)
1739 if (ret && ret != -ERESTARTSYS)
1740 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1741 __func__, ret, seqno, i915_get_gem_seqno(dev));
1743 /* Directly dispatch request retiring. While we have the work queue
1744 * to handle this, the waiter on a request often wants an associated
1745 * buffer to have made it to the inactive list, and we would need
1746 * a separate wait queue to handle that.
1749 i915_gem_retire_requests(dev);
1755 i915_gem_flush(struct drm_device *dev,
1756 uint32_t invalidate_domains,
1757 uint32_t flush_domains)
1759 drm_i915_private_t *dev_priv = dev->dev_private;
1764 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
1765 invalidate_domains, flush_domains);
1768 if (flush_domains & I915_GEM_DOMAIN_CPU)
1769 drm_agp_chipset_flush(dev);
1771 if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
1773 * read/write caches:
1775 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1776 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
1777 * also flushed at 2d versus 3d pipeline switches.
1781 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1782 * MI_READ_FLUSH is set, and is always flushed on 965.
1784 * I915_GEM_DOMAIN_COMMAND may not exist?
1786 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1787 * invalidated when MI_EXE_FLUSH is set.
1789 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1790 * invalidated with every MI_FLUSH.
1794 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1795 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1796 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1797 * are flushed at any MI_FLUSH.
1800 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1801 if ((invalidate_domains|flush_domains) &
1802 I915_GEM_DOMAIN_RENDER)
1803 cmd &= ~MI_NO_WRITE_FLUSH;
1804 if (!IS_I965G(dev)) {
1806 * On the 965, the sampler cache always gets flushed
1807 * and this bit is reserved.
1809 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
1810 cmd |= MI_READ_FLUSH;
1812 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
1813 cmd |= MI_EXE_FLUSH;
1816 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
1820 OUT_RING(0); /* noop */
1826 * Ensures that all rendering to the object has completed and the object is
1827 * safe to unbind from the GTT or access from the CPU.
1830 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1832 struct drm_device *dev = obj->dev;
1833 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1836 /* This function only exists to support waiting for existing rendering,
1837 * not for emitting required flushes.
1839 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
1841 /* If there is rendering queued on the buffer being evicted, wait for
1844 if (obj_priv->active) {
1846 DRM_INFO("%s: object %p wait for seqno %08x\n",
1847 __func__, obj, obj_priv->last_rendering_seqno);
1849 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
1858 * Unbinds an object from the GTT aperture.
1861 i915_gem_object_unbind(struct drm_gem_object *obj)
1863 struct drm_device *dev = obj->dev;
1864 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1869 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1870 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1872 if (obj_priv->gtt_space == NULL)
1875 if (obj_priv->pin_count != 0) {
1876 DRM_ERROR("Attempting to unbind pinned buffer\n");
1880 /* Move the object to the CPU domain to ensure that
1881 * any possible CPU writes while it's not in the GTT
1882 * are flushed when we go to remap it. This will
1883 * also ensure that all pending GPU writes are finished
1886 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1888 if (ret != -ERESTARTSYS)
1889 DRM_ERROR("set_domain failed: %d\n", ret);
1893 if (obj_priv->agp_mem != NULL) {
1894 drm_unbind_agp(obj_priv->agp_mem);
1895 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
1896 obj_priv->agp_mem = NULL;
1899 BUG_ON(obj_priv->active);
1901 /* blow away mappings if mapped through GTT */
1902 offset = ((loff_t) obj->map_list.hash.key) << PAGE_SHIFT;
1903 if (dev->dev_mapping)
1904 unmap_mapping_range(dev->dev_mapping, offset, obj->size, 1);
1906 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
1907 i915_gem_clear_fence_reg(obj);
1909 i915_gem_object_put_pages(obj);
1911 if (obj_priv->gtt_space) {
1912 atomic_dec(&dev->gtt_count);
1913 atomic_sub(obj->size, &dev->gtt_memory);
1915 drm_mm_put_block(obj_priv->gtt_space);
1916 obj_priv->gtt_space = NULL;
1919 /* Remove ourselves from the LRU list if present. */
1920 if (!list_empty(&obj_priv->list))
1921 list_del_init(&obj_priv->list);
1927 i915_gem_evict_something(struct drm_device *dev)
1929 drm_i915_private_t *dev_priv = dev->dev_private;
1930 struct drm_gem_object *obj;
1931 struct drm_i915_gem_object *obj_priv;
1935 /* If there's an inactive buffer available now, grab it
1938 if (!list_empty(&dev_priv->mm.inactive_list)) {
1939 obj_priv = list_first_entry(&dev_priv->mm.inactive_list,
1940 struct drm_i915_gem_object,
1942 obj = obj_priv->obj;
1943 BUG_ON(obj_priv->pin_count != 0);
1945 DRM_INFO("%s: evicting %p\n", __func__, obj);
1947 BUG_ON(obj_priv->active);
1949 /* Wait on the rendering and unbind the buffer. */
1950 ret = i915_gem_object_unbind(obj);
1954 /* If we didn't get anything, but the ring is still processing
1955 * things, wait for one of those things to finish and hopefully
1956 * leave us a buffer to evict.
1958 if (!list_empty(&dev_priv->mm.request_list)) {
1959 struct drm_i915_gem_request *request;
1961 request = list_first_entry(&dev_priv->mm.request_list,
1962 struct drm_i915_gem_request,
1965 ret = i915_wait_request(dev, request->seqno);
1969 /* if waiting caused an object to become inactive,
1970 * then loop around and wait for it. Otherwise, we
1971 * assume that waiting freed and unbound something,
1972 * so there should now be some space in the GTT
1974 if (!list_empty(&dev_priv->mm.inactive_list))
1979 /* If we didn't have anything on the request list but there
1980 * are buffers awaiting a flush, emit one and try again.
1981 * When we wait on it, those buffers waiting for that flush
1982 * will get moved to inactive.
1984 if (!list_empty(&dev_priv->mm.flushing_list)) {
1985 obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
1986 struct drm_i915_gem_object,
1988 obj = obj_priv->obj;
1993 i915_add_request(dev, NULL, obj->write_domain);
1999 DRM_ERROR("inactive empty %d request empty %d "
2000 "flushing empty %d\n",
2001 list_empty(&dev_priv->mm.inactive_list),
2002 list_empty(&dev_priv->mm.request_list),
2003 list_empty(&dev_priv->mm.flushing_list));
2004 /* If we didn't do any of the above, there's nothing to be done
2005 * and we just can't fit it in.
2013 i915_gem_evict_everything(struct drm_device *dev)
2018 ret = i915_gem_evict_something(dev);
2028 i915_gem_object_get_pages(struct drm_gem_object *obj)
2030 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2032 struct address_space *mapping;
2033 struct inode *inode;
2037 if (obj_priv->pages_refcount++ != 0)
2040 /* Get the list of pages out of our struct file. They'll be pinned
2041 * at this point until we release them.
2043 page_count = obj->size / PAGE_SIZE;
2044 BUG_ON(obj_priv->pages != NULL);
2045 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
2046 if (obj_priv->pages == NULL) {
2047 DRM_ERROR("Faled to allocate page list\n");
2048 obj_priv->pages_refcount--;
2052 inode = obj->filp->f_path.dentry->d_inode;
2053 mapping = inode->i_mapping;
2054 for (i = 0; i < page_count; i++) {
2055 page = read_mapping_page(mapping, i, NULL);
2057 ret = PTR_ERR(page);
2058 DRM_ERROR("read_mapping_page failed: %d\n", ret);
2059 i915_gem_object_put_pages(obj);
2062 obj_priv->pages[i] = page;
2065 if (obj_priv->tiling_mode != I915_TILING_NONE)
2066 i915_gem_object_do_bit_17_swizzle(obj);
2071 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2073 struct drm_gem_object *obj = reg->obj;
2074 struct drm_device *dev = obj->dev;
2075 drm_i915_private_t *dev_priv = dev->dev_private;
2076 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2077 int regnum = obj_priv->fence_reg;
2080 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2082 val |= obj_priv->gtt_offset & 0xfffff000;
2083 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2084 if (obj_priv->tiling_mode == I915_TILING_Y)
2085 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2086 val |= I965_FENCE_REG_VALID;
2088 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2091 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2093 struct drm_gem_object *obj = reg->obj;
2094 struct drm_device *dev = obj->dev;
2095 drm_i915_private_t *dev_priv = dev->dev_private;
2096 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2097 int regnum = obj_priv->fence_reg;
2099 uint32_t fence_reg, val;
2102 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2103 (obj_priv->gtt_offset & (obj->size - 1))) {
2104 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2105 __func__, obj_priv->gtt_offset, obj->size);
2109 if (obj_priv->tiling_mode == I915_TILING_Y &&
2110 HAS_128_BYTE_Y_TILING(dev))
2115 /* Note: pitch better be a power of two tile widths */
2116 pitch_val = obj_priv->stride / tile_width;
2117 pitch_val = ffs(pitch_val) - 1;
2119 val = obj_priv->gtt_offset;
2120 if (obj_priv->tiling_mode == I915_TILING_Y)
2121 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2122 val |= I915_FENCE_SIZE_BITS(obj->size);
2123 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2124 val |= I830_FENCE_REG_VALID;
2127 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2129 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2130 I915_WRITE(fence_reg, val);
2133 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2135 struct drm_gem_object *obj = reg->obj;
2136 struct drm_device *dev = obj->dev;
2137 drm_i915_private_t *dev_priv = dev->dev_private;
2138 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2139 int regnum = obj_priv->fence_reg;
2142 uint32_t fence_size_bits;
2144 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
2145 (obj_priv->gtt_offset & (obj->size - 1))) {
2146 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2147 __func__, obj_priv->gtt_offset);
2151 pitch_val = obj_priv->stride / 128;
2152 pitch_val = ffs(pitch_val) - 1;
2153 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2155 val = obj_priv->gtt_offset;
2156 if (obj_priv->tiling_mode == I915_TILING_Y)
2157 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2158 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2159 WARN_ON(fence_size_bits & ~0x00000f00);
2160 val |= fence_size_bits;
2161 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2162 val |= I830_FENCE_REG_VALID;
2164 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
2169 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2170 * @obj: object to map through a fence reg
2172 * When mapping objects through the GTT, userspace wants to be able to write
2173 * to them without having to worry about swizzling if the object is tiled.
2175 * This function walks the fence regs looking for a free one for @obj,
2176 * stealing one if it can't find any.
2178 * It then sets up the reg based on the object's properties: address, pitch
2179 * and tiling format.
2182 i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
2184 struct drm_device *dev = obj->dev;
2185 struct drm_i915_private *dev_priv = dev->dev_private;
2186 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2187 struct drm_i915_fence_reg *reg = NULL;
2188 struct drm_i915_gem_object *old_obj_priv = NULL;
2191 switch (obj_priv->tiling_mode) {
2192 case I915_TILING_NONE:
2193 WARN(1, "allocating a fence for non-tiled object?\n");
2196 if (!obj_priv->stride)
2198 WARN((obj_priv->stride & (512 - 1)),
2199 "object 0x%08x is X tiled but has non-512B pitch\n",
2200 obj_priv->gtt_offset);
2203 if (!obj_priv->stride)
2205 WARN((obj_priv->stride & (128 - 1)),
2206 "object 0x%08x is Y tiled but has non-128B pitch\n",
2207 obj_priv->gtt_offset);
2211 /* First try to find a free reg */
2214 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2215 reg = &dev_priv->fence_regs[i];
2219 old_obj_priv = reg->obj->driver_private;
2220 if (!old_obj_priv->pin_count)
2224 /* None available, try to steal one or wait for a user to finish */
2225 if (i == dev_priv->num_fence_regs) {
2226 uint32_t seqno = dev_priv->mm.next_gem_seqno;
2232 for (i = dev_priv->fence_reg_start;
2233 i < dev_priv->num_fence_regs; i++) {
2234 uint32_t this_seqno;
2236 reg = &dev_priv->fence_regs[i];
2237 old_obj_priv = reg->obj->driver_private;
2239 if (old_obj_priv->pin_count)
2242 /* i915 uses fences for GPU access to tiled buffers */
2243 if (IS_I965G(dev) || !old_obj_priv->active)
2246 /* find the seqno of the first available fence */
2247 this_seqno = old_obj_priv->last_rendering_seqno;
2248 if (this_seqno != 0 &&
2249 reg->obj->write_domain == 0 &&
2250 i915_seqno_passed(seqno, this_seqno))
2255 * Now things get ugly... we have to wait for one of the
2256 * objects to finish before trying again.
2258 if (i == dev_priv->num_fence_regs) {
2259 if (seqno == dev_priv->mm.next_gem_seqno) {
2261 I915_GEM_GPU_DOMAINS,
2262 I915_GEM_GPU_DOMAINS);
2263 seqno = i915_add_request(dev, NULL,
2264 I915_GEM_GPU_DOMAINS);
2269 ret = i915_wait_request(dev, seqno);
2276 * Zap this virtual mapping so we can set up a fence again
2277 * for this object next time we need it.
2279 offset = ((loff_t) reg->obj->map_list.hash.key) << PAGE_SHIFT;
2280 if (dev->dev_mapping)
2281 unmap_mapping_range(dev->dev_mapping, offset,
2283 old_obj_priv->fence_reg = I915_FENCE_REG_NONE;
2286 obj_priv->fence_reg = i;
2290 i965_write_fence_reg(reg);
2291 else if (IS_I9XX(dev))
2292 i915_write_fence_reg(reg);
2294 i830_write_fence_reg(reg);
2300 * i915_gem_clear_fence_reg - clear out fence register info
2301 * @obj: object to clear
2303 * Zeroes out the fence register itself and clears out the associated
2304 * data structures in dev_priv and obj_priv.
2307 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2309 struct drm_device *dev = obj->dev;
2310 drm_i915_private_t *dev_priv = dev->dev_private;
2311 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2314 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
2318 if (obj_priv->fence_reg < 8)
2319 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2321 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2324 I915_WRITE(fence_reg, 0);
2327 dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL;
2328 obj_priv->fence_reg = I915_FENCE_REG_NONE;
2332 * Finds free space in the GTT aperture and binds the object there.
2335 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2337 struct drm_device *dev = obj->dev;
2338 drm_i915_private_t *dev_priv = dev->dev_private;
2339 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2340 struct drm_mm_node *free_space;
2341 int page_count, ret;
2343 if (dev_priv->mm.suspended)
2346 alignment = i915_gem_get_gtt_alignment(obj);
2347 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
2348 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2353 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2354 obj->size, alignment, 0);
2355 if (free_space != NULL) {
2356 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2358 if (obj_priv->gtt_space != NULL) {
2359 obj_priv->gtt_space->private = obj;
2360 obj_priv->gtt_offset = obj_priv->gtt_space->start;
2363 if (obj_priv->gtt_space == NULL) {
2366 /* If the gtt is empty and we're still having trouble
2367 * fitting our object in, we're out of memory.
2370 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2372 spin_lock(&dev_priv->mm.active_list_lock);
2373 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2374 list_empty(&dev_priv->mm.flushing_list) &&
2375 list_empty(&dev_priv->mm.active_list));
2376 spin_unlock(&dev_priv->mm.active_list_lock);
2378 DRM_ERROR("GTT full, but LRU list empty\n");
2382 ret = i915_gem_evict_something(dev);
2384 if (ret != -ERESTARTSYS)
2385 DRM_ERROR("Failed to evict a buffer %d\n", ret);
2392 DRM_INFO("Binding object of size %d at 0x%08x\n",
2393 obj->size, obj_priv->gtt_offset);
2395 ret = i915_gem_object_get_pages(obj);
2397 drm_mm_put_block(obj_priv->gtt_space);
2398 obj_priv->gtt_space = NULL;
2402 page_count = obj->size / PAGE_SIZE;
2403 /* Create an AGP memory structure pointing at our pages, and bind it
2406 obj_priv->agp_mem = drm_agp_bind_pages(dev,
2409 obj_priv->gtt_offset,
2410 obj_priv->agp_type);
2411 if (obj_priv->agp_mem == NULL) {
2412 i915_gem_object_put_pages(obj);
2413 drm_mm_put_block(obj_priv->gtt_space);
2414 obj_priv->gtt_space = NULL;
2417 atomic_inc(&dev->gtt_count);
2418 atomic_add(obj->size, &dev->gtt_memory);
2420 /* Assert that the object is not currently in any GPU domain. As it
2421 * wasn't in the GTT, there shouldn't be any way it could have been in
2424 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2425 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
2431 i915_gem_clflush_object(struct drm_gem_object *obj)
2433 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2435 /* If we don't have a page list set up, then we're not pinned
2436 * to GPU, and we can ignore the cache flush because it'll happen
2437 * again at bind time.
2439 if (obj_priv->pages == NULL)
2442 /* XXX: The 865 in particular appears to be weird in how it handles
2443 * cache flushing. We haven't figured it out, but the
2444 * clflush+agp_chipset_flush doesn't appear to successfully get the
2445 * data visible to the PGU, while wbinvd + agp_chipset_flush does.
2447 if (IS_I865G(obj->dev)) {
2452 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2455 /** Flushes any GPU write domain for the object if it's dirty. */
2457 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2459 struct drm_device *dev = obj->dev;
2462 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2465 /* Queue the GPU write cache flushing we need. */
2466 i915_gem_flush(dev, 0, obj->write_domain);
2467 seqno = i915_add_request(dev, NULL, obj->write_domain);
2468 obj->write_domain = 0;
2469 i915_gem_object_move_to_active(obj, seqno);
2472 /** Flushes the GTT write domain for the object if it's dirty. */
2474 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2476 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2479 /* No actual flushing is required for the GTT write domain. Writes
2480 * to it immediately go to main memory as far as we know, so there's
2481 * no chipset flush. It also doesn't land in render cache.
2483 obj->write_domain = 0;
2486 /** Flushes the CPU write domain for the object if it's dirty. */
2488 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2490 struct drm_device *dev = obj->dev;
2492 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2495 i915_gem_clflush_object(obj);
2496 drm_agp_chipset_flush(dev);
2497 obj->write_domain = 0;
2501 * Moves a single object to the GTT read, and possibly write domain.
2503 * This function returns when the move is complete, including waiting on
2507 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2509 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2512 /* Not valid to be called on unbound objects. */
2513 if (obj_priv->gtt_space == NULL)
2516 i915_gem_object_flush_gpu_write_domain(obj);
2517 /* Wait on any GPU rendering and flushing to occur. */
2518 ret = i915_gem_object_wait_rendering(obj);
2522 /* If we're writing through the GTT domain, then CPU and GPU caches
2523 * will need to be invalidated at next use.
2526 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2528 i915_gem_object_flush_cpu_write_domain(obj);
2530 /* It should now be out of any other write domains, and we can update
2531 * the domain values for our changes.
2533 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2534 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2536 obj->write_domain = I915_GEM_DOMAIN_GTT;
2537 obj_priv->dirty = 1;
2544 * Moves a single object to the CPU read, and possibly write domain.
2546 * This function returns when the move is complete, including waiting on
2550 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2554 i915_gem_object_flush_gpu_write_domain(obj);
2555 /* Wait on any GPU rendering and flushing to occur. */
2556 ret = i915_gem_object_wait_rendering(obj);
2560 i915_gem_object_flush_gtt_write_domain(obj);
2562 /* If we have a partially-valid cache of the object in the CPU,
2563 * finish invalidating it and free the per-page flags.
2565 i915_gem_object_set_to_full_cpu_read_domain(obj);
2567 /* Flush the CPU cache if it's still invalid. */
2568 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2569 i915_gem_clflush_object(obj);
2571 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2574 /* It should now be out of any other write domains, and we can update
2575 * the domain values for our changes.
2577 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2579 /* If we're writing through the CPU, then the GPU read domains will
2580 * need to be invalidated at next use.
2583 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2584 obj->write_domain = I915_GEM_DOMAIN_CPU;
2591 * Set the next domain for the specified object. This
2592 * may not actually perform the necessary flushing/invaliding though,
2593 * as that may want to be batched with other set_domain operations
2595 * This is (we hope) the only really tricky part of gem. The goal
2596 * is fairly simple -- track which caches hold bits of the object
2597 * and make sure they remain coherent. A few concrete examples may
2598 * help to explain how it works. For shorthand, we use the notation
2599 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2600 * a pair of read and write domain masks.
2602 * Case 1: the batch buffer
2608 * 5. Unmapped from GTT
2611 * Let's take these a step at a time
2614 * Pages allocated from the kernel may still have
2615 * cache contents, so we set them to (CPU, CPU) always.
2616 * 2. Written by CPU (using pwrite)
2617 * The pwrite function calls set_domain (CPU, CPU) and
2618 * this function does nothing (as nothing changes)
2620 * This function asserts that the object is not
2621 * currently in any GPU-based read or write domains
2623 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2624 * As write_domain is zero, this function adds in the
2625 * current read domains (CPU+COMMAND, 0).
2626 * flush_domains is set to CPU.
2627 * invalidate_domains is set to COMMAND
2628 * clflush is run to get data out of the CPU caches
2629 * then i915_dev_set_domain calls i915_gem_flush to
2630 * emit an MI_FLUSH and drm_agp_chipset_flush
2631 * 5. Unmapped from GTT
2632 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2633 * flush_domains and invalidate_domains end up both zero
2634 * so no flushing/invalidating happens
2638 * Case 2: The shared render buffer
2642 * 3. Read/written by GPU
2643 * 4. set_domain to (CPU,CPU)
2644 * 5. Read/written by CPU
2645 * 6. Read/written by GPU
2648 * Same as last example, (CPU, CPU)
2650 * Nothing changes (assertions find that it is not in the GPU)
2651 * 3. Read/written by GPU
2652 * execbuffer calls set_domain (RENDER, RENDER)
2653 * flush_domains gets CPU
2654 * invalidate_domains gets GPU
2656 * MI_FLUSH and drm_agp_chipset_flush
2657 * 4. set_domain (CPU, CPU)
2658 * flush_domains gets GPU
2659 * invalidate_domains gets CPU
2660 * wait_rendering (obj) to make sure all drawing is complete.
2661 * This will include an MI_FLUSH to get the data from GPU
2663 * clflush (obj) to invalidate the CPU cache
2664 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
2665 * 5. Read/written by CPU
2666 * cache lines are loaded and dirtied
2667 * 6. Read written by GPU
2668 * Same as last GPU access
2670 * Case 3: The constant buffer
2675 * 4. Updated (written) by CPU again
2684 * flush_domains = CPU
2685 * invalidate_domains = RENDER
2688 * drm_agp_chipset_flush
2689 * 4. Updated (written) by CPU again
2691 * flush_domains = 0 (no previous write domain)
2692 * invalidate_domains = 0 (no new read domains)
2695 * flush_domains = CPU
2696 * invalidate_domains = RENDER
2699 * drm_agp_chipset_flush
2702 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
2704 struct drm_device *dev = obj->dev;
2705 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2706 uint32_t invalidate_domains = 0;
2707 uint32_t flush_domains = 0;
2709 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
2710 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
2713 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2715 obj->read_domains, obj->pending_read_domains,
2716 obj->write_domain, obj->pending_write_domain);
2719 * If the object isn't moving to a new write domain,
2720 * let the object stay in multiple read domains
2722 if (obj->pending_write_domain == 0)
2723 obj->pending_read_domains |= obj->read_domains;
2725 obj_priv->dirty = 1;
2728 * Flush the current write domain if
2729 * the new read domains don't match. Invalidate
2730 * any read domains which differ from the old
2733 if (obj->write_domain &&
2734 obj->write_domain != obj->pending_read_domains) {
2735 flush_domains |= obj->write_domain;
2736 invalidate_domains |=
2737 obj->pending_read_domains & ~obj->write_domain;
2740 * Invalidate any read caches which may have
2741 * stale data. That is, any new read domains.
2743 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
2744 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
2746 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
2747 __func__, flush_domains, invalidate_domains);
2749 i915_gem_clflush_object(obj);
2752 /* The actual obj->write_domain will be updated with
2753 * pending_write_domain after we emit the accumulated flush for all
2754 * of our domain changes in execbuffers (which clears objects'
2755 * write_domains). So if we have a current write domain that we
2756 * aren't changing, set pending_write_domain to that.
2758 if (flush_domains == 0 && obj->pending_write_domain == 0)
2759 obj->pending_write_domain = obj->write_domain;
2760 obj->read_domains = obj->pending_read_domains;
2762 dev->invalidate_domains |= invalidate_domains;
2763 dev->flush_domains |= flush_domains;
2765 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
2767 obj->read_domains, obj->write_domain,
2768 dev->invalidate_domains, dev->flush_domains);
2773 * Moves the object from a partially CPU read to a full one.
2775 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
2776 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
2779 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
2781 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2783 if (!obj_priv->page_cpu_valid)
2786 /* If we're partially in the CPU read domain, finish moving it in.
2788 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
2791 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
2792 if (obj_priv->page_cpu_valid[i])
2794 drm_clflush_pages(obj_priv->pages + i, 1);
2798 /* Free the page_cpu_valid mappings which are now stale, whether
2799 * or not we've got I915_GEM_DOMAIN_CPU.
2801 drm_free(obj_priv->page_cpu_valid, obj->size / PAGE_SIZE,
2803 obj_priv->page_cpu_valid = NULL;
2807 * Set the CPU read domain on a range of the object.
2809 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
2810 * not entirely valid. The page_cpu_valid member of the object flags which
2811 * pages have been flushed, and will be respected by
2812 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
2813 * of the whole object.
2815 * This function returns when the move is complete, including waiting on
2819 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
2820 uint64_t offset, uint64_t size)
2822 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2825 if (offset == 0 && size == obj->size)
2826 return i915_gem_object_set_to_cpu_domain(obj, 0);
2828 i915_gem_object_flush_gpu_write_domain(obj);
2829 /* Wait on any GPU rendering and flushing to occur. */
2830 ret = i915_gem_object_wait_rendering(obj);
2833 i915_gem_object_flush_gtt_write_domain(obj);
2835 /* If we're already fully in the CPU read domain, we're done. */
2836 if (obj_priv->page_cpu_valid == NULL &&
2837 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
2840 /* Otherwise, create/clear the per-page CPU read domain flag if we're
2841 * newly adding I915_GEM_DOMAIN_CPU
2843 if (obj_priv->page_cpu_valid == NULL) {
2844 obj_priv->page_cpu_valid = drm_calloc(1, obj->size / PAGE_SIZE,
2846 if (obj_priv->page_cpu_valid == NULL)
2848 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
2849 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
2851 /* Flush the cache on any pages that are still invalid from the CPU's
2854 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
2856 if (obj_priv->page_cpu_valid[i])
2859 drm_clflush_pages(obj_priv->pages + i, 1);
2861 obj_priv->page_cpu_valid[i] = 1;
2864 /* It should now be out of any other write domains, and we can update
2865 * the domain values for our changes.
2867 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2869 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2875 * Pin an object to the GTT and evaluate the relocations landing in it.
2878 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
2879 struct drm_file *file_priv,
2880 struct drm_i915_gem_exec_object *entry,
2881 struct drm_i915_gem_relocation_entry *relocs)
2883 struct drm_device *dev = obj->dev;
2884 drm_i915_private_t *dev_priv = dev->dev_private;
2885 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2887 void __iomem *reloc_page;
2889 /* Choose the GTT offset for our buffer and put it there. */
2890 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
2894 entry->offset = obj_priv->gtt_offset;
2896 /* Apply the relocations, using the GTT aperture to avoid cache
2897 * flushing requirements.
2899 for (i = 0; i < entry->relocation_count; i++) {
2900 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
2901 struct drm_gem_object *target_obj;
2902 struct drm_i915_gem_object *target_obj_priv;
2903 uint32_t reloc_val, reloc_offset;
2904 uint32_t __iomem *reloc_entry;
2906 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
2907 reloc->target_handle);
2908 if (target_obj == NULL) {
2909 i915_gem_object_unpin(obj);
2912 target_obj_priv = target_obj->driver_private;
2914 /* The target buffer should have appeared before us in the
2915 * exec_object list, so it should have a GTT space bound by now.
2917 if (target_obj_priv->gtt_space == NULL) {
2918 DRM_ERROR("No GTT space found for object %d\n",
2919 reloc->target_handle);
2920 drm_gem_object_unreference(target_obj);
2921 i915_gem_object_unpin(obj);
2925 if (reloc->offset > obj->size - 4) {
2926 DRM_ERROR("Relocation beyond object bounds: "
2927 "obj %p target %d offset %d size %d.\n",
2928 obj, reloc->target_handle,
2929 (int) reloc->offset, (int) obj->size);
2930 drm_gem_object_unreference(target_obj);
2931 i915_gem_object_unpin(obj);
2934 if (reloc->offset & 3) {
2935 DRM_ERROR("Relocation not 4-byte aligned: "
2936 "obj %p target %d offset %d.\n",
2937 obj, reloc->target_handle,
2938 (int) reloc->offset);
2939 drm_gem_object_unreference(target_obj);
2940 i915_gem_object_unpin(obj);
2944 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
2945 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
2946 DRM_ERROR("reloc with read/write CPU domains: "
2947 "obj %p target %d offset %d "
2948 "read %08x write %08x",
2949 obj, reloc->target_handle,
2950 (int) reloc->offset,
2951 reloc->read_domains,
2952 reloc->write_domain);
2953 drm_gem_object_unreference(target_obj);
2954 i915_gem_object_unpin(obj);
2958 if (reloc->write_domain && target_obj->pending_write_domain &&
2959 reloc->write_domain != target_obj->pending_write_domain) {
2960 DRM_ERROR("Write domain conflict: "
2961 "obj %p target %d offset %d "
2962 "new %08x old %08x\n",
2963 obj, reloc->target_handle,
2964 (int) reloc->offset,
2965 reloc->write_domain,
2966 target_obj->pending_write_domain);
2967 drm_gem_object_unreference(target_obj);
2968 i915_gem_object_unpin(obj);
2973 DRM_INFO("%s: obj %p offset %08x target %d "
2974 "read %08x write %08x gtt %08x "
2975 "presumed %08x delta %08x\n",
2978 (int) reloc->offset,
2979 (int) reloc->target_handle,
2980 (int) reloc->read_domains,
2981 (int) reloc->write_domain,
2982 (int) target_obj_priv->gtt_offset,
2983 (int) reloc->presumed_offset,
2987 target_obj->pending_read_domains |= reloc->read_domains;
2988 target_obj->pending_write_domain |= reloc->write_domain;
2990 /* If the relocation already has the right value in it, no
2991 * more work needs to be done.
2993 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
2994 drm_gem_object_unreference(target_obj);
2998 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3000 drm_gem_object_unreference(target_obj);
3001 i915_gem_object_unpin(obj);
3005 /* Map the page containing the relocation we're going to
3008 reloc_offset = obj_priv->gtt_offset + reloc->offset;
3009 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3012 reloc_entry = (uint32_t __iomem *)(reloc_page +
3013 (reloc_offset & (PAGE_SIZE - 1)));
3014 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
3017 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3018 obj, (unsigned int) reloc->offset,
3019 readl(reloc_entry), reloc_val);
3021 writel(reloc_val, reloc_entry);
3022 io_mapping_unmap_atomic(reloc_page);
3024 /* The updated presumed offset for this entry will be
3025 * copied back out to the user.
3027 reloc->presumed_offset = target_obj_priv->gtt_offset;
3029 drm_gem_object_unreference(target_obj);
3034 i915_gem_dump_object(obj, 128, __func__, ~0);
3039 /** Dispatch a batchbuffer to the ring
3042 i915_dispatch_gem_execbuffer(struct drm_device *dev,
3043 struct drm_i915_gem_execbuffer *exec,
3044 struct drm_clip_rect *cliprects,
3045 uint64_t exec_offset)
3047 drm_i915_private_t *dev_priv = dev->dev_private;
3048 int nbox = exec->num_cliprects;
3050 uint32_t exec_start, exec_len;
3053 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3054 exec_len = (uint32_t) exec->batch_len;
3056 count = nbox ? nbox : 1;
3058 for (i = 0; i < count; i++) {
3060 int ret = i915_emit_box(dev, cliprects, i,
3061 exec->DR1, exec->DR4);
3066 if (IS_I830(dev) || IS_845G(dev)) {
3068 OUT_RING(MI_BATCH_BUFFER);
3069 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3070 OUT_RING(exec_start + exec_len - 4);
3075 if (IS_I965G(dev)) {
3076 OUT_RING(MI_BATCH_BUFFER_START |
3078 MI_BATCH_NON_SECURE_I965);
3079 OUT_RING(exec_start);
3081 OUT_RING(MI_BATCH_BUFFER_START |
3083 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3089 /* XXX breadcrumb */
3093 /* Throttle our rendering by waiting until the ring has completed our requests
3094 * emitted over 20 msec ago.
3096 * Note that if we were to use the current jiffies each time around the loop,
3097 * we wouldn't escape the function with any frames outstanding if the time to
3098 * render a frame was over 20ms.
3100 * This should get us reasonable parallelism between CPU and GPU but also
3101 * relatively low latency when blocking on a particular request to finish.
3104 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3106 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3108 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3110 mutex_lock(&dev->struct_mutex);
3111 while (!list_empty(&i915_file_priv->mm.request_list)) {
3112 struct drm_i915_gem_request *request;
3114 request = list_first_entry(&i915_file_priv->mm.request_list,
3115 struct drm_i915_gem_request,
3118 if (time_after_eq(request->emitted_jiffies, recent_enough))
3121 ret = i915_wait_request(dev, request->seqno);
3125 mutex_unlock(&dev->struct_mutex);
3131 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object *exec_list,
3132 uint32_t buffer_count,
3133 struct drm_i915_gem_relocation_entry **relocs)
3135 uint32_t reloc_count = 0, reloc_index = 0, i;
3139 for (i = 0; i < buffer_count; i++) {
3140 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3142 reloc_count += exec_list[i].relocation_count;
3145 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
3146 if (*relocs == NULL)
3149 for (i = 0; i < buffer_count; i++) {
3150 struct drm_i915_gem_relocation_entry __user *user_relocs;
3152 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3154 ret = copy_from_user(&(*relocs)[reloc_index],
3156 exec_list[i].relocation_count *
3159 drm_free_large(*relocs);
3164 reloc_index += exec_list[i].relocation_count;
3171 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object *exec_list,
3172 uint32_t buffer_count,
3173 struct drm_i915_gem_relocation_entry *relocs)
3175 uint32_t reloc_count = 0, i;
3178 for (i = 0; i < buffer_count; i++) {
3179 struct drm_i915_gem_relocation_entry __user *user_relocs;
3182 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3184 unwritten = copy_to_user(user_relocs,
3185 &relocs[reloc_count],
3186 exec_list[i].relocation_count *
3194 reloc_count += exec_list[i].relocation_count;
3198 drm_free_large(relocs);
3204 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer *exec,
3205 uint64_t exec_offset)
3207 uint32_t exec_start, exec_len;
3209 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3210 exec_len = (uint32_t) exec->batch_len;
3212 if ((exec_start | exec_len) & 0x7)
3222 i915_gem_execbuffer(struct drm_device *dev, void *data,
3223 struct drm_file *file_priv)
3225 drm_i915_private_t *dev_priv = dev->dev_private;
3226 struct drm_i915_gem_execbuffer *args = data;
3227 struct drm_i915_gem_exec_object *exec_list = NULL;
3228 struct drm_gem_object **object_list = NULL;
3229 struct drm_gem_object *batch_obj;
3230 struct drm_i915_gem_object *obj_priv;
3231 struct drm_clip_rect *cliprects = NULL;
3232 struct drm_i915_gem_relocation_entry *relocs;
3233 int ret, ret2, i, pinned = 0;
3234 uint64_t exec_offset;
3235 uint32_t seqno, flush_domains, reloc_index;
3239 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3240 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3243 if (args->buffer_count < 1) {
3244 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3247 /* Copy in the exec list from userland */
3248 exec_list = drm_calloc_large(sizeof(*exec_list), args->buffer_count);
3249 object_list = drm_calloc_large(sizeof(*object_list), args->buffer_count);
3250 if (exec_list == NULL || object_list == NULL) {
3251 DRM_ERROR("Failed to allocate exec or object list "
3253 args->buffer_count);
3257 ret = copy_from_user(exec_list,
3258 (struct drm_i915_relocation_entry __user *)
3259 (uintptr_t) args->buffers_ptr,
3260 sizeof(*exec_list) * args->buffer_count);
3262 DRM_ERROR("copy %d exec entries failed %d\n",
3263 args->buffer_count, ret);
3267 if (args->num_cliprects != 0) {
3268 cliprects = drm_calloc(args->num_cliprects, sizeof(*cliprects),
3270 if (cliprects == NULL)
3273 ret = copy_from_user(cliprects,
3274 (struct drm_clip_rect __user *)
3275 (uintptr_t) args->cliprects_ptr,
3276 sizeof(*cliprects) * args->num_cliprects);
3278 DRM_ERROR("copy %d cliprects failed: %d\n",
3279 args->num_cliprects, ret);
3284 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3289 mutex_lock(&dev->struct_mutex);
3291 i915_verify_inactive(dev, __FILE__, __LINE__);
3293 if (dev_priv->mm.wedged) {
3294 DRM_ERROR("Execbuf while wedged\n");
3295 mutex_unlock(&dev->struct_mutex);
3300 if (dev_priv->mm.suspended) {
3301 DRM_ERROR("Execbuf while VT-switched.\n");
3302 mutex_unlock(&dev->struct_mutex);
3307 /* Look up object handles */
3308 for (i = 0; i < args->buffer_count; i++) {
3309 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3310 exec_list[i].handle);
3311 if (object_list[i] == NULL) {
3312 DRM_ERROR("Invalid object handle %d at index %d\n",
3313 exec_list[i].handle, i);
3318 obj_priv = object_list[i]->driver_private;
3319 if (obj_priv->in_execbuffer) {
3320 DRM_ERROR("Object %p appears more than once in object list\n",
3325 obj_priv->in_execbuffer = true;
3328 /* Pin and relocate */
3329 for (pin_tries = 0; ; pin_tries++) {
3333 for (i = 0; i < args->buffer_count; i++) {
3334 object_list[i]->pending_read_domains = 0;
3335 object_list[i]->pending_write_domain = 0;
3336 ret = i915_gem_object_pin_and_relocate(object_list[i],
3339 &relocs[reloc_index]);
3343 reloc_index += exec_list[i].relocation_count;
3349 /* error other than GTT full, or we've already tried again */
3350 if (ret != -ENOSPC || pin_tries >= 1) {
3351 if (ret != -ERESTARTSYS)
3352 DRM_ERROR("Failed to pin buffers %d\n", ret);
3356 /* unpin all of our buffers */
3357 for (i = 0; i < pinned; i++)
3358 i915_gem_object_unpin(object_list[i]);
3361 /* evict everyone we can from the aperture */
3362 ret = i915_gem_evict_everything(dev);
3367 /* Set the pending read domains for the batch buffer to COMMAND */
3368 batch_obj = object_list[args->buffer_count-1];
3369 if (batch_obj->pending_write_domain) {
3370 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3374 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
3376 /* Sanity check the batch buffer, prior to moving objects */
3377 exec_offset = exec_list[args->buffer_count - 1].offset;
3378 ret = i915_gem_check_execbuffer (args, exec_offset);
3380 DRM_ERROR("execbuf with invalid offset/length\n");
3384 i915_verify_inactive(dev, __FILE__, __LINE__);
3386 /* Zero the global flush/invalidate flags. These
3387 * will be modified as new domains are computed
3390 dev->invalidate_domains = 0;
3391 dev->flush_domains = 0;
3393 for (i = 0; i < args->buffer_count; i++) {
3394 struct drm_gem_object *obj = object_list[i];
3396 /* Compute new gpu domains and update invalidate/flush */
3397 i915_gem_object_set_to_gpu_domain(obj);
3400 i915_verify_inactive(dev, __FILE__, __LINE__);
3402 if (dev->invalidate_domains | dev->flush_domains) {
3404 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3406 dev->invalidate_domains,
3407 dev->flush_domains);
3410 dev->invalidate_domains,
3411 dev->flush_domains);
3412 if (dev->flush_domains)
3413 (void)i915_add_request(dev, file_priv,
3414 dev->flush_domains);
3417 for (i = 0; i < args->buffer_count; i++) {
3418 struct drm_gem_object *obj = object_list[i];
3420 obj->write_domain = obj->pending_write_domain;
3423 i915_verify_inactive(dev, __FILE__, __LINE__);
3426 for (i = 0; i < args->buffer_count; i++) {
3427 i915_gem_object_check_coherency(object_list[i],
3428 exec_list[i].handle);
3433 i915_gem_dump_object(batch_obj,
3439 /* Exec the batchbuffer */
3440 ret = i915_dispatch_gem_execbuffer(dev, args, cliprects, exec_offset);
3442 DRM_ERROR("dispatch failed %d\n", ret);
3447 * Ensure that the commands in the batch buffer are
3448 * finished before the interrupt fires
3450 flush_domains = i915_retire_commands(dev);
3452 i915_verify_inactive(dev, __FILE__, __LINE__);
3455 * Get a seqno representing the execution of the current buffer,
3456 * which we can wait on. We would like to mitigate these interrupts,
3457 * likely by only creating seqnos occasionally (so that we have
3458 * *some* interrupts representing completion of buffers that we can
3459 * wait on when trying to clear up gtt space).
3461 seqno = i915_add_request(dev, file_priv, flush_domains);
3463 for (i = 0; i < args->buffer_count; i++) {
3464 struct drm_gem_object *obj = object_list[i];
3466 i915_gem_object_move_to_active(obj, seqno);
3468 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3472 i915_dump_lru(dev, __func__);
3475 i915_verify_inactive(dev, __FILE__, __LINE__);
3478 for (i = 0; i < pinned; i++)
3479 i915_gem_object_unpin(object_list[i]);
3481 for (i = 0; i < args->buffer_count; i++) {
3482 if (object_list[i]) {
3483 obj_priv = object_list[i]->driver_private;
3484 obj_priv->in_execbuffer = false;
3486 drm_gem_object_unreference(object_list[i]);
3489 mutex_unlock(&dev->struct_mutex);
3492 /* Copy the new buffer offsets back to the user's exec list. */
3493 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
3494 (uintptr_t) args->buffers_ptr,
3496 sizeof(*exec_list) * args->buffer_count);
3499 DRM_ERROR("failed to copy %d exec entries "
3500 "back to user (%d)\n",
3501 args->buffer_count, ret);
3505 /* Copy the updated relocations out regardless of current error
3506 * state. Failure to update the relocs would mean that the next
3507 * time userland calls execbuf, it would do so with presumed offset
3508 * state that didn't match the actual object state.
3510 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
3513 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
3520 drm_free_large(object_list);
3521 drm_free_large(exec_list);
3522 drm_free(cliprects, sizeof(*cliprects) * args->num_cliprects,
3529 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
3531 struct drm_device *dev = obj->dev;
3532 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3535 i915_verify_inactive(dev, __FILE__, __LINE__);
3536 if (obj_priv->gtt_space == NULL) {
3537 ret = i915_gem_object_bind_to_gtt(obj, alignment);
3539 if (ret != -EBUSY && ret != -ERESTARTSYS)
3540 DRM_ERROR("Failure to bind: %d\n", ret);
3545 * Pre-965 chips need a fence register set up in order to
3546 * properly handle tiled surfaces.
3548 if (!IS_I965G(dev) &&
3549 obj_priv->fence_reg == I915_FENCE_REG_NONE &&
3550 obj_priv->tiling_mode != I915_TILING_NONE) {
3551 ret = i915_gem_object_get_fence_reg(obj);
3553 if (ret != -EBUSY && ret != -ERESTARTSYS)
3554 DRM_ERROR("Failure to install fence: %d\n",
3559 obj_priv->pin_count++;
3561 /* If the object is not active and not pending a flush,
3562 * remove it from the inactive list
3564 if (obj_priv->pin_count == 1) {
3565 atomic_inc(&dev->pin_count);
3566 atomic_add(obj->size, &dev->pin_memory);
3567 if (!obj_priv->active &&
3568 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 &&
3569 !list_empty(&obj_priv->list))
3570 list_del_init(&obj_priv->list);
3572 i915_verify_inactive(dev, __FILE__, __LINE__);
3578 i915_gem_object_unpin(struct drm_gem_object *obj)
3580 struct drm_device *dev = obj->dev;
3581 drm_i915_private_t *dev_priv = dev->dev_private;
3582 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3584 i915_verify_inactive(dev, __FILE__, __LINE__);
3585 obj_priv->pin_count--;
3586 BUG_ON(obj_priv->pin_count < 0);
3587 BUG_ON(obj_priv->gtt_space == NULL);
3589 /* If the object is no longer pinned, and is
3590 * neither active nor being flushed, then stick it on
3593 if (obj_priv->pin_count == 0) {
3594 if (!obj_priv->active &&
3595 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
3596 list_move_tail(&obj_priv->list,
3597 &dev_priv->mm.inactive_list);
3598 atomic_dec(&dev->pin_count);
3599 atomic_sub(obj->size, &dev->pin_memory);
3601 i915_verify_inactive(dev, __FILE__, __LINE__);
3605 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3606 struct drm_file *file_priv)
3608 struct drm_i915_gem_pin *args = data;
3609 struct drm_gem_object *obj;
3610 struct drm_i915_gem_object *obj_priv;
3613 mutex_lock(&dev->struct_mutex);
3615 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
3617 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
3619 mutex_unlock(&dev->struct_mutex);
3622 obj_priv = obj->driver_private;
3624 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
3625 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3627 drm_gem_object_unreference(obj);
3628 mutex_unlock(&dev->struct_mutex);
3632 obj_priv->user_pin_count++;
3633 obj_priv->pin_filp = file_priv;
3634 if (obj_priv->user_pin_count == 1) {
3635 ret = i915_gem_object_pin(obj, args->alignment);
3637 drm_gem_object_unreference(obj);
3638 mutex_unlock(&dev->struct_mutex);
3643 /* XXX - flush the CPU caches for pinned objects
3644 * as the X server doesn't manage domains yet
3646 i915_gem_object_flush_cpu_write_domain(obj);
3647 args->offset = obj_priv->gtt_offset;
3648 drm_gem_object_unreference(obj);
3649 mutex_unlock(&dev->struct_mutex);
3655 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3656 struct drm_file *file_priv)
3658 struct drm_i915_gem_pin *args = data;
3659 struct drm_gem_object *obj;
3660 struct drm_i915_gem_object *obj_priv;
3662 mutex_lock(&dev->struct_mutex);
3664 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
3666 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
3668 mutex_unlock(&dev->struct_mutex);
3672 obj_priv = obj->driver_private;
3673 if (obj_priv->pin_filp != file_priv) {
3674 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3676 drm_gem_object_unreference(obj);
3677 mutex_unlock(&dev->struct_mutex);
3680 obj_priv->user_pin_count--;
3681 if (obj_priv->user_pin_count == 0) {
3682 obj_priv->pin_filp = NULL;
3683 i915_gem_object_unpin(obj);
3686 drm_gem_object_unreference(obj);
3687 mutex_unlock(&dev->struct_mutex);
3692 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3693 struct drm_file *file_priv)
3695 struct drm_i915_gem_busy *args = data;
3696 struct drm_gem_object *obj;
3697 struct drm_i915_gem_object *obj_priv;
3699 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
3701 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
3706 mutex_lock(&dev->struct_mutex);
3707 /* Update the active list for the hardware's current position.
3708 * Otherwise this only updates on a delayed timer or when irqs are
3709 * actually unmasked, and our working set ends up being larger than
3712 i915_gem_retire_requests(dev);
3714 obj_priv = obj->driver_private;
3715 /* Don't count being on the flushing list against the object being
3716 * done. Otherwise, a buffer left on the flushing list but not getting
3717 * flushed (because nobody's flushing that domain) won't ever return
3718 * unbusy and get reused by libdrm's bo cache. The other expected
3719 * consumer of this interface, OpenGL's occlusion queries, also specs
3720 * that the objects get unbusy "eventually" without any interference.
3722 args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
3724 drm_gem_object_unreference(obj);
3725 mutex_unlock(&dev->struct_mutex);
3730 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3731 struct drm_file *file_priv)
3733 return i915_gem_ring_throttle(dev, file_priv);
3736 int i915_gem_init_object(struct drm_gem_object *obj)
3738 struct drm_i915_gem_object *obj_priv;
3740 obj_priv = drm_calloc(1, sizeof(*obj_priv), DRM_MEM_DRIVER);
3741 if (obj_priv == NULL)
3745 * We've just allocated pages from the kernel,
3746 * so they've just been written by the CPU with
3747 * zeros. They'll need to be clflushed before we
3748 * use them with the GPU.
3750 obj->write_domain = I915_GEM_DOMAIN_CPU;
3751 obj->read_domains = I915_GEM_DOMAIN_CPU;
3753 obj_priv->agp_type = AGP_USER_MEMORY;
3755 obj->driver_private = obj_priv;
3756 obj_priv->obj = obj;
3757 obj_priv->fence_reg = I915_FENCE_REG_NONE;
3758 INIT_LIST_HEAD(&obj_priv->list);
3763 void i915_gem_free_object(struct drm_gem_object *obj)
3765 struct drm_device *dev = obj->dev;
3766 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3768 while (obj_priv->pin_count > 0)
3769 i915_gem_object_unpin(obj);
3771 if (obj_priv->phys_obj)
3772 i915_gem_detach_phys_object(dev, obj);
3774 i915_gem_object_unbind(obj);
3776 i915_gem_free_mmap_offset(obj);
3778 drm_free(obj_priv->page_cpu_valid, 1, DRM_MEM_DRIVER);
3779 kfree(obj_priv->bit_17);
3780 drm_free(obj->driver_private, 1, DRM_MEM_DRIVER);
3783 /** Unbinds all objects that are on the given buffer list. */
3785 i915_gem_evict_from_list(struct drm_device *dev, struct list_head *head)
3787 struct drm_gem_object *obj;
3788 struct drm_i915_gem_object *obj_priv;
3791 while (!list_empty(head)) {
3792 obj_priv = list_first_entry(head,
3793 struct drm_i915_gem_object,
3795 obj = obj_priv->obj;
3797 if (obj_priv->pin_count != 0) {
3798 DRM_ERROR("Pinned object in unbind list\n");
3799 mutex_unlock(&dev->struct_mutex);
3803 ret = i915_gem_object_unbind(obj);
3805 DRM_ERROR("Error unbinding object in LeaveVT: %d\n",
3807 mutex_unlock(&dev->struct_mutex);
3817 i915_gem_idle(struct drm_device *dev)
3819 drm_i915_private_t *dev_priv = dev->dev_private;
3820 uint32_t seqno, cur_seqno, last_seqno;
3823 mutex_lock(&dev->struct_mutex);
3825 if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
3826 mutex_unlock(&dev->struct_mutex);
3830 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3831 * We need to replace this with a semaphore, or something.
3833 dev_priv->mm.suspended = 1;
3835 /* Cancel the retire work handler, wait for it to finish if running
3837 mutex_unlock(&dev->struct_mutex);
3838 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3839 mutex_lock(&dev->struct_mutex);
3841 i915_kernel_lost_context(dev);
3843 /* Flush the GPU along with all non-CPU write domains
3845 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
3846 seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
3849 mutex_unlock(&dev->struct_mutex);
3853 dev_priv->mm.waiting_gem_seqno = seqno;
3857 cur_seqno = i915_get_gem_seqno(dev);
3858 if (i915_seqno_passed(cur_seqno, seqno))
3860 if (last_seqno == cur_seqno) {
3861 if (stuck++ > 100) {
3862 DRM_ERROR("hardware wedged\n");
3863 dev_priv->mm.wedged = 1;
3864 DRM_WAKEUP(&dev_priv->irq_queue);
3869 last_seqno = cur_seqno;
3871 dev_priv->mm.waiting_gem_seqno = 0;
3873 i915_gem_retire_requests(dev);
3875 spin_lock(&dev_priv->mm.active_list_lock);
3876 if (!dev_priv->mm.wedged) {
3877 /* Active and flushing should now be empty as we've
3878 * waited for a sequence higher than any pending execbuffer
3880 WARN_ON(!list_empty(&dev_priv->mm.active_list));
3881 WARN_ON(!list_empty(&dev_priv->mm.flushing_list));
3882 /* Request should now be empty as we've also waited
3883 * for the last request in the list
3885 WARN_ON(!list_empty(&dev_priv->mm.request_list));
3888 /* Empty the active and flushing lists to inactive. If there's
3889 * anything left at this point, it means that we're wedged and
3890 * nothing good's going to happen by leaving them there. So strip
3891 * the GPU domains and just stuff them onto inactive.
3893 while (!list_empty(&dev_priv->mm.active_list)) {
3894 struct drm_i915_gem_object *obj_priv;
3896 obj_priv = list_first_entry(&dev_priv->mm.active_list,
3897 struct drm_i915_gem_object,
3899 obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
3900 i915_gem_object_move_to_inactive(obj_priv->obj);
3902 spin_unlock(&dev_priv->mm.active_list_lock);
3904 while (!list_empty(&dev_priv->mm.flushing_list)) {
3905 struct drm_i915_gem_object *obj_priv;
3907 obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
3908 struct drm_i915_gem_object,
3910 obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
3911 i915_gem_object_move_to_inactive(obj_priv->obj);
3915 /* Move all inactive buffers out of the GTT. */
3916 ret = i915_gem_evict_from_list(dev, &dev_priv->mm.inactive_list);
3917 WARN_ON(!list_empty(&dev_priv->mm.inactive_list));
3919 mutex_unlock(&dev->struct_mutex);
3923 i915_gem_cleanup_ringbuffer(dev);
3924 mutex_unlock(&dev->struct_mutex);
3930 i915_gem_init_hws(struct drm_device *dev)
3932 drm_i915_private_t *dev_priv = dev->dev_private;
3933 struct drm_gem_object *obj;
3934 struct drm_i915_gem_object *obj_priv;
3937 /* If we need a physical address for the status page, it's already
3938 * initialized at driver load time.
3940 if (!I915_NEED_GFX_HWS(dev))
3943 obj = drm_gem_object_alloc(dev, 4096);
3945 DRM_ERROR("Failed to allocate status page\n");
3948 obj_priv = obj->driver_private;
3949 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
3951 ret = i915_gem_object_pin(obj, 4096);
3953 drm_gem_object_unreference(obj);
3957 dev_priv->status_gfx_addr = obj_priv->gtt_offset;
3959 dev_priv->hw_status_page = kmap(obj_priv->pages[0]);
3960 if (dev_priv->hw_status_page == NULL) {
3961 DRM_ERROR("Failed to map status page.\n");
3962 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
3963 i915_gem_object_unpin(obj);
3964 drm_gem_object_unreference(obj);
3967 dev_priv->hws_obj = obj;
3968 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
3969 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
3970 I915_READ(HWS_PGA); /* posting read */
3971 DRM_DEBUG("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
3977 i915_gem_cleanup_hws(struct drm_device *dev)
3979 drm_i915_private_t *dev_priv = dev->dev_private;
3980 struct drm_gem_object *obj;
3981 struct drm_i915_gem_object *obj_priv;
3983 if (dev_priv->hws_obj == NULL)
3986 obj = dev_priv->hws_obj;
3987 obj_priv = obj->driver_private;
3989 kunmap(obj_priv->pages[0]);
3990 i915_gem_object_unpin(obj);
3991 drm_gem_object_unreference(obj);
3992 dev_priv->hws_obj = NULL;
3994 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
3995 dev_priv->hw_status_page = NULL;
3997 /* Write high address into HWS_PGA when disabling. */
3998 I915_WRITE(HWS_PGA, 0x1ffff000);
4002 i915_gem_init_ringbuffer(struct drm_device *dev)
4004 drm_i915_private_t *dev_priv = dev->dev_private;
4005 struct drm_gem_object *obj;
4006 struct drm_i915_gem_object *obj_priv;
4007 drm_i915_ring_buffer_t *ring = &dev_priv->ring;
4011 ret = i915_gem_init_hws(dev);
4015 obj = drm_gem_object_alloc(dev, 128 * 1024);
4017 DRM_ERROR("Failed to allocate ringbuffer\n");
4018 i915_gem_cleanup_hws(dev);
4021 obj_priv = obj->driver_private;
4023 ret = i915_gem_object_pin(obj, 4096);
4025 drm_gem_object_unreference(obj);
4026 i915_gem_cleanup_hws(dev);
4030 /* Set up the kernel mapping for the ring. */
4031 ring->Size = obj->size;
4032 ring->tail_mask = obj->size - 1;
4034 ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
4035 ring->map.size = obj->size;
4037 ring->map.flags = 0;
4040 drm_core_ioremap_wc(&ring->map, dev);
4041 if (ring->map.handle == NULL) {
4042 DRM_ERROR("Failed to map ringbuffer.\n");
4043 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4044 i915_gem_object_unpin(obj);
4045 drm_gem_object_unreference(obj);
4046 i915_gem_cleanup_hws(dev);
4049 ring->ring_obj = obj;
4050 ring->virtual_start = ring->map.handle;
4052 /* Stop the ring if it's running. */
4053 I915_WRITE(PRB0_CTL, 0);
4054 I915_WRITE(PRB0_TAIL, 0);
4055 I915_WRITE(PRB0_HEAD, 0);
4057 /* Initialize the ring. */
4058 I915_WRITE(PRB0_START, obj_priv->gtt_offset);
4059 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4061 /* G45 ring initialization fails to reset head to zero */
4063 DRM_ERROR("Ring head not reset to zero "
4064 "ctl %08x head %08x tail %08x start %08x\n",
4065 I915_READ(PRB0_CTL),
4066 I915_READ(PRB0_HEAD),
4067 I915_READ(PRB0_TAIL),
4068 I915_READ(PRB0_START));
4069 I915_WRITE(PRB0_HEAD, 0);
4071 DRM_ERROR("Ring head forced to zero "
4072 "ctl %08x head %08x tail %08x start %08x\n",
4073 I915_READ(PRB0_CTL),
4074 I915_READ(PRB0_HEAD),
4075 I915_READ(PRB0_TAIL),
4076 I915_READ(PRB0_START));
4079 I915_WRITE(PRB0_CTL,
4080 ((obj->size - 4096) & RING_NR_PAGES) |
4084 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4086 /* If the head is still not zero, the ring is dead */
4088 DRM_ERROR("Ring initialization failed "
4089 "ctl %08x head %08x tail %08x start %08x\n",
4090 I915_READ(PRB0_CTL),
4091 I915_READ(PRB0_HEAD),
4092 I915_READ(PRB0_TAIL),
4093 I915_READ(PRB0_START));
4097 /* Update our cache of the ring state */
4098 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4099 i915_kernel_lost_context(dev);
4101 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4102 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
4103 ring->space = ring->head - (ring->tail + 8);
4104 if (ring->space < 0)
4105 ring->space += ring->Size;
4112 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4114 drm_i915_private_t *dev_priv = dev->dev_private;
4116 if (dev_priv->ring.ring_obj == NULL)
4119 drm_core_ioremapfree(&dev_priv->ring.map, dev);
4121 i915_gem_object_unpin(dev_priv->ring.ring_obj);
4122 drm_gem_object_unreference(dev_priv->ring.ring_obj);
4123 dev_priv->ring.ring_obj = NULL;
4124 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4126 i915_gem_cleanup_hws(dev);
4130 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4131 struct drm_file *file_priv)
4133 drm_i915_private_t *dev_priv = dev->dev_private;
4136 if (drm_core_check_feature(dev, DRIVER_MODESET))
4139 if (dev_priv->mm.wedged) {
4140 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4141 dev_priv->mm.wedged = 0;
4144 mutex_lock(&dev->struct_mutex);
4145 dev_priv->mm.suspended = 0;
4147 ret = i915_gem_init_ringbuffer(dev);
4149 mutex_unlock(&dev->struct_mutex);
4153 spin_lock(&dev_priv->mm.active_list_lock);
4154 BUG_ON(!list_empty(&dev_priv->mm.active_list));
4155 spin_unlock(&dev_priv->mm.active_list_lock);
4157 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4158 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4159 BUG_ON(!list_empty(&dev_priv->mm.request_list));
4160 mutex_unlock(&dev->struct_mutex);
4162 drm_irq_install(dev);
4168 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4169 struct drm_file *file_priv)
4173 if (drm_core_check_feature(dev, DRIVER_MODESET))
4176 ret = i915_gem_idle(dev);
4177 drm_irq_uninstall(dev);
4183 i915_gem_lastclose(struct drm_device *dev)
4187 if (drm_core_check_feature(dev, DRIVER_MODESET))
4190 ret = i915_gem_idle(dev);
4192 DRM_ERROR("failed to idle hardware: %d\n", ret);
4196 i915_gem_load(struct drm_device *dev)
4198 drm_i915_private_t *dev_priv = dev->dev_private;
4200 spin_lock_init(&dev_priv->mm.active_list_lock);
4201 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4202 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4203 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4204 INIT_LIST_HEAD(&dev_priv->mm.request_list);
4205 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4206 i915_gem_retire_work_handler);
4207 dev_priv->mm.next_gem_seqno = 1;
4209 /* Old X drivers will take 0-2 for front, back, depth buffers */
4210 dev_priv->fence_reg_start = 3;
4212 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4213 dev_priv->num_fence_regs = 16;
4215 dev_priv->num_fence_regs = 8;
4217 i915_gem_detect_bit_6_swizzle(dev);
4221 * Create a physically contiguous memory object for this object
4222 * e.g. for cursor + overlay regs
4224 int i915_gem_init_phys_object(struct drm_device *dev,
4227 drm_i915_private_t *dev_priv = dev->dev_private;
4228 struct drm_i915_gem_phys_object *phys_obj;
4231 if (dev_priv->mm.phys_objs[id - 1] || !size)
4234 phys_obj = drm_calloc(1, sizeof(struct drm_i915_gem_phys_object), DRM_MEM_DRIVER);
4240 phys_obj->handle = drm_pci_alloc(dev, size, 0, 0xffffffff);
4241 if (!phys_obj->handle) {
4246 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4249 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4253 drm_free(phys_obj, sizeof(struct drm_i915_gem_phys_object), DRM_MEM_DRIVER);
4257 void i915_gem_free_phys_object(struct drm_device *dev, int id)
4259 drm_i915_private_t *dev_priv = dev->dev_private;
4260 struct drm_i915_gem_phys_object *phys_obj;
4262 if (!dev_priv->mm.phys_objs[id - 1])
4265 phys_obj = dev_priv->mm.phys_objs[id - 1];
4266 if (phys_obj->cur_obj) {
4267 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4271 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4273 drm_pci_free(dev, phys_obj->handle);
4275 dev_priv->mm.phys_objs[id - 1] = NULL;
4278 void i915_gem_free_all_phys_object(struct drm_device *dev)
4282 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4283 i915_gem_free_phys_object(dev, i);
4286 void i915_gem_detach_phys_object(struct drm_device *dev,
4287 struct drm_gem_object *obj)
4289 struct drm_i915_gem_object *obj_priv;
4294 obj_priv = obj->driver_private;
4295 if (!obj_priv->phys_obj)
4298 ret = i915_gem_object_get_pages(obj);
4302 page_count = obj->size / PAGE_SIZE;
4304 for (i = 0; i < page_count; i++) {
4305 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
4306 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4308 memcpy(dst, src, PAGE_SIZE);
4309 kunmap_atomic(dst, KM_USER0);
4311 drm_clflush_pages(obj_priv->pages, page_count);
4312 drm_agp_chipset_flush(dev);
4314 i915_gem_object_put_pages(obj);
4316 obj_priv->phys_obj->cur_obj = NULL;
4317 obj_priv->phys_obj = NULL;
4321 i915_gem_attach_phys_object(struct drm_device *dev,
4322 struct drm_gem_object *obj, int id)
4324 drm_i915_private_t *dev_priv = dev->dev_private;
4325 struct drm_i915_gem_object *obj_priv;
4330 if (id > I915_MAX_PHYS_OBJECT)
4333 obj_priv = obj->driver_private;
4335 if (obj_priv->phys_obj) {
4336 if (obj_priv->phys_obj->id == id)
4338 i915_gem_detach_phys_object(dev, obj);
4342 /* create a new object */
4343 if (!dev_priv->mm.phys_objs[id - 1]) {
4344 ret = i915_gem_init_phys_object(dev, id,
4347 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
4352 /* bind to the object */
4353 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4354 obj_priv->phys_obj->cur_obj = obj;
4356 ret = i915_gem_object_get_pages(obj);
4358 DRM_ERROR("failed to get page list\n");
4362 page_count = obj->size / PAGE_SIZE;
4364 for (i = 0; i < page_count; i++) {
4365 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
4366 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4368 memcpy(dst, src, PAGE_SIZE);
4369 kunmap_atomic(src, KM_USER0);
4372 i915_gem_object_put_pages(obj);
4380 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4381 struct drm_i915_gem_pwrite *args,
4382 struct drm_file *file_priv)
4384 struct drm_i915_gem_object *obj_priv = obj->driver_private;
4387 char __user *user_data;
4389 user_data = (char __user *) (uintptr_t) args->data_ptr;
4390 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4392 DRM_DEBUG("obj_addr %p, %lld\n", obj_addr, args->size);
4393 ret = copy_from_user(obj_addr, user_data, args->size);
4397 drm_agp_chipset_flush(dev);
4401 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
4403 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
4405 /* Clean up our request list when the client is going away, so that
4406 * later retire_requests won't dereference our soon-to-be-gone
4409 mutex_lock(&dev->struct_mutex);
4410 while (!list_empty(&i915_file_priv->mm.request_list))
4411 list_del_init(i915_file_priv->mm.request_list.next);
4412 mutex_unlock(&dev->struct_mutex);