2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
38 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
39 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
40 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
41 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
43 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
46 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
47 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
48 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
50 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
51 static int i915_gem_evict_something(struct drm_device *dev, int min_size);
52 static int i915_gem_evict_from_inactive_list(struct drm_device *dev);
53 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
54 struct drm_i915_gem_pwrite *args,
55 struct drm_file *file_priv);
57 static LIST_HEAD(shrink_list);
58 static DEFINE_SPINLOCK(shrink_list_lock);
60 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
63 drm_i915_private_t *dev_priv = dev->dev_private;
66 (start & (PAGE_SIZE - 1)) != 0 ||
67 (end & (PAGE_SIZE - 1)) != 0) {
71 drm_mm_init(&dev_priv->mm.gtt_space, start,
74 dev->gtt_total = (uint32_t) (end - start);
80 i915_gem_init_ioctl(struct drm_device *dev, void *data,
81 struct drm_file *file_priv)
83 struct drm_i915_gem_init *args = data;
86 mutex_lock(&dev->struct_mutex);
87 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
88 mutex_unlock(&dev->struct_mutex);
94 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
95 struct drm_file *file_priv)
97 struct drm_i915_gem_get_aperture *args = data;
99 if (!(dev->driver->driver_features & DRIVER_GEM))
102 args->aper_size = dev->gtt_total;
103 args->aper_available_size = (args->aper_size -
104 atomic_read(&dev->pin_memory));
111 * Creates a new mm object and returns a handle to it.
114 i915_gem_create_ioctl(struct drm_device *dev, void *data,
115 struct drm_file *file_priv)
117 struct drm_i915_gem_create *args = data;
118 struct drm_gem_object *obj;
122 args->size = roundup(args->size, PAGE_SIZE);
124 /* Allocate the new object */
125 obj = i915_gem_alloc_object(dev, args->size);
129 ret = drm_gem_handle_create(file_priv, obj, &handle);
130 drm_gem_object_handle_unreference_unlocked(obj);
135 args->handle = handle;
141 fast_shmem_read(struct page **pages,
142 loff_t page_base, int page_offset,
149 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
152 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
153 kunmap_atomic(vaddr, KM_USER0);
161 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
163 drm_i915_private_t *dev_priv = obj->dev->dev_private;
164 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
166 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
167 obj_priv->tiling_mode != I915_TILING_NONE;
171 slow_shmem_copy(struct page *dst_page,
173 struct page *src_page,
177 char *dst_vaddr, *src_vaddr;
179 dst_vaddr = kmap_atomic(dst_page, KM_USER0);
180 if (dst_vaddr == NULL)
183 src_vaddr = kmap_atomic(src_page, KM_USER1);
184 if (src_vaddr == NULL) {
185 kunmap_atomic(dst_vaddr, KM_USER0);
189 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
191 kunmap_atomic(src_vaddr, KM_USER1);
192 kunmap_atomic(dst_vaddr, KM_USER0);
198 slow_shmem_bit17_copy(struct page *gpu_page,
200 struct page *cpu_page,
205 char *gpu_vaddr, *cpu_vaddr;
207 /* Use the unswizzled path if this page isn't affected. */
208 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
210 return slow_shmem_copy(cpu_page, cpu_offset,
211 gpu_page, gpu_offset, length);
213 return slow_shmem_copy(gpu_page, gpu_offset,
214 cpu_page, cpu_offset, length);
217 gpu_vaddr = kmap_atomic(gpu_page, KM_USER0);
218 if (gpu_vaddr == NULL)
221 cpu_vaddr = kmap_atomic(cpu_page, KM_USER1);
222 if (cpu_vaddr == NULL) {
223 kunmap_atomic(gpu_vaddr, KM_USER0);
227 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
228 * XORing with the other bits (A9 for Y, A9 and A10 for X)
231 int cacheline_end = ALIGN(gpu_offset + 1, 64);
232 int this_length = min(cacheline_end - gpu_offset, length);
233 int swizzled_gpu_offset = gpu_offset ^ 64;
236 memcpy(cpu_vaddr + cpu_offset,
237 gpu_vaddr + swizzled_gpu_offset,
240 memcpy(gpu_vaddr + swizzled_gpu_offset,
241 cpu_vaddr + cpu_offset,
244 cpu_offset += this_length;
245 gpu_offset += this_length;
246 length -= this_length;
249 kunmap_atomic(cpu_vaddr, KM_USER1);
250 kunmap_atomic(gpu_vaddr, KM_USER0);
256 * This is the fast shmem pread path, which attempts to copy_from_user directly
257 * from the backing pages of the object to the user's address space. On a
258 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
261 i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
262 struct drm_i915_gem_pread *args,
263 struct drm_file *file_priv)
265 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
267 loff_t offset, page_base;
268 char __user *user_data;
269 int page_offset, page_length;
272 user_data = (char __user *) (uintptr_t) args->data_ptr;
275 mutex_lock(&dev->struct_mutex);
277 ret = i915_gem_object_get_pages(obj, 0);
281 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
286 obj_priv = to_intel_bo(obj);
287 offset = args->offset;
290 /* Operation in this page
292 * page_base = page offset within aperture
293 * page_offset = offset within page
294 * page_length = bytes to copy for this page
296 page_base = (offset & ~(PAGE_SIZE-1));
297 page_offset = offset & (PAGE_SIZE-1);
298 page_length = remain;
299 if ((page_offset + remain) > PAGE_SIZE)
300 page_length = PAGE_SIZE - page_offset;
302 ret = fast_shmem_read(obj_priv->pages,
303 page_base, page_offset,
304 user_data, page_length);
308 remain -= page_length;
309 user_data += page_length;
310 offset += page_length;
314 i915_gem_object_put_pages(obj);
316 mutex_unlock(&dev->struct_mutex);
322 i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
326 ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
328 /* If we've insufficient memory to map in the pages, attempt
329 * to make some space by throwing out some old buffers.
331 if (ret == -ENOMEM) {
332 struct drm_device *dev = obj->dev;
334 ret = i915_gem_evict_something(dev, obj->size);
338 ret = i915_gem_object_get_pages(obj, 0);
345 * This is the fallback shmem pread path, which allocates temporary storage
346 * in kernel space to copy_to_user into outside of the struct_mutex, so we
347 * can copy out of the object's backing pages while holding the struct mutex
348 * and not take page faults.
351 i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
352 struct drm_i915_gem_pread *args,
353 struct drm_file *file_priv)
355 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
356 struct mm_struct *mm = current->mm;
357 struct page **user_pages;
359 loff_t offset, pinned_pages, i;
360 loff_t first_data_page, last_data_page, num_pages;
361 int shmem_page_index, shmem_page_offset;
362 int data_page_index, data_page_offset;
365 uint64_t data_ptr = args->data_ptr;
366 int do_bit17_swizzling;
370 /* Pin the user pages containing the data. We can't fault while
371 * holding the struct mutex, yet we want to hold it while
372 * dereferencing the user data.
374 first_data_page = data_ptr / PAGE_SIZE;
375 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
376 num_pages = last_data_page - first_data_page + 1;
378 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
379 if (user_pages == NULL)
382 down_read(&mm->mmap_sem);
383 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
384 num_pages, 1, 0, user_pages, NULL);
385 up_read(&mm->mmap_sem);
386 if (pinned_pages < num_pages) {
388 goto fail_put_user_pages;
391 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
393 mutex_lock(&dev->struct_mutex);
395 ret = i915_gem_object_get_pages_or_evict(obj);
399 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
404 obj_priv = to_intel_bo(obj);
405 offset = args->offset;
408 /* Operation in this page
410 * shmem_page_index = page number within shmem file
411 * shmem_page_offset = offset within page in shmem file
412 * data_page_index = page number in get_user_pages return
413 * data_page_offset = offset with data_page_index page.
414 * page_length = bytes to copy for this page
416 shmem_page_index = offset / PAGE_SIZE;
417 shmem_page_offset = offset & ~PAGE_MASK;
418 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
419 data_page_offset = data_ptr & ~PAGE_MASK;
421 page_length = remain;
422 if ((shmem_page_offset + page_length) > PAGE_SIZE)
423 page_length = PAGE_SIZE - shmem_page_offset;
424 if ((data_page_offset + page_length) > PAGE_SIZE)
425 page_length = PAGE_SIZE - data_page_offset;
427 if (do_bit17_swizzling) {
428 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
430 user_pages[data_page_index],
435 ret = slow_shmem_copy(user_pages[data_page_index],
437 obj_priv->pages[shmem_page_index],
444 remain -= page_length;
445 data_ptr += page_length;
446 offset += page_length;
450 i915_gem_object_put_pages(obj);
452 mutex_unlock(&dev->struct_mutex);
454 for (i = 0; i < pinned_pages; i++) {
455 SetPageDirty(user_pages[i]);
456 page_cache_release(user_pages[i]);
458 drm_free_large(user_pages);
464 * Reads data from the object referenced by handle.
466 * On error, the contents of *data are undefined.
469 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
470 struct drm_file *file_priv)
472 struct drm_i915_gem_pread *args = data;
473 struct drm_gem_object *obj;
474 struct drm_i915_gem_object *obj_priv;
477 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
480 obj_priv = to_intel_bo(obj);
482 /* Bounds check source.
484 * XXX: This could use review for overflow issues...
486 if (args->offset > obj->size || args->size > obj->size ||
487 args->offset + args->size > obj->size) {
488 drm_gem_object_unreference_unlocked(obj);
492 if (i915_gem_object_needs_bit17_swizzle(obj)) {
493 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
495 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
497 ret = i915_gem_shmem_pread_slow(dev, obj, args,
501 drm_gem_object_unreference_unlocked(obj);
506 /* This is the fast write path which cannot handle
507 * page faults in the source data
511 fast_user_write(struct io_mapping *mapping,
512 loff_t page_base, int page_offset,
513 char __user *user_data,
517 unsigned long unwritten;
519 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
520 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
522 io_mapping_unmap_atomic(vaddr_atomic);
528 /* Here's the write path which can sleep for
533 slow_kernel_write(struct io_mapping *mapping,
534 loff_t gtt_base, int gtt_offset,
535 struct page *user_page, int user_offset,
538 char *src_vaddr, *dst_vaddr;
539 unsigned long unwritten;
541 dst_vaddr = io_mapping_map_atomic_wc(mapping, gtt_base);
542 src_vaddr = kmap_atomic(user_page, KM_USER1);
543 unwritten = __copy_from_user_inatomic_nocache(dst_vaddr + gtt_offset,
544 src_vaddr + user_offset,
546 kunmap_atomic(src_vaddr, KM_USER1);
547 io_mapping_unmap_atomic(dst_vaddr);
554 fast_shmem_write(struct page **pages,
555 loff_t page_base, int page_offset,
560 unsigned long unwritten;
562 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
565 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
566 kunmap_atomic(vaddr, KM_USER0);
574 * This is the fast pwrite path, where we copy the data directly from the
575 * user into the GTT, uncached.
578 i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
579 struct drm_i915_gem_pwrite *args,
580 struct drm_file *file_priv)
582 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
583 drm_i915_private_t *dev_priv = dev->dev_private;
585 loff_t offset, page_base;
586 char __user *user_data;
587 int page_offset, page_length;
590 user_data = (char __user *) (uintptr_t) args->data_ptr;
592 if (!access_ok(VERIFY_READ, user_data, remain))
596 mutex_lock(&dev->struct_mutex);
597 ret = i915_gem_object_pin(obj, 0);
599 mutex_unlock(&dev->struct_mutex);
602 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
606 obj_priv = to_intel_bo(obj);
607 offset = obj_priv->gtt_offset + args->offset;
610 /* Operation in this page
612 * page_base = page offset within aperture
613 * page_offset = offset within page
614 * page_length = bytes to copy for this page
616 page_base = (offset & ~(PAGE_SIZE-1));
617 page_offset = offset & (PAGE_SIZE-1);
618 page_length = remain;
619 if ((page_offset + remain) > PAGE_SIZE)
620 page_length = PAGE_SIZE - page_offset;
622 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
623 page_offset, user_data, page_length);
625 /* If we get a fault while copying data, then (presumably) our
626 * source page isn't available. Return the error and we'll
627 * retry in the slow path.
632 remain -= page_length;
633 user_data += page_length;
634 offset += page_length;
638 i915_gem_object_unpin(obj);
639 mutex_unlock(&dev->struct_mutex);
645 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
646 * the memory and maps it using kmap_atomic for copying.
648 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
649 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
652 i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
653 struct drm_i915_gem_pwrite *args,
654 struct drm_file *file_priv)
656 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
657 drm_i915_private_t *dev_priv = dev->dev_private;
659 loff_t gtt_page_base, offset;
660 loff_t first_data_page, last_data_page, num_pages;
661 loff_t pinned_pages, i;
662 struct page **user_pages;
663 struct mm_struct *mm = current->mm;
664 int gtt_page_offset, data_page_offset, data_page_index, page_length;
666 uint64_t data_ptr = args->data_ptr;
670 /* Pin the user pages containing the data. We can't fault while
671 * holding the struct mutex, and all of the pwrite implementations
672 * want to hold it while dereferencing the user data.
674 first_data_page = data_ptr / PAGE_SIZE;
675 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
676 num_pages = last_data_page - first_data_page + 1;
678 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
679 if (user_pages == NULL)
682 down_read(&mm->mmap_sem);
683 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
684 num_pages, 0, 0, user_pages, NULL);
685 up_read(&mm->mmap_sem);
686 if (pinned_pages < num_pages) {
688 goto out_unpin_pages;
691 mutex_lock(&dev->struct_mutex);
692 ret = i915_gem_object_pin(obj, 0);
696 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
698 goto out_unpin_object;
700 obj_priv = to_intel_bo(obj);
701 offset = obj_priv->gtt_offset + args->offset;
704 /* Operation in this page
706 * gtt_page_base = page offset within aperture
707 * gtt_page_offset = offset within page in aperture
708 * data_page_index = page number in get_user_pages return
709 * data_page_offset = offset with data_page_index page.
710 * page_length = bytes to copy for this page
712 gtt_page_base = offset & PAGE_MASK;
713 gtt_page_offset = offset & ~PAGE_MASK;
714 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
715 data_page_offset = data_ptr & ~PAGE_MASK;
717 page_length = remain;
718 if ((gtt_page_offset + page_length) > PAGE_SIZE)
719 page_length = PAGE_SIZE - gtt_page_offset;
720 if ((data_page_offset + page_length) > PAGE_SIZE)
721 page_length = PAGE_SIZE - data_page_offset;
723 ret = slow_kernel_write(dev_priv->mm.gtt_mapping,
724 gtt_page_base, gtt_page_offset,
725 user_pages[data_page_index],
729 /* If we get a fault while copying data, then (presumably) our
730 * source page isn't available. Return the error and we'll
731 * retry in the slow path.
734 goto out_unpin_object;
736 remain -= page_length;
737 offset += page_length;
738 data_ptr += page_length;
742 i915_gem_object_unpin(obj);
744 mutex_unlock(&dev->struct_mutex);
746 for (i = 0; i < pinned_pages; i++)
747 page_cache_release(user_pages[i]);
748 drm_free_large(user_pages);
754 * This is the fast shmem pwrite path, which attempts to directly
755 * copy_from_user into the kmapped pages backing the object.
758 i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
759 struct drm_i915_gem_pwrite *args,
760 struct drm_file *file_priv)
762 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
764 loff_t offset, page_base;
765 char __user *user_data;
766 int page_offset, page_length;
769 user_data = (char __user *) (uintptr_t) args->data_ptr;
772 mutex_lock(&dev->struct_mutex);
774 ret = i915_gem_object_get_pages(obj, 0);
778 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
782 obj_priv = to_intel_bo(obj);
783 offset = args->offset;
787 /* Operation in this page
789 * page_base = page offset within aperture
790 * page_offset = offset within page
791 * page_length = bytes to copy for this page
793 page_base = (offset & ~(PAGE_SIZE-1));
794 page_offset = offset & (PAGE_SIZE-1);
795 page_length = remain;
796 if ((page_offset + remain) > PAGE_SIZE)
797 page_length = PAGE_SIZE - page_offset;
799 ret = fast_shmem_write(obj_priv->pages,
800 page_base, page_offset,
801 user_data, page_length);
805 remain -= page_length;
806 user_data += page_length;
807 offset += page_length;
811 i915_gem_object_put_pages(obj);
813 mutex_unlock(&dev->struct_mutex);
819 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
820 * the memory and maps it using kmap_atomic for copying.
822 * This avoids taking mmap_sem for faulting on the user's address while the
823 * struct_mutex is held.
826 i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
827 struct drm_i915_gem_pwrite *args,
828 struct drm_file *file_priv)
830 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
831 struct mm_struct *mm = current->mm;
832 struct page **user_pages;
834 loff_t offset, pinned_pages, i;
835 loff_t first_data_page, last_data_page, num_pages;
836 int shmem_page_index, shmem_page_offset;
837 int data_page_index, data_page_offset;
840 uint64_t data_ptr = args->data_ptr;
841 int do_bit17_swizzling;
845 /* Pin the user pages containing the data. We can't fault while
846 * holding the struct mutex, and all of the pwrite implementations
847 * want to hold it while dereferencing the user data.
849 first_data_page = data_ptr / PAGE_SIZE;
850 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
851 num_pages = last_data_page - first_data_page + 1;
853 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
854 if (user_pages == NULL)
857 down_read(&mm->mmap_sem);
858 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
859 num_pages, 0, 0, user_pages, NULL);
860 up_read(&mm->mmap_sem);
861 if (pinned_pages < num_pages) {
863 goto fail_put_user_pages;
866 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
868 mutex_lock(&dev->struct_mutex);
870 ret = i915_gem_object_get_pages_or_evict(obj);
874 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
878 obj_priv = to_intel_bo(obj);
879 offset = args->offset;
883 /* Operation in this page
885 * shmem_page_index = page number within shmem file
886 * shmem_page_offset = offset within page in shmem file
887 * data_page_index = page number in get_user_pages return
888 * data_page_offset = offset with data_page_index page.
889 * page_length = bytes to copy for this page
891 shmem_page_index = offset / PAGE_SIZE;
892 shmem_page_offset = offset & ~PAGE_MASK;
893 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
894 data_page_offset = data_ptr & ~PAGE_MASK;
896 page_length = remain;
897 if ((shmem_page_offset + page_length) > PAGE_SIZE)
898 page_length = PAGE_SIZE - shmem_page_offset;
899 if ((data_page_offset + page_length) > PAGE_SIZE)
900 page_length = PAGE_SIZE - data_page_offset;
902 if (do_bit17_swizzling) {
903 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
905 user_pages[data_page_index],
910 ret = slow_shmem_copy(obj_priv->pages[shmem_page_index],
912 user_pages[data_page_index],
919 remain -= page_length;
920 data_ptr += page_length;
921 offset += page_length;
925 i915_gem_object_put_pages(obj);
927 mutex_unlock(&dev->struct_mutex);
929 for (i = 0; i < pinned_pages; i++)
930 page_cache_release(user_pages[i]);
931 drm_free_large(user_pages);
937 * Writes data to the object referenced by handle.
939 * On error, the contents of the buffer that were to be modified are undefined.
942 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
943 struct drm_file *file_priv)
945 struct drm_i915_gem_pwrite *args = data;
946 struct drm_gem_object *obj;
947 struct drm_i915_gem_object *obj_priv;
950 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
953 obj_priv = to_intel_bo(obj);
955 /* Bounds check destination.
957 * XXX: This could use review for overflow issues...
959 if (args->offset > obj->size || args->size > obj->size ||
960 args->offset + args->size > obj->size) {
961 drm_gem_object_unreference_unlocked(obj);
965 /* We can only do the GTT pwrite on untiled buffers, as otherwise
966 * it would end up going through the fenced access, and we'll get
967 * different detiling behavior between reading and writing.
968 * pread/pwrite currently are reading and writing from the CPU
969 * perspective, requiring manual detiling by the client.
971 if (obj_priv->phys_obj)
972 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
973 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
974 dev->gtt_total != 0 &&
975 obj->write_domain != I915_GEM_DOMAIN_CPU) {
976 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
977 if (ret == -EFAULT) {
978 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
981 } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
982 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
984 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
985 if (ret == -EFAULT) {
986 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
993 DRM_INFO("pwrite failed %d\n", ret);
996 drm_gem_object_unreference_unlocked(obj);
1002 * Called when user space prepares to use an object with the CPU, either
1003 * through the mmap ioctl's mapping or a GTT mapping.
1006 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1007 struct drm_file *file_priv)
1009 struct drm_i915_private *dev_priv = dev->dev_private;
1010 struct drm_i915_gem_set_domain *args = data;
1011 struct drm_gem_object *obj;
1012 struct drm_i915_gem_object *obj_priv;
1013 uint32_t read_domains = args->read_domains;
1014 uint32_t write_domain = args->write_domain;
1017 if (!(dev->driver->driver_features & DRIVER_GEM))
1020 /* Only handle setting domains to types used by the CPU. */
1021 if (write_domain & I915_GEM_GPU_DOMAINS)
1024 if (read_domains & I915_GEM_GPU_DOMAINS)
1027 /* Having something in the write domain implies it's in the read
1028 * domain, and only that read domain. Enforce that in the request.
1030 if (write_domain != 0 && read_domains != write_domain)
1033 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1036 obj_priv = to_intel_bo(obj);
1038 mutex_lock(&dev->struct_mutex);
1040 intel_mark_busy(dev, obj);
1043 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1044 obj, obj->size, read_domains, write_domain);
1046 if (read_domains & I915_GEM_DOMAIN_GTT) {
1047 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1049 /* Update the LRU on the fence for the CPU access that's
1052 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1053 struct drm_i915_fence_reg *reg =
1054 &dev_priv->fence_regs[obj_priv->fence_reg];
1055 list_move_tail(®->lru_list,
1056 &dev_priv->mm.fence_list);
1059 /* Silently promote "you're not bound, there was nothing to do"
1060 * to success, since the client was just asking us to
1061 * make sure everything was done.
1066 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1069 drm_gem_object_unreference(obj);
1070 mutex_unlock(&dev->struct_mutex);
1075 * Called when user space has done writes to this buffer
1078 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1079 struct drm_file *file_priv)
1081 struct drm_i915_gem_sw_finish *args = data;
1082 struct drm_gem_object *obj;
1083 struct drm_i915_gem_object *obj_priv;
1086 if (!(dev->driver->driver_features & DRIVER_GEM))
1089 mutex_lock(&dev->struct_mutex);
1090 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1092 mutex_unlock(&dev->struct_mutex);
1097 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1098 __func__, args->handle, obj, obj->size);
1100 obj_priv = to_intel_bo(obj);
1102 /* Pinned buffers may be scanout, so flush the cache */
1103 if (obj_priv->pin_count)
1104 i915_gem_object_flush_cpu_write_domain(obj);
1106 drm_gem_object_unreference(obj);
1107 mutex_unlock(&dev->struct_mutex);
1112 * Maps the contents of an object, returning the address it is mapped
1115 * While the mapping holds a reference on the contents of the object, it doesn't
1116 * imply a ref on the object itself.
1119 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1120 struct drm_file *file_priv)
1122 struct drm_i915_gem_mmap *args = data;
1123 struct drm_gem_object *obj;
1127 if (!(dev->driver->driver_features & DRIVER_GEM))
1130 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1134 offset = args->offset;
1136 down_write(¤t->mm->mmap_sem);
1137 addr = do_mmap(obj->filp, 0, args->size,
1138 PROT_READ | PROT_WRITE, MAP_SHARED,
1140 up_write(¤t->mm->mmap_sem);
1141 drm_gem_object_unreference_unlocked(obj);
1142 if (IS_ERR((void *)addr))
1145 args->addr_ptr = (uint64_t) addr;
1151 * i915_gem_fault - fault a page into the GTT
1152 * vma: VMA in question
1155 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1156 * from userspace. The fault handler takes care of binding the object to
1157 * the GTT (if needed), allocating and programming a fence register (again,
1158 * only if needed based on whether the old reg is still valid or the object
1159 * is tiled) and inserting a new PTE into the faulting process.
1161 * Note that the faulting process may involve evicting existing objects
1162 * from the GTT and/or fence registers to make room. So performance may
1163 * suffer if the GTT working set is large or there are few fence registers
1166 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1168 struct drm_gem_object *obj = vma->vm_private_data;
1169 struct drm_device *dev = obj->dev;
1170 struct drm_i915_private *dev_priv = dev->dev_private;
1171 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1172 pgoff_t page_offset;
1175 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1177 /* We don't use vmf->pgoff since that has the fake offset */
1178 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1181 /* Now bind it into the GTT if needed */
1182 mutex_lock(&dev->struct_mutex);
1183 if (!obj_priv->gtt_space) {
1184 ret = i915_gem_object_bind_to_gtt(obj, 0);
1188 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1190 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1195 /* Need a new fence register? */
1196 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1197 ret = i915_gem_object_get_fence_reg(obj);
1202 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1205 /* Finally, remap it using the new GTT offset */
1206 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1208 mutex_unlock(&dev->struct_mutex);
1213 return VM_FAULT_NOPAGE;
1216 return VM_FAULT_OOM;
1218 return VM_FAULT_SIGBUS;
1223 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1224 * @obj: obj in question
1226 * GEM memory mapping works by handing back to userspace a fake mmap offset
1227 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1228 * up the object based on the offset and sets up the various memory mapping
1231 * This routine allocates and attaches a fake offset for @obj.
1234 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1236 struct drm_device *dev = obj->dev;
1237 struct drm_gem_mm *mm = dev->mm_private;
1238 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1239 struct drm_map_list *list;
1240 struct drm_local_map *map;
1243 /* Set the object up for mmap'ing */
1244 list = &obj->map_list;
1245 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1250 map->type = _DRM_GEM;
1251 map->size = obj->size;
1254 /* Get a DRM GEM mmap offset allocated... */
1255 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1256 obj->size / PAGE_SIZE, 0, 0);
1257 if (!list->file_offset_node) {
1258 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1263 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1264 obj->size / PAGE_SIZE, 0);
1265 if (!list->file_offset_node) {
1270 list->hash.key = list->file_offset_node->start;
1271 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1272 DRM_ERROR("failed to add to map hash\n");
1277 /* By now we should be all set, any drm_mmap request on the offset
1278 * below will get to our mmap & fault handler */
1279 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1284 drm_mm_put_block(list->file_offset_node);
1292 * i915_gem_release_mmap - remove physical page mappings
1293 * @obj: obj in question
1295 * Preserve the reservation of the mmapping with the DRM core code, but
1296 * relinquish ownership of the pages back to the system.
1298 * It is vital that we remove the page mapping if we have mapped a tiled
1299 * object through the GTT and then lose the fence register due to
1300 * resource pressure. Similarly if the object has been moved out of the
1301 * aperture, than pages mapped into userspace must be revoked. Removing the
1302 * mapping will then trigger a page fault on the next user access, allowing
1303 * fixup by i915_gem_fault().
1306 i915_gem_release_mmap(struct drm_gem_object *obj)
1308 struct drm_device *dev = obj->dev;
1309 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1311 if (dev->dev_mapping)
1312 unmap_mapping_range(dev->dev_mapping,
1313 obj_priv->mmap_offset, obj->size, 1);
1317 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1319 struct drm_device *dev = obj->dev;
1320 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1321 struct drm_gem_mm *mm = dev->mm_private;
1322 struct drm_map_list *list;
1324 list = &obj->map_list;
1325 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1327 if (list->file_offset_node) {
1328 drm_mm_put_block(list->file_offset_node);
1329 list->file_offset_node = NULL;
1337 obj_priv->mmap_offset = 0;
1341 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1342 * @obj: object to check
1344 * Return the required GTT alignment for an object, taking into account
1345 * potential fence register mapping if needed.
1348 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1350 struct drm_device *dev = obj->dev;
1351 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1355 * Minimum alignment is 4k (GTT page size), but might be greater
1356 * if a fence register is needed for the object.
1358 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1362 * Previous chips need to be aligned to the size of the smallest
1363 * fence register that can contain the object.
1370 for (i = start; i < obj->size; i <<= 1)
1377 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1379 * @data: GTT mapping ioctl data
1380 * @file_priv: GEM object info
1382 * Simply returns the fake offset to userspace so it can mmap it.
1383 * The mmap call will end up in drm_gem_mmap(), which will set things
1384 * up so we can get faults in the handler above.
1386 * The fault handler will take care of binding the object into the GTT
1387 * (since it may have been evicted to make room for something), allocating
1388 * a fence register, and mapping the appropriate aperture address into
1392 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1393 struct drm_file *file_priv)
1395 struct drm_i915_gem_mmap_gtt *args = data;
1396 struct drm_i915_private *dev_priv = dev->dev_private;
1397 struct drm_gem_object *obj;
1398 struct drm_i915_gem_object *obj_priv;
1401 if (!(dev->driver->driver_features & DRIVER_GEM))
1404 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1408 mutex_lock(&dev->struct_mutex);
1410 obj_priv = to_intel_bo(obj);
1412 if (obj_priv->madv != I915_MADV_WILLNEED) {
1413 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1414 drm_gem_object_unreference(obj);
1415 mutex_unlock(&dev->struct_mutex);
1420 if (!obj_priv->mmap_offset) {
1421 ret = i915_gem_create_mmap_offset(obj);
1423 drm_gem_object_unreference(obj);
1424 mutex_unlock(&dev->struct_mutex);
1429 args->offset = obj_priv->mmap_offset;
1432 * Pull it into the GTT so that we have a page list (makes the
1433 * initial fault faster and any subsequent flushing possible).
1435 if (!obj_priv->agp_mem) {
1436 ret = i915_gem_object_bind_to_gtt(obj, 0);
1438 drm_gem_object_unreference(obj);
1439 mutex_unlock(&dev->struct_mutex);
1442 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1445 drm_gem_object_unreference(obj);
1446 mutex_unlock(&dev->struct_mutex);
1452 i915_gem_object_put_pages(struct drm_gem_object *obj)
1454 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1455 int page_count = obj->size / PAGE_SIZE;
1458 BUG_ON(obj_priv->pages_refcount == 0);
1459 BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
1461 if (--obj_priv->pages_refcount != 0)
1464 if (obj_priv->tiling_mode != I915_TILING_NONE)
1465 i915_gem_object_save_bit_17_swizzle(obj);
1467 if (obj_priv->madv == I915_MADV_DONTNEED)
1468 obj_priv->dirty = 0;
1470 for (i = 0; i < page_count; i++) {
1471 if (obj_priv->dirty)
1472 set_page_dirty(obj_priv->pages[i]);
1474 if (obj_priv->madv == I915_MADV_WILLNEED)
1475 mark_page_accessed(obj_priv->pages[i]);
1477 page_cache_release(obj_priv->pages[i]);
1479 obj_priv->dirty = 0;
1481 drm_free_large(obj_priv->pages);
1482 obj_priv->pages = NULL;
1486 i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno,
1487 struct intel_ring_buffer *ring)
1489 struct drm_device *dev = obj->dev;
1490 drm_i915_private_t *dev_priv = dev->dev_private;
1491 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1492 BUG_ON(ring == NULL);
1493 obj_priv->ring = ring;
1495 /* Add a reference if we're newly entering the active list. */
1496 if (!obj_priv->active) {
1497 drm_gem_object_reference(obj);
1498 obj_priv->active = 1;
1500 /* Move from whatever list we were on to the tail of execution. */
1501 spin_lock(&dev_priv->mm.active_list_lock);
1502 list_move_tail(&obj_priv->list, &ring->active_list);
1503 spin_unlock(&dev_priv->mm.active_list_lock);
1504 obj_priv->last_rendering_seqno = seqno;
1508 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1510 struct drm_device *dev = obj->dev;
1511 drm_i915_private_t *dev_priv = dev->dev_private;
1512 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1514 BUG_ON(!obj_priv->active);
1515 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1516 obj_priv->last_rendering_seqno = 0;
1519 /* Immediately discard the backing storage */
1521 i915_gem_object_truncate(struct drm_gem_object *obj)
1523 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1524 struct inode *inode;
1526 inode = obj->filp->f_path.dentry->d_inode;
1527 if (inode->i_op->truncate)
1528 inode->i_op->truncate (inode);
1530 obj_priv->madv = __I915_MADV_PURGED;
1534 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1536 return obj_priv->madv == I915_MADV_DONTNEED;
1540 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1542 struct drm_device *dev = obj->dev;
1543 drm_i915_private_t *dev_priv = dev->dev_private;
1544 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1546 i915_verify_inactive(dev, __FILE__, __LINE__);
1547 if (obj_priv->pin_count != 0)
1548 list_del_init(&obj_priv->list);
1550 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1552 BUG_ON(!list_empty(&obj_priv->gpu_write_list));
1554 obj_priv->last_rendering_seqno = 0;
1555 obj_priv->ring = NULL;
1556 if (obj_priv->active) {
1557 obj_priv->active = 0;
1558 drm_gem_object_unreference(obj);
1560 i915_verify_inactive(dev, __FILE__, __LINE__);
1564 i915_gem_process_flushing_list(struct drm_device *dev,
1565 uint32_t flush_domains, uint32_t seqno,
1566 struct intel_ring_buffer *ring)
1568 drm_i915_private_t *dev_priv = dev->dev_private;
1569 struct drm_i915_gem_object *obj_priv, *next;
1571 list_for_each_entry_safe(obj_priv, next,
1572 &dev_priv->mm.gpu_write_list,
1574 struct drm_gem_object *obj = &obj_priv->base;
1576 if ((obj->write_domain & flush_domains) ==
1577 obj->write_domain &&
1578 obj_priv->ring->ring_flag == ring->ring_flag) {
1579 uint32_t old_write_domain = obj->write_domain;
1581 obj->write_domain = 0;
1582 list_del_init(&obj_priv->gpu_write_list);
1583 i915_gem_object_move_to_active(obj, seqno, ring);
1585 /* update the fence lru list */
1586 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1587 struct drm_i915_fence_reg *reg =
1588 &dev_priv->fence_regs[obj_priv->fence_reg];
1589 list_move_tail(®->lru_list,
1590 &dev_priv->mm.fence_list);
1593 trace_i915_gem_object_change_domain(obj,
1601 i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1602 uint32_t flush_domains, struct intel_ring_buffer *ring)
1604 drm_i915_private_t *dev_priv = dev->dev_private;
1605 struct drm_i915_file_private *i915_file_priv = NULL;
1606 struct drm_i915_gem_request *request;
1610 if (file_priv != NULL)
1611 i915_file_priv = file_priv->driver_priv;
1613 request = kzalloc(sizeof(*request), GFP_KERNEL);
1614 if (request == NULL)
1617 seqno = ring->add_request(dev, ring, file_priv, flush_domains);
1619 request->seqno = seqno;
1620 request->ring = ring;
1621 request->emitted_jiffies = jiffies;
1622 was_empty = list_empty(&ring->request_list);
1623 list_add_tail(&request->list, &ring->request_list);
1625 if (i915_file_priv) {
1626 list_add_tail(&request->client_list,
1627 &i915_file_priv->mm.request_list);
1629 INIT_LIST_HEAD(&request->client_list);
1632 /* Associate any objects on the flushing list matching the write
1633 * domain we're flushing with our flush.
1635 if (flush_domains != 0)
1636 i915_gem_process_flushing_list(dev, flush_domains, seqno, ring);
1638 if (!dev_priv->mm.suspended) {
1639 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1641 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1647 * Command execution barrier
1649 * Ensures that all commands in the ring are finished
1650 * before signalling the CPU
1653 i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring)
1655 uint32_t flush_domains = 0;
1657 /* The sampler always gets flushed on i965 (sigh) */
1659 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1661 ring->flush(dev, ring,
1662 I915_GEM_DOMAIN_COMMAND, flush_domains);
1663 return flush_domains;
1667 * Moves buffers associated only with the given active seqno from the active
1668 * to inactive list, potentially freeing them.
1671 i915_gem_retire_request(struct drm_device *dev,
1672 struct drm_i915_gem_request *request)
1674 drm_i915_private_t *dev_priv = dev->dev_private;
1676 trace_i915_gem_request_retire(dev, request->seqno);
1678 /* Move any buffers on the active list that are no longer referenced
1679 * by the ringbuffer to the flushing/inactive lists as appropriate.
1681 spin_lock(&dev_priv->mm.active_list_lock);
1682 while (!list_empty(&request->ring->active_list)) {
1683 struct drm_gem_object *obj;
1684 struct drm_i915_gem_object *obj_priv;
1686 obj_priv = list_first_entry(&request->ring->active_list,
1687 struct drm_i915_gem_object,
1689 obj = &obj_priv->base;
1691 /* If the seqno being retired doesn't match the oldest in the
1692 * list, then the oldest in the list must still be newer than
1695 if (obj_priv->last_rendering_seqno != request->seqno)
1699 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1700 __func__, request->seqno, obj);
1703 if (obj->write_domain != 0)
1704 i915_gem_object_move_to_flushing(obj);
1706 /* Take a reference on the object so it won't be
1707 * freed while the spinlock is held. The list
1708 * protection for this spinlock is safe when breaking
1709 * the lock like this since the next thing we do
1710 * is just get the head of the list again.
1712 drm_gem_object_reference(obj);
1713 i915_gem_object_move_to_inactive(obj);
1714 spin_unlock(&dev_priv->mm.active_list_lock);
1715 drm_gem_object_unreference(obj);
1716 spin_lock(&dev_priv->mm.active_list_lock);
1720 spin_unlock(&dev_priv->mm.active_list_lock);
1724 * Returns true if seq1 is later than seq2.
1727 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1729 return (int32_t)(seq1 - seq2) >= 0;
1733 i915_get_gem_seqno(struct drm_device *dev,
1734 struct intel_ring_buffer *ring)
1736 return ring->get_gem_seqno(dev, ring);
1740 * This function clears the request list as sequence numbers are passed.
1743 i915_gem_retire_requests(struct drm_device *dev,
1744 struct intel_ring_buffer *ring)
1746 drm_i915_private_t *dev_priv = dev->dev_private;
1749 if (!ring->status_page.page_addr
1750 || list_empty(&ring->request_list))
1753 seqno = i915_get_gem_seqno(dev, ring);
1755 while (!list_empty(&ring->request_list)) {
1756 struct drm_i915_gem_request *request;
1757 uint32_t retiring_seqno;
1759 request = list_first_entry(&ring->request_list,
1760 struct drm_i915_gem_request,
1762 retiring_seqno = request->seqno;
1764 if (i915_seqno_passed(seqno, retiring_seqno) ||
1765 atomic_read(&dev_priv->mm.wedged)) {
1766 i915_gem_retire_request(dev, request);
1768 list_del(&request->list);
1769 list_del(&request->client_list);
1775 if (unlikely (dev_priv->trace_irq_seqno &&
1776 i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
1778 ring->user_irq_put(dev, ring);
1779 dev_priv->trace_irq_seqno = 0;
1784 i915_gem_retire_work_handler(struct work_struct *work)
1786 drm_i915_private_t *dev_priv;
1787 struct drm_device *dev;
1789 dev_priv = container_of(work, drm_i915_private_t,
1790 mm.retire_work.work);
1791 dev = dev_priv->dev;
1793 mutex_lock(&dev->struct_mutex);
1794 i915_gem_retire_requests(dev, &dev_priv->render_ring);
1797 i915_gem_retire_requests(dev, &dev_priv->bsd_ring);
1799 if (!dev_priv->mm.suspended &&
1800 (!list_empty(&dev_priv->render_ring.request_list) ||
1802 !list_empty(&dev_priv->bsd_ring.request_list))))
1803 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1804 mutex_unlock(&dev->struct_mutex);
1808 i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
1809 int interruptible, struct intel_ring_buffer *ring)
1811 drm_i915_private_t *dev_priv = dev->dev_private;
1817 if (atomic_read(&dev_priv->mm.wedged))
1820 if (!i915_seqno_passed(ring->get_gem_seqno(dev, ring), seqno)) {
1821 if (HAS_PCH_SPLIT(dev))
1822 ier = I915_READ(DEIER) | I915_READ(GTIER);
1824 ier = I915_READ(IER);
1826 DRM_ERROR("something (likely vbetool) disabled "
1827 "interrupts, re-enabling\n");
1828 i915_driver_irq_preinstall(dev);
1829 i915_driver_irq_postinstall(dev);
1832 trace_i915_gem_request_wait_begin(dev, seqno);
1834 ring->waiting_gem_seqno = seqno;
1835 ring->user_irq_get(dev, ring);
1837 ret = wait_event_interruptible(ring->irq_queue,
1839 ring->get_gem_seqno(dev, ring), seqno)
1840 || atomic_read(&dev_priv->mm.wedged));
1842 wait_event(ring->irq_queue,
1844 ring->get_gem_seqno(dev, ring), seqno)
1845 || atomic_read(&dev_priv->mm.wedged));
1847 ring->user_irq_put(dev, ring);
1848 ring->waiting_gem_seqno = 0;
1850 trace_i915_gem_request_wait_end(dev, seqno);
1852 if (atomic_read(&dev_priv->mm.wedged))
1855 if (ret && ret != -ERESTARTSYS)
1856 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1857 __func__, ret, seqno, ring->get_gem_seqno(dev, ring));
1859 /* Directly dispatch request retiring. While we have the work queue
1860 * to handle this, the waiter on a request often wants an associated
1861 * buffer to have made it to the inactive list, and we would need
1862 * a separate wait queue to handle that.
1865 i915_gem_retire_requests(dev, ring);
1871 * Waits for a sequence number to be signaled, and cleans up the
1872 * request and object lists appropriately for that event.
1875 i915_wait_request(struct drm_device *dev, uint32_t seqno,
1876 struct intel_ring_buffer *ring)
1878 return i915_do_wait_request(dev, seqno, 1, ring);
1882 i915_gem_flush(struct drm_device *dev,
1883 uint32_t invalidate_domains,
1884 uint32_t flush_domains)
1886 drm_i915_private_t *dev_priv = dev->dev_private;
1887 if (flush_domains & I915_GEM_DOMAIN_CPU)
1888 drm_agp_chipset_flush(dev);
1889 dev_priv->render_ring.flush(dev, &dev_priv->render_ring,
1894 dev_priv->bsd_ring.flush(dev, &dev_priv->bsd_ring,
1900 i915_gem_flush_ring(struct drm_device *dev,
1901 uint32_t invalidate_domains,
1902 uint32_t flush_domains,
1903 struct intel_ring_buffer *ring)
1905 if (flush_domains & I915_GEM_DOMAIN_CPU)
1906 drm_agp_chipset_flush(dev);
1907 ring->flush(dev, ring,
1913 * Ensures that all rendering to the object has completed and the object is
1914 * safe to unbind from the GTT or access from the CPU.
1917 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1919 struct drm_device *dev = obj->dev;
1920 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1923 /* This function only exists to support waiting for existing rendering,
1924 * not for emitting required flushes.
1926 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
1928 /* If there is rendering queued on the buffer being evicted, wait for
1931 if (obj_priv->active) {
1933 DRM_INFO("%s: object %p wait for seqno %08x\n",
1934 __func__, obj, obj_priv->last_rendering_seqno);
1936 ret = i915_wait_request(dev,
1937 obj_priv->last_rendering_seqno, obj_priv->ring);
1946 * Unbinds an object from the GTT aperture.
1949 i915_gem_object_unbind(struct drm_gem_object *obj)
1951 struct drm_device *dev = obj->dev;
1952 drm_i915_private_t *dev_priv = dev->dev_private;
1953 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1957 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1958 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1960 if (obj_priv->gtt_space == NULL)
1963 if (obj_priv->pin_count != 0) {
1964 DRM_ERROR("Attempting to unbind pinned buffer\n");
1968 /* blow away mappings if mapped through GTT */
1969 i915_gem_release_mmap(obj);
1971 /* Move the object to the CPU domain to ensure that
1972 * any possible CPU writes while it's not in the GTT
1973 * are flushed when we go to remap it. This will
1974 * also ensure that all pending GPU writes are finished
1977 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1979 if (ret != -ERESTARTSYS)
1980 DRM_ERROR("set_domain failed: %d\n", ret);
1984 BUG_ON(obj_priv->active);
1986 /* release the fence reg _after_ flushing */
1987 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
1988 i915_gem_clear_fence_reg(obj);
1990 if (obj_priv->agp_mem != NULL) {
1991 drm_unbind_agp(obj_priv->agp_mem);
1992 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
1993 obj_priv->agp_mem = NULL;
1996 i915_gem_object_put_pages(obj);
1997 BUG_ON(obj_priv->pages_refcount);
1999 if (obj_priv->gtt_space) {
2000 atomic_dec(&dev->gtt_count);
2001 atomic_sub(obj->size, &dev->gtt_memory);
2003 drm_mm_put_block(obj_priv->gtt_space);
2004 obj_priv->gtt_space = NULL;
2007 /* Remove ourselves from the LRU list if present. */
2008 spin_lock(&dev_priv->mm.active_list_lock);
2009 if (!list_empty(&obj_priv->list))
2010 list_del_init(&obj_priv->list);
2011 spin_unlock(&dev_priv->mm.active_list_lock);
2013 if (i915_gem_object_is_purgeable(obj_priv))
2014 i915_gem_object_truncate(obj);
2016 trace_i915_gem_object_unbind(obj);
2021 static struct drm_gem_object *
2022 i915_gem_find_inactive_object(struct drm_device *dev, int min_size)
2024 drm_i915_private_t *dev_priv = dev->dev_private;
2025 struct drm_i915_gem_object *obj_priv;
2026 struct drm_gem_object *best = NULL;
2027 struct drm_gem_object *first = NULL;
2029 /* Try to find the smallest clean object */
2030 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
2031 struct drm_gem_object *obj = &obj_priv->base;
2032 if (obj->size >= min_size) {
2033 if ((!obj_priv->dirty ||
2034 i915_gem_object_is_purgeable(obj_priv)) &&
2035 (!best || obj->size < best->size)) {
2037 if (best->size == min_size)
2045 return best ? best : first;
2049 i915_gpu_idle(struct drm_device *dev)
2051 drm_i915_private_t *dev_priv = dev->dev_private;
2053 uint32_t seqno1, seqno2;
2056 spin_lock(&dev_priv->mm.active_list_lock);
2057 lists_empty = (list_empty(&dev_priv->mm.flushing_list) &&
2058 list_empty(&dev_priv->render_ring.active_list) &&
2060 list_empty(&dev_priv->bsd_ring.active_list)));
2061 spin_unlock(&dev_priv->mm.active_list_lock);
2066 /* Flush everything onto the inactive list. */
2067 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2068 seqno1 = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS,
2069 &dev_priv->render_ring);
2072 ret = i915_wait_request(dev, seqno1, &dev_priv->render_ring);
2075 seqno2 = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS,
2076 &dev_priv->bsd_ring);
2080 ret = i915_wait_request(dev, seqno2, &dev_priv->bsd_ring);
2090 i915_gem_evict_everything(struct drm_device *dev)
2092 drm_i915_private_t *dev_priv = dev->dev_private;
2096 spin_lock(&dev_priv->mm.active_list_lock);
2097 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2098 list_empty(&dev_priv->mm.flushing_list) &&
2099 list_empty(&dev_priv->render_ring.active_list) &&
2101 || list_empty(&dev_priv->bsd_ring.active_list)));
2102 spin_unlock(&dev_priv->mm.active_list_lock);
2107 /* Flush everything (on to the inactive lists) and evict */
2108 ret = i915_gpu_idle(dev);
2112 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2114 ret = i915_gem_evict_from_inactive_list(dev);
2118 spin_lock(&dev_priv->mm.active_list_lock);
2119 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2120 list_empty(&dev_priv->mm.flushing_list) &&
2121 list_empty(&dev_priv->render_ring.active_list) &&
2123 || list_empty(&dev_priv->bsd_ring.active_list)));
2124 spin_unlock(&dev_priv->mm.active_list_lock);
2125 BUG_ON(!lists_empty);
2131 i915_gem_evict_something(struct drm_device *dev, int min_size)
2133 drm_i915_private_t *dev_priv = dev->dev_private;
2134 struct drm_gem_object *obj;
2137 struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
2138 struct intel_ring_buffer *bsd_ring = &dev_priv->bsd_ring;
2140 i915_gem_retire_requests(dev, render_ring);
2143 i915_gem_retire_requests(dev, bsd_ring);
2145 /* If there's an inactive buffer available now, grab it
2148 obj = i915_gem_find_inactive_object(dev, min_size);
2150 struct drm_i915_gem_object *obj_priv;
2153 DRM_INFO("%s: evicting %p\n", __func__, obj);
2155 obj_priv = to_intel_bo(obj);
2156 BUG_ON(obj_priv->pin_count != 0);
2157 BUG_ON(obj_priv->active);
2159 /* Wait on the rendering and unbind the buffer. */
2160 return i915_gem_object_unbind(obj);
2163 /* If we didn't get anything, but the ring is still processing
2164 * things, wait for the next to finish and hopefully leave us
2165 * a buffer to evict.
2167 if (!list_empty(&render_ring->request_list)) {
2168 struct drm_i915_gem_request *request;
2170 request = list_first_entry(&render_ring->request_list,
2171 struct drm_i915_gem_request,
2174 ret = i915_wait_request(dev,
2175 request->seqno, request->ring);
2182 if (HAS_BSD(dev) && !list_empty(&bsd_ring->request_list)) {
2183 struct drm_i915_gem_request *request;
2185 request = list_first_entry(&bsd_ring->request_list,
2186 struct drm_i915_gem_request,
2189 ret = i915_wait_request(dev,
2190 request->seqno, request->ring);
2197 /* If we didn't have anything on the request list but there
2198 * are buffers awaiting a flush, emit one and try again.
2199 * When we wait on it, those buffers waiting for that flush
2200 * will get moved to inactive.
2202 if (!list_empty(&dev_priv->mm.flushing_list)) {
2203 struct drm_i915_gem_object *obj_priv;
2205 /* Find an object that we can immediately reuse */
2206 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
2207 obj = &obj_priv->base;
2208 if (obj->size >= min_size)
2217 i915_gem_flush_ring(dev,
2221 seqno = i915_add_request(dev, NULL,
2230 /* If we didn't do any of the above, there's no single buffer
2231 * large enough to swap out for the new one, so just evict
2232 * everything and start again. (This should be rare.)
2234 if (!list_empty (&dev_priv->mm.inactive_list))
2235 return i915_gem_evict_from_inactive_list(dev);
2237 return i915_gem_evict_everything(dev);
2242 i915_gem_object_get_pages(struct drm_gem_object *obj,
2245 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2247 struct address_space *mapping;
2248 struct inode *inode;
2251 BUG_ON(obj_priv->pages_refcount
2252 == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT);
2254 if (obj_priv->pages_refcount++ != 0)
2257 /* Get the list of pages out of our struct file. They'll be pinned
2258 * at this point until we release them.
2260 page_count = obj->size / PAGE_SIZE;
2261 BUG_ON(obj_priv->pages != NULL);
2262 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
2263 if (obj_priv->pages == NULL) {
2264 obj_priv->pages_refcount--;
2268 inode = obj->filp->f_path.dentry->d_inode;
2269 mapping = inode->i_mapping;
2270 for (i = 0; i < page_count; i++) {
2271 page = read_cache_page_gfp(mapping, i,
2272 mapping_gfp_mask (mapping) |
2278 obj_priv->pages[i] = page;
2281 if (obj_priv->tiling_mode != I915_TILING_NONE)
2282 i915_gem_object_do_bit_17_swizzle(obj);
2288 page_cache_release(obj_priv->pages[i]);
2290 drm_free_large(obj_priv->pages);
2291 obj_priv->pages = NULL;
2292 obj_priv->pages_refcount--;
2293 return PTR_ERR(page);
2296 static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg)
2298 struct drm_gem_object *obj = reg->obj;
2299 struct drm_device *dev = obj->dev;
2300 drm_i915_private_t *dev_priv = dev->dev_private;
2301 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2302 int regnum = obj_priv->fence_reg;
2305 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2307 val |= obj_priv->gtt_offset & 0xfffff000;
2308 val |= (uint64_t)((obj_priv->stride / 128) - 1) <<
2309 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2311 if (obj_priv->tiling_mode == I915_TILING_Y)
2312 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2313 val |= I965_FENCE_REG_VALID;
2315 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val);
2318 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2320 struct drm_gem_object *obj = reg->obj;
2321 struct drm_device *dev = obj->dev;
2322 drm_i915_private_t *dev_priv = dev->dev_private;
2323 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2324 int regnum = obj_priv->fence_reg;
2327 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2329 val |= obj_priv->gtt_offset & 0xfffff000;
2330 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2331 if (obj_priv->tiling_mode == I915_TILING_Y)
2332 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2333 val |= I965_FENCE_REG_VALID;
2335 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2338 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2340 struct drm_gem_object *obj = reg->obj;
2341 struct drm_device *dev = obj->dev;
2342 drm_i915_private_t *dev_priv = dev->dev_private;
2343 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2344 int regnum = obj_priv->fence_reg;
2346 uint32_t fence_reg, val;
2349 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2350 (obj_priv->gtt_offset & (obj->size - 1))) {
2351 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2352 __func__, obj_priv->gtt_offset, obj->size);
2356 if (obj_priv->tiling_mode == I915_TILING_Y &&
2357 HAS_128_BYTE_Y_TILING(dev))
2362 /* Note: pitch better be a power of two tile widths */
2363 pitch_val = obj_priv->stride / tile_width;
2364 pitch_val = ffs(pitch_val) - 1;
2366 if (obj_priv->tiling_mode == I915_TILING_Y &&
2367 HAS_128_BYTE_Y_TILING(dev))
2368 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2370 WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL);
2372 val = obj_priv->gtt_offset;
2373 if (obj_priv->tiling_mode == I915_TILING_Y)
2374 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2375 val |= I915_FENCE_SIZE_BITS(obj->size);
2376 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2377 val |= I830_FENCE_REG_VALID;
2380 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2382 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2383 I915_WRITE(fence_reg, val);
2386 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2388 struct drm_gem_object *obj = reg->obj;
2389 struct drm_device *dev = obj->dev;
2390 drm_i915_private_t *dev_priv = dev->dev_private;
2391 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2392 int regnum = obj_priv->fence_reg;
2395 uint32_t fence_size_bits;
2397 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
2398 (obj_priv->gtt_offset & (obj->size - 1))) {
2399 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2400 __func__, obj_priv->gtt_offset);
2404 pitch_val = obj_priv->stride / 128;
2405 pitch_val = ffs(pitch_val) - 1;
2406 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2408 val = obj_priv->gtt_offset;
2409 if (obj_priv->tiling_mode == I915_TILING_Y)
2410 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2411 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2412 WARN_ON(fence_size_bits & ~0x00000f00);
2413 val |= fence_size_bits;
2414 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2415 val |= I830_FENCE_REG_VALID;
2417 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
2420 static int i915_find_fence_reg(struct drm_device *dev)
2422 struct drm_i915_fence_reg *reg = NULL;
2423 struct drm_i915_gem_object *obj_priv = NULL;
2424 struct drm_i915_private *dev_priv = dev->dev_private;
2425 struct drm_gem_object *obj = NULL;
2428 /* First try to find a free reg */
2430 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2431 reg = &dev_priv->fence_regs[i];
2435 obj_priv = to_intel_bo(reg->obj);
2436 if (!obj_priv->pin_count)
2443 /* None available, try to steal one or wait for a user to finish */
2444 i = I915_FENCE_REG_NONE;
2445 list_for_each_entry(reg, &dev_priv->mm.fence_list,
2448 obj_priv = to_intel_bo(obj);
2450 if (obj_priv->pin_count)
2454 i = obj_priv->fence_reg;
2458 BUG_ON(i == I915_FENCE_REG_NONE);
2460 /* We only have a reference on obj from the active list. put_fence_reg
2461 * might drop that one, causing a use-after-free in it. So hold a
2462 * private reference to obj like the other callers of put_fence_reg
2463 * (set_tiling ioctl) do. */
2464 drm_gem_object_reference(obj);
2465 ret = i915_gem_object_put_fence_reg(obj);
2466 drm_gem_object_unreference(obj);
2474 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2475 * @obj: object to map through a fence reg
2477 * When mapping objects through the GTT, userspace wants to be able to write
2478 * to them without having to worry about swizzling if the object is tiled.
2480 * This function walks the fence regs looking for a free one for @obj,
2481 * stealing one if it can't find any.
2483 * It then sets up the reg based on the object's properties: address, pitch
2484 * and tiling format.
2487 i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
2489 struct drm_device *dev = obj->dev;
2490 struct drm_i915_private *dev_priv = dev->dev_private;
2491 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2492 struct drm_i915_fence_reg *reg = NULL;
2495 /* Just update our place in the LRU if our fence is getting used. */
2496 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2497 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2498 list_move_tail(®->lru_list, &dev_priv->mm.fence_list);
2502 switch (obj_priv->tiling_mode) {
2503 case I915_TILING_NONE:
2504 WARN(1, "allocating a fence for non-tiled object?\n");
2507 if (!obj_priv->stride)
2509 WARN((obj_priv->stride & (512 - 1)),
2510 "object 0x%08x is X tiled but has non-512B pitch\n",
2511 obj_priv->gtt_offset);
2514 if (!obj_priv->stride)
2516 WARN((obj_priv->stride & (128 - 1)),
2517 "object 0x%08x is Y tiled but has non-128B pitch\n",
2518 obj_priv->gtt_offset);
2522 ret = i915_find_fence_reg(dev);
2526 obj_priv->fence_reg = ret;
2527 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2528 list_add_tail(®->lru_list, &dev_priv->mm.fence_list);
2533 sandybridge_write_fence_reg(reg);
2534 else if (IS_I965G(dev))
2535 i965_write_fence_reg(reg);
2536 else if (IS_I9XX(dev))
2537 i915_write_fence_reg(reg);
2539 i830_write_fence_reg(reg);
2541 trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg,
2542 obj_priv->tiling_mode);
2548 * i915_gem_clear_fence_reg - clear out fence register info
2549 * @obj: object to clear
2551 * Zeroes out the fence register itself and clears out the associated
2552 * data structures in dev_priv and obj_priv.
2555 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2557 struct drm_device *dev = obj->dev;
2558 drm_i915_private_t *dev_priv = dev->dev_private;
2559 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2560 struct drm_i915_fence_reg *reg =
2561 &dev_priv->fence_regs[obj_priv->fence_reg];
2564 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 +
2565 (obj_priv->fence_reg * 8), 0);
2566 } else if (IS_I965G(dev)) {
2567 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
2571 if (obj_priv->fence_reg < 8)
2572 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2574 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2577 I915_WRITE(fence_reg, 0);
2581 obj_priv->fence_reg = I915_FENCE_REG_NONE;
2582 list_del_init(®->lru_list);
2586 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2587 * to the buffer to finish, and then resets the fence register.
2588 * @obj: tiled object holding a fence register.
2590 * Zeroes out the fence register itself and clears out the associated
2591 * data structures in dev_priv and obj_priv.
2594 i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2596 struct drm_device *dev = obj->dev;
2597 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2599 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2602 /* If we've changed tiling, GTT-mappings of the object
2603 * need to re-fault to ensure that the correct fence register
2604 * setup is in place.
2606 i915_gem_release_mmap(obj);
2608 /* On the i915, GPU access to tiled buffers is via a fence,
2609 * therefore we must wait for any outstanding access to complete
2610 * before clearing the fence.
2612 if (!IS_I965G(dev)) {
2615 i915_gem_object_flush_gpu_write_domain(obj);
2616 ret = i915_gem_object_wait_rendering(obj);
2621 i915_gem_object_flush_gtt_write_domain(obj);
2622 i915_gem_clear_fence_reg (obj);
2628 * Finds free space in the GTT aperture and binds the object there.
2631 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2633 struct drm_device *dev = obj->dev;
2634 drm_i915_private_t *dev_priv = dev->dev_private;
2635 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2636 struct drm_mm_node *free_space;
2637 gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
2640 if (obj_priv->madv != I915_MADV_WILLNEED) {
2641 DRM_ERROR("Attempting to bind a purgeable object\n");
2646 alignment = i915_gem_get_gtt_alignment(obj);
2647 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
2648 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2652 /* If the object is bigger than the entire aperture, reject it early
2653 * before evicting everything in a vain attempt to find space.
2655 if (obj->size > dev->gtt_total) {
2656 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2661 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2662 obj->size, alignment, 0);
2663 if (free_space != NULL) {
2664 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2666 if (obj_priv->gtt_space != NULL) {
2667 obj_priv->gtt_space->private = obj;
2668 obj_priv->gtt_offset = obj_priv->gtt_space->start;
2671 if (obj_priv->gtt_space == NULL) {
2672 /* If the gtt is empty and we're still having trouble
2673 * fitting our object in, we're out of memory.
2676 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2678 ret = i915_gem_evict_something(dev, obj->size);
2686 DRM_INFO("Binding object of size %zd at 0x%08x\n",
2687 obj->size, obj_priv->gtt_offset);
2689 ret = i915_gem_object_get_pages(obj, gfpmask);
2691 drm_mm_put_block(obj_priv->gtt_space);
2692 obj_priv->gtt_space = NULL;
2694 if (ret == -ENOMEM) {
2695 /* first try to clear up some space from the GTT */
2696 ret = i915_gem_evict_something(dev, obj->size);
2698 /* now try to shrink everyone else */
2713 /* Create an AGP memory structure pointing at our pages, and bind it
2716 obj_priv->agp_mem = drm_agp_bind_pages(dev,
2718 obj->size >> PAGE_SHIFT,
2719 obj_priv->gtt_offset,
2720 obj_priv->agp_type);
2721 if (obj_priv->agp_mem == NULL) {
2722 i915_gem_object_put_pages(obj);
2723 drm_mm_put_block(obj_priv->gtt_space);
2724 obj_priv->gtt_space = NULL;
2726 ret = i915_gem_evict_something(dev, obj->size);
2732 atomic_inc(&dev->gtt_count);
2733 atomic_add(obj->size, &dev->gtt_memory);
2735 /* Assert that the object is not currently in any GPU domain. As it
2736 * wasn't in the GTT, there shouldn't be any way it could have been in
2739 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2740 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
2742 trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2748 i915_gem_clflush_object(struct drm_gem_object *obj)
2750 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2752 /* If we don't have a page list set up, then we're not pinned
2753 * to GPU, and we can ignore the cache flush because it'll happen
2754 * again at bind time.
2756 if (obj_priv->pages == NULL)
2759 trace_i915_gem_object_clflush(obj);
2761 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2764 /** Flushes any GPU write domain for the object if it's dirty. */
2766 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2768 struct drm_device *dev = obj->dev;
2769 uint32_t old_write_domain;
2770 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2772 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2775 /* Queue the GPU write cache flushing we need. */
2776 old_write_domain = obj->write_domain;
2777 i915_gem_flush(dev, 0, obj->write_domain);
2778 (void) i915_add_request(dev, NULL, obj->write_domain, obj_priv->ring);
2779 BUG_ON(obj->write_domain);
2781 trace_i915_gem_object_change_domain(obj,
2786 /** Flushes the GTT write domain for the object if it's dirty. */
2788 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2790 uint32_t old_write_domain;
2792 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2795 /* No actual flushing is required for the GTT write domain. Writes
2796 * to it immediately go to main memory as far as we know, so there's
2797 * no chipset flush. It also doesn't land in render cache.
2799 old_write_domain = obj->write_domain;
2800 obj->write_domain = 0;
2802 trace_i915_gem_object_change_domain(obj,
2807 /** Flushes the CPU write domain for the object if it's dirty. */
2809 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2811 struct drm_device *dev = obj->dev;
2812 uint32_t old_write_domain;
2814 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2817 i915_gem_clflush_object(obj);
2818 drm_agp_chipset_flush(dev);
2819 old_write_domain = obj->write_domain;
2820 obj->write_domain = 0;
2822 trace_i915_gem_object_change_domain(obj,
2828 i915_gem_object_flush_write_domain(struct drm_gem_object *obj)
2830 switch (obj->write_domain) {
2831 case I915_GEM_DOMAIN_GTT:
2832 i915_gem_object_flush_gtt_write_domain(obj);
2834 case I915_GEM_DOMAIN_CPU:
2835 i915_gem_object_flush_cpu_write_domain(obj);
2838 i915_gem_object_flush_gpu_write_domain(obj);
2844 * Moves a single object to the GTT read, and possibly write domain.
2846 * This function returns when the move is complete, including waiting on
2850 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2852 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2853 uint32_t old_write_domain, old_read_domains;
2856 /* Not valid to be called on unbound objects. */
2857 if (obj_priv->gtt_space == NULL)
2860 i915_gem_object_flush_gpu_write_domain(obj);
2861 /* Wait on any GPU rendering and flushing to occur. */
2862 ret = i915_gem_object_wait_rendering(obj);
2866 old_write_domain = obj->write_domain;
2867 old_read_domains = obj->read_domains;
2869 /* If we're writing through the GTT domain, then CPU and GPU caches
2870 * will need to be invalidated at next use.
2873 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2875 i915_gem_object_flush_cpu_write_domain(obj);
2877 /* It should now be out of any other write domains, and we can update
2878 * the domain values for our changes.
2880 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2881 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2883 obj->write_domain = I915_GEM_DOMAIN_GTT;
2884 obj_priv->dirty = 1;
2887 trace_i915_gem_object_change_domain(obj,
2895 * Prepare buffer for display plane. Use uninterruptible for possible flush
2896 * wait, as in modesetting process we're not supposed to be interrupted.
2899 i915_gem_object_set_to_display_plane(struct drm_gem_object *obj)
2901 struct drm_device *dev = obj->dev;
2902 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2903 uint32_t old_write_domain, old_read_domains;
2906 /* Not valid to be called on unbound objects. */
2907 if (obj_priv->gtt_space == NULL)
2910 i915_gem_object_flush_gpu_write_domain(obj);
2912 /* Wait on any GPU rendering and flushing to occur. */
2913 if (obj_priv->active) {
2915 DRM_INFO("%s: object %p wait for seqno %08x\n",
2916 __func__, obj, obj_priv->last_rendering_seqno);
2918 ret = i915_do_wait_request(dev,
2919 obj_priv->last_rendering_seqno,
2926 i915_gem_object_flush_cpu_write_domain(obj);
2928 old_write_domain = obj->write_domain;
2929 old_read_domains = obj->read_domains;
2931 /* It should now be out of any other write domains, and we can update
2932 * the domain values for our changes.
2934 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2935 obj->read_domains = I915_GEM_DOMAIN_GTT;
2936 obj->write_domain = I915_GEM_DOMAIN_GTT;
2937 obj_priv->dirty = 1;
2939 trace_i915_gem_object_change_domain(obj,
2947 * Moves a single object to the CPU read, and possibly write domain.
2949 * This function returns when the move is complete, including waiting on
2953 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2955 uint32_t old_write_domain, old_read_domains;
2958 i915_gem_object_flush_gpu_write_domain(obj);
2959 /* Wait on any GPU rendering and flushing to occur. */
2960 ret = i915_gem_object_wait_rendering(obj);
2964 i915_gem_object_flush_gtt_write_domain(obj);
2966 /* If we have a partially-valid cache of the object in the CPU,
2967 * finish invalidating it and free the per-page flags.
2969 i915_gem_object_set_to_full_cpu_read_domain(obj);
2971 old_write_domain = obj->write_domain;
2972 old_read_domains = obj->read_domains;
2974 /* Flush the CPU cache if it's still invalid. */
2975 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2976 i915_gem_clflush_object(obj);
2978 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2981 /* It should now be out of any other write domains, and we can update
2982 * the domain values for our changes.
2984 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2986 /* If we're writing through the CPU, then the GPU read domains will
2987 * need to be invalidated at next use.
2990 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2991 obj->write_domain = I915_GEM_DOMAIN_CPU;
2994 trace_i915_gem_object_change_domain(obj,
3002 * Set the next domain for the specified object. This
3003 * may not actually perform the necessary flushing/invaliding though,
3004 * as that may want to be batched with other set_domain operations
3006 * This is (we hope) the only really tricky part of gem. The goal
3007 * is fairly simple -- track which caches hold bits of the object
3008 * and make sure they remain coherent. A few concrete examples may
3009 * help to explain how it works. For shorthand, we use the notation
3010 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
3011 * a pair of read and write domain masks.
3013 * Case 1: the batch buffer
3019 * 5. Unmapped from GTT
3022 * Let's take these a step at a time
3025 * Pages allocated from the kernel may still have
3026 * cache contents, so we set them to (CPU, CPU) always.
3027 * 2. Written by CPU (using pwrite)
3028 * The pwrite function calls set_domain (CPU, CPU) and
3029 * this function does nothing (as nothing changes)
3031 * This function asserts that the object is not
3032 * currently in any GPU-based read or write domains
3034 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
3035 * As write_domain is zero, this function adds in the
3036 * current read domains (CPU+COMMAND, 0).
3037 * flush_domains is set to CPU.
3038 * invalidate_domains is set to COMMAND
3039 * clflush is run to get data out of the CPU caches
3040 * then i915_dev_set_domain calls i915_gem_flush to
3041 * emit an MI_FLUSH and drm_agp_chipset_flush
3042 * 5. Unmapped from GTT
3043 * i915_gem_object_unbind calls set_domain (CPU, CPU)
3044 * flush_domains and invalidate_domains end up both zero
3045 * so no flushing/invalidating happens
3049 * Case 2: The shared render buffer
3053 * 3. Read/written by GPU
3054 * 4. set_domain to (CPU,CPU)
3055 * 5. Read/written by CPU
3056 * 6. Read/written by GPU
3059 * Same as last example, (CPU, CPU)
3061 * Nothing changes (assertions find that it is not in the GPU)
3062 * 3. Read/written by GPU
3063 * execbuffer calls set_domain (RENDER, RENDER)
3064 * flush_domains gets CPU
3065 * invalidate_domains gets GPU
3067 * MI_FLUSH and drm_agp_chipset_flush
3068 * 4. set_domain (CPU, CPU)
3069 * flush_domains gets GPU
3070 * invalidate_domains gets CPU
3071 * wait_rendering (obj) to make sure all drawing is complete.
3072 * This will include an MI_FLUSH to get the data from GPU
3074 * clflush (obj) to invalidate the CPU cache
3075 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3076 * 5. Read/written by CPU
3077 * cache lines are loaded and dirtied
3078 * 6. Read written by GPU
3079 * Same as last GPU access
3081 * Case 3: The constant buffer
3086 * 4. Updated (written) by CPU again
3095 * flush_domains = CPU
3096 * invalidate_domains = RENDER
3099 * drm_agp_chipset_flush
3100 * 4. Updated (written) by CPU again
3102 * flush_domains = 0 (no previous write domain)
3103 * invalidate_domains = 0 (no new read domains)
3106 * flush_domains = CPU
3107 * invalidate_domains = RENDER
3110 * drm_agp_chipset_flush
3113 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
3115 struct drm_device *dev = obj->dev;
3116 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3117 uint32_t invalidate_domains = 0;
3118 uint32_t flush_domains = 0;
3119 uint32_t old_read_domains;
3121 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
3122 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
3124 intel_mark_busy(dev, obj);
3127 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
3129 obj->read_domains, obj->pending_read_domains,
3130 obj->write_domain, obj->pending_write_domain);
3133 * If the object isn't moving to a new write domain,
3134 * let the object stay in multiple read domains
3136 if (obj->pending_write_domain == 0)
3137 obj->pending_read_domains |= obj->read_domains;
3139 obj_priv->dirty = 1;
3142 * Flush the current write domain if
3143 * the new read domains don't match. Invalidate
3144 * any read domains which differ from the old
3147 if (obj->write_domain &&
3148 obj->write_domain != obj->pending_read_domains) {
3149 flush_domains |= obj->write_domain;
3150 invalidate_domains |=
3151 obj->pending_read_domains & ~obj->write_domain;
3154 * Invalidate any read caches which may have
3155 * stale data. That is, any new read domains.
3157 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
3158 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
3160 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3161 __func__, flush_domains, invalidate_domains);
3163 i915_gem_clflush_object(obj);
3166 old_read_domains = obj->read_domains;
3168 /* The actual obj->write_domain will be updated with
3169 * pending_write_domain after we emit the accumulated flush for all
3170 * of our domain changes in execbuffers (which clears objects'
3171 * write_domains). So if we have a current write domain that we
3172 * aren't changing, set pending_write_domain to that.
3174 if (flush_domains == 0 && obj->pending_write_domain == 0)
3175 obj->pending_write_domain = obj->write_domain;
3176 obj->read_domains = obj->pending_read_domains;
3178 dev->invalidate_domains |= invalidate_domains;
3179 dev->flush_domains |= flush_domains;
3181 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3183 obj->read_domains, obj->write_domain,
3184 dev->invalidate_domains, dev->flush_domains);
3187 trace_i915_gem_object_change_domain(obj,
3193 * Moves the object from a partially CPU read to a full one.
3195 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3196 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3199 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
3201 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3203 if (!obj_priv->page_cpu_valid)
3206 /* If we're partially in the CPU read domain, finish moving it in.
3208 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3211 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3212 if (obj_priv->page_cpu_valid[i])
3214 drm_clflush_pages(obj_priv->pages + i, 1);
3218 /* Free the page_cpu_valid mappings which are now stale, whether
3219 * or not we've got I915_GEM_DOMAIN_CPU.
3221 kfree(obj_priv->page_cpu_valid);
3222 obj_priv->page_cpu_valid = NULL;
3226 * Set the CPU read domain on a range of the object.
3228 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3229 * not entirely valid. The page_cpu_valid member of the object flags which
3230 * pages have been flushed, and will be respected by
3231 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3232 * of the whole object.
3234 * This function returns when the move is complete, including waiting on
3238 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3239 uint64_t offset, uint64_t size)
3241 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3242 uint32_t old_read_domains;
3245 if (offset == 0 && size == obj->size)
3246 return i915_gem_object_set_to_cpu_domain(obj, 0);
3248 i915_gem_object_flush_gpu_write_domain(obj);
3249 /* Wait on any GPU rendering and flushing to occur. */
3250 ret = i915_gem_object_wait_rendering(obj);
3253 i915_gem_object_flush_gtt_write_domain(obj);
3255 /* If we're already fully in the CPU read domain, we're done. */
3256 if (obj_priv->page_cpu_valid == NULL &&
3257 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3260 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3261 * newly adding I915_GEM_DOMAIN_CPU
3263 if (obj_priv->page_cpu_valid == NULL) {
3264 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3266 if (obj_priv->page_cpu_valid == NULL)
3268 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3269 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
3271 /* Flush the cache on any pages that are still invalid from the CPU's
3274 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3276 if (obj_priv->page_cpu_valid[i])
3279 drm_clflush_pages(obj_priv->pages + i, 1);
3281 obj_priv->page_cpu_valid[i] = 1;
3284 /* It should now be out of any other write domains, and we can update
3285 * the domain values for our changes.
3287 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3289 old_read_domains = obj->read_domains;
3290 obj->read_domains |= I915_GEM_DOMAIN_CPU;
3292 trace_i915_gem_object_change_domain(obj,
3300 * Pin an object to the GTT and evaluate the relocations landing in it.
3303 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3304 struct drm_file *file_priv,
3305 struct drm_i915_gem_exec_object2 *entry,
3306 struct drm_i915_gem_relocation_entry *relocs)
3308 struct drm_device *dev = obj->dev;
3309 drm_i915_private_t *dev_priv = dev->dev_private;
3310 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3312 void __iomem *reloc_page;
3315 need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
3316 obj_priv->tiling_mode != I915_TILING_NONE;
3318 /* Check fence reg constraints and rebind if necessary */
3320 !i915_gem_object_fence_offset_ok(obj,
3321 obj_priv->tiling_mode)) {
3322 ret = i915_gem_object_unbind(obj);
3327 /* Choose the GTT offset for our buffer and put it there. */
3328 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3333 * Pre-965 chips need a fence register set up in order to
3334 * properly handle blits to/from tiled surfaces.
3337 ret = i915_gem_object_get_fence_reg(obj);
3339 i915_gem_object_unpin(obj);
3344 entry->offset = obj_priv->gtt_offset;
3346 /* Apply the relocations, using the GTT aperture to avoid cache
3347 * flushing requirements.
3349 for (i = 0; i < entry->relocation_count; i++) {
3350 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
3351 struct drm_gem_object *target_obj;
3352 struct drm_i915_gem_object *target_obj_priv;
3353 uint32_t reloc_val, reloc_offset;
3354 uint32_t __iomem *reloc_entry;
3356 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
3357 reloc->target_handle);
3358 if (target_obj == NULL) {
3359 i915_gem_object_unpin(obj);
3362 target_obj_priv = to_intel_bo(target_obj);
3365 DRM_INFO("%s: obj %p offset %08x target %d "
3366 "read %08x write %08x gtt %08x "
3367 "presumed %08x delta %08x\n",
3370 (int) reloc->offset,
3371 (int) reloc->target_handle,
3372 (int) reloc->read_domains,
3373 (int) reloc->write_domain,
3374 (int) target_obj_priv->gtt_offset,
3375 (int) reloc->presumed_offset,
3379 /* The target buffer should have appeared before us in the
3380 * exec_object list, so it should have a GTT space bound by now.
3382 if (target_obj_priv->gtt_space == NULL) {
3383 DRM_ERROR("No GTT space found for object %d\n",
3384 reloc->target_handle);
3385 drm_gem_object_unreference(target_obj);
3386 i915_gem_object_unpin(obj);
3390 /* Validate that the target is in a valid r/w GPU domain */
3391 if (reloc->write_domain & (reloc->write_domain - 1)) {
3392 DRM_ERROR("reloc with multiple write domains: "
3393 "obj %p target %d offset %d "
3394 "read %08x write %08x",
3395 obj, reloc->target_handle,
3396 (int) reloc->offset,
3397 reloc->read_domains,
3398 reloc->write_domain);
3401 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3402 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
3403 DRM_ERROR("reloc with read/write CPU domains: "
3404 "obj %p target %d offset %d "
3405 "read %08x write %08x",
3406 obj, reloc->target_handle,
3407 (int) reloc->offset,
3408 reloc->read_domains,
3409 reloc->write_domain);
3410 drm_gem_object_unreference(target_obj);
3411 i915_gem_object_unpin(obj);
3414 if (reloc->write_domain && target_obj->pending_write_domain &&
3415 reloc->write_domain != target_obj->pending_write_domain) {
3416 DRM_ERROR("Write domain conflict: "
3417 "obj %p target %d offset %d "
3418 "new %08x old %08x\n",
3419 obj, reloc->target_handle,
3420 (int) reloc->offset,
3421 reloc->write_domain,
3422 target_obj->pending_write_domain);
3423 drm_gem_object_unreference(target_obj);
3424 i915_gem_object_unpin(obj);
3428 target_obj->pending_read_domains |= reloc->read_domains;
3429 target_obj->pending_write_domain |= reloc->write_domain;
3431 /* If the relocation already has the right value in it, no
3432 * more work needs to be done.
3434 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
3435 drm_gem_object_unreference(target_obj);
3439 /* Check that the relocation address is valid... */
3440 if (reloc->offset > obj->size - 4) {
3441 DRM_ERROR("Relocation beyond object bounds: "
3442 "obj %p target %d offset %d size %d.\n",
3443 obj, reloc->target_handle,
3444 (int) reloc->offset, (int) obj->size);
3445 drm_gem_object_unreference(target_obj);
3446 i915_gem_object_unpin(obj);
3449 if (reloc->offset & 3) {
3450 DRM_ERROR("Relocation not 4-byte aligned: "
3451 "obj %p target %d offset %d.\n",
3452 obj, reloc->target_handle,
3453 (int) reloc->offset);
3454 drm_gem_object_unreference(target_obj);
3455 i915_gem_object_unpin(obj);
3459 /* and points to somewhere within the target object. */
3460 if (reloc->delta >= target_obj->size) {
3461 DRM_ERROR("Relocation beyond target object bounds: "
3462 "obj %p target %d delta %d size %d.\n",
3463 obj, reloc->target_handle,
3464 (int) reloc->delta, (int) target_obj->size);
3465 drm_gem_object_unreference(target_obj);
3466 i915_gem_object_unpin(obj);
3470 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3472 drm_gem_object_unreference(target_obj);
3473 i915_gem_object_unpin(obj);
3477 /* Map the page containing the relocation we're going to
3480 reloc_offset = obj_priv->gtt_offset + reloc->offset;
3481 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3484 reloc_entry = (uint32_t __iomem *)(reloc_page +
3485 (reloc_offset & (PAGE_SIZE - 1)));
3486 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
3489 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3490 obj, (unsigned int) reloc->offset,
3491 readl(reloc_entry), reloc_val);
3493 writel(reloc_val, reloc_entry);
3494 io_mapping_unmap_atomic(reloc_page);
3496 /* The updated presumed offset for this entry will be
3497 * copied back out to the user.
3499 reloc->presumed_offset = target_obj_priv->gtt_offset;
3501 drm_gem_object_unreference(target_obj);
3506 i915_gem_dump_object(obj, 128, __func__, ~0);
3511 /* Throttle our rendering by waiting until the ring has completed our requests
3512 * emitted over 20 msec ago.
3514 * Note that if we were to use the current jiffies each time around the loop,
3515 * we wouldn't escape the function with any frames outstanding if the time to
3516 * render a frame was over 20ms.
3518 * This should get us reasonable parallelism between CPU and GPU but also
3519 * relatively low latency when blocking on a particular request to finish.
3522 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3524 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3526 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3528 mutex_lock(&dev->struct_mutex);
3529 while (!list_empty(&i915_file_priv->mm.request_list)) {
3530 struct drm_i915_gem_request *request;
3532 request = list_first_entry(&i915_file_priv->mm.request_list,
3533 struct drm_i915_gem_request,
3536 if (time_after_eq(request->emitted_jiffies, recent_enough))
3539 ret = i915_wait_request(dev, request->seqno, request->ring);
3543 mutex_unlock(&dev->struct_mutex);
3549 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list,
3550 uint32_t buffer_count,
3551 struct drm_i915_gem_relocation_entry **relocs)
3553 uint32_t reloc_count = 0, reloc_index = 0, i;
3557 for (i = 0; i < buffer_count; i++) {
3558 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3560 reloc_count += exec_list[i].relocation_count;
3563 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
3564 if (*relocs == NULL) {
3565 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count);
3569 for (i = 0; i < buffer_count; i++) {
3570 struct drm_i915_gem_relocation_entry __user *user_relocs;
3572 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3574 ret = copy_from_user(&(*relocs)[reloc_index],
3576 exec_list[i].relocation_count *
3579 drm_free_large(*relocs);
3584 reloc_index += exec_list[i].relocation_count;
3591 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list,
3592 uint32_t buffer_count,
3593 struct drm_i915_gem_relocation_entry *relocs)
3595 uint32_t reloc_count = 0, i;
3601 for (i = 0; i < buffer_count; i++) {
3602 struct drm_i915_gem_relocation_entry __user *user_relocs;
3605 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3607 unwritten = copy_to_user(user_relocs,
3608 &relocs[reloc_count],
3609 exec_list[i].relocation_count *
3617 reloc_count += exec_list[i].relocation_count;
3621 drm_free_large(relocs);
3627 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec,
3628 uint64_t exec_offset)
3630 uint32_t exec_start, exec_len;
3632 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3633 exec_len = (uint32_t) exec->batch_len;
3635 if ((exec_start | exec_len) & 0x7)
3645 i915_gem_wait_for_pending_flip(struct drm_device *dev,
3646 struct drm_gem_object **object_list,
3649 drm_i915_private_t *dev_priv = dev->dev_private;
3650 struct drm_i915_gem_object *obj_priv;
3655 prepare_to_wait(&dev_priv->pending_flip_queue,
3656 &wait, TASK_INTERRUPTIBLE);
3657 for (i = 0; i < count; i++) {
3658 obj_priv = to_intel_bo(object_list[i]);
3659 if (atomic_read(&obj_priv->pending_flip) > 0)
3665 if (!signal_pending(current)) {
3666 mutex_unlock(&dev->struct_mutex);
3668 mutex_lock(&dev->struct_mutex);
3674 finish_wait(&dev_priv->pending_flip_queue, &wait);
3680 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3681 struct drm_file *file_priv,
3682 struct drm_i915_gem_execbuffer2 *args,
3683 struct drm_i915_gem_exec_object2 *exec_list)
3685 drm_i915_private_t *dev_priv = dev->dev_private;
3686 struct drm_gem_object **object_list = NULL;
3687 struct drm_gem_object *batch_obj;
3688 struct drm_i915_gem_object *obj_priv;
3689 struct drm_clip_rect *cliprects = NULL;
3690 struct drm_i915_gem_relocation_entry *relocs = NULL;
3691 int ret = 0, ret2, i, pinned = 0;
3692 uint64_t exec_offset;
3693 uint32_t seqno, flush_domains, reloc_index;
3694 int pin_tries, flips;
3696 struct intel_ring_buffer *ring = NULL;
3699 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3700 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3702 if (args->flags & I915_EXEC_BSD) {
3703 if (!HAS_BSD(dev)) {
3704 DRM_ERROR("execbuf with wrong flag\n");
3707 ring = &dev_priv->bsd_ring;
3709 ring = &dev_priv->render_ring;
3713 if (args->buffer_count < 1) {
3714 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3717 object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
3718 if (object_list == NULL) {
3719 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3720 args->buffer_count);
3725 if (args->num_cliprects != 0) {
3726 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3728 if (cliprects == NULL) {
3733 ret = copy_from_user(cliprects,
3734 (struct drm_clip_rect __user *)
3735 (uintptr_t) args->cliprects_ptr,
3736 sizeof(*cliprects) * args->num_cliprects);
3738 DRM_ERROR("copy %d cliprects failed: %d\n",
3739 args->num_cliprects, ret);
3744 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3749 mutex_lock(&dev->struct_mutex);
3751 i915_verify_inactive(dev, __FILE__, __LINE__);
3753 if (atomic_read(&dev_priv->mm.wedged)) {
3754 mutex_unlock(&dev->struct_mutex);
3759 if (dev_priv->mm.suspended) {
3760 mutex_unlock(&dev->struct_mutex);
3765 /* Look up object handles */
3767 for (i = 0; i < args->buffer_count; i++) {
3768 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3769 exec_list[i].handle);
3770 if (object_list[i] == NULL) {
3771 DRM_ERROR("Invalid object handle %d at index %d\n",
3772 exec_list[i].handle, i);
3773 /* prevent error path from reading uninitialized data */
3774 args->buffer_count = i + 1;
3779 obj_priv = to_intel_bo(object_list[i]);
3780 if (obj_priv->in_execbuffer) {
3781 DRM_ERROR("Object %p appears more than once in object list\n",
3783 /* prevent error path from reading uninitialized data */
3784 args->buffer_count = i + 1;
3788 obj_priv->in_execbuffer = true;
3789 flips += atomic_read(&obj_priv->pending_flip);
3793 ret = i915_gem_wait_for_pending_flip(dev, object_list,
3794 args->buffer_count);
3799 /* Pin and relocate */
3800 for (pin_tries = 0; ; pin_tries++) {
3804 for (i = 0; i < args->buffer_count; i++) {
3805 object_list[i]->pending_read_domains = 0;
3806 object_list[i]->pending_write_domain = 0;
3807 ret = i915_gem_object_pin_and_relocate(object_list[i],
3810 &relocs[reloc_index]);
3814 reloc_index += exec_list[i].relocation_count;
3820 /* error other than GTT full, or we've already tried again */
3821 if (ret != -ENOSPC || pin_tries >= 1) {
3822 if (ret != -ERESTARTSYS) {
3823 unsigned long long total_size = 0;
3825 for (i = 0; i < args->buffer_count; i++) {
3826 obj_priv = object_list[i]->driver_private;
3828 total_size += object_list[i]->size;
3830 exec_list[i].flags & EXEC_OBJECT_NEEDS_FENCE &&
3831 obj_priv->tiling_mode != I915_TILING_NONE;
3833 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes, %d fences: %d\n",
3834 pinned+1, args->buffer_count,
3835 total_size, num_fences,
3837 DRM_ERROR("%d objects [%d pinned], "
3838 "%d object bytes [%d pinned], "
3839 "%d/%d gtt bytes\n",
3840 atomic_read(&dev->object_count),
3841 atomic_read(&dev->pin_count),
3842 atomic_read(&dev->object_memory),
3843 atomic_read(&dev->pin_memory),
3844 atomic_read(&dev->gtt_memory),
3850 /* unpin all of our buffers */
3851 for (i = 0; i < pinned; i++)
3852 i915_gem_object_unpin(object_list[i]);
3855 /* evict everyone we can from the aperture */
3856 ret = i915_gem_evict_everything(dev);
3857 if (ret && ret != -ENOSPC)
3861 /* Set the pending read domains for the batch buffer to COMMAND */
3862 batch_obj = object_list[args->buffer_count-1];
3863 if (batch_obj->pending_write_domain) {
3864 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3868 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
3870 /* Sanity check the batch buffer, prior to moving objects */
3871 exec_offset = exec_list[args->buffer_count - 1].offset;
3872 ret = i915_gem_check_execbuffer (args, exec_offset);
3874 DRM_ERROR("execbuf with invalid offset/length\n");
3878 i915_verify_inactive(dev, __FILE__, __LINE__);
3880 /* Zero the global flush/invalidate flags. These
3881 * will be modified as new domains are computed
3884 dev->invalidate_domains = 0;
3885 dev->flush_domains = 0;
3887 for (i = 0; i < args->buffer_count; i++) {
3888 struct drm_gem_object *obj = object_list[i];
3890 /* Compute new gpu domains and update invalidate/flush */
3891 i915_gem_object_set_to_gpu_domain(obj);
3894 i915_verify_inactive(dev, __FILE__, __LINE__);
3896 if (dev->invalidate_domains | dev->flush_domains) {
3898 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3900 dev->invalidate_domains,
3901 dev->flush_domains);
3904 dev->invalidate_domains,
3905 dev->flush_domains);
3906 if (dev->flush_domains & I915_GEM_GPU_DOMAINS) {
3907 (void)i915_add_request(dev, file_priv,
3909 &dev_priv->render_ring);
3912 (void)i915_add_request(dev, file_priv,
3914 &dev_priv->bsd_ring);
3918 for (i = 0; i < args->buffer_count; i++) {
3919 struct drm_gem_object *obj = object_list[i];
3920 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3921 uint32_t old_write_domain = obj->write_domain;
3923 obj->write_domain = obj->pending_write_domain;
3924 if (obj->write_domain)
3925 list_move_tail(&obj_priv->gpu_write_list,
3926 &dev_priv->mm.gpu_write_list);
3928 list_del_init(&obj_priv->gpu_write_list);
3930 trace_i915_gem_object_change_domain(obj,
3935 i915_verify_inactive(dev, __FILE__, __LINE__);
3938 for (i = 0; i < args->buffer_count; i++) {
3939 i915_gem_object_check_coherency(object_list[i],
3940 exec_list[i].handle);
3945 i915_gem_dump_object(batch_obj,
3951 /* Exec the batchbuffer */
3952 ret = ring->dispatch_gem_execbuffer(dev, ring, args,
3953 cliprects, exec_offset);
3955 DRM_ERROR("dispatch failed %d\n", ret);
3960 * Ensure that the commands in the batch buffer are
3961 * finished before the interrupt fires
3963 flush_domains = i915_retire_commands(dev, ring);
3965 i915_verify_inactive(dev, __FILE__, __LINE__);
3968 * Get a seqno representing the execution of the current buffer,
3969 * which we can wait on. We would like to mitigate these interrupts,
3970 * likely by only creating seqnos occasionally (so that we have
3971 * *some* interrupts representing completion of buffers that we can
3972 * wait on when trying to clear up gtt space).
3974 seqno = i915_add_request(dev, file_priv, flush_domains, ring);
3976 for (i = 0; i < args->buffer_count; i++) {
3977 struct drm_gem_object *obj = object_list[i];
3978 obj_priv = to_intel_bo(obj);
3980 i915_gem_object_move_to_active(obj, seqno, ring);
3982 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3986 i915_dump_lru(dev, __func__);
3989 i915_verify_inactive(dev, __FILE__, __LINE__);
3992 for (i = 0; i < pinned; i++)
3993 i915_gem_object_unpin(object_list[i]);
3995 for (i = 0; i < args->buffer_count; i++) {
3996 if (object_list[i]) {
3997 obj_priv = to_intel_bo(object_list[i]);
3998 obj_priv->in_execbuffer = false;
4000 drm_gem_object_unreference(object_list[i]);
4003 mutex_unlock(&dev->struct_mutex);
4006 /* Copy the updated relocations out regardless of current error
4007 * state. Failure to update the relocs would mean that the next
4008 * time userland calls execbuf, it would do so with presumed offset
4009 * state that didn't match the actual object state.
4011 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
4014 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
4020 drm_free_large(object_list);
4027 * Legacy execbuffer just creates an exec2 list from the original exec object
4028 * list array and passes it to the real function.
4031 i915_gem_execbuffer(struct drm_device *dev, void *data,
4032 struct drm_file *file_priv)
4034 struct drm_i915_gem_execbuffer *args = data;
4035 struct drm_i915_gem_execbuffer2 exec2;
4036 struct drm_i915_gem_exec_object *exec_list = NULL;
4037 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4041 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4042 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4045 if (args->buffer_count < 1) {
4046 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
4050 /* Copy in the exec list from userland */
4051 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
4052 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4053 if (exec_list == NULL || exec2_list == NULL) {
4054 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4055 args->buffer_count);
4056 drm_free_large(exec_list);
4057 drm_free_large(exec2_list);
4060 ret = copy_from_user(exec_list,
4061 (struct drm_i915_relocation_entry __user *)
4062 (uintptr_t) args->buffers_ptr,
4063 sizeof(*exec_list) * args->buffer_count);
4065 DRM_ERROR("copy %d exec entries failed %d\n",
4066 args->buffer_count, ret);
4067 drm_free_large(exec_list);
4068 drm_free_large(exec2_list);
4072 for (i = 0; i < args->buffer_count; i++) {
4073 exec2_list[i].handle = exec_list[i].handle;
4074 exec2_list[i].relocation_count = exec_list[i].relocation_count;
4075 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
4076 exec2_list[i].alignment = exec_list[i].alignment;
4077 exec2_list[i].offset = exec_list[i].offset;
4079 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
4081 exec2_list[i].flags = 0;
4084 exec2.buffers_ptr = args->buffers_ptr;
4085 exec2.buffer_count = args->buffer_count;
4086 exec2.batch_start_offset = args->batch_start_offset;
4087 exec2.batch_len = args->batch_len;
4088 exec2.DR1 = args->DR1;
4089 exec2.DR4 = args->DR4;
4090 exec2.num_cliprects = args->num_cliprects;
4091 exec2.cliprects_ptr = args->cliprects_ptr;
4092 exec2.flags = I915_EXEC_RENDER;
4094 ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
4096 /* Copy the new buffer offsets back to the user's exec list. */
4097 for (i = 0; i < args->buffer_count; i++)
4098 exec_list[i].offset = exec2_list[i].offset;
4099 /* ... and back out to userspace */
4100 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4101 (uintptr_t) args->buffers_ptr,
4103 sizeof(*exec_list) * args->buffer_count);
4106 DRM_ERROR("failed to copy %d exec entries "
4107 "back to user (%d)\n",
4108 args->buffer_count, ret);
4112 drm_free_large(exec_list);
4113 drm_free_large(exec2_list);
4118 i915_gem_execbuffer2(struct drm_device *dev, void *data,
4119 struct drm_file *file_priv)
4121 struct drm_i915_gem_execbuffer2 *args = data;
4122 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4126 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4127 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4130 if (args->buffer_count < 1) {
4131 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
4135 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4136 if (exec2_list == NULL) {
4137 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4138 args->buffer_count);
4141 ret = copy_from_user(exec2_list,
4142 (struct drm_i915_relocation_entry __user *)
4143 (uintptr_t) args->buffers_ptr,
4144 sizeof(*exec2_list) * args->buffer_count);
4146 DRM_ERROR("copy %d exec entries failed %d\n",
4147 args->buffer_count, ret);
4148 drm_free_large(exec2_list);
4152 ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
4154 /* Copy the new buffer offsets back to the user's exec list. */
4155 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4156 (uintptr_t) args->buffers_ptr,
4158 sizeof(*exec2_list) * args->buffer_count);
4161 DRM_ERROR("failed to copy %d exec entries "
4162 "back to user (%d)\n",
4163 args->buffer_count, ret);
4167 drm_free_large(exec2_list);
4172 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
4174 struct drm_device *dev = obj->dev;
4175 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4178 BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
4180 i915_verify_inactive(dev, __FILE__, __LINE__);
4182 if (obj_priv->gtt_space != NULL) {
4184 alignment = i915_gem_get_gtt_alignment(obj);
4185 if (obj_priv->gtt_offset & (alignment - 1)) {
4186 ret = i915_gem_object_unbind(obj);
4192 if (obj_priv->gtt_space == NULL) {
4193 ret = i915_gem_object_bind_to_gtt(obj, alignment);
4198 obj_priv->pin_count++;
4200 /* If the object is not active and not pending a flush,
4201 * remove it from the inactive list
4203 if (obj_priv->pin_count == 1) {
4204 atomic_inc(&dev->pin_count);
4205 atomic_add(obj->size, &dev->pin_memory);
4206 if (!obj_priv->active &&
4207 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 &&
4208 !list_empty(&obj_priv->list))
4209 list_del_init(&obj_priv->list);
4211 i915_verify_inactive(dev, __FILE__, __LINE__);
4217 i915_gem_object_unpin(struct drm_gem_object *obj)
4219 struct drm_device *dev = obj->dev;
4220 drm_i915_private_t *dev_priv = dev->dev_private;
4221 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4223 i915_verify_inactive(dev, __FILE__, __LINE__);
4224 obj_priv->pin_count--;
4225 BUG_ON(obj_priv->pin_count < 0);
4226 BUG_ON(obj_priv->gtt_space == NULL);
4228 /* If the object is no longer pinned, and is
4229 * neither active nor being flushed, then stick it on
4232 if (obj_priv->pin_count == 0) {
4233 if (!obj_priv->active &&
4234 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
4235 list_move_tail(&obj_priv->list,
4236 &dev_priv->mm.inactive_list);
4237 atomic_dec(&dev->pin_count);
4238 atomic_sub(obj->size, &dev->pin_memory);
4240 i915_verify_inactive(dev, __FILE__, __LINE__);
4244 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4245 struct drm_file *file_priv)
4247 struct drm_i915_gem_pin *args = data;
4248 struct drm_gem_object *obj;
4249 struct drm_i915_gem_object *obj_priv;
4252 mutex_lock(&dev->struct_mutex);
4254 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4256 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4258 mutex_unlock(&dev->struct_mutex);
4261 obj_priv = to_intel_bo(obj);
4263 if (obj_priv->madv != I915_MADV_WILLNEED) {
4264 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4265 drm_gem_object_unreference(obj);
4266 mutex_unlock(&dev->struct_mutex);
4270 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
4271 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4273 drm_gem_object_unreference(obj);
4274 mutex_unlock(&dev->struct_mutex);
4278 obj_priv->user_pin_count++;
4279 obj_priv->pin_filp = file_priv;
4280 if (obj_priv->user_pin_count == 1) {
4281 ret = i915_gem_object_pin(obj, args->alignment);
4283 drm_gem_object_unreference(obj);
4284 mutex_unlock(&dev->struct_mutex);
4289 /* XXX - flush the CPU caches for pinned objects
4290 * as the X server doesn't manage domains yet
4292 i915_gem_object_flush_cpu_write_domain(obj);
4293 args->offset = obj_priv->gtt_offset;
4294 drm_gem_object_unreference(obj);
4295 mutex_unlock(&dev->struct_mutex);
4301 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4302 struct drm_file *file_priv)
4304 struct drm_i915_gem_pin *args = data;
4305 struct drm_gem_object *obj;
4306 struct drm_i915_gem_object *obj_priv;
4308 mutex_lock(&dev->struct_mutex);
4310 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4312 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4314 mutex_unlock(&dev->struct_mutex);
4318 obj_priv = to_intel_bo(obj);
4319 if (obj_priv->pin_filp != file_priv) {
4320 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4322 drm_gem_object_unreference(obj);
4323 mutex_unlock(&dev->struct_mutex);
4326 obj_priv->user_pin_count--;
4327 if (obj_priv->user_pin_count == 0) {
4328 obj_priv->pin_filp = NULL;
4329 i915_gem_object_unpin(obj);
4332 drm_gem_object_unreference(obj);
4333 mutex_unlock(&dev->struct_mutex);
4338 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4339 struct drm_file *file_priv)
4341 struct drm_i915_gem_busy *args = data;
4342 struct drm_gem_object *obj;
4343 struct drm_i915_gem_object *obj_priv;
4344 drm_i915_private_t *dev_priv = dev->dev_private;
4346 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4348 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4353 mutex_lock(&dev->struct_mutex);
4354 /* Update the active list for the hardware's current position.
4355 * Otherwise this only updates on a delayed timer or when irqs are
4356 * actually unmasked, and our working set ends up being larger than
4359 i915_gem_retire_requests(dev, &dev_priv->render_ring);
4362 i915_gem_retire_requests(dev, &dev_priv->bsd_ring);
4364 obj_priv = to_intel_bo(obj);
4365 /* Don't count being on the flushing list against the object being
4366 * done. Otherwise, a buffer left on the flushing list but not getting
4367 * flushed (because nobody's flushing that domain) won't ever return
4368 * unbusy and get reused by libdrm's bo cache. The other expected
4369 * consumer of this interface, OpenGL's occlusion queries, also specs
4370 * that the objects get unbusy "eventually" without any interference.
4372 args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
4374 drm_gem_object_unreference(obj);
4375 mutex_unlock(&dev->struct_mutex);
4380 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4381 struct drm_file *file_priv)
4383 return i915_gem_ring_throttle(dev, file_priv);
4387 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4388 struct drm_file *file_priv)
4390 struct drm_i915_gem_madvise *args = data;
4391 struct drm_gem_object *obj;
4392 struct drm_i915_gem_object *obj_priv;
4394 switch (args->madv) {
4395 case I915_MADV_DONTNEED:
4396 case I915_MADV_WILLNEED:
4402 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4404 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4409 mutex_lock(&dev->struct_mutex);
4410 obj_priv = to_intel_bo(obj);
4412 if (obj_priv->pin_count) {
4413 drm_gem_object_unreference(obj);
4414 mutex_unlock(&dev->struct_mutex);
4416 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4420 if (obj_priv->madv != __I915_MADV_PURGED)
4421 obj_priv->madv = args->madv;
4423 /* if the object is no longer bound, discard its backing storage */
4424 if (i915_gem_object_is_purgeable(obj_priv) &&
4425 obj_priv->gtt_space == NULL)
4426 i915_gem_object_truncate(obj);
4428 args->retained = obj_priv->madv != __I915_MADV_PURGED;
4430 drm_gem_object_unreference(obj);
4431 mutex_unlock(&dev->struct_mutex);
4436 struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
4439 struct drm_i915_gem_object *obj;
4441 obj = kzalloc(sizeof(*obj), GFP_KERNEL);
4445 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4450 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4451 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4453 obj->agp_type = AGP_USER_MEMORY;
4454 obj->base.driver_private = NULL;
4455 obj->fence_reg = I915_FENCE_REG_NONE;
4456 INIT_LIST_HEAD(&obj->list);
4457 INIT_LIST_HEAD(&obj->gpu_write_list);
4458 obj->madv = I915_MADV_WILLNEED;
4460 trace_i915_gem_object_create(&obj->base);
4465 int i915_gem_init_object(struct drm_gem_object *obj)
4472 void i915_gem_free_object(struct drm_gem_object *obj)
4474 struct drm_device *dev = obj->dev;
4475 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4477 trace_i915_gem_object_destroy(obj);
4479 while (obj_priv->pin_count > 0)
4480 i915_gem_object_unpin(obj);
4482 if (obj_priv->phys_obj)
4483 i915_gem_detach_phys_object(dev, obj);
4485 i915_gem_object_unbind(obj);
4487 if (obj_priv->mmap_offset)
4488 i915_gem_free_mmap_offset(obj);
4490 drm_gem_object_release(obj);
4492 kfree(obj_priv->page_cpu_valid);
4493 kfree(obj_priv->bit_17);
4497 /** Unbinds all inactive objects. */
4499 i915_gem_evict_from_inactive_list(struct drm_device *dev)
4501 drm_i915_private_t *dev_priv = dev->dev_private;
4503 while (!list_empty(&dev_priv->mm.inactive_list)) {
4504 struct drm_gem_object *obj;
4507 obj = &list_first_entry(&dev_priv->mm.inactive_list,
4508 struct drm_i915_gem_object,
4511 ret = i915_gem_object_unbind(obj);
4513 DRM_ERROR("Error unbinding object: %d\n", ret);
4522 i915_gem_idle(struct drm_device *dev)
4524 drm_i915_private_t *dev_priv = dev->dev_private;
4527 mutex_lock(&dev->struct_mutex);
4529 if (dev_priv->mm.suspended ||
4530 (dev_priv->render_ring.gem_object == NULL) ||
4532 dev_priv->bsd_ring.gem_object == NULL)) {
4533 mutex_unlock(&dev->struct_mutex);
4537 ret = i915_gpu_idle(dev);
4539 mutex_unlock(&dev->struct_mutex);
4543 /* Under UMS, be paranoid and evict. */
4544 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
4545 ret = i915_gem_evict_from_inactive_list(dev);
4547 mutex_unlock(&dev->struct_mutex);
4552 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4553 * We need to replace this with a semaphore, or something.
4554 * And not confound mm.suspended!
4556 dev_priv->mm.suspended = 1;
4557 del_timer(&dev_priv->hangcheck_timer);
4559 i915_kernel_lost_context(dev);
4560 i915_gem_cleanup_ringbuffer(dev);
4562 mutex_unlock(&dev->struct_mutex);
4564 /* Cancel the retire work handler, which should be idle now. */
4565 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4571 * 965+ support PIPE_CONTROL commands, which provide finer grained control
4572 * over cache flushing.
4575 i915_gem_init_pipe_control(struct drm_device *dev)
4577 drm_i915_private_t *dev_priv = dev->dev_private;
4578 struct drm_gem_object *obj;
4579 struct drm_i915_gem_object *obj_priv;
4582 obj = i915_gem_alloc_object(dev, 4096);
4584 DRM_ERROR("Failed to allocate seqno page\n");
4588 obj_priv = to_intel_bo(obj);
4589 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4591 ret = i915_gem_object_pin(obj, 4096);
4595 dev_priv->seqno_gfx_addr = obj_priv->gtt_offset;
4596 dev_priv->seqno_page = kmap(obj_priv->pages[0]);
4597 if (dev_priv->seqno_page == NULL)
4600 dev_priv->seqno_obj = obj;
4601 memset(dev_priv->seqno_page, 0, PAGE_SIZE);
4606 i915_gem_object_unpin(obj);
4608 drm_gem_object_unreference(obj);
4615 i915_gem_cleanup_pipe_control(struct drm_device *dev)
4617 drm_i915_private_t *dev_priv = dev->dev_private;
4618 struct drm_gem_object *obj;
4619 struct drm_i915_gem_object *obj_priv;
4621 obj = dev_priv->seqno_obj;
4622 obj_priv = to_intel_bo(obj);
4623 kunmap(obj_priv->pages[0]);
4624 i915_gem_object_unpin(obj);
4625 drm_gem_object_unreference(obj);
4626 dev_priv->seqno_obj = NULL;
4628 dev_priv->seqno_page = NULL;
4632 i915_gem_init_ringbuffer(struct drm_device *dev)
4634 drm_i915_private_t *dev_priv = dev->dev_private;
4637 dev_priv->render_ring = render_ring;
4639 if (!I915_NEED_GFX_HWS(dev)) {
4640 dev_priv->render_ring.status_page.page_addr
4641 = dev_priv->status_page_dmah->vaddr;
4642 memset(dev_priv->render_ring.status_page.page_addr,
4646 if (HAS_PIPE_CONTROL(dev)) {
4647 ret = i915_gem_init_pipe_control(dev);
4652 ret = intel_init_ring_buffer(dev, &dev_priv->render_ring);
4654 goto cleanup_pipe_control;
4657 dev_priv->bsd_ring = bsd_ring;
4658 ret = intel_init_ring_buffer(dev, &dev_priv->bsd_ring);
4660 goto cleanup_render_ring;
4665 cleanup_render_ring:
4666 intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
4667 cleanup_pipe_control:
4668 if (HAS_PIPE_CONTROL(dev))
4669 i915_gem_cleanup_pipe_control(dev);
4674 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4676 drm_i915_private_t *dev_priv = dev->dev_private;
4678 intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
4680 intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
4681 if (HAS_PIPE_CONTROL(dev))
4682 i915_gem_cleanup_pipe_control(dev);
4686 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4687 struct drm_file *file_priv)
4689 drm_i915_private_t *dev_priv = dev->dev_private;
4692 if (drm_core_check_feature(dev, DRIVER_MODESET))
4695 if (atomic_read(&dev_priv->mm.wedged)) {
4696 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4697 atomic_set(&dev_priv->mm.wedged, 0);
4700 mutex_lock(&dev->struct_mutex);
4701 dev_priv->mm.suspended = 0;
4703 ret = i915_gem_init_ringbuffer(dev);
4705 mutex_unlock(&dev->struct_mutex);
4709 spin_lock(&dev_priv->mm.active_list_lock);
4710 BUG_ON(!list_empty(&dev_priv->render_ring.active_list));
4711 BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.active_list));
4712 spin_unlock(&dev_priv->mm.active_list_lock);
4714 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4715 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4716 BUG_ON(!list_empty(&dev_priv->render_ring.request_list));
4717 BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.request_list));
4718 mutex_unlock(&dev->struct_mutex);
4720 drm_irq_install(dev);
4726 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4727 struct drm_file *file_priv)
4729 if (drm_core_check_feature(dev, DRIVER_MODESET))
4732 drm_irq_uninstall(dev);
4733 return i915_gem_idle(dev);
4737 i915_gem_lastclose(struct drm_device *dev)
4741 if (drm_core_check_feature(dev, DRIVER_MODESET))
4744 ret = i915_gem_idle(dev);
4746 DRM_ERROR("failed to idle hardware: %d\n", ret);
4750 i915_gem_load(struct drm_device *dev)
4753 drm_i915_private_t *dev_priv = dev->dev_private;
4755 spin_lock_init(&dev_priv->mm.active_list_lock);
4756 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4757 INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list);
4758 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4759 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4760 INIT_LIST_HEAD(&dev_priv->render_ring.active_list);
4761 INIT_LIST_HEAD(&dev_priv->render_ring.request_list);
4763 INIT_LIST_HEAD(&dev_priv->bsd_ring.active_list);
4764 INIT_LIST_HEAD(&dev_priv->bsd_ring.request_list);
4766 for (i = 0; i < 16; i++)
4767 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4768 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4769 i915_gem_retire_work_handler);
4770 spin_lock(&shrink_list_lock);
4771 list_add(&dev_priv->mm.shrink_list, &shrink_list);
4772 spin_unlock(&shrink_list_lock);
4774 /* Old X drivers will take 0-2 for front, back, depth buffers */
4775 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4776 dev_priv->fence_reg_start = 3;
4778 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4779 dev_priv->num_fence_regs = 16;
4781 dev_priv->num_fence_regs = 8;
4783 /* Initialize fence registers to zero */
4784 if (IS_I965G(dev)) {
4785 for (i = 0; i < 16; i++)
4786 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4788 for (i = 0; i < 8; i++)
4789 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4790 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4791 for (i = 0; i < 8; i++)
4792 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4794 i915_gem_detect_bit_6_swizzle(dev);
4795 init_waitqueue_head(&dev_priv->pending_flip_queue);
4799 * Create a physically contiguous memory object for this object
4800 * e.g. for cursor + overlay regs
4802 int i915_gem_init_phys_object(struct drm_device *dev,
4805 drm_i915_private_t *dev_priv = dev->dev_private;
4806 struct drm_i915_gem_phys_object *phys_obj;
4809 if (dev_priv->mm.phys_objs[id - 1] || !size)
4812 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4818 phys_obj->handle = drm_pci_alloc(dev, size, 0);
4819 if (!phys_obj->handle) {
4824 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4827 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4835 void i915_gem_free_phys_object(struct drm_device *dev, int id)
4837 drm_i915_private_t *dev_priv = dev->dev_private;
4838 struct drm_i915_gem_phys_object *phys_obj;
4840 if (!dev_priv->mm.phys_objs[id - 1])
4843 phys_obj = dev_priv->mm.phys_objs[id - 1];
4844 if (phys_obj->cur_obj) {
4845 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4849 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4851 drm_pci_free(dev, phys_obj->handle);
4853 dev_priv->mm.phys_objs[id - 1] = NULL;
4856 void i915_gem_free_all_phys_object(struct drm_device *dev)
4860 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4861 i915_gem_free_phys_object(dev, i);
4864 void i915_gem_detach_phys_object(struct drm_device *dev,
4865 struct drm_gem_object *obj)
4867 struct drm_i915_gem_object *obj_priv;
4872 obj_priv = to_intel_bo(obj);
4873 if (!obj_priv->phys_obj)
4876 ret = i915_gem_object_get_pages(obj, 0);
4880 page_count = obj->size / PAGE_SIZE;
4882 for (i = 0; i < page_count; i++) {
4883 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
4884 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4886 memcpy(dst, src, PAGE_SIZE);
4887 kunmap_atomic(dst, KM_USER0);
4889 drm_clflush_pages(obj_priv->pages, page_count);
4890 drm_agp_chipset_flush(dev);
4892 i915_gem_object_put_pages(obj);
4894 obj_priv->phys_obj->cur_obj = NULL;
4895 obj_priv->phys_obj = NULL;
4899 i915_gem_attach_phys_object(struct drm_device *dev,
4900 struct drm_gem_object *obj, int id)
4902 drm_i915_private_t *dev_priv = dev->dev_private;
4903 struct drm_i915_gem_object *obj_priv;
4908 if (id > I915_MAX_PHYS_OBJECT)
4911 obj_priv = to_intel_bo(obj);
4913 if (obj_priv->phys_obj) {
4914 if (obj_priv->phys_obj->id == id)
4916 i915_gem_detach_phys_object(dev, obj);
4920 /* create a new object */
4921 if (!dev_priv->mm.phys_objs[id - 1]) {
4922 ret = i915_gem_init_phys_object(dev, id,
4925 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
4930 /* bind to the object */
4931 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4932 obj_priv->phys_obj->cur_obj = obj;
4934 ret = i915_gem_object_get_pages(obj, 0);
4936 DRM_ERROR("failed to get page list\n");
4940 page_count = obj->size / PAGE_SIZE;
4942 for (i = 0; i < page_count; i++) {
4943 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
4944 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4946 memcpy(dst, src, PAGE_SIZE);
4947 kunmap_atomic(src, KM_USER0);
4950 i915_gem_object_put_pages(obj);
4958 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4959 struct drm_i915_gem_pwrite *args,
4960 struct drm_file *file_priv)
4962 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4965 char __user *user_data;
4967 user_data = (char __user *) (uintptr_t) args->data_ptr;
4968 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4970 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size);
4971 ret = copy_from_user(obj_addr, user_data, args->size);
4975 drm_agp_chipset_flush(dev);
4979 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
4981 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
4983 /* Clean up our request list when the client is going away, so that
4984 * later retire_requests won't dereference our soon-to-be-gone
4987 mutex_lock(&dev->struct_mutex);
4988 while (!list_empty(&i915_file_priv->mm.request_list))
4989 list_del_init(i915_file_priv->mm.request_list.next);
4990 mutex_unlock(&dev->struct_mutex);
4994 i915_gpu_is_active(struct drm_device *dev)
4996 drm_i915_private_t *dev_priv = dev->dev_private;
4999 spin_lock(&dev_priv->mm.active_list_lock);
5000 lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
5001 list_empty(&dev_priv->render_ring.active_list);
5003 lists_empty &= list_empty(&dev_priv->bsd_ring.active_list);
5004 spin_unlock(&dev_priv->mm.active_list_lock);
5006 return !lists_empty;
5010 i915_gem_shrink(int nr_to_scan, gfp_t gfp_mask)
5012 drm_i915_private_t *dev_priv, *next_dev;
5013 struct drm_i915_gem_object *obj_priv, *next_obj;
5015 int would_deadlock = 1;
5017 /* "fast-path" to count number of available objects */
5018 if (nr_to_scan == 0) {
5019 spin_lock(&shrink_list_lock);
5020 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
5021 struct drm_device *dev = dev_priv->dev;
5023 if (mutex_trylock(&dev->struct_mutex)) {
5024 list_for_each_entry(obj_priv,
5025 &dev_priv->mm.inactive_list,
5028 mutex_unlock(&dev->struct_mutex);
5031 spin_unlock(&shrink_list_lock);
5033 return (cnt / 100) * sysctl_vfs_cache_pressure;
5036 spin_lock(&shrink_list_lock);
5039 /* first scan for clean buffers */
5040 list_for_each_entry_safe(dev_priv, next_dev,
5041 &shrink_list, mm.shrink_list) {
5042 struct drm_device *dev = dev_priv->dev;
5044 if (! mutex_trylock(&dev->struct_mutex))
5047 spin_unlock(&shrink_list_lock);
5048 i915_gem_retire_requests(dev, &dev_priv->render_ring);
5051 i915_gem_retire_requests(dev, &dev_priv->bsd_ring);
5053 list_for_each_entry_safe(obj_priv, next_obj,
5054 &dev_priv->mm.inactive_list,
5056 if (i915_gem_object_is_purgeable(obj_priv)) {
5057 i915_gem_object_unbind(&obj_priv->base);
5058 if (--nr_to_scan <= 0)
5063 spin_lock(&shrink_list_lock);
5064 mutex_unlock(&dev->struct_mutex);
5068 if (nr_to_scan <= 0)
5072 /* second pass, evict/count anything still on the inactive list */
5073 list_for_each_entry_safe(dev_priv, next_dev,
5074 &shrink_list, mm.shrink_list) {
5075 struct drm_device *dev = dev_priv->dev;
5077 if (! mutex_trylock(&dev->struct_mutex))
5080 spin_unlock(&shrink_list_lock);
5082 list_for_each_entry_safe(obj_priv, next_obj,
5083 &dev_priv->mm.inactive_list,
5085 if (nr_to_scan > 0) {
5086 i915_gem_object_unbind(&obj_priv->base);
5092 spin_lock(&shrink_list_lock);
5093 mutex_unlock(&dev->struct_mutex);
5102 * We are desperate for pages, so as a last resort, wait
5103 * for the GPU to finish and discard whatever we can.
5104 * This has a dramatic impact to reduce the number of
5105 * OOM-killer events whilst running the GPU aggressively.
5107 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
5108 struct drm_device *dev = dev_priv->dev;
5110 if (!mutex_trylock(&dev->struct_mutex))
5113 spin_unlock(&shrink_list_lock);
5115 if (i915_gpu_is_active(dev)) {
5120 spin_lock(&shrink_list_lock);
5121 mutex_unlock(&dev->struct_mutex);
5128 spin_unlock(&shrink_list_lock);
5133 return (cnt / 100) * sysctl_vfs_cache_pressure;
5138 static struct shrinker shrinker = {
5139 .shrink = i915_gem_shrink,
5140 .seeks = DEFAULT_SEEKS,
5144 i915_gem_shrinker_init(void)
5146 register_shrinker(&shrinker);
5150 i915_gem_shrinker_exit(void)
5152 unregister_shrinker(&shrinker);