2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "intel_drv.h"
33 #include <linux/swap.h>
34 #include <linux/pci.h>
36 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
38 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
39 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
40 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
41 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
43 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
46 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
47 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
48 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
50 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
51 static int i915_gem_evict_something(struct drm_device *dev);
52 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
53 struct drm_i915_gem_pwrite *args,
54 struct drm_file *file_priv);
56 static LIST_HEAD(shrink_list);
57 static DEFINE_SPINLOCK(shrink_list_lock);
59 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
62 drm_i915_private_t *dev_priv = dev->dev_private;
65 (start & (PAGE_SIZE - 1)) != 0 ||
66 (end & (PAGE_SIZE - 1)) != 0) {
70 drm_mm_init(&dev_priv->mm.gtt_space, start,
73 dev->gtt_total = (uint32_t) (end - start);
79 i915_gem_init_ioctl(struct drm_device *dev, void *data,
80 struct drm_file *file_priv)
82 struct drm_i915_gem_init *args = data;
85 mutex_lock(&dev->struct_mutex);
86 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
87 mutex_unlock(&dev->struct_mutex);
93 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
94 struct drm_file *file_priv)
96 struct drm_i915_gem_get_aperture *args = data;
98 if (!(dev->driver->driver_features & DRIVER_GEM))
101 args->aper_size = dev->gtt_total;
102 args->aper_available_size = (args->aper_size -
103 atomic_read(&dev->pin_memory));
110 * Creates a new mm object and returns a handle to it.
113 i915_gem_create_ioctl(struct drm_device *dev, void *data,
114 struct drm_file *file_priv)
116 struct drm_i915_gem_create *args = data;
117 struct drm_gem_object *obj;
121 args->size = roundup(args->size, PAGE_SIZE);
123 /* Allocate the new object */
124 obj = drm_gem_object_alloc(dev, args->size);
128 ret = drm_gem_handle_create(file_priv, obj, &handle);
129 mutex_lock(&dev->struct_mutex);
130 drm_gem_object_handle_unreference(obj);
131 mutex_unlock(&dev->struct_mutex);
136 args->handle = handle;
142 fast_shmem_read(struct page **pages,
143 loff_t page_base, int page_offset,
150 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
153 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
154 kunmap_atomic(vaddr, KM_USER0);
162 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
164 drm_i915_private_t *dev_priv = obj->dev->dev_private;
165 struct drm_i915_gem_object *obj_priv = obj->driver_private;
167 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
168 obj_priv->tiling_mode != I915_TILING_NONE;
172 slow_shmem_copy(struct page *dst_page,
174 struct page *src_page,
178 char *dst_vaddr, *src_vaddr;
180 dst_vaddr = kmap_atomic(dst_page, KM_USER0);
181 if (dst_vaddr == NULL)
184 src_vaddr = kmap_atomic(src_page, KM_USER1);
185 if (src_vaddr == NULL) {
186 kunmap_atomic(dst_vaddr, KM_USER0);
190 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
192 kunmap_atomic(src_vaddr, KM_USER1);
193 kunmap_atomic(dst_vaddr, KM_USER0);
199 slow_shmem_bit17_copy(struct page *gpu_page,
201 struct page *cpu_page,
206 char *gpu_vaddr, *cpu_vaddr;
208 /* Use the unswizzled path if this page isn't affected. */
209 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
211 return slow_shmem_copy(cpu_page, cpu_offset,
212 gpu_page, gpu_offset, length);
214 return slow_shmem_copy(gpu_page, gpu_offset,
215 cpu_page, cpu_offset, length);
218 gpu_vaddr = kmap_atomic(gpu_page, KM_USER0);
219 if (gpu_vaddr == NULL)
222 cpu_vaddr = kmap_atomic(cpu_page, KM_USER1);
223 if (cpu_vaddr == NULL) {
224 kunmap_atomic(gpu_vaddr, KM_USER0);
228 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
229 * XORing with the other bits (A9 for Y, A9 and A10 for X)
232 int cacheline_end = ALIGN(gpu_offset + 1, 64);
233 int this_length = min(cacheline_end - gpu_offset, length);
234 int swizzled_gpu_offset = gpu_offset ^ 64;
237 memcpy(cpu_vaddr + cpu_offset,
238 gpu_vaddr + swizzled_gpu_offset,
241 memcpy(gpu_vaddr + swizzled_gpu_offset,
242 cpu_vaddr + cpu_offset,
245 cpu_offset += this_length;
246 gpu_offset += this_length;
247 length -= this_length;
250 kunmap_atomic(cpu_vaddr, KM_USER1);
251 kunmap_atomic(gpu_vaddr, KM_USER0);
257 * This is the fast shmem pread path, which attempts to copy_from_user directly
258 * from the backing pages of the object to the user's address space. On a
259 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
262 i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
263 struct drm_i915_gem_pread *args,
264 struct drm_file *file_priv)
266 struct drm_i915_gem_object *obj_priv = obj->driver_private;
268 loff_t offset, page_base;
269 char __user *user_data;
270 int page_offset, page_length;
273 user_data = (char __user *) (uintptr_t) args->data_ptr;
276 mutex_lock(&dev->struct_mutex);
278 ret = i915_gem_object_get_pages(obj);
282 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
287 obj_priv = obj->driver_private;
288 offset = args->offset;
291 /* Operation in this page
293 * page_base = page offset within aperture
294 * page_offset = offset within page
295 * page_length = bytes to copy for this page
297 page_base = (offset & ~(PAGE_SIZE-1));
298 page_offset = offset & (PAGE_SIZE-1);
299 page_length = remain;
300 if ((page_offset + remain) > PAGE_SIZE)
301 page_length = PAGE_SIZE - page_offset;
303 ret = fast_shmem_read(obj_priv->pages,
304 page_base, page_offset,
305 user_data, page_length);
309 remain -= page_length;
310 user_data += page_length;
311 offset += page_length;
315 i915_gem_object_put_pages(obj);
317 mutex_unlock(&dev->struct_mutex);
323 * This is the fallback shmem pread path, which allocates temporary storage
324 * in kernel space to copy_to_user into outside of the struct_mutex, so we
325 * can copy out of the object's backing pages while holding the struct mutex
326 * and not take page faults.
329 i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
330 struct drm_i915_gem_pread *args,
331 struct drm_file *file_priv)
333 struct drm_i915_gem_object *obj_priv = obj->driver_private;
334 struct mm_struct *mm = current->mm;
335 struct page **user_pages;
337 loff_t offset, pinned_pages, i;
338 loff_t first_data_page, last_data_page, num_pages;
339 int shmem_page_index, shmem_page_offset;
340 int data_page_index, data_page_offset;
343 uint64_t data_ptr = args->data_ptr;
344 int do_bit17_swizzling;
348 /* Pin the user pages containing the data. We can't fault while
349 * holding the struct mutex, yet we want to hold it while
350 * dereferencing the user data.
352 first_data_page = data_ptr / PAGE_SIZE;
353 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
354 num_pages = last_data_page - first_data_page + 1;
356 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
357 if (user_pages == NULL)
360 down_read(&mm->mmap_sem);
361 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
362 num_pages, 1, 0, user_pages, NULL);
363 up_read(&mm->mmap_sem);
364 if (pinned_pages < num_pages) {
366 goto fail_put_user_pages;
369 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
371 mutex_lock(&dev->struct_mutex);
373 ret = i915_gem_object_get_pages(obj);
377 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
382 obj_priv = obj->driver_private;
383 offset = args->offset;
386 /* Operation in this page
388 * shmem_page_index = page number within shmem file
389 * shmem_page_offset = offset within page in shmem file
390 * data_page_index = page number in get_user_pages return
391 * data_page_offset = offset with data_page_index page.
392 * page_length = bytes to copy for this page
394 shmem_page_index = offset / PAGE_SIZE;
395 shmem_page_offset = offset & ~PAGE_MASK;
396 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
397 data_page_offset = data_ptr & ~PAGE_MASK;
399 page_length = remain;
400 if ((shmem_page_offset + page_length) > PAGE_SIZE)
401 page_length = PAGE_SIZE - shmem_page_offset;
402 if ((data_page_offset + page_length) > PAGE_SIZE)
403 page_length = PAGE_SIZE - data_page_offset;
405 if (do_bit17_swizzling) {
406 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
408 user_pages[data_page_index],
413 ret = slow_shmem_copy(user_pages[data_page_index],
415 obj_priv->pages[shmem_page_index],
422 remain -= page_length;
423 data_ptr += page_length;
424 offset += page_length;
428 i915_gem_object_put_pages(obj);
430 mutex_unlock(&dev->struct_mutex);
432 for (i = 0; i < pinned_pages; i++) {
433 SetPageDirty(user_pages[i]);
434 page_cache_release(user_pages[i]);
436 drm_free_large(user_pages);
442 * Reads data from the object referenced by handle.
444 * On error, the contents of *data are undefined.
447 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
448 struct drm_file *file_priv)
450 struct drm_i915_gem_pread *args = data;
451 struct drm_gem_object *obj;
452 struct drm_i915_gem_object *obj_priv;
455 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
458 obj_priv = obj->driver_private;
460 /* Bounds check source.
462 * XXX: This could use review for overflow issues...
464 if (args->offset > obj->size || args->size > obj->size ||
465 args->offset + args->size > obj->size) {
466 drm_gem_object_unreference(obj);
470 if (i915_gem_object_needs_bit17_swizzle(obj)) {
471 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
473 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
475 ret = i915_gem_shmem_pread_slow(dev, obj, args,
479 drm_gem_object_unreference(obj);
484 /* This is the fast write path which cannot handle
485 * page faults in the source data
489 fast_user_write(struct io_mapping *mapping,
490 loff_t page_base, int page_offset,
491 char __user *user_data,
495 unsigned long unwritten;
497 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
498 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
500 io_mapping_unmap_atomic(vaddr_atomic);
506 /* Here's the write path which can sleep for
511 slow_kernel_write(struct io_mapping *mapping,
512 loff_t gtt_base, int gtt_offset,
513 struct page *user_page, int user_offset,
516 char *src_vaddr, *dst_vaddr;
517 unsigned long unwritten;
519 dst_vaddr = io_mapping_map_atomic_wc(mapping, gtt_base);
520 src_vaddr = kmap_atomic(user_page, KM_USER1);
521 unwritten = __copy_from_user_inatomic_nocache(dst_vaddr + gtt_offset,
522 src_vaddr + user_offset,
524 kunmap_atomic(src_vaddr, KM_USER1);
525 io_mapping_unmap_atomic(dst_vaddr);
532 fast_shmem_write(struct page **pages,
533 loff_t page_base, int page_offset,
538 unsigned long unwritten;
540 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
543 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
544 kunmap_atomic(vaddr, KM_USER0);
552 * This is the fast pwrite path, where we copy the data directly from the
553 * user into the GTT, uncached.
556 i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
557 struct drm_i915_gem_pwrite *args,
558 struct drm_file *file_priv)
560 struct drm_i915_gem_object *obj_priv = obj->driver_private;
561 drm_i915_private_t *dev_priv = dev->dev_private;
563 loff_t offset, page_base;
564 char __user *user_data;
565 int page_offset, page_length;
568 user_data = (char __user *) (uintptr_t) args->data_ptr;
570 if (!access_ok(VERIFY_READ, user_data, remain))
574 mutex_lock(&dev->struct_mutex);
575 ret = i915_gem_object_pin(obj, 0);
577 mutex_unlock(&dev->struct_mutex);
580 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
584 obj_priv = obj->driver_private;
585 offset = obj_priv->gtt_offset + args->offset;
588 /* Operation in this page
590 * page_base = page offset within aperture
591 * page_offset = offset within page
592 * page_length = bytes to copy for this page
594 page_base = (offset & ~(PAGE_SIZE-1));
595 page_offset = offset & (PAGE_SIZE-1);
596 page_length = remain;
597 if ((page_offset + remain) > PAGE_SIZE)
598 page_length = PAGE_SIZE - page_offset;
600 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
601 page_offset, user_data, page_length);
603 /* If we get a fault while copying data, then (presumably) our
604 * source page isn't available. Return the error and we'll
605 * retry in the slow path.
610 remain -= page_length;
611 user_data += page_length;
612 offset += page_length;
616 i915_gem_object_unpin(obj);
617 mutex_unlock(&dev->struct_mutex);
623 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
624 * the memory and maps it using kmap_atomic for copying.
626 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
627 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
630 i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
631 struct drm_i915_gem_pwrite *args,
632 struct drm_file *file_priv)
634 struct drm_i915_gem_object *obj_priv = obj->driver_private;
635 drm_i915_private_t *dev_priv = dev->dev_private;
637 loff_t gtt_page_base, offset;
638 loff_t first_data_page, last_data_page, num_pages;
639 loff_t pinned_pages, i;
640 struct page **user_pages;
641 struct mm_struct *mm = current->mm;
642 int gtt_page_offset, data_page_offset, data_page_index, page_length;
644 uint64_t data_ptr = args->data_ptr;
648 /* Pin the user pages containing the data. We can't fault while
649 * holding the struct mutex, and all of the pwrite implementations
650 * want to hold it while dereferencing the user data.
652 first_data_page = data_ptr / PAGE_SIZE;
653 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
654 num_pages = last_data_page - first_data_page + 1;
656 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
657 if (user_pages == NULL)
660 down_read(&mm->mmap_sem);
661 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
662 num_pages, 0, 0, user_pages, NULL);
663 up_read(&mm->mmap_sem);
664 if (pinned_pages < num_pages) {
666 goto out_unpin_pages;
669 mutex_lock(&dev->struct_mutex);
670 ret = i915_gem_object_pin(obj, 0);
674 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
676 goto out_unpin_object;
678 obj_priv = obj->driver_private;
679 offset = obj_priv->gtt_offset + args->offset;
682 /* Operation in this page
684 * gtt_page_base = page offset within aperture
685 * gtt_page_offset = offset within page in aperture
686 * data_page_index = page number in get_user_pages return
687 * data_page_offset = offset with data_page_index page.
688 * page_length = bytes to copy for this page
690 gtt_page_base = offset & PAGE_MASK;
691 gtt_page_offset = offset & ~PAGE_MASK;
692 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
693 data_page_offset = data_ptr & ~PAGE_MASK;
695 page_length = remain;
696 if ((gtt_page_offset + page_length) > PAGE_SIZE)
697 page_length = PAGE_SIZE - gtt_page_offset;
698 if ((data_page_offset + page_length) > PAGE_SIZE)
699 page_length = PAGE_SIZE - data_page_offset;
701 ret = slow_kernel_write(dev_priv->mm.gtt_mapping,
702 gtt_page_base, gtt_page_offset,
703 user_pages[data_page_index],
707 /* If we get a fault while copying data, then (presumably) our
708 * source page isn't available. Return the error and we'll
709 * retry in the slow path.
712 goto out_unpin_object;
714 remain -= page_length;
715 offset += page_length;
716 data_ptr += page_length;
720 i915_gem_object_unpin(obj);
722 mutex_unlock(&dev->struct_mutex);
724 for (i = 0; i < pinned_pages; i++)
725 page_cache_release(user_pages[i]);
726 drm_free_large(user_pages);
732 * This is the fast shmem pwrite path, which attempts to directly
733 * copy_from_user into the kmapped pages backing the object.
736 i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
737 struct drm_i915_gem_pwrite *args,
738 struct drm_file *file_priv)
740 struct drm_i915_gem_object *obj_priv = obj->driver_private;
742 loff_t offset, page_base;
743 char __user *user_data;
744 int page_offset, page_length;
747 user_data = (char __user *) (uintptr_t) args->data_ptr;
750 mutex_lock(&dev->struct_mutex);
752 ret = i915_gem_object_get_pages(obj);
756 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
760 obj_priv = obj->driver_private;
761 offset = args->offset;
765 /* Operation in this page
767 * page_base = page offset within aperture
768 * page_offset = offset within page
769 * page_length = bytes to copy for this page
771 page_base = (offset & ~(PAGE_SIZE-1));
772 page_offset = offset & (PAGE_SIZE-1);
773 page_length = remain;
774 if ((page_offset + remain) > PAGE_SIZE)
775 page_length = PAGE_SIZE - page_offset;
777 ret = fast_shmem_write(obj_priv->pages,
778 page_base, page_offset,
779 user_data, page_length);
783 remain -= page_length;
784 user_data += page_length;
785 offset += page_length;
789 i915_gem_object_put_pages(obj);
791 mutex_unlock(&dev->struct_mutex);
797 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
798 * the memory and maps it using kmap_atomic for copying.
800 * This avoids taking mmap_sem for faulting on the user's address while the
801 * struct_mutex is held.
804 i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
805 struct drm_i915_gem_pwrite *args,
806 struct drm_file *file_priv)
808 struct drm_i915_gem_object *obj_priv = obj->driver_private;
809 struct mm_struct *mm = current->mm;
810 struct page **user_pages;
812 loff_t offset, pinned_pages, i;
813 loff_t first_data_page, last_data_page, num_pages;
814 int shmem_page_index, shmem_page_offset;
815 int data_page_index, data_page_offset;
818 uint64_t data_ptr = args->data_ptr;
819 int do_bit17_swizzling;
823 /* Pin the user pages containing the data. We can't fault while
824 * holding the struct mutex, and all of the pwrite implementations
825 * want to hold it while dereferencing the user data.
827 first_data_page = data_ptr / PAGE_SIZE;
828 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
829 num_pages = last_data_page - first_data_page + 1;
831 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
832 if (user_pages == NULL)
835 down_read(&mm->mmap_sem);
836 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
837 num_pages, 0, 0, user_pages, NULL);
838 up_read(&mm->mmap_sem);
839 if (pinned_pages < num_pages) {
841 goto fail_put_user_pages;
844 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
846 mutex_lock(&dev->struct_mutex);
848 ret = i915_gem_object_get_pages(obj);
852 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
856 obj_priv = obj->driver_private;
857 offset = args->offset;
861 /* Operation in this page
863 * shmem_page_index = page number within shmem file
864 * shmem_page_offset = offset within page in shmem file
865 * data_page_index = page number in get_user_pages return
866 * data_page_offset = offset with data_page_index page.
867 * page_length = bytes to copy for this page
869 shmem_page_index = offset / PAGE_SIZE;
870 shmem_page_offset = offset & ~PAGE_MASK;
871 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
872 data_page_offset = data_ptr & ~PAGE_MASK;
874 page_length = remain;
875 if ((shmem_page_offset + page_length) > PAGE_SIZE)
876 page_length = PAGE_SIZE - shmem_page_offset;
877 if ((data_page_offset + page_length) > PAGE_SIZE)
878 page_length = PAGE_SIZE - data_page_offset;
880 if (do_bit17_swizzling) {
881 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
883 user_pages[data_page_index],
888 ret = slow_shmem_copy(obj_priv->pages[shmem_page_index],
890 user_pages[data_page_index],
897 remain -= page_length;
898 data_ptr += page_length;
899 offset += page_length;
903 i915_gem_object_put_pages(obj);
905 mutex_unlock(&dev->struct_mutex);
907 for (i = 0; i < pinned_pages; i++)
908 page_cache_release(user_pages[i]);
909 drm_free_large(user_pages);
915 * Writes data to the object referenced by handle.
917 * On error, the contents of the buffer that were to be modified are undefined.
920 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
921 struct drm_file *file_priv)
923 struct drm_i915_gem_pwrite *args = data;
924 struct drm_gem_object *obj;
925 struct drm_i915_gem_object *obj_priv;
928 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
931 obj_priv = obj->driver_private;
933 /* Bounds check destination.
935 * XXX: This could use review for overflow issues...
937 if (args->offset > obj->size || args->size > obj->size ||
938 args->offset + args->size > obj->size) {
939 drm_gem_object_unreference(obj);
943 /* We can only do the GTT pwrite on untiled buffers, as otherwise
944 * it would end up going through the fenced access, and we'll get
945 * different detiling behavior between reading and writing.
946 * pread/pwrite currently are reading and writing from the CPU
947 * perspective, requiring manual detiling by the client.
949 if (obj_priv->phys_obj)
950 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
951 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
952 dev->gtt_total != 0) {
953 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
954 if (ret == -EFAULT) {
955 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
958 } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
959 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
961 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
962 if (ret == -EFAULT) {
963 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
970 DRM_INFO("pwrite failed %d\n", ret);
973 drm_gem_object_unreference(obj);
979 * Called when user space prepares to use an object with the CPU, either
980 * through the mmap ioctl's mapping or a GTT mapping.
983 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
984 struct drm_file *file_priv)
986 struct drm_i915_private *dev_priv = dev->dev_private;
987 struct drm_i915_gem_set_domain *args = data;
988 struct drm_gem_object *obj;
989 struct drm_i915_gem_object *obj_priv;
990 uint32_t read_domains = args->read_domains;
991 uint32_t write_domain = args->write_domain;
994 if (!(dev->driver->driver_features & DRIVER_GEM))
997 /* Only handle setting domains to types used by the CPU. */
998 if (write_domain & I915_GEM_GPU_DOMAINS)
1001 if (read_domains & I915_GEM_GPU_DOMAINS)
1004 /* Having something in the write domain implies it's in the read
1005 * domain, and only that read domain. Enforce that in the request.
1007 if (write_domain != 0 && read_domains != write_domain)
1010 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1013 obj_priv = obj->driver_private;
1015 mutex_lock(&dev->struct_mutex);
1017 intel_mark_busy(dev, obj);
1020 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1021 obj, obj->size, read_domains, write_domain);
1023 if (read_domains & I915_GEM_DOMAIN_GTT) {
1024 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1026 /* Update the LRU on the fence for the CPU access that's
1029 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1030 list_move_tail(&obj_priv->fence_list,
1031 &dev_priv->mm.fence_list);
1034 /* Silently promote "you're not bound, there was nothing to do"
1035 * to success, since the client was just asking us to
1036 * make sure everything was done.
1041 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1044 drm_gem_object_unreference(obj);
1045 mutex_unlock(&dev->struct_mutex);
1050 * Called when user space has done writes to this buffer
1053 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1054 struct drm_file *file_priv)
1056 struct drm_i915_gem_sw_finish *args = data;
1057 struct drm_gem_object *obj;
1058 struct drm_i915_gem_object *obj_priv;
1061 if (!(dev->driver->driver_features & DRIVER_GEM))
1064 mutex_lock(&dev->struct_mutex);
1065 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1067 mutex_unlock(&dev->struct_mutex);
1072 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1073 __func__, args->handle, obj, obj->size);
1075 obj_priv = obj->driver_private;
1077 /* Pinned buffers may be scanout, so flush the cache */
1078 if (obj_priv->pin_count)
1079 i915_gem_object_flush_cpu_write_domain(obj);
1081 drm_gem_object_unreference(obj);
1082 mutex_unlock(&dev->struct_mutex);
1087 * Maps the contents of an object, returning the address it is mapped
1090 * While the mapping holds a reference on the contents of the object, it doesn't
1091 * imply a ref on the object itself.
1094 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1095 struct drm_file *file_priv)
1097 struct drm_i915_gem_mmap *args = data;
1098 struct drm_gem_object *obj;
1102 if (!(dev->driver->driver_features & DRIVER_GEM))
1105 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1109 offset = args->offset;
1111 down_write(¤t->mm->mmap_sem);
1112 addr = do_mmap(obj->filp, 0, args->size,
1113 PROT_READ | PROT_WRITE, MAP_SHARED,
1115 up_write(¤t->mm->mmap_sem);
1116 mutex_lock(&dev->struct_mutex);
1117 drm_gem_object_unreference(obj);
1118 mutex_unlock(&dev->struct_mutex);
1119 if (IS_ERR((void *)addr))
1122 args->addr_ptr = (uint64_t) addr;
1128 * i915_gem_fault - fault a page into the GTT
1129 * vma: VMA in question
1132 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1133 * from userspace. The fault handler takes care of binding the object to
1134 * the GTT (if needed), allocating and programming a fence register (again,
1135 * only if needed based on whether the old reg is still valid or the object
1136 * is tiled) and inserting a new PTE into the faulting process.
1138 * Note that the faulting process may involve evicting existing objects
1139 * from the GTT and/or fence registers to make room. So performance may
1140 * suffer if the GTT working set is large or there are few fence registers
1143 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1145 struct drm_gem_object *obj = vma->vm_private_data;
1146 struct drm_device *dev = obj->dev;
1147 struct drm_i915_private *dev_priv = dev->dev_private;
1148 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1149 pgoff_t page_offset;
1152 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1154 /* We don't use vmf->pgoff since that has the fake offset */
1155 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1158 /* Now bind it into the GTT if needed */
1159 mutex_lock(&dev->struct_mutex);
1160 if (!obj_priv->gtt_space) {
1161 ret = i915_gem_object_bind_to_gtt(obj, 0);
1163 mutex_unlock(&dev->struct_mutex);
1164 return VM_FAULT_SIGBUS;
1166 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1168 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1170 mutex_unlock(&dev->struct_mutex);
1171 return VM_FAULT_SIGBUS;
1175 /* Need a new fence register? */
1176 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1177 ret = i915_gem_object_get_fence_reg(obj);
1179 mutex_unlock(&dev->struct_mutex);
1180 return VM_FAULT_SIGBUS;
1184 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1187 /* Finally, remap it using the new GTT offset */
1188 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1190 mutex_unlock(&dev->struct_mutex);
1195 return VM_FAULT_OOM;
1198 return VM_FAULT_SIGBUS;
1200 return VM_FAULT_NOPAGE;
1205 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1206 * @obj: obj in question
1208 * GEM memory mapping works by handing back to userspace a fake mmap offset
1209 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1210 * up the object based on the offset and sets up the various memory mapping
1213 * This routine allocates and attaches a fake offset for @obj.
1216 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1218 struct drm_device *dev = obj->dev;
1219 struct drm_gem_mm *mm = dev->mm_private;
1220 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1221 struct drm_map_list *list;
1222 struct drm_local_map *map;
1225 /* Set the object up for mmap'ing */
1226 list = &obj->map_list;
1227 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1232 map->type = _DRM_GEM;
1233 map->size = obj->size;
1236 /* Get a DRM GEM mmap offset allocated... */
1237 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1238 obj->size / PAGE_SIZE, 0, 0);
1239 if (!list->file_offset_node) {
1240 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1245 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1246 obj->size / PAGE_SIZE, 0);
1247 if (!list->file_offset_node) {
1252 list->hash.key = list->file_offset_node->start;
1253 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1254 DRM_ERROR("failed to add to map hash\n");
1258 /* By now we should be all set, any drm_mmap request on the offset
1259 * below will get to our mmap & fault handler */
1260 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1265 drm_mm_put_block(list->file_offset_node);
1273 * i915_gem_release_mmap - remove physical page mappings
1274 * @obj: obj in question
1276 * Preserve the reservation of the mmaping with the DRM core code, but
1277 * relinquish ownership of the pages back to the system.
1279 * It is vital that we remove the page mapping if we have mapped a tiled
1280 * object through the GTT and then lose the fence register due to
1281 * resource pressure. Similarly if the object has been moved out of the
1282 * aperture, than pages mapped into userspace must be revoked. Removing the
1283 * mapping will then trigger a page fault on the next user access, allowing
1284 * fixup by i915_gem_fault().
1287 i915_gem_release_mmap(struct drm_gem_object *obj)
1289 struct drm_device *dev = obj->dev;
1290 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1292 if (dev->dev_mapping)
1293 unmap_mapping_range(dev->dev_mapping,
1294 obj_priv->mmap_offset, obj->size, 1);
1298 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1300 struct drm_device *dev = obj->dev;
1301 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1302 struct drm_gem_mm *mm = dev->mm_private;
1303 struct drm_map_list *list;
1305 list = &obj->map_list;
1306 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1308 if (list->file_offset_node) {
1309 drm_mm_put_block(list->file_offset_node);
1310 list->file_offset_node = NULL;
1318 obj_priv->mmap_offset = 0;
1322 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1323 * @obj: object to check
1325 * Return the required GTT alignment for an object, taking into account
1326 * potential fence register mapping if needed.
1329 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1331 struct drm_device *dev = obj->dev;
1332 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1336 * Minimum alignment is 4k (GTT page size), but might be greater
1337 * if a fence register is needed for the object.
1339 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1343 * Previous chips need to be aligned to the size of the smallest
1344 * fence register that can contain the object.
1351 for (i = start; i < obj->size; i <<= 1)
1358 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1360 * @data: GTT mapping ioctl data
1361 * @file_priv: GEM object info
1363 * Simply returns the fake offset to userspace so it can mmap it.
1364 * The mmap call will end up in drm_gem_mmap(), which will set things
1365 * up so we can get faults in the handler above.
1367 * The fault handler will take care of binding the object into the GTT
1368 * (since it may have been evicted to make room for something), allocating
1369 * a fence register, and mapping the appropriate aperture address into
1373 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1374 struct drm_file *file_priv)
1376 struct drm_i915_gem_mmap_gtt *args = data;
1377 struct drm_i915_private *dev_priv = dev->dev_private;
1378 struct drm_gem_object *obj;
1379 struct drm_i915_gem_object *obj_priv;
1382 if (!(dev->driver->driver_features & DRIVER_GEM))
1385 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1389 mutex_lock(&dev->struct_mutex);
1391 obj_priv = obj->driver_private;
1393 if (!obj_priv->mmap_offset) {
1394 ret = i915_gem_create_mmap_offset(obj);
1396 drm_gem_object_unreference(obj);
1397 mutex_unlock(&dev->struct_mutex);
1402 args->offset = obj_priv->mmap_offset;
1405 * Pull it into the GTT so that we have a page list (makes the
1406 * initial fault faster and any subsequent flushing possible).
1408 if (!obj_priv->agp_mem) {
1409 ret = i915_gem_object_bind_to_gtt(obj, 0);
1411 drm_gem_object_unreference(obj);
1412 mutex_unlock(&dev->struct_mutex);
1415 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1418 drm_gem_object_unreference(obj);
1419 mutex_unlock(&dev->struct_mutex);
1425 i915_gem_object_put_pages(struct drm_gem_object *obj)
1427 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1428 int page_count = obj->size / PAGE_SIZE;
1431 BUG_ON(obj_priv->pages_refcount == 0);
1433 if (--obj_priv->pages_refcount != 0)
1436 if (obj_priv->tiling_mode != I915_TILING_NONE)
1437 i915_gem_object_save_bit_17_swizzle(obj);
1439 for (i = 0; i < page_count; i++)
1440 if (obj_priv->pages[i] != NULL) {
1441 if (obj_priv->dirty)
1442 set_page_dirty(obj_priv->pages[i]);
1443 mark_page_accessed(obj_priv->pages[i]);
1444 page_cache_release(obj_priv->pages[i]);
1446 obj_priv->dirty = 0;
1448 drm_free_large(obj_priv->pages);
1449 obj_priv->pages = NULL;
1453 i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
1455 struct drm_device *dev = obj->dev;
1456 drm_i915_private_t *dev_priv = dev->dev_private;
1457 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1459 /* Add a reference if we're newly entering the active list. */
1460 if (!obj_priv->active) {
1461 drm_gem_object_reference(obj);
1462 obj_priv->active = 1;
1464 /* Move from whatever list we were on to the tail of execution. */
1465 spin_lock(&dev_priv->mm.active_list_lock);
1466 list_move_tail(&obj_priv->list,
1467 &dev_priv->mm.active_list);
1468 spin_unlock(&dev_priv->mm.active_list_lock);
1469 obj_priv->last_rendering_seqno = seqno;
1473 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1475 struct drm_device *dev = obj->dev;
1476 drm_i915_private_t *dev_priv = dev->dev_private;
1477 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1479 BUG_ON(!obj_priv->active);
1480 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1481 obj_priv->last_rendering_seqno = 0;
1485 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1487 struct drm_device *dev = obj->dev;
1488 drm_i915_private_t *dev_priv = dev->dev_private;
1489 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1491 i915_verify_inactive(dev, __FILE__, __LINE__);
1492 if (obj_priv->pin_count != 0)
1493 list_del_init(&obj_priv->list);
1495 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1497 obj_priv->last_rendering_seqno = 0;
1498 if (obj_priv->active) {
1499 obj_priv->active = 0;
1500 drm_gem_object_unreference(obj);
1502 i915_verify_inactive(dev, __FILE__, __LINE__);
1506 * Creates a new sequence number, emitting a write of it to the status page
1507 * plus an interrupt, which will trigger i915_user_interrupt_handler.
1509 * Must be called with struct_lock held.
1511 * Returned sequence numbers are nonzero on success.
1514 i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1515 uint32_t flush_domains)
1517 drm_i915_private_t *dev_priv = dev->dev_private;
1518 struct drm_i915_file_private *i915_file_priv = NULL;
1519 struct drm_i915_gem_request *request;
1524 if (file_priv != NULL)
1525 i915_file_priv = file_priv->driver_priv;
1527 request = kzalloc(sizeof(*request), GFP_KERNEL);
1528 if (request == NULL)
1531 /* Grab the seqno we're going to make this request be, and bump the
1532 * next (skipping 0 so it can be the reserved no-seqno value).
1534 seqno = dev_priv->mm.next_gem_seqno;
1535 dev_priv->mm.next_gem_seqno++;
1536 if (dev_priv->mm.next_gem_seqno == 0)
1537 dev_priv->mm.next_gem_seqno++;
1540 OUT_RING(MI_STORE_DWORD_INDEX);
1541 OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1544 OUT_RING(MI_USER_INTERRUPT);
1547 DRM_DEBUG("%d\n", seqno);
1549 request->seqno = seqno;
1550 request->emitted_jiffies = jiffies;
1551 was_empty = list_empty(&dev_priv->mm.request_list);
1552 list_add_tail(&request->list, &dev_priv->mm.request_list);
1553 if (i915_file_priv) {
1554 list_add_tail(&request->client_list,
1555 &i915_file_priv->mm.request_list);
1557 INIT_LIST_HEAD(&request->client_list);
1560 /* Associate any objects on the flushing list matching the write
1561 * domain we're flushing with our flush.
1563 if (flush_domains != 0) {
1564 struct drm_i915_gem_object *obj_priv, *next;
1566 list_for_each_entry_safe(obj_priv, next,
1567 &dev_priv->mm.flushing_list, list) {
1568 struct drm_gem_object *obj = obj_priv->obj;
1570 if ((obj->write_domain & flush_domains) ==
1571 obj->write_domain) {
1572 obj->write_domain = 0;
1573 i915_gem_object_move_to_active(obj, seqno);
1579 if (!dev_priv->mm.suspended) {
1580 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1582 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1588 * Command execution barrier
1590 * Ensures that all commands in the ring are finished
1591 * before signalling the CPU
1594 i915_retire_commands(struct drm_device *dev)
1596 drm_i915_private_t *dev_priv = dev->dev_private;
1597 uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1598 uint32_t flush_domains = 0;
1601 /* The sampler always gets flushed on i965 (sigh) */
1603 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1606 OUT_RING(0); /* noop */
1608 return flush_domains;
1612 * Moves buffers associated only with the given active seqno from the active
1613 * to inactive list, potentially freeing them.
1616 i915_gem_retire_request(struct drm_device *dev,
1617 struct drm_i915_gem_request *request)
1619 drm_i915_private_t *dev_priv = dev->dev_private;
1621 /* Move any buffers on the active list that are no longer referenced
1622 * by the ringbuffer to the flushing/inactive lists as appropriate.
1624 spin_lock(&dev_priv->mm.active_list_lock);
1625 while (!list_empty(&dev_priv->mm.active_list)) {
1626 struct drm_gem_object *obj;
1627 struct drm_i915_gem_object *obj_priv;
1629 obj_priv = list_first_entry(&dev_priv->mm.active_list,
1630 struct drm_i915_gem_object,
1632 obj = obj_priv->obj;
1634 /* If the seqno being retired doesn't match the oldest in the
1635 * list, then the oldest in the list must still be newer than
1638 if (obj_priv->last_rendering_seqno != request->seqno)
1642 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1643 __func__, request->seqno, obj);
1646 if (obj->write_domain != 0)
1647 i915_gem_object_move_to_flushing(obj);
1649 /* Take a reference on the object so it won't be
1650 * freed while the spinlock is held. The list
1651 * protection for this spinlock is safe when breaking
1652 * the lock like this since the next thing we do
1653 * is just get the head of the list again.
1655 drm_gem_object_reference(obj);
1656 i915_gem_object_move_to_inactive(obj);
1657 spin_unlock(&dev_priv->mm.active_list_lock);
1658 drm_gem_object_unreference(obj);
1659 spin_lock(&dev_priv->mm.active_list_lock);
1663 spin_unlock(&dev_priv->mm.active_list_lock);
1667 * Returns true if seq1 is later than seq2.
1670 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1672 return (int32_t)(seq1 - seq2) >= 0;
1676 i915_get_gem_seqno(struct drm_device *dev)
1678 drm_i915_private_t *dev_priv = dev->dev_private;
1680 return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
1684 * This function clears the request list as sequence numbers are passed.
1687 i915_gem_retire_requests(struct drm_device *dev)
1689 drm_i915_private_t *dev_priv = dev->dev_private;
1692 if (!dev_priv->hw_status_page)
1695 seqno = i915_get_gem_seqno(dev);
1697 while (!list_empty(&dev_priv->mm.request_list)) {
1698 struct drm_i915_gem_request *request;
1699 uint32_t retiring_seqno;
1701 request = list_first_entry(&dev_priv->mm.request_list,
1702 struct drm_i915_gem_request,
1704 retiring_seqno = request->seqno;
1706 if (i915_seqno_passed(seqno, retiring_seqno) ||
1707 atomic_read(&dev_priv->mm.wedged)) {
1708 i915_gem_retire_request(dev, request);
1710 list_del(&request->list);
1711 list_del(&request->client_list);
1719 i915_gem_retire_work_handler(struct work_struct *work)
1721 drm_i915_private_t *dev_priv;
1722 struct drm_device *dev;
1724 dev_priv = container_of(work, drm_i915_private_t,
1725 mm.retire_work.work);
1726 dev = dev_priv->dev;
1728 mutex_lock(&dev->struct_mutex);
1729 i915_gem_retire_requests(dev);
1730 if (!dev_priv->mm.suspended &&
1731 !list_empty(&dev_priv->mm.request_list))
1732 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1733 mutex_unlock(&dev->struct_mutex);
1737 * Waits for a sequence number to be signaled, and cleans up the
1738 * request and object lists appropriately for that event.
1741 i915_wait_request(struct drm_device *dev, uint32_t seqno)
1743 drm_i915_private_t *dev_priv = dev->dev_private;
1749 if (atomic_read(&dev_priv->mm.wedged))
1752 if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
1754 ier = I915_READ(DEIER) | I915_READ(GTIER);
1756 ier = I915_READ(IER);
1758 DRM_ERROR("something (likely vbetool) disabled "
1759 "interrupts, re-enabling\n");
1760 i915_driver_irq_preinstall(dev);
1761 i915_driver_irq_postinstall(dev);
1764 dev_priv->mm.waiting_gem_seqno = seqno;
1765 i915_user_irq_get(dev);
1766 ret = wait_event_interruptible(dev_priv->irq_queue,
1767 i915_seqno_passed(i915_get_gem_seqno(dev),
1769 atomic_read(&dev_priv->mm.wedged));
1770 i915_user_irq_put(dev);
1771 dev_priv->mm.waiting_gem_seqno = 0;
1773 if (atomic_read(&dev_priv->mm.wedged))
1776 if (ret && ret != -ERESTARTSYS)
1777 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1778 __func__, ret, seqno, i915_get_gem_seqno(dev));
1780 /* Directly dispatch request retiring. While we have the work queue
1781 * to handle this, the waiter on a request often wants an associated
1782 * buffer to have made it to the inactive list, and we would need
1783 * a separate wait queue to handle that.
1786 i915_gem_retire_requests(dev);
1792 i915_gem_flush(struct drm_device *dev,
1793 uint32_t invalidate_domains,
1794 uint32_t flush_domains)
1796 drm_i915_private_t *dev_priv = dev->dev_private;
1801 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
1802 invalidate_domains, flush_domains);
1805 if (flush_domains & I915_GEM_DOMAIN_CPU)
1806 drm_agp_chipset_flush(dev);
1808 if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
1810 * read/write caches:
1812 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1813 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
1814 * also flushed at 2d versus 3d pipeline switches.
1818 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1819 * MI_READ_FLUSH is set, and is always flushed on 965.
1821 * I915_GEM_DOMAIN_COMMAND may not exist?
1823 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1824 * invalidated when MI_EXE_FLUSH is set.
1826 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1827 * invalidated with every MI_FLUSH.
1831 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1832 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1833 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1834 * are flushed at any MI_FLUSH.
1837 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1838 if ((invalidate_domains|flush_domains) &
1839 I915_GEM_DOMAIN_RENDER)
1840 cmd &= ~MI_NO_WRITE_FLUSH;
1841 if (!IS_I965G(dev)) {
1843 * On the 965, the sampler cache always gets flushed
1844 * and this bit is reserved.
1846 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
1847 cmd |= MI_READ_FLUSH;
1849 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
1850 cmd |= MI_EXE_FLUSH;
1853 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
1857 OUT_RING(0); /* noop */
1863 * Ensures that all rendering to the object has completed and the object is
1864 * safe to unbind from the GTT or access from the CPU.
1867 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1869 struct drm_device *dev = obj->dev;
1870 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1873 /* This function only exists to support waiting for existing rendering,
1874 * not for emitting required flushes.
1876 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
1878 /* If there is rendering queued on the buffer being evicted, wait for
1881 if (obj_priv->active) {
1883 DRM_INFO("%s: object %p wait for seqno %08x\n",
1884 __func__, obj, obj_priv->last_rendering_seqno);
1886 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
1895 * Unbinds an object from the GTT aperture.
1898 i915_gem_object_unbind(struct drm_gem_object *obj)
1900 struct drm_device *dev = obj->dev;
1901 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1905 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1906 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1908 if (obj_priv->gtt_space == NULL)
1911 if (obj_priv->pin_count != 0) {
1912 DRM_ERROR("Attempting to unbind pinned buffer\n");
1916 /* blow away mappings if mapped through GTT */
1917 i915_gem_release_mmap(obj);
1919 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
1920 i915_gem_clear_fence_reg(obj);
1922 /* Move the object to the CPU domain to ensure that
1923 * any possible CPU writes while it's not in the GTT
1924 * are flushed when we go to remap it. This will
1925 * also ensure that all pending GPU writes are finished
1928 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1930 if (ret != -ERESTARTSYS)
1931 DRM_ERROR("set_domain failed: %d\n", ret);
1935 BUG_ON(obj_priv->active);
1937 if (obj_priv->agp_mem != NULL) {
1938 drm_unbind_agp(obj_priv->agp_mem);
1939 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
1940 obj_priv->agp_mem = NULL;
1943 i915_gem_object_put_pages(obj);
1945 if (obj_priv->gtt_space) {
1946 atomic_dec(&dev->gtt_count);
1947 atomic_sub(obj->size, &dev->gtt_memory);
1949 drm_mm_put_block(obj_priv->gtt_space);
1950 obj_priv->gtt_space = NULL;
1953 /* Remove ourselves from the LRU list if present. */
1954 if (!list_empty(&obj_priv->list))
1955 list_del_init(&obj_priv->list);
1961 i915_gem_evict_something(struct drm_device *dev)
1963 drm_i915_private_t *dev_priv = dev->dev_private;
1964 struct drm_gem_object *obj;
1965 struct drm_i915_gem_object *obj_priv;
1969 /* If there's an inactive buffer available now, grab it
1972 if (!list_empty(&dev_priv->mm.inactive_list)) {
1973 obj_priv = list_first_entry(&dev_priv->mm.inactive_list,
1974 struct drm_i915_gem_object,
1976 obj = obj_priv->obj;
1977 BUG_ON(obj_priv->pin_count != 0);
1979 DRM_INFO("%s: evicting %p\n", __func__, obj);
1981 BUG_ON(obj_priv->active);
1983 /* Wait on the rendering and unbind the buffer. */
1984 ret = i915_gem_object_unbind(obj);
1988 /* If we didn't get anything, but the ring is still processing
1989 * things, wait for one of those things to finish and hopefully
1990 * leave us a buffer to evict.
1992 if (!list_empty(&dev_priv->mm.request_list)) {
1993 struct drm_i915_gem_request *request;
1995 request = list_first_entry(&dev_priv->mm.request_list,
1996 struct drm_i915_gem_request,
1999 ret = i915_wait_request(dev, request->seqno);
2003 /* if waiting caused an object to become inactive,
2004 * then loop around and wait for it. Otherwise, we
2005 * assume that waiting freed and unbound something,
2006 * so there should now be some space in the GTT
2008 if (!list_empty(&dev_priv->mm.inactive_list))
2013 /* If we didn't have anything on the request list but there
2014 * are buffers awaiting a flush, emit one and try again.
2015 * When we wait on it, those buffers waiting for that flush
2016 * will get moved to inactive.
2018 if (!list_empty(&dev_priv->mm.flushing_list)) {
2019 obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
2020 struct drm_i915_gem_object,
2022 obj = obj_priv->obj;
2027 i915_add_request(dev, NULL, obj->write_domain);
2033 DRM_ERROR("inactive empty %d request empty %d "
2034 "flushing empty %d\n",
2035 list_empty(&dev_priv->mm.inactive_list),
2036 list_empty(&dev_priv->mm.request_list),
2037 list_empty(&dev_priv->mm.flushing_list));
2038 /* If we didn't do any of the above, there's nothing to be done
2039 * and we just can't fit it in.
2047 i915_gem_evict_everything(struct drm_device *dev)
2052 ret = i915_gem_evict_something(dev);
2062 i915_gem_object_get_pages(struct drm_gem_object *obj)
2064 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2066 struct address_space *mapping;
2067 struct inode *inode;
2071 if (obj_priv->pages_refcount++ != 0)
2074 /* Get the list of pages out of our struct file. They'll be pinned
2075 * at this point until we release them.
2077 page_count = obj->size / PAGE_SIZE;
2078 BUG_ON(obj_priv->pages != NULL);
2079 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
2080 if (obj_priv->pages == NULL) {
2081 DRM_ERROR("Faled to allocate page list\n");
2082 obj_priv->pages_refcount--;
2086 inode = obj->filp->f_path.dentry->d_inode;
2087 mapping = inode->i_mapping;
2088 for (i = 0; i < page_count; i++) {
2089 page = read_mapping_page(mapping, i, NULL);
2091 ret = PTR_ERR(page);
2092 DRM_ERROR("read_mapping_page failed: %d\n", ret);
2093 i915_gem_object_put_pages(obj);
2096 obj_priv->pages[i] = page;
2099 if (obj_priv->tiling_mode != I915_TILING_NONE)
2100 i915_gem_object_do_bit_17_swizzle(obj);
2105 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2107 struct drm_gem_object *obj = reg->obj;
2108 struct drm_device *dev = obj->dev;
2109 drm_i915_private_t *dev_priv = dev->dev_private;
2110 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2111 int regnum = obj_priv->fence_reg;
2114 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2116 val |= obj_priv->gtt_offset & 0xfffff000;
2117 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2118 if (obj_priv->tiling_mode == I915_TILING_Y)
2119 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2120 val |= I965_FENCE_REG_VALID;
2122 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2125 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2127 struct drm_gem_object *obj = reg->obj;
2128 struct drm_device *dev = obj->dev;
2129 drm_i915_private_t *dev_priv = dev->dev_private;
2130 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2131 int regnum = obj_priv->fence_reg;
2133 uint32_t fence_reg, val;
2136 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2137 (obj_priv->gtt_offset & (obj->size - 1))) {
2138 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2139 __func__, obj_priv->gtt_offset, obj->size);
2143 if (obj_priv->tiling_mode == I915_TILING_Y &&
2144 HAS_128_BYTE_Y_TILING(dev))
2149 /* Note: pitch better be a power of two tile widths */
2150 pitch_val = obj_priv->stride / tile_width;
2151 pitch_val = ffs(pitch_val) - 1;
2153 val = obj_priv->gtt_offset;
2154 if (obj_priv->tiling_mode == I915_TILING_Y)
2155 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2156 val |= I915_FENCE_SIZE_BITS(obj->size);
2157 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2158 val |= I830_FENCE_REG_VALID;
2161 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2163 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2164 I915_WRITE(fence_reg, val);
2167 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2169 struct drm_gem_object *obj = reg->obj;
2170 struct drm_device *dev = obj->dev;
2171 drm_i915_private_t *dev_priv = dev->dev_private;
2172 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2173 int regnum = obj_priv->fence_reg;
2176 uint32_t fence_size_bits;
2178 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
2179 (obj_priv->gtt_offset & (obj->size - 1))) {
2180 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2181 __func__, obj_priv->gtt_offset);
2185 pitch_val = obj_priv->stride / 128;
2186 pitch_val = ffs(pitch_val) - 1;
2187 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2189 val = obj_priv->gtt_offset;
2190 if (obj_priv->tiling_mode == I915_TILING_Y)
2191 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2192 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2193 WARN_ON(fence_size_bits & ~0x00000f00);
2194 val |= fence_size_bits;
2195 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2196 val |= I830_FENCE_REG_VALID;
2198 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
2202 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2203 * @obj: object to map through a fence reg
2205 * When mapping objects through the GTT, userspace wants to be able to write
2206 * to them without having to worry about swizzling if the object is tiled.
2208 * This function walks the fence regs looking for a free one for @obj,
2209 * stealing one if it can't find any.
2211 * It then sets up the reg based on the object's properties: address, pitch
2212 * and tiling format.
2215 i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
2217 struct drm_device *dev = obj->dev;
2218 struct drm_i915_private *dev_priv = dev->dev_private;
2219 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2220 struct drm_i915_fence_reg *reg = NULL;
2221 struct drm_i915_gem_object *old_obj_priv = NULL;
2224 /* Just update our place in the LRU if our fence is getting used. */
2225 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2226 list_move_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2230 switch (obj_priv->tiling_mode) {
2231 case I915_TILING_NONE:
2232 WARN(1, "allocating a fence for non-tiled object?\n");
2235 if (!obj_priv->stride)
2237 WARN((obj_priv->stride & (512 - 1)),
2238 "object 0x%08x is X tiled but has non-512B pitch\n",
2239 obj_priv->gtt_offset);
2242 if (!obj_priv->stride)
2244 WARN((obj_priv->stride & (128 - 1)),
2245 "object 0x%08x is Y tiled but has non-128B pitch\n",
2246 obj_priv->gtt_offset);
2250 /* First try to find a free reg */
2252 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2253 reg = &dev_priv->fence_regs[i];
2257 old_obj_priv = reg->obj->driver_private;
2258 if (!old_obj_priv->pin_count)
2262 /* None available, try to steal one or wait for a user to finish */
2263 if (i == dev_priv->num_fence_regs) {
2264 struct drm_gem_object *old_obj = NULL;
2269 list_for_each_entry(old_obj_priv, &dev_priv->mm.fence_list,
2271 old_obj = old_obj_priv->obj;
2273 if (old_obj_priv->pin_count)
2276 /* Take a reference, as otherwise the wait_rendering
2277 * below may cause the object to get freed out from
2280 drm_gem_object_reference(old_obj);
2282 /* i915 uses fences for GPU access to tiled buffers */
2283 if (IS_I965G(dev) || !old_obj_priv->active)
2286 /* This brings the object to the head of the LRU if it
2287 * had been written to. The only way this should
2288 * result in us waiting longer than the expected
2289 * optimal amount of time is if there was a
2290 * fence-using buffer later that was read-only.
2292 i915_gem_object_flush_gpu_write_domain(old_obj);
2293 ret = i915_gem_object_wait_rendering(old_obj);
2295 drm_gem_object_unreference(old_obj);
2303 * Zap this virtual mapping so we can set up a fence again
2304 * for this object next time we need it.
2306 i915_gem_release_mmap(old_obj);
2308 i = old_obj_priv->fence_reg;
2309 reg = &dev_priv->fence_regs[i];
2311 old_obj_priv->fence_reg = I915_FENCE_REG_NONE;
2312 list_del_init(&old_obj_priv->fence_list);
2314 drm_gem_object_unreference(old_obj);
2317 obj_priv->fence_reg = i;
2318 list_add_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2323 i965_write_fence_reg(reg);
2324 else if (IS_I9XX(dev))
2325 i915_write_fence_reg(reg);
2327 i830_write_fence_reg(reg);
2333 * i915_gem_clear_fence_reg - clear out fence register info
2334 * @obj: object to clear
2336 * Zeroes out the fence register itself and clears out the associated
2337 * data structures in dev_priv and obj_priv.
2340 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2342 struct drm_device *dev = obj->dev;
2343 drm_i915_private_t *dev_priv = dev->dev_private;
2344 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2347 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
2351 if (obj_priv->fence_reg < 8)
2352 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2354 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2357 I915_WRITE(fence_reg, 0);
2360 dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL;
2361 obj_priv->fence_reg = I915_FENCE_REG_NONE;
2362 list_del_init(&obj_priv->fence_list);
2366 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2367 * to the buffer to finish, and then resets the fence register.
2368 * @obj: tiled object holding a fence register.
2370 * Zeroes out the fence register itself and clears out the associated
2371 * data structures in dev_priv and obj_priv.
2374 i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2376 struct drm_device *dev = obj->dev;
2377 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2379 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2382 /* On the i915, GPU access to tiled buffers is via a fence,
2383 * therefore we must wait for any outstanding access to complete
2384 * before clearing the fence.
2386 if (!IS_I965G(dev)) {
2389 i915_gem_object_flush_gpu_write_domain(obj);
2390 i915_gem_object_flush_gtt_write_domain(obj);
2391 ret = i915_gem_object_wait_rendering(obj);
2396 i915_gem_clear_fence_reg (obj);
2402 * Finds free space in the GTT aperture and binds the object there.
2405 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2407 struct drm_device *dev = obj->dev;
2408 drm_i915_private_t *dev_priv = dev->dev_private;
2409 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2410 struct drm_mm_node *free_space;
2411 int page_count, ret;
2413 if (dev_priv->mm.suspended)
2416 alignment = i915_gem_get_gtt_alignment(obj);
2417 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
2418 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2423 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2424 obj->size, alignment, 0);
2425 if (free_space != NULL) {
2426 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2428 if (obj_priv->gtt_space != NULL) {
2429 obj_priv->gtt_space->private = obj;
2430 obj_priv->gtt_offset = obj_priv->gtt_space->start;
2433 if (obj_priv->gtt_space == NULL) {
2436 /* If the gtt is empty and we're still having trouble
2437 * fitting our object in, we're out of memory.
2440 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2442 spin_lock(&dev_priv->mm.active_list_lock);
2443 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2444 list_empty(&dev_priv->mm.flushing_list) &&
2445 list_empty(&dev_priv->mm.active_list));
2446 spin_unlock(&dev_priv->mm.active_list_lock);
2448 DRM_ERROR("GTT full, but LRU list empty\n");
2452 ret = i915_gem_evict_something(dev);
2454 if (ret != -ERESTARTSYS)
2455 DRM_ERROR("Failed to evict a buffer %d\n", ret);
2462 DRM_INFO("Binding object of size %zd at 0x%08x\n",
2463 obj->size, obj_priv->gtt_offset);
2465 ret = i915_gem_object_get_pages(obj);
2467 drm_mm_put_block(obj_priv->gtt_space);
2468 obj_priv->gtt_space = NULL;
2472 page_count = obj->size / PAGE_SIZE;
2473 /* Create an AGP memory structure pointing at our pages, and bind it
2476 obj_priv->agp_mem = drm_agp_bind_pages(dev,
2479 obj_priv->gtt_offset,
2480 obj_priv->agp_type);
2481 if (obj_priv->agp_mem == NULL) {
2482 i915_gem_object_put_pages(obj);
2483 drm_mm_put_block(obj_priv->gtt_space);
2484 obj_priv->gtt_space = NULL;
2487 atomic_inc(&dev->gtt_count);
2488 atomic_add(obj->size, &dev->gtt_memory);
2490 /* Assert that the object is not currently in any GPU domain. As it
2491 * wasn't in the GTT, there shouldn't be any way it could have been in
2494 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2495 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
2501 i915_gem_clflush_object(struct drm_gem_object *obj)
2503 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2505 /* If we don't have a page list set up, then we're not pinned
2506 * to GPU, and we can ignore the cache flush because it'll happen
2507 * again at bind time.
2509 if (obj_priv->pages == NULL)
2512 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2515 /** Flushes any GPU write domain for the object if it's dirty. */
2517 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2519 struct drm_device *dev = obj->dev;
2522 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2525 /* Queue the GPU write cache flushing we need. */
2526 i915_gem_flush(dev, 0, obj->write_domain);
2527 seqno = i915_add_request(dev, NULL, obj->write_domain);
2528 obj->write_domain = 0;
2529 i915_gem_object_move_to_active(obj, seqno);
2532 /** Flushes the GTT write domain for the object if it's dirty. */
2534 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2536 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2539 /* No actual flushing is required for the GTT write domain. Writes
2540 * to it immediately go to main memory as far as we know, so there's
2541 * no chipset flush. It also doesn't land in render cache.
2543 obj->write_domain = 0;
2546 /** Flushes the CPU write domain for the object if it's dirty. */
2548 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2550 struct drm_device *dev = obj->dev;
2552 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2555 i915_gem_clflush_object(obj);
2556 drm_agp_chipset_flush(dev);
2557 obj->write_domain = 0;
2561 * Moves a single object to the GTT read, and possibly write domain.
2563 * This function returns when the move is complete, including waiting on
2567 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2569 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2572 /* Not valid to be called on unbound objects. */
2573 if (obj_priv->gtt_space == NULL)
2576 i915_gem_object_flush_gpu_write_domain(obj);
2577 /* Wait on any GPU rendering and flushing to occur. */
2578 ret = i915_gem_object_wait_rendering(obj);
2582 /* If we're writing through the GTT domain, then CPU and GPU caches
2583 * will need to be invalidated at next use.
2586 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2588 i915_gem_object_flush_cpu_write_domain(obj);
2590 /* It should now be out of any other write domains, and we can update
2591 * the domain values for our changes.
2593 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2594 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2596 obj->write_domain = I915_GEM_DOMAIN_GTT;
2597 obj_priv->dirty = 1;
2604 * Moves a single object to the CPU read, and possibly write domain.
2606 * This function returns when the move is complete, including waiting on
2610 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2614 i915_gem_object_flush_gpu_write_domain(obj);
2615 /* Wait on any GPU rendering and flushing to occur. */
2616 ret = i915_gem_object_wait_rendering(obj);
2620 i915_gem_object_flush_gtt_write_domain(obj);
2622 /* If we have a partially-valid cache of the object in the CPU,
2623 * finish invalidating it and free the per-page flags.
2625 i915_gem_object_set_to_full_cpu_read_domain(obj);
2627 /* Flush the CPU cache if it's still invalid. */
2628 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2629 i915_gem_clflush_object(obj);
2631 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2634 /* It should now be out of any other write domains, and we can update
2635 * the domain values for our changes.
2637 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2639 /* If we're writing through the CPU, then the GPU read domains will
2640 * need to be invalidated at next use.
2643 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2644 obj->write_domain = I915_GEM_DOMAIN_CPU;
2651 * Set the next domain for the specified object. This
2652 * may not actually perform the necessary flushing/invaliding though,
2653 * as that may want to be batched with other set_domain operations
2655 * This is (we hope) the only really tricky part of gem. The goal
2656 * is fairly simple -- track which caches hold bits of the object
2657 * and make sure they remain coherent. A few concrete examples may
2658 * help to explain how it works. For shorthand, we use the notation
2659 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2660 * a pair of read and write domain masks.
2662 * Case 1: the batch buffer
2668 * 5. Unmapped from GTT
2671 * Let's take these a step at a time
2674 * Pages allocated from the kernel may still have
2675 * cache contents, so we set them to (CPU, CPU) always.
2676 * 2. Written by CPU (using pwrite)
2677 * The pwrite function calls set_domain (CPU, CPU) and
2678 * this function does nothing (as nothing changes)
2680 * This function asserts that the object is not
2681 * currently in any GPU-based read or write domains
2683 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2684 * As write_domain is zero, this function adds in the
2685 * current read domains (CPU+COMMAND, 0).
2686 * flush_domains is set to CPU.
2687 * invalidate_domains is set to COMMAND
2688 * clflush is run to get data out of the CPU caches
2689 * then i915_dev_set_domain calls i915_gem_flush to
2690 * emit an MI_FLUSH and drm_agp_chipset_flush
2691 * 5. Unmapped from GTT
2692 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2693 * flush_domains and invalidate_domains end up both zero
2694 * so no flushing/invalidating happens
2698 * Case 2: The shared render buffer
2702 * 3. Read/written by GPU
2703 * 4. set_domain to (CPU,CPU)
2704 * 5. Read/written by CPU
2705 * 6. Read/written by GPU
2708 * Same as last example, (CPU, CPU)
2710 * Nothing changes (assertions find that it is not in the GPU)
2711 * 3. Read/written by GPU
2712 * execbuffer calls set_domain (RENDER, RENDER)
2713 * flush_domains gets CPU
2714 * invalidate_domains gets GPU
2716 * MI_FLUSH and drm_agp_chipset_flush
2717 * 4. set_domain (CPU, CPU)
2718 * flush_domains gets GPU
2719 * invalidate_domains gets CPU
2720 * wait_rendering (obj) to make sure all drawing is complete.
2721 * This will include an MI_FLUSH to get the data from GPU
2723 * clflush (obj) to invalidate the CPU cache
2724 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
2725 * 5. Read/written by CPU
2726 * cache lines are loaded and dirtied
2727 * 6. Read written by GPU
2728 * Same as last GPU access
2730 * Case 3: The constant buffer
2735 * 4. Updated (written) by CPU again
2744 * flush_domains = CPU
2745 * invalidate_domains = RENDER
2748 * drm_agp_chipset_flush
2749 * 4. Updated (written) by CPU again
2751 * flush_domains = 0 (no previous write domain)
2752 * invalidate_domains = 0 (no new read domains)
2755 * flush_domains = CPU
2756 * invalidate_domains = RENDER
2759 * drm_agp_chipset_flush
2762 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
2764 struct drm_device *dev = obj->dev;
2765 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2766 uint32_t invalidate_domains = 0;
2767 uint32_t flush_domains = 0;
2769 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
2770 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
2772 intel_mark_busy(dev, obj);
2775 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2777 obj->read_domains, obj->pending_read_domains,
2778 obj->write_domain, obj->pending_write_domain);
2781 * If the object isn't moving to a new write domain,
2782 * let the object stay in multiple read domains
2784 if (obj->pending_write_domain == 0)
2785 obj->pending_read_domains |= obj->read_domains;
2787 obj_priv->dirty = 1;
2790 * Flush the current write domain if
2791 * the new read domains don't match. Invalidate
2792 * any read domains which differ from the old
2795 if (obj->write_domain &&
2796 obj->write_domain != obj->pending_read_domains) {
2797 flush_domains |= obj->write_domain;
2798 invalidate_domains |=
2799 obj->pending_read_domains & ~obj->write_domain;
2802 * Invalidate any read caches which may have
2803 * stale data. That is, any new read domains.
2805 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
2806 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
2808 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
2809 __func__, flush_domains, invalidate_domains);
2811 i915_gem_clflush_object(obj);
2814 /* The actual obj->write_domain will be updated with
2815 * pending_write_domain after we emit the accumulated flush for all
2816 * of our domain changes in execbuffers (which clears objects'
2817 * write_domains). So if we have a current write domain that we
2818 * aren't changing, set pending_write_domain to that.
2820 if (flush_domains == 0 && obj->pending_write_domain == 0)
2821 obj->pending_write_domain = obj->write_domain;
2822 obj->read_domains = obj->pending_read_domains;
2824 dev->invalidate_domains |= invalidate_domains;
2825 dev->flush_domains |= flush_domains;
2827 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
2829 obj->read_domains, obj->write_domain,
2830 dev->invalidate_domains, dev->flush_domains);
2835 * Moves the object from a partially CPU read to a full one.
2837 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
2838 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
2841 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
2843 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2845 if (!obj_priv->page_cpu_valid)
2848 /* If we're partially in the CPU read domain, finish moving it in.
2850 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
2853 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
2854 if (obj_priv->page_cpu_valid[i])
2856 drm_clflush_pages(obj_priv->pages + i, 1);
2860 /* Free the page_cpu_valid mappings which are now stale, whether
2861 * or not we've got I915_GEM_DOMAIN_CPU.
2863 kfree(obj_priv->page_cpu_valid);
2864 obj_priv->page_cpu_valid = NULL;
2868 * Set the CPU read domain on a range of the object.
2870 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
2871 * not entirely valid. The page_cpu_valid member of the object flags which
2872 * pages have been flushed, and will be respected by
2873 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
2874 * of the whole object.
2876 * This function returns when the move is complete, including waiting on
2880 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
2881 uint64_t offset, uint64_t size)
2883 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2886 if (offset == 0 && size == obj->size)
2887 return i915_gem_object_set_to_cpu_domain(obj, 0);
2889 i915_gem_object_flush_gpu_write_domain(obj);
2890 /* Wait on any GPU rendering and flushing to occur. */
2891 ret = i915_gem_object_wait_rendering(obj);
2894 i915_gem_object_flush_gtt_write_domain(obj);
2896 /* If we're already fully in the CPU read domain, we're done. */
2897 if (obj_priv->page_cpu_valid == NULL &&
2898 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
2901 /* Otherwise, create/clear the per-page CPU read domain flag if we're
2902 * newly adding I915_GEM_DOMAIN_CPU
2904 if (obj_priv->page_cpu_valid == NULL) {
2905 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
2907 if (obj_priv->page_cpu_valid == NULL)
2909 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
2910 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
2912 /* Flush the cache on any pages that are still invalid from the CPU's
2915 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
2917 if (obj_priv->page_cpu_valid[i])
2920 drm_clflush_pages(obj_priv->pages + i, 1);
2922 obj_priv->page_cpu_valid[i] = 1;
2925 /* It should now be out of any other write domains, and we can update
2926 * the domain values for our changes.
2928 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2930 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2936 * Pin an object to the GTT and evaluate the relocations landing in it.
2939 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
2940 struct drm_file *file_priv,
2941 struct drm_i915_gem_exec_object *entry,
2942 struct drm_i915_gem_relocation_entry *relocs)
2944 struct drm_device *dev = obj->dev;
2945 drm_i915_private_t *dev_priv = dev->dev_private;
2946 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2948 void __iomem *reloc_page;
2950 /* Choose the GTT offset for our buffer and put it there. */
2951 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
2955 entry->offset = obj_priv->gtt_offset;
2957 /* Apply the relocations, using the GTT aperture to avoid cache
2958 * flushing requirements.
2960 for (i = 0; i < entry->relocation_count; i++) {
2961 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
2962 struct drm_gem_object *target_obj;
2963 struct drm_i915_gem_object *target_obj_priv;
2964 uint32_t reloc_val, reloc_offset;
2965 uint32_t __iomem *reloc_entry;
2967 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
2968 reloc->target_handle);
2969 if (target_obj == NULL) {
2970 i915_gem_object_unpin(obj);
2973 target_obj_priv = target_obj->driver_private;
2975 /* The target buffer should have appeared before us in the
2976 * exec_object list, so it should have a GTT space bound by now.
2978 if (target_obj_priv->gtt_space == NULL) {
2979 DRM_ERROR("No GTT space found for object %d\n",
2980 reloc->target_handle);
2981 drm_gem_object_unreference(target_obj);
2982 i915_gem_object_unpin(obj);
2986 if (reloc->offset > obj->size - 4) {
2987 DRM_ERROR("Relocation beyond object bounds: "
2988 "obj %p target %d offset %d size %d.\n",
2989 obj, reloc->target_handle,
2990 (int) reloc->offset, (int) obj->size);
2991 drm_gem_object_unreference(target_obj);
2992 i915_gem_object_unpin(obj);
2995 if (reloc->offset & 3) {
2996 DRM_ERROR("Relocation not 4-byte aligned: "
2997 "obj %p target %d offset %d.\n",
2998 obj, reloc->target_handle,
2999 (int) reloc->offset);
3000 drm_gem_object_unreference(target_obj);
3001 i915_gem_object_unpin(obj);
3005 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3006 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
3007 DRM_ERROR("reloc with read/write CPU domains: "
3008 "obj %p target %d offset %d "
3009 "read %08x write %08x",
3010 obj, reloc->target_handle,
3011 (int) reloc->offset,
3012 reloc->read_domains,
3013 reloc->write_domain);
3014 drm_gem_object_unreference(target_obj);
3015 i915_gem_object_unpin(obj);
3019 if (reloc->write_domain && target_obj->pending_write_domain &&
3020 reloc->write_domain != target_obj->pending_write_domain) {
3021 DRM_ERROR("Write domain conflict: "
3022 "obj %p target %d offset %d "
3023 "new %08x old %08x\n",
3024 obj, reloc->target_handle,
3025 (int) reloc->offset,
3026 reloc->write_domain,
3027 target_obj->pending_write_domain);
3028 drm_gem_object_unreference(target_obj);
3029 i915_gem_object_unpin(obj);
3034 DRM_INFO("%s: obj %p offset %08x target %d "
3035 "read %08x write %08x gtt %08x "
3036 "presumed %08x delta %08x\n",
3039 (int) reloc->offset,
3040 (int) reloc->target_handle,
3041 (int) reloc->read_domains,
3042 (int) reloc->write_domain,
3043 (int) target_obj_priv->gtt_offset,
3044 (int) reloc->presumed_offset,
3048 target_obj->pending_read_domains |= reloc->read_domains;
3049 target_obj->pending_write_domain |= reloc->write_domain;
3051 /* If the relocation already has the right value in it, no
3052 * more work needs to be done.
3054 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
3055 drm_gem_object_unreference(target_obj);
3059 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3061 drm_gem_object_unreference(target_obj);
3062 i915_gem_object_unpin(obj);
3066 /* Map the page containing the relocation we're going to
3069 reloc_offset = obj_priv->gtt_offset + reloc->offset;
3070 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3073 reloc_entry = (uint32_t __iomem *)(reloc_page +
3074 (reloc_offset & (PAGE_SIZE - 1)));
3075 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
3078 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3079 obj, (unsigned int) reloc->offset,
3080 readl(reloc_entry), reloc_val);
3082 writel(reloc_val, reloc_entry);
3083 io_mapping_unmap_atomic(reloc_page);
3085 /* The updated presumed offset for this entry will be
3086 * copied back out to the user.
3088 reloc->presumed_offset = target_obj_priv->gtt_offset;
3090 drm_gem_object_unreference(target_obj);
3095 i915_gem_dump_object(obj, 128, __func__, ~0);
3100 /** Dispatch a batchbuffer to the ring
3103 i915_dispatch_gem_execbuffer(struct drm_device *dev,
3104 struct drm_i915_gem_execbuffer *exec,
3105 struct drm_clip_rect *cliprects,
3106 uint64_t exec_offset)
3108 drm_i915_private_t *dev_priv = dev->dev_private;
3109 int nbox = exec->num_cliprects;
3111 uint32_t exec_start, exec_len;
3114 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3115 exec_len = (uint32_t) exec->batch_len;
3117 count = nbox ? nbox : 1;
3119 for (i = 0; i < count; i++) {
3121 int ret = i915_emit_box(dev, cliprects, i,
3122 exec->DR1, exec->DR4);
3127 if (IS_I830(dev) || IS_845G(dev)) {
3129 OUT_RING(MI_BATCH_BUFFER);
3130 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3131 OUT_RING(exec_start + exec_len - 4);
3136 if (IS_I965G(dev)) {
3137 OUT_RING(MI_BATCH_BUFFER_START |
3139 MI_BATCH_NON_SECURE_I965);
3140 OUT_RING(exec_start);
3142 OUT_RING(MI_BATCH_BUFFER_START |
3144 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3150 /* XXX breadcrumb */
3154 /* Throttle our rendering by waiting until the ring has completed our requests
3155 * emitted over 20 msec ago.
3157 * Note that if we were to use the current jiffies each time around the loop,
3158 * we wouldn't escape the function with any frames outstanding if the time to
3159 * render a frame was over 20ms.
3161 * This should get us reasonable parallelism between CPU and GPU but also
3162 * relatively low latency when blocking on a particular request to finish.
3165 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3167 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3169 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3171 mutex_lock(&dev->struct_mutex);
3172 while (!list_empty(&i915_file_priv->mm.request_list)) {
3173 struct drm_i915_gem_request *request;
3175 request = list_first_entry(&i915_file_priv->mm.request_list,
3176 struct drm_i915_gem_request,
3179 if (time_after_eq(request->emitted_jiffies, recent_enough))
3182 ret = i915_wait_request(dev, request->seqno);
3186 mutex_unlock(&dev->struct_mutex);
3192 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object *exec_list,
3193 uint32_t buffer_count,
3194 struct drm_i915_gem_relocation_entry **relocs)
3196 uint32_t reloc_count = 0, reloc_index = 0, i;
3200 for (i = 0; i < buffer_count; i++) {
3201 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3203 reloc_count += exec_list[i].relocation_count;
3206 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
3207 if (*relocs == NULL)
3210 for (i = 0; i < buffer_count; i++) {
3211 struct drm_i915_gem_relocation_entry __user *user_relocs;
3213 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3215 ret = copy_from_user(&(*relocs)[reloc_index],
3217 exec_list[i].relocation_count *
3220 drm_free_large(*relocs);
3225 reloc_index += exec_list[i].relocation_count;
3232 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object *exec_list,
3233 uint32_t buffer_count,
3234 struct drm_i915_gem_relocation_entry *relocs)
3236 uint32_t reloc_count = 0, i;
3239 for (i = 0; i < buffer_count; i++) {
3240 struct drm_i915_gem_relocation_entry __user *user_relocs;
3243 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3245 unwritten = copy_to_user(user_relocs,
3246 &relocs[reloc_count],
3247 exec_list[i].relocation_count *
3255 reloc_count += exec_list[i].relocation_count;
3259 drm_free_large(relocs);
3265 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer *exec,
3266 uint64_t exec_offset)
3268 uint32_t exec_start, exec_len;
3270 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3271 exec_len = (uint32_t) exec->batch_len;
3273 if ((exec_start | exec_len) & 0x7)
3283 i915_gem_execbuffer(struct drm_device *dev, void *data,
3284 struct drm_file *file_priv)
3286 drm_i915_private_t *dev_priv = dev->dev_private;
3287 struct drm_i915_gem_execbuffer *args = data;
3288 struct drm_i915_gem_exec_object *exec_list = NULL;
3289 struct drm_gem_object **object_list = NULL;
3290 struct drm_gem_object *batch_obj;
3291 struct drm_i915_gem_object *obj_priv;
3292 struct drm_clip_rect *cliprects = NULL;
3293 struct drm_i915_gem_relocation_entry *relocs;
3294 int ret, ret2, i, pinned = 0;
3295 uint64_t exec_offset;
3296 uint32_t seqno, flush_domains, reloc_index;
3300 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3301 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3304 if (args->buffer_count < 1) {
3305 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3308 /* Copy in the exec list from userland */
3309 exec_list = drm_calloc_large(sizeof(*exec_list), args->buffer_count);
3310 object_list = drm_calloc_large(sizeof(*object_list), args->buffer_count);
3311 if (exec_list == NULL || object_list == NULL) {
3312 DRM_ERROR("Failed to allocate exec or object list "
3314 args->buffer_count);
3318 ret = copy_from_user(exec_list,
3319 (struct drm_i915_relocation_entry __user *)
3320 (uintptr_t) args->buffers_ptr,
3321 sizeof(*exec_list) * args->buffer_count);
3323 DRM_ERROR("copy %d exec entries failed %d\n",
3324 args->buffer_count, ret);
3328 if (args->num_cliprects != 0) {
3329 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3331 if (cliprects == NULL)
3334 ret = copy_from_user(cliprects,
3335 (struct drm_clip_rect __user *)
3336 (uintptr_t) args->cliprects_ptr,
3337 sizeof(*cliprects) * args->num_cliprects);
3339 DRM_ERROR("copy %d cliprects failed: %d\n",
3340 args->num_cliprects, ret);
3345 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3350 mutex_lock(&dev->struct_mutex);
3352 i915_verify_inactive(dev, __FILE__, __LINE__);
3354 if (atomic_read(&dev_priv->mm.wedged)) {
3355 DRM_ERROR("Execbuf while wedged\n");
3356 mutex_unlock(&dev->struct_mutex);
3361 if (dev_priv->mm.suspended) {
3362 DRM_ERROR("Execbuf while VT-switched.\n");
3363 mutex_unlock(&dev->struct_mutex);
3368 /* Look up object handles */
3369 for (i = 0; i < args->buffer_count; i++) {
3370 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3371 exec_list[i].handle);
3372 if (object_list[i] == NULL) {
3373 DRM_ERROR("Invalid object handle %d at index %d\n",
3374 exec_list[i].handle, i);
3379 obj_priv = object_list[i]->driver_private;
3380 if (obj_priv->in_execbuffer) {
3381 DRM_ERROR("Object %p appears more than once in object list\n",
3386 obj_priv->in_execbuffer = true;
3389 /* Pin and relocate */
3390 for (pin_tries = 0; ; pin_tries++) {
3394 for (i = 0; i < args->buffer_count; i++) {
3395 object_list[i]->pending_read_domains = 0;
3396 object_list[i]->pending_write_domain = 0;
3397 ret = i915_gem_object_pin_and_relocate(object_list[i],
3400 &relocs[reloc_index]);
3404 reloc_index += exec_list[i].relocation_count;
3410 /* error other than GTT full, or we've already tried again */
3411 if (ret != -ENOSPC || pin_tries >= 1) {
3412 if (ret != -ERESTARTSYS)
3413 DRM_ERROR("Failed to pin buffers %d\n", ret);
3417 /* unpin all of our buffers */
3418 for (i = 0; i < pinned; i++)
3419 i915_gem_object_unpin(object_list[i]);
3422 /* evict everyone we can from the aperture */
3423 ret = i915_gem_evict_everything(dev);
3428 /* Set the pending read domains for the batch buffer to COMMAND */
3429 batch_obj = object_list[args->buffer_count-1];
3430 if (batch_obj->pending_write_domain) {
3431 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3435 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
3437 /* Sanity check the batch buffer, prior to moving objects */
3438 exec_offset = exec_list[args->buffer_count - 1].offset;
3439 ret = i915_gem_check_execbuffer (args, exec_offset);
3441 DRM_ERROR("execbuf with invalid offset/length\n");
3445 i915_verify_inactive(dev, __FILE__, __LINE__);
3447 /* Zero the global flush/invalidate flags. These
3448 * will be modified as new domains are computed
3451 dev->invalidate_domains = 0;
3452 dev->flush_domains = 0;
3454 for (i = 0; i < args->buffer_count; i++) {
3455 struct drm_gem_object *obj = object_list[i];
3457 /* Compute new gpu domains and update invalidate/flush */
3458 i915_gem_object_set_to_gpu_domain(obj);
3461 i915_verify_inactive(dev, __FILE__, __LINE__);
3463 if (dev->invalidate_domains | dev->flush_domains) {
3465 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3467 dev->invalidate_domains,
3468 dev->flush_domains);
3471 dev->invalidate_domains,
3472 dev->flush_domains);
3473 if (dev->flush_domains)
3474 (void)i915_add_request(dev, file_priv,
3475 dev->flush_domains);
3478 for (i = 0; i < args->buffer_count; i++) {
3479 struct drm_gem_object *obj = object_list[i];
3481 obj->write_domain = obj->pending_write_domain;
3484 i915_verify_inactive(dev, __FILE__, __LINE__);
3487 for (i = 0; i < args->buffer_count; i++) {
3488 i915_gem_object_check_coherency(object_list[i],
3489 exec_list[i].handle);
3494 i915_gem_dump_object(batch_obj,
3500 /* Exec the batchbuffer */
3501 ret = i915_dispatch_gem_execbuffer(dev, args, cliprects, exec_offset);
3503 DRM_ERROR("dispatch failed %d\n", ret);
3508 * Ensure that the commands in the batch buffer are
3509 * finished before the interrupt fires
3511 flush_domains = i915_retire_commands(dev);
3513 i915_verify_inactive(dev, __FILE__, __LINE__);
3516 * Get a seqno representing the execution of the current buffer,
3517 * which we can wait on. We would like to mitigate these interrupts,
3518 * likely by only creating seqnos occasionally (so that we have
3519 * *some* interrupts representing completion of buffers that we can
3520 * wait on when trying to clear up gtt space).
3522 seqno = i915_add_request(dev, file_priv, flush_domains);
3524 for (i = 0; i < args->buffer_count; i++) {
3525 struct drm_gem_object *obj = object_list[i];
3527 i915_gem_object_move_to_active(obj, seqno);
3529 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3533 i915_dump_lru(dev, __func__);
3536 i915_verify_inactive(dev, __FILE__, __LINE__);
3539 for (i = 0; i < pinned; i++)
3540 i915_gem_object_unpin(object_list[i]);
3542 for (i = 0; i < args->buffer_count; i++) {
3543 if (object_list[i]) {
3544 obj_priv = object_list[i]->driver_private;
3545 obj_priv->in_execbuffer = false;
3547 drm_gem_object_unreference(object_list[i]);
3550 mutex_unlock(&dev->struct_mutex);
3553 /* Copy the new buffer offsets back to the user's exec list. */
3554 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
3555 (uintptr_t) args->buffers_ptr,
3557 sizeof(*exec_list) * args->buffer_count);
3560 DRM_ERROR("failed to copy %d exec entries "
3561 "back to user (%d)\n",
3562 args->buffer_count, ret);
3566 /* Copy the updated relocations out regardless of current error
3567 * state. Failure to update the relocs would mean that the next
3568 * time userland calls execbuf, it would do so with presumed offset
3569 * state that didn't match the actual object state.
3571 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
3574 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
3581 drm_free_large(object_list);
3582 drm_free_large(exec_list);
3589 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
3591 struct drm_device *dev = obj->dev;
3592 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3595 i915_verify_inactive(dev, __FILE__, __LINE__);
3596 if (obj_priv->gtt_space == NULL) {
3597 ret = i915_gem_object_bind_to_gtt(obj, alignment);
3599 if (ret != -EBUSY && ret != -ERESTARTSYS)
3600 DRM_ERROR("Failure to bind: %d\n", ret);
3605 * Pre-965 chips need a fence register set up in order to
3606 * properly handle tiled surfaces.
3608 if (!IS_I965G(dev) && obj_priv->tiling_mode != I915_TILING_NONE) {
3609 ret = i915_gem_object_get_fence_reg(obj);
3611 if (ret != -EBUSY && ret != -ERESTARTSYS)
3612 DRM_ERROR("Failure to install fence: %d\n",
3617 obj_priv->pin_count++;
3619 /* If the object is not active and not pending a flush,
3620 * remove it from the inactive list
3622 if (obj_priv->pin_count == 1) {
3623 atomic_inc(&dev->pin_count);
3624 atomic_add(obj->size, &dev->pin_memory);
3625 if (!obj_priv->active &&
3626 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 &&
3627 !list_empty(&obj_priv->list))
3628 list_del_init(&obj_priv->list);
3630 i915_verify_inactive(dev, __FILE__, __LINE__);
3636 i915_gem_object_unpin(struct drm_gem_object *obj)
3638 struct drm_device *dev = obj->dev;
3639 drm_i915_private_t *dev_priv = dev->dev_private;
3640 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3642 i915_verify_inactive(dev, __FILE__, __LINE__);
3643 obj_priv->pin_count--;
3644 BUG_ON(obj_priv->pin_count < 0);
3645 BUG_ON(obj_priv->gtt_space == NULL);
3647 /* If the object is no longer pinned, and is
3648 * neither active nor being flushed, then stick it on
3651 if (obj_priv->pin_count == 0) {
3652 if (!obj_priv->active &&
3653 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
3654 list_move_tail(&obj_priv->list,
3655 &dev_priv->mm.inactive_list);
3656 atomic_dec(&dev->pin_count);
3657 atomic_sub(obj->size, &dev->pin_memory);
3659 i915_verify_inactive(dev, __FILE__, __LINE__);
3663 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3664 struct drm_file *file_priv)
3666 struct drm_i915_gem_pin *args = data;
3667 struct drm_gem_object *obj;
3668 struct drm_i915_gem_object *obj_priv;
3671 mutex_lock(&dev->struct_mutex);
3673 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
3675 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
3677 mutex_unlock(&dev->struct_mutex);
3680 obj_priv = obj->driver_private;
3682 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
3683 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3685 drm_gem_object_unreference(obj);
3686 mutex_unlock(&dev->struct_mutex);
3690 obj_priv->user_pin_count++;
3691 obj_priv->pin_filp = file_priv;
3692 if (obj_priv->user_pin_count == 1) {
3693 ret = i915_gem_object_pin(obj, args->alignment);
3695 drm_gem_object_unreference(obj);
3696 mutex_unlock(&dev->struct_mutex);
3701 /* XXX - flush the CPU caches for pinned objects
3702 * as the X server doesn't manage domains yet
3704 i915_gem_object_flush_cpu_write_domain(obj);
3705 args->offset = obj_priv->gtt_offset;
3706 drm_gem_object_unreference(obj);
3707 mutex_unlock(&dev->struct_mutex);
3713 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3714 struct drm_file *file_priv)
3716 struct drm_i915_gem_pin *args = data;
3717 struct drm_gem_object *obj;
3718 struct drm_i915_gem_object *obj_priv;
3720 mutex_lock(&dev->struct_mutex);
3722 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
3724 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
3726 mutex_unlock(&dev->struct_mutex);
3730 obj_priv = obj->driver_private;
3731 if (obj_priv->pin_filp != file_priv) {
3732 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3734 drm_gem_object_unreference(obj);
3735 mutex_unlock(&dev->struct_mutex);
3738 obj_priv->user_pin_count--;
3739 if (obj_priv->user_pin_count == 0) {
3740 obj_priv->pin_filp = NULL;
3741 i915_gem_object_unpin(obj);
3744 drm_gem_object_unreference(obj);
3745 mutex_unlock(&dev->struct_mutex);
3750 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3751 struct drm_file *file_priv)
3753 struct drm_i915_gem_busy *args = data;
3754 struct drm_gem_object *obj;
3755 struct drm_i915_gem_object *obj_priv;
3757 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
3759 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
3764 mutex_lock(&dev->struct_mutex);
3765 /* Update the active list for the hardware's current position.
3766 * Otherwise this only updates on a delayed timer or when irqs are
3767 * actually unmasked, and our working set ends up being larger than
3770 i915_gem_retire_requests(dev);
3772 obj_priv = obj->driver_private;
3773 /* Don't count being on the flushing list against the object being
3774 * done. Otherwise, a buffer left on the flushing list but not getting
3775 * flushed (because nobody's flushing that domain) won't ever return
3776 * unbusy and get reused by libdrm's bo cache. The other expected
3777 * consumer of this interface, OpenGL's occlusion queries, also specs
3778 * that the objects get unbusy "eventually" without any interference.
3780 args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
3782 drm_gem_object_unreference(obj);
3783 mutex_unlock(&dev->struct_mutex);
3788 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3789 struct drm_file *file_priv)
3791 return i915_gem_ring_throttle(dev, file_priv);
3794 int i915_gem_init_object(struct drm_gem_object *obj)
3796 struct drm_i915_gem_object *obj_priv;
3798 obj_priv = kzalloc(sizeof(*obj_priv), GFP_KERNEL);
3799 if (obj_priv == NULL)
3803 * We've just allocated pages from the kernel,
3804 * so they've just been written by the CPU with
3805 * zeros. They'll need to be clflushed before we
3806 * use them with the GPU.
3808 obj->write_domain = I915_GEM_DOMAIN_CPU;
3809 obj->read_domains = I915_GEM_DOMAIN_CPU;
3811 obj_priv->agp_type = AGP_USER_MEMORY;
3813 obj->driver_private = obj_priv;
3814 obj_priv->obj = obj;
3815 obj_priv->fence_reg = I915_FENCE_REG_NONE;
3816 INIT_LIST_HEAD(&obj_priv->list);
3817 INIT_LIST_HEAD(&obj_priv->fence_list);
3822 void i915_gem_free_object(struct drm_gem_object *obj)
3824 struct drm_device *dev = obj->dev;
3825 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3827 while (obj_priv->pin_count > 0)
3828 i915_gem_object_unpin(obj);
3830 if (obj_priv->phys_obj)
3831 i915_gem_detach_phys_object(dev, obj);
3833 i915_gem_object_unbind(obj);
3835 if (obj_priv->mmap_offset)
3836 i915_gem_free_mmap_offset(obj);
3838 kfree(obj_priv->page_cpu_valid);
3839 kfree(obj_priv->bit_17);
3840 kfree(obj->driver_private);
3843 /** Unbinds all objects that are on the given buffer list. */
3845 i915_gem_evict_from_list(struct drm_device *dev, struct list_head *head)
3847 struct drm_gem_object *obj;
3848 struct drm_i915_gem_object *obj_priv;
3851 while (!list_empty(head)) {
3852 obj_priv = list_first_entry(head,
3853 struct drm_i915_gem_object,
3855 obj = obj_priv->obj;
3857 if (obj_priv->pin_count != 0) {
3858 DRM_ERROR("Pinned object in unbind list\n");
3859 mutex_unlock(&dev->struct_mutex);
3863 ret = i915_gem_object_unbind(obj);
3865 DRM_ERROR("Error unbinding object in LeaveVT: %d\n",
3867 mutex_unlock(&dev->struct_mutex);
3877 i915_gem_idle(struct drm_device *dev)
3879 drm_i915_private_t *dev_priv = dev->dev_private;
3880 uint32_t seqno, cur_seqno, last_seqno;
3883 mutex_lock(&dev->struct_mutex);
3885 if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
3886 mutex_unlock(&dev->struct_mutex);
3890 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3891 * We need to replace this with a semaphore, or something.
3893 dev_priv->mm.suspended = 1;
3894 del_timer(&dev_priv->hangcheck_timer);
3896 /* Cancel the retire work handler, wait for it to finish if running
3898 mutex_unlock(&dev->struct_mutex);
3899 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3900 mutex_lock(&dev->struct_mutex);
3902 i915_kernel_lost_context(dev);
3904 /* Flush the GPU along with all non-CPU write domains
3906 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
3907 seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
3910 mutex_unlock(&dev->struct_mutex);
3914 dev_priv->mm.waiting_gem_seqno = seqno;
3918 cur_seqno = i915_get_gem_seqno(dev);
3919 if (i915_seqno_passed(cur_seqno, seqno))
3921 if (last_seqno == cur_seqno) {
3922 if (stuck++ > 100) {
3923 DRM_ERROR("hardware wedged\n");
3924 atomic_set(&dev_priv->mm.wedged, 1);
3925 DRM_WAKEUP(&dev_priv->irq_queue);
3930 last_seqno = cur_seqno;
3932 dev_priv->mm.waiting_gem_seqno = 0;
3934 i915_gem_retire_requests(dev);
3936 spin_lock(&dev_priv->mm.active_list_lock);
3937 if (!atomic_read(&dev_priv->mm.wedged)) {
3938 /* Active and flushing should now be empty as we've
3939 * waited for a sequence higher than any pending execbuffer
3941 WARN_ON(!list_empty(&dev_priv->mm.active_list));
3942 WARN_ON(!list_empty(&dev_priv->mm.flushing_list));
3943 /* Request should now be empty as we've also waited
3944 * for the last request in the list
3946 WARN_ON(!list_empty(&dev_priv->mm.request_list));
3949 /* Empty the active and flushing lists to inactive. If there's
3950 * anything left at this point, it means that we're wedged and
3951 * nothing good's going to happen by leaving them there. So strip
3952 * the GPU domains and just stuff them onto inactive.
3954 while (!list_empty(&dev_priv->mm.active_list)) {
3955 struct drm_i915_gem_object *obj_priv;
3957 obj_priv = list_first_entry(&dev_priv->mm.active_list,
3958 struct drm_i915_gem_object,
3960 obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
3961 i915_gem_object_move_to_inactive(obj_priv->obj);
3963 spin_unlock(&dev_priv->mm.active_list_lock);
3965 while (!list_empty(&dev_priv->mm.flushing_list)) {
3966 struct drm_i915_gem_object *obj_priv;
3968 obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
3969 struct drm_i915_gem_object,
3971 obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
3972 i915_gem_object_move_to_inactive(obj_priv->obj);
3976 /* Move all inactive buffers out of the GTT. */
3977 ret = i915_gem_evict_from_list(dev, &dev_priv->mm.inactive_list);
3978 WARN_ON(!list_empty(&dev_priv->mm.inactive_list));
3980 mutex_unlock(&dev->struct_mutex);
3984 i915_gem_cleanup_ringbuffer(dev);
3985 mutex_unlock(&dev->struct_mutex);
3991 i915_gem_init_hws(struct drm_device *dev)
3993 drm_i915_private_t *dev_priv = dev->dev_private;
3994 struct drm_gem_object *obj;
3995 struct drm_i915_gem_object *obj_priv;
3998 /* If we need a physical address for the status page, it's already
3999 * initialized at driver load time.
4001 if (!I915_NEED_GFX_HWS(dev))
4004 obj = drm_gem_object_alloc(dev, 4096);
4006 DRM_ERROR("Failed to allocate status page\n");
4009 obj_priv = obj->driver_private;
4010 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4012 ret = i915_gem_object_pin(obj, 4096);
4014 drm_gem_object_unreference(obj);
4018 dev_priv->status_gfx_addr = obj_priv->gtt_offset;
4020 dev_priv->hw_status_page = kmap(obj_priv->pages[0]);
4021 if (dev_priv->hw_status_page == NULL) {
4022 DRM_ERROR("Failed to map status page.\n");
4023 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4024 i915_gem_object_unpin(obj);
4025 drm_gem_object_unreference(obj);
4028 dev_priv->hws_obj = obj;
4029 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
4030 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
4031 I915_READ(HWS_PGA); /* posting read */
4032 DRM_DEBUG("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
4038 i915_gem_cleanup_hws(struct drm_device *dev)
4040 drm_i915_private_t *dev_priv = dev->dev_private;
4041 struct drm_gem_object *obj;
4042 struct drm_i915_gem_object *obj_priv;
4044 if (dev_priv->hws_obj == NULL)
4047 obj = dev_priv->hws_obj;
4048 obj_priv = obj->driver_private;
4050 kunmap(obj_priv->pages[0]);
4051 i915_gem_object_unpin(obj);
4052 drm_gem_object_unreference(obj);
4053 dev_priv->hws_obj = NULL;
4055 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4056 dev_priv->hw_status_page = NULL;
4058 /* Write high address into HWS_PGA when disabling. */
4059 I915_WRITE(HWS_PGA, 0x1ffff000);
4063 i915_gem_init_ringbuffer(struct drm_device *dev)
4065 drm_i915_private_t *dev_priv = dev->dev_private;
4066 struct drm_gem_object *obj;
4067 struct drm_i915_gem_object *obj_priv;
4068 drm_i915_ring_buffer_t *ring = &dev_priv->ring;
4072 ret = i915_gem_init_hws(dev);
4076 obj = drm_gem_object_alloc(dev, 128 * 1024);
4078 DRM_ERROR("Failed to allocate ringbuffer\n");
4079 i915_gem_cleanup_hws(dev);
4082 obj_priv = obj->driver_private;
4084 ret = i915_gem_object_pin(obj, 4096);
4086 drm_gem_object_unreference(obj);
4087 i915_gem_cleanup_hws(dev);
4091 /* Set up the kernel mapping for the ring. */
4092 ring->Size = obj->size;
4094 ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
4095 ring->map.size = obj->size;
4097 ring->map.flags = 0;
4100 drm_core_ioremap_wc(&ring->map, dev);
4101 if (ring->map.handle == NULL) {
4102 DRM_ERROR("Failed to map ringbuffer.\n");
4103 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4104 i915_gem_object_unpin(obj);
4105 drm_gem_object_unreference(obj);
4106 i915_gem_cleanup_hws(dev);
4109 ring->ring_obj = obj;
4110 ring->virtual_start = ring->map.handle;
4112 /* Stop the ring if it's running. */
4113 I915_WRITE(PRB0_CTL, 0);
4114 I915_WRITE(PRB0_TAIL, 0);
4115 I915_WRITE(PRB0_HEAD, 0);
4117 /* Initialize the ring. */
4118 I915_WRITE(PRB0_START, obj_priv->gtt_offset);
4119 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4121 /* G45 ring initialization fails to reset head to zero */
4123 DRM_ERROR("Ring head not reset to zero "
4124 "ctl %08x head %08x tail %08x start %08x\n",
4125 I915_READ(PRB0_CTL),
4126 I915_READ(PRB0_HEAD),
4127 I915_READ(PRB0_TAIL),
4128 I915_READ(PRB0_START));
4129 I915_WRITE(PRB0_HEAD, 0);
4131 DRM_ERROR("Ring head forced to zero "
4132 "ctl %08x head %08x tail %08x start %08x\n",
4133 I915_READ(PRB0_CTL),
4134 I915_READ(PRB0_HEAD),
4135 I915_READ(PRB0_TAIL),
4136 I915_READ(PRB0_START));
4139 I915_WRITE(PRB0_CTL,
4140 ((obj->size - 4096) & RING_NR_PAGES) |
4144 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4146 /* If the head is still not zero, the ring is dead */
4148 DRM_ERROR("Ring initialization failed "
4149 "ctl %08x head %08x tail %08x start %08x\n",
4150 I915_READ(PRB0_CTL),
4151 I915_READ(PRB0_HEAD),
4152 I915_READ(PRB0_TAIL),
4153 I915_READ(PRB0_START));
4157 /* Update our cache of the ring state */
4158 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4159 i915_kernel_lost_context(dev);
4161 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4162 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
4163 ring->space = ring->head - (ring->tail + 8);
4164 if (ring->space < 0)
4165 ring->space += ring->Size;
4172 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4174 drm_i915_private_t *dev_priv = dev->dev_private;
4176 if (dev_priv->ring.ring_obj == NULL)
4179 drm_core_ioremapfree(&dev_priv->ring.map, dev);
4181 i915_gem_object_unpin(dev_priv->ring.ring_obj);
4182 drm_gem_object_unreference(dev_priv->ring.ring_obj);
4183 dev_priv->ring.ring_obj = NULL;
4184 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4186 i915_gem_cleanup_hws(dev);
4190 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4191 struct drm_file *file_priv)
4193 drm_i915_private_t *dev_priv = dev->dev_private;
4196 if (drm_core_check_feature(dev, DRIVER_MODESET))
4199 if (atomic_read(&dev_priv->mm.wedged)) {
4200 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4201 atomic_set(&dev_priv->mm.wedged, 0);
4204 mutex_lock(&dev->struct_mutex);
4205 dev_priv->mm.suspended = 0;
4207 ret = i915_gem_init_ringbuffer(dev);
4209 mutex_unlock(&dev->struct_mutex);
4213 spin_lock(&dev_priv->mm.active_list_lock);
4214 BUG_ON(!list_empty(&dev_priv->mm.active_list));
4215 spin_unlock(&dev_priv->mm.active_list_lock);
4217 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4218 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4219 BUG_ON(!list_empty(&dev_priv->mm.request_list));
4220 mutex_unlock(&dev->struct_mutex);
4222 drm_irq_install(dev);
4228 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4229 struct drm_file *file_priv)
4233 if (drm_core_check_feature(dev, DRIVER_MODESET))
4236 ret = i915_gem_idle(dev);
4237 drm_irq_uninstall(dev);
4243 i915_gem_lastclose(struct drm_device *dev)
4247 if (drm_core_check_feature(dev, DRIVER_MODESET))
4250 ret = i915_gem_idle(dev);
4252 DRM_ERROR("failed to idle hardware: %d\n", ret);
4256 i915_gem_load(struct drm_device *dev)
4259 drm_i915_private_t *dev_priv = dev->dev_private;
4261 spin_lock_init(&dev_priv->mm.active_list_lock);
4262 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4263 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4264 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4265 INIT_LIST_HEAD(&dev_priv->mm.request_list);
4266 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4267 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4268 i915_gem_retire_work_handler);
4269 dev_priv->mm.next_gem_seqno = 1;
4271 spin_lock(&shrink_list_lock);
4272 list_add(&dev_priv->mm.shrink_list, &shrink_list);
4273 spin_unlock(&shrink_list_lock);
4275 /* Old X drivers will take 0-2 for front, back, depth buffers */
4276 dev_priv->fence_reg_start = 3;
4278 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4279 dev_priv->num_fence_regs = 16;
4281 dev_priv->num_fence_regs = 8;
4283 /* Initialize fence registers to zero */
4284 if (IS_I965G(dev)) {
4285 for (i = 0; i < 16; i++)
4286 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4288 for (i = 0; i < 8; i++)
4289 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4290 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4291 for (i = 0; i < 8; i++)
4292 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4295 i915_gem_detect_bit_6_swizzle(dev);
4299 * Create a physically contiguous memory object for this object
4300 * e.g. for cursor + overlay regs
4302 int i915_gem_init_phys_object(struct drm_device *dev,
4305 drm_i915_private_t *dev_priv = dev->dev_private;
4306 struct drm_i915_gem_phys_object *phys_obj;
4309 if (dev_priv->mm.phys_objs[id - 1] || !size)
4312 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4318 phys_obj->handle = drm_pci_alloc(dev, size, 0, 0xffffffff);
4319 if (!phys_obj->handle) {
4324 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4327 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4335 void i915_gem_free_phys_object(struct drm_device *dev, int id)
4337 drm_i915_private_t *dev_priv = dev->dev_private;
4338 struct drm_i915_gem_phys_object *phys_obj;
4340 if (!dev_priv->mm.phys_objs[id - 1])
4343 phys_obj = dev_priv->mm.phys_objs[id - 1];
4344 if (phys_obj->cur_obj) {
4345 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4349 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4351 drm_pci_free(dev, phys_obj->handle);
4353 dev_priv->mm.phys_objs[id - 1] = NULL;
4356 void i915_gem_free_all_phys_object(struct drm_device *dev)
4360 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4361 i915_gem_free_phys_object(dev, i);
4364 void i915_gem_detach_phys_object(struct drm_device *dev,
4365 struct drm_gem_object *obj)
4367 struct drm_i915_gem_object *obj_priv;
4372 obj_priv = obj->driver_private;
4373 if (!obj_priv->phys_obj)
4376 ret = i915_gem_object_get_pages(obj);
4380 page_count = obj->size / PAGE_SIZE;
4382 for (i = 0; i < page_count; i++) {
4383 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
4384 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4386 memcpy(dst, src, PAGE_SIZE);
4387 kunmap_atomic(dst, KM_USER0);
4389 drm_clflush_pages(obj_priv->pages, page_count);
4390 drm_agp_chipset_flush(dev);
4392 i915_gem_object_put_pages(obj);
4394 obj_priv->phys_obj->cur_obj = NULL;
4395 obj_priv->phys_obj = NULL;
4399 i915_gem_attach_phys_object(struct drm_device *dev,
4400 struct drm_gem_object *obj, int id)
4402 drm_i915_private_t *dev_priv = dev->dev_private;
4403 struct drm_i915_gem_object *obj_priv;
4408 if (id > I915_MAX_PHYS_OBJECT)
4411 obj_priv = obj->driver_private;
4413 if (obj_priv->phys_obj) {
4414 if (obj_priv->phys_obj->id == id)
4416 i915_gem_detach_phys_object(dev, obj);
4420 /* create a new object */
4421 if (!dev_priv->mm.phys_objs[id - 1]) {
4422 ret = i915_gem_init_phys_object(dev, id,
4425 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
4430 /* bind to the object */
4431 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4432 obj_priv->phys_obj->cur_obj = obj;
4434 ret = i915_gem_object_get_pages(obj);
4436 DRM_ERROR("failed to get page list\n");
4440 page_count = obj->size / PAGE_SIZE;
4442 for (i = 0; i < page_count; i++) {
4443 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
4444 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4446 memcpy(dst, src, PAGE_SIZE);
4447 kunmap_atomic(src, KM_USER0);
4450 i915_gem_object_put_pages(obj);
4458 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4459 struct drm_i915_gem_pwrite *args,
4460 struct drm_file *file_priv)
4462 struct drm_i915_gem_object *obj_priv = obj->driver_private;
4465 char __user *user_data;
4467 user_data = (char __user *) (uintptr_t) args->data_ptr;
4468 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4470 DRM_DEBUG("obj_addr %p, %lld\n", obj_addr, args->size);
4471 ret = copy_from_user(obj_addr, user_data, args->size);
4475 drm_agp_chipset_flush(dev);
4479 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
4481 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
4483 /* Clean up our request list when the client is going away, so that
4484 * later retire_requests won't dereference our soon-to-be-gone
4487 mutex_lock(&dev->struct_mutex);
4488 while (!list_empty(&i915_file_priv->mm.request_list))
4489 list_del_init(i915_file_priv->mm.request_list.next);
4490 mutex_unlock(&dev->struct_mutex);
4493 /* Immediately discard the backing storage */
4495 i915_gem_object_truncate(struct drm_gem_object *obj)
4497 struct inode *inode;
4499 inode = obj->filp->f_path.dentry->d_inode;
4501 mutex_lock(&inode->i_mutex);
4502 truncate_inode_pages(inode->i_mapping, 0);
4503 mutex_unlock(&inode->i_mutex);
4507 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
4509 return !obj_priv->dirty;
4513 i915_gem_shrink(int nr_to_scan, gfp_t gfp_mask)
4515 drm_i915_private_t *dev_priv, *next_dev;
4516 struct drm_i915_gem_object *obj_priv, *next_obj;
4518 int would_deadlock = 1;
4520 /* "fast-path" to count number of available objects */
4521 if (nr_to_scan == 0) {
4522 spin_lock(&shrink_list_lock);
4523 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4524 struct drm_device *dev = dev_priv->dev;
4526 if (mutex_trylock(&dev->struct_mutex)) {
4527 list_for_each_entry(obj_priv,
4528 &dev_priv->mm.inactive_list,
4531 mutex_unlock(&dev->struct_mutex);
4534 spin_unlock(&shrink_list_lock);
4536 return (cnt / 100) * sysctl_vfs_cache_pressure;
4539 spin_lock(&shrink_list_lock);
4541 /* first scan for clean buffers */
4542 list_for_each_entry_safe(dev_priv, next_dev,
4543 &shrink_list, mm.shrink_list) {
4544 struct drm_device *dev = dev_priv->dev;
4546 if (! mutex_trylock(&dev->struct_mutex))
4549 spin_unlock(&shrink_list_lock);
4551 i915_gem_retire_requests(dev);
4553 list_for_each_entry_safe(obj_priv, next_obj,
4554 &dev_priv->mm.inactive_list,
4556 if (i915_gem_object_is_purgeable(obj_priv)) {
4557 struct drm_gem_object *obj = obj_priv->obj;
4558 i915_gem_object_unbind(obj);
4559 i915_gem_object_truncate(obj);
4561 if (--nr_to_scan <= 0)
4566 spin_lock(&shrink_list_lock);
4567 mutex_unlock(&dev->struct_mutex);
4569 if (nr_to_scan <= 0)
4573 /* second pass, evict/count anything still on the inactive list */
4574 list_for_each_entry_safe(dev_priv, next_dev,
4575 &shrink_list, mm.shrink_list) {
4576 struct drm_device *dev = dev_priv->dev;
4578 if (! mutex_trylock(&dev->struct_mutex))
4581 spin_unlock(&shrink_list_lock);
4583 list_for_each_entry_safe(obj_priv, next_obj,
4584 &dev_priv->mm.inactive_list,
4586 if (nr_to_scan > 0) {
4587 struct drm_gem_object *obj = obj_priv->obj;
4588 i915_gem_object_unbind(obj);
4589 if (i915_gem_object_is_purgeable(obj_priv))
4590 i915_gem_object_truncate(obj);
4597 spin_lock(&shrink_list_lock);
4598 mutex_unlock(&dev->struct_mutex);
4603 spin_unlock(&shrink_list_lock);
4608 return (cnt / 100) * sysctl_vfs_cache_pressure;
4613 static struct shrinker shrinker = {
4614 .shrink = i915_gem_shrink,
4615 .seeks = DEFAULT_SEEKS,
4619 i915_gem_shrinker_init(void)
4621 register_shrinker(&shrinker);
4625 i915_gem_shrinker_exit(void)
4627 unregister_shrinker(&shrinker);