1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
35 #include "intel_bios.h"
36 #include <linux/io-mapping.h>
38 /* General customization:
41 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
43 #define DRIVER_NAME "i915"
44 #define DRIVER_DESC "Intel Graphics"
45 #define DRIVER_DATE "20080730"
57 #define I915_NUM_PIPE 2
59 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
64 * 1.2: Add Power Management
65 * 1.3: Add vblank support
66 * 1.4: Fix cmdbuffer path, add heap destroy
67 * 1.5: Add vblank pipe configuration
68 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
69 * - Support vertical blank on secondary display pipe
71 #define DRIVER_MAJOR 1
72 #define DRIVER_MINOR 6
73 #define DRIVER_PATCHLEVEL 0
75 #define WATCH_COHERENCY 0
80 #define WATCH_INACTIVE 0
81 #define WATCH_PWRITE 0
83 #define I915_GEM_PHYS_CURSOR_0 1
84 #define I915_GEM_PHYS_CURSOR_1 2
85 #define I915_GEM_PHYS_OVERLAY_REGS 3
86 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
88 struct drm_i915_gem_phys_object {
90 struct page **page_list;
91 drm_dma_handle_t *handle;
92 struct drm_gem_object *cur_obj;
95 typedef struct _drm_i915_ring_buffer {
102 struct drm_gem_object *ring_obj;
103 } drm_i915_ring_buffer_t;
106 struct mem_block *next;
107 struct mem_block *prev;
110 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
113 struct opregion_header;
114 struct opregion_acpi;
115 struct opregion_swsci;
116 struct opregion_asle;
118 struct intel_opregion {
119 struct opregion_header *header;
120 struct opregion_acpi *acpi;
121 struct opregion_swsci *swsci;
122 struct opregion_asle *asle;
126 struct drm_i915_master_private {
127 drm_local_map_t *sarea;
128 struct _drm_i915_sarea *sarea_priv;
130 #define I915_FENCE_REG_NONE -1
132 struct drm_i915_fence_reg {
133 struct drm_gem_object *obj;
134 struct list_head lru_list;
137 struct sdvo_device_mapping {
145 struct drm_i915_error_state {
160 struct drm_i915_error_object {
164 } *ringbuffer, *batchbuffer[2];
165 struct drm_i915_error_buffer {
181 struct drm_i915_display_funcs {
182 void (*dpms)(struct drm_crtc *crtc, int mode);
183 bool (*fbc_enabled)(struct drm_device *dev);
184 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
185 void (*disable_fbc)(struct drm_device *dev);
186 int (*get_display_clock_speed)(struct drm_device *dev);
187 int (*get_fifo_size)(struct drm_device *dev, int plane);
188 void (*update_wm)(struct drm_device *dev, int planea_clock,
189 int planeb_clock, int sr_hdisplay, int pixel_size);
190 /* clock updates for mode set */
192 /* render clock increase/decrease */
193 /* display clock increase/decrease */
194 /* pll clock increase/decrease */
195 /* clock gating init */
198 struct intel_overlay;
200 struct intel_device_info {
217 u8 has_pipe_cxsr : 1;
219 u8 cursor_needs_physical : 1;
223 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
224 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
225 FBC_MODE_TOO_LARGE, /* mode too large for compression */
226 FBC_BAD_PLANE, /* fbc not supported on plane */
227 FBC_NOT_TILED, /* buffer not tiled */
231 PCH_IBX, /* Ibexpeak PCH */
232 PCH_CPT, /* Cougarpoint PCH */
237 typedef struct drm_i915_private {
238 struct drm_device *dev;
240 const struct intel_device_info *info;
246 struct pci_dev *bridge_dev;
247 drm_i915_ring_buffer_t render_ring;
249 drm_dma_handle_t *status_page_dmah;
250 void *hw_status_page;
252 dma_addr_t dma_status_page;
254 unsigned int status_gfx_addr;
255 unsigned int seqno_gfx_addr;
256 drm_local_map_t hws_map;
257 struct drm_gem_object *hws_obj;
258 struct drm_gem_object *seqno_obj;
259 struct drm_gem_object *pwrctx;
261 struct resource mch_res;
269 wait_queue_head_t irq_queue;
270 atomic_t irq_received;
271 /** Protects user_irq_refcount and irq_mask_reg */
272 spinlock_t user_irq_lock;
273 /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
274 int user_irq_refcount;
276 /** Cached value of IMR to avoid reads in updating the bitfield */
279 /** splitted irq regs for graphics and display engine on Ironlake,
280 irq_mask_reg is still used for display irq. */
282 u32 gt_irq_enable_reg;
283 u32 de_irq_enable_reg;
284 u32 pch_irq_mask_reg;
285 u32 pch_irq_enable_reg;
287 u32 hotplug_supported_mask;
288 struct work_struct hotplug_work;
290 int tex_lru_log_granularity;
291 int allow_batchbuffer;
292 struct mem_block *agp_heap;
293 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
296 /* For hangcheck timer */
297 #define DRM_I915_HANGCHECK_PERIOD 75 /* in jiffies */
298 struct timer_list hangcheck_timer;
304 unsigned long cfb_size;
305 unsigned long cfb_pitch;
311 struct intel_opregion opregion;
314 struct intel_overlay *overlay;
317 int backlight_duty_cycle; /* restore backlight to this value */
318 bool panel_wants_dither;
319 struct drm_display_mode *panel_fixed_mode;
320 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
321 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
323 /* Feature bits from the VBIOS */
324 unsigned int int_tv_support:1;
325 unsigned int lvds_dither:1;
326 unsigned int lvds_vbt:1;
327 unsigned int int_crt_support:1;
328 unsigned int lvds_use_ssc:1;
329 unsigned int edp_support:1;
333 struct notifier_block lid_notifier;
335 int crt_ddc_bus; /* 0 = unknown, else GPIO to use for CRT DDC */
336 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
337 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
338 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
340 unsigned int fsb_freq, mem_freq;
342 spinlock_t error_lock;
343 struct drm_i915_error_state *first_error;
344 struct work_struct error_work;
345 struct workqueue_struct *wq;
347 /* Display functions */
348 struct drm_i915_display_funcs display;
350 /* PCH chipset type */
351 enum intel_pch pch_type;
376 u32 saveTRANS_HTOTAL_A;
377 u32 saveTRANS_HBLANK_A;
378 u32 saveTRANS_HSYNC_A;
379 u32 saveTRANS_VTOTAL_A;
380 u32 saveTRANS_VBLANK_A;
381 u32 saveTRANS_VSYNC_A;
389 u32 savePFIT_PGM_RATIOS;
390 u32 saveBLC_HIST_CTL;
392 u32 saveBLC_PWM_CTL2;
393 u32 saveBLC_CPU_PWM_CTL;
394 u32 saveBLC_CPU_PWM_CTL2;
407 u32 saveTRANS_HTOTAL_B;
408 u32 saveTRANS_HBLANK_B;
409 u32 saveTRANS_HSYNC_B;
410 u32 saveTRANS_VTOTAL_B;
411 u32 saveTRANS_VBLANK_B;
412 u32 saveTRANS_VSYNC_B;
426 u32 savePP_ON_DELAYS;
427 u32 savePP_OFF_DELAYS;
435 u32 savePFIT_CONTROL;
436 u32 save_palette_a[256];
437 u32 save_palette_b[256];
438 u32 saveDPFC_CB_BASE;
439 u32 saveFBC_CFB_BASE;
442 u32 saveFBC_CONTROL2;
452 u32 saveCACHE_MODE_0;
453 u32 saveMI_ARB_STATE;
464 uint64_t saveFENCE[16];
475 u32 savePIPEA_GMCH_DATA_M;
476 u32 savePIPEB_GMCH_DATA_M;
477 u32 savePIPEA_GMCH_DATA_N;
478 u32 savePIPEB_GMCH_DATA_N;
479 u32 savePIPEA_DP_LINK_M;
480 u32 savePIPEB_DP_LINK_M;
481 u32 savePIPEA_DP_LINK_N;
482 u32 savePIPEB_DP_LINK_N;
493 u32 savePCH_DREF_CONTROL;
494 u32 saveDISP_ARB_CTL;
495 u32 savePIPEA_DATA_M1;
496 u32 savePIPEA_DATA_N1;
497 u32 savePIPEA_LINK_M1;
498 u32 savePIPEA_LINK_N1;
499 u32 savePIPEB_DATA_M1;
500 u32 savePIPEB_DATA_N1;
501 u32 savePIPEB_LINK_M1;
502 u32 savePIPEB_LINK_N1;
503 u32 saveMCHBAR_RENDER_STANDBY;
506 struct drm_mm gtt_space;
508 struct io_mapping *gtt_mapping;
512 * Membership on list of all loaded devices, used to evict
513 * inactive buffers under memory pressure.
515 * Modifications should only be done whilst holding the
516 * shrink_list_lock spinlock.
518 struct list_head shrink_list;
521 * List of objects currently involved in rendering from the
524 * Includes buffers having the contents of their GPU caches
525 * flushed, not necessarily primitives. last_rendering_seqno
526 * represents when the rendering involved will be completed.
528 * A reference is held on the buffer while on this list.
530 spinlock_t active_list_lock;
531 struct list_head active_list;
534 * List of objects which are not in the ringbuffer but which
535 * still have a write_domain which needs to be flushed before
538 * last_rendering_seqno is 0 while an object is in this list.
540 * A reference is held on the buffer while on this list.
542 struct list_head flushing_list;
545 * List of objects currently pending a GPU write flush.
547 * All elements on this list will belong to either the
548 * active_list or flushing_list, last_rendering_seqno can
549 * be used to differentiate between the two elements.
551 struct list_head gpu_write_list;
554 * LRU list of objects which are not in the ringbuffer and
555 * are ready to unbind, but are still in the GTT.
557 * last_rendering_seqno is 0 while an object is in this list.
559 * A reference is not held on the buffer while on this list,
560 * as merely being GTT-bound shouldn't prevent its being
561 * freed, and we'll pull it off the list in the free path.
563 struct list_head inactive_list;
565 /** LRU list of objects with fence regs on them. */
566 struct list_head fence_list;
569 * List of breadcrumbs associated with GPU requests currently
572 struct list_head request_list;
575 * We leave the user IRQ off as much as possible,
576 * but this means that requests will finish and never
577 * be retired once the system goes idle. Set a timer to
578 * fire periodically while the ring is running. When it
579 * fires, go retire requests.
581 struct delayed_work retire_work;
583 uint32_t next_gem_seqno;
586 * Waiting sequence number, if any
588 uint32_t waiting_gem_seqno;
591 * Last seq seen at irq time
593 uint32_t irq_gem_seqno;
596 * Flag if the X Server, and thus DRM, is not currently in
597 * control of the device.
599 * This is set between LeaveVT and EnterVT. It needs to be
600 * replaced with a semaphore. It also needs to be
601 * transitioned away from for kernel modesetting.
606 * Flag if the hardware appears to be wedged.
608 * This is set when attempts to idle the device timeout.
609 * It prevents command submission from occuring and makes
610 * every pending request fail
614 /** Bit 6 swizzling required for X tiling */
615 uint32_t bit_6_swizzle_x;
616 /** Bit 6 swizzling required for Y tiling */
617 uint32_t bit_6_swizzle_y;
619 /* storage for physical objects */
620 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
622 struct sdvo_device_mapping sdvo_mappings[2];
623 /* indicate whether the LVDS_BORDER should be enabled or not */
624 unsigned int lvds_border_bits;
626 struct drm_crtc *plane_to_crtc_mapping[2];
627 struct drm_crtc *pipe_to_crtc_mapping[2];
628 wait_queue_head_t pending_flip_queue;
630 /* Reclocking support */
631 bool render_reclock_avail;
632 bool lvds_downclock_avail;
633 /* indicate whether the LVDS EDID is OK */
635 /* indicates the reduced downclock for LVDS*/
637 struct work_struct idle_work;
638 struct timer_list idle_timer;
642 struct child_device_config *child_dev;
643 struct drm_connector *int_lvds_connector;
645 bool mchbar_need_disable;
651 enum no_fbc_reason no_fbc_reason;
653 struct drm_mm_node *compressed_fb;
654 struct drm_mm_node *compressed_llb;
656 /* list of fbdev register on this device */
657 struct intel_fbdev *fbdev;
658 } drm_i915_private_t;
660 /** driver private structure attached to each drm_gem_object */
661 struct drm_i915_gem_object {
662 struct drm_gem_object base;
664 /** Current space allocated to this object in the GTT, if any. */
665 struct drm_mm_node *gtt_space;
667 /** This object's place on the active/flushing/inactive lists */
668 struct list_head list;
669 /** This object's place on GPU write list */
670 struct list_head gpu_write_list;
673 * This is set if the object is on the active or flushing lists
674 * (has pending rendering), and is not set if it's on inactive (ready
680 * This is set if the object has been written to since last bound
685 /** AGP memory structure for our GTT binding. */
686 DRM_AGP_MEM *agp_mem;
692 * Current offset of the object in GTT space.
694 * This is the same as gtt_space->start
699 * Fake offset for use by mmap(2)
701 uint64_t mmap_offset;
704 * Fence register bits (if any) for this object. Will be set
705 * as needed when mapped into the GTT.
706 * Protected by dev->struct_mutex.
710 /** How many users have pinned this object in GTT space */
713 /** Breadcrumb of last rendering to the buffer. */
714 uint32_t last_rendering_seqno;
716 /** Current tiling mode for the object. */
717 uint32_t tiling_mode;
720 /** Record of address bit 17 of each page at last unbind. */
723 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
727 * If present, while GEM_DOMAIN_CPU is in the read domain this array
728 * flags which individual pages are valid.
730 uint8_t *page_cpu_valid;
732 /** User space pin count and filp owning the pin */
733 uint32_t user_pin_count;
734 struct drm_file *pin_filp;
736 /** for phy allocated objects */
737 struct drm_i915_gem_phys_object *phys_obj;
740 * Used for checking the object doesn't appear more than once
741 * in an execbuffer object list.
746 * Advice: are the backing pages purgeable?
751 * Number of crtcs where this object is currently the fb, but
752 * will be page flipped away on the next vblank. When it
753 * reaches 0, dev_priv->pending_flip_queue will be woken up.
755 atomic_t pending_flip;
758 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
761 * Request queue structure.
763 * The request queue allows us to note sequence numbers that have been emitted
764 * and may be associated with active buffers to be retired.
766 * By keeping this list, we can avoid having to do questionable
767 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
768 * an emission time with seqnos for tracking how far ahead of the GPU we are.
770 struct drm_i915_gem_request {
771 /** GEM sequence number associated with this request. */
774 /** Time at which this request was emitted, in jiffies. */
775 unsigned long emitted_jiffies;
777 /** global list entry for this request */
778 struct list_head list;
780 /** file_priv list entry for this request */
781 struct list_head client_list;
784 struct drm_i915_file_private {
786 struct list_head request_list;
790 enum intel_chip_family {
797 extern struct drm_ioctl_desc i915_ioctls[];
798 extern int i915_max_ioctl;
799 extern unsigned int i915_fbpercrtc;
800 extern unsigned int i915_powersave;
801 extern unsigned int i915_lvds_downclock;
803 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
804 extern int i915_resume(struct drm_device *dev);
805 extern void i915_save_display(struct drm_device *dev);
806 extern void i915_restore_display(struct drm_device *dev);
807 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
808 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
811 extern void i915_kernel_lost_context(struct drm_device * dev);
812 extern int i915_driver_load(struct drm_device *, unsigned long flags);
813 extern int i915_driver_unload(struct drm_device *);
814 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
815 extern void i915_driver_lastclose(struct drm_device * dev);
816 extern void i915_driver_preclose(struct drm_device *dev,
817 struct drm_file *file_priv);
818 extern void i915_driver_postclose(struct drm_device *dev,
819 struct drm_file *file_priv);
820 extern int i915_driver_device_is_agp(struct drm_device * dev);
821 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
823 extern int i915_emit_box(struct drm_device *dev,
824 struct drm_clip_rect *boxes,
825 int i, int DR1, int DR4);
826 extern int i965_reset(struct drm_device *dev, u8 flags);
829 void i915_hangcheck_elapsed(unsigned long data);
830 void i915_destroy_error_state(struct drm_device *dev);
831 extern int i915_irq_emit(struct drm_device *dev, void *data,
832 struct drm_file *file_priv);
833 extern int i915_irq_wait(struct drm_device *dev, void *data,
834 struct drm_file *file_priv);
835 void i915_user_irq_get(struct drm_device *dev);
836 void i915_trace_irq_get(struct drm_device *dev, u32 seqno);
837 void i915_user_irq_put(struct drm_device *dev);
838 extern void i915_enable_interrupt (struct drm_device *dev);
840 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
841 extern void i915_driver_irq_preinstall(struct drm_device * dev);
842 extern int i915_driver_irq_postinstall(struct drm_device *dev);
843 extern void i915_driver_irq_uninstall(struct drm_device * dev);
844 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
845 struct drm_file *file_priv);
846 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
847 struct drm_file *file_priv);
848 extern int i915_enable_vblank(struct drm_device *dev, int crtc);
849 extern void i915_disable_vblank(struct drm_device *dev, int crtc);
850 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
851 extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
852 extern int i915_vblank_swap(struct drm_device *dev, void *data,
853 struct drm_file *file_priv);
854 extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
855 extern void i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask);
856 void ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask);
857 void ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask);
860 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
863 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
865 void intel_enable_asle (struct drm_device *dev);
869 extern int i915_mem_alloc(struct drm_device *dev, void *data,
870 struct drm_file *file_priv);
871 extern int i915_mem_free(struct drm_device *dev, void *data,
872 struct drm_file *file_priv);
873 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
874 struct drm_file *file_priv);
875 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
876 struct drm_file *file_priv);
877 extern void i915_mem_takedown(struct mem_block **heap);
878 extern void i915_mem_release(struct drm_device * dev,
879 struct drm_file *file_priv, struct mem_block *heap);
881 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
882 struct drm_file *file_priv);
883 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
884 struct drm_file *file_priv);
885 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
886 struct drm_file *file_priv);
887 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
888 struct drm_file *file_priv);
889 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
890 struct drm_file *file_priv);
891 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
892 struct drm_file *file_priv);
893 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
894 struct drm_file *file_priv);
895 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
896 struct drm_file *file_priv);
897 int i915_gem_execbuffer(struct drm_device *dev, void *data,
898 struct drm_file *file_priv);
899 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
900 struct drm_file *file_priv);
901 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
902 struct drm_file *file_priv);
903 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
904 struct drm_file *file_priv);
905 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
906 struct drm_file *file_priv);
907 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
908 struct drm_file *file_priv);
909 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
910 struct drm_file *file_priv);
911 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
912 struct drm_file *file_priv);
913 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
914 struct drm_file *file_priv);
915 int i915_gem_set_tiling(struct drm_device *dev, void *data,
916 struct drm_file *file_priv);
917 int i915_gem_get_tiling(struct drm_device *dev, void *data,
918 struct drm_file *file_priv);
919 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
920 struct drm_file *file_priv);
921 void i915_gem_load(struct drm_device *dev);
922 int i915_gem_init_object(struct drm_gem_object *obj);
923 struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
925 void i915_gem_free_object(struct drm_gem_object *obj);
926 int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
927 void i915_gem_object_unpin(struct drm_gem_object *obj);
928 int i915_gem_object_unbind(struct drm_gem_object *obj);
929 void i915_gem_release_mmap(struct drm_gem_object *obj);
930 void i915_gem_lastclose(struct drm_device *dev);
931 uint32_t i915_get_gem_seqno(struct drm_device *dev);
932 bool i915_seqno_passed(uint32_t seq1, uint32_t seq2);
933 int i915_gem_object_get_fence_reg(struct drm_gem_object *obj);
934 int i915_gem_object_put_fence_reg(struct drm_gem_object *obj);
935 void i915_gem_retire_requests(struct drm_device *dev);
936 void i915_gem_retire_work_handler(struct work_struct *work);
937 void i915_gem_clflush_object(struct drm_gem_object *obj);
938 int i915_gem_object_set_domain(struct drm_gem_object *obj,
939 uint32_t read_domains,
940 uint32_t write_domain);
941 int i915_gem_init_ringbuffer(struct drm_device *dev);
942 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
943 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
945 int i915_gem_idle(struct drm_device *dev);
946 uint32_t i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
947 uint32_t flush_domains);
948 int i915_do_wait_request(struct drm_device *dev, uint32_t seqno, int interruptible);
949 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
950 int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
952 int i915_gem_object_set_to_display_plane(struct drm_gem_object *obj);
953 int i915_gem_attach_phys_object(struct drm_device *dev,
954 struct drm_gem_object *obj, int id);
955 void i915_gem_detach_phys_object(struct drm_device *dev,
956 struct drm_gem_object *obj);
957 void i915_gem_free_all_phys_object(struct drm_device *dev);
958 int i915_gem_object_get_pages(struct drm_gem_object *obj, gfp_t gfpmask);
959 void i915_gem_object_put_pages(struct drm_gem_object *obj);
960 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv);
961 void i915_gem_object_flush_write_domain(struct drm_gem_object *obj);
963 void i915_gem_shrinker_init(void);
964 void i915_gem_shrinker_exit(void);
965 int i915_gem_init_pipe_control(struct drm_device *dev);
966 void i915_gem_cleanup_pipe_control(struct drm_device *dev);
968 /* i915_gem_tiling.c */
969 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
970 void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj);
971 void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj);
972 bool i915_tiling_ok(struct drm_device *dev, int stride, int size,
974 bool i915_gem_object_fence_offset_ok(struct drm_gem_object *obj,
977 /* i915_gem_debug.c */
978 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
979 const char *where, uint32_t mark);
981 void i915_verify_inactive(struct drm_device *dev, char *file, int line);
983 #define i915_verify_inactive(dev, file, line)
985 void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
986 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
987 const char *where, uint32_t mark);
988 void i915_dump_lru(struct drm_device *dev, const char *where);
991 int i915_debugfs_init(struct drm_minor *minor);
992 void i915_debugfs_cleanup(struct drm_minor *minor);
995 extern int i915_save_state(struct drm_device *dev);
996 extern int i915_restore_state(struct drm_device *dev);
999 extern int i915_save_state(struct drm_device *dev);
1000 extern int i915_restore_state(struct drm_device *dev);
1003 /* i915_opregion.c */
1004 extern int intel_opregion_init(struct drm_device *dev, int resume);
1005 extern void intel_opregion_free(struct drm_device *dev, int suspend);
1006 extern void opregion_asle_intr(struct drm_device *dev);
1007 extern void ironlake_opregion_gse_intr(struct drm_device *dev);
1008 extern void opregion_enable_asle(struct drm_device *dev);
1010 static inline int intel_opregion_init(struct drm_device *dev, int resume) { return 0; }
1011 static inline void intel_opregion_free(struct drm_device *dev, int suspend) { return; }
1012 static inline void opregion_asle_intr(struct drm_device *dev) { return; }
1013 static inline void ironlake_opregion_gse_intr(struct drm_device *dev) { return; }
1014 static inline void opregion_enable_asle(struct drm_device *dev) { return; }
1017 /* intel_ringbuffer.c */
1018 extern void i915_gem_flush(struct drm_device *dev,
1019 uint32_t invalidate_domains,
1020 uint32_t flush_domains);
1021 extern int i915_dispatch_gem_execbuffer(struct drm_device *dev,
1022 struct drm_i915_gem_execbuffer2 *exec,
1023 struct drm_clip_rect *cliprects,
1024 uint64_t exec_offset);
1025 extern uint32_t i915_ring_add_request(struct drm_device *dev);
1028 extern void intel_modeset_init(struct drm_device *dev);
1029 extern void intel_modeset_cleanup(struct drm_device *dev);
1030 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1031 extern void i8xx_disable_fbc(struct drm_device *dev);
1032 extern void g4x_disable_fbc(struct drm_device *dev);
1033 extern void intel_disable_fbc(struct drm_device *dev);
1034 extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
1035 extern bool intel_fbc_enabled(struct drm_device *dev);
1037 extern void intel_detect_pch (struct drm_device *dev);
1038 extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
1041 * Lock test for when it's just for synchronization of ring access.
1043 * In that case, we don't need to do it when GEM is initialized as nobody else
1044 * has access to the ring.
1046 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
1047 if (((drm_i915_private_t *)dev->dev_private)->render_ring.ring_obj == NULL) \
1048 LOCK_TEST_WITH_RETURN(dev, file_priv); \
1051 #define I915_READ(reg) readl(dev_priv->regs + (reg))
1052 #define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg))
1053 #define I915_READ16(reg) readw(dev_priv->regs + (reg))
1054 #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
1055 #define I915_READ8(reg) readb(dev_priv->regs + (reg))
1056 #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
1057 #define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
1058 #define I915_READ64(reg) readq(dev_priv->regs + (reg))
1059 #define POSTING_READ(reg) (void)I915_READ(reg)
1061 #define I915_VERBOSE 0
1063 #define RING_LOCALS volatile unsigned int *ring_virt__;
1065 #define BEGIN_LP_RING(n) do { \
1066 int bytes__ = 4*(n); \
1067 if (I915_VERBOSE) DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \
1068 /* a wrap must occur between instructions so pad beforehand */ \
1069 if (unlikely (dev_priv->render_ring.tail + bytes__ > dev_priv->render_ring.Size)) \
1070 i915_wrap_ring(dev); \
1071 if (unlikely (dev_priv->render_ring.space < bytes__)) \
1072 i915_wait_ring(dev, bytes__, __func__); \
1073 ring_virt__ = (unsigned int *) \
1074 (dev_priv->render_ring.virtual_start + dev_priv->render_ring.tail); \
1075 dev_priv->render_ring.tail += bytes__; \
1076 dev_priv->render_ring.tail &= dev_priv->render_ring.Size - 1; \
1077 dev_priv->render_ring.space -= bytes__; \
1080 #define OUT_RING(n) do { \
1081 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
1082 *ring_virt__++ = (n); \
1085 #define ADVANCE_LP_RING() do { \
1087 DRM_DEBUG("ADVANCE_LP_RING %x\n", dev_priv->render_ring.tail); \
1088 I915_WRITE(PRB0_TAIL, dev_priv->render_ring.tail); \
1092 * Reads a dword out of the status page, which is written to from the command
1093 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
1094 * MI_STORE_DATA_IMM.
1096 * The following dwords have a reserved meaning:
1097 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
1098 * 0x04: ring 0 head pointer
1099 * 0x05: ring 1 head pointer (915-class)
1100 * 0x06: ring 2 head pointer (915-class)
1101 * 0x10-0x1b: Context status DWords (GM45)
1102 * 0x1f: Last written status offset. (GM45)
1104 * The area from dword 0x20 to 0x3ff is available for driver usage.
1106 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
1107 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
1108 #define I915_GEM_HWS_INDEX 0x20
1109 #define I915_BREADCRUMB_INDEX 0x21
1111 extern int i915_wrap_ring(struct drm_device * dev);
1112 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
1114 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1116 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1117 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1118 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1119 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1120 #define IS_GEN2(dev) (INTEL_INFO(dev)->is_i8xx)
1121 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1122 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1123 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1124 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1125 #define IS_I965G(dev) (INTEL_INFO(dev)->is_i965g)
1126 #define IS_I965GM(dev) (INTEL_INFO(dev)->is_i965gm)
1127 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1128 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1129 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1130 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1131 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1132 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1133 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1134 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1135 #define IS_IRONLAKE(dev) (INTEL_INFO(dev)->is_ironlake)
1136 #define IS_I9XX(dev) (INTEL_INFO(dev)->is_i9xx)
1137 #define IS_GEN6(dev) (INTEL_INFO(dev)->is_gen6)
1138 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1140 #define IS_GEN3(dev) (IS_I915G(dev) || \
1146 #define IS_GEN4(dev) ((dev)->pci_device == 0x2972 || \
1147 (dev)->pci_device == 0x2982 || \
1148 (dev)->pci_device == 0x2992 || \
1149 (dev)->pci_device == 0x29A2 || \
1150 (dev)->pci_device == 0x2A02 || \
1151 (dev)->pci_device == 0x2A12 || \
1152 (dev)->pci_device == 0x2E02 || \
1153 (dev)->pci_device == 0x2E12 || \
1154 (dev)->pci_device == 0x2E22 || \
1155 (dev)->pci_device == 0x2E32 || \
1156 (dev)->pci_device == 0x2A42 || \
1157 (dev)->pci_device == 0x2E42)
1159 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1161 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1162 * rows, which changed the alignment requirements and fence programming.
1164 #define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
1166 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (IS_I9XX(dev) && !IS_PINEVIEW(dev))
1167 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1168 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1169 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1170 #define SUPPORTS_TV(dev) (IS_I9XX(dev) && IS_MOBILE(dev) && \
1171 !IS_IRONLAKE(dev) && !IS_PINEVIEW(dev) && \
1173 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1174 /* dsparb controlled by hw only */
1175 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1177 #define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IRONLAKE(dev))
1178 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1179 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1180 #define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)
1182 #define HAS_PCH_SPLIT(dev) (IS_IRONLAKE(dev) || \
1184 #define HAS_PIPE_CONTROL(dev) (IS_IRONLAKE(dev) || IS_GEN6(dev))
1186 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1187 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1189 #define PRIMARY_RINGBUFFER_SIZE (128*1024)